1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
38 ;; 2 builtin_setjmp_receiver
41 ;; 5 prologue_stack_probe_loop
43 ;; 7 exception_receiver
48 ;; Processor type -- this attribute must exactly match the processor_type
49 ;; enumeration in alpha.h.
51 (define_attr "cpu" "ev4,ev5,ev6"
52 (const (symbol_ref "alpha_cpu")))
54 ;; Define an insn type attribute. This is used in function unit delay
55 ;; computations, among other purposes. For the most part, we use the names
56 ;; defined in the EV4 documentation, but add a few that we have to know about
60 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
61 (const_string "iadd"))
63 ;; Describe a user's asm statement.
64 (define_asm_attributes
65 [(set_attr "type" "multi")])
67 ;; Define the operand size an insn operates on. Used primarily by mul
68 ;; and div operations that have size dependant timings.
70 (define_attr "opsize" "si,di,udi" (const_string "di"))
72 ;; The TRAP_TYPE attribute marks instructions that may generate traps
73 ;; (which are imprecise and may need a trapb if software completion
76 (define_attr "trap" "no,yes" (const_string "no"))
78 ;; The length of an instruction sequence in bytes.
80 (define_attr "length" "" (const_int 4))
82 ;; On EV4 there are two classes of resources to consider: resources needed
83 ;; to issue, and resources needed to execute. IBUS[01] are in the first
84 ;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
85 ;; (There are a few other register-like resources, but ...)
87 ; First, describe all of the issue constraints with single cycle delays.
88 ; All insns need a bus, but all except loads require one or the other.
89 (define_function_unit "ev4_ibus0" 1 0
90 (and (eq_attr "cpu" "ev4")
91 (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
94 (define_function_unit "ev4_ibus1" 1 0
95 (and (eq_attr "cpu" "ev4")
96 (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
99 ; Memory delivers its result in three cycles. Actually return one and
100 ; take care of this in adjust_cost, since we want to handle user-defined
102 (define_function_unit "ev4_abox" 1 0
103 (and (eq_attr "cpu" "ev4")
104 (eq_attr "type" "ild,fld,ldsym,ist,fst"))
107 ; Branches have no delay cost, but do tie up the unit for two cycles.
108 (define_function_unit "ev4_bbox" 1 1
109 (and (eq_attr "cpu" "ev4")
110 (eq_attr "type" "ibr,fbr,jsr"))
113 ; Arithmetic insns are normally have their results available after
114 ; two cycles. There are a number of exceptions. They are encoded in
115 ; ADJUST_COST. Some of the other insns have similar exceptions.
116 (define_function_unit "ev4_ebox" 1 0
117 (and (eq_attr "cpu" "ev4")
118 (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
121 (define_function_unit "imul" 1 0
122 (and (eq_attr "cpu" "ev4")
123 (and (eq_attr "type" "imul")
124 (eq_attr "opsize" "si")))
127 (define_function_unit "imul" 1 0
128 (and (eq_attr "cpu" "ev4")
129 (and (eq_attr "type" "imul")
130 (eq_attr "opsize" "!si")))
133 (define_function_unit "ev4_fbox" 1 0
134 (and (eq_attr "cpu" "ev4")
135 (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
138 (define_function_unit "fdiv" 1 0
139 (and (eq_attr "cpu" "ev4")
140 (and (eq_attr "type" "fdiv")
141 (eq_attr "opsize" "si")))
144 (define_function_unit "fdiv" 1 0
145 (and (eq_attr "cpu" "ev4")
146 (and (eq_attr "type" "fdiv")
147 (eq_attr "opsize" "di")))
150 ;; EV5 scheduling. EV5 can issue 4 insns per clock.
152 ;; EV5 has two asymetric integer units. Model this with E0 & E1 along
153 ;; with the combined resource EBOX.
155 (define_function_unit "ev5_ebox" 2 0
156 (and (eq_attr "cpu" "ev5")
157 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
160 ; Memory takes at least 2 clocks. Return one from here and fix up with
161 ; user-defined latencies in adjust_cost.
162 (define_function_unit "ev5_ebox" 2 0
163 (and (eq_attr "cpu" "ev5")
164 (eq_attr "type" "ild,fld,ldsym"))
167 ; Loads can dual issue with one another, but loads and stores do not mix.
168 (define_function_unit "ev5_e0" 1 0
169 (and (eq_attr "cpu" "ev5")
170 (eq_attr "type" "ild,fld,ldsym"))
172 [(eq_attr "type" "ist,fst")])
174 ; Stores, shifts, multiplies can only issue to E0
175 (define_function_unit "ev5_e0" 1 0
176 (and (eq_attr "cpu" "ev5")
177 (eq_attr "type" "ist,fst,shift,imul"))
180 ; Motion video insns also issue only to E0, and take two ticks.
181 (define_function_unit "ev5_e0" 1 0
182 (and (eq_attr "cpu" "ev5")
183 (eq_attr "type" "mvi"))
186 ; Conditional moves always take 2 ticks.
187 (define_function_unit "ev5_ebox" 2 0
188 (and (eq_attr "cpu" "ev5")
189 (eq_attr "type" "icmov"))
192 ; Branches can only issue to E1
193 (define_function_unit "ev5_e1" 1 0
194 (and (eq_attr "cpu" "ev5")
195 (eq_attr "type" "ibr,jsr"))
198 ; Multiplies also use the integer multiplier.
199 ; ??? How to: "No instruction can be issued to pipe E0 exactly two
200 ; cycles before an integer multiplication completes."
201 (define_function_unit "imul" 1 0
202 (and (eq_attr "cpu" "ev5")
203 (and (eq_attr "type" "imul")
204 (eq_attr "opsize" "si")))
207 (define_function_unit "imul" 1 0
208 (and (eq_attr "cpu" "ev5")
209 (and (eq_attr "type" "imul")
210 (eq_attr "opsize" "di")))
213 (define_function_unit "imul" 1 0
214 (and (eq_attr "cpu" "ev5")
215 (and (eq_attr "type" "imul")
216 (eq_attr "opsize" "udi")))
219 ;; Similarly for the FPU we have two asymetric units. But fcpys can issue
220 ;; on either so we have to play the game again.
222 (define_function_unit "ev5_fbox" 2 0
223 (and (eq_attr "cpu" "ev5")
224 (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
227 (define_function_unit "ev5_fm" 1 0
228 (and (eq_attr "cpu" "ev5")
229 (eq_attr "type" "fmul"))
232 ; Add and cmov as you would expect; fbr never produces a result;
233 ; fdiv issues through fa to the divider,
234 (define_function_unit "ev5_fa" 1 0
235 (and (eq_attr "cpu" "ev5")
236 (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
239 ; ??? How to: "No instruction can be issued to pipe FA exactly five
240 ; cycles before a floating point divide completes."
241 (define_function_unit "fdiv" 1 0
242 (and (eq_attr "cpu" "ev5")
243 (and (eq_attr "type" "fdiv")
244 (eq_attr "opsize" "si")))
245 15 15) ; 15 to 31 data dependant
247 (define_function_unit "fdiv" 1 0
248 (and (eq_attr "cpu" "ev5")
249 (and (eq_attr "type" "fdiv")
250 (eq_attr "opsize" "di")))
251 22 22) ; 22 to 60 data dependant
253 ;; EV6 scheduling. EV6 can issue 4 insns per clock.
255 ;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
256 ;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
258 ;; Conditional moves decompose into two independant primitives, each
259 ;; taking one cycle. Since ev6 is out-of-order, we can't see anything
261 (define_function_unit "ev6_ebox" 4 0
262 (and (eq_attr "cpu" "ev6")
263 (eq_attr "type" "icmov"))
266 (define_function_unit "ev6_ebox" 4 0
267 (and (eq_attr "cpu" "ev6")
268 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
271 ;; Integer loads take at least 3 clocks, and only issue to lower units.
272 ;; Return one from here and fix up with user-defined latencies in adjust_cost.
273 (define_function_unit "ev6_l" 2 0
274 (and (eq_attr "cpu" "ev6")
275 (eq_attr "type" "ild,ldsym,ist,fst"))
278 ;; FP loads take at least 4 clocks. Return two from here...
279 (define_function_unit "ev6_l" 2 0
280 (and (eq_attr "cpu" "ev6")
281 (eq_attr "type" "fld"))
284 ;; Motion video insns also issue only to U0, and take three ticks.
285 (define_function_unit "ev6_u0" 1 0
286 (and (eq_attr "cpu" "ev6")
287 (eq_attr "type" "mvi"))
290 (define_function_unit "ev6_u" 2 0
291 (and (eq_attr "cpu" "ev6")
292 (eq_attr "type" "mvi"))
295 ;; Shifts issue to either upper pipe.
296 (define_function_unit "ev6_u" 2 0
297 (and (eq_attr "cpu" "ev6")
298 (eq_attr "type" "shift"))
301 ;; Multiplies issue only to U1, and all take 7 ticks.
302 ;; Rather than create a new function unit just for U1, reuse IMUL
303 (define_function_unit "imul" 1 0
304 (and (eq_attr "cpu" "ev6")
305 (eq_attr "type" "imul"))
308 (define_function_unit "ev6_u" 2 0
309 (and (eq_attr "cpu" "ev6")
310 (eq_attr "type" "imul"))
313 ;; Branches issue to either upper pipe
314 (define_function_unit "ev6_u" 2 0
315 (and (eq_attr "cpu" "ev6")
316 (eq_attr "type" "ibr"))
319 ;; Calls only issue to L0.
320 (define_function_unit "ev6_l0" 1 0
321 (and (eq_attr "cpu" "ev6")
322 (eq_attr "type" "jsr"))
325 (define_function_unit "ev6_l" 2 0
326 (and (eq_attr "cpu" "ev6")
327 (eq_attr "type" "jsr"))
330 ;; Ftoi/itof only issue to lower pipes
331 (define_function_unit "ev6_l" 2 0
332 (and (eq_attr "cpu" "ev6")
333 (eq_attr "type" "ftoi"))
336 (define_function_unit "ev6_l" 2 0
337 (and (eq_attr "cpu" "ev6")
338 (eq_attr "type" "itof"))
341 ;; For the FPU we are very similar to EV5, except there's no insn that
342 ;; can issue to fm & fa, so we get to leave that out.
344 (define_function_unit "ev6_fm" 1 0
345 (and (eq_attr "cpu" "ev6")
346 (eq_attr "type" "fmul"))
349 (define_function_unit "ev6_fa" 1 0
350 (and (eq_attr "cpu" "ev6")
351 (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
354 (define_function_unit "ev6_fa" 1 0
355 (and (eq_attr "cpu" "ev6")
356 (eq_attr "type" "fcmov"))
359 (define_function_unit "fdiv" 1 0
360 (and (eq_attr "cpu" "ev6")
361 (and (eq_attr "type" "fdiv")
362 (eq_attr "opsize" "si")))
365 (define_function_unit "fdiv" 1 0
366 (and (eq_attr "cpu" "ev6")
367 (and (eq_attr "type" "fdiv")
368 (eq_attr "opsize" "di")))
371 (define_function_unit "fsqrt" 1 0
372 (and (eq_attr "cpu" "ev6")
373 (and (eq_attr "type" "fsqrt")
374 (eq_attr "opsize" "si")))
377 (define_function_unit "fsqrt" 1 0
378 (and (eq_attr "cpu" "ev6")
379 (and (eq_attr "type" "fsqrt")
380 (eq_attr "opsize" "di")))
383 ; ??? The FPU communicates with memory and the integer register file
384 ; via two fp store units. We need a slot in the fst immediately, and
385 ; a slot in LOW after the operand data is ready. At which point the
386 ; data may be moved either to the store queue or the integer register
387 ; file and the insn retired.
390 ;; First define the arithmetic insns. Note that the 32-bit forms also
393 ;; Handle 32-64 bit extension from memory to a floating point register
394 ;; specially, since this ocurrs frequently in int->double conversions.
396 ;; Note that while we must retain the =f case in the insn for reload's
397 ;; benefit, it should be eliminated after reload, so we should never emit
398 ;; code for that case. But we don't reject the possibility.
400 (define_expand "extendsidi2"
401 [(set (match_operand:DI 0 "register_operand" "")
402 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
406 (define_insn "*extendsidi2_nofix"
407 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
409 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
415 lds %0,%1\;cvtlq %0,%0"
416 [(set_attr "type" "iadd,ild,fadd,fld")
417 (set_attr "length" "*,*,*,8")])
419 (define_insn "*extendsidi2_fix"
420 [(set (match_operand:DI 0 "register_operand" "=r,r,r,*f,?*f")
422 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
429 lds %0,%1\;cvtlq %0,%0"
430 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
431 (set_attr "length" "*,*,*,*,8")])
433 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
435 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
436 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
438 [(set (match_dup 2) (match_dup 1))
439 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
440 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
442 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
443 ;; reload when converting fp->int.
446 [(set (match_operand:SI 0 "hard_int_register_operand" "")
447 (match_operand:SI 1 "memory_operand" ""))
448 (set (match_operand:DI 2 "hard_int_register_operand" "")
449 (sign_extend:DI (match_dup 0)))]
450 "true_regnum (operands[0]) == true_regnum (operands[2])
451 || peep2_reg_dead_p (2, operands[0])"
453 (sign_extend:DI (match_dup 1)))]
457 [(set (match_operand:SI 0 "hard_int_register_operand" "")
458 (match_operand:SI 1 "hard_fp_register_operand" ""))
459 (set (match_operand:DI 2 "hard_int_register_operand" "")
460 (sign_extend:DI (match_dup 0)))]
462 && (true_regnum (operands[0]) == true_regnum (operands[2])
463 || peep2_reg_dead_p (2, operands[0]))"
465 (sign_extend:DI (match_dup 1)))]
469 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
470 (sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" "")))
471 (set (match_operand:DI 2 "hard_int_register_operand" "")
473 "TARGET_FIX && peep2_reg_dead_p (2, operands[0])"
475 (sign_extend:DI (match_dup 1)))]
478 ;; Do addsi3 the way expand_binop would do if we didn't have one. This
479 ;; generates better code. We have the anonymous addsi3 pattern below in
480 ;; case combine wants to make it.
481 (define_expand "addsi3"
482 [(set (match_operand:SI 0 "register_operand" "")
483 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
484 (match_operand:SI 2 "add_operand" "")))]
490 rtx op1 = gen_lowpart (DImode, operands[1]);
491 rtx op2 = gen_lowpart (DImode, operands[2]);
493 if (! cse_not_expected)
495 rtx tmp = gen_reg_rtx (DImode);
496 emit_insn (gen_adddi3 (tmp, op1, op2));
497 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
500 emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
505 (define_insn "*addsi_internal"
506 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
507 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
508 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
517 [(set (match_operand:SI 0 "register_operand" "")
518 (plus:SI (match_operand:SI 1 "register_operand" "")
519 (match_operand:SI 2 "const_int_operand" "")))]
520 "! add_operand (operands[2], SImode)"
521 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
522 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
525 HOST_WIDE_INT val = INTVAL (operands[2]);
526 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
527 HOST_WIDE_INT rest = val - low;
529 operands[3] = GEN_INT (rest);
530 operands[4] = GEN_INT (low);
533 (define_insn "*addsi_se"
534 [(set (match_operand:DI 0 "register_operand" "=r,r")
536 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
537 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
544 [(set (match_operand:DI 0 "register_operand" "")
546 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
547 (match_operand:SI 2 "const_int_operand" ""))))
548 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
549 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
550 && INTVAL (operands[2]) % 4 == 0"
551 [(set (match_dup 3) (match_dup 4))
552 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
557 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
563 operands[4] = GEN_INT (val);
564 operands[5] = GEN_INT (mult);
568 [(set (match_operand:DI 0 "register_operand" "")
570 (plus:SI (match_operator:SI 1 "comparison_operator"
571 [(match_operand 2 "" "")
572 (match_operand 3 "" "")])
573 (match_operand:SI 4 "add_operand" ""))))
574 (clobber (match_operand:DI 5 "register_operand" ""))]
576 [(set (match_dup 5) (match_dup 6))
577 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
580 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
581 operands[2], operands[3]);
582 operands[7] = gen_lowpart (SImode, operands[5]);
585 (define_insn "addvsi3"
586 [(set (match_operand:SI 0 "register_operand" "=r,r")
587 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
588 (match_operand:SI 2 "sext_add_operand" "rI,O")))
589 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
590 (sign_extend:DI (match_dup 2)))
591 (sign_extend:DI (plus:SI (match_dup 1)
599 (define_expand "adddi3"
600 [(set (match_operand:DI 0 "register_operand" "")
601 (plus:DI (match_operand:DI 1 "register_operand" "")
602 (match_operand:DI 2 "add_operand" "")))]
606 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
607 ;; With complications like
609 ;; The NT stack unwind code can't handle a subq to adjust the stack
610 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
611 ;; the exception handling code will loop if a subq is used and an
614 ;; The 19980616 change to emit prologues as RTL also confused some
615 ;; versions of GDB, which also interprets prologues. This has been
616 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
619 ;; and the fact that the three insns schedule exactly the same, it's
620 ;; just not worth the effort.
622 (define_insn "*adddi_internal"
623 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
624 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
625 (match_operand:DI 2 "add_operand" "r,K,L")))]
632 ;; ??? Allow large constants when basing off the frame pointer or some
633 ;; virtual register that may eliminate to the frame pointer. This is
634 ;; done because register elimination offsets will change the hi/lo split,
635 ;; and if we split before reload, we will require additional instructions.
637 (define_insn "*adddi_fp_hack"
638 [(set (match_operand:DI 0 "register_operand" "=r")
639 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
640 (match_operand:DI 2 "const_int_operand" "n")))]
641 "REG_OK_FP_BASE_P (operands[1])
642 && INTVAL (operands[2]) >= 0
643 /* This is the largest constant an lda+ldah pair can add, minus
644 an upper bound on the displacement between SP and AP during
645 register elimination. See INITIAL_ELIMINATION_OFFSET. */
646 && INTVAL (operands[2])
648 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
649 - ALPHA_ROUND(current_function_outgoing_args_size)
650 - (ALPHA_ROUND (get_frame_size ()
651 + max_reg_num () * UNITS_PER_WORD
652 + current_function_pretend_args_size)
653 - current_function_pretend_args_size))"
656 ;; Don't do this if we are adjusting SP since we don't want to do it
657 ;; in two steps. Don't split FP sources for the reason listed above.
659 [(set (match_operand:DI 0 "register_operand" "")
660 (plus:DI (match_operand:DI 1 "register_operand" "")
661 (match_operand:DI 2 "const_int_operand" "")))]
662 "! add_operand (operands[2], DImode)
663 && operands[0] != stack_pointer_rtx
664 && operands[1] != frame_pointer_rtx
665 && operands[1] != arg_pointer_rtx"
666 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
667 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
670 HOST_WIDE_INT val = INTVAL (operands[2]);
671 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
672 HOST_WIDE_INT rest = val - low;
674 operands[4] = GEN_INT (low);
675 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
676 operands[3] = GEN_INT (rest);
677 else if (! no_new_pseudos)
679 operands[3] = gen_reg_rtx (DImode);
680 emit_move_insn (operands[3], operands[2]);
681 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
688 (define_insn "*saddl"
689 [(set (match_operand:SI 0 "register_operand" "=r,r")
690 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
691 (match_operand:SI 2 "const48_operand" "I,I"))
692 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
698 (define_insn "*saddl_se"
699 [(set (match_operand:DI 0 "register_operand" "=r,r")
701 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
702 (match_operand:SI 2 "const48_operand" "I,I"))
703 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
710 [(set (match_operand:DI 0 "register_operand" "")
712 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
713 [(match_operand 2 "" "")
714 (match_operand 3 "" "")])
715 (match_operand:SI 4 "const48_operand" ""))
716 (match_operand:SI 5 "sext_add_operand" ""))))
717 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
719 [(set (match_dup 6) (match_dup 7))
721 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
725 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
726 operands[2], operands[3]);
727 operands[8] = gen_lowpart (SImode, operands[6]);
730 (define_insn "*saddq"
731 [(set (match_operand:DI 0 "register_operand" "=r,r")
732 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
733 (match_operand:DI 2 "const48_operand" "I,I"))
734 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
740 (define_insn "addvdi3"
741 [(set (match_operand:DI 0 "register_operand" "=r,r")
742 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
743 (match_operand:DI 2 "sext_add_operand" "rI,O")))
744 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
745 (sign_extend:TI (match_dup 2)))
746 (sign_extend:TI (plus:DI (match_dup 1)
754 (define_insn "negsi2"
755 [(set (match_operand:SI 0 "register_operand" "=r")
756 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
760 (define_insn "*negsi_se"
761 [(set (match_operand:DI 0 "register_operand" "=r")
762 (sign_extend:DI (neg:SI
763 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
767 (define_insn "negvsi2"
768 [(set (match_operand:SI 0 "register_operand" "=r")
769 (neg:SI (match_operand:SI 1 "register_operand" "r")))
770 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
771 (sign_extend:DI (neg:SI (match_dup 1))))
776 (define_insn "negdi2"
777 [(set (match_operand:DI 0 "register_operand" "=r")
778 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
782 (define_insn "negvdi2"
783 [(set (match_operand:DI 0 "register_operand" "=r")
784 (neg:DI (match_operand:DI 1 "register_operand" "r")))
785 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
786 (sign_extend:TI (neg:DI (match_dup 1))))
791 (define_expand "subsi3"
792 [(set (match_operand:SI 0 "register_operand" "")
793 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
794 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
800 rtx op1 = gen_lowpart (DImode, operands[1]);
801 rtx op2 = gen_lowpart (DImode, operands[2]);
803 if (! cse_not_expected)
805 rtx tmp = gen_reg_rtx (DImode);
806 emit_insn (gen_subdi3 (tmp, op1, op2));
807 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
810 emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
815 (define_insn "*subsi_internal"
816 [(set (match_operand:SI 0 "register_operand" "=r")
817 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
818 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
822 (define_insn "*subsi_se"
823 [(set (match_operand:DI 0 "register_operand" "=r")
824 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
825 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
829 (define_insn "subvsi3"
830 [(set (match_operand:SI 0 "register_operand" "=r")
831 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
832 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
833 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
834 (sign_extend:DI (match_dup 2)))
835 (sign_extend:DI (minus:SI (match_dup 1)
841 (define_insn "subdi3"
842 [(set (match_operand:DI 0 "register_operand" "=r")
843 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
844 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
848 (define_insn "*ssubl"
849 [(set (match_operand:SI 0 "register_operand" "=r")
850 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
851 (match_operand:SI 2 "const48_operand" "I"))
852 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
856 (define_insn "*ssubl_se"
857 [(set (match_operand:DI 0 "register_operand" "=r")
859 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
860 (match_operand:SI 2 "const48_operand" "I"))
861 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
865 (define_insn "*ssubq"
866 [(set (match_operand:DI 0 "register_operand" "=r")
867 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
868 (match_operand:DI 2 "const48_operand" "I"))
869 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
873 (define_insn "subvdi3"
874 [(set (match_operand:DI 0 "register_operand" "=r")
875 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
876 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
877 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
878 (sign_extend:TI (match_dup 2)))
879 (sign_extend:TI (minus:DI (match_dup 1)
885 (define_insn "mulsi3"
886 [(set (match_operand:SI 0 "register_operand" "=r")
887 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
888 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
891 [(set_attr "type" "imul")
892 (set_attr "opsize" "si")])
894 (define_insn "*mulsi_se"
895 [(set (match_operand:DI 0 "register_operand" "=r")
897 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
898 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
901 [(set_attr "type" "imul")
902 (set_attr "opsize" "si")])
904 (define_insn "mulvsi3"
905 [(set (match_operand:SI 0 "register_operand" "=r")
906 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
907 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
908 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
909 (sign_extend:DI (match_dup 2)))
910 (sign_extend:DI (mult:SI (match_dup 1)
915 [(set_attr "type" "imul")
916 (set_attr "opsize" "si")])
918 (define_insn "muldi3"
919 [(set (match_operand:DI 0 "register_operand" "=r")
920 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
921 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
924 [(set_attr "type" "imul")])
926 (define_insn "mulvdi3"
927 [(set (match_operand:DI 0 "register_operand" "=r")
928 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
929 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
930 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
931 (sign_extend:TI (match_dup 2)))
932 (sign_extend:TI (mult:DI (match_dup 1)
937 [(set_attr "type" "imul")])
939 (define_insn "umuldi3_highpart"
940 [(set (match_operand:DI 0 "register_operand" "=r")
943 (mult:TI (zero_extend:TI
944 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
946 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
950 [(set_attr "type" "imul")
951 (set_attr "opsize" "udi")])
953 (define_insn "*umuldi3_highpart_const"
954 [(set (match_operand:DI 0 "register_operand" "=r")
957 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
958 (match_operand:TI 2 "cint8_operand" "I"))
962 [(set_attr "type" "imul")
963 (set_attr "opsize" "udi")])
965 ;; The divide and remainder operations always take their inputs from
966 ;; r24 and r25, put their output in r27, and clobber r23 and r28.
968 ;; ??? Force sign-extension here because some versions of OSF/1 don't
969 ;; do the right thing if the inputs are not properly sign-extended.
970 ;; But Linux, for instance, does not have this problem. Is it worth
971 ;; the complication here to eliminate the sign extension?
972 ;; Interix/NT has the same sign-extension problem.
974 (define_expand "divsi3"
976 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
978 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
979 (parallel [(set (reg:DI 27)
980 (sign_extend:DI (div:SI (reg:DI 24) (reg:DI 25))))
981 (clobber (reg:DI 23))
982 (clobber (reg:DI 28))])
983 (set (match_operand:SI 0 "nonimmediate_operand" "")
984 (subreg:SI (reg:DI 27) 0))]
988 (define_expand "udivsi3"
990 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
992 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
993 (parallel [(set (reg:DI 27)
994 (sign_extend:DI (udiv:SI (reg:DI 24) (reg:DI 25))))
995 (clobber (reg:DI 23))
996 (clobber (reg:DI 28))])
997 (set (match_operand:SI 0 "nonimmediate_operand" "")
998 (subreg:SI (reg:DI 27) 0))]
1002 (define_expand "modsi3"
1004 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1006 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1007 (parallel [(set (reg:DI 27)
1008 (sign_extend:DI (mod:SI (reg:DI 24) (reg:DI 25))))
1009 (clobber (reg:DI 23))
1010 (clobber (reg:DI 28))])
1011 (set (match_operand:SI 0 "nonimmediate_operand" "")
1012 (subreg:SI (reg:DI 27) 0))]
1016 (define_expand "umodsi3"
1018 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1020 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1021 (parallel [(set (reg:DI 27)
1022 (sign_extend:DI (umod:SI (reg:DI 24) (reg:DI 25))))
1023 (clobber (reg:DI 23))
1024 (clobber (reg:DI 28))])
1025 (set (match_operand:SI 0 "nonimmediate_operand" "")
1026 (subreg:SI (reg:DI 27) 0))]
1030 (define_expand "divdi3"
1031 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
1032 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
1033 (parallel [(set (reg:DI 27)
1036 (clobber (reg:DI 23))
1037 (clobber (reg:DI 28))])
1038 (set (match_operand:DI 0 "nonimmediate_operand" "")
1043 (define_expand "udivdi3"
1044 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
1045 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
1046 (parallel [(set (reg:DI 27)
1047 (udiv:DI (reg:DI 24)
1049 (clobber (reg:DI 23))
1050 (clobber (reg:DI 28))])
1051 (set (match_operand:DI 0 "nonimmediate_operand" "")
1056 (define_expand "moddi3"
1057 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
1058 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
1059 (parallel [(set (reg:DI 27)
1062 (clobber (reg:DI 23))
1063 (clobber (reg:DI 28))])
1064 (set (match_operand:DI 0 "nonimmediate_operand" "")
1069 (define_expand "umoddi3"
1070 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
1071 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
1072 (parallel [(set (reg:DI 27)
1073 (umod:DI (reg:DI 24)
1075 (clobber (reg:DI 23))
1076 (clobber (reg:DI 28))])
1077 (set (match_operand:DI 0 "nonimmediate_operand" "")
1082 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
1083 ;; expanded by the assembler.
1084 (define_insn "*divmodsi_internal"
1086 (sign_extend:DI (match_operator:SI 0 "divmod_operator"
1087 [(reg:DI 24) (reg:DI 25)])))
1088 (clobber (reg:DI 23))
1089 (clobber (reg:DI 28))]
1092 [(set_attr "type" "jsr")
1093 (set_attr "length" "8")])
1095 (define_insn "*divmoddi_internal"
1097 (match_operator:DI 0 "divmod_operator"
1098 [(reg:DI 24) (reg:DI 25)]))
1099 (clobber (reg:DI 23))
1100 (clobber (reg:DI 28))]
1103 [(set_attr "type" "jsr")
1104 (set_attr "length" "8")])
1106 ;; Next are the basic logical operations. These only exist in DImode.
1108 (define_insn "anddi3"
1109 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1110 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1111 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1117 [(set_attr "type" "ilog,ilog,shift")])
1119 ;; There are times when we can split an AND into two AND insns. This occurs
1120 ;; when we can first clear any bytes and then clear anything else. For
1121 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1122 ;; Only do this when running on 64-bit host since the computations are
1123 ;; too messy otherwise.
1126 [(set (match_operand:DI 0 "register_operand" "")
1127 (and:DI (match_operand:DI 1 "register_operand" "")
1128 (match_operand:DI 2 "const_int_operand" "")))]
1129 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1130 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1131 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1134 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1135 unsigned HOST_WIDE_INT mask2 = mask1;
1138 /* For each byte that isn't all zeros, make it all ones. */
1139 for (i = 0; i < 64; i += 8)
1140 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1141 mask1 |= (HOST_WIDE_INT) 0xff << i;
1143 /* Now turn on any bits we've just turned off. */
1146 operands[3] = GEN_INT (mask1);
1147 operands[4] = GEN_INT (mask2);
1150 (define_expand "zero_extendqihi2"
1151 [(set (match_operand:HI 0 "register_operand" "")
1152 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1157 operands[1] = force_reg (QImode, operands[1]);
1160 (define_insn "*zero_extendqihi2_bwx"
1161 [(set (match_operand:HI 0 "register_operand" "=r,r")
1162 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1167 [(set_attr "type" "ilog,ild")])
1169 (define_insn "*zero_extendqihi2_nobwx"
1170 [(set (match_operand:HI 0 "register_operand" "=r")
1171 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1174 [(set_attr "type" "ilog")])
1176 (define_expand "zero_extendqisi2"
1177 [(set (match_operand:SI 0 "register_operand" "")
1178 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1183 operands[1] = force_reg (QImode, operands[1]);
1186 (define_insn "*zero_extendqisi2_bwx"
1187 [(set (match_operand:SI 0 "register_operand" "=r,r")
1188 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1193 [(set_attr "type" "ilog,ild")])
1195 (define_insn "*zero_extendqisi2_nobwx"
1196 [(set (match_operand:SI 0 "register_operand" "=r")
1197 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1200 [(set_attr "type" "ilog")])
1202 (define_expand "zero_extendqidi2"
1203 [(set (match_operand:DI 0 "register_operand" "")
1204 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1209 operands[1] = force_reg (QImode, operands[1]);
1212 (define_insn "*zero_extendqidi2_bwx"
1213 [(set (match_operand:DI 0 "register_operand" "=r,r")
1214 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1219 [(set_attr "type" "ilog,ild")])
1221 (define_insn "*zero_extendqidi2_nobwx"
1222 [(set (match_operand:DI 0 "register_operand" "=r")
1223 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1226 [(set_attr "type" "ilog")])
1228 (define_expand "zero_extendhisi2"
1229 [(set (match_operand:SI 0 "register_operand" "")
1230 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1235 operands[1] = force_reg (HImode, operands[1]);
1238 (define_insn "*zero_extendhisi2_bwx"
1239 [(set (match_operand:SI 0 "register_operand" "=r,r")
1240 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1245 [(set_attr "type" "shift,ild")])
1247 (define_insn "*zero_extendhisi2_nobwx"
1248 [(set (match_operand:SI 0 "register_operand" "=r")
1249 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1252 [(set_attr "type" "shift")])
1254 (define_expand "zero_extendhidi2"
1255 [(set (match_operand:DI 0 "register_operand" "")
1256 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1261 operands[1] = force_reg (HImode, operands[1]);
1264 (define_insn "*zero_extendhidi2_bwx"
1265 [(set (match_operand:DI 0 "register_operand" "=r,r")
1266 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1271 [(set_attr "type" "shift,ild")])
1273 (define_insn "*zero_extendhidi2_nobwx"
1274 [(set (match_operand:DI 0 "register_operand" "=r")
1275 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1278 [(set_attr "type" "shift")])
1280 (define_insn "zero_extendsidi2"
1281 [(set (match_operand:DI 0 "register_operand" "=r")
1282 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1285 [(set_attr "type" "shift")])
1287 (define_insn "andnotdi3"
1288 [(set (match_operand:DI 0 "register_operand" "=r")
1289 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1290 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1293 [(set_attr "type" "ilog")])
1295 (define_insn "iordi3"
1296 [(set (match_operand:DI 0 "register_operand" "=r,r")
1297 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1298 (match_operand:DI 2 "or_operand" "rI,N")))]
1303 [(set_attr "type" "ilog")])
1305 (define_insn "one_cmpldi2"
1306 [(set (match_operand:DI 0 "register_operand" "=r")
1307 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1310 [(set_attr "type" "ilog")])
1312 (define_insn "*iornot"
1313 [(set (match_operand:DI 0 "register_operand" "=r")
1314 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1315 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1318 [(set_attr "type" "ilog")])
1320 (define_insn "xordi3"
1321 [(set (match_operand:DI 0 "register_operand" "=r,r")
1322 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1323 (match_operand:DI 2 "or_operand" "rI,N")))]
1328 [(set_attr "type" "ilog")])
1330 (define_insn "*xornot"
1331 [(set (match_operand:DI 0 "register_operand" "=r")
1332 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1333 (match_operand:DI 2 "register_operand" "rI"))))]
1336 [(set_attr "type" "ilog")])
1338 ;; Handle the FFS insn iff we support CIX.
1340 (define_expand "ffsdi2"
1342 (unspec:DI [(match_operand:DI 1 "register_operand" "")] 1))
1344 (plus:DI (match_dup 2) (const_int 1)))
1345 (set (match_operand:DI 0 "register_operand" "")
1346 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1347 (const_int 0) (match_dup 3)))]
1351 operands[2] = gen_reg_rtx (DImode);
1352 operands[3] = gen_reg_rtx (DImode);
1355 (define_insn "*cttz"
1356 [(set (match_operand:DI 0 "register_operand" "=r")
1357 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 1))]
1360 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1361 ; reuse the existing type name.
1362 [(set_attr "type" "mvi")])
1364 ;; Next come the shifts and the various extract and insert operations.
1366 (define_insn "ashldi3"
1367 [(set (match_operand:DI 0 "register_operand" "=r,r")
1368 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1369 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1373 switch (which_alternative)
1376 if (operands[2] == const1_rtx)
1377 return \"addq %r1,%r1,%0\";
1379 return \"s%P2addq %r1,0,%0\";
1381 return \"sll %r1,%2,%0\";
1386 [(set_attr "type" "iadd,shift")])
1388 ;; ??? The following pattern is made by combine, but earlier phases
1389 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
1390 ;; with this in a better way at some point.
1392 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1394 ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1395 ;; (match_operand:DI 2 "const_int_operand" "P"))
1397 ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1400 ;; if (operands[2] == const1_rtx)
1401 ;; return \"addl %r1,%r1,%0\";
1403 ;; return \"s%P2addl %r1,0,%0\";
1405 ;; [(set_attr "type" "iadd")])
1407 (define_insn "lshrdi3"
1408 [(set (match_operand:DI 0 "register_operand" "=r")
1409 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1410 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1413 [(set_attr "type" "shift")])
1415 (define_insn "ashrdi3"
1416 [(set (match_operand:DI 0 "register_operand" "=r")
1417 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1418 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1421 [(set_attr "type" "shift")])
1423 (define_expand "extendqihi2"
1425 (ashift:DI (match_operand:QI 1 "some_operand" "")
1427 (set (match_operand:HI 0 "register_operand" "")
1428 (ashiftrt:DI (match_dup 2)
1435 emit_insn (gen_extendqihi2x (operands[0],
1436 force_reg (QImode, operands[1])));
1440 /* If we have an unaligned MEM, extend to DImode (which we do
1441 specially) and then copy to the result. */
1442 if (unaligned_memory_operand (operands[1], HImode))
1444 rtx temp = gen_reg_rtx (DImode);
1446 emit_insn (gen_extendqidi2 (temp, operands[1]));
1447 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1451 operands[0] = gen_lowpart (DImode, operands[0]);
1452 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1453 operands[2] = gen_reg_rtx (DImode);
1456 (define_insn "extendqidi2x"
1457 [(set (match_operand:DI 0 "register_operand" "=r")
1458 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1461 [(set_attr "type" "shift")])
1463 (define_insn "extendhidi2x"
1464 [(set (match_operand:DI 0 "register_operand" "=r")
1465 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1468 [(set_attr "type" "shift")])
1470 (define_insn "extendqisi2x"
1471 [(set (match_operand:SI 0 "register_operand" "=r")
1472 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1475 [(set_attr "type" "shift")])
1477 (define_insn "extendhisi2x"
1478 [(set (match_operand:SI 0 "register_operand" "=r")
1479 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1482 [(set_attr "type" "shift")])
1484 (define_insn "extendqihi2x"
1485 [(set (match_operand:HI 0 "register_operand" "=r")
1486 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1489 [(set_attr "type" "shift")])
1491 (define_expand "extendqisi2"
1493 (ashift:DI (match_operand:QI 1 "some_operand" "")
1495 (set (match_operand:SI 0 "register_operand" "")
1496 (ashiftrt:DI (match_dup 2)
1503 emit_insn (gen_extendqisi2x (operands[0],
1504 force_reg (QImode, operands[1])));
1508 /* If we have an unaligned MEM, extend to a DImode form of
1509 the result (which we do specially). */
1510 if (unaligned_memory_operand (operands[1], QImode))
1512 rtx temp = gen_reg_rtx (DImode);
1514 emit_insn (gen_extendqidi2 (temp, operands[1]));
1515 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1519 operands[0] = gen_lowpart (DImode, operands[0]);
1520 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1521 operands[2] = gen_reg_rtx (DImode);
1524 (define_expand "extendqidi2"
1526 (ashift:DI (match_operand:QI 1 "some_operand" "")
1528 (set (match_operand:DI 0 "register_operand" "")
1529 (ashiftrt:DI (match_dup 2)
1536 emit_insn (gen_extendqidi2x (operands[0],
1537 force_reg (QImode, operands[1])));
1541 if (unaligned_memory_operand (operands[1], QImode))
1544 = gen_unaligned_extendqidi (operands[0],
1545 get_unaligned_address (operands[1], 1));
1547 alpha_set_memflags (seq, operands[1]);
1552 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1553 operands[2] = gen_reg_rtx (DImode);
1556 (define_expand "extendhisi2"
1558 (ashift:DI (match_operand:HI 1 "some_operand" "")
1560 (set (match_operand:SI 0 "register_operand" "")
1561 (ashiftrt:DI (match_dup 2)
1568 emit_insn (gen_extendhisi2x (operands[0],
1569 force_reg (HImode, operands[1])));
1573 /* If we have an unaligned MEM, extend to a DImode form of
1574 the result (which we do specially). */
1575 if (unaligned_memory_operand (operands[1], HImode))
1577 rtx temp = gen_reg_rtx (DImode);
1579 emit_insn (gen_extendhidi2 (temp, operands[1]));
1580 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1584 operands[0] = gen_lowpart (DImode, operands[0]);
1585 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1586 operands[2] = gen_reg_rtx (DImode);
1589 (define_expand "extendhidi2"
1591 (ashift:DI (match_operand:HI 1 "some_operand" "")
1593 (set (match_operand:DI 0 "register_operand" "")
1594 (ashiftrt:DI (match_dup 2)
1601 emit_insn (gen_extendhidi2x (operands[0],
1602 force_reg (HImode, operands[1])));
1606 if (unaligned_memory_operand (operands[1], HImode))
1609 = gen_unaligned_extendhidi (operands[0],
1610 get_unaligned_address (operands[1], 2));
1612 alpha_set_memflags (seq, operands[1]);
1617 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1618 operands[2] = gen_reg_rtx (DImode);
1621 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1622 ;; as a pattern saves one instruction. The code is similar to that for
1623 ;; the unaligned loads (see below).
1625 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1626 (define_expand "unaligned_extendqidi"
1627 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1629 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1632 (ashift:DI (match_dup 3)
1633 (minus:DI (const_int 64)
1635 (and:DI (match_dup 2) (const_int 7))
1637 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1638 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1641 { operands[2] = gen_reg_rtx (DImode);
1642 operands[3] = gen_reg_rtx (DImode);
1643 operands[4] = gen_reg_rtx (DImode);
1646 (define_expand "unaligned_extendhidi"
1647 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1649 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1652 (ashift:DI (match_dup 3)
1653 (minus:DI (const_int 64)
1655 (and:DI (match_dup 2) (const_int 7))
1657 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1658 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1661 { operands[2] = gen_reg_rtx (DImode);
1662 operands[3] = gen_reg_rtx (DImode);
1663 operands[4] = gen_reg_rtx (DImode);
1666 (define_insn "*extxl_const"
1667 [(set (match_operand:DI 0 "register_operand" "=r")
1668 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1669 (match_operand:DI 2 "mode_width_operand" "n")
1670 (match_operand:DI 3 "mul8_operand" "I")))]
1672 "ext%M2l %r1,%s3,%0"
1673 [(set_attr "type" "shift")])
1675 (define_insn "extxl"
1676 [(set (match_operand:DI 0 "register_operand" "=r")
1677 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1678 (match_operand:DI 2 "mode_width_operand" "n")
1679 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1683 [(set_attr "type" "shift")])
1685 ;; Combine has some strange notion of preserving existing undefined behaviour
1686 ;; in shifts larger than a word size. So capture these patterns that it
1687 ;; should have turned into zero_extracts.
1689 (define_insn "*extxl_1"
1690 [(set (match_operand:DI 0 "register_operand" "=r")
1691 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1692 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1694 (match_operand:DI 3 "mode_mask_operand" "n")))]
1697 [(set_attr "type" "shift")])
1699 (define_insn "*extql_2"
1700 [(set (match_operand:DI 0 "register_operand" "=r")
1701 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1702 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1706 [(set_attr "type" "shift")])
1708 (define_insn "extqh"
1709 [(set (match_operand:DI 0 "register_operand" "=r")
1711 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1712 (minus:DI (const_int 64)
1715 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1720 [(set_attr "type" "shift")])
1722 (define_insn "extlh"
1723 [(set (match_operand:DI 0 "register_operand" "=r")
1725 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1726 (const_int 2147483647))
1727 (minus:DI (const_int 64)
1730 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1735 [(set_attr "type" "shift")])
1737 (define_insn "extwh"
1738 [(set (match_operand:DI 0 "register_operand" "=r")
1740 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1742 (minus:DI (const_int 64)
1745 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1750 [(set_attr "type" "shift")])
1752 ;; This converts an extXl into an extXh with an appropriate adjustment
1753 ;; to the address calculation.
1756 ;; [(set (match_operand:DI 0 "register_operand" "")
1757 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1758 ;; (match_operand:DI 2 "mode_width_operand" "")
1759 ;; (ashift:DI (match_operand:DI 3 "" "")
1761 ;; (match_operand:DI 4 "const_int_operand" "")))
1762 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1763 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1764 ;; [(set (match_dup 5) (match_dup 6))
1765 ;; (set (match_dup 0)
1766 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1767 ;; (ashift:DI (plus:DI (match_dup 5)
1773 ;; operands[6] = plus_constant (operands[3],
1774 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1775 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1778 (define_insn "*insbl_const"
1779 [(set (match_operand:DI 0 "register_operand" "=r")
1780 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1781 (match_operand:DI 2 "mul8_operand" "I")))]
1784 [(set_attr "type" "shift")])
1786 (define_insn "*inswl_const"
1787 [(set (match_operand:DI 0 "register_operand" "=r")
1788 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1789 (match_operand:DI 2 "mul8_operand" "I")))]
1792 [(set_attr "type" "shift")])
1794 (define_insn "*insll_const"
1795 [(set (match_operand:DI 0 "register_operand" "=r")
1796 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1797 (match_operand:DI 2 "mul8_operand" "I")))]
1800 [(set_attr "type" "shift")])
1802 (define_insn "insbl"
1803 [(set (match_operand:DI 0 "register_operand" "=r")
1804 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1805 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1809 [(set_attr "type" "shift")])
1811 (define_insn "inswl"
1812 [(set (match_operand:DI 0 "register_operand" "=r")
1813 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1814 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1818 [(set_attr "type" "shift")])
1820 (define_insn "insll"
1821 [(set (match_operand:DI 0 "register_operand" "=r")
1822 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1823 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1827 [(set_attr "type" "shift")])
1829 (define_insn "insql"
1830 [(set (match_operand:DI 0 "register_operand" "=r")
1831 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1832 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1836 [(set_attr "type" "shift")])
1838 ;; Combine has this sometimes habit of moving the and outside of the
1839 ;; shift, making life more interesting.
1841 (define_insn "*insxl"
1842 [(set (match_operand:DI 0 "register_operand" "=r")
1843 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
1844 (match_operand:DI 2 "mul8_operand" "I"))
1845 (match_operand:DI 3 "immediate_operand" "i")))]
1846 "HOST_BITS_PER_WIDE_INT == 64
1847 && GET_CODE (operands[3]) == CONST_INT
1848 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1849 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1850 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1851 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1852 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1853 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
1856 #if HOST_BITS_PER_WIDE_INT == 64
1857 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1858 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1859 return \"insbl %1,%s2,%0\";
1860 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1861 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1862 return \"inswl %1,%s2,%0\";
1863 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1864 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1865 return \"insll %1,%s2,%0\";
1869 [(set_attr "type" "shift")])
1871 ;; We do not include the insXh insns because they are complex to express
1872 ;; and it does not appear that we would ever want to generate them.
1874 ;; Since we need them for block moves, though, cop out and use unspec.
1876 (define_insn "insxh"
1877 [(set (match_operand:DI 0 "register_operand" "=r")
1878 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1879 (match_operand:DI 2 "mode_width_operand" "n")
1880 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 2))]
1883 [(set_attr "type" "shift")])
1885 (define_insn "mskxl"
1886 [(set (match_operand:DI 0 "register_operand" "=r")
1887 (and:DI (not:DI (ashift:DI
1888 (match_operand:DI 2 "mode_mask_operand" "n")
1890 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1892 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
1895 [(set_attr "type" "shift")])
1897 ;; We do not include the mskXh insns because it does not appear we would
1898 ;; ever generate one.
1900 ;; Again, we do for block moves and we use unspec again.
1902 (define_insn "mskxh"
1903 [(set (match_operand:DI 0 "register_operand" "=r")
1904 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1905 (match_operand:DI 2 "mode_width_operand" "n")
1906 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 3))]
1909 [(set_attr "type" "shift")])
1911 ;; Prefer AND + NE over LSHIFTRT + AND.
1913 (define_insn_and_split "*ze_and_ne"
1914 [(set (match_operand:DI 0 "register_operand" "=r")
1915 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1917 (match_operand 2 "const_int_operand" "I")))]
1918 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
1920 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
1922 (and:DI (match_dup 1) (match_dup 3)))
1924 (ne:DI (match_dup 0) (const_int 0)))]
1925 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
1927 ;; Floating-point operations. All the double-precision insns can extend
1928 ;; from single, so indicate that. The exception are the ones that simply
1929 ;; play with the sign bits; it's not clear what to do there.
1931 (define_insn "abssf2"
1932 [(set (match_operand:SF 0 "register_operand" "=f")
1933 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1936 [(set_attr "type" "fcpys")])
1938 (define_insn "*nabssf2"
1939 [(set (match_operand:SF 0 "register_operand" "=f")
1940 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
1943 [(set_attr "type" "fadd")])
1945 (define_insn "absdf2"
1946 [(set (match_operand:DF 0 "register_operand" "=f")
1947 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1950 [(set_attr "type" "fcpys")])
1952 (define_insn "*nabsdf2"
1953 [(set (match_operand:DF 0 "register_operand" "=f")
1954 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG"))))]
1957 [(set_attr "type" "fadd")])
1959 (define_expand "abstf2"
1960 [(parallel [(set (match_operand:TF 0 "register_operand" "")
1961 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
1962 (use (match_dup 2))])]
1963 "TARGET_HAS_XFLOATING_LIBS"
1966 #if HOST_BITS_PER_WIDE_INT >= 64
1967 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
1969 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
1973 (define_insn_and_split "*abstf_internal"
1974 [(set (match_operand:TF 0 "register_operand" "=r")
1975 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
1976 (use (match_operand:DI 2 "register_operand" "r"))]
1977 "TARGET_HAS_XFLOATING_LIBS"
1979 "&& reload_completed"
1981 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
1983 (define_insn "negsf2"
1984 [(set (match_operand:SF 0 "register_operand" "=f")
1985 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1988 [(set_attr "type" "fadd")])
1990 (define_insn "negdf2"
1991 [(set (match_operand:DF 0 "register_operand" "=f")
1992 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1995 [(set_attr "type" "fadd")])
1997 (define_expand "negtf2"
1998 [(parallel [(set (match_operand:TF 0 "register_operand" "")
1999 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
2000 (use (match_dup 2))])]
2001 "TARGET_HAS_XFLOATING_LIBS"
2004 #if HOST_BITS_PER_WIDE_INT >= 64
2005 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
2007 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2011 (define_insn_and_split "*negtf_internal"
2012 [(set (match_operand:TF 0 "register_operand" "=r")
2013 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
2014 (use (match_operand:DI 2 "register_operand" "r"))]
2015 "TARGET_HAS_XFLOATING_LIBS"
2017 "&& reload_completed"
2019 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2021 (define_insn "*addsf_ieee"
2022 [(set (match_operand:SF 0 "register_operand" "=&f")
2023 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2024 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2025 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2026 "add%,%)%& %R1,%R2,%0"
2027 [(set_attr "type" "fadd")
2028 (set_attr "trap" "yes")])
2030 (define_insn "addsf3"
2031 [(set (match_operand:SF 0 "register_operand" "=f")
2032 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2033 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2035 "add%,%)%& %R1,%R2,%0"
2036 [(set_attr "type" "fadd")
2037 (set_attr "trap" "yes")])
2039 (define_insn "*adddf_ieee"
2040 [(set (match_operand:DF 0 "register_operand" "=&f")
2041 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2042 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2043 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2044 "add%-%)%& %R1,%R2,%0"
2045 [(set_attr "type" "fadd")
2046 (set_attr "trap" "yes")])
2048 (define_insn "adddf3"
2049 [(set (match_operand:DF 0 "register_operand" "=f")
2050 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2051 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2053 "add%-%)%& %R1,%R2,%0"
2054 [(set_attr "type" "fadd")
2055 (set_attr "trap" "yes")])
2057 (define_insn "*adddf_ext1"
2058 [(set (match_operand:DF 0 "register_operand" "=f")
2059 (plus:DF (float_extend:DF
2060 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2061 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2062 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2063 "add%-%)%& %R1,%R2,%0"
2064 [(set_attr "type" "fadd")
2065 (set_attr "trap" "yes")])
2067 (define_insn "*adddf_ext2"
2068 [(set (match_operand:DF 0 "register_operand" "=f")
2069 (plus:DF (float_extend:DF
2070 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2072 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2073 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2074 "add%-%)%& %R1,%R2,%0"
2075 [(set_attr "type" "fadd")
2076 (set_attr "trap" "yes")])
2078 (define_expand "addtf3"
2079 [(use (match_operand 0 "register_operand" ""))
2080 (use (match_operand 1 "general_operand" ""))
2081 (use (match_operand 2 "general_operand" ""))]
2082 "TARGET_HAS_XFLOATING_LIBS"
2083 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2085 ;; Define conversion operators between DFmode and SImode, using the cvtql
2086 ;; instruction. To allow combine et al to do useful things, we keep the
2087 ;; operation as a unit until after reload, at which point we split the
2090 ;; Note that we (attempt to) only consider this optimization when the
2091 ;; ultimate destination is memory. If we will be doing further integer
2092 ;; processing, it is cheaper to do the truncation in the int regs.
2094 (define_insn "*cvtql"
2095 [(set (match_operand:SI 0 "register_operand" "=f")
2096 (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")] 5))]
2099 [(set_attr "type" "fadd")
2100 (set_attr "trap" "yes")])
2102 (define_insn_and_split "*fix_truncdfsi_ieee"
2103 [(set (match_operand:SI 0 "memory_operand" "=m")
2104 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2105 (clobber (match_scratch:DI 2 "=&f"))
2106 (clobber (match_scratch:SI 3 "=&f"))]
2107 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2109 "&& reload_completed"
2110 [(set (match_dup 2) (fix:DI (match_dup 1)))
2111 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
2112 (set (match_dup 0) (match_dup 3))]
2114 [(set_attr "type" "fadd")
2115 (set_attr "trap" "yes")])
2117 (define_insn_and_split "*fix_truncdfsi_internal"
2118 [(set (match_operand:SI 0 "memory_operand" "=m")
2119 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2120 (clobber (match_scratch:DI 2 "=f"))]
2121 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2123 "&& reload_completed"
2124 [(set (match_dup 2) (fix:DI (match_dup 1)))
2125 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
2126 (set (match_dup 0) (match_dup 3))]
2127 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2128 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2129 [(set_attr "type" "fadd")
2130 (set_attr "trap" "yes")])
2132 (define_insn "*fix_truncdfdi_ieee"
2133 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2134 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2135 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2137 [(set_attr "type" "fadd")
2138 (set_attr "trap" "yes")])
2140 (define_insn "fix_truncdfdi2"
2141 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2142 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2145 [(set_attr "type" "fadd")
2146 (set_attr "trap" "yes")])
2148 ;; Likewise between SFmode and SImode.
2150 (define_insn_and_split "*fix_truncsfsi_ieee"
2151 [(set (match_operand:SI 0 "memory_operand" "=m")
2152 (subreg:SI (fix:DI (float_extend:DF
2153 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2154 (clobber (match_scratch:DI 2 "=&f"))
2155 (clobber (match_scratch:SI 3 "=&f"))]
2156 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2158 "&& reload_completed"
2159 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2160 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
2161 (set (match_dup 0) (match_dup 3))]
2163 [(set_attr "type" "fadd")
2164 (set_attr "trap" "yes")])
2166 (define_insn_and_split "*fix_truncsfsi_internal"
2167 [(set (match_operand:SI 0 "memory_operand" "=m")
2168 (subreg:SI (fix:DI (float_extend:DF
2169 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2170 (clobber (match_scratch:DI 2 "=f"))]
2171 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2173 "&& reload_completed"
2174 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2175 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
2176 (set (match_dup 0) (match_dup 3))]
2177 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2178 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2179 [(set_attr "type" "fadd")
2180 (set_attr "trap" "yes")])
2182 (define_insn "*fix_truncsfdi_ieee"
2183 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2184 (fix:DI (float_extend:DF
2185 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2186 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2188 [(set_attr "type" "fadd")
2189 (set_attr "trap" "yes")])
2191 (define_insn "fix_truncsfdi2"
2192 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2193 (fix:DI (float_extend:DF
2194 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2197 [(set_attr "type" "fadd")
2198 (set_attr "trap" "yes")])
2200 (define_expand "fix_trunctfdi2"
2201 [(use (match_operand:DI 0 "register_operand" ""))
2202 (use (match_operand:TF 1 "general_operand" ""))]
2203 "TARGET_HAS_XFLOATING_LIBS"
2204 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2206 (define_insn "*floatdisf_ieee"
2207 [(set (match_operand:SF 0 "register_operand" "=&f")
2208 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2209 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2211 [(set_attr "type" "fadd")
2212 (set_attr "trap" "yes")])
2214 (define_insn "floatdisf2"
2215 [(set (match_operand:SF 0 "register_operand" "=f")
2216 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2219 [(set_attr "type" "fadd")
2220 (set_attr "trap" "yes")])
2222 (define_insn "*floatdidf_ieee"
2223 [(set (match_operand:DF 0 "register_operand" "=&f")
2224 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2225 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2227 [(set_attr "type" "fadd")
2228 (set_attr "trap" "yes")])
2230 (define_insn "floatdidf2"
2231 [(set (match_operand:DF 0 "register_operand" "=f")
2232 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2235 [(set_attr "type" "fadd")
2236 (set_attr "trap" "yes")])
2238 (define_expand "floatditf2"
2239 [(use (match_operand:TF 0 "register_operand" ""))
2240 (use (match_operand:DI 1 "general_operand" ""))]
2241 "TARGET_HAS_XFLOATING_LIBS"
2242 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2244 (define_expand "floatunsdisf2"
2245 [(use (match_operand:SF 0 "register_operand" ""))
2246 (use (match_operand:DI 1 "register_operand" ""))]
2248 "alpha_emit_floatuns (operands); DONE;")
2250 (define_expand "floatunsdidf2"
2251 [(use (match_operand:DF 0 "register_operand" ""))
2252 (use (match_operand:DI 1 "register_operand" ""))]
2254 "alpha_emit_floatuns (operands); DONE;")
2256 (define_expand "floatunsditf2"
2257 [(use (match_operand:TF 0 "register_operand" ""))
2258 (use (match_operand:DI 1 "general_operand" ""))]
2259 "TARGET_HAS_XFLOATING_LIBS"
2260 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2262 (define_expand "extendsfdf2"
2263 [(set (match_operand:DF 0 "register_operand" "")
2264 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2268 if (alpha_fptm >= ALPHA_FPTM_SU)
2269 operands[1] = force_reg (SFmode, operands[1]);
2272 (define_insn "*extendsfdf2_ieee"
2273 [(set (match_operand:DF 0 "register_operand" "=&f")
2274 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2275 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2277 [(set_attr "type" "fadd")
2278 (set_attr "trap" "yes")])
2280 (define_insn "*extendsfdf2_internal"
2281 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2282 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2283 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2288 [(set_attr "type" "fcpys,fld,fst")])
2290 (define_expand "extendsftf2"
2291 [(use (match_operand:TF 0 "register_operand" ""))
2292 (use (match_operand:SF 1 "general_operand" ""))]
2293 "TARGET_HAS_XFLOATING_LIBS"
2296 rtx tmp = gen_reg_rtx (DFmode);
2297 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2298 emit_insn (gen_extenddftf2 (operands[0], tmp));
2302 (define_expand "extenddftf2"
2303 [(use (match_operand:TF 0 "register_operand" ""))
2304 (use (match_operand:DF 1 "general_operand" ""))]
2305 "TARGET_HAS_XFLOATING_LIBS"
2306 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2308 (define_insn "*truncdfsf2_ieee"
2309 [(set (match_operand:SF 0 "register_operand" "=&f")
2310 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2311 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2312 "cvt%-%,%)%& %R1,%0"
2313 [(set_attr "type" "fadd")
2314 (set_attr "trap" "yes")])
2316 (define_insn "truncdfsf2"
2317 [(set (match_operand:SF 0 "register_operand" "=f")
2318 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2320 "cvt%-%,%)%& %R1,%0"
2321 [(set_attr "type" "fadd")
2322 (set_attr "trap" "yes")])
2324 (define_expand "trunctfdf2"
2325 [(use (match_operand:DF 0 "register_operand" ""))
2326 (use (match_operand:TF 1 "general_operand" ""))]
2327 "TARGET_HAS_XFLOATING_LIBS"
2328 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2330 (define_expand "trunctfsf2"
2331 [(use (match_operand:SF 0 "register_operand" ""))
2332 (use (match_operand:TF 1 "general_operand" ""))]
2333 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2336 rtx tmpf, sticky, arg, lo, hi;
2338 tmpf = gen_reg_rtx (DFmode);
2339 sticky = gen_reg_rtx (DImode);
2340 arg = copy_to_mode_reg (TFmode, operands[1]);
2341 lo = gen_lowpart (DImode, arg);
2342 hi = gen_highpart (DImode, arg);
2344 /* Convert the low word of the TFmode value into a sticky rounding bit,
2345 then or it into the low bit of the high word. This leaves the sticky
2346 bit at bit 48 of the fraction, which is representable in DFmode,
2347 which prevents rounding error in the final conversion to SFmode. */
2349 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2350 gen_rtx_NE (DImode, lo, const0_rtx)));
2351 emit_insn (gen_iordi3 (hi, hi, sticky));
2352 emit_insn (gen_trunctfdf2 (tmpf, arg));
2353 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2357 (define_insn "*divsf3_ieee"
2358 [(set (match_operand:SF 0 "register_operand" "=&f")
2359 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2360 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2361 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2362 "div%,%)%& %R1,%R2,%0"
2363 [(set_attr "type" "fdiv")
2364 (set_attr "opsize" "si")
2365 (set_attr "trap" "yes")])
2367 (define_insn "divsf3"
2368 [(set (match_operand:SF 0 "register_operand" "=f")
2369 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2370 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2372 "div%,%)%& %R1,%R2,%0"
2373 [(set_attr "type" "fdiv")
2374 (set_attr "opsize" "si")
2375 (set_attr "trap" "yes")])
2377 (define_insn "*divdf3_ieee"
2378 [(set (match_operand:DF 0 "register_operand" "=&f")
2379 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2380 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2381 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2382 "div%-%)%& %R1,%R2,%0"
2383 [(set_attr "type" "fdiv")
2384 (set_attr "trap" "yes")])
2386 (define_insn "divdf3"
2387 [(set (match_operand:DF 0 "register_operand" "=f")
2388 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2389 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2391 "div%-%)%& %R1,%R2,%0"
2392 [(set_attr "type" "fdiv")
2393 (set_attr "trap" "yes")])
2395 (define_insn "*divdf_ext1"
2396 [(set (match_operand:DF 0 "register_operand" "=f")
2397 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2398 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2399 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2400 "div%-%)%& %R1,%R2,%0"
2401 [(set_attr "type" "fdiv")
2402 (set_attr "trap" "yes")])
2404 (define_insn "*divdf_ext2"
2405 [(set (match_operand:DF 0 "register_operand" "=f")
2406 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2408 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2409 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2410 "div%-%)%& %R1,%R2,%0"
2411 [(set_attr "type" "fdiv")
2412 (set_attr "trap" "yes")])
2414 (define_insn "*divdf_ext3"
2415 [(set (match_operand:DF 0 "register_operand" "=f")
2416 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2417 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2418 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2419 "div%-%)%& %R1,%R2,%0"
2420 [(set_attr "type" "fdiv")
2421 (set_attr "trap" "yes")])
2423 (define_expand "divtf3"
2424 [(use (match_operand 0 "register_operand" ""))
2425 (use (match_operand 1 "general_operand" ""))
2426 (use (match_operand 2 "general_operand" ""))]
2427 "TARGET_HAS_XFLOATING_LIBS"
2428 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2430 (define_insn "*mulsf3_ieee"
2431 [(set (match_operand:SF 0 "register_operand" "=&f")
2432 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2433 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2434 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2435 "mul%,%)%& %R1,%R2,%0"
2436 [(set_attr "type" "fmul")
2437 (set_attr "trap" "yes")])
2439 (define_insn "mulsf3"
2440 [(set (match_operand:SF 0 "register_operand" "=f")
2441 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2442 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2444 "mul%,%)%& %R1,%R2,%0"
2445 [(set_attr "type" "fmul")
2446 (set_attr "trap" "yes")])
2448 (define_insn "*muldf3_ieee"
2449 [(set (match_operand:DF 0 "register_operand" "=&f")
2450 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2451 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2452 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2453 "mul%-%)%& %R1,%R2,%0"
2454 [(set_attr "type" "fmul")
2455 (set_attr "trap" "yes")])
2457 (define_insn "muldf3"
2458 [(set (match_operand:DF 0 "register_operand" "=f")
2459 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2460 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2462 "mul%-%)%& %R1,%R2,%0"
2463 [(set_attr "type" "fmul")
2464 (set_attr "trap" "yes")])
2466 (define_insn "*muldf_ext1"
2467 [(set (match_operand:DF 0 "register_operand" "=f")
2468 (mult:DF (float_extend:DF
2469 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2470 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2471 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2472 "mul%-%)%& %R1,%R2,%0"
2473 [(set_attr "type" "fmul")
2474 (set_attr "trap" "yes")])
2476 (define_insn "*muldf_ext2"
2477 [(set (match_operand:DF 0 "register_operand" "=f")
2478 (mult:DF (float_extend:DF
2479 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2481 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2482 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2483 "mul%-%)%& %R1,%R2,%0"
2484 [(set_attr "type" "fmul")
2485 (set_attr "trap" "yes")])
2487 (define_expand "multf3"
2488 [(use (match_operand 0 "register_operand" ""))
2489 (use (match_operand 1 "general_operand" ""))
2490 (use (match_operand 2 "general_operand" ""))]
2491 "TARGET_HAS_XFLOATING_LIBS"
2492 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2494 (define_insn "*subsf3_ieee"
2495 [(set (match_operand:SF 0 "register_operand" "=&f")
2496 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2497 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2498 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2499 "sub%,%)%& %R1,%R2,%0"
2500 [(set_attr "type" "fadd")
2501 (set_attr "trap" "yes")])
2503 (define_insn "subsf3"
2504 [(set (match_operand:SF 0 "register_operand" "=f")
2505 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2506 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2508 "sub%,%)%& %R1,%R2,%0"
2509 [(set_attr "type" "fadd")
2510 (set_attr "trap" "yes")])
2512 (define_insn "*subdf3_ieee"
2513 [(set (match_operand:DF 0 "register_operand" "=&f")
2514 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2515 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2516 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2517 "sub%-%)%& %R1,%R2,%0"
2518 [(set_attr "type" "fadd")
2519 (set_attr "trap" "yes")])
2521 (define_insn "subdf3"
2522 [(set (match_operand:DF 0 "register_operand" "=f")
2523 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2524 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2526 "sub%-%)%& %R1,%R2,%0"
2527 [(set_attr "type" "fadd")
2528 (set_attr "trap" "yes")])
2530 (define_insn "*subdf_ext1"
2531 [(set (match_operand:DF 0 "register_operand" "=f")
2532 (minus:DF (float_extend:DF
2533 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2534 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2535 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2536 "sub%-%)%& %R1,%R2,%0"
2537 [(set_attr "type" "fadd")
2538 (set_attr "trap" "yes")])
2540 (define_insn "*subdf_ext2"
2541 [(set (match_operand:DF 0 "register_operand" "=f")
2542 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2544 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2545 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2546 "sub%-%)%& %R1,%R2,%0"
2547 [(set_attr "type" "fadd")
2548 (set_attr "trap" "yes")])
2550 (define_insn "*subdf_ext3"
2551 [(set (match_operand:DF 0 "register_operand" "=f")
2552 (minus:DF (float_extend:DF
2553 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2555 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2556 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2557 "sub%-%)%& %R1,%R2,%0"
2558 [(set_attr "type" "fadd")
2559 (set_attr "trap" "yes")])
2561 (define_expand "subtf3"
2562 [(use (match_operand 0 "register_operand" ""))
2563 (use (match_operand 1 "general_operand" ""))
2564 (use (match_operand 2 "general_operand" ""))]
2565 "TARGET_HAS_XFLOATING_LIBS"
2566 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
2568 (define_insn "*sqrtsf2_ieee"
2569 [(set (match_operand:SF 0 "register_operand" "=&f")
2570 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2571 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2573 [(set_attr "type" "fsqrt")
2574 (set_attr "opsize" "si")
2575 (set_attr "trap" "yes")])
2577 (define_insn "sqrtsf2"
2578 [(set (match_operand:SF 0 "register_operand" "=f")
2579 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2580 "TARGET_FP && TARGET_FIX"
2582 [(set_attr "type" "fsqrt")
2583 (set_attr "opsize" "si")
2584 (set_attr "trap" "yes")])
2586 (define_insn "*sqrtdf2_ieee"
2587 [(set (match_operand:DF 0 "register_operand" "=&f")
2588 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2589 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2591 [(set_attr "type" "fsqrt")
2592 (set_attr "trap" "yes")])
2594 (define_insn "sqrtdf2"
2595 [(set (match_operand:DF 0 "register_operand" "=f")
2596 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2597 "TARGET_FP && TARGET_FIX"
2599 [(set_attr "type" "fsqrt")
2600 (set_attr "trap" "yes")])
2602 ;; Next are all the integer comparisons, and conditional moves and branches
2603 ;; and some of the related define_expand's and define_split's.
2605 (define_insn "*setcc_internal"
2606 [(set (match_operand 0 "register_operand" "=r")
2607 (match_operator 1 "alpha_comparison_operator"
2608 [(match_operand:DI 2 "register_operand" "r")
2609 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
2610 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2611 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2612 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2614 [(set_attr "type" "icmp")])
2616 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
2617 ;; but that's non-canonical rtl and allowing that causes inefficiencies
2619 (define_insn "*setcc_swapped_internal"
2620 [(set (match_operand 0 "register_operand" "=r")
2621 (match_operator 1 "alpha_swapped_comparison_operator"
2622 [(match_operand:DI 2 "register_operand" "r")
2623 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
2624 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2625 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2626 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2628 [(set_attr "type" "icmp")])
2630 ;; Use match_operator rather than ne directly so that we can match
2631 ;; multiple integer modes.
2632 (define_insn "*setne_internal"
2633 [(set (match_operand 0 "register_operand" "=r")
2634 (match_operator 1 "signed_comparison_operator"
2635 [(match_operand:DI 2 "register_operand" "r")
2637 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2638 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2639 && GET_CODE (operands[1]) == NE
2640 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2642 [(set_attr "type" "icmp")])
2644 ;; The mode folding trick can't be used with const_int operands, since
2645 ;; reload needs to know the proper mode.
2647 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
2648 ;; in order to create more pairs of constants. As long as we're allowing
2649 ;; two constants at the same time, and will have to reload one of them...
2651 (define_insn "*movqicc_internal"
2652 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
2654 (match_operator 2 "signed_comparison_operator"
2655 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2656 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2657 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
2658 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
2659 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2665 [(set_attr "type" "icmov")])
2667 (define_insn "*movhicc_internal"
2668 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2670 (match_operator 2 "signed_comparison_operator"
2671 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2672 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2673 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
2674 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
2675 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2681 [(set_attr "type" "icmov")])
2683 (define_insn "*movsicc_internal"
2684 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2686 (match_operator 2 "signed_comparison_operator"
2687 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2688 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2689 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
2690 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
2691 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2697 [(set_attr "type" "icmov")])
2699 (define_insn "*movdicc_internal"
2700 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
2702 (match_operator 2 "signed_comparison_operator"
2703 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2704 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2705 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
2706 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
2707 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2713 [(set_attr "type" "icmov")])
2715 (define_insn "*movqicc_lbc"
2716 [(set (match_operand:QI 0 "register_operand" "=r,r")
2718 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2722 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
2723 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
2728 [(set_attr "type" "icmov")])
2730 (define_insn "*movhicc_lbc"
2731 [(set (match_operand:HI 0 "register_operand" "=r,r")
2733 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2737 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
2738 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
2743 [(set_attr "type" "icmov")])
2745 (define_insn "*movsicc_lbc"
2746 [(set (match_operand:SI 0 "register_operand" "=r,r")
2748 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2752 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
2753 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
2758 [(set_attr "type" "icmov")])
2760 (define_insn "*movdicc_lbc"
2761 [(set (match_operand:DI 0 "register_operand" "=r,r")
2763 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2767 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2768 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2773 [(set_attr "type" "icmov")])
2775 (define_insn "*movqicc_lbs"
2776 [(set (match_operand:QI 0 "register_operand" "=r,r")
2778 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2782 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
2783 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
2788 [(set_attr "type" "icmov")])
2790 (define_insn "*movhicc_lbs"
2791 [(set (match_operand:HI 0 "register_operand" "=r,r")
2793 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2797 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
2798 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
2803 [(set_attr "type" "icmov")])
2805 (define_insn "*movsicc_lbs"
2806 [(set (match_operand:SI 0 "register_operand" "=r,r")
2808 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2812 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
2813 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
2818 [(set_attr "type" "icmov")])
2820 (define_insn "*movdicc_lbs"
2821 [(set (match_operand:DI 0 "register_operand" "=r,r")
2823 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2827 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2828 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2833 [(set_attr "type" "icmov")])
2835 ;; For ABS, we have two choices, depending on whether the input and output
2836 ;; registers are the same or not.
2837 (define_expand "absdi2"
2838 [(set (match_operand:DI 0 "register_operand" "")
2839 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2842 { if (rtx_equal_p (operands[0], operands[1]))
2843 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
2845 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
2850 (define_expand "absdi2_same"
2851 [(set (match_operand:DI 1 "register_operand" "")
2852 (neg:DI (match_operand:DI 0 "register_operand" "")))
2854 (if_then_else:DI (ge (match_dup 0) (const_int 0))
2860 (define_expand "absdi2_diff"
2861 [(set (match_operand:DI 0 "register_operand" "")
2862 (neg:DI (match_operand:DI 1 "register_operand" "")))
2864 (if_then_else:DI (lt (match_dup 1) (const_int 0))
2871 [(set (match_operand:DI 0 "register_operand" "")
2872 (abs:DI (match_dup 0)))
2873 (clobber (match_operand:DI 1 "register_operand" ""))]
2875 [(set (match_dup 1) (neg:DI (match_dup 0)))
2876 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
2877 (match_dup 0) (match_dup 1)))]
2881 [(set (match_operand:DI 0 "register_operand" "")
2882 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2883 "! rtx_equal_p (operands[0], operands[1])"
2884 [(set (match_dup 0) (neg:DI (match_dup 1)))
2885 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
2886 (match_dup 0) (match_dup 1)))]
2890 [(set (match_operand:DI 0 "register_operand" "")
2891 (neg:DI (abs:DI (match_dup 0))))
2892 (clobber (match_operand:DI 1 "register_operand" ""))]
2894 [(set (match_dup 1) (neg:DI (match_dup 0)))
2895 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
2896 (match_dup 0) (match_dup 1)))]
2900 [(set (match_operand:DI 0 "register_operand" "")
2901 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
2902 "! rtx_equal_p (operands[0], operands[1])"
2903 [(set (match_dup 0) (neg:DI (match_dup 1)))
2904 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
2905 (match_dup 0) (match_dup 1)))]
2908 (define_insn "sminqi3"
2909 [(set (match_operand:QI 0 "register_operand" "=r")
2910 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2911 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2914 [(set_attr "type" "mvi")])
2916 (define_insn "uminqi3"
2917 [(set (match_operand:QI 0 "register_operand" "=r")
2918 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2919 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2922 [(set_attr "type" "mvi")])
2924 (define_insn "smaxqi3"
2925 [(set (match_operand:QI 0 "register_operand" "=r")
2926 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2927 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2930 [(set_attr "type" "mvi")])
2932 (define_insn "umaxqi3"
2933 [(set (match_operand:QI 0 "register_operand" "=r")
2934 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2935 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2938 [(set_attr "type" "mvi")])
2940 (define_insn "sminhi3"
2941 [(set (match_operand:HI 0 "register_operand" "=r")
2942 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2943 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2946 [(set_attr "type" "mvi")])
2948 (define_insn "uminhi3"
2949 [(set (match_operand:HI 0 "register_operand" "=r")
2950 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2951 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2954 [(set_attr "type" "mvi")])
2956 (define_insn "smaxhi3"
2957 [(set (match_operand:HI 0 "register_operand" "=r")
2958 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2959 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2962 [(set_attr "type" "mvi")])
2964 (define_insn "umaxhi3"
2965 [(set (match_operand:HI 0 "register_operand" "=r")
2966 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2967 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2970 [(set_attr "type" "shift")])
2972 (define_expand "smaxdi3"
2974 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
2975 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2976 (set (match_operand:DI 0 "register_operand" "")
2977 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2978 (match_dup 1) (match_dup 2)))]
2981 { operands[3] = gen_reg_rtx (DImode);
2985 [(set (match_operand:DI 0 "register_operand" "")
2986 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2987 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2988 (clobber (match_operand:DI 3 "register_operand" ""))]
2989 "operands[2] != const0_rtx"
2990 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
2991 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2992 (match_dup 1) (match_dup 2)))]
2995 (define_insn "*smax_const0"
2996 [(set (match_operand:DI 0 "register_operand" "=r")
2997 (smax:DI (match_operand:DI 1 "register_operand" "0")
3001 [(set_attr "type" "icmov")])
3003 (define_expand "smindi3"
3005 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3006 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3007 (set (match_operand:DI 0 "register_operand" "")
3008 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3009 (match_dup 1) (match_dup 2)))]
3012 { operands[3] = gen_reg_rtx (DImode);
3016 [(set (match_operand:DI 0 "register_operand" "")
3017 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3018 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3019 (clobber (match_operand:DI 3 "register_operand" ""))]
3020 "operands[2] != const0_rtx"
3021 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3022 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3023 (match_dup 1) (match_dup 2)))]
3026 (define_insn "*smin_const0"
3027 [(set (match_operand:DI 0 "register_operand" "=r")
3028 (smin:DI (match_operand:DI 1 "register_operand" "0")
3032 [(set_attr "type" "icmov")])
3034 (define_expand "umaxdi3"
3036 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3037 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3038 (set (match_operand:DI 0 "register_operand" "")
3039 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3040 (match_dup 1) (match_dup 2)))]
3042 "operands[3] = gen_reg_rtx (DImode);")
3045 [(set (match_operand:DI 0 "register_operand" "")
3046 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3047 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3048 (clobber (match_operand:DI 3 "register_operand" ""))]
3049 "operands[2] != const0_rtx"
3050 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3051 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3052 (match_dup 1) (match_dup 2)))]
3055 (define_expand "umindi3"
3057 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3058 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3059 (set (match_operand:DI 0 "register_operand" "")
3060 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3061 (match_dup 1) (match_dup 2)))]
3063 "operands[3] = gen_reg_rtx (DImode);")
3066 [(set (match_operand:DI 0 "register_operand" "")
3067 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3068 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3069 (clobber (match_operand:DI 3 "register_operand" ""))]
3070 "operands[2] != const0_rtx"
3071 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3072 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3073 (match_dup 1) (match_dup 2)))]
3076 (define_insn "*bcc_normal"
3079 (match_operator 1 "signed_comparison_operator"
3080 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3082 (label_ref (match_operand 0 "" ""))
3086 [(set_attr "type" "ibr")])
3088 (define_insn "*bcc_reverse"
3091 (match_operator 1 "signed_comparison_operator"
3092 [(match_operand:DI 2 "register_operand" "r")
3096 (label_ref (match_operand 0 "" ""))))]
3099 [(set_attr "type" "ibr")])
3101 (define_insn "*blbs_normal"
3104 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3108 (label_ref (match_operand 0 "" ""))
3112 [(set_attr "type" "ibr")])
3114 (define_insn "*blbc_normal"
3117 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3121 (label_ref (match_operand 0 "" ""))
3125 [(set_attr "type" "ibr")])
3131 (match_operator 1 "comparison_operator"
3132 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3134 (match_operand:DI 3 "const_int_operand" ""))
3136 (label_ref (match_operand 0 "" ""))
3138 (clobber (match_operand:DI 4 "register_operand" ""))])]
3139 "INTVAL (operands[3]) != 0"
3141 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3143 (if_then_else (match_op_dup 1
3144 [(zero_extract:DI (match_dup 4)
3148 (label_ref (match_dup 0))
3152 ;; The following are the corresponding floating-point insns. Recall
3153 ;; we need to have variants that expand the arguments from SFmode
3156 (define_insn "*cmpdf_ieee"
3157 [(set (match_operand:DF 0 "register_operand" "=&f")
3158 (match_operator:DF 1 "alpha_fp_comparison_operator"
3159 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3160 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3161 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3162 "cmp%-%C1%' %R2,%R3,%0"
3163 [(set_attr "type" "fadd")
3164 (set_attr "trap" "yes")])
3166 (define_insn "*cmpdf_internal"
3167 [(set (match_operand:DF 0 "register_operand" "=f")
3168 (match_operator:DF 1 "alpha_fp_comparison_operator"
3169 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3170 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3171 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3172 "cmp%-%C1%' %R2,%R3,%0"
3173 [(set_attr "type" "fadd")
3174 (set_attr "trap" "yes")])
3176 (define_insn "*cmpdf_ieee_ext1"
3177 [(set (match_operand:DF 0 "register_operand" "=&f")
3178 (match_operator:DF 1 "alpha_fp_comparison_operator"
3180 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3181 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3182 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3183 "cmp%-%C1%' %R2,%R3,%0"
3184 [(set_attr "type" "fadd")
3185 (set_attr "trap" "yes")])
3187 (define_insn "*cmpdf_ext1"
3188 [(set (match_operand:DF 0 "register_operand" "=f")
3189 (match_operator:DF 1 "alpha_fp_comparison_operator"
3191 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3192 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3193 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3194 "cmp%-%C1%' %R2,%R3,%0"
3195 [(set_attr "type" "fadd")
3196 (set_attr "trap" "yes")])
3198 (define_insn "*cmpdf_ieee_ext2"
3199 [(set (match_operand:DF 0 "register_operand" "=&f")
3200 (match_operator:DF 1 "alpha_fp_comparison_operator"
3201 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3203 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3204 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3205 "cmp%-%C1%' %R2,%R3,%0"
3206 [(set_attr "type" "fadd")
3207 (set_attr "trap" "yes")])
3209 (define_insn "*cmpdf_ext2"
3210 [(set (match_operand:DF 0 "register_operand" "=f")
3211 (match_operator:DF 1 "alpha_fp_comparison_operator"
3212 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3214 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3215 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3216 "cmp%-%C1%' %R2,%R3,%0"
3217 [(set_attr "type" "fadd")
3218 (set_attr "trap" "yes")])
3220 (define_insn "*cmpdf_ieee_ext3"
3221 [(set (match_operand:DF 0 "register_operand" "=&f")
3222 (match_operator:DF 1 "alpha_fp_comparison_operator"
3224 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3226 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3227 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3228 "cmp%-%C1%' %R2,%R3,%0"
3229 [(set_attr "type" "fadd")
3230 (set_attr "trap" "yes")])
3232 (define_insn "*cmpdf_ext3"
3233 [(set (match_operand:DF 0 "register_operand" "=f")
3234 (match_operator:DF 1 "alpha_fp_comparison_operator"
3236 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3238 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3239 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3240 "cmp%-%C1%' %R2,%R3,%0"
3241 [(set_attr "type" "fadd")
3242 (set_attr "trap" "yes")])
3244 (define_insn "*movdfcc_internal"
3245 [(set (match_operand:DF 0 "register_operand" "=f,f")
3247 (match_operator 3 "signed_comparison_operator"
3248 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3249 (match_operand:DF 2 "fp0_operand" "G,G")])
3250 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3251 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3255 fcmov%D3 %R4,%R5,%0"
3256 [(set_attr "type" "fcmov")])
3258 (define_insn "*movsfcc_internal"
3259 [(set (match_operand:SF 0 "register_operand" "=f,f")
3261 (match_operator 3 "signed_comparison_operator"
3262 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3263 (match_operand:DF 2 "fp0_operand" "G,G")])
3264 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3265 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3269 fcmov%D3 %R4,%R5,%0"
3270 [(set_attr "type" "fcmov")])
3272 (define_insn "*movdfcc_ext1"
3273 [(set (match_operand:DF 0 "register_operand" "=f,f")
3275 (match_operator 3 "signed_comparison_operator"
3276 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3277 (match_operand:DF 2 "fp0_operand" "G,G")])
3278 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3279 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3283 fcmov%D3 %R4,%R5,%0"
3284 [(set_attr "type" "fcmov")])
3286 (define_insn "*movdfcc_ext2"
3287 [(set (match_operand:DF 0 "register_operand" "=f,f")
3289 (match_operator 3 "signed_comparison_operator"
3291 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3292 (match_operand:DF 2 "fp0_operand" "G,G")])
3293 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3294 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3298 fcmov%D3 %R4,%R5,%0"
3299 [(set_attr "type" "fcmov")])
3301 (define_insn "*movdfcc_ext3"
3302 [(set (match_operand:SF 0 "register_operand" "=f,f")
3304 (match_operator 3 "signed_comparison_operator"
3306 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3307 (match_operand:DF 2 "fp0_operand" "G,G")])
3308 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3309 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3313 fcmov%D3 %R4,%R5,%0"
3314 [(set_attr "type" "fcmov")])
3316 (define_insn "*movdfcc_ext4"
3317 [(set (match_operand:DF 0 "register_operand" "=f,f")
3319 (match_operator 3 "signed_comparison_operator"
3321 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3322 (match_operand:DF 2 "fp0_operand" "G,G")])
3323 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3324 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3328 fcmov%D3 %R4,%R5,%0"
3329 [(set_attr "type" "fcmov")])
3331 (define_expand "maxdf3"
3333 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3334 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3335 (set (match_operand:DF 0 "register_operand" "")
3336 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3337 (match_dup 1) (match_dup 2)))]
3340 { operands[3] = gen_reg_rtx (DFmode);
3341 operands[4] = CONST0_RTX (DFmode);
3344 (define_expand "mindf3"
3346 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3347 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3348 (set (match_operand:DF 0 "register_operand" "")
3349 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3350 (match_dup 1) (match_dup 2)))]
3353 { operands[3] = gen_reg_rtx (DFmode);
3354 operands[4] = CONST0_RTX (DFmode);
3357 (define_expand "maxsf3"
3359 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3360 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3361 (set (match_operand:SF 0 "register_operand" "")
3362 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3363 (match_dup 1) (match_dup 2)))]
3366 { operands[3] = gen_reg_rtx (DFmode);
3367 operands[4] = CONST0_RTX (DFmode);
3370 (define_expand "minsf3"
3372 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3373 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3374 (set (match_operand:SF 0 "register_operand" "")
3375 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3376 (match_dup 1) (match_dup 2)))]
3379 { operands[3] = gen_reg_rtx (DFmode);
3380 operands[4] = CONST0_RTX (DFmode);
3383 (define_insn "*fbcc_normal"
3386 (match_operator 1 "signed_comparison_operator"
3387 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3388 (match_operand:DF 3 "fp0_operand" "G")])
3389 (label_ref (match_operand 0 "" ""))
3393 [(set_attr "type" "fbr")])
3395 (define_insn "*fbcc_ext_normal"
3398 (match_operator 1 "signed_comparison_operator"
3400 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3401 (match_operand:DF 3 "fp0_operand" "G")])
3402 (label_ref (match_operand 0 "" ""))
3406 [(set_attr "type" "fbr")])
3408 ;; These are the main define_expand's used to make conditional branches
3411 (define_expand "cmpdf"
3412 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
3413 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
3417 alpha_compare.op0 = operands[0];
3418 alpha_compare.op1 = operands[1];
3419 alpha_compare.fp_p = 1;
3423 (define_expand "cmptf"
3424 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3425 (match_operand:TF 1 "general_operand" "")))]
3426 "TARGET_HAS_XFLOATING_LIBS"
3429 alpha_compare.op0 = operands[0];
3430 alpha_compare.op1 = operands[1];
3431 alpha_compare.fp_p = 1;
3435 (define_expand "cmpdi"
3436 [(set (cc0) (compare (match_operand:DI 0 "general_operand" "")
3437 (match_operand:DI 1 "general_operand" "")))]
3441 alpha_compare.op0 = operands[0];
3442 alpha_compare.op1 = operands[1];
3443 alpha_compare.fp_p = 0;
3447 (define_expand "beq"
3449 (if_then_else (match_dup 1)
3450 (label_ref (match_operand 0 "" ""))
3453 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3455 (define_expand "bne"
3457 (if_then_else (match_dup 1)
3458 (label_ref (match_operand 0 "" ""))
3461 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3463 (define_expand "blt"
3465 (if_then_else (match_dup 1)
3466 (label_ref (match_operand 0 "" ""))
3469 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3471 (define_expand "ble"
3473 (if_then_else (match_dup 1)
3474 (label_ref (match_operand 0 "" ""))
3477 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3479 (define_expand "bgt"
3481 (if_then_else (match_dup 1)
3482 (label_ref (match_operand 0 "" ""))
3485 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3487 (define_expand "bge"
3489 (if_then_else (match_dup 1)
3490 (label_ref (match_operand 0 "" ""))
3493 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3495 (define_expand "bltu"
3497 (if_then_else (match_dup 1)
3498 (label_ref (match_operand 0 "" ""))
3501 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3503 (define_expand "bleu"
3505 (if_then_else (match_dup 1)
3506 (label_ref (match_operand 0 "" ""))
3509 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3511 (define_expand "bgtu"
3513 (if_then_else (match_dup 1)
3514 (label_ref (match_operand 0 "" ""))
3517 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3519 (define_expand "bgeu"
3521 (if_then_else (match_dup 1)
3522 (label_ref (match_operand 0 "" ""))
3525 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3527 (define_expand "bunordered"
3529 (if_then_else (match_dup 1)
3530 (label_ref (match_operand 0 "" ""))
3533 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3535 (define_expand "bordered"
3537 (if_then_else (match_dup 1)
3538 (label_ref (match_operand 0 "" ""))
3541 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3543 (define_expand "seq"
3544 [(set (match_operand:DI 0 "register_operand" "")
3547 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
3549 (define_expand "sne"
3550 [(set (match_operand:DI 0 "register_operand" "")
3553 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
3555 (define_expand "slt"
3556 [(set (match_operand:DI 0 "register_operand" "")
3559 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
3561 (define_expand "sle"
3562 [(set (match_operand:DI 0 "register_operand" "")
3565 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
3567 (define_expand "sgt"
3568 [(set (match_operand:DI 0 "register_operand" "")
3571 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
3573 (define_expand "sge"
3574 [(set (match_operand:DI 0 "register_operand" "")
3577 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
3579 (define_expand "sltu"
3580 [(set (match_operand:DI 0 "register_operand" "")
3583 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
3585 (define_expand "sleu"
3586 [(set (match_operand:DI 0 "register_operand" "")
3589 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
3591 (define_expand "sgtu"
3592 [(set (match_operand:DI 0 "register_operand" "")
3595 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
3597 (define_expand "sgeu"
3598 [(set (match_operand:DI 0 "register_operand" "")
3601 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
3603 (define_expand "sunordered"
3604 [(set (match_operand:DI 0 "register_operand" "")
3607 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
3609 (define_expand "sordered"
3610 [(set (match_operand:DI 0 "register_operand" "")
3613 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
3615 ;; These are the main define_expand's used to make conditional moves.
3617 (define_expand "movsicc"
3618 [(set (match_operand:SI 0 "register_operand" "")
3619 (if_then_else:SI (match_operand 1 "comparison_operator" "")
3620 (match_operand:SI 2 "reg_or_8bit_operand" "")
3621 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
3625 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
3629 (define_expand "movdicc"
3630 [(set (match_operand:DI 0 "register_operand" "")
3631 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3632 (match_operand:DI 2 "reg_or_8bit_operand" "")
3633 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
3637 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
3641 (define_expand "movsfcc"
3642 [(set (match_operand:SF 0 "register_operand" "")
3643 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3644 (match_operand:SF 2 "reg_or_8bit_operand" "")
3645 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
3649 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
3653 (define_expand "movdfcc"
3654 [(set (match_operand:DF 0 "register_operand" "")
3655 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3656 (match_operand:DF 2 "reg_or_8bit_operand" "")
3657 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
3661 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
3665 ;; These define_split definitions are used in cases when comparisons have
3666 ;; not be stated in the correct way and we need to reverse the second
3667 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
3668 ;; comparison that tests the result being reversed. We have one define_split
3669 ;; for each use of a comparison. They do not match valid insns and need
3670 ;; not generate valid insns.
3672 ;; We can also handle equality comparisons (and inequality comparisons in
3673 ;; cases where the resulting add cannot overflow) by doing an add followed by
3674 ;; a comparison with zero. This is faster since the addition takes one
3675 ;; less cycle than a compare when feeding into a conditional move.
3676 ;; For this case, we also have an SImode pattern since we can merge the add
3677 ;; and sign extend and the order doesn't matter.
3679 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
3680 ;; operation could have been generated.
3683 [(set (match_operand:DI 0 "register_operand" "")
3685 (match_operator 1 "comparison_operator"
3686 [(match_operand:DI 2 "reg_or_0_operand" "")
3687 (match_operand:DI 3 "reg_or_cint_operand" "")])
3688 (match_operand:DI 4 "reg_or_cint_operand" "")
3689 (match_operand:DI 5 "reg_or_cint_operand" "")))
3690 (clobber (match_operand:DI 6 "register_operand" ""))]
3691 "operands[3] != const0_rtx"
3692 [(set (match_dup 6) (match_dup 7))
3694 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3696 { enum rtx_code code = GET_CODE (operands[1]);
3697 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3699 /* If we are comparing for equality with a constant and that constant
3700 appears in the arm when the register equals the constant, use the
3701 register since that is more likely to match (and to produce better code
3704 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
3705 && rtx_equal_p (operands[4], operands[3]))
3706 operands[4] = operands[2];
3708 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
3709 && rtx_equal_p (operands[5], operands[3]))
3710 operands[5] = operands[2];
3712 if (code == NE || code == EQ
3713 || (extended_count (operands[2], DImode, unsignedp) >= 1
3714 && extended_count (operands[3], DImode, unsignedp) >= 1))
3716 if (GET_CODE (operands[3]) == CONST_INT)
3717 operands[7] = gen_rtx_PLUS (DImode, operands[2],
3718 GEN_INT (- INTVAL (operands[3])));
3720 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3722 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
3725 else if (code == EQ || code == LE || code == LT
3726 || code == LEU || code == LTU)
3728 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3729 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
3733 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3734 operands[2], operands[3]);
3735 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
3740 [(set (match_operand:DI 0 "register_operand" "")
3742 (match_operator 1 "comparison_operator"
3743 [(match_operand:SI 2 "reg_or_0_operand" "")
3744 (match_operand:SI 3 "reg_or_cint_operand" "")])
3745 (match_operand:DI 4 "reg_or_8bit_operand" "")
3746 (match_operand:DI 5 "reg_or_8bit_operand" "")))
3747 (clobber (match_operand:DI 6 "register_operand" ""))]
3748 "operands[3] != const0_rtx
3749 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3750 [(set (match_dup 6) (match_dup 7))
3752 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3754 { enum rtx_code code = GET_CODE (operands[1]);
3755 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3758 if ((code != NE && code != EQ
3759 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
3760 && extended_count (operands[3], DImode, unsignedp) >= 1)))
3763 if (GET_CODE (operands[3]) == CONST_INT)
3764 tem = gen_rtx_PLUS (SImode, operands[2],
3765 GEN_INT (- INTVAL (operands[3])));
3767 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3769 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
3770 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3771 operands[6], const0_rtx);
3777 (match_operator 1 "comparison_operator"
3778 [(match_operand:DI 2 "reg_or_0_operand" "")
3779 (match_operand:DI 3 "reg_or_cint_operand" "")])
3780 (label_ref (match_operand 0 "" ""))
3782 (clobber (match_operand:DI 4 "register_operand" ""))]
3783 "operands[3] != const0_rtx"
3784 [(set (match_dup 4) (match_dup 5))
3785 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3787 { enum rtx_code code = GET_CODE (operands[1]);
3788 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3790 if (code == NE || code == EQ
3791 || (extended_count (operands[2], DImode, unsignedp) >= 1
3792 && extended_count (operands[3], DImode, unsignedp) >= 1))
3794 if (GET_CODE (operands[3]) == CONST_INT)
3795 operands[5] = gen_rtx_PLUS (DImode, operands[2],
3796 GEN_INT (- INTVAL (operands[3])));
3798 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3800 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
3803 else if (code == EQ || code == LE || code == LT
3804 || code == LEU || code == LTU)
3806 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3807 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
3811 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3812 operands[2], operands[3]);
3813 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
3820 (match_operator 1 "comparison_operator"
3821 [(match_operand:SI 2 "reg_or_0_operand" "")
3822 (match_operand:SI 3 "const_int_operand" "")])
3823 (label_ref (match_operand 0 "" ""))
3825 (clobber (match_operand:DI 4 "register_operand" ""))]
3826 "operands[3] != const0_rtx
3827 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3828 [(set (match_dup 4) (match_dup 5))
3829 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3833 if (GET_CODE (operands[3]) == CONST_INT)
3834 tem = gen_rtx_PLUS (SImode, operands[2],
3835 GEN_INT (- INTVAL (operands[3])));
3837 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3839 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
3840 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3841 operands[4], const0_rtx);
3844 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
3845 ;; This eliminates one, and sometimes two, insns when the AND can be done
3848 [(set (match_operand:DI 0 "register_operand" "")
3849 (match_operator:DI 1 "comparison_operator"
3850 [(match_operand:DI 2 "register_operand" "")
3851 (match_operand:DI 3 "const_int_operand" "")]))
3852 (clobber (match_operand:DI 4 "register_operand" ""))]
3853 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
3854 && (GET_CODE (operands[1]) == GTU
3855 || GET_CODE (operands[1]) == LEU
3856 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
3857 && extended_count (operands[2], DImode, 1) > 0))"
3858 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
3859 (set (match_dup 0) (match_dup 6))]
3862 operands[5] = GEN_INT (~ INTVAL (operands[3]));
3863 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
3864 || GET_CODE (operands[1]) == GT)
3866 DImode, operands[4], const0_rtx);
3869 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
3872 [(set (match_operand 0 "register_operand" "")
3873 (if_then_else (match_operator 1 "signed_comparison_operator"
3874 [(match_operand:DI 2 "reg_or_0_operand" "")
3876 (match_operand 3 "const_int_operand" "")
3877 (match_operand 4 "const_int_operand" "")))]
3882 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
3883 operands[2], operands[3], operands[4]))
3889 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
3890 ;; Oh well, we match it in movcc, so it must be partially our fault.
3892 [(set (match_operand 0 "register_operand" "")
3893 (if_then_else (match_operator 1 "signed_comparison_operator"
3895 (match_operand:DI 2 "reg_or_0_operand" "")])
3896 (match_operand 3 "const_int_operand" "")
3897 (match_operand 4 "const_int_operand" "")))]
3902 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
3903 operands[0], operands[2], operands[3],
3910 (define_insn_and_split "*cmp_sadd_di"
3911 [(set (match_operand:DI 0 "register_operand" "=r")
3912 (plus:DI (if_then_else:DI
3913 (match_operator 1 "alpha_zero_comparison_operator"
3914 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3916 (match_operand:DI 3 "const48_operand" "I")
3918 (match_operand:DI 4 "sext_add_operand" "rIO")))
3919 (clobber (match_scratch:DI 5 "=r"))]
3922 "! no_new_pseudos || reload_completed"
3924 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
3926 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
3930 if (! no_new_pseudos)
3931 operands[5] = gen_reg_rtx (DImode);
3932 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3933 operands[5] = operands[0];
3936 (define_insn_and_split "*cmp_sadd_si"
3937 [(set (match_operand:SI 0 "register_operand" "=r")
3938 (plus:SI (if_then_else:SI
3939 (match_operator 1 "alpha_zero_comparison_operator"
3940 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3942 (match_operand:SI 3 "const48_operand" "I")
3944 (match_operand:SI 4 "sext_add_operand" "rIO")))
3945 (clobber (match_scratch:SI 5 "=r"))]
3948 "! no_new_pseudos || reload_completed"
3950 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
3952 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
3956 if (! no_new_pseudos)
3957 operands[5] = gen_reg_rtx (DImode);
3958 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3959 operands[5] = operands[0];
3962 (define_insn_and_split "*cmp_sadd_sidi"
3963 [(set (match_operand:DI 0 "register_operand" "=r")
3965 (plus:SI (if_then_else:SI
3966 (match_operator 1 "alpha_zero_comparison_operator"
3967 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3969 (match_operand:SI 3 "const48_operand" "I")
3971 (match_operand:SI 4 "sext_add_operand" "rIO"))))
3972 (clobber (match_scratch:SI 5 "=r"))]
3975 "! no_new_pseudos || reload_completed"
3977 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
3979 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
3983 if (! no_new_pseudos)
3984 operands[5] = gen_reg_rtx (DImode);
3985 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
3986 operands[5] = operands[0];
3989 (define_insn_and_split "*cmp_ssub_di"
3990 [(set (match_operand:DI 0 "register_operand" "=r")
3991 (minus:DI (if_then_else:DI
3992 (match_operator 1 "alpha_zero_comparison_operator"
3993 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3995 (match_operand:DI 3 "const48_operand" "I")
3997 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
3998 (clobber (match_scratch:DI 5 "=r"))]
4001 "! no_new_pseudos || reload_completed"
4003 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4005 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4009 if (! no_new_pseudos)
4010 operands[5] = gen_reg_rtx (DImode);
4011 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4012 operands[5] = operands[0];
4015 (define_insn_and_split "*cmp_ssub_si"
4016 [(set (match_operand:SI 0 "register_operand" "=r")
4017 (minus:SI (if_then_else:SI
4018 (match_operator 1 "alpha_zero_comparison_operator"
4019 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4021 (match_operand:SI 3 "const48_operand" "I")
4023 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4024 (clobber (match_scratch:SI 5 "=r"))]
4027 "! no_new_pseudos || reload_completed"
4029 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4031 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4035 if (! no_new_pseudos)
4036 operands[5] = gen_reg_rtx (DImode);
4037 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4038 operands[5] = operands[0];
4041 (define_insn_and_split "*cmp_ssub_sidi"
4042 [(set (match_operand:DI 0 "register_operand" "=r")
4044 (minus:SI (if_then_else:SI
4045 (match_operator 1 "alpha_zero_comparison_operator"
4046 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4048 (match_operand:SI 3 "const48_operand" "I")
4050 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4051 (clobber (match_scratch:SI 5 "=r"))]
4054 "! no_new_pseudos || reload_completed"
4056 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4058 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4062 if (! no_new_pseudos)
4063 operands[5] = gen_reg_rtx (DImode);
4064 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4065 operands[5] = operands[0];
4068 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4069 ;; work differently, so we have different patterns for each.
4071 (define_expand "call"
4072 [(use (match_operand:DI 0 "" ""))
4073 (use (match_operand 1 "" ""))
4074 (use (match_operand 2 "" ""))
4075 (use (match_operand 3 "" ""))]
4078 { if (TARGET_WINDOWS_NT)
4079 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4080 else if (TARGET_OPEN_VMS)
4081 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4083 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4088 (define_expand "sibcall"
4089 [(call (mem:DI (match_operand 0 "" ""))
4090 (match_operand 1 "" ""))]
4091 "!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT"
4094 if (GET_CODE (operands[0]) != MEM)
4096 operands[0] = XEXP (operands[0], 0);
4099 (define_expand "call_osf"
4100 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4101 (match_operand 1 "" ""))
4102 (clobber (reg:DI 27))
4103 (clobber (reg:DI 26))])]
4106 { if (GET_CODE (operands[0]) != MEM)
4109 operands[0] = XEXP (operands[0], 0);
4111 if (GET_CODE (operands[0]) != SYMBOL_REF
4112 && ! (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 27))
4114 rtx tem = gen_rtx_REG (DImode, 27);
4115 emit_move_insn (tem, operands[0]);
4120 (define_expand "call_nt"
4121 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4122 (match_operand 1 "" ""))
4123 (clobber (reg:DI 26))])]
4126 { if (GET_CODE (operands[0]) != MEM)
4129 operands[0] = XEXP (operands[0], 0);
4130 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4131 operands[0] = force_reg (DImode, operands[0]);
4135 ;; call openvms/alpha
4136 ;; op 0: symbol ref for called function
4137 ;; op 1: next_arg_reg (argument information value for R25)
4139 (define_expand "call_vms"
4140 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4141 (match_operand 1 "" ""))
4145 (clobber (reg:DI 27))])]
4148 { if (GET_CODE (operands[0]) != MEM)
4151 operands[0] = XEXP (operands[0], 0);
4153 /* Always load AI with argument information, then handle symbolic and
4154 indirect call differently. Load RA and set operands[2] to PV in
4157 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4158 if (GET_CODE (operands[0]) == SYMBOL_REF)
4160 rtx linkage = alpha_need_linkage (XSTR (operands[0], 0), 0);
4162 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4164 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4168 emit_move_insn (gen_rtx_REG (Pmode, 26),
4169 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4170 operands[2] = operands[0];
4175 (define_expand "call_value"
4176 [(use (match_operand 0 "" ""))
4177 (use (match_operand:DI 1 "" ""))
4178 (use (match_operand 2 "" ""))
4179 (use (match_operand 3 "" ""))
4180 (use (match_operand 4 "" ""))]
4183 { if (TARGET_WINDOWS_NT)
4184 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4185 else if (TARGET_OPEN_VMS)
4186 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4189 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4194 (define_expand "sibcall_value"
4195 [(set (match_operand 0 "" "")
4196 (call (mem:DI (match_operand 1 "" ""))
4197 (match_operand 2 "" "")))]
4198 "!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT"
4201 if (GET_CODE (operands[1]) != MEM)
4203 operands[1] = XEXP (operands[1], 0);
4206 (define_expand "call_value_osf"
4207 [(parallel [(set (match_operand 0 "" "")
4208 (call (mem:DI (match_operand 1 "" ""))
4209 (match_operand 2 "" "")))
4210 (clobber (reg:DI 27))
4211 (clobber (reg:DI 26))])]
4214 { if (GET_CODE (operands[1]) != MEM)
4217 operands[1] = XEXP (operands[1], 0);
4219 if (GET_CODE (operands[1]) != SYMBOL_REF
4220 && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
4222 rtx tem = gen_rtx_REG (DImode, 27);
4223 emit_move_insn (tem, operands[1]);
4228 (define_expand "call_value_nt"
4229 [(parallel [(set (match_operand 0 "" "")
4230 (call (mem:DI (match_operand 1 "" ""))
4231 (match_operand 2 "" "")))
4232 (clobber (reg:DI 26))])]
4235 { if (GET_CODE (operands[1]) != MEM)
4238 operands[1] = XEXP (operands[1], 0);
4239 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4240 operands[1] = force_reg (DImode, operands[1]);
4243 (define_expand "call_value_vms"
4244 [(parallel [(set (match_operand 0 "" "")
4245 (call (mem:DI (match_operand:DI 1 "" ""))
4246 (match_operand 2 "" "")))
4250 (clobber (reg:DI 27))])]
4253 { if (GET_CODE (operands[1]) != MEM)
4256 operands[1] = XEXP (operands[1], 0);
4258 /* Always load AI with argument information, then handle symbolic and
4259 indirect call differently. Load RA and set operands[3] to PV in
4262 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4263 if (GET_CODE (operands[1]) == SYMBOL_REF)
4265 rtx linkage = alpha_need_linkage (XSTR (operands[1], 0), 0);
4267 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4269 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4273 emit_move_insn (gen_rtx_REG (Pmode, 26),
4274 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4275 operands[3] = operands[1];
4279 (define_insn "*call_osf_1"
4280 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,i"))
4281 (match_operand 1 "" ""))
4282 (clobber (reg:DI 27))
4283 (clobber (reg:DI 26))]
4284 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
4286 jsr $26,($27),0\;ldgp $29,0($26)
4288 jsr $26,%0\;ldgp $29,0($26)"
4289 [(set_attr "type" "jsr")
4290 (set_attr "length" "12,*,16")])
4292 (define_insn "*sibcall_osf_1"
4293 [(call (mem:DI (match_operand:DI 0 "call_operand" "R,i"))
4294 (match_operand 1 "" ""))]
4295 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
4299 [(set_attr "type" "jsr")
4300 (set_attr "length" "*,8")])
4302 (define_insn "*call_nt_1"
4303 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
4304 (match_operand 1 "" ""))
4305 (clobber (reg:DI 26))]
4311 [(set_attr "type" "jsr")
4312 (set_attr "length" "*,*,12")])
4314 (define_insn "*call_vms_1"
4315 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
4316 (match_operand 1 "" ""))
4317 (use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
4320 (clobber (reg:DI 27))]
4323 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
4324 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
4325 [(set_attr "type" "jsr")
4326 (set_attr "length" "12,16")])
4328 ;; Call subroutine returning any type.
4330 (define_expand "untyped_call"
4331 [(parallel [(call (match_operand 0 "" "")
4333 (match_operand 1 "" "")
4334 (match_operand 2 "" "")])]
4340 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4342 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4344 rtx set = XVECEXP (operands[2], 0, i);
4345 emit_move_insn (SET_DEST (set), SET_SRC (set));
4348 /* The optimizer does not know that the call sets the function value
4349 registers we stored in the result block. We avoid problems by
4350 claiming that all hard registers are used and clobbered at this
4352 emit_insn (gen_blockage ());
4357 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4358 ;; all of memory. This blocks insns from being moved across this point.
4360 (define_insn "blockage"
4361 [(unspec_volatile [(const_int 0)] 1)]
4364 [(set_attr "length" "0")])
4368 (label_ref (match_operand 0 "" "")))]
4371 [(set_attr "type" "ibr")])
4373 (define_expand "return"
4378 (define_insn "*return_internal"
4382 [(set_attr "type" "ibr")])
4384 (define_insn "indirect_jump"
4385 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4388 [(set_attr "type" "ibr")])
4390 (define_expand "tablejump"
4391 [(use (match_operand:SI 0 "register_operand" ""))
4392 (use (match_operand:SI 1 "" ""))]
4396 if (TARGET_WINDOWS_NT)
4397 emit_jump_insn (gen_tablejump_nt (operands[0], operands[1]));
4398 else if (TARGET_OPEN_VMS)
4399 emit_jump_insn (gen_tablejump_vms (operands[0], operands[1]));
4401 emit_jump_insn (gen_tablejump_osf (operands[0], operands[1]));
4406 (define_expand "tablejump_osf"
4408 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
4409 (parallel [(set (pc)
4410 (plus:DI (match_dup 3)
4411 (label_ref (match_operand 1 "" ""))))
4412 (clobber (match_scratch:DI 2 "=r"))])]
4415 { operands[3] = gen_reg_rtx (DImode); }")
4417 (define_expand "tablejump_nt"
4419 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
4420 (parallel [(set (pc)
4422 (use (label_ref (match_operand 1 "" "")))])]
4425 { operands[3] = gen_reg_rtx (DImode); }")
4428 ;; tablejump, openVMS way
4430 ;; op 1: label preceding jump-table
4432 (define_expand "tablejump_vms"
4434 (match_operand:DI 0 "register_operand" ""))
4436 (plus:DI (match_dup 2)
4437 (label_ref (match_operand 1 "" ""))))]
4440 { operands[2] = gen_reg_rtx (DImode); }")
4442 (define_insn "*tablejump_osf_internal"
4444 (plus (match_operand:DI 0 "register_operand" "r")
4445 (label_ref (match_operand 1 "" ""))))
4446 (clobber (match_scratch:DI 2 "=r"))]
4447 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && next_active_insn (insn) != 0
4448 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
4449 && PREV_INSN (next_active_insn (insn)) == operands[1]"
4451 { rtx best_label = 0;
4452 rtx jump_table_insn = next_active_insn (operands[1]);
4454 if (GET_CODE (jump_table_insn) == JUMP_INSN
4455 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
4457 rtx jump_table = PATTERN (jump_table_insn);
4458 int n_labels = XVECLEN (jump_table, 1);
4459 int best_count = -1;
4462 for (i = 0; i < n_labels; i++)
4466 for (j = i + 1; j < n_labels; j++)
4467 if (XEXP (XVECEXP (jump_table, 1, i), 0)
4468 == XEXP (XVECEXP (jump_table, 1, j), 0))
4471 if (count > best_count)
4472 best_count = count, best_label = XVECEXP (jump_table, 1, i);
4478 operands[3] = best_label;
4479 return \"addq %0,$29,%2\;jmp $31,(%2),%3\";
4482 return \"addq %0,$29,%2\;jmp $31,(%2),0\";
4484 [(set_attr "type" "ibr")
4485 (set_attr "length" "8")])
4487 (define_insn "*tablejump_nt_internal"
4489 (match_operand:DI 0 "register_operand" "r"))
4490 (use (label_ref (match_operand 1 "" "")))]
4491 "TARGET_WINDOWS_NT && next_active_insn (insn) != 0
4492 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
4493 && PREV_INSN (next_active_insn (insn)) == operands[1]"
4495 { rtx best_label = 0;
4496 rtx jump_table_insn = next_active_insn (operands[1]);
4498 if (GET_CODE (jump_table_insn) == JUMP_INSN
4499 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
4501 rtx jump_table = PATTERN (jump_table_insn);
4502 int n_labels = XVECLEN (jump_table, 1);
4503 int best_count = -1;
4506 for (i = 0; i < n_labels; i++)
4510 for (j = i + 1; j < n_labels; j++)
4511 if (XEXP (XVECEXP (jump_table, 1, i), 0)
4512 == XEXP (XVECEXP (jump_table, 1, j), 0))
4515 if (count > best_count)
4516 best_count = count, best_label = XVECEXP (jump_table, 1, i);
4522 operands[2] = best_label;
4523 return \"jmp $31,(%0),%2\";
4526 return \"jmp $31,(%0),0\";
4528 [(set_attr "type" "ibr")])
4531 ;; op 0 is table offset
4532 ;; op 1 is table label
4535 (define_insn "*tablejump_vms_internal"
4537 (plus (match_operand:DI 0 "register_operand" "r")
4538 (label_ref (match_operand 1 "" ""))))]
4541 [(set_attr "type" "ibr")])
4543 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4544 ;; want to have to include pal.h in our .s file.
4546 ;; Technically the type for call_pal is jsr, but we use that for determining
4547 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
4550 [(unspec_volatile [(const_int 0)] 0)]
4553 [(set_attr "type" "ibr")])
4555 ;; Finally, we have the basic data motion insns. The byte and word insns
4556 ;; are done via define_expand. Start with the floating-point insns, since
4557 ;; they are simpler.
4559 (define_insn "*movsf_nofix"
4560 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4561 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4562 "TARGET_FPREGS && ! TARGET_FIX
4563 && (register_operand (operands[0], SFmode)
4564 || reg_or_fp0_operand (operands[1], SFmode))"
4572 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4574 (define_insn "*movsf_fix"
4575 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4576 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4577 "TARGET_FPREGS && TARGET_FIX
4578 && (register_operand (operands[0], SFmode)
4579 || reg_or_fp0_operand (operands[1], SFmode))"
4589 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4591 (define_insn "*movsf_nofp"
4592 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
4593 (match_operand:SF 1 "input_operand" "rG,m,r"))]
4595 && (register_operand (operands[0], SFmode)
4596 || reg_or_fp0_operand (operands[1], SFmode))"
4601 [(set_attr "type" "ilog,ild,ist")])
4603 (define_insn "*movdf_nofix"
4604 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4605 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4606 "TARGET_FPREGS && ! TARGET_FIX
4607 && (register_operand (operands[0], DFmode)
4608 || reg_or_fp0_operand (operands[1], DFmode))"
4616 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4618 (define_insn "*movdf_fix"
4619 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4620 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4621 "TARGET_FPREGS && TARGET_FIX
4622 && (register_operand (operands[0], DFmode)
4623 || reg_or_fp0_operand (operands[1], DFmode))"
4633 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4635 (define_insn "*movdf_nofp"
4636 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
4637 (match_operand:DF 1 "input_operand" "rG,m,r"))]
4639 && (register_operand (operands[0], DFmode)
4640 || reg_or_fp0_operand (operands[1], DFmode))"
4645 [(set_attr "type" "ilog,ild,ist")])
4647 ;; Subregs suck for register allocation. Pretend we can move TFmode
4648 ;; data between general registers until after reload.
4650 (define_insn_and_split "*movtf_internal"
4651 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
4652 (match_operand:TF 1 "input_operand" "roG,rG"))]
4653 "register_operand (operands[0], TFmode)
4654 || reg_or_fp0_operand (operands[1], TFmode)"
4657 [(set (match_dup 0) (match_dup 2))
4658 (set (match_dup 1) (match_dup 3))]
4661 alpha_split_tfmode_pair (operands);
4662 if (rtx_equal_p (operands[0], operands[3]))
4665 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
4666 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
4670 (define_expand "movsf"
4671 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4672 (match_operand:SF 1 "general_operand" ""))]
4676 if (GET_CODE (operands[0]) == MEM
4677 && ! reg_or_fp0_operand (operands[1], SFmode))
4678 operands[1] = force_reg (SFmode, operands[1]);
4681 (define_expand "movdf"
4682 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4683 (match_operand:DF 1 "general_operand" ""))]
4687 if (GET_CODE (operands[0]) == MEM
4688 && ! reg_or_fp0_operand (operands[1], DFmode))
4689 operands[1] = force_reg (DFmode, operands[1]);
4692 (define_expand "movtf"
4693 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4694 (match_operand:TF 1 "general_operand" ""))]
4698 if (GET_CODE (operands[0]) == MEM
4699 && ! reg_or_fp0_operand (operands[1], TFmode))
4700 operands[1] = force_reg (TFmode, operands[1]);
4703 (define_insn "*movsi_nofix"
4704 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
4705 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
4706 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && ! TARGET_FIX
4707 && (register_operand (operands[0], SImode)
4708 || reg_or_0_operand (operands[1], SImode))"
4718 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
4720 (define_insn "*movsf_fix"
4721 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
4722 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
4723 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && TARGET_FIX
4724 && (register_operand (operands[0], SImode)
4725 || reg_or_0_operand (operands[1], SImode))"
4737 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
4739 (define_insn "*movsi_nt_vms"
4740 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
4741 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
4742 "(TARGET_WINDOWS_NT || TARGET_OPEN_VMS)
4743 && (register_operand (operands[0], SImode)
4744 || reg_or_0_operand (operands[1], SImode))"
4755 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4757 (define_insn "*movhi_nobwx"
4758 [(set (match_operand:HI 0 "register_operand" "=r,r")
4759 (match_operand:HI 1 "input_operand" "rJ,n"))]
4761 && (register_operand (operands[0], HImode)
4762 || register_operand (operands[1], HImode))"
4766 [(set_attr "type" "ilog,iadd")])
4768 (define_insn "*movhi_bwx"
4769 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
4770 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
4772 && (register_operand (operands[0], HImode)
4773 || reg_or_0_operand (operands[1], HImode))"
4779 [(set_attr "type" "ilog,iadd,ild,ist")])
4781 (define_insn "*movqi_nobwx"
4782 [(set (match_operand:QI 0 "register_operand" "=r,r")
4783 (match_operand:QI 1 "input_operand" "rJ,n"))]
4785 && (register_operand (operands[0], QImode)
4786 || register_operand (operands[1], QImode))"
4790 [(set_attr "type" "ilog,iadd")])
4792 (define_insn "*movqi_bwx"
4793 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
4794 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
4796 && (register_operand (operands[0], QImode)
4797 || reg_or_0_operand (operands[1], QImode))"
4803 [(set_attr "type" "ilog,iadd,ild,ist")])
4805 ;; We do two major things here: handle mem->mem and construct long
4808 (define_expand "movsi"
4809 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4810 (match_operand:SI 1 "general_operand" ""))]
4814 if (GET_CODE (operands[0]) == MEM
4815 && ! reg_or_0_operand (operands[1], SImode))
4816 operands[1] = force_reg (SImode, operands[1]);
4818 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
4820 else if (GET_CODE (operands[1]) == CONST_INT)
4823 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 3);
4824 if (rtx_equal_p (operands[0], operands[1]))
4829 ;; Split a load of a large constant into the appropriate two-insn
4833 [(set (match_operand:SI 0 "register_operand" "")
4834 (match_operand:SI 1 "const_int_operand" ""))]
4835 "! add_operand (operands[1], SImode)"
4836 [(set (match_dup 0) (match_dup 2))
4837 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
4840 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
4842 if (tem == operands[0])
4848 (define_insn "*movdi_nofix"
4849 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q")
4850 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f"))]
4852 && (register_operand (operands[0], DImode)
4853 || reg_or_0_operand (operands[1], DImode))"
4864 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4866 (define_insn "*movdi_fix"
4867 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
4868 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
4870 && (register_operand (operands[0], DImode)
4871 || reg_or_0_operand (operands[1], DImode))"
4884 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
4886 ;; We do three major things here: handle mem->mem, put 64-bit constants in
4887 ;; memory, and construct long 32-bit constants.
4889 (define_expand "movdi"
4890 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4891 (match_operand:DI 1 "general_operand" ""))]
4897 if (GET_CODE (operands[0]) == MEM
4898 && ! reg_or_0_operand (operands[1], DImode))
4899 operands[1] = force_reg (DImode, operands[1]);
4901 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
4903 else if (GET_CODE (operands[1]) == CONST_INT
4904 && (tem = alpha_emit_set_const (operands[0], DImode,
4905 INTVAL (operands[1]), 3)) != 0)
4907 if (rtx_equal_p (tem, operands[0]))
4912 else if (CONSTANT_P (operands[1]))
4914 if (TARGET_BUILD_CONSTANTS)
4916 HOST_WIDE_INT i0, i1;
4918 if (GET_CODE (operands[1]) == CONST_INT)
4920 i0 = INTVAL (operands[1]);
4923 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
4925 #if HOST_BITS_PER_WIDE_INT >= 64
4926 i0 = CONST_DOUBLE_LOW (operands[1]);
4929 i0 = CONST_DOUBLE_LOW (operands[1]);
4930 i1 = CONST_DOUBLE_HIGH (operands[1]);
4936 tem = alpha_emit_set_long_const (operands[0], i0, i1);
4937 if (rtx_equal_p (tem, operands[0]))
4944 operands[1] = force_const_mem (DImode, operands[1]);
4945 if (reload_in_progress)
4947 emit_move_insn (operands[0], XEXP (operands[1], 0));
4948 operands[1] = copy_rtx (operands[1]);
4949 XEXP (operands[1], 0) = operands[0];
4952 operands[1] = validize_mem (operands[1]);
4959 ;; Split a load of a large constant into the appropriate two-insn
4963 [(set (match_operand:DI 0 "register_operand" "")
4964 (match_operand:DI 1 "const_int_operand" ""))]
4965 "! add_operand (operands[1], DImode)"
4966 [(set (match_dup 0) (match_dup 2))
4967 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
4970 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
4972 if (tem == operands[0])
4978 ;; These are the partial-word cases.
4980 ;; First we have the code to load an aligned word. Operand 0 is the register
4981 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
4982 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
4983 ;; number of bits within the word that the value is. Operand 3 is an SImode
4984 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
4985 ;; same register. It is allowed to conflict with operand 1 as well.
4987 (define_expand "aligned_loadqi"
4988 [(set (match_operand:SI 3 "register_operand" "")
4989 (match_operand:SI 1 "memory_operand" ""))
4990 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4991 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4993 (match_operand:DI 2 "const_int_operand" "")))]
4998 (define_expand "aligned_loadhi"
4999 [(set (match_operand:SI 3 "register_operand" "")
5000 (match_operand:SI 1 "memory_operand" ""))
5001 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
5002 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5004 (match_operand:DI 2 "const_int_operand" "")))]
5009 ;; Similar for unaligned loads, where we use the sequence from the
5010 ;; Alpha Architecture manual.
5012 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5013 ;; operand 3 can overlap the input and output registers.
5015 (define_expand "unaligned_loadqi"
5016 [(set (match_operand:DI 2 "register_operand" "")
5017 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5019 (set (match_operand:DI 3 "register_operand" "")
5021 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5022 (zero_extract:DI (match_dup 2)
5024 (ashift:DI (match_dup 3) (const_int 3))))]
5028 (define_expand "unaligned_loadhi"
5029 [(set (match_operand:DI 2 "register_operand" "")
5030 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5032 (set (match_operand:DI 3 "register_operand" "")
5034 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5035 (zero_extract:DI (match_dup 2)
5037 (ashift:DI (match_dup 3) (const_int 3))))]
5041 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5042 ;; aligned SImode MEM. Operand 1 is the register containing the
5043 ;; byte or word to store. Operand 2 is the number of bits within the word that
5044 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5046 (define_expand "aligned_store"
5047 [(set (match_operand:SI 3 "register_operand" "")
5048 (match_operand:SI 0 "memory_operand" ""))
5049 (set (subreg:DI (match_dup 3) 0)
5050 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5051 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5052 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5053 (match_operand:DI 2 "const_int_operand" "")))
5054 (set (subreg:DI (match_dup 4) 0)
5055 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5056 (set (match_dup 0) (match_dup 4))]
5059 { operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5060 << INTVAL (operands[2])));
5063 ;; For the unaligned byte and halfword cases, we use code similar to that
5064 ;; in the ;; Architecture book, but reordered to lower the number of registers
5065 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5066 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5067 ;; be the same temporary, if desired. If the address is in a register,
5068 ;; operand 2 can be that register.
5070 (define_expand "unaligned_storeqi"
5071 [(set (match_operand:DI 3 "register_operand" "")
5072 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5074 (set (match_operand:DI 2 "register_operand" "")
5077 (and:DI (not:DI (ashift:DI (const_int 255)
5078 (ashift:DI (match_dup 2) (const_int 3))))
5080 (set (match_operand:DI 4 "register_operand" "")
5081 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5082 (ashift:DI (match_dup 2) (const_int 3))))
5083 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5084 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5089 (define_expand "unaligned_storehi"
5090 [(set (match_operand:DI 3 "register_operand" "")
5091 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5093 (set (match_operand:DI 2 "register_operand" "")
5096 (and:DI (not:DI (ashift:DI (const_int 65535)
5097 (ashift:DI (match_dup 2) (const_int 3))))
5099 (set (match_operand:DI 4 "register_operand" "")
5100 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5101 (ashift:DI (match_dup 2) (const_int 3))))
5102 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5103 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5108 ;; Here are the define_expand's for QI and HI moves that use the above
5109 ;; patterns. We have the normal sets, plus the ones that need scratch
5110 ;; registers for reload.
5112 (define_expand "movqi"
5113 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5114 (match_operand:QI 1 "general_operand" ""))]
5120 if (GET_CODE (operands[0]) == MEM
5121 && ! reg_or_0_operand (operands[1], QImode))
5122 operands[1] = force_reg (QImode, operands[1]);
5124 if (GET_CODE (operands[1]) == CONST_INT
5125 && ! input_operand (operands[1], QImode))
5127 operands[1] = alpha_emit_set_const (operands[0], QImode,
5128 INTVAL (operands[1]), 3);
5130 if (rtx_equal_p (operands[0], operands[1]))
5137 /* If the output is not a register, the input must be. */
5138 if (GET_CODE (operands[0]) == MEM)
5139 operands[1] = force_reg (QImode, operands[1]);
5141 /* Handle four memory cases, unaligned and aligned for either the input
5142 or the output. The only case where we can be called during reload is
5143 for aligned loads; all other cases require temporaries. */
5145 if (GET_CODE (operands[1]) == MEM
5146 || (GET_CODE (operands[1]) == SUBREG
5147 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
5148 || (reload_in_progress && GET_CODE (operands[1]) == REG
5149 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
5150 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
5151 && GET_CODE (SUBREG_REG (operands[1])) == REG
5152 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
5154 if (aligned_memory_operand (operands[1], QImode))
5156 if (reload_in_progress)
5158 emit_insn (gen_reload_inqi_help
5159 (operands[0], operands[1],
5160 gen_rtx_REG (SImode, REGNO (operands[0]))));
5164 rtx aligned_mem, bitnum;
5165 rtx scratch = gen_reg_rtx (SImode);
5167 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5169 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
5175 /* Don't pass these as parameters since that makes the generated
5176 code depend on parameter evaluation order which will cause
5177 bootstrap failures. */
5179 rtx temp1 = gen_reg_rtx (DImode);
5180 rtx temp2 = gen_reg_rtx (DImode);
5182 = gen_unaligned_loadqi (operands[0],
5183 get_unaligned_address (operands[1], 0),
5186 alpha_set_memflags (seq, operands[1]);
5193 else if (GET_CODE (operands[0]) == MEM
5194 || (GET_CODE (operands[0]) == SUBREG
5195 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
5196 || (reload_in_progress && GET_CODE (operands[0]) == REG
5197 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
5198 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
5199 && GET_CODE (SUBREG_REG (operands[0])) == REG
5200 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
5202 if (aligned_memory_operand (operands[0], QImode))
5204 rtx aligned_mem, bitnum;
5205 rtx temp1 = gen_reg_rtx (SImode);
5206 rtx temp2 = gen_reg_rtx (SImode);
5208 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5210 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5215 rtx temp1 = gen_reg_rtx (DImode);
5216 rtx temp2 = gen_reg_rtx (DImode);
5217 rtx temp3 = gen_reg_rtx (DImode);
5219 = gen_unaligned_storeqi (get_unaligned_address (operands[0], 0),
5220 operands[1], temp1, temp2, temp3);
5222 alpha_set_memflags (seq, operands[0]);
5230 (define_expand "movhi"
5231 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5232 (match_operand:HI 1 "general_operand" ""))]
5238 if (GET_CODE (operands[0]) == MEM
5239 && ! reg_or_0_operand (operands[1], HImode))
5240 operands[1] = force_reg (HImode, operands[1]);
5242 if (GET_CODE (operands[1]) == CONST_INT
5243 && ! input_operand (operands[1], HImode))
5245 operands[1] = alpha_emit_set_const (operands[0], HImode,
5246 INTVAL (operands[1]), 3);
5248 if (rtx_equal_p (operands[0], operands[1]))
5255 /* If the output is not a register, the input must be. */
5256 if (GET_CODE (operands[0]) == MEM)
5257 operands[1] = force_reg (HImode, operands[1]);
5259 /* Handle four memory cases, unaligned and aligned for either the input
5260 or the output. The only case where we can be called during reload is
5261 for aligned loads; all other cases require temporaries. */
5263 if (GET_CODE (operands[1]) == MEM
5264 || (GET_CODE (operands[1]) == SUBREG
5265 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
5266 || (reload_in_progress && GET_CODE (operands[1]) == REG
5267 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
5268 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
5269 && GET_CODE (SUBREG_REG (operands[1])) == REG
5270 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
5272 if (aligned_memory_operand (operands[1], HImode))
5274 if (reload_in_progress)
5276 emit_insn (gen_reload_inhi_help
5277 (operands[0], operands[1],
5278 gen_rtx_REG (SImode, REGNO (operands[0]))));
5282 rtx aligned_mem, bitnum;
5283 rtx scratch = gen_reg_rtx (SImode);
5285 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5287 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
5293 /* Don't pass these as parameters since that makes the generated
5294 code depend on parameter evaluation order which will cause
5295 bootstrap failures. */
5297 rtx temp1 = gen_reg_rtx (DImode);
5298 rtx temp2 = gen_reg_rtx (DImode);
5300 = gen_unaligned_loadhi (operands[0],
5301 get_unaligned_address (operands[1], 0),
5304 alpha_set_memflags (seq, operands[1]);
5311 else if (GET_CODE (operands[0]) == MEM
5312 || (GET_CODE (operands[0]) == SUBREG
5313 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
5314 || (reload_in_progress && GET_CODE (operands[0]) == REG
5315 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
5316 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
5317 && GET_CODE (SUBREG_REG (operands[0])) == REG
5318 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
5320 if (aligned_memory_operand (operands[0], HImode))
5322 rtx aligned_mem, bitnum;
5323 rtx temp1 = gen_reg_rtx (SImode);
5324 rtx temp2 = gen_reg_rtx (SImode);
5326 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5328 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5333 rtx temp1 = gen_reg_rtx (DImode);
5334 rtx temp2 = gen_reg_rtx (DImode);
5335 rtx temp3 = gen_reg_rtx (DImode);
5337 = gen_unaligned_storehi (get_unaligned_address (operands[0], 0),
5338 operands[1], temp1, temp2, temp3);
5340 alpha_set_memflags (seq, operands[0]);
5349 ;; Here are the versions for reload. Note that in the unaligned cases
5350 ;; we know that the operand must not be a pseudo-register because stack
5351 ;; slots are always aligned references.
5353 (define_expand "reload_inqi"
5354 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5355 (match_operand:QI 1 "any_memory_operand" "m")
5356 (match_operand:TI 2 "register_operand" "=&r")])]
5362 if (GET_CODE (operands[1]) != MEM)
5365 if (aligned_memory_operand (operands[1], QImode))
5367 seq = gen_reload_inqi_help (operands[0], operands[1],
5368 gen_rtx_REG (SImode, REGNO (operands[2])));
5374 /* It is possible that one of the registers we got for operands[2]
5375 might coincide with that of operands[0] (which is why we made
5376 it TImode). Pick the other one to use as our scratch. */
5377 if (REGNO (operands[0]) == REGNO (operands[2]))
5378 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5380 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5382 addr = get_unaligned_address (operands[1], 0);
5383 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
5384 gen_rtx_REG (DImode, REGNO (operands[0])));
5385 alpha_set_memflags (seq, operands[1]);
5391 (define_expand "reload_inhi"
5392 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5393 (match_operand:HI 1 "any_memory_operand" "m")
5394 (match_operand:TI 2 "register_operand" "=&r")])]
5400 if (GET_CODE (operands[1]) != MEM)
5403 if (aligned_memory_operand (operands[1], HImode))
5405 seq = gen_reload_inhi_help (operands[0], operands[1],
5406 gen_rtx_REG (SImode, REGNO (operands[2])));
5412 /* It is possible that one of the registers we got for operands[2]
5413 might coincide with that of operands[0] (which is why we made
5414 it TImode). Pick the other one to use as our scratch. */
5415 if (REGNO (operands[0]) == REGNO (operands[2]))
5416 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5418 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5420 addr = get_unaligned_address (operands[1], 0);
5421 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
5422 gen_rtx_REG (DImode, REGNO (operands[0])));
5423 alpha_set_memflags (seq, operands[1]);
5429 (define_expand "reload_outqi"
5430 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
5431 (match_operand:QI 1 "register_operand" "r")
5432 (match_operand:TI 2 "register_operand" "=&r")])]
5436 if (GET_CODE (operands[0]) != MEM)
5439 if (aligned_memory_operand (operands[0], QImode))
5441 emit_insn (gen_reload_outqi_help
5442 (operands[0], operands[1],
5443 gen_rtx_REG (SImode, REGNO (operands[2])),
5444 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5448 rtx addr = get_unaligned_address (operands[0], 0);
5449 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5450 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5451 rtx scratch3 = scratch1;
5454 if (GET_CODE (addr) == REG)
5457 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
5458 scratch2, scratch3);
5459 alpha_set_memflags (seq, operands[0]);
5465 (define_expand "reload_outhi"
5466 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
5467 (match_operand:HI 1 "register_operand" "r")
5468 (match_operand:TI 2 "register_operand" "=&r")])]
5472 if (GET_CODE (operands[0]) != MEM)
5475 if (aligned_memory_operand (operands[0], HImode))
5477 emit_insn (gen_reload_outhi_help
5478 (operands[0], operands[1],
5479 gen_rtx_REG (SImode, REGNO (operands[2])),
5480 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5484 rtx addr = get_unaligned_address (operands[0], 0);
5485 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5486 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5487 rtx scratch3 = scratch1;
5490 if (GET_CODE (addr) == REG)
5493 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
5494 scratch2, scratch3);
5495 alpha_set_memflags (seq, operands[0]);
5501 ;; Helpers for the above. The way reload is structured, we can't
5502 ;; always get a proper address for a stack slot during reload_foo
5503 ;; expansion, so we must delay our address manipulations until after.
5505 (define_insn "reload_inqi_help"
5506 [(set (match_operand:QI 0 "register_operand" "=r")
5507 (match_operand:QI 1 "memory_operand" "m"))
5508 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5509 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5512 (define_insn "reload_inhi_help"
5513 [(set (match_operand:HI 0 "register_operand" "=r")
5514 (match_operand:HI 1 "memory_operand" "m"))
5515 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5516 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5519 (define_insn "reload_outqi_help"
5520 [(set (match_operand:QI 0 "memory_operand" "=m")
5521 (match_operand:QI 1 "register_operand" "r"))
5522 (clobber (match_operand:SI 2 "register_operand" "=r"))
5523 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5524 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5527 (define_insn "reload_outhi_help"
5528 [(set (match_operand:HI 0 "memory_operand" "=m")
5529 (match_operand:HI 1 "register_operand" "r"))
5530 (clobber (match_operand:SI 2 "register_operand" "=r"))
5531 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5532 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5536 [(set (match_operand:QI 0 "register_operand" "")
5537 (match_operand:QI 1 "memory_operand" ""))
5538 (clobber (match_operand:SI 2 "register_operand" ""))]
5539 "! TARGET_BWX && reload_completed"
5543 rtx aligned_mem, bitnum;
5544 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5545 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
5551 [(set (match_operand:HI 0 "register_operand" "")
5552 (match_operand:HI 1 "memory_operand" ""))
5553 (clobber (match_operand:SI 2 "register_operand" ""))]
5554 "! TARGET_BWX && reload_completed"
5558 rtx aligned_mem, bitnum;
5559 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5560 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
5566 [(set (match_operand:QI 0 "memory_operand" "")
5567 (match_operand:QI 1 "register_operand" ""))
5568 (clobber (match_operand:SI 2 "register_operand" ""))
5569 (clobber (match_operand:SI 3 "register_operand" ""))]
5570 "! TARGET_BWX && reload_completed"
5574 rtx aligned_mem, bitnum;
5575 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5576 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5577 operands[2], operands[3]));
5582 [(set (match_operand:HI 0 "memory_operand" "")
5583 (match_operand:HI 1 "register_operand" ""))
5584 (clobber (match_operand:SI 2 "register_operand" ""))
5585 (clobber (match_operand:SI 3 "register_operand" ""))]
5586 "! TARGET_BWX && reload_completed"
5590 rtx aligned_mem, bitnum;
5591 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5592 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5593 operands[2], operands[3]));
5597 ;; Bit field extract patterns which use ext[wlq][lh]
5599 (define_expand "extv"
5600 [(set (match_operand:DI 0 "register_operand" "")
5601 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
5602 (match_operand:DI 2 "immediate_operand" "")
5603 (match_operand:DI 3 "immediate_operand" "")))]
5607 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5608 if (INTVAL (operands[3]) % 8 != 0
5609 || (INTVAL (operands[2]) != 16
5610 && INTVAL (operands[2]) != 32
5611 && INTVAL (operands[2]) != 64))
5614 /* From mips.md: extract_bit_field doesn't verify that our source
5615 matches the predicate, so we force it to be a MEM here. */
5616 if (GET_CODE (operands[1]) != MEM)
5619 alpha_expand_unaligned_load (operands[0], operands[1],
5620 INTVAL (operands[2]) / 8,
5621 INTVAL (operands[3]) / 8, 1);
5625 (define_expand "extzv"
5626 [(set (match_operand:DI 0 "register_operand" "")
5627 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
5628 (match_operand:DI 2 "immediate_operand" "")
5629 (match_operand:DI 3 "immediate_operand" "")))]
5633 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5634 if (INTVAL (operands[3]) % 8 != 0
5635 || (INTVAL (operands[2]) != 8
5636 && INTVAL (operands[2]) != 16
5637 && INTVAL (operands[2]) != 32
5638 && INTVAL (operands[2]) != 64))
5641 if (GET_CODE (operands[1]) == MEM)
5643 /* Fail 8 bit fields, falling back on a simple byte load. */
5644 if (INTVAL (operands[2]) == 8)
5647 alpha_expand_unaligned_load (operands[0], operands[1],
5648 INTVAL (operands[2]) / 8,
5649 INTVAL (operands[3]) / 8, 0);
5654 (define_expand "insv"
5655 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
5656 (match_operand:DI 1 "immediate_operand" "")
5657 (match_operand:DI 2 "immediate_operand" ""))
5658 (match_operand:DI 3 "register_operand" ""))]
5662 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5663 if (INTVAL (operands[2]) % 8 != 0
5664 || (INTVAL (operands[1]) != 16
5665 && INTVAL (operands[1]) != 32
5666 && INTVAL (operands[1]) != 64))
5669 /* From mips.md: store_bit_field doesn't verify that our source
5670 matches the predicate, so we force it to be a MEM here. */
5671 if (GET_CODE (operands[0]) != MEM)
5674 alpha_expand_unaligned_store (operands[0], operands[3],
5675 INTVAL (operands[1]) / 8,
5676 INTVAL (operands[2]) / 8);
5680 ;; Block move/clear, see alpha.c for more details.
5681 ;; Argument 0 is the destination
5682 ;; Argument 1 is the source
5683 ;; Argument 2 is the length
5684 ;; Argument 3 is the alignment
5686 (define_expand "movstrqi"
5687 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
5688 (match_operand:BLK 1 "memory_operand" ""))
5689 (use (match_operand:DI 2 "immediate_operand" ""))
5690 (use (match_operand:DI 3 "immediate_operand" ""))])]
5694 if (alpha_expand_block_move (operands))
5700 (define_expand "clrstrqi"
5701 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
5703 (use (match_operand:DI 1 "immediate_operand" ""))
5704 (use (match_operand:DI 2 "immediate_operand" ""))])]
5708 if (alpha_expand_block_clear (operands))
5714 ;; Subroutine of stack space allocation. Perform a stack probe.
5715 (define_expand "probe_stack"
5716 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
5720 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
5721 INTVAL (operands[0])));
5722 MEM_VOLATILE_P (operands[1]) = 1;
5724 operands[0] = const0_rtx;
5727 ;; This is how we allocate stack space. If we are allocating a
5728 ;; constant amount of space and we know it is less than 4096
5729 ;; bytes, we need do nothing.
5731 ;; If it is more than 4096 bytes, we need to probe the stack
5733 (define_expand "allocate_stack"
5735 (plus:DI (reg:DI 30)
5736 (match_operand:DI 1 "reg_or_cint_operand" "")))
5737 (set (match_operand:DI 0 "register_operand" "=r")
5742 if (GET_CODE (operands[1]) == CONST_INT
5743 && INTVAL (operands[1]) < 32768)
5745 if (INTVAL (operands[1]) >= 4096)
5747 /* We do this the same way as in the prologue and generate explicit
5748 probes. Then we update the stack by the constant. */
5752 emit_insn (gen_probe_stack (GEN_INT (- probed)));
5753 while (probed + 8192 < INTVAL (operands[1]))
5754 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
5756 if (probed + 4096 < INTVAL (operands[1]))
5757 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
5760 operands[1] = GEN_INT (- INTVAL (operands[1]));
5761 operands[2] = virtual_stack_dynamic_rtx;
5766 rtx loop_label = gen_label_rtx ();
5767 rtx want = gen_reg_rtx (Pmode);
5768 rtx tmp = gen_reg_rtx (Pmode);
5771 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
5772 force_reg (Pmode, operands[1])));
5773 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
5775 if (GET_CODE (operands[1]) != CONST_INT)
5777 out_label = gen_label_rtx ();
5778 emit_insn (gen_cmpdi (want, tmp));
5779 emit_jump_insn (gen_bgeu (out_label));
5782 emit_label (loop_label);
5783 memref = gen_rtx_MEM (DImode, tmp);
5784 MEM_VOLATILE_P (memref) = 1;
5785 emit_move_insn (memref, const0_rtx);
5786 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
5787 emit_insn (gen_cmpdi (tmp, want));
5788 emit_jump_insn (gen_bgtu (loop_label));
5790 memref = gen_rtx_MEM (DImode, want);
5791 MEM_VOLATILE_P (memref) = 1;
5792 emit_move_insn (memref, const0_rtx);
5795 emit_label (out_label);
5797 emit_move_insn (stack_pointer_rtx, want);
5798 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
5803 ;; This is used by alpha_expand_prolog to do the same thing as above,
5804 ;; except we cannot at that time generate new basic blocks, so we hide
5805 ;; the loop in this one insn.
5807 (define_insn "prologue_stack_probe_loop"
5808 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
5809 (match_operand:DI 1 "register_operand" "r")] 5)]
5813 operands[2] = gen_label_rtx ();
5814 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5815 CODE_LABEL_NUMBER (operands[2]));
5817 return \"stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2\";
5819 [(set_attr "length" "16")
5820 (set_attr "type" "multi")])
5822 (define_expand "prologue"
5823 [(clobber (const_int 0))]
5827 alpha_expand_prologue ();
5831 ;; These take care of emitting the ldgp insn in the prologue. This will be
5832 ;; an lda/ldah pair and we want to align them properly. So we have two
5833 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
5834 ;; and the second of which emits nothing. However, both are marked as type
5835 ;; IADD (the default) so the alignment code in alpha.c does the right thing
5838 (define_expand "prologue_ldgp"
5839 [(unspec_volatile [(const_int 0)] 9)
5840 (unspec_volatile [(const_int 0)] 10)]
5844 (define_insn "*prologue_ldgp_1"
5845 [(unspec_volatile [(const_int 0)] 9)]
5846 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5847 "ldgp $29,0($27)\\n$%~..ng:")
5849 (define_insn "*prologue_ldgp_2"
5850 [(unspec_volatile [(const_int 0)] 10)]
5851 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5854 ;; The _mcount profiling hook has special calling conventions, and
5855 ;; does not clobber all the registers that a normal call would. So
5856 ;; hide the fact this is a call at all.
5858 (define_insn "prologue_mcount"
5859 [(unspec_volatile [(const_int 0)] 8)]
5861 "lda $28,_mcount\;jsr $28,($28),_mcount"
5862 [(set_attr "type" "multi")
5863 (set_attr "length" "8")])
5865 (define_insn "init_fp"
5866 [(set (match_operand:DI 0 "register_operand" "=r")
5867 (match_operand:DI 1 "register_operand" "r"))
5868 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
5872 (define_expand "epilogue"
5877 alpha_expand_epilogue ();
5880 (define_expand "sibcall_epilogue"
5882 "!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT"
5885 alpha_expand_epilogue ();
5889 (define_expand "eh_epilogue"
5890 [(use (match_operand:DI 0 "register_operand" "r"))
5891 (use (match_operand:DI 1 "register_operand" "r"))
5892 (use (match_operand:DI 2 "register_operand" "r"))]
5896 cfun->machine->eh_epilogue_sp_ofs = operands[1];
5897 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 26)
5899 rtx ra = gen_rtx_REG (Pmode, 26);
5900 emit_move_insn (ra, operands[2]);
5905 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
5906 ;; the frame size into a register. We use this pattern to ensure
5907 ;; we get lda instead of addq.
5908 (define_insn "nt_lda"
5909 [(set (match_operand:DI 0 "register_operand" "=r")
5910 (unspec:DI [(match_dup 0)
5911 (match_operand:DI 1 "const_int_operand" "n")] 6))]
5915 (define_expand "builtin_longjmp"
5916 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 3)]
5917 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5920 /* The elements of the buffer are, in order: */
5921 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5922 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
5923 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
5924 rtx pv = gen_rtx_REG (Pmode, 27);
5926 /* This bit is the same as expand_builtin_longjmp. */
5927 emit_move_insn (hard_frame_pointer_rtx, fp);
5928 emit_move_insn (pv, lab);
5929 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5930 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5931 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5933 /* Load the label we are jumping through into $27 so that we know
5934 where to look for it when we get back to setjmp's function for
5935 restoring the gp. */
5936 emit_indirect_jump (pv);
5940 (define_insn "*builtin_setjmp_receiver_sub_label"
5941 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
5942 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT && TARGET_AS_CAN_SUBTRACT_LABELS"
5943 "\\n$LSJ%=:\;ldgp $29,$LSJ%=-%l0($27)"
5944 [(set_attr "length" "8")
5945 (set_attr "type" "multi")])
5947 (define_insn "builtin_setjmp_receiver"
5948 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
5949 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5950 "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
5951 [(set_attr "length" "12")
5952 (set_attr "type" "multi")])
5954 (define_insn "exception_receiver"
5955 [(unspec_volatile [(const_int 0)] 7)]
5956 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5957 "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
5958 [(set_attr "length" "12")
5959 (set_attr "type" "multi")])
5961 (define_expand "nonlocal_goto_receiver"
5962 [(unspec_volatile [(const_int 0)] 1)
5963 (set (reg:DI 27) (mem:DI (reg:DI 29)))
5964 (unspec_volatile [(const_int 0)] 1)
5969 (define_insn "arg_home"
5970 [(unspec [(const_int 0)] 0)
5985 (clobber (mem:BLK (const_int 0)))
5986 (clobber (reg:DI 24))
5987 (clobber (reg:DI 25))
5988 (clobber (reg:DI 0))]
5990 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
5991 [(set_attr "length" "16")
5992 (set_attr "type" "multi")])
5994 ;; Close the trap shadow of preceeding instructions. This is generated
5997 (define_insn "trapb"
5998 [(unspec_volatile [(const_int 0)] 4)]
6001 [(set_attr "type" "misc")])
6003 ;; No-op instructions used by machine-dependant reorg to preserve
6004 ;; alignment for instruction issue.
6010 [(set_attr "type" "ilog")])
6016 [(set_attr "type" "fcpys")])
6023 (define_insn "realign"
6024 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")] 6)]
6026 ".align %0 #realign")
6028 ;; The call patterns are at the end of the file because their
6029 ;; wildcard operand0 interferes with nice recognition.
6031 (define_insn "*call_value_osf_1"
6032 [(set (match_operand 0 "" "")
6033 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,i"))
6034 (match_operand 2 "" "")))
6035 (clobber (reg:DI 27))
6036 (clobber (reg:DI 26))]
6037 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
6039 jsr $26,($27),0\;ldgp $29,0($26)
6041 jsr $26,%1\;ldgp $29,0($26)"
6042 [(set_attr "type" "jsr")
6043 (set_attr "length" "12,*,16")])
6045 (define_insn "*sibcall_value_osf_1"
6046 [(set (match_operand 0 "" "")
6047 (call (mem:DI (match_operand:DI 1 "call_operand" "R,i"))
6048 (match_operand 2 "" "")))]
6049 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
6053 [(set_attr "type" "jsr")
6054 (set_attr "length" "*,8")])
6056 (define_insn "*call_value_nt_1"
6057 [(set (match_operand 0 "" "")
6058 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
6059 (match_operand 2 "" "")))
6060 (clobber (reg:DI 26))]
6066 [(set_attr "type" "jsr")
6067 (set_attr "length" "*,*,12")])
6069 (define_insn "*call_value_vms_1"
6070 [(set (match_operand 0 "" "")
6071 (call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
6072 (match_operand 2 "" "")))
6073 (use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
6076 (clobber (reg:DI 27))]
6079 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
6080 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
6081 [(set_attr "type" "jsr")
6082 (set_attr "length" "12,16")])