1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
37 (UNSPEC_UMK_LOAD_CIW 9)
45 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
46 (UNSPECV_LONGJMP 3) ; builtin_longjmp
48 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
50 (UNSPECV_EHR 7) ; exception_receiver
54 (UNSPECV_FORCE_MOV 11)
57 ;; Where necessary, the suffixes _le and _be are used to distinguish between
58 ;; little-endian and big-endian patterns.
60 ;; Note that the Unicos/Mk assembler does not support the following
61 ;; opcodes: mov, fmov, nop, fnop, unop.
63 ;; Processor type -- this attribute must exactly match the processor_type
64 ;; enumeration in alpha.h.
66 (define_attr "cpu" "ev4,ev5,ev6"
67 (const (symbol_ref "alpha_cpu")))
69 ;; Define an insn type attribute. This is used in function unit delay
70 ;; computations, among other purposes. For the most part, we use the names
71 ;; defined in the EV4 documentation, but add a few that we have to know about
75 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,\
76 fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
77 (const_string "iadd"))
79 ;; Describe a user's asm statement.
80 (define_asm_attributes
81 [(set_attr "type" "multi")])
83 ;; Define the operand size an insn operates on. Used primarily by mul
84 ;; and div operations that have size dependant timings.
86 (define_attr "opsize" "si,di,udi"
89 ;; The TRAP attribute marks instructions that may generate traps
90 ;; (which are imprecise and may need a trapb if software completion
93 (define_attr "trap" "no,yes"
96 ;; The ROUND_SUFFIX attribute marks which instructions require a
97 ;; rounding-mode suffix. The value NONE indicates no suffix,
98 ;; the value NORMAL indicates a suffix controled by alpha_fprm.
100 (define_attr "round_suffix" "none,normal,c"
101 (const_string "none"))
103 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
105 ;; SU accepts only /su (cmpt et al)
106 ;; SUI accepts only /sui (cvtqt and cvtqs)
107 ;; V_SV accepts /v and /sv (cvtql only)
108 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
109 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
111 ;; The actual suffix emitted is controled by alpha_fptm.
113 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
114 (const_string "none"))
116 ;; The length of an instruction sequence in bytes.
118 (define_attr "length" ""
121 ;; On EV4 there are two classes of resources to consider: resources needed
122 ;; to issue, and resources needed to execute. IBUS[01] are in the first
123 ;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
124 ;; (There are a few other register-like resources, but ...)
126 ; First, describe all of the issue constraints with single cycle delays.
127 ; All insns need a bus, but all except loads require one or the other.
128 (define_function_unit "ev4_ibus0" 1 0
129 (and (eq_attr "cpu" "ev4")
130 (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
133 (define_function_unit "ev4_ibus1" 1 0
134 (and (eq_attr "cpu" "ev4")
135 (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
138 ; Memory delivers its result in three cycles. Actually return one and
139 ; take care of this in adjust_cost, since we want to handle user-defined
141 (define_function_unit "ev4_abox" 1 0
142 (and (eq_attr "cpu" "ev4")
143 (eq_attr "type" "ild,fld,ldsym,ist,fst"))
146 ; Branches have no delay cost, but do tie up the unit for two cycles.
147 (define_function_unit "ev4_bbox" 1 1
148 (and (eq_attr "cpu" "ev4")
149 (eq_attr "type" "ibr,fbr,jsr"))
152 ; Arithmetic insns are normally have their results available after
153 ; two cycles. There are a number of exceptions. They are encoded in
154 ; ADJUST_COST. Some of the other insns have similar exceptions.
155 (define_function_unit "ev4_ebox" 1 0
156 (and (eq_attr "cpu" "ev4")
157 (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
160 (define_function_unit "imul" 1 0
161 (and (eq_attr "cpu" "ev4")
162 (and (eq_attr "type" "imul")
163 (eq_attr "opsize" "si")))
166 (define_function_unit "imul" 1 0
167 (and (eq_attr "cpu" "ev4")
168 (and (eq_attr "type" "imul")
169 (eq_attr "opsize" "!si")))
172 (define_function_unit "ev4_fbox" 1 0
173 (and (eq_attr "cpu" "ev4")
174 (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
177 (define_function_unit "fdiv" 1 0
178 (and (eq_attr "cpu" "ev4")
179 (and (eq_attr "type" "fdiv")
180 (eq_attr "opsize" "si")))
183 (define_function_unit "fdiv" 1 0
184 (and (eq_attr "cpu" "ev4")
185 (and (eq_attr "type" "fdiv")
186 (eq_attr "opsize" "di")))
189 ;; EV5 scheduling. EV5 can issue 4 insns per clock.
191 ;; EV5 has two asymetric integer units. Model this with E0 & E1 along
192 ;; with the combined resource EBOX.
194 (define_function_unit "ev5_ebox" 2 0
195 (and (eq_attr "cpu" "ev5")
196 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
199 ; Memory takes at least 2 clocks. Return one from here and fix up with
200 ; user-defined latencies in adjust_cost.
201 (define_function_unit "ev5_ebox" 2 0
202 (and (eq_attr "cpu" "ev5")
203 (eq_attr "type" "ild,fld,ldsym"))
206 ; Loads can dual issue with one another, but loads and stores do not mix.
207 (define_function_unit "ev5_e0" 1 0
208 (and (eq_attr "cpu" "ev5")
209 (eq_attr "type" "ild,fld,ldsym"))
211 [(eq_attr "type" "ist,fst")])
213 ; Stores, shifts, multiplies can only issue to E0
214 (define_function_unit "ev5_e0" 1 0
215 (and (eq_attr "cpu" "ev5")
216 (eq_attr "type" "ist,fst,shift,imul"))
219 ; Motion video insns also issue only to E0, and take two ticks.
220 (define_function_unit "ev5_e0" 1 0
221 (and (eq_attr "cpu" "ev5")
222 (eq_attr "type" "mvi"))
225 ; Conditional moves always take 2 ticks.
226 (define_function_unit "ev5_ebox" 2 0
227 (and (eq_attr "cpu" "ev5")
228 (eq_attr "type" "icmov"))
231 ; Branches can only issue to E1
232 (define_function_unit "ev5_e1" 1 0
233 (and (eq_attr "cpu" "ev5")
234 (eq_attr "type" "ibr,jsr"))
237 ; Multiplies also use the integer multiplier.
238 ; ??? How to: "No instruction can be issued to pipe E0 exactly two
239 ; cycles before an integer multiplication completes."
240 (define_function_unit "imul" 1 0
241 (and (eq_attr "cpu" "ev5")
242 (and (eq_attr "type" "imul")
243 (eq_attr "opsize" "si")))
246 (define_function_unit "imul" 1 0
247 (and (eq_attr "cpu" "ev5")
248 (and (eq_attr "type" "imul")
249 (eq_attr "opsize" "di")))
252 (define_function_unit "imul" 1 0
253 (and (eq_attr "cpu" "ev5")
254 (and (eq_attr "type" "imul")
255 (eq_attr "opsize" "udi")))
258 ;; Similarly for the FPU we have two asymetric units. But fcpys can issue
259 ;; on either so we have to play the game again.
261 (define_function_unit "ev5_fbox" 2 0
262 (and (eq_attr "cpu" "ev5")
263 (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
266 (define_function_unit "ev5_fm" 1 0
267 (and (eq_attr "cpu" "ev5")
268 (eq_attr "type" "fmul"))
271 ; Add and cmov as you would expect; fbr never produces a result;
272 ; fdiv issues through fa to the divider,
273 (define_function_unit "ev5_fa" 1 0
274 (and (eq_attr "cpu" "ev5")
275 (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
278 ; ??? How to: "No instruction can be issued to pipe FA exactly five
279 ; cycles before a floating point divide completes."
280 (define_function_unit "fdiv" 1 0
281 (and (eq_attr "cpu" "ev5")
282 (and (eq_attr "type" "fdiv")
283 (eq_attr "opsize" "si")))
284 15 15) ; 15 to 31 data dependant
286 (define_function_unit "fdiv" 1 0
287 (and (eq_attr "cpu" "ev5")
288 (and (eq_attr "type" "fdiv")
289 (eq_attr "opsize" "di")))
290 22 22) ; 22 to 60 data dependant
292 ;; EV6 scheduling. EV6 can issue 4 insns per clock.
294 ;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
295 ;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
297 ;; Conditional moves decompose into two independant primitives, each
298 ;; taking one cycle. Since ev6 is out-of-order, we can't see anything
300 (define_function_unit "ev6_ebox" 4 0
301 (and (eq_attr "cpu" "ev6")
302 (eq_attr "type" "icmov"))
305 (define_function_unit "ev6_ebox" 4 0
306 (and (eq_attr "cpu" "ev6")
307 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
310 ;; Integer loads take at least 3 clocks, and only issue to lower units.
311 ;; Return one from here and fix up with user-defined latencies in adjust_cost.
312 (define_function_unit "ev6_l" 2 0
313 (and (eq_attr "cpu" "ev6")
314 (eq_attr "type" "ild,ldsym,ist,fst"))
317 ;; FP loads take at least 4 clocks. Return two from here...
318 (define_function_unit "ev6_l" 2 0
319 (and (eq_attr "cpu" "ev6")
320 (eq_attr "type" "fld"))
323 ;; Motion video insns also issue only to U0, and take three ticks.
324 (define_function_unit "ev6_u0" 1 0
325 (and (eq_attr "cpu" "ev6")
326 (eq_attr "type" "mvi"))
329 (define_function_unit "ev6_u" 2 0
330 (and (eq_attr "cpu" "ev6")
331 (eq_attr "type" "mvi"))
334 ;; Shifts issue to either upper pipe.
335 (define_function_unit "ev6_u" 2 0
336 (and (eq_attr "cpu" "ev6")
337 (eq_attr "type" "shift"))
340 ;; Multiplies issue only to U1, and all take 7 ticks.
341 ;; Rather than create a new function unit just for U1, reuse IMUL
342 (define_function_unit "imul" 1 0
343 (and (eq_attr "cpu" "ev6")
344 (eq_attr "type" "imul"))
347 (define_function_unit "ev6_u" 2 0
348 (and (eq_attr "cpu" "ev6")
349 (eq_attr "type" "imul"))
352 ;; Branches issue to either upper pipe
353 (define_function_unit "ev6_u" 2 0
354 (and (eq_attr "cpu" "ev6")
355 (eq_attr "type" "ibr"))
358 ;; Calls only issue to L0.
359 (define_function_unit "ev6_l0" 1 0
360 (and (eq_attr "cpu" "ev6")
361 (eq_attr "type" "jsr"))
364 (define_function_unit "ev6_l" 2 0
365 (and (eq_attr "cpu" "ev6")
366 (eq_attr "type" "jsr"))
369 ;; Ftoi/itof only issue to lower pipes
370 (define_function_unit "ev6_l" 2 0
371 (and (eq_attr "cpu" "ev6")
372 (eq_attr "type" "ftoi"))
375 (define_function_unit "ev6_l" 2 0
376 (and (eq_attr "cpu" "ev6")
377 (eq_attr "type" "itof"))
380 ;; For the FPU we are very similar to EV5, except there's no insn that
381 ;; can issue to fm & fa, so we get to leave that out.
383 (define_function_unit "ev6_fm" 1 0
384 (and (eq_attr "cpu" "ev6")
385 (eq_attr "type" "fmul"))
388 (define_function_unit "ev6_fa" 1 0
389 (and (eq_attr "cpu" "ev6")
390 (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
393 (define_function_unit "ev6_fa" 1 0
394 (and (eq_attr "cpu" "ev6")
395 (eq_attr "type" "fcmov"))
398 (define_function_unit "fdiv" 1 0
399 (and (eq_attr "cpu" "ev6")
400 (and (eq_attr "type" "fdiv")
401 (eq_attr "opsize" "si")))
404 (define_function_unit "fdiv" 1 0
405 (and (eq_attr "cpu" "ev6")
406 (and (eq_attr "type" "fdiv")
407 (eq_attr "opsize" "di")))
410 (define_function_unit "fsqrt" 1 0
411 (and (eq_attr "cpu" "ev6")
412 (and (eq_attr "type" "fsqrt")
413 (eq_attr "opsize" "si")))
416 (define_function_unit "fsqrt" 1 0
417 (and (eq_attr "cpu" "ev6")
418 (and (eq_attr "type" "fsqrt")
419 (eq_attr "opsize" "di")))
422 ; ??? The FPU communicates with memory and the integer register file
423 ; via two fp store units. We need a slot in the fst immediately, and
424 ; a slot in LOW after the operand data is ready. At which point the
425 ; data may be moved either to the store queue or the integer register
426 ; file and the insn retired.
429 ;; First define the arithmetic insns. Note that the 32-bit forms also
432 ;; Handle 32-64 bit extension from memory to a floating point register
433 ;; specially, since this ocurrs frequently in int->double conversions.
435 ;; Note that while we must retain the =f case in the insn for reload's
436 ;; benefit, it should be eliminated after reload, so we should never emit
437 ;; code for that case. But we don't reject the possibility.
439 (define_expand "extendsidi2"
440 [(set (match_operand:DI 0 "register_operand" "")
441 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
445 (define_insn "*extendsidi2_nofix"
446 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
448 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
454 lds %0,%1\;cvtlq %0,%0"
455 [(set_attr "type" "iadd,ild,fadd,fld")
456 (set_attr "length" "*,*,*,8")])
458 (define_insn "*extendsidi2_fix"
459 [(set (match_operand:DI 0 "register_operand" "=r,r,r,*f,?*f")
461 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
468 lds %0,%1\;cvtlq %0,%0"
469 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
470 (set_attr "length" "*,*,*,*,8")])
472 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
474 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
475 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
477 [(set (match_dup 2) (match_dup 1))
478 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
479 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
481 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
482 ;; reload when converting fp->int.
485 [(set (match_operand:SI 0 "hard_int_register_operand" "")
486 (match_operand:SI 1 "memory_operand" ""))
487 (set (match_operand:DI 2 "hard_int_register_operand" "")
488 (sign_extend:DI (match_dup 0)))]
489 "true_regnum (operands[0]) == true_regnum (operands[2])
490 || peep2_reg_dead_p (2, operands[0])"
492 (sign_extend:DI (match_dup 1)))]
496 [(set (match_operand:SI 0 "hard_int_register_operand" "")
497 (match_operand:SI 1 "hard_fp_register_operand" ""))
498 (set (match_operand:DI 2 "hard_int_register_operand" "")
499 (sign_extend:DI (match_dup 0)))]
501 && (true_regnum (operands[0]) == true_regnum (operands[2])
502 || peep2_reg_dead_p (2, operands[0]))"
504 (sign_extend:DI (match_dup 1)))]
508 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
509 (sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" "")))
510 (set (match_operand:DI 2 "hard_int_register_operand" "")
512 "TARGET_FIX && peep2_reg_dead_p (2, operands[0])"
514 (sign_extend:DI (match_dup 1)))]
517 ;; Do addsi3 the way expand_binop would do if we didn't have one. This
518 ;; generates better code. We have the anonymous addsi3 pattern below in
519 ;; case combine wants to make it.
520 (define_expand "addsi3"
521 [(set (match_operand:SI 0 "register_operand" "")
522 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
523 (match_operand:SI 2 "add_operand" "")))]
528 rtx op1 = gen_lowpart (DImode, operands[1]);
529 rtx op2 = gen_lowpart (DImode, operands[2]);
531 if (! cse_not_expected)
533 rtx tmp = gen_reg_rtx (DImode);
534 emit_insn (gen_adddi3 (tmp, op1, op2));
535 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
538 emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
543 (define_insn "*addsi_internal"
544 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
545 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
546 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
555 [(set (match_operand:SI 0 "register_operand" "")
556 (plus:SI (match_operand:SI 1 "register_operand" "")
557 (match_operand:SI 2 "const_int_operand" "")))]
558 "! add_operand (operands[2], SImode)"
559 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
560 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
562 HOST_WIDE_INT val = INTVAL (operands[2]);
563 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
564 HOST_WIDE_INT rest = val - low;
566 operands[3] = GEN_INT (rest);
567 operands[4] = GEN_INT (low);
570 (define_insn "*addsi_se"
571 [(set (match_operand:DI 0 "register_operand" "=r,r")
573 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
574 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
581 [(set (match_operand:DI 0 "register_operand" "")
583 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
584 (match_operand:SI 2 "const_int_operand" ""))))
585 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
586 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
587 && INTVAL (operands[2]) % 4 == 0"
588 [(set (match_dup 3) (match_dup 4))
589 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
593 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
599 operands[4] = GEN_INT (val);
600 operands[5] = GEN_INT (mult);
604 [(set (match_operand:DI 0 "register_operand" "")
606 (plus:SI (match_operator:SI 1 "comparison_operator"
607 [(match_operand 2 "" "")
608 (match_operand 3 "" "")])
609 (match_operand:SI 4 "add_operand" ""))))
610 (clobber (match_operand:DI 5 "register_operand" ""))]
612 [(set (match_dup 5) (match_dup 6))
613 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
615 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
616 operands[2], operands[3]);
617 operands[7] = gen_lowpart (SImode, operands[5]);
620 (define_insn "addvsi3"
621 [(set (match_operand:SI 0 "register_operand" "=r,r")
622 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
623 (match_operand:SI 2 "sext_add_operand" "rI,O")))
624 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
625 (sign_extend:DI (match_dup 2)))
626 (sign_extend:DI (plus:SI (match_dup 1)
634 (define_expand "adddi3"
635 [(set (match_operand:DI 0 "register_operand" "")
636 (plus:DI (match_operand:DI 1 "register_operand" "")
637 (match_operand:DI 2 "add_operand" "")))]
641 (define_insn "*adddi_er_high"
642 [(set (match_operand:DI 0 "register_operand" "=r")
643 (plus:DI (match_operand:DI 1 "register_operand" "r")
644 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
645 "TARGET_EXPLICIT_RELOCS"
646 "ldah %0,%2(%1)\t\t!gprelhigh")
648 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
649 ;; With complications like
651 ;; The NT stack unwind code can't handle a subq to adjust the stack
652 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
653 ;; the exception handling code will loop if a subq is used and an
656 ;; The 19980616 change to emit prologues as RTL also confused some
657 ;; versions of GDB, which also interprets prologues. This has been
658 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
661 ;; and the fact that the three insns schedule exactly the same, it's
662 ;; just not worth the effort.
664 (define_insn "*adddi_internal"
665 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
666 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
667 (match_operand:DI 2 "add_operand" "r,K,L")))]
674 ;; ??? Allow large constants when basing off the frame pointer or some
675 ;; virtual register that may eliminate to the frame pointer. This is
676 ;; done because register elimination offsets will change the hi/lo split,
677 ;; and if we split before reload, we will require additional instructions.
679 (define_insn "*adddi_fp_hack"
680 [(set (match_operand:DI 0 "register_operand" "=r")
681 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
682 (match_operand:DI 2 "const_int_operand" "n")))]
683 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
684 && INTVAL (operands[2]) >= 0
685 /* This is the largest constant an lda+ldah pair can add, minus
686 an upper bound on the displacement between SP and AP during
687 register elimination. See INITIAL_ELIMINATION_OFFSET. */
688 && INTVAL (operands[2])
690 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
691 - ALPHA_ROUND(current_function_outgoing_args_size)
692 - (ALPHA_ROUND (get_frame_size ()
693 + max_reg_num () * UNITS_PER_WORD
694 + current_function_pretend_args_size)
695 - current_function_pretend_args_size))"
698 ;; Don't do this if we are adjusting SP since we don't want to do it
699 ;; in two steps. Don't split FP sources for the reason listed above.
701 [(set (match_operand:DI 0 "register_operand" "")
702 (plus:DI (match_operand:DI 1 "register_operand" "")
703 (match_operand:DI 2 "const_int_operand" "")))]
704 "! add_operand (operands[2], DImode)
705 && operands[0] != stack_pointer_rtx
706 && operands[1] != frame_pointer_rtx
707 && operands[1] != arg_pointer_rtx"
708 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
709 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
711 HOST_WIDE_INT val = INTVAL (operands[2]);
712 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
713 HOST_WIDE_INT rest = val - low;
715 operands[4] = GEN_INT (low);
716 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
717 operands[3] = GEN_INT (rest);
718 else if (! no_new_pseudos)
720 operands[3] = gen_reg_rtx (DImode);
721 emit_move_insn (operands[3], operands[2]);
722 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
729 (define_insn "*saddl"
730 [(set (match_operand:SI 0 "register_operand" "=r,r")
731 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
732 (match_operand:SI 2 "const48_operand" "I,I"))
733 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
739 (define_insn "*saddl_se"
740 [(set (match_operand:DI 0 "register_operand" "=r,r")
742 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
743 (match_operand:SI 2 "const48_operand" "I,I"))
744 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
751 [(set (match_operand:DI 0 "register_operand" "")
753 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
754 [(match_operand 2 "" "")
755 (match_operand 3 "" "")])
756 (match_operand:SI 4 "const48_operand" ""))
757 (match_operand:SI 5 "sext_add_operand" ""))))
758 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
760 [(set (match_dup 6) (match_dup 7))
762 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
765 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
766 operands[2], operands[3]);
767 operands[8] = gen_lowpart (SImode, operands[6]);
770 (define_insn "*saddq"
771 [(set (match_operand:DI 0 "register_operand" "=r,r")
772 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
773 (match_operand:DI 2 "const48_operand" "I,I"))
774 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
780 (define_insn "addvdi3"
781 [(set (match_operand:DI 0 "register_operand" "=r,r")
782 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
783 (match_operand:DI 2 "sext_add_operand" "rI,O")))
784 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
785 (sign_extend:TI (match_dup 2)))
786 (sign_extend:TI (plus:DI (match_dup 1)
794 (define_insn "negsi2"
795 [(set (match_operand:SI 0 "register_operand" "=r")
796 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
800 (define_insn "*negsi_se"
801 [(set (match_operand:DI 0 "register_operand" "=r")
802 (sign_extend:DI (neg:SI
803 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
807 (define_insn "negvsi2"
808 [(set (match_operand:SI 0 "register_operand" "=r")
809 (neg:SI (match_operand:SI 1 "register_operand" "r")))
810 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
811 (sign_extend:DI (neg:SI (match_dup 1))))
816 (define_insn "negdi2"
817 [(set (match_operand:DI 0 "register_operand" "=r")
818 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
822 (define_insn "negvdi2"
823 [(set (match_operand:DI 0 "register_operand" "=r")
824 (neg:DI (match_operand:DI 1 "register_operand" "r")))
825 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
826 (sign_extend:TI (neg:DI (match_dup 1))))
831 (define_expand "subsi3"
832 [(set (match_operand:SI 0 "register_operand" "")
833 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
834 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
839 rtx op1 = gen_lowpart (DImode, operands[1]);
840 rtx op2 = gen_lowpart (DImode, operands[2]);
842 if (! cse_not_expected)
844 rtx tmp = gen_reg_rtx (DImode);
845 emit_insn (gen_subdi3 (tmp, op1, op2));
846 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
849 emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
854 (define_insn "*subsi_internal"
855 [(set (match_operand:SI 0 "register_operand" "=r")
856 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
857 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
861 (define_insn "*subsi_se"
862 [(set (match_operand:DI 0 "register_operand" "=r")
863 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
864 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
868 (define_insn "subvsi3"
869 [(set (match_operand:SI 0 "register_operand" "=r")
870 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
871 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
872 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
873 (sign_extend:DI (match_dup 2)))
874 (sign_extend:DI (minus:SI (match_dup 1)
880 (define_insn "subdi3"
881 [(set (match_operand:DI 0 "register_operand" "=r")
882 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
883 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
887 (define_insn "*ssubl"
888 [(set (match_operand:SI 0 "register_operand" "=r")
889 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
890 (match_operand:SI 2 "const48_operand" "I"))
891 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
895 (define_insn "*ssubl_se"
896 [(set (match_operand:DI 0 "register_operand" "=r")
898 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
899 (match_operand:SI 2 "const48_operand" "I"))
900 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
904 (define_insn "*ssubq"
905 [(set (match_operand:DI 0 "register_operand" "=r")
906 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
907 (match_operand:DI 2 "const48_operand" "I"))
908 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
912 (define_insn "subvdi3"
913 [(set (match_operand:DI 0 "register_operand" "=r")
914 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
915 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
916 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
917 (sign_extend:TI (match_dup 2)))
918 (sign_extend:TI (minus:DI (match_dup 1)
924 ;; The Unicos/Mk assembler doesn't support mull.
926 (define_insn "mulsi3"
927 [(set (match_operand:SI 0 "register_operand" "=r")
928 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
929 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
930 "!TARGET_ABI_UNICOSMK"
932 [(set_attr "type" "imul")
933 (set_attr "opsize" "si")])
935 (define_insn "*mulsi_se"
936 [(set (match_operand:DI 0 "register_operand" "=r")
938 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
939 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
940 "!TARGET_ABI_UNICOSMK"
942 [(set_attr "type" "imul")
943 (set_attr "opsize" "si")])
945 (define_insn "mulvsi3"
946 [(set (match_operand:SI 0 "register_operand" "=r")
947 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
948 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
949 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
950 (sign_extend:DI (match_dup 2)))
951 (sign_extend:DI (mult:SI (match_dup 1)
954 "!TARGET_ABI_UNICOSMK"
956 [(set_attr "type" "imul")
957 (set_attr "opsize" "si")])
959 (define_insn "muldi3"
960 [(set (match_operand:DI 0 "register_operand" "=r")
961 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
962 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
965 [(set_attr "type" "imul")])
967 (define_insn "mulvdi3"
968 [(set (match_operand:DI 0 "register_operand" "=r")
969 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
970 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
971 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
972 (sign_extend:TI (match_dup 2)))
973 (sign_extend:TI (mult:DI (match_dup 1)
978 [(set_attr "type" "imul")])
980 (define_insn "umuldi3_highpart"
981 [(set (match_operand:DI 0 "register_operand" "=r")
984 (mult:TI (zero_extend:TI
985 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
987 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
991 [(set_attr "type" "imul")
992 (set_attr "opsize" "udi")])
994 (define_insn "*umuldi3_highpart_const"
995 [(set (match_operand:DI 0 "register_operand" "=r")
998 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
999 (match_operand:TI 2 "cint8_operand" "I"))
1003 [(set_attr "type" "imul")
1004 (set_attr "opsize" "udi")])
1006 ;; The divide and remainder operations take their inputs from r24 and
1007 ;; r25, put their output in r27, and clobber r23 and r28 on all
1008 ;; systems except Unicos/Mk. On Unicos, the standard library provides
1009 ;; subroutines which use the standard calling convention and work on
1012 ;; ??? Force sign-extension here because some versions of OSF/1 and
1013 ;; Interix/NT don't do the right thing if the inputs are not properly
1014 ;; sign-extended. But Linux, for instance, does not have this
1015 ;; problem. Is it worth the complication here to eliminate the sign
1018 (define_expand "divsi3"
1020 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1022 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1023 (parallel [(set (reg:DI 27)
1024 (sign_extend:DI (div:SI (reg:DI 24) (reg:DI 25))))
1025 (clobber (reg:DI 23))
1026 (clobber (reg:DI 28))])
1027 (set (match_operand:SI 0 "nonimmediate_operand" "")
1028 (subreg:SI (reg:DI 27) 0))]
1029 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1032 (define_expand "udivsi3"
1034 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1036 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1037 (parallel [(set (reg:DI 27)
1038 (sign_extend:DI (udiv:SI (reg:DI 24) (reg:DI 25))))
1039 (clobber (reg:DI 23))
1040 (clobber (reg:DI 28))])
1041 (set (match_operand:SI 0 "nonimmediate_operand" "")
1042 (subreg:SI (reg:DI 27) 0))]
1043 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1046 (define_expand "modsi3"
1048 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1050 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1051 (parallel [(set (reg:DI 27)
1052 (sign_extend:DI (mod:SI (reg:DI 24) (reg:DI 25))))
1053 (clobber (reg:DI 23))
1054 (clobber (reg:DI 28))])
1055 (set (match_operand:SI 0 "nonimmediate_operand" "")
1056 (subreg:SI (reg:DI 27) 0))]
1057 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1060 (define_expand "umodsi3"
1062 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
1064 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
1065 (parallel [(set (reg:DI 27)
1066 (sign_extend:DI (umod:SI (reg:DI 24) (reg:DI 25))))
1067 (clobber (reg:DI 23))
1068 (clobber (reg:DI 28))])
1069 (set (match_operand:SI 0 "nonimmediate_operand" "")
1070 (subreg:SI (reg:DI 27) 0))]
1071 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1074 (define_expand "divdi3"
1075 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
1076 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
1077 (parallel [(set (reg:DI 27)
1080 (clobber (reg:DI 23))
1081 (clobber (reg:DI 28))])
1082 (set (match_operand:DI 0 "nonimmediate_operand" "")
1084 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1087 (define_expand "udivdi3"
1088 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
1089 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
1090 (parallel [(set (reg:DI 27)
1091 (udiv:DI (reg:DI 24)
1093 (clobber (reg:DI 23))
1094 (clobber (reg:DI 28))])
1095 (set (match_operand:DI 0 "nonimmediate_operand" "")
1097 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1100 (define_expand "moddi3"
1101 [(use (match_operand:DI 0 "nonimmediate_operand" ""))
1102 (use (match_operand:DI 1 "input_operand" ""))
1103 (use (match_operand:DI 2 "input_operand" ""))]
1104 "!TARGET_ABI_OPEN_VMS"
1106 if (TARGET_ABI_UNICOSMK)
1107 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
1109 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
1113 (define_expand "moddi3_dft"
1114 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
1115 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
1116 (parallel [(set (reg:DI 27)
1119 (clobber (reg:DI 23))
1120 (clobber (reg:DI 28))])
1121 (set (match_operand:DI 0 "nonimmediate_operand" "")
1123 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1126 ;; On Unicos/Mk, we do as the system's C compiler does:
1127 ;; compute the quotient, multiply and subtract.
1129 (define_expand "moddi3_umk"
1130 [(use (match_operand:DI 0 "nonimmediate_operand" ""))
1131 (use (match_operand:DI 1 "input_operand" ""))
1132 (use (match_operand:DI 2 "input_operand" ""))]
1133 "TARGET_ABI_UNICOSMK"
1137 mul = gen_reg_rtx (DImode);
1138 tmp = gen_reg_rtx (DImode);
1139 operands[1] = force_reg (DImode, operands[1]);
1140 operands[2] = force_reg (DImode, operands[2]);
1142 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
1143 NULL_RTX, 0, OPTAB_LIB);
1144 div = force_reg (DImode, div);
1145 emit_insn (gen_muldi3 (mul, operands[2], div));
1146 emit_insn (gen_subdi3 (tmp, operands[1], mul));
1147 emit_move_insn (operands[0], tmp);
1151 (define_expand "umoddi3"
1152 [(use (match_operand:DI 0 "nonimmediate_operand" ""))
1153 (use (match_operand:DI 1 "input_operand" ""))
1154 (use (match_operand:DI 2 "input_operand" ""))]
1155 "! TARGET_ABI_OPEN_VMS"
1157 if (TARGET_ABI_UNICOSMK)
1158 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
1160 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
1164 (define_expand "umoddi3_dft"
1165 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
1166 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
1167 (parallel [(set (reg:DI 27)
1168 (umod:DI (reg:DI 24)
1170 (clobber (reg:DI 23))
1171 (clobber (reg:DI 28))])
1172 (set (match_operand:DI 0 "nonimmediate_operand" "")
1174 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1177 (define_expand "umoddi3_umk"
1178 [(use (match_operand:DI 0 "nonimmediate_operand" ""))
1179 (use (match_operand:DI 1 "input_operand" ""))
1180 (use (match_operand:DI 2 "input_operand" ""))]
1181 "TARGET_ABI_UNICOSMK"
1185 mul = gen_reg_rtx (DImode);
1186 tmp = gen_reg_rtx (DImode);
1187 operands[1] = force_reg (DImode, operands[1]);
1188 operands[2] = force_reg (DImode, operands[2]);
1190 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
1191 NULL_RTX, 1, OPTAB_LIB);
1192 div = force_reg (DImode, div);
1193 emit_insn (gen_muldi3 (mul, operands[2], div));
1194 emit_insn (gen_subdi3 (tmp, operands[1], mul));
1195 emit_move_insn (operands[0], tmp);
1199 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
1200 ;; expanded by the assembler.
1202 (define_insn "*divmodsi_internal_er"
1204 (sign_extend:DI (match_operator:SI 0 "divmod_operator"
1205 [(reg:DI 24) (reg:DI 25)])))
1206 (clobber (reg:DI 23))
1207 (clobber (reg:DI 28))]
1208 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1209 "ldq $27,__%E0($29)\t\t!literal!%#\;jsr $23,($27),__%E0\t\t!lituse_jsr!%#"
1210 [(set_attr "type" "jsr")
1211 (set_attr "length" "8")])
1213 (define_insn "*divmodsi_internal"
1215 (sign_extend:DI (match_operator:SI 0 "divmod_operator"
1216 [(reg:DI 24) (reg:DI 25)])))
1217 (clobber (reg:DI 23))
1218 (clobber (reg:DI 28))]
1219 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1221 [(set_attr "type" "jsr")
1222 (set_attr "length" "8")])
1224 (define_insn "*divmoddi_internal_er"
1226 (match_operator:DI 0 "divmod_operator"
1227 [(reg:DI 24) (reg:DI 25)]))
1228 (clobber (reg:DI 23))
1229 (clobber (reg:DI 28))]
1230 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1231 "ldq $27,__%E0($29)\t\t!literal!%#\;jsr $23,($27),__%E0\t\t!lituse_jsr!%#"
1232 [(set_attr "type" "jsr")
1233 (set_attr "length" "8")])
1235 (define_insn "*divmoddi_internal"
1237 (match_operator:DI 0 "divmod_operator"
1238 [(reg:DI 24) (reg:DI 25)]))
1239 (clobber (reg:DI 23))
1240 (clobber (reg:DI 28))]
1241 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1243 [(set_attr "type" "jsr")
1244 (set_attr "length" "8")])
1246 ;; Next are the basic logical operations. These only exist in DImode.
1248 (define_insn "anddi3"
1249 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1250 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1251 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1257 [(set_attr "type" "ilog,ilog,shift")])
1259 ;; There are times when we can split an AND into two AND insns. This occurs
1260 ;; when we can first clear any bytes and then clear anything else. For
1261 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1262 ;; Only do this when running on 64-bit host since the computations are
1263 ;; too messy otherwise.
1266 [(set (match_operand:DI 0 "register_operand" "")
1267 (and:DI (match_operand:DI 1 "register_operand" "")
1268 (match_operand:DI 2 "const_int_operand" "")))]
1269 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1270 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1271 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1273 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1274 unsigned HOST_WIDE_INT mask2 = mask1;
1277 /* For each byte that isn't all zeros, make it all ones. */
1278 for (i = 0; i < 64; i += 8)
1279 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1280 mask1 |= (HOST_WIDE_INT) 0xff << i;
1282 /* Now turn on any bits we've just turned off. */
1285 operands[3] = GEN_INT (mask1);
1286 operands[4] = GEN_INT (mask2);
1289 (define_expand "zero_extendqihi2"
1290 [(set (match_operand:HI 0 "register_operand" "")
1291 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1295 operands[1] = force_reg (QImode, operands[1]);
1298 (define_insn "*zero_extendqihi2_bwx"
1299 [(set (match_operand:HI 0 "register_operand" "=r,r")
1300 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1305 [(set_attr "type" "ilog,ild")])
1307 (define_insn "*zero_extendqihi2_nobwx"
1308 [(set (match_operand:HI 0 "register_operand" "=r")
1309 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1312 [(set_attr "type" "ilog")])
1314 (define_expand "zero_extendqisi2"
1315 [(set (match_operand:SI 0 "register_operand" "")
1316 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1320 operands[1] = force_reg (QImode, operands[1]);
1323 (define_insn "*zero_extendqisi2_bwx"
1324 [(set (match_operand:SI 0 "register_operand" "=r,r")
1325 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1330 [(set_attr "type" "ilog,ild")])
1332 (define_insn "*zero_extendqisi2_nobwx"
1333 [(set (match_operand:SI 0 "register_operand" "=r")
1334 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1337 [(set_attr "type" "ilog")])
1339 (define_expand "zero_extendqidi2"
1340 [(set (match_operand:DI 0 "register_operand" "")
1341 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1345 operands[1] = force_reg (QImode, operands[1]);
1348 (define_insn "*zero_extendqidi2_bwx"
1349 [(set (match_operand:DI 0 "register_operand" "=r,r")
1350 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1355 [(set_attr "type" "ilog,ild")])
1357 (define_insn "*zero_extendqidi2_nobwx"
1358 [(set (match_operand:DI 0 "register_operand" "=r")
1359 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1362 [(set_attr "type" "ilog")])
1364 (define_expand "zero_extendhisi2"
1365 [(set (match_operand:SI 0 "register_operand" "")
1366 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1370 operands[1] = force_reg (HImode, operands[1]);
1373 (define_insn "*zero_extendhisi2_bwx"
1374 [(set (match_operand:SI 0 "register_operand" "=r,r")
1375 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1380 [(set_attr "type" "shift,ild")])
1382 (define_insn "*zero_extendhisi2_nobwx"
1383 [(set (match_operand:SI 0 "register_operand" "=r")
1384 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1387 [(set_attr "type" "shift")])
1389 (define_expand "zero_extendhidi2"
1390 [(set (match_operand:DI 0 "register_operand" "")
1391 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1395 operands[1] = force_reg (HImode, operands[1]);
1398 (define_insn "*zero_extendhidi2_bwx"
1399 [(set (match_operand:DI 0 "register_operand" "=r,r")
1400 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1405 [(set_attr "type" "shift,ild")])
1407 (define_insn "*zero_extendhidi2_nobwx"
1408 [(set (match_operand:DI 0 "register_operand" "=r")
1409 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1412 [(set_attr "type" "shift")])
1414 (define_insn "zero_extendsidi2"
1415 [(set (match_operand:DI 0 "register_operand" "=r")
1416 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1419 [(set_attr "type" "shift")])
1421 (define_insn "andnotdi3"
1422 [(set (match_operand:DI 0 "register_operand" "=r")
1423 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1424 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1427 [(set_attr "type" "ilog")])
1429 (define_insn "iordi3"
1430 [(set (match_operand:DI 0 "register_operand" "=r,r")
1431 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1432 (match_operand:DI 2 "or_operand" "rI,N")))]
1437 [(set_attr "type" "ilog")])
1439 (define_insn "one_cmpldi2"
1440 [(set (match_operand:DI 0 "register_operand" "=r")
1441 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1444 [(set_attr "type" "ilog")])
1446 (define_insn "*iornot"
1447 [(set (match_operand:DI 0 "register_operand" "=r")
1448 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1449 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1452 [(set_attr "type" "ilog")])
1454 (define_insn "xordi3"
1455 [(set (match_operand:DI 0 "register_operand" "=r,r")
1456 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1457 (match_operand:DI 2 "or_operand" "rI,N")))]
1462 [(set_attr "type" "ilog")])
1464 (define_insn "*xornot"
1465 [(set (match_operand:DI 0 "register_operand" "=r")
1466 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1467 (match_operand:DI 2 "register_operand" "rI"))))]
1470 [(set_attr "type" "ilog")])
1472 ;; Handle the FFS insn iff we support CIX.
1474 (define_expand "ffsdi2"
1476 (unspec:DI [(match_operand:DI 1 "register_operand" "")] UNSPEC_CTTZ))
1478 (plus:DI (match_dup 2) (const_int 1)))
1479 (set (match_operand:DI 0 "register_operand" "")
1480 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1481 (const_int 0) (match_dup 3)))]
1484 operands[2] = gen_reg_rtx (DImode);
1485 operands[3] = gen_reg_rtx (DImode);
1488 (define_insn "*cttz"
1489 [(set (match_operand:DI 0 "register_operand" "=r")
1490 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_CTTZ))]
1493 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1494 ; reuse the existing type name.
1495 [(set_attr "type" "mvi")])
1497 ;; Next come the shifts and the various extract and insert operations.
1499 (define_insn "ashldi3"
1500 [(set (match_operand:DI 0 "register_operand" "=r,r")
1501 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1502 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1505 switch (which_alternative)
1508 if (operands[2] == const1_rtx)
1509 return "addq %r1,%r1,%0";
1511 return "s%P2addq %r1,0,%0";
1513 return "sll %r1,%2,%0";
1518 [(set_attr "type" "iadd,shift")])
1520 ;; ??? The following pattern is made by combine, but earlier phases
1521 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
1522 ;; with this in a better way at some point.
1524 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1526 ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1527 ;; (match_operand:DI 2 "const_int_operand" "P"))
1529 ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1531 ;; if (operands[2] == const1_rtx)
1532 ;; return "addl %r1,%r1,%0";
1534 ;; return "s%P2addl %r1,0,%0";
1536 ;; [(set_attr "type" "iadd")])
1538 (define_insn "lshrdi3"
1539 [(set (match_operand:DI 0 "register_operand" "=r")
1540 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1541 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1544 [(set_attr "type" "shift")])
1546 (define_insn "ashrdi3"
1547 [(set (match_operand:DI 0 "register_operand" "=r")
1548 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1549 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1552 [(set_attr "type" "shift")])
1554 (define_expand "extendqihi2"
1556 (ashift:DI (match_operand:QI 1 "some_operand" "")
1558 (set (match_operand:HI 0 "register_operand" "")
1559 (ashiftrt:DI (match_dup 2)
1565 emit_insn (gen_extendqihi2x (operands[0],
1566 force_reg (QImode, operands[1])));
1570 /* If we have an unaligned MEM, extend to DImode (which we do
1571 specially) and then copy to the result. */
1572 if (unaligned_memory_operand (operands[1], HImode))
1574 rtx temp = gen_reg_rtx (DImode);
1576 emit_insn (gen_extendqidi2 (temp, operands[1]));
1577 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1581 operands[0] = gen_lowpart (DImode, operands[0]);
1582 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1583 operands[2] = gen_reg_rtx (DImode);
1586 (define_insn "extendqidi2x"
1587 [(set (match_operand:DI 0 "register_operand" "=r")
1588 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1591 [(set_attr "type" "shift")])
1593 (define_insn "extendhidi2x"
1594 [(set (match_operand:DI 0 "register_operand" "=r")
1595 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1598 [(set_attr "type" "shift")])
1600 (define_insn "extendqisi2x"
1601 [(set (match_operand:SI 0 "register_operand" "=r")
1602 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1605 [(set_attr "type" "shift")])
1607 (define_insn "extendhisi2x"
1608 [(set (match_operand:SI 0 "register_operand" "=r")
1609 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1612 [(set_attr "type" "shift")])
1614 (define_insn "extendqihi2x"
1615 [(set (match_operand:HI 0 "register_operand" "=r")
1616 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1619 [(set_attr "type" "shift")])
1621 (define_expand "extendqisi2"
1623 (ashift:DI (match_operand:QI 1 "some_operand" "")
1625 (set (match_operand:SI 0 "register_operand" "")
1626 (ashiftrt:DI (match_dup 2)
1632 emit_insn (gen_extendqisi2x (operands[0],
1633 force_reg (QImode, operands[1])));
1637 /* If we have an unaligned MEM, extend to a DImode form of
1638 the result (which we do specially). */
1639 if (unaligned_memory_operand (operands[1], QImode))
1641 rtx temp = gen_reg_rtx (DImode);
1643 emit_insn (gen_extendqidi2 (temp, operands[1]));
1644 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1648 operands[0] = gen_lowpart (DImode, operands[0]);
1649 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1650 operands[2] = gen_reg_rtx (DImode);
1653 (define_expand "extendqidi2"
1655 (ashift:DI (match_operand:QI 1 "some_operand" "")
1657 (set (match_operand:DI 0 "register_operand" "")
1658 (ashiftrt:DI (match_dup 2)
1664 emit_insn (gen_extendqidi2x (operands[0],
1665 force_reg (QImode, operands[1])));
1669 if (unaligned_memory_operand (operands[1], QImode))
1672 = gen_unaligned_extendqidi (operands[0],
1673 get_unaligned_address (operands[1], 1));
1675 alpha_set_memflags (seq, operands[1]);
1680 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1681 operands[2] = gen_reg_rtx (DImode);
1684 (define_expand "extendhisi2"
1686 (ashift:DI (match_operand:HI 1 "some_operand" "")
1688 (set (match_operand:SI 0 "register_operand" "")
1689 (ashiftrt:DI (match_dup 2)
1695 emit_insn (gen_extendhisi2x (operands[0],
1696 force_reg (HImode, operands[1])));
1700 /* If we have an unaligned MEM, extend to a DImode form of
1701 the result (which we do specially). */
1702 if (unaligned_memory_operand (operands[1], HImode))
1704 rtx temp = gen_reg_rtx (DImode);
1706 emit_insn (gen_extendhidi2 (temp, operands[1]));
1707 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1711 operands[0] = gen_lowpart (DImode, operands[0]);
1712 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1713 operands[2] = gen_reg_rtx (DImode);
1716 (define_expand "extendhidi2"
1718 (ashift:DI (match_operand:HI 1 "some_operand" "")
1720 (set (match_operand:DI 0 "register_operand" "")
1721 (ashiftrt:DI (match_dup 2)
1727 emit_insn (gen_extendhidi2x (operands[0],
1728 force_reg (HImode, operands[1])));
1732 if (unaligned_memory_operand (operands[1], HImode))
1735 = gen_unaligned_extendhidi (operands[0],
1736 get_unaligned_address (operands[1], 2));
1738 alpha_set_memflags (seq, operands[1]);
1743 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1744 operands[2] = gen_reg_rtx (DImode);
1747 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1748 ;; as a pattern saves one instruction. The code is similar to that for
1749 ;; the unaligned loads (see below).
1751 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1752 (define_expand "unaligned_extendqidi"
1753 [(use (match_operand:QI 0 "register_operand" ""))
1754 (use (match_operand:DI 1 "address_operand" ""))]
1757 if (WORDS_BIG_ENDIAN)
1758 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1760 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1764 (define_expand "unaligned_extendqidi_le"
1765 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1767 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1770 (ashift:DI (match_dup 3)
1771 (minus:DI (const_int 64)
1773 (and:DI (match_dup 2) (const_int 7))
1775 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1776 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1777 "! WORDS_BIG_ENDIAN"
1779 operands[2] = gen_reg_rtx (DImode);
1780 operands[3] = gen_reg_rtx (DImode);
1781 operands[4] = gen_reg_rtx (DImode);
1784 (define_expand "unaligned_extendqidi_be"
1785 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1786 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
1788 (mem:DI (and:DI (match_dup 3)
1790 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
1792 (ashift:DI (match_dup 4)
1795 (plus:DI (match_dup 5) (const_int 1))
1798 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1799 (ashiftrt:DI (match_dup 6) (const_int 56)))]
1802 operands[2] = gen_reg_rtx (DImode);
1803 operands[3] = gen_reg_rtx (DImode);
1804 operands[4] = gen_reg_rtx (DImode);
1805 operands[5] = gen_reg_rtx (DImode);
1806 operands[6] = gen_reg_rtx (DImode);
1809 (define_expand "unaligned_extendhidi"
1810 [(use (match_operand:QI 0 "register_operand" ""))
1811 (use (match_operand:DI 1 "address_operand" ""))]
1814 if (WORDS_BIG_ENDIAN)
1815 emit_insn (gen_unaligned_extendhidi_be (operands[0], operands[1]));
1817 emit_insn (gen_unaligned_extendhidi_le (operands[0], operands[1]));
1821 (define_expand "unaligned_extendhidi_le"
1822 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1824 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1827 (ashift:DI (match_dup 3)
1828 (minus:DI (const_int 64)
1830 (and:DI (match_dup 2) (const_int 7))
1832 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1833 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1834 "! WORDS_BIG_ENDIAN"
1836 operands[2] = gen_reg_rtx (DImode);
1837 operands[3] = gen_reg_rtx (DImode);
1838 operands[4] = gen_reg_rtx (DImode);
1841 (define_expand "unaligned_extendhidi_be"
1842 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1843 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
1845 (mem:DI (and:DI (match_dup 3)
1847 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
1849 (ashift:DI (match_dup 4)
1852 (plus:DI (match_dup 5) (const_int 1))
1855 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1856 (ashiftrt:DI (match_dup 6) (const_int 48)))]
1859 operands[2] = gen_reg_rtx (DImode);
1860 operands[3] = gen_reg_rtx (DImode);
1861 operands[4] = gen_reg_rtx (DImode);
1862 operands[5] = gen_reg_rtx (DImode);
1863 operands[6] = gen_reg_rtx (DImode);
1866 (define_insn "*extxl_const"
1867 [(set (match_operand:DI 0 "register_operand" "=r")
1868 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1869 (match_operand:DI 2 "mode_width_operand" "n")
1870 (match_operand:DI 3 "mul8_operand" "I")))]
1872 "ext%M2l %r1,%s3,%0"
1873 [(set_attr "type" "shift")])
1875 (define_insn "extxl_le"
1876 [(set (match_operand:DI 0 "register_operand" "=r")
1877 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1878 (match_operand:DI 2 "mode_width_operand" "n")
1879 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1881 "! WORDS_BIG_ENDIAN"
1883 [(set_attr "type" "shift")])
1885 (define_insn "extxl_be"
1886 [(set (match_operand:DI 0 "register_operand" "=r")
1887 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1888 (match_operand:DI 2 "mode_width_operand" "n")
1892 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1896 [(set_attr "type" "shift")])
1898 ;; Combine has some strange notion of preserving existing undefined behaviour
1899 ;; in shifts larger than a word size. So capture these patterns that it
1900 ;; should have turned into zero_extracts.
1902 (define_insn "*extxl_1_le"
1903 [(set (match_operand:DI 0 "register_operand" "=r")
1904 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1905 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1907 (match_operand:DI 3 "mode_mask_operand" "n")))]
1908 "! WORDS_BIG_ENDIAN"
1910 [(set_attr "type" "shift")])
1912 (define_insn "*extxl_1_be"
1913 [(set (match_operand:DI 0 "register_operand" "=r")
1914 (and:DI (lshiftrt:DI
1915 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1916 (minus:DI (const_int 56)
1917 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1919 (match_operand:DI 3 "mode_mask_operand" "n")))]
1922 [(set_attr "type" "shift")])
1924 (define_insn "*extql_2_le"
1925 [(set (match_operand:DI 0 "register_operand" "=r")
1926 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1927 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1929 "! WORDS_BIG_ENDIAN"
1931 [(set_attr "type" "shift")])
1933 (define_insn "*extql_2_be"
1934 [(set (match_operand:DI 0 "register_operand" "=r")
1936 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1937 (minus:DI (const_int 56)
1939 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1943 [(set_attr "type" "shift")])
1945 (define_insn "extqh_le"
1946 [(set (match_operand:DI 0 "register_operand" "=r")
1948 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1949 (minus:DI (const_int 64)
1952 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1955 "! WORDS_BIG_ENDIAN"
1957 [(set_attr "type" "shift")])
1959 (define_insn "extqh_be"
1960 [(set (match_operand:DI 0 "register_operand" "=r")
1962 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1965 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1971 [(set_attr "type" "shift")])
1973 (define_insn "extlh_le"
1974 [(set (match_operand:DI 0 "register_operand" "=r")
1976 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1977 (const_int 2147483647))
1978 (minus:DI (const_int 64)
1981 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1984 "! WORDS_BIG_ENDIAN"
1986 [(set_attr "type" "shift")])
1988 (define_insn "extlh_be"
1989 [(set (match_operand:DI 0 "register_operand" "=r")
1992 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1996 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2000 (const_int 2147483647)))]
2003 [(set_attr "type" "shift")])
2005 (define_insn "extwh_le"
2006 [(set (match_operand:DI 0 "register_operand" "=r")
2008 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2010 (minus:DI (const_int 64)
2013 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2016 "! WORDS_BIG_ENDIAN"
2018 [(set_attr "type" "shift")])
2020 (define_insn "extwh_be"
2021 [(set (match_operand:DI 0 "register_operand" "=r")
2023 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2027 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2031 (const_int 65535)))]
2034 [(set_attr "type" "shift")])
2036 ;; This converts an extXl into an extXh with an appropriate adjustment
2037 ;; to the address calculation.
2040 ;; [(set (match_operand:DI 0 "register_operand" "")
2041 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
2042 ;; (match_operand:DI 2 "mode_width_operand" "")
2043 ;; (ashift:DI (match_operand:DI 3 "" "")
2045 ;; (match_operand:DI 4 "const_int_operand" "")))
2046 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
2047 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
2048 ;; [(set (match_dup 5) (match_dup 6))
2049 ;; (set (match_dup 0)
2050 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
2051 ;; (ashift:DI (plus:DI (match_dup 5)
2057 ;; operands[6] = plus_constant (operands[3],
2058 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
2059 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
2062 (define_insn "*insbl_const"
2063 [(set (match_operand:DI 0 "register_operand" "=r")
2064 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2065 (match_operand:DI 2 "mul8_operand" "I")))]
2068 [(set_attr "type" "shift")])
2070 (define_insn "*inswl_const"
2071 [(set (match_operand:DI 0 "register_operand" "=r")
2072 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2073 (match_operand:DI 2 "mul8_operand" "I")))]
2076 [(set_attr "type" "shift")])
2078 (define_insn "*insll_const"
2079 [(set (match_operand:DI 0 "register_operand" "=r")
2080 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2081 (match_operand:DI 2 "mul8_operand" "I")))]
2084 [(set_attr "type" "shift")])
2086 (define_insn "insbl_le"
2087 [(set (match_operand:DI 0 "register_operand" "=r")
2088 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2089 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2091 "! WORDS_BIG_ENDIAN"
2093 [(set_attr "type" "shift")])
2095 (define_insn "insbl_be"
2096 [(set (match_operand:DI 0 "register_operand" "=r")
2097 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2098 (minus:DI (const_int 56)
2099 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2103 [(set_attr "type" "shift")])
2105 (define_insn "inswl_le"
2106 [(set (match_operand:DI 0 "register_operand" "=r")
2107 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2108 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2110 "! WORDS_BIG_ENDIAN"
2112 [(set_attr "type" "shift")])
2114 (define_insn "inswl_be"
2115 [(set (match_operand:DI 0 "register_operand" "=r")
2116 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2117 (minus:DI (const_int 56)
2118 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2122 [(set_attr "type" "shift")])
2124 (define_insn "insll_le"
2125 [(set (match_operand:DI 0 "register_operand" "=r")
2126 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2127 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2129 "! WORDS_BIG_ENDIAN"
2131 [(set_attr "type" "shift")])
2133 (define_insn "insll_be"
2134 [(set (match_operand:DI 0 "register_operand" "=r")
2135 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2136 (minus:DI (const_int 56)
2137 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2141 [(set_attr "type" "shift")])
2143 (define_insn "insql_le"
2144 [(set (match_operand:DI 0 "register_operand" "=r")
2145 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2146 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2148 "! WORDS_BIG_ENDIAN"
2150 [(set_attr "type" "shift")])
2152 (define_insn "insql_be"
2153 [(set (match_operand:DI 0 "register_operand" "=r")
2154 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2155 (minus:DI (const_int 56)
2156 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2160 [(set_attr "type" "shift")])
2162 ;; Combine has this sometimes habit of moving the and outside of the
2163 ;; shift, making life more interesting.
2165 (define_insn "*insxl"
2166 [(set (match_operand:DI 0 "register_operand" "=r")
2167 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2168 (match_operand:DI 2 "mul8_operand" "I"))
2169 (match_operand:DI 3 "immediate_operand" "i")))]
2170 "HOST_BITS_PER_WIDE_INT == 64
2171 && GET_CODE (operands[3]) == CONST_INT
2172 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2173 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2174 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2175 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2176 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2177 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2179 #if HOST_BITS_PER_WIDE_INT == 64
2180 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2181 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2182 return "insbl %1,%s2,%0";
2183 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2184 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2185 return "inswl %1,%s2,%0";
2186 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2187 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2188 return "insll %1,%s2,%0";
2192 [(set_attr "type" "shift")])
2194 ;; We do not include the insXh insns because they are complex to express
2195 ;; and it does not appear that we would ever want to generate them.
2197 ;; Since we need them for block moves, though, cop out and use unspec.
2199 (define_insn "insxh"
2200 [(set (match_operand:DI 0 "register_operand" "=r")
2201 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2202 (match_operand:DI 2 "mode_width_operand" "n")
2203 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2207 [(set_attr "type" "shift")])
2209 (define_insn "mskxl_le"
2210 [(set (match_operand:DI 0 "register_operand" "=r")
2211 (and:DI (not:DI (ashift:DI
2212 (match_operand:DI 2 "mode_mask_operand" "n")
2214 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2216 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2217 "! WORDS_BIG_ENDIAN"
2219 [(set_attr "type" "shift")])
2221 (define_insn "mskxl_be"
2222 [(set (match_operand:DI 0 "register_operand" "=r")
2223 (and:DI (not:DI (ashift:DI
2224 (match_operand:DI 2 "mode_mask_operand" "n")
2225 (minus:DI (const_int 56)
2227 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2229 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2232 [(set_attr "type" "shift")])
2234 ;; We do not include the mskXh insns because it does not appear we would
2235 ;; ever generate one.
2237 ;; Again, we do for block moves and we use unspec again.
2239 (define_insn "mskxh"
2240 [(set (match_operand:DI 0 "register_operand" "=r")
2241 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2242 (match_operand:DI 2 "mode_width_operand" "n")
2243 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2247 [(set_attr "type" "shift")])
2249 ;; Prefer AND + NE over LSHIFTRT + AND.
2251 (define_insn_and_split "*ze_and_ne"
2252 [(set (match_operand:DI 0 "register_operand" "=r")
2253 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2255 (match_operand 2 "const_int_operand" "I")))]
2256 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2258 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2260 (and:DI (match_dup 1) (match_dup 3)))
2262 (ne:DI (match_dup 0) (const_int 0)))]
2263 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2265 ;; Floating-point operations. All the double-precision insns can extend
2266 ;; from single, so indicate that. The exception are the ones that simply
2267 ;; play with the sign bits; it's not clear what to do there.
2269 (define_insn "abssf2"
2270 [(set (match_operand:SF 0 "register_operand" "=f")
2271 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2274 [(set_attr "type" "fcpys")])
2276 (define_insn "*nabssf2"
2277 [(set (match_operand:SF 0 "register_operand" "=f")
2278 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2281 [(set_attr "type" "fadd")])
2283 (define_insn "absdf2"
2284 [(set (match_operand:DF 0 "register_operand" "=f")
2285 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2288 [(set_attr "type" "fcpys")])
2290 (define_insn "*nabsdf2"
2291 [(set (match_operand:DF 0 "register_operand" "=f")
2292 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG"))))]
2295 [(set_attr "type" "fadd")])
2297 (define_expand "abstf2"
2298 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2299 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
2300 (use (match_dup 2))])]
2301 "TARGET_HAS_XFLOATING_LIBS"
2303 #if HOST_BITS_PER_WIDE_INT >= 64
2304 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
2306 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2310 (define_insn_and_split "*abstf_internal"
2311 [(set (match_operand:TF 0 "register_operand" "=r")
2312 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
2313 (use (match_operand:DI 2 "register_operand" "r"))]
2314 "TARGET_HAS_XFLOATING_LIBS"
2316 "&& reload_completed"
2318 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2320 (define_insn "negsf2"
2321 [(set (match_operand:SF 0 "register_operand" "=f")
2322 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2325 [(set_attr "type" "fadd")])
2327 (define_insn "negdf2"
2328 [(set (match_operand:DF 0 "register_operand" "=f")
2329 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2332 [(set_attr "type" "fadd")])
2334 (define_expand "negtf2"
2335 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2336 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
2337 (use (match_dup 2))])]
2338 "TARGET_HAS_XFLOATING_LIBS"
2340 #if HOST_BITS_PER_WIDE_INT >= 64
2341 operands[2] = force_reg (DImode, GEN_INT (0x8000000000000000));
2343 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2347 (define_insn_and_split "*negtf_internal"
2348 [(set (match_operand:TF 0 "register_operand" "=r")
2349 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
2350 (use (match_operand:DI 2 "register_operand" "r"))]
2351 "TARGET_HAS_XFLOATING_LIBS"
2353 "&& reload_completed"
2355 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2357 (define_insn "*addsf_ieee"
2358 [(set (match_operand:SF 0 "register_operand" "=&f")
2359 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2360 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2361 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2362 "add%,%/ %R1,%R2,%0"
2363 [(set_attr "type" "fadd")
2364 (set_attr "trap" "yes")
2365 (set_attr "round_suffix" "normal")
2366 (set_attr "trap_suffix" "u_su_sui")])
2368 (define_insn "addsf3"
2369 [(set (match_operand:SF 0 "register_operand" "=f")
2370 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2371 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2373 "add%,%/ %R1,%R2,%0"
2374 [(set_attr "type" "fadd")
2375 (set_attr "trap" "yes")
2376 (set_attr "round_suffix" "normal")
2377 (set_attr "trap_suffix" "u_su_sui")])
2379 (define_insn "*adddf_ieee"
2380 [(set (match_operand:DF 0 "register_operand" "=&f")
2381 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2382 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2383 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2384 "add%-%/ %R1,%R2,%0"
2385 [(set_attr "type" "fadd")
2386 (set_attr "trap" "yes")
2387 (set_attr "round_suffix" "normal")
2388 (set_attr "trap_suffix" "u_su_sui")])
2390 (define_insn "adddf3"
2391 [(set (match_operand:DF 0 "register_operand" "=f")
2392 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2393 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2395 "add%-%/ %R1,%R2,%0"
2396 [(set_attr "type" "fadd")
2397 (set_attr "trap" "yes")
2398 (set_attr "round_suffix" "normal")
2399 (set_attr "trap_suffix" "u_su_sui")])
2401 (define_insn "*adddf_ext1"
2402 [(set (match_operand:DF 0 "register_operand" "=f")
2403 (plus:DF (float_extend:DF
2404 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2405 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2406 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2407 "add%-%/ %R1,%R2,%0"
2408 [(set_attr "type" "fadd")
2409 (set_attr "trap" "yes")
2410 (set_attr "round_suffix" "normal")
2411 (set_attr "trap_suffix" "u_su_sui")])
2413 (define_insn "*adddf_ext2"
2414 [(set (match_operand:DF 0 "register_operand" "=f")
2415 (plus:DF (float_extend:DF
2416 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2418 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2419 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2420 "add%-%/ %R1,%R2,%0"
2421 [(set_attr "type" "fadd")
2422 (set_attr "trap" "yes")
2423 (set_attr "round_suffix" "normal")
2424 (set_attr "trap_suffix" "u_su_sui")])
2426 (define_expand "addtf3"
2427 [(use (match_operand 0 "register_operand" ""))
2428 (use (match_operand 1 "general_operand" ""))
2429 (use (match_operand 2 "general_operand" ""))]
2430 "TARGET_HAS_XFLOATING_LIBS"
2431 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2433 ;; Define conversion operators between DFmode and SImode, using the cvtql
2434 ;; instruction. To allow combine et al to do useful things, we keep the
2435 ;; operation as a unit until after reload, at which point we split the
2438 ;; Note that we (attempt to) only consider this optimization when the
2439 ;; ultimate destination is memory. If we will be doing further integer
2440 ;; processing, it is cheaper to do the truncation in the int regs.
2442 (define_insn "*cvtql"
2443 [(set (match_operand:SI 0 "register_operand" "=f")
2444 (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")]
2448 [(set_attr "type" "fadd")
2449 (set_attr "trap" "yes")
2450 (set_attr "trap_suffix" "v_sv")])
2452 (define_insn_and_split "*fix_truncdfsi_ieee"
2453 [(set (match_operand:SI 0 "memory_operand" "=m")
2454 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2455 (clobber (match_scratch:DI 2 "=&f"))
2456 (clobber (match_scratch:SI 3 "=&f"))]
2457 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2459 "&& reload_completed"
2460 [(set (match_dup 2) (fix:DI (match_dup 1)))
2461 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2462 (set (match_dup 0) (match_dup 3))]
2464 [(set_attr "type" "fadd")
2465 (set_attr "trap" "yes")])
2467 (define_insn_and_split "*fix_truncdfsi_internal"
2468 [(set (match_operand:SI 0 "memory_operand" "=m")
2469 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2470 (clobber (match_scratch:DI 2 "=f"))]
2471 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2473 "&& reload_completed"
2474 [(set (match_dup 2) (fix:DI (match_dup 1)))
2475 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2476 (set (match_dup 0) (match_dup 3))]
2477 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2478 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2479 [(set_attr "type" "fadd")
2480 (set_attr "trap" "yes")])
2482 (define_insn "*fix_truncdfdi_ieee"
2483 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2484 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2485 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2487 [(set_attr "type" "fadd")
2488 (set_attr "trap" "yes")
2489 (set_attr "round_suffix" "c")
2490 (set_attr "trap_suffix" "v_sv_svi")])
2492 (define_insn "fix_truncdfdi2"
2493 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2494 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2497 [(set_attr "type" "fadd")
2498 (set_attr "trap" "yes")
2499 (set_attr "round_suffix" "c")
2500 (set_attr "trap_suffix" "v_sv_svi")])
2502 ;; Likewise between SFmode and SImode.
2504 (define_insn_and_split "*fix_truncsfsi_ieee"
2505 [(set (match_operand:SI 0 "memory_operand" "=m")
2506 (subreg:SI (fix:DI (float_extend:DF
2507 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2508 (clobber (match_scratch:DI 2 "=&f"))
2509 (clobber (match_scratch:SI 3 "=&f"))]
2510 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2512 "&& reload_completed"
2513 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2514 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2515 (set (match_dup 0) (match_dup 3))]
2517 [(set_attr "type" "fadd")
2518 (set_attr "trap" "yes")])
2520 (define_insn_and_split "*fix_truncsfsi_internal"
2521 [(set (match_operand:SI 0 "memory_operand" "=m")
2522 (subreg:SI (fix:DI (float_extend:DF
2523 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2524 (clobber (match_scratch:DI 2 "=f"))]
2525 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2527 "&& reload_completed"
2528 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2529 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2530 (set (match_dup 0) (match_dup 3))]
2531 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2532 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2533 [(set_attr "type" "fadd")
2534 (set_attr "trap" "yes")])
2536 (define_insn "*fix_truncsfdi_ieee"
2537 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2538 (fix:DI (float_extend:DF
2539 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2540 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2542 [(set_attr "type" "fadd")
2543 (set_attr "trap" "yes")
2544 (set_attr "round_suffix" "c")
2545 (set_attr "trap_suffix" "v_sv_svi")])
2547 (define_insn "fix_truncsfdi2"
2548 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2549 (fix:DI (float_extend:DF
2550 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2553 [(set_attr "type" "fadd")
2554 (set_attr "trap" "yes")
2555 (set_attr "round_suffix" "c")
2556 (set_attr "trap_suffix" "v_sv_svi")])
2558 (define_expand "fix_trunctfdi2"
2559 [(use (match_operand:DI 0 "register_operand" ""))
2560 (use (match_operand:TF 1 "general_operand" ""))]
2561 "TARGET_HAS_XFLOATING_LIBS"
2562 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2564 (define_insn "*floatdisf_ieee"
2565 [(set (match_operand:SF 0 "register_operand" "=&f")
2566 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2567 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2569 [(set_attr "type" "fadd")
2570 (set_attr "trap" "yes")
2571 (set_attr "round_suffix" "normal")
2572 (set_attr "trap_suffix" "sui")])
2574 (define_insn "floatdisf2"
2575 [(set (match_operand:SF 0 "register_operand" "=f")
2576 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2579 [(set_attr "type" "fadd")
2580 (set_attr "trap" "yes")
2581 (set_attr "round_suffix" "normal")
2582 (set_attr "trap_suffix" "sui")])
2584 (define_insn "*floatdidf_ieee"
2585 [(set (match_operand:DF 0 "register_operand" "=&f")
2586 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2587 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2589 [(set_attr "type" "fadd")
2590 (set_attr "trap" "yes")
2591 (set_attr "round_suffix" "normal")
2592 (set_attr "trap_suffix" "sui")])
2594 (define_insn "floatdidf2"
2595 [(set (match_operand:DF 0 "register_operand" "=f")
2596 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2599 [(set_attr "type" "fadd")
2600 (set_attr "trap" "yes")
2601 (set_attr "round_suffix" "normal")
2602 (set_attr "trap_suffix" "sui")])
2604 (define_expand "floatditf2"
2605 [(use (match_operand:TF 0 "register_operand" ""))
2606 (use (match_operand:DI 1 "general_operand" ""))]
2607 "TARGET_HAS_XFLOATING_LIBS"
2608 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2610 (define_expand "floatunsdisf2"
2611 [(use (match_operand:SF 0 "register_operand" ""))
2612 (use (match_operand:DI 1 "register_operand" ""))]
2614 "alpha_emit_floatuns (operands); DONE;")
2616 (define_expand "floatunsdidf2"
2617 [(use (match_operand:DF 0 "register_operand" ""))
2618 (use (match_operand:DI 1 "register_operand" ""))]
2620 "alpha_emit_floatuns (operands); DONE;")
2622 (define_expand "floatunsditf2"
2623 [(use (match_operand:TF 0 "register_operand" ""))
2624 (use (match_operand:DI 1 "general_operand" ""))]
2625 "TARGET_HAS_XFLOATING_LIBS"
2626 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2628 (define_expand "extendsfdf2"
2629 [(set (match_operand:DF 0 "register_operand" "")
2630 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2633 if (alpha_fptm >= ALPHA_FPTM_SU)
2634 operands[1] = force_reg (SFmode, operands[1]);
2637 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2638 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2640 (define_insn "*extendsfdf2_ieee"
2641 [(set (match_operand:DF 0 "register_operand" "=&f")
2642 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2643 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2645 [(set_attr "type" "fadd")
2646 (set_attr "trap" "yes")])
2648 (define_insn "*extendsfdf2_internal"
2649 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2650 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2651 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2656 [(set_attr "type" "fcpys,fld,fst")])
2658 (define_expand "extendsftf2"
2659 [(use (match_operand:TF 0 "register_operand" ""))
2660 (use (match_operand:SF 1 "general_operand" ""))]
2661 "TARGET_HAS_XFLOATING_LIBS"
2663 rtx tmp = gen_reg_rtx (DFmode);
2664 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2665 emit_insn (gen_extenddftf2 (operands[0], tmp));
2669 (define_expand "extenddftf2"
2670 [(use (match_operand:TF 0 "register_operand" ""))
2671 (use (match_operand:DF 1 "general_operand" ""))]
2672 "TARGET_HAS_XFLOATING_LIBS"
2673 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2675 (define_insn "*truncdfsf2_ieee"
2676 [(set (match_operand:SF 0 "register_operand" "=&f")
2677 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2678 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2680 [(set_attr "type" "fadd")
2681 (set_attr "trap" "yes")
2682 (set_attr "round_suffix" "normal")
2683 (set_attr "trap_suffix" "u_su_sui")])
2685 (define_insn "truncdfsf2"
2686 [(set (match_operand:SF 0 "register_operand" "=f")
2687 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2690 [(set_attr "type" "fadd")
2691 (set_attr "trap" "yes")
2692 (set_attr "round_suffix" "normal")
2693 (set_attr "trap_suffix" "u_su_sui")])
2695 (define_expand "trunctfdf2"
2696 [(use (match_operand:DF 0 "register_operand" ""))
2697 (use (match_operand:TF 1 "general_operand" ""))]
2698 "TARGET_HAS_XFLOATING_LIBS"
2699 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2701 (define_expand "trunctfsf2"
2702 [(use (match_operand:SF 0 "register_operand" ""))
2703 (use (match_operand:TF 1 "general_operand" ""))]
2704 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2706 rtx tmpf, sticky, arg, lo, hi;
2708 tmpf = gen_reg_rtx (DFmode);
2709 sticky = gen_reg_rtx (DImode);
2710 arg = copy_to_mode_reg (TFmode, operands[1]);
2711 lo = gen_lowpart (DImode, arg);
2712 hi = gen_highpart (DImode, arg);
2714 /* Convert the low word of the TFmode value into a sticky rounding bit,
2715 then or it into the low bit of the high word. This leaves the sticky
2716 bit at bit 48 of the fraction, which is representable in DFmode,
2717 which prevents rounding error in the final conversion to SFmode. */
2719 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2720 gen_rtx_NE (DImode, lo, const0_rtx)));
2721 emit_insn (gen_iordi3 (hi, hi, sticky));
2722 emit_insn (gen_trunctfdf2 (tmpf, arg));
2723 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2727 (define_insn "*divsf3_ieee"
2728 [(set (match_operand:SF 0 "register_operand" "=&f")
2729 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2730 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2731 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2732 "div%,%/ %R1,%R2,%0"
2733 [(set_attr "type" "fdiv")
2734 (set_attr "opsize" "si")
2735 (set_attr "trap" "yes")
2736 (set_attr "round_suffix" "normal")
2737 (set_attr "trap_suffix" "u_su_sui")])
2739 (define_insn "divsf3"
2740 [(set (match_operand:SF 0 "register_operand" "=f")
2741 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2742 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2744 "div%,%/ %R1,%R2,%0"
2745 [(set_attr "type" "fdiv")
2746 (set_attr "opsize" "si")
2747 (set_attr "trap" "yes")
2748 (set_attr "round_suffix" "normal")
2749 (set_attr "trap_suffix" "u_su_sui")])
2751 (define_insn "*divdf3_ieee"
2752 [(set (match_operand:DF 0 "register_operand" "=&f")
2753 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2754 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2755 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2756 "div%-%/ %R1,%R2,%0"
2757 [(set_attr "type" "fdiv")
2758 (set_attr "trap" "yes")
2759 (set_attr "round_suffix" "normal")
2760 (set_attr "trap_suffix" "u_su_sui")])
2762 (define_insn "divdf3"
2763 [(set (match_operand:DF 0 "register_operand" "=f")
2764 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2765 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2767 "div%-%/ %R1,%R2,%0"
2768 [(set_attr "type" "fdiv")
2769 (set_attr "trap" "yes")
2770 (set_attr "round_suffix" "normal")
2771 (set_attr "trap_suffix" "u_su_sui")])
2773 (define_insn "*divdf_ext1"
2774 [(set (match_operand:DF 0 "register_operand" "=f")
2775 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2776 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2777 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2778 "div%-%/ %R1,%R2,%0"
2779 [(set_attr "type" "fdiv")
2780 (set_attr "trap" "yes")
2781 (set_attr "round_suffix" "normal")
2782 (set_attr "trap_suffix" "u_su_sui")])
2784 (define_insn "*divdf_ext2"
2785 [(set (match_operand:DF 0 "register_operand" "=f")
2786 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2788 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2789 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2790 "div%-%/ %R1,%R2,%0"
2791 [(set_attr "type" "fdiv")
2792 (set_attr "trap" "yes")
2793 (set_attr "round_suffix" "normal")
2794 (set_attr "trap_suffix" "u_su_sui")])
2796 (define_insn "*divdf_ext3"
2797 [(set (match_operand:DF 0 "register_operand" "=f")
2798 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2799 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2800 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2801 "div%-%/ %R1,%R2,%0"
2802 [(set_attr "type" "fdiv")
2803 (set_attr "trap" "yes")
2804 (set_attr "round_suffix" "normal")
2805 (set_attr "trap_suffix" "u_su_sui")])
2807 (define_expand "divtf3"
2808 [(use (match_operand 0 "register_operand" ""))
2809 (use (match_operand 1 "general_operand" ""))
2810 (use (match_operand 2 "general_operand" ""))]
2811 "TARGET_HAS_XFLOATING_LIBS"
2812 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2814 (define_insn "*mulsf3_ieee"
2815 [(set (match_operand:SF 0 "register_operand" "=&f")
2816 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2817 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2818 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2819 "mul%,%/ %R1,%R2,%0"
2820 [(set_attr "type" "fmul")
2821 (set_attr "trap" "yes")
2822 (set_attr "round_suffix" "normal")
2823 (set_attr "trap_suffix" "u_su_sui")])
2825 (define_insn "mulsf3"
2826 [(set (match_operand:SF 0 "register_operand" "=f")
2827 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2828 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2830 "mul%,%/ %R1,%R2,%0"
2831 [(set_attr "type" "fmul")
2832 (set_attr "trap" "yes")
2833 (set_attr "round_suffix" "normal")
2834 (set_attr "trap_suffix" "u_su_sui")])
2836 (define_insn "*muldf3_ieee"
2837 [(set (match_operand:DF 0 "register_operand" "=&f")
2838 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2839 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2840 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2841 "mul%-%/ %R1,%R2,%0"
2842 [(set_attr "type" "fmul")
2843 (set_attr "trap" "yes")
2844 (set_attr "round_suffix" "normal")
2845 (set_attr "trap_suffix" "u_su_sui")])
2847 (define_insn "muldf3"
2848 [(set (match_operand:DF 0 "register_operand" "=f")
2849 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2850 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2852 "mul%-%/ %R1,%R2,%0"
2853 [(set_attr "type" "fmul")
2854 (set_attr "trap" "yes")
2855 (set_attr "round_suffix" "normal")
2856 (set_attr "trap_suffix" "u_su_sui")])
2858 (define_insn "*muldf_ext1"
2859 [(set (match_operand:DF 0 "register_operand" "=f")
2860 (mult:DF (float_extend:DF
2861 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2862 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2863 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2864 "mul%-%/ %R1,%R2,%0"
2865 [(set_attr "type" "fmul")
2866 (set_attr "trap" "yes")
2867 (set_attr "round_suffix" "normal")
2868 (set_attr "trap_suffix" "u_su_sui")])
2870 (define_insn "*muldf_ext2"
2871 [(set (match_operand:DF 0 "register_operand" "=f")
2872 (mult:DF (float_extend:DF
2873 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2875 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2876 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2877 "mul%-%/ %R1,%R2,%0"
2878 [(set_attr "type" "fmul")
2879 (set_attr "trap" "yes")
2880 (set_attr "round_suffix" "normal")
2881 (set_attr "trap_suffix" "u_su_sui")])
2883 (define_expand "multf3"
2884 [(use (match_operand 0 "register_operand" ""))
2885 (use (match_operand 1 "general_operand" ""))
2886 (use (match_operand 2 "general_operand" ""))]
2887 "TARGET_HAS_XFLOATING_LIBS"
2888 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2890 (define_insn "*subsf3_ieee"
2891 [(set (match_operand:SF 0 "register_operand" "=&f")
2892 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2893 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2894 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2895 "sub%,%/ %R1,%R2,%0"
2896 [(set_attr "type" "fadd")
2897 (set_attr "trap" "yes")
2898 (set_attr "round_suffix" "normal")
2899 (set_attr "trap_suffix" "u_su_sui")])
2901 (define_insn "subsf3"
2902 [(set (match_operand:SF 0 "register_operand" "=f")
2903 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2904 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2906 "sub%,%/ %R1,%R2,%0"
2907 [(set_attr "type" "fadd")
2908 (set_attr "trap" "yes")
2909 (set_attr "round_suffix" "normal")
2910 (set_attr "trap_suffix" "u_su_sui")])
2912 (define_insn "*subdf3_ieee"
2913 [(set (match_operand:DF 0 "register_operand" "=&f")
2914 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2915 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2916 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2917 "sub%-%/ %R1,%R2,%0"
2918 [(set_attr "type" "fadd")
2919 (set_attr "trap" "yes")
2920 (set_attr "round_suffix" "normal")
2921 (set_attr "trap_suffix" "u_su_sui")])
2923 (define_insn "subdf3"
2924 [(set (match_operand:DF 0 "register_operand" "=f")
2925 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2926 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2928 "sub%-%/ %R1,%R2,%0"
2929 [(set_attr "type" "fadd")
2930 (set_attr "trap" "yes")
2931 (set_attr "round_suffix" "normal")
2932 (set_attr "trap_suffix" "u_su_sui")])
2934 (define_insn "*subdf_ext1"
2935 [(set (match_operand:DF 0 "register_operand" "=f")
2936 (minus:DF (float_extend:DF
2937 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2938 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2939 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2940 "sub%-%/ %R1,%R2,%0"
2941 [(set_attr "type" "fadd")
2942 (set_attr "trap" "yes")
2943 (set_attr "round_suffix" "normal")
2944 (set_attr "trap_suffix" "u_su_sui")])
2946 (define_insn "*subdf_ext2"
2947 [(set (match_operand:DF 0 "register_operand" "=f")
2948 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2950 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2951 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2952 "sub%-%/ %R1,%R2,%0"
2953 [(set_attr "type" "fadd")
2954 (set_attr "trap" "yes")
2955 (set_attr "round_suffix" "normal")
2956 (set_attr "trap_suffix" "u_su_sui")])
2958 (define_insn "*subdf_ext3"
2959 [(set (match_operand:DF 0 "register_operand" "=f")
2960 (minus:DF (float_extend:DF
2961 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2963 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2964 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2965 "sub%-%/ %R1,%R2,%0"
2966 [(set_attr "type" "fadd")
2967 (set_attr "trap" "yes")
2968 (set_attr "round_suffix" "normal")
2969 (set_attr "trap_suffix" "u_su_sui")])
2971 (define_expand "subtf3"
2972 [(use (match_operand 0 "register_operand" ""))
2973 (use (match_operand 1 "general_operand" ""))
2974 (use (match_operand 2 "general_operand" ""))]
2975 "TARGET_HAS_XFLOATING_LIBS"
2976 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
2978 (define_insn "*sqrtsf2_ieee"
2979 [(set (match_operand:SF 0 "register_operand" "=&f")
2980 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2981 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2983 [(set_attr "type" "fsqrt")
2984 (set_attr "opsize" "si")
2985 (set_attr "trap" "yes")
2986 (set_attr "round_suffix" "normal")
2987 (set_attr "trap_suffix" "u_su_sui")])
2989 (define_insn "sqrtsf2"
2990 [(set (match_operand:SF 0 "register_operand" "=f")
2991 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2992 "TARGET_FP && TARGET_FIX"
2994 [(set_attr "type" "fsqrt")
2995 (set_attr "opsize" "si")
2996 (set_attr "trap" "yes")
2997 (set_attr "round_suffix" "normal")
2998 (set_attr "trap_suffix" "u_su_sui")])
3000 (define_insn "*sqrtdf2_ieee"
3001 [(set (match_operand:DF 0 "register_operand" "=&f")
3002 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
3003 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3005 [(set_attr "type" "fsqrt")
3006 (set_attr "trap" "yes")
3007 (set_attr "round_suffix" "normal")
3008 (set_attr "trap_suffix" "u_su_sui")])
3010 (define_insn "sqrtdf2"
3011 [(set (match_operand:DF 0 "register_operand" "=f")
3012 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
3013 "TARGET_FP && TARGET_FIX"
3015 [(set_attr "type" "fsqrt")
3016 (set_attr "trap" "yes")
3017 (set_attr "round_suffix" "normal")
3018 (set_attr "trap_suffix" "u_su_sui")])
3020 ;; Next are all the integer comparisons, and conditional moves and branches
3021 ;; and some of the related define_expand's and define_split's.
3023 (define_insn "*setcc_internal"
3024 [(set (match_operand 0 "register_operand" "=r")
3025 (match_operator 1 "alpha_comparison_operator"
3026 [(match_operand:DI 2 "register_operand" "r")
3027 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
3028 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3029 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3030 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3032 [(set_attr "type" "icmp")])
3034 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
3035 ;; but that's non-canonical rtl and allowing that causes inefficiencies
3037 (define_insn "*setcc_swapped_internal"
3038 [(set (match_operand 0 "register_operand" "=r")
3039 (match_operator 1 "alpha_swapped_comparison_operator"
3040 [(match_operand:DI 2 "register_operand" "r")
3041 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
3042 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3043 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3044 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3046 [(set_attr "type" "icmp")])
3048 ;; Use match_operator rather than ne directly so that we can match
3049 ;; multiple integer modes.
3050 (define_insn "*setne_internal"
3051 [(set (match_operand 0 "register_operand" "=r")
3052 (match_operator 1 "signed_comparison_operator"
3053 [(match_operand:DI 2 "register_operand" "r")
3055 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3056 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3057 && GET_CODE (operands[1]) == NE
3058 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3060 [(set_attr "type" "icmp")])
3062 ;; The mode folding trick can't be used with const_int operands, since
3063 ;; reload needs to know the proper mode.
3065 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
3066 ;; in order to create more pairs of constants. As long as we're allowing
3067 ;; two constants at the same time, and will have to reload one of them...
3069 (define_insn "*movqicc_internal"
3070 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
3072 (match_operator 2 "signed_comparison_operator"
3073 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3074 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3075 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
3076 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
3077 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3083 [(set_attr "type" "icmov")])
3085 (define_insn "*movhicc_internal"
3086 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
3088 (match_operator 2 "signed_comparison_operator"
3089 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3090 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3091 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
3092 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
3093 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3099 [(set_attr "type" "icmov")])
3101 (define_insn "*movsicc_internal"
3102 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
3104 (match_operator 2 "signed_comparison_operator"
3105 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3106 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3107 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
3108 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
3109 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3115 [(set_attr "type" "icmov")])
3117 (define_insn "*movdicc_internal"
3118 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
3120 (match_operator 2 "signed_comparison_operator"
3121 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3122 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3123 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
3124 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
3125 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3131 [(set_attr "type" "icmov")])
3133 (define_insn "*movqicc_lbc"
3134 [(set (match_operand:QI 0 "register_operand" "=r,r")
3136 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3140 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3141 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3146 [(set_attr "type" "icmov")])
3148 (define_insn "*movhicc_lbc"
3149 [(set (match_operand:HI 0 "register_operand" "=r,r")
3151 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3155 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3156 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3161 [(set_attr "type" "icmov")])
3163 (define_insn "*movsicc_lbc"
3164 [(set (match_operand:SI 0 "register_operand" "=r,r")
3166 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3170 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3171 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3176 [(set_attr "type" "icmov")])
3178 (define_insn "*movdicc_lbc"
3179 [(set (match_operand:DI 0 "register_operand" "=r,r")
3181 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3185 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3186 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3191 [(set_attr "type" "icmov")])
3193 (define_insn "*movqicc_lbs"
3194 [(set (match_operand:QI 0 "register_operand" "=r,r")
3196 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3200 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3201 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3206 [(set_attr "type" "icmov")])
3208 (define_insn "*movhicc_lbs"
3209 [(set (match_operand:HI 0 "register_operand" "=r,r")
3211 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3215 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3216 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3221 [(set_attr "type" "icmov")])
3223 (define_insn "*movsicc_lbs"
3224 [(set (match_operand:SI 0 "register_operand" "=r,r")
3226 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3230 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3231 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3236 [(set_attr "type" "icmov")])
3238 (define_insn "*movdicc_lbs"
3239 [(set (match_operand:DI 0 "register_operand" "=r,r")
3241 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3245 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3246 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3251 [(set_attr "type" "icmov")])
3253 ;; For ABS, we have two choices, depending on whether the input and output
3254 ;; registers are the same or not.
3255 (define_expand "absdi2"
3256 [(set (match_operand:DI 0 "register_operand" "")
3257 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3260 if (rtx_equal_p (operands[0], operands[1]))
3261 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3263 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3267 (define_expand "absdi2_same"
3268 [(set (match_operand:DI 1 "register_operand" "")
3269 (neg:DI (match_operand:DI 0 "register_operand" "")))
3271 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3277 (define_expand "absdi2_diff"
3278 [(set (match_operand:DI 0 "register_operand" "")
3279 (neg:DI (match_operand:DI 1 "register_operand" "")))
3281 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3288 [(set (match_operand:DI 0 "register_operand" "")
3289 (abs:DI (match_dup 0)))
3290 (clobber (match_operand:DI 1 "register_operand" ""))]
3292 [(set (match_dup 1) (neg:DI (match_dup 0)))
3293 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3294 (match_dup 0) (match_dup 1)))]
3298 [(set (match_operand:DI 0 "register_operand" "")
3299 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3300 "! rtx_equal_p (operands[0], operands[1])"
3301 [(set (match_dup 0) (neg:DI (match_dup 1)))
3302 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3303 (match_dup 0) (match_dup 1)))]
3307 [(set (match_operand:DI 0 "register_operand" "")
3308 (neg:DI (abs:DI (match_dup 0))))
3309 (clobber (match_operand:DI 1 "register_operand" ""))]
3311 [(set (match_dup 1) (neg:DI (match_dup 0)))
3312 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3313 (match_dup 0) (match_dup 1)))]
3317 [(set (match_operand:DI 0 "register_operand" "")
3318 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3319 "! rtx_equal_p (operands[0], operands[1])"
3320 [(set (match_dup 0) (neg:DI (match_dup 1)))
3321 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3322 (match_dup 0) (match_dup 1)))]
3325 (define_insn "sminqi3"
3326 [(set (match_operand:QI 0 "register_operand" "=r")
3327 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3328 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3331 [(set_attr "type" "mvi")])
3333 (define_insn "uminqi3"
3334 [(set (match_operand:QI 0 "register_operand" "=r")
3335 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3336 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3339 [(set_attr "type" "mvi")])
3341 (define_insn "smaxqi3"
3342 [(set (match_operand:QI 0 "register_operand" "=r")
3343 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3344 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3347 [(set_attr "type" "mvi")])
3349 (define_insn "umaxqi3"
3350 [(set (match_operand:QI 0 "register_operand" "=r")
3351 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3352 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3355 [(set_attr "type" "mvi")])
3357 (define_insn "sminhi3"
3358 [(set (match_operand:HI 0 "register_operand" "=r")
3359 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3360 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3363 [(set_attr "type" "mvi")])
3365 (define_insn "uminhi3"
3366 [(set (match_operand:HI 0 "register_operand" "=r")
3367 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3368 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3371 [(set_attr "type" "mvi")])
3373 (define_insn "smaxhi3"
3374 [(set (match_operand:HI 0 "register_operand" "=r")
3375 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3376 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3379 [(set_attr "type" "mvi")])
3381 (define_insn "umaxhi3"
3382 [(set (match_operand:HI 0 "register_operand" "=r")
3383 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3384 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3387 [(set_attr "type" "shift")])
3389 (define_expand "smaxdi3"
3391 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3392 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3393 (set (match_operand:DI 0 "register_operand" "")
3394 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3395 (match_dup 1) (match_dup 2)))]
3397 { operands[3] = gen_reg_rtx (DImode); })
3400 [(set (match_operand:DI 0 "register_operand" "")
3401 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3402 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3403 (clobber (match_operand:DI 3 "register_operand" ""))]
3404 "operands[2] != const0_rtx"
3405 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3406 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3407 (match_dup 1) (match_dup 2)))]
3410 (define_insn "*smax_const0"
3411 [(set (match_operand:DI 0 "register_operand" "=r")
3412 (smax:DI (match_operand:DI 1 "register_operand" "0")
3416 [(set_attr "type" "icmov")])
3418 (define_expand "smindi3"
3420 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3421 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3422 (set (match_operand:DI 0 "register_operand" "")
3423 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3424 (match_dup 1) (match_dup 2)))]
3426 { operands[3] = gen_reg_rtx (DImode); })
3429 [(set (match_operand:DI 0 "register_operand" "")
3430 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3431 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3432 (clobber (match_operand:DI 3 "register_operand" ""))]
3433 "operands[2] != const0_rtx"
3434 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3435 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3436 (match_dup 1) (match_dup 2)))]
3439 (define_insn "*smin_const0"
3440 [(set (match_operand:DI 0 "register_operand" "=r")
3441 (smin:DI (match_operand:DI 1 "register_operand" "0")
3445 [(set_attr "type" "icmov")])
3447 (define_expand "umaxdi3"
3449 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3450 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3451 (set (match_operand:DI 0 "register_operand" "")
3452 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3453 (match_dup 1) (match_dup 2)))]
3455 "operands[3] = gen_reg_rtx (DImode);")
3458 [(set (match_operand:DI 0 "register_operand" "")
3459 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3460 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3461 (clobber (match_operand:DI 3 "register_operand" ""))]
3462 "operands[2] != const0_rtx"
3463 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3464 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3465 (match_dup 1) (match_dup 2)))]
3468 (define_expand "umindi3"
3470 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3471 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3472 (set (match_operand:DI 0 "register_operand" "")
3473 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3474 (match_dup 1) (match_dup 2)))]
3476 "operands[3] = gen_reg_rtx (DImode);")
3479 [(set (match_operand:DI 0 "register_operand" "")
3480 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3481 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3482 (clobber (match_operand:DI 3 "register_operand" ""))]
3483 "operands[2] != const0_rtx"
3484 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3485 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3486 (match_dup 1) (match_dup 2)))]
3489 (define_insn "*bcc_normal"
3492 (match_operator 1 "signed_comparison_operator"
3493 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3495 (label_ref (match_operand 0 "" ""))
3499 [(set_attr "type" "ibr")])
3501 (define_insn "*bcc_reverse"
3504 (match_operator 1 "signed_comparison_operator"
3505 [(match_operand:DI 2 "register_operand" "r")
3509 (label_ref (match_operand 0 "" ""))))]
3512 [(set_attr "type" "ibr")])
3514 (define_insn "*blbs_normal"
3517 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3521 (label_ref (match_operand 0 "" ""))
3525 [(set_attr "type" "ibr")])
3527 (define_insn "*blbc_normal"
3530 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3534 (label_ref (match_operand 0 "" ""))
3538 [(set_attr "type" "ibr")])
3544 (match_operator 1 "comparison_operator"
3545 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3547 (match_operand:DI 3 "const_int_operand" ""))
3549 (label_ref (match_operand 0 "" ""))
3551 (clobber (match_operand:DI 4 "register_operand" ""))])]
3552 "INTVAL (operands[3]) != 0"
3554 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3556 (if_then_else (match_op_dup 1
3557 [(zero_extract:DI (match_dup 4)
3561 (label_ref (match_dup 0))
3565 ;; The following are the corresponding floating-point insns. Recall
3566 ;; we need to have variants that expand the arguments from SFmode
3569 (define_insn "*cmpdf_ieee"
3570 [(set (match_operand:DF 0 "register_operand" "=&f")
3571 (match_operator:DF 1 "alpha_fp_comparison_operator"
3572 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3573 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3574 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3575 "cmp%-%C1%/ %R2,%R3,%0"
3576 [(set_attr "type" "fadd")
3577 (set_attr "trap" "yes")
3578 (set_attr "trap_suffix" "su")])
3580 (define_insn "*cmpdf_internal"
3581 [(set (match_operand:DF 0 "register_operand" "=f")
3582 (match_operator:DF 1 "alpha_fp_comparison_operator"
3583 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3584 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3585 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3586 "cmp%-%C1%/ %R2,%R3,%0"
3587 [(set_attr "type" "fadd")
3588 (set_attr "trap" "yes")
3589 (set_attr "trap_suffix" "su")])
3591 (define_insn "*cmpdf_ieee_ext1"
3592 [(set (match_operand:DF 0 "register_operand" "=&f")
3593 (match_operator:DF 1 "alpha_fp_comparison_operator"
3595 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3596 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3597 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3598 "cmp%-%C1%/ %R2,%R3,%0"
3599 [(set_attr "type" "fadd")
3600 (set_attr "trap" "yes")
3601 (set_attr "trap_suffix" "su")])
3603 (define_insn "*cmpdf_ext1"
3604 [(set (match_operand:DF 0 "register_operand" "=f")
3605 (match_operator:DF 1 "alpha_fp_comparison_operator"
3607 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3608 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3609 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3610 "cmp%-%C1%/ %R2,%R3,%0"
3611 [(set_attr "type" "fadd")
3612 (set_attr "trap" "yes")
3613 (set_attr "trap_suffix" "su")])
3615 (define_insn "*cmpdf_ieee_ext2"
3616 [(set (match_operand:DF 0 "register_operand" "=&f")
3617 (match_operator:DF 1 "alpha_fp_comparison_operator"
3618 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3620 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3621 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3622 "cmp%-%C1%/ %R2,%R3,%0"
3623 [(set_attr "type" "fadd")
3624 (set_attr "trap" "yes")
3625 (set_attr "trap_suffix" "su")])
3627 (define_insn "*cmpdf_ext2"
3628 [(set (match_operand:DF 0 "register_operand" "=f")
3629 (match_operator:DF 1 "alpha_fp_comparison_operator"
3630 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3632 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3633 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3634 "cmp%-%C1%/ %R2,%R3,%0"
3635 [(set_attr "type" "fadd")
3636 (set_attr "trap" "yes")
3637 (set_attr "trap_suffix" "su")])
3639 (define_insn "*cmpdf_ieee_ext3"
3640 [(set (match_operand:DF 0 "register_operand" "=&f")
3641 (match_operator:DF 1 "alpha_fp_comparison_operator"
3643 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3645 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3646 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3647 "cmp%-%C1%/ %R2,%R3,%0"
3648 [(set_attr "type" "fadd")
3649 (set_attr "trap" "yes")
3650 (set_attr "trap_suffix" "su")])
3652 (define_insn "*cmpdf_ext3"
3653 [(set (match_operand:DF 0 "register_operand" "=f")
3654 (match_operator:DF 1 "alpha_fp_comparison_operator"
3656 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3658 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3659 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3660 "cmp%-%C1%/ %R2,%R3,%0"
3661 [(set_attr "type" "fadd")
3662 (set_attr "trap" "yes")
3663 (set_attr "trap_suffix" "su")])
3665 (define_insn "*movdfcc_internal"
3666 [(set (match_operand:DF 0 "register_operand" "=f,f")
3668 (match_operator 3 "signed_comparison_operator"
3669 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3670 (match_operand:DF 2 "fp0_operand" "G,G")])
3671 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3672 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3676 fcmov%D3 %R4,%R5,%0"
3677 [(set_attr "type" "fcmov")])
3679 (define_insn "*movsfcc_internal"
3680 [(set (match_operand:SF 0 "register_operand" "=f,f")
3682 (match_operator 3 "signed_comparison_operator"
3683 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3684 (match_operand:DF 2 "fp0_operand" "G,G")])
3685 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3686 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3690 fcmov%D3 %R4,%R5,%0"
3691 [(set_attr "type" "fcmov")])
3693 (define_insn "*movdfcc_ext1"
3694 [(set (match_operand:DF 0 "register_operand" "=f,f")
3696 (match_operator 3 "signed_comparison_operator"
3697 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3698 (match_operand:DF 2 "fp0_operand" "G,G")])
3699 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3700 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3704 fcmov%D3 %R4,%R5,%0"
3705 [(set_attr "type" "fcmov")])
3707 (define_insn "*movdfcc_ext2"
3708 [(set (match_operand:DF 0 "register_operand" "=f,f")
3710 (match_operator 3 "signed_comparison_operator"
3712 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3713 (match_operand:DF 2 "fp0_operand" "G,G")])
3714 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3715 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3719 fcmov%D3 %R4,%R5,%0"
3720 [(set_attr "type" "fcmov")])
3722 (define_insn "*movdfcc_ext3"
3723 [(set (match_operand:SF 0 "register_operand" "=f,f")
3725 (match_operator 3 "signed_comparison_operator"
3727 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3728 (match_operand:DF 2 "fp0_operand" "G,G")])
3729 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3730 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3734 fcmov%D3 %R4,%R5,%0"
3735 [(set_attr "type" "fcmov")])
3737 (define_insn "*movdfcc_ext4"
3738 [(set (match_operand:DF 0 "register_operand" "=f,f")
3740 (match_operator 3 "signed_comparison_operator"
3742 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3743 (match_operand:DF 2 "fp0_operand" "G,G")])
3744 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3745 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3749 fcmov%D3 %R4,%R5,%0"
3750 [(set_attr "type" "fcmov")])
3752 (define_expand "maxdf3"
3754 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3755 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3756 (set (match_operand:DF 0 "register_operand" "")
3757 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3758 (match_dup 1) (match_dup 2)))]
3761 operands[3] = gen_reg_rtx (DFmode);
3762 operands[4] = CONST0_RTX (DFmode);
3765 (define_expand "mindf3"
3767 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3768 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3769 (set (match_operand:DF 0 "register_operand" "")
3770 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3771 (match_dup 1) (match_dup 2)))]
3774 operands[3] = gen_reg_rtx (DFmode);
3775 operands[4] = CONST0_RTX (DFmode);
3778 (define_expand "maxsf3"
3780 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3781 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3782 (set (match_operand:SF 0 "register_operand" "")
3783 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3784 (match_dup 1) (match_dup 2)))]
3787 operands[3] = gen_reg_rtx (DFmode);
3788 operands[4] = CONST0_RTX (DFmode);
3791 (define_expand "minsf3"
3793 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3794 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3795 (set (match_operand:SF 0 "register_operand" "")
3796 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3797 (match_dup 1) (match_dup 2)))]
3800 operands[3] = gen_reg_rtx (DFmode);
3801 operands[4] = CONST0_RTX (DFmode);
3804 (define_insn "*fbcc_normal"
3807 (match_operator 1 "signed_comparison_operator"
3808 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3809 (match_operand:DF 3 "fp0_operand" "G")])
3810 (label_ref (match_operand 0 "" ""))
3814 [(set_attr "type" "fbr")])
3816 (define_insn "*fbcc_ext_normal"
3819 (match_operator 1 "signed_comparison_operator"
3821 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3822 (match_operand:DF 3 "fp0_operand" "G")])
3823 (label_ref (match_operand 0 "" ""))
3827 [(set_attr "type" "fbr")])
3829 ;; These are the main define_expand's used to make conditional branches
3832 (define_expand "cmpdf"
3833 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
3834 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
3837 alpha_compare.op0 = operands[0];
3838 alpha_compare.op1 = operands[1];
3839 alpha_compare.fp_p = 1;
3843 (define_expand "cmptf"
3844 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3845 (match_operand:TF 1 "general_operand" "")))]
3846 "TARGET_HAS_XFLOATING_LIBS"
3848 alpha_compare.op0 = operands[0];
3849 alpha_compare.op1 = operands[1];
3850 alpha_compare.fp_p = 1;
3854 (define_expand "cmpdi"
3855 [(set (cc0) (compare (match_operand:DI 0 "general_operand" "")
3856 (match_operand:DI 1 "general_operand" "")))]
3859 alpha_compare.op0 = operands[0];
3860 alpha_compare.op1 = operands[1];
3861 alpha_compare.fp_p = 0;
3865 (define_expand "beq"
3867 (if_then_else (match_dup 1)
3868 (label_ref (match_operand 0 "" ""))
3871 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3873 (define_expand "bne"
3875 (if_then_else (match_dup 1)
3876 (label_ref (match_operand 0 "" ""))
3879 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3881 (define_expand "blt"
3883 (if_then_else (match_dup 1)
3884 (label_ref (match_operand 0 "" ""))
3887 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3889 (define_expand "ble"
3891 (if_then_else (match_dup 1)
3892 (label_ref (match_operand 0 "" ""))
3895 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3897 (define_expand "bgt"
3899 (if_then_else (match_dup 1)
3900 (label_ref (match_operand 0 "" ""))
3903 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3905 (define_expand "bge"
3907 (if_then_else (match_dup 1)
3908 (label_ref (match_operand 0 "" ""))
3911 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3913 (define_expand "bltu"
3915 (if_then_else (match_dup 1)
3916 (label_ref (match_operand 0 "" ""))
3919 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3921 (define_expand "bleu"
3923 (if_then_else (match_dup 1)
3924 (label_ref (match_operand 0 "" ""))
3927 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3929 (define_expand "bgtu"
3931 (if_then_else (match_dup 1)
3932 (label_ref (match_operand 0 "" ""))
3935 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3937 (define_expand "bgeu"
3939 (if_then_else (match_dup 1)
3940 (label_ref (match_operand 0 "" ""))
3943 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3945 (define_expand "bunordered"
3947 (if_then_else (match_dup 1)
3948 (label_ref (match_operand 0 "" ""))
3951 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3953 (define_expand "bordered"
3955 (if_then_else (match_dup 1)
3956 (label_ref (match_operand 0 "" ""))
3959 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3961 (define_expand "seq"
3962 [(set (match_operand:DI 0 "register_operand" "")
3965 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
3967 (define_expand "sne"
3968 [(set (match_operand:DI 0 "register_operand" "")
3971 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
3973 (define_expand "slt"
3974 [(set (match_operand:DI 0 "register_operand" "")
3977 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
3979 (define_expand "sle"
3980 [(set (match_operand:DI 0 "register_operand" "")
3983 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
3985 (define_expand "sgt"
3986 [(set (match_operand:DI 0 "register_operand" "")
3989 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
3991 (define_expand "sge"
3992 [(set (match_operand:DI 0 "register_operand" "")
3995 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
3997 (define_expand "sltu"
3998 [(set (match_operand:DI 0 "register_operand" "")
4001 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
4003 (define_expand "sleu"
4004 [(set (match_operand:DI 0 "register_operand" "")
4007 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
4009 (define_expand "sgtu"
4010 [(set (match_operand:DI 0 "register_operand" "")
4013 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
4015 (define_expand "sgeu"
4016 [(set (match_operand:DI 0 "register_operand" "")
4019 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
4021 (define_expand "sunordered"
4022 [(set (match_operand:DI 0 "register_operand" "")
4025 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
4027 (define_expand "sordered"
4028 [(set (match_operand:DI 0 "register_operand" "")
4031 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
4033 ;; These are the main define_expand's used to make conditional moves.
4035 (define_expand "movsicc"
4036 [(set (match_operand:SI 0 "register_operand" "")
4037 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4038 (match_operand:SI 2 "reg_or_8bit_operand" "")
4039 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
4042 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
4046 (define_expand "movdicc"
4047 [(set (match_operand:DI 0 "register_operand" "")
4048 (if_then_else:DI (match_operand 1 "comparison_operator" "")
4049 (match_operand:DI 2 "reg_or_8bit_operand" "")
4050 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
4053 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
4057 (define_expand "movsfcc"
4058 [(set (match_operand:SF 0 "register_operand" "")
4059 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4060 (match_operand:SF 2 "reg_or_8bit_operand" "")
4061 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
4064 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
4068 (define_expand "movdfcc"
4069 [(set (match_operand:DF 0 "register_operand" "")
4070 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4071 (match_operand:DF 2 "reg_or_8bit_operand" "")
4072 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
4075 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
4079 ;; These define_split definitions are used in cases when comparisons have
4080 ;; not be stated in the correct way and we need to reverse the second
4081 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
4082 ;; comparison that tests the result being reversed. We have one define_split
4083 ;; for each use of a comparison. They do not match valid insns and need
4084 ;; not generate valid insns.
4086 ;; We can also handle equality comparisons (and inequality comparisons in
4087 ;; cases where the resulting add cannot overflow) by doing an add followed by
4088 ;; a comparison with zero. This is faster since the addition takes one
4089 ;; less cycle than a compare when feeding into a conditional move.
4090 ;; For this case, we also have an SImode pattern since we can merge the add
4091 ;; and sign extend and the order doesn't matter.
4093 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
4094 ;; operation could have been generated.
4097 [(set (match_operand:DI 0 "register_operand" "")
4099 (match_operator 1 "comparison_operator"
4100 [(match_operand:DI 2 "reg_or_0_operand" "")
4101 (match_operand:DI 3 "reg_or_cint_operand" "")])
4102 (match_operand:DI 4 "reg_or_cint_operand" "")
4103 (match_operand:DI 5 "reg_or_cint_operand" "")))
4104 (clobber (match_operand:DI 6 "register_operand" ""))]
4105 "operands[3] != const0_rtx"
4106 [(set (match_dup 6) (match_dup 7))
4108 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4110 enum rtx_code code = GET_CODE (operands[1]);
4111 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4113 /* If we are comparing for equality with a constant and that constant
4114 appears in the arm when the register equals the constant, use the
4115 register since that is more likely to match (and to produce better code
4118 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
4119 && rtx_equal_p (operands[4], operands[3]))
4120 operands[4] = operands[2];
4122 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
4123 && rtx_equal_p (operands[5], operands[3]))
4124 operands[5] = operands[2];
4126 if (code == NE || code == EQ
4127 || (extended_count (operands[2], DImode, unsignedp) >= 1
4128 && extended_count (operands[3], DImode, unsignedp) >= 1))
4130 if (GET_CODE (operands[3]) == CONST_INT)
4131 operands[7] = gen_rtx_PLUS (DImode, operands[2],
4132 GEN_INT (- INTVAL (operands[3])));
4134 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4136 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
4139 else if (code == EQ || code == LE || code == LT
4140 || code == LEU || code == LTU)
4142 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4143 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
4147 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4148 operands[2], operands[3]);
4149 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
4154 [(set (match_operand:DI 0 "register_operand" "")
4156 (match_operator 1 "comparison_operator"
4157 [(match_operand:SI 2 "reg_or_0_operand" "")
4158 (match_operand:SI 3 "reg_or_cint_operand" "")])
4159 (match_operand:DI 4 "reg_or_8bit_operand" "")
4160 (match_operand:DI 5 "reg_or_8bit_operand" "")))
4161 (clobber (match_operand:DI 6 "register_operand" ""))]
4162 "operands[3] != const0_rtx
4163 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4164 [(set (match_dup 6) (match_dup 7))
4166 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4168 enum rtx_code code = GET_CODE (operands[1]);
4169 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4172 if ((code != NE && code != EQ
4173 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4174 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4177 if (GET_CODE (operands[3]) == CONST_INT)
4178 tem = gen_rtx_PLUS (SImode, operands[2],
4179 GEN_INT (- INTVAL (operands[3])));
4181 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4183 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4184 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4185 operands[6], const0_rtx);
4191 (match_operator 1 "comparison_operator"
4192 [(match_operand:DI 2 "reg_or_0_operand" "")
4193 (match_operand:DI 3 "reg_or_cint_operand" "")])
4194 (label_ref (match_operand 0 "" ""))
4196 (clobber (match_operand:DI 4 "register_operand" ""))]
4197 "operands[3] != const0_rtx"
4198 [(set (match_dup 4) (match_dup 5))
4199 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4201 enum rtx_code code = GET_CODE (operands[1]);
4202 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4204 if (code == NE || code == EQ
4205 || (extended_count (operands[2], DImode, unsignedp) >= 1
4206 && extended_count (operands[3], DImode, unsignedp) >= 1))
4208 if (GET_CODE (operands[3]) == CONST_INT)
4209 operands[5] = gen_rtx_PLUS (DImode, operands[2],
4210 GEN_INT (- INTVAL (operands[3])));
4212 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4214 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
4217 else if (code == EQ || code == LE || code == LT
4218 || code == LEU || code == LTU)
4220 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4221 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
4225 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4226 operands[2], operands[3]);
4227 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
4234 (match_operator 1 "comparison_operator"
4235 [(match_operand:SI 2 "reg_or_0_operand" "")
4236 (match_operand:SI 3 "const_int_operand" "")])
4237 (label_ref (match_operand 0 "" ""))
4239 (clobber (match_operand:DI 4 "register_operand" ""))]
4240 "operands[3] != const0_rtx
4241 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4242 [(set (match_dup 4) (match_dup 5))
4243 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4247 if (GET_CODE (operands[3]) == CONST_INT)
4248 tem = gen_rtx_PLUS (SImode, operands[2],
4249 GEN_INT (- INTVAL (operands[3])));
4251 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4253 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
4254 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4255 operands[4], const0_rtx);
4258 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
4259 ;; This eliminates one, and sometimes two, insns when the AND can be done
4262 [(set (match_operand:DI 0 "register_operand" "")
4263 (match_operator:DI 1 "comparison_operator"
4264 [(match_operand:DI 2 "register_operand" "")
4265 (match_operand:DI 3 "const_int_operand" "")]))
4266 (clobber (match_operand:DI 4 "register_operand" ""))]
4267 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
4268 && (GET_CODE (operands[1]) == GTU
4269 || GET_CODE (operands[1]) == LEU
4270 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
4271 && extended_count (operands[2], DImode, 1) > 0))"
4272 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
4273 (set (match_dup 0) (match_dup 6))]
4275 operands[5] = GEN_INT (~ INTVAL (operands[3]));
4276 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
4277 || GET_CODE (operands[1]) == GT)
4279 DImode, operands[4], const0_rtx);
4282 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4285 [(set (match_operand 0 "register_operand" "")
4286 (if_then_else (match_operator 1 "signed_comparison_operator"
4287 [(match_operand:DI 2 "reg_or_0_operand" "")
4289 (match_operand 3 "const_int_operand" "")
4290 (match_operand 4 "const_int_operand" "")))]
4294 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4295 operands[2], operands[3], operands[4]))
4301 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4302 ;; Oh well, we match it in movcc, so it must be partially our fault.
4304 [(set (match_operand 0 "register_operand" "")
4305 (if_then_else (match_operator 1 "signed_comparison_operator"
4307 (match_operand:DI 2 "reg_or_0_operand" "")])
4308 (match_operand 3 "const_int_operand" "")
4309 (match_operand 4 "const_int_operand" "")))]
4313 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4314 operands[0], operands[2], operands[3],
4321 (define_insn_and_split "*cmp_sadd_di"
4322 [(set (match_operand:DI 0 "register_operand" "=r")
4323 (plus:DI (if_then_else:DI
4324 (match_operator 1 "alpha_zero_comparison_operator"
4325 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4327 (match_operand:DI 3 "const48_operand" "I")
4329 (match_operand:DI 4 "sext_add_operand" "rIO")))
4330 (clobber (match_scratch:DI 5 "=r"))]
4333 "! no_new_pseudos || reload_completed"
4335 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4337 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4340 if (! no_new_pseudos)
4341 operands[5] = gen_reg_rtx (DImode);
4342 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4343 operands[5] = operands[0];
4346 (define_insn_and_split "*cmp_sadd_si"
4347 [(set (match_operand:SI 0 "register_operand" "=r")
4348 (plus:SI (if_then_else:SI
4349 (match_operator 1 "alpha_zero_comparison_operator"
4350 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4352 (match_operand:SI 3 "const48_operand" "I")
4354 (match_operand:SI 4 "sext_add_operand" "rIO")))
4355 (clobber (match_scratch:SI 5 "=r"))]
4358 "! no_new_pseudos || reload_completed"
4360 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4362 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4365 if (! no_new_pseudos)
4366 operands[5] = gen_reg_rtx (DImode);
4367 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4368 operands[5] = operands[0];
4371 (define_insn_and_split "*cmp_sadd_sidi"
4372 [(set (match_operand:DI 0 "register_operand" "=r")
4374 (plus:SI (if_then_else:SI
4375 (match_operator 1 "alpha_zero_comparison_operator"
4376 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4378 (match_operand:SI 3 "const48_operand" "I")
4380 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4381 (clobber (match_scratch:SI 5 "=r"))]
4384 "! no_new_pseudos || reload_completed"
4386 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4388 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4391 if (! no_new_pseudos)
4392 operands[5] = gen_reg_rtx (DImode);
4393 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4394 operands[5] = operands[0];
4397 (define_insn_and_split "*cmp_ssub_di"
4398 [(set (match_operand:DI 0 "register_operand" "=r")
4399 (minus:DI (if_then_else:DI
4400 (match_operator 1 "alpha_zero_comparison_operator"
4401 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4403 (match_operand:DI 3 "const48_operand" "I")
4405 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4406 (clobber (match_scratch:DI 5 "=r"))]
4409 "! no_new_pseudos || reload_completed"
4411 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4413 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4416 if (! no_new_pseudos)
4417 operands[5] = gen_reg_rtx (DImode);
4418 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4419 operands[5] = operands[0];
4422 (define_insn_and_split "*cmp_ssub_si"
4423 [(set (match_operand:SI 0 "register_operand" "=r")
4424 (minus:SI (if_then_else:SI
4425 (match_operator 1 "alpha_zero_comparison_operator"
4426 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4428 (match_operand:SI 3 "const48_operand" "I")
4430 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4431 (clobber (match_scratch:SI 5 "=r"))]
4434 "! no_new_pseudos || reload_completed"
4436 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4438 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4441 if (! no_new_pseudos)
4442 operands[5] = gen_reg_rtx (DImode);
4443 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4444 operands[5] = operands[0];
4447 (define_insn_and_split "*cmp_ssub_sidi"
4448 [(set (match_operand:DI 0 "register_operand" "=r")
4450 (minus:SI (if_then_else:SI
4451 (match_operator 1 "alpha_zero_comparison_operator"
4452 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4454 (match_operand:SI 3 "const48_operand" "I")
4456 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4457 (clobber (match_scratch:SI 5 "=r"))]
4460 "! no_new_pseudos || reload_completed"
4462 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4464 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4467 if (! no_new_pseudos)
4468 operands[5] = gen_reg_rtx (DImode);
4469 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4470 operands[5] = operands[0];
4473 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4474 ;; work differently, so we have different patterns for each.
4476 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4477 ;; call. The CIW contains information about arguments passed in registers
4478 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4479 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4480 ;; in the presence of inlining since the CIWs for calls performed by the
4481 ;; inlined function must be stored in the SSIB of the function it is inlined
4482 ;; into as well. We encode the CIW in an unspec and append it to the list
4483 ;; of the CIWs for the current function only when the instruction for loading
4484 ;; $25 is generated.
4486 (define_expand "call"
4487 [(use (match_operand:DI 0 "" ""))
4488 (use (match_operand 1 "" ""))
4489 (use (match_operand 2 "" ""))
4490 (use (match_operand 3 "" ""))]
4493 if (TARGET_ABI_WINDOWS_NT)
4494 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4495 else if (TARGET_ABI_OPEN_VMS)
4496 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4497 else if (TARGET_ABI_UNICOSMK)
4498 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4500 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4504 (define_expand "sibcall"
4505 [(call (mem:DI (match_operand 0 "" ""))
4506 (match_operand 1 "" ""))]
4509 if (GET_CODE (operands[0]) != MEM)
4511 operands[0] = XEXP (operands[0], 0);
4514 (define_expand "call_osf"
4515 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4516 (match_operand 1 "" ""))
4517 (clobber (reg:DI 27))
4518 (clobber (reg:DI 26))])]
4521 if (GET_CODE (operands[0]) != MEM)
4524 operands[0] = XEXP (operands[0], 0);
4526 if (GET_CODE (operands[0]) != SYMBOL_REF
4527 && ! (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 27))
4529 rtx tem = gen_rtx_REG (DImode, 27);
4530 emit_move_insn (tem, operands[0]);
4535 (define_expand "call_nt"
4536 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4537 (match_operand 1 "" ""))
4538 (clobber (reg:DI 26))])]
4541 if (GET_CODE (operands[0]) != MEM)
4544 operands[0] = XEXP (operands[0], 0);
4545 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4546 operands[0] = force_reg (DImode, operands[0]);
4549 ;; Calls on Unicos/Mk are always indirect.
4550 ;; op 0: symbol ref for called function
4551 ;; op 1: CIW for $25 represented by an unspec
4553 (define_expand "call_umk"
4554 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4555 (match_operand 1 "" ""))
4557 (clobber (reg:DI 26))])]
4560 if (GET_CODE (operands[0]) != MEM)
4563 /* Always load the address of the called function into a register;
4564 load the CIW in $25. */
4566 operands[0] = XEXP (operands[0], 0);
4567 if (GET_CODE (operands[0]) != REG)
4568 operands[0] = force_reg (DImode, operands[0]);
4570 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4574 ;; call openvms/alpha
4575 ;; op 0: symbol ref for called function
4576 ;; op 1: next_arg_reg (argument information value for R25)
4578 (define_expand "call_vms"
4579 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4580 (match_operand 1 "" ""))
4584 (clobber (reg:DI 27))])]
4587 if (GET_CODE (operands[0]) != MEM)
4590 operands[0] = XEXP (operands[0], 0);
4592 /* Always load AI with argument information, then handle symbolic and
4593 indirect call differently. Load RA and set operands[2] to PV in
4596 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4597 if (GET_CODE (operands[0]) == SYMBOL_REF)
4599 rtx linkage = alpha_need_linkage (XSTR (operands[0], 0), 0);
4601 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4603 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4607 emit_move_insn (gen_rtx_REG (Pmode, 26),
4608 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4609 operands[2] = operands[0];
4614 (define_expand "call_value"
4615 [(use (match_operand 0 "" ""))
4616 (use (match_operand:DI 1 "" ""))
4617 (use (match_operand 2 "" ""))
4618 (use (match_operand 3 "" ""))
4619 (use (match_operand 4 "" ""))]
4622 if (TARGET_ABI_WINDOWS_NT)
4623 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4624 else if (TARGET_ABI_OPEN_VMS)
4625 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4627 else if (TARGET_ABI_UNICOSMK)
4628 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4631 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4636 (define_expand "sibcall_value"
4637 [(set (match_operand 0 "" "")
4638 (call (mem:DI (match_operand 1 "" ""))
4639 (match_operand 2 "" "")))]
4642 if (GET_CODE (operands[1]) != MEM)
4644 operands[1] = XEXP (operands[1], 0);
4647 (define_expand "call_value_osf"
4648 [(parallel [(set (match_operand 0 "" "")
4649 (call (mem:DI (match_operand 1 "" ""))
4650 (match_operand 2 "" "")))
4651 (clobber (reg:DI 27))
4652 (clobber (reg:DI 26))])]
4655 if (GET_CODE (operands[1]) != MEM)
4658 operands[1] = XEXP (operands[1], 0);
4660 if (GET_CODE (operands[1]) != SYMBOL_REF
4661 && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
4663 rtx tem = gen_rtx_REG (DImode, 27);
4664 emit_move_insn (tem, operands[1]);
4669 (define_expand "call_value_nt"
4670 [(parallel [(set (match_operand 0 "" "")
4671 (call (mem:DI (match_operand 1 "" ""))
4672 (match_operand 2 "" "")))
4673 (clobber (reg:DI 26))])]
4676 if (GET_CODE (operands[1]) != MEM)
4679 operands[1] = XEXP (operands[1], 0);
4680 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4681 operands[1] = force_reg (DImode, operands[1]);
4684 (define_expand "call_value_vms"
4685 [(parallel [(set (match_operand 0 "" "")
4686 (call (mem:DI (match_operand:DI 1 "" ""))
4687 (match_operand 2 "" "")))
4691 (clobber (reg:DI 27))])]
4694 if (GET_CODE (operands[1]) != MEM)
4697 operands[1] = XEXP (operands[1], 0);
4699 /* Always load AI with argument information, then handle symbolic and
4700 indirect call differently. Load RA and set operands[3] to PV in
4703 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4704 if (GET_CODE (operands[1]) == SYMBOL_REF)
4706 rtx linkage = alpha_need_linkage (XSTR (operands[1], 0), 0);
4708 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4710 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4714 emit_move_insn (gen_rtx_REG (Pmode, 26),
4715 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4716 operands[3] = operands[1];
4720 (define_expand "call_value_umk"
4721 [(parallel [(set (match_operand 0 "" "")
4722 (call (mem:DI (match_operand 1 "" ""))
4723 (match_operand 2 "" "")))
4725 (clobber (reg:DI 26))])]
4728 if (GET_CODE (operands[1]) != MEM)
4731 operands[1] = XEXP (operands[1], 0);
4732 if (GET_CODE (operands[1]) != REG)
4733 operands[1] = force_reg (DImode, operands[1]);
4735 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4738 (define_insn "*call_osf_1_er_noreturn"
4739 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,i"))
4740 (match_operand 1 "" ""))
4741 (clobber (reg:DI 27))
4742 (clobber (reg:DI 26))]
4743 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4744 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4748 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#"
4749 [(set_attr "type" "jsr")
4750 (set_attr "length" "*,*,8")])
4752 (define_insn "*call_osf_1_er"
4753 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,i"))
4754 (match_operand 1 "" ""))
4755 (clobber (reg:DI 27))
4756 (clobber (reg:DI 26))]
4757 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4759 jsr $26,($27),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4761 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4762 [(set_attr "type" "jsr")
4763 (set_attr "length" "12,*,16")])
4765 (define_insn "*call_osf_1_noreturn"
4766 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,i"))
4767 (match_operand 1 "" ""))
4768 (clobber (reg:DI 27))
4769 (clobber (reg:DI 26))]
4770 "TARGET_ABI_OSF && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4775 [(set_attr "type" "jsr")
4776 (set_attr "length" "*,*,8")])
4778 (define_insn "*call_osf_1"
4779 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,i"))
4780 (match_operand 1 "" ""))
4781 (clobber (reg:DI 27))
4782 (clobber (reg:DI 26))]
4785 jsr $26,($27),0\;ldgp $29,0($26)
4787 jsr $26,%0\;ldgp $29,0($26)"
4788 [(set_attr "type" "jsr")
4789 (set_attr "length" "12,*,16")])
4791 (define_insn "*sibcall_osf_1"
4792 [(call (mem:DI (match_operand:DI 0 "current_file_function_operand" "R"))
4793 (match_operand 1 "" ""))]
4796 [(set_attr "type" "jsr")])
4798 (define_insn "*call_nt_1"
4799 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
4800 (match_operand 1 "" ""))
4801 (clobber (reg:DI 26))]
4802 "TARGET_ABI_WINDOWS_NT"
4807 [(set_attr "type" "jsr")
4808 (set_attr "length" "*,*,12")])
4810 (define_insn "*call_vms_1"
4811 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
4812 (match_operand 1 "" ""))
4813 (use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
4816 (clobber (reg:DI 27))]
4817 "TARGET_ABI_OPEN_VMS"
4819 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
4820 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
4821 [(set_attr "type" "jsr")
4822 (set_attr "length" "12,16")])
4824 (define_insn "*call_umk_1"
4825 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4826 (match_operand 1 "" ""))
4828 (clobber (reg:DI 26))]
4829 "TARGET_ABI_UNICOSMK"
4831 [(set_attr "type" "jsr")])
4833 ;; Call subroutine returning any type.
4835 (define_expand "untyped_call"
4836 [(parallel [(call (match_operand 0 "" "")
4838 (match_operand 1 "" "")
4839 (match_operand 2 "" "")])]
4844 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4846 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4848 rtx set = XVECEXP (operands[2], 0, i);
4849 emit_move_insn (SET_DEST (set), SET_SRC (set));
4852 /* The optimizer does not know that the call sets the function value
4853 registers we stored in the result block. We avoid problems by
4854 claiming that all hard registers are used and clobbered at this
4856 emit_insn (gen_blockage ());
4861 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4862 ;; all of memory. This blocks insns from being moved across this point.
4864 (define_insn "blockage"
4865 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4868 [(set_attr "length" "0")])
4872 (label_ref (match_operand 0 "" "")))]
4875 [(set_attr "type" "ibr")])
4877 (define_expand "return"
4882 (define_insn "*return_internal"
4886 [(set_attr "type" "ibr")])
4888 (define_insn "indirect_jump"
4889 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4892 [(set_attr "type" "ibr")])
4894 (define_expand "tablejump"
4895 [(parallel [(set (pc)
4896 (match_operand 0 "register_operand" ""))
4897 (use (label_ref:DI (match_operand 1 "" "")))])]
4900 if (TARGET_ABI_WINDOWS_NT)
4902 rtx dest = gen_reg_rtx (DImode);
4903 emit_insn (gen_extendsidi2 (dest, operands[0]));
4906 else if (TARGET_ABI_OSF)
4908 rtx dest = gen_reg_rtx (DImode);
4909 emit_insn (gen_extendsidi2 (dest, operands[0]));
4910 emit_insn (gen_adddi3 (dest, gen_rtx_REG (DImode, 29), dest));
4915 (define_insn "*tablejump_osf_nt_internal"
4917 (match_operand:DI 0 "register_operand" "r"))
4918 (use (label_ref:DI (match_operand 1 "" "")))]
4919 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
4920 && alpha_tablejump_addr_vec (insn)"
4922 operands[2] = alpha_tablejump_best_label (insn);
4923 return "jmp $31,(%0),%2";
4925 [(set_attr "type" "ibr")])
4927 (define_insn "*tablejump_internal"
4929 (match_operand:DI 0 "register_operand" "r"))
4930 (use (label_ref (match_operand 1 "" "")))]
4933 [(set_attr "type" "ibr")])
4935 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4936 ;; want to have to include pal.h in our .s file.
4938 ;; Technically the type for call_pal is jsr, but we use that for determining
4939 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
4942 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
4945 [(set_attr "type" "ibr")])
4947 ;; Finally, we have the basic data motion insns. The byte and word insns
4948 ;; are done via define_expand. Start with the floating-point insns, since
4949 ;; they are simpler.
4951 (define_insn "*movsf_nofix"
4952 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4953 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4954 "TARGET_FPREGS && ! TARGET_FIX
4955 && (register_operand (operands[0], SFmode)
4956 || reg_or_fp0_operand (operands[1], SFmode))"
4964 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4966 (define_insn "*movsf_fix"
4967 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4968 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4969 "TARGET_FPREGS && TARGET_FIX
4970 && (register_operand (operands[0], SFmode)
4971 || reg_or_fp0_operand (operands[1], SFmode))"
4981 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4983 (define_insn "*movsf_nofp"
4984 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
4985 (match_operand:SF 1 "input_operand" "rG,m,r"))]
4987 && (register_operand (operands[0], SFmode)
4988 || reg_or_fp0_operand (operands[1], SFmode))"
4993 [(set_attr "type" "ilog,ild,ist")])
4995 (define_insn "*movdf_nofix"
4996 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4997 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4998 "TARGET_FPREGS && ! TARGET_FIX
4999 && (register_operand (operands[0], DFmode)
5000 || reg_or_fp0_operand (operands[1], DFmode))"
5008 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5010 (define_insn "*movdf_fix"
5011 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5012 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5013 "TARGET_FPREGS && TARGET_FIX
5014 && (register_operand (operands[0], DFmode)
5015 || reg_or_fp0_operand (operands[1], DFmode))"
5025 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5027 (define_insn "*movdf_nofp"
5028 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
5029 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5031 && (register_operand (operands[0], DFmode)
5032 || reg_or_fp0_operand (operands[1], DFmode))"
5037 [(set_attr "type" "ilog,ild,ist")])
5039 ;; Subregs suck for register allocation. Pretend we can move TFmode
5040 ;; data between general registers until after reload.
5042 (define_insn_and_split "*movtf_internal"
5043 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5044 (match_operand:TF 1 "input_operand" "roG,rG"))]
5045 "register_operand (operands[0], TFmode)
5046 || reg_or_fp0_operand (operands[1], TFmode)"
5049 [(set (match_dup 0) (match_dup 2))
5050 (set (match_dup 1) (match_dup 3))]
5052 alpha_split_tfmode_pair (operands);
5053 if (reg_overlap_mentioned_p (operands[0], operands[3]))
5056 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
5057 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
5061 (define_expand "movsf"
5062 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5063 (match_operand:SF 1 "general_operand" ""))]
5066 if (GET_CODE (operands[0]) == MEM
5067 && ! reg_or_fp0_operand (operands[1], SFmode))
5068 operands[1] = force_reg (SFmode, operands[1]);
5071 (define_expand "movdf"
5072 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5073 (match_operand:DF 1 "general_operand" ""))]
5076 if (GET_CODE (operands[0]) == MEM
5077 && ! reg_or_fp0_operand (operands[1], DFmode))
5078 operands[1] = force_reg (DFmode, operands[1]);
5081 (define_expand "movtf"
5082 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5083 (match_operand:TF 1 "general_operand" ""))]
5086 if (GET_CODE (operands[0]) == MEM
5087 && ! reg_or_fp0_operand (operands[1], TFmode))
5088 operands[1] = force_reg (TFmode, operands[1]);
5091 (define_insn "*movsi_nofix"
5092 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
5093 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
5094 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK) && ! TARGET_FIX
5095 && (register_operand (operands[0], SImode)
5096 || reg_or_0_operand (operands[1], SImode))"
5106 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
5108 (define_insn "*movsi_fix"
5109 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
5110 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
5111 "TARGET_ABI_OSF && TARGET_FIX
5112 && (register_operand (operands[0], SImode)
5113 || reg_or_0_operand (operands[1], SImode))"
5125 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
5127 (define_insn "*movsi_nt_vms"
5128 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
5129 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
5130 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5131 && (register_operand (operands[0], SImode)
5132 || reg_or_0_operand (operands[1], SImode))"
5143 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5145 (define_insn "*movhi_nobwx"
5146 [(set (match_operand:HI 0 "register_operand" "=r,r")
5147 (match_operand:HI 1 "input_operand" "rJ,n"))]
5149 && (register_operand (operands[0], HImode)
5150 || register_operand (operands[1], HImode))"
5154 [(set_attr "type" "ilog,iadd")])
5156 (define_insn "*movhi_bwx"
5157 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5158 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5160 && (register_operand (operands[0], HImode)
5161 || reg_or_0_operand (operands[1], HImode))"
5167 [(set_attr "type" "ilog,iadd,ild,ist")])
5169 (define_insn "*movqi_nobwx"
5170 [(set (match_operand:QI 0 "register_operand" "=r,r")
5171 (match_operand:QI 1 "input_operand" "rJ,n"))]
5173 && (register_operand (operands[0], QImode)
5174 || register_operand (operands[1], QImode))"
5178 [(set_attr "type" "ilog,iadd")])
5180 (define_insn "*movqi_bwx"
5181 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5182 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5184 && (register_operand (operands[0], QImode)
5185 || reg_or_0_operand (operands[1], QImode))"
5191 [(set_attr "type" "ilog,iadd,ild,ist")])
5193 ;; We do two major things here: handle mem->mem and construct long
5196 (define_expand "movsi"
5197 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5198 (match_operand:SI 1 "general_operand" ""))]
5201 if (alpha_expand_mov (SImode, operands))
5205 ;; Split a load of a large constant into the appropriate two-insn
5209 [(set (match_operand:SI 0 "register_operand" "")
5210 (match_operand:SI 1 "const_int_operand" ""))]
5211 "! add_operand (operands[1], SImode)"
5212 [(set (match_dup 0) (match_dup 2))
5213 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
5216 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
5218 if (tem == operands[0])
5224 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5225 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5226 ;; optimisations. If the symbolic operand is a label_ref, generate REG_LABEL
5227 ;; notes and update LABEL_NUSES because this is not done automatically.
5228 ;; Labels may be incorrectly deleted if we don't do this.
5230 ;; Describing what the individual instructions do correctly is too complicated
5231 ;; so use UNSPECs for each of the three parts of an address.
5234 [(set (match_operand:DI 0 "register_operand" "")
5235 (match_operand:DI 1 "symbolic_operand" ""))]
5236 "TARGET_ABI_UNICOSMK && reload_completed"
5239 rtx insn1, insn2, insn3;
5241 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5242 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5243 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5244 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5245 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
5247 if (GET_CODE (operands[1]) == LABEL_REF)
5251 label = XEXP (operands[1], 0);
5252 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5254 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5256 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5258 LABEL_NUSES (label) += 3;
5263 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5265 (define_insn "umk_laum"
5266 [(set (match_operand:DI 0 "register_operand" "=r")
5267 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5269 "TARGET_ABI_UNICOSMK"
5271 [(set_attr "type" "iadd")])
5273 (define_insn "umk_lalm"
5274 [(set (match_operand:DI 0 "register_operand" "=r")
5275 (plus:DI (match_operand:DI 1 "register_operand" "r")
5276 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5278 "TARGET_ABI_UNICOSMK"
5280 [(set_attr "type" "iadd")])
5282 (define_insn "umk_lal"
5283 [(set (match_operand:DI 0 "register_operand" "=r")
5284 (plus:DI (match_operand:DI 1 "register_operand" "r")
5285 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5287 "TARGET_ABI_UNICOSMK"
5289 [(set_attr "type" "iadd")])
5291 ;; Add a new call information word to the current function's list of CIWs
5292 ;; and load its index into $25. Doing it here ensures that the CIW will be
5293 ;; associated with the correct function even in the presence of inlining.
5295 (define_insn "*umk_load_ciw"
5297 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5298 "TARGET_ABI_UNICOSMK"
5300 operands[0] = unicosmk_add_call_info_word (operands[0]);
5301 return "lda $25,%0";
5303 [(set_attr "type" "iadd")])
5305 (define_insn "*movdi_er_low"
5306 [(set (match_operand:DI 0 "register_operand" "=r")
5307 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5308 (match_operand:DI 2 "local_symbolic_operand" "")))]
5309 "TARGET_EXPLICIT_RELOCS"
5311 if (true_regnum (operands[1]) == 29)
5312 return "lda %0,%2(%1)\t\t!gprel";
5314 return "lda %0,%2(%1)\t\t!gprellow";
5317 (define_insn "*movdi_er_nofix"
5318 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5319 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,m,rJ,*fJ,Q,*f"))]
5320 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5321 && (register_operand (operands[0], DImode)
5322 || reg_or_0_operand (operands[1], DImode))
5323 && ! local_symbolic_operand (operands[1], DImode)"
5329 ldq %0,%1($29)\t\t!literal
5335 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5337 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5338 ;; have been split up by the rules above but we shouldn't reject the
5339 ;; possibility of them getting through.
5341 (define_insn "*movdi_nofix"
5342 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5343 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,m,rJ,*fJ,Q,*f"))]
5345 && (register_operand (operands[0], DImode)
5346 || reg_or_0_operand (operands[1], DImode))"
5351 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5358 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,ild,ist,fcpys,fld,fst")
5359 (set_attr "length" "*,*,*,16,*,*,*,*,*,*")])
5361 (define_insn "*movdi_er_fix"
5362 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q,r,*f")
5363 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,m,rJ,*fJ,Q,*f,*f,r"))]
5364 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5365 && (register_operand (operands[0], DImode)
5366 || reg_or_0_operand (operands[1], DImode))
5367 && ! local_symbolic_operand (operands[1], DImode)"
5373 ldq %0,%1($29)\t\t!literal
5381 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5383 (define_insn "*movdi_fix"
5384 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
5385 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
5386 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5387 && (register_operand (operands[0], DImode)
5388 || reg_or_0_operand (operands[1], DImode))"
5401 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5403 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5404 ;; often appears dead to the life analysis code, at which point we
5405 ;; abort for emitting dead prologue instructions. Force this live.
5407 (define_insn "force_movdi"
5408 [(set (match_operand:DI 0 "register_operand" "=r")
5409 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5410 UNSPECV_FORCE_MOV))]
5413 [(set_attr "type" "ilog")])
5415 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5416 ;; memory, and construct long 32-bit constants.
5418 (define_expand "movdi"
5419 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5420 (match_operand:DI 1 "general_operand" ""))]
5423 if (alpha_expand_mov (DImode, operands))
5427 ;; Split a load of a large constant into the appropriate two-insn
5431 [(set (match_operand:DI 0 "register_operand" "")
5432 (match_operand:DI 1 "const_int_operand" ""))]
5433 "! add_operand (operands[1], DImode)"
5434 [(set (match_dup 0) (match_dup 2))
5435 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5438 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
5440 if (tem == operands[0])
5446 ;; These are the partial-word cases.
5448 ;; First we have the code to load an aligned word. Operand 0 is the register
5449 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5450 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5451 ;; number of bits within the word that the value is. Operand 3 is an SImode
5452 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5453 ;; same register. It is allowed to conflict with operand 1 as well.
5455 (define_expand "aligned_loadqi"
5456 [(set (match_operand:SI 3 "register_operand" "")
5457 (match_operand:SI 1 "memory_operand" ""))
5458 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5459 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5461 (match_operand:DI 2 "const_int_operand" "")))]
5466 (define_expand "aligned_loadhi"
5467 [(set (match_operand:SI 3 "register_operand" "")
5468 (match_operand:SI 1 "memory_operand" ""))
5469 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
5470 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5472 (match_operand:DI 2 "const_int_operand" "")))]
5477 ;; Similar for unaligned loads, where we use the sequence from the
5478 ;; Alpha Architecture manual. We have to distinguish between little-endian
5479 ;; and big-endian systems as the sequences are different.
5481 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5482 ;; operand 3 can overlap the input and output registers.
5484 (define_expand "unaligned_loadqi"
5485 [(use (match_operand:QI 0 "register_operand" ""))
5486 (use (match_operand:DI 1 "address_operand" ""))
5487 (use (match_operand:DI 2 "register_operand" ""))
5488 (use (match_operand:DI 3 "register_operand" ""))]
5491 if (WORDS_BIG_ENDIAN)
5492 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5493 operands[2], operands[3]));
5495 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5496 operands[2], operands[3]));
5500 (define_expand "unaligned_loadqi_le"
5501 [(set (match_operand:DI 2 "register_operand" "")
5502 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5504 (set (match_operand:DI 3 "register_operand" "")
5506 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5507 (zero_extract:DI (match_dup 2)
5509 (ashift:DI (match_dup 3) (const_int 3))))]
5510 "! WORDS_BIG_ENDIAN"
5513 (define_expand "unaligned_loadqi_be"
5514 [(set (match_operand:DI 2 "register_operand" "")
5515 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5517 (set (match_operand:DI 3 "register_operand" "")
5519 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5520 (zero_extract:DI (match_dup 2)
5524 (ashift:DI (match_dup 3) (const_int 3)))))]
5528 (define_expand "unaligned_loadhi"
5529 [(use (match_operand:QI 0 "register_operand" ""))
5530 (use (match_operand:DI 1 "address_operand" ""))
5531 (use (match_operand:DI 2 "register_operand" ""))
5532 (use (match_operand:DI 3 "register_operand" ""))]
5535 if (WORDS_BIG_ENDIAN)
5536 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5537 operands[2], operands[3]));
5539 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5540 operands[2], operands[3]));
5544 (define_expand "unaligned_loadhi_le"
5545 [(set (match_operand:DI 2 "register_operand" "")
5546 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5548 (set (match_operand:DI 3 "register_operand" "")
5550 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5551 (zero_extract:DI (match_dup 2)
5553 (ashift:DI (match_dup 3) (const_int 3))))]
5554 "! WORDS_BIG_ENDIAN"
5557 (define_expand "unaligned_loadhi_be"
5558 [(set (match_operand:DI 2 "register_operand" "")
5559 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5561 (set (match_operand:DI 3 "register_operand" "")
5562 (plus:DI (match_dup 1) (const_int 1)))
5563 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5564 (zero_extract:DI (match_dup 2)
5568 (ashift:DI (match_dup 3) (const_int 3)))))]
5572 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5573 ;; aligned SImode MEM. Operand 1 is the register containing the
5574 ;; byte or word to store. Operand 2 is the number of bits within the word that
5575 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5577 (define_expand "aligned_store"
5578 [(set (match_operand:SI 3 "register_operand" "")
5579 (match_operand:SI 0 "memory_operand" ""))
5580 (set (subreg:DI (match_dup 3) 0)
5581 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5582 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5583 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5584 (match_operand:DI 2 "const_int_operand" "")))
5585 (set (subreg:DI (match_dup 4) 0)
5586 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5587 (set (match_dup 0) (match_dup 4))]
5590 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5591 << INTVAL (operands[2])));
5594 ;; For the unaligned byte and halfword cases, we use code similar to that
5595 ;; in the ;; Architecture book, but reordered to lower the number of registers
5596 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5597 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5598 ;; be the same temporary, if desired. If the address is in a register,
5599 ;; operand 2 can be that register.
5601 (define_expand "unaligned_storeqi"
5602 [(use (match_operand:DI 0 "address_operand" ""))
5603 (use (match_operand:QI 1 "register_operand" ""))
5604 (use (match_operand:DI 2 "register_operand" ""))
5605 (use (match_operand:DI 3 "register_operand" ""))
5606 (use (match_operand:DI 4 "register_operand" ""))]
5609 if (WORDS_BIG_ENDIAN)
5610 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5611 operands[2], operands[3],
5614 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5615 operands[2], operands[3],
5620 (define_expand "unaligned_storeqi_le"
5621 [(set (match_operand:DI 3 "register_operand" "")
5622 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5624 (set (match_operand:DI 2 "register_operand" "")
5627 (and:DI (not:DI (ashift:DI (const_int 255)
5628 (ashift:DI (match_dup 2) (const_int 3))))
5630 (set (match_operand:DI 4 "register_operand" "")
5631 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5632 (ashift:DI (match_dup 2) (const_int 3))))
5633 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5634 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5636 "! WORDS_BIG_ENDIAN"
5639 (define_expand "unaligned_storeqi_be"
5640 [(set (match_operand:DI 3 "register_operand" "")
5641 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5643 (set (match_operand:DI 2 "register_operand" "")
5646 (and:DI (not:DI (ashift:DI (const_int 255)
5647 (minus:DI (const_int 56)
5648 (ashift:DI (match_dup 2) (const_int 3)))))
5650 (set (match_operand:DI 4 "register_operand" "")
5651 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5652 (minus:DI (const_int 56)
5653 (ashift:DI (match_dup 2) (const_int 3)))))
5654 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5655 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5660 (define_expand "unaligned_storehi"
5661 [(use (match_operand:DI 0 "address_operand" ""))
5662 (use (match_operand:HI 1 "register_operand" ""))
5663 (use (match_operand:DI 2 "register_operand" ""))
5664 (use (match_operand:DI 3 "register_operand" ""))
5665 (use (match_operand:DI 4 "register_operand" ""))]
5668 if (WORDS_BIG_ENDIAN)
5669 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5670 operands[2], operands[3],
5673 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5674 operands[2], operands[3],
5679 (define_expand "unaligned_storehi_le"
5680 [(set (match_operand:DI 3 "register_operand" "")
5681 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5683 (set (match_operand:DI 2 "register_operand" "")
5686 (and:DI (not:DI (ashift:DI (const_int 65535)
5687 (ashift:DI (match_dup 2) (const_int 3))))
5689 (set (match_operand:DI 4 "register_operand" "")
5690 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5691 (ashift:DI (match_dup 2) (const_int 3))))
5692 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5693 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5695 "! WORDS_BIG_ENDIAN"
5698 (define_expand "unaligned_storehi_be"
5699 [(set (match_operand:DI 3 "register_operand" "")
5700 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5702 (set (match_operand:DI 2 "register_operand" "")
5703 (plus:DI (match_dup 0) (const_int 1)))
5705 (and:DI (not:DI (ashift:DI
5707 (minus:DI (const_int 56)
5708 (ashift:DI (match_dup 2) (const_int 3)))))
5710 (set (match_operand:DI 4 "register_operand" "")
5711 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5712 (minus:DI (const_int 56)
5713 (ashift:DI (match_dup 2) (const_int 3)))))
5714 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5715 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5720 ;; Here are the define_expand's for QI and HI moves that use the above
5721 ;; patterns. We have the normal sets, plus the ones that need scratch
5722 ;; registers for reload.
5724 (define_expand "movqi"
5725 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5726 (match_operand:QI 1 "general_operand" ""))]
5730 ? alpha_expand_mov (QImode, operands)
5731 : alpha_expand_mov_nobwx (QImode, operands))
5735 (define_expand "movhi"
5736 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5737 (match_operand:HI 1 "general_operand" ""))]
5741 ? alpha_expand_mov (HImode, operands)
5742 : alpha_expand_mov_nobwx (HImode, operands))
5746 ;; Here are the versions for reload. Note that in the unaligned cases
5747 ;; we know that the operand must not be a pseudo-register because stack
5748 ;; slots are always aligned references.
5750 (define_expand "reload_inqi"
5751 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5752 (match_operand:QI 1 "any_memory_operand" "m")
5753 (match_operand:TI 2 "register_operand" "=&r")])]
5758 if (GET_CODE (operands[1]) != MEM)
5761 if (aligned_memory_operand (operands[1], QImode))
5763 seq = gen_reload_inqi_help (operands[0], operands[1],
5764 gen_rtx_REG (SImode, REGNO (operands[2])));
5770 /* It is possible that one of the registers we got for operands[2]
5771 might coincide with that of operands[0] (which is why we made
5772 it TImode). Pick the other one to use as our scratch. */
5773 if (REGNO (operands[0]) == REGNO (operands[2]))
5774 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5776 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5778 addr = get_unaligned_address (operands[1], 0);
5779 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
5780 gen_rtx_REG (DImode, REGNO (operands[0])));
5781 alpha_set_memflags (seq, operands[1]);
5787 (define_expand "reload_inhi"
5788 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5789 (match_operand:HI 1 "any_memory_operand" "m")
5790 (match_operand:TI 2 "register_operand" "=&r")])]
5795 if (GET_CODE (operands[1]) != MEM)
5798 if (aligned_memory_operand (operands[1], HImode))
5800 seq = gen_reload_inhi_help (operands[0], operands[1],
5801 gen_rtx_REG (SImode, REGNO (operands[2])));
5807 /* It is possible that one of the registers we got for operands[2]
5808 might coincide with that of operands[0] (which is why we made
5809 it TImode). Pick the other one to use as our scratch. */
5810 if (REGNO (operands[0]) == REGNO (operands[2]))
5811 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5813 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5815 addr = get_unaligned_address (operands[1], 0);
5816 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
5817 gen_rtx_REG (DImode, REGNO (operands[0])));
5818 alpha_set_memflags (seq, operands[1]);
5824 (define_expand "reload_outqi"
5825 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
5826 (match_operand:QI 1 "register_operand" "r")
5827 (match_operand:TI 2 "register_operand" "=&r")])]
5830 if (GET_CODE (operands[0]) != MEM)
5833 if (aligned_memory_operand (operands[0], QImode))
5835 emit_insn (gen_reload_outqi_help
5836 (operands[0], operands[1],
5837 gen_rtx_REG (SImode, REGNO (operands[2])),
5838 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5842 rtx addr = get_unaligned_address (operands[0], 0);
5843 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5844 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5845 rtx scratch3 = scratch1;
5848 if (GET_CODE (addr) == REG)
5851 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
5852 scratch2, scratch3);
5853 alpha_set_memflags (seq, operands[0]);
5859 (define_expand "reload_outhi"
5860 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
5861 (match_operand:HI 1 "register_operand" "r")
5862 (match_operand:TI 2 "register_operand" "=&r")])]
5865 if (GET_CODE (operands[0]) != MEM)
5868 if (aligned_memory_operand (operands[0], HImode))
5870 emit_insn (gen_reload_outhi_help
5871 (operands[0], operands[1],
5872 gen_rtx_REG (SImode, REGNO (operands[2])),
5873 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5877 rtx addr = get_unaligned_address (operands[0], 0);
5878 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5879 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5880 rtx scratch3 = scratch1;
5883 if (GET_CODE (addr) == REG)
5886 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
5887 scratch2, scratch3);
5888 alpha_set_memflags (seq, operands[0]);
5894 ;; Helpers for the above. The way reload is structured, we can't
5895 ;; always get a proper address for a stack slot during reload_foo
5896 ;; expansion, so we must delay our address manipulations until after.
5898 (define_insn "reload_inqi_help"
5899 [(set (match_operand:QI 0 "register_operand" "=r")
5900 (match_operand:QI 1 "memory_operand" "m"))
5901 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5902 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5905 (define_insn "reload_inhi_help"
5906 [(set (match_operand:HI 0 "register_operand" "=r")
5907 (match_operand:HI 1 "memory_operand" "m"))
5908 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5909 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5912 (define_insn "reload_outqi_help"
5913 [(set (match_operand:QI 0 "memory_operand" "=m")
5914 (match_operand:QI 1 "register_operand" "r"))
5915 (clobber (match_operand:SI 2 "register_operand" "=r"))
5916 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5917 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5920 (define_insn "reload_outhi_help"
5921 [(set (match_operand:HI 0 "memory_operand" "=m")
5922 (match_operand:HI 1 "register_operand" "r"))
5923 (clobber (match_operand:SI 2 "register_operand" "=r"))
5924 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5925 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5929 [(set (match_operand:QI 0 "register_operand" "")
5930 (match_operand:QI 1 "memory_operand" ""))
5931 (clobber (match_operand:SI 2 "register_operand" ""))]
5932 "! TARGET_BWX && reload_completed"
5935 rtx aligned_mem, bitnum;
5936 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5938 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
5944 [(set (match_operand:HI 0 "register_operand" "")
5945 (match_operand:HI 1 "memory_operand" ""))
5946 (clobber (match_operand:SI 2 "register_operand" ""))]
5947 "! TARGET_BWX && reload_completed"
5950 rtx aligned_mem, bitnum;
5951 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5953 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
5959 [(set (match_operand:QI 0 "memory_operand" "")
5960 (match_operand:QI 1 "register_operand" ""))
5961 (clobber (match_operand:SI 2 "register_operand" ""))
5962 (clobber (match_operand:SI 3 "register_operand" ""))]
5963 "! TARGET_BWX && reload_completed"
5966 rtx aligned_mem, bitnum;
5967 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5968 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5969 operands[2], operands[3]));
5974 [(set (match_operand:HI 0 "memory_operand" "")
5975 (match_operand:HI 1 "register_operand" ""))
5976 (clobber (match_operand:SI 2 "register_operand" ""))
5977 (clobber (match_operand:SI 3 "register_operand" ""))]
5978 "! TARGET_BWX && reload_completed"
5981 rtx aligned_mem, bitnum;
5982 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5983 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5984 operands[2], operands[3]));
5988 ;; Bit field extract patterns which use ext[wlq][lh]
5990 (define_expand "extv"
5991 [(set (match_operand:DI 0 "register_operand" "")
5992 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
5993 (match_operand:DI 2 "immediate_operand" "")
5994 (match_operand:DI 3 "immediate_operand" "")))]
5999 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6000 if (INTVAL (operands[3]) % 8 != 0
6001 || (INTVAL (operands[2]) != 16
6002 && INTVAL (operands[2]) != 32
6003 && INTVAL (operands[2]) != 64))
6006 /* From mips.md: extract_bit_field doesn't verify that our source
6007 matches the predicate, so we force it to be a MEM here. */
6008 if (GET_CODE (operands[1]) != MEM)
6011 /* The bit number is relative to the mode of operand 1 which is
6012 usually QImode (this might actually be a bug in expmed.c). Note
6013 that the bit number is negative in big-endian mode in this case.
6014 We have to convert that to the offset. */
6015 if (WORDS_BIG_ENDIAN)
6016 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6017 - INTVAL (operands[2]) - INTVAL (operands[3]);
6019 ofs = INTVAL (operands[3]);
6023 alpha_expand_unaligned_load (operands[0], operands[1],
6024 INTVAL (operands[2]) / 8,
6029 (define_expand "extzv"
6030 [(set (match_operand:DI 0 "register_operand" "")
6031 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6032 (match_operand:DI 2 "immediate_operand" "")
6033 (match_operand:DI 3 "immediate_operand" "")))]
6036 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6037 if (INTVAL (operands[3]) % 8 != 0
6038 || (INTVAL (operands[2]) != 8
6039 && INTVAL (operands[2]) != 16
6040 && INTVAL (operands[2]) != 32
6041 && INTVAL (operands[2]) != 64))
6044 if (GET_CODE (operands[1]) == MEM)
6048 /* Fail 8 bit fields, falling back on a simple byte load. */
6049 if (INTVAL (operands[2]) == 8)
6052 /* The bit number is relative to the mode of operand 1 which is
6053 usually QImode (this might actually be a bug in expmed.c). Note
6054 that the bit number is negative in big-endian mode in this case.
6055 We have to convert that to the offset. */
6056 if (WORDS_BIG_ENDIAN)
6057 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6058 - INTVAL (operands[2]) - INTVAL (operands[3]);
6060 ofs = INTVAL (operands[3]);
6064 alpha_expand_unaligned_load (operands[0], operands[1],
6065 INTVAL (operands[2]) / 8,
6071 (define_expand "insv"
6072 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6073 (match_operand:DI 1 "immediate_operand" "")
6074 (match_operand:DI 2 "immediate_operand" ""))
6075 (match_operand:DI 3 "register_operand" ""))]
6080 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6081 if (INTVAL (operands[2]) % 8 != 0
6082 || (INTVAL (operands[1]) != 16
6083 && INTVAL (operands[1]) != 32
6084 && INTVAL (operands[1]) != 64))
6087 /* From mips.md: store_bit_field doesn't verify that our source
6088 matches the predicate, so we force it to be a MEM here. */
6089 if (GET_CODE (operands[0]) != MEM)
6092 /* The bit number is relative to the mode of operand 1 which is
6093 usually QImode (this might actually be a bug in expmed.c). Note
6094 that the bit number is negative in big-endian mode in this case.
6095 We have to convert that to the offset. */
6096 if (WORDS_BIG_ENDIAN)
6097 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6098 - INTVAL (operands[1]) - INTVAL (operands[2]);
6100 ofs = INTVAL (operands[2]);
6104 alpha_expand_unaligned_store (operands[0], operands[3],
6105 INTVAL (operands[1]) / 8, ofs);
6109 ;; Block move/clear, see alpha.c for more details.
6110 ;; Argument 0 is the destination
6111 ;; Argument 1 is the source
6112 ;; Argument 2 is the length
6113 ;; Argument 3 is the alignment
6115 (define_expand "movstrqi"
6116 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6117 (match_operand:BLK 1 "memory_operand" ""))
6118 (use (match_operand:DI 2 "immediate_operand" ""))
6119 (use (match_operand:DI 3 "immediate_operand" ""))])]
6122 if (alpha_expand_block_move (operands))
6128 (define_expand "clrstrqi"
6129 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6131 (use (match_operand:DI 1 "immediate_operand" ""))
6132 (use (match_operand:DI 2 "immediate_operand" ""))])]
6135 if (alpha_expand_block_clear (operands))
6141 ;; Subroutine of stack space allocation. Perform a stack probe.
6142 (define_expand "probe_stack"
6143 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6146 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6147 INTVAL (operands[0])));
6148 MEM_VOLATILE_P (operands[1]) = 1;
6150 operands[0] = const0_rtx;
6153 ;; This is how we allocate stack space. If we are allocating a
6154 ;; constant amount of space and we know it is less than 4096
6155 ;; bytes, we need do nothing.
6157 ;; If it is more than 4096 bytes, we need to probe the stack
6159 (define_expand "allocate_stack"
6161 (plus:DI (reg:DI 30)
6162 (match_operand:DI 1 "reg_or_cint_operand" "")))
6163 (set (match_operand:DI 0 "register_operand" "=r")
6167 if (GET_CODE (operands[1]) == CONST_INT
6168 && INTVAL (operands[1]) < 32768)
6170 if (INTVAL (operands[1]) >= 4096)
6172 /* We do this the same way as in the prologue and generate explicit
6173 probes. Then we update the stack by the constant. */
6177 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6178 while (probed + 8192 < INTVAL (operands[1]))
6179 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6181 if (probed + 4096 < INTVAL (operands[1]))
6182 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6185 operands[1] = GEN_INT (- INTVAL (operands[1]));
6186 operands[2] = virtual_stack_dynamic_rtx;
6191 rtx loop_label = gen_label_rtx ();
6192 rtx want = gen_reg_rtx (Pmode);
6193 rtx tmp = gen_reg_rtx (Pmode);
6196 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6197 force_reg (Pmode, operands[1])));
6198 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6200 if (GET_CODE (operands[1]) != CONST_INT)
6202 out_label = gen_label_rtx ();
6203 emit_insn (gen_cmpdi (want, tmp));
6204 emit_jump_insn (gen_bgeu (out_label));
6207 emit_label (loop_label);
6208 memref = gen_rtx_MEM (DImode, tmp);
6209 MEM_VOLATILE_P (memref) = 1;
6210 emit_move_insn (memref, const0_rtx);
6211 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6212 emit_insn (gen_cmpdi (tmp, want));
6213 emit_jump_insn (gen_bgtu (loop_label));
6215 memref = gen_rtx_MEM (DImode, want);
6216 MEM_VOLATILE_P (memref) = 1;
6217 emit_move_insn (memref, const0_rtx);
6220 emit_label (out_label);
6222 emit_move_insn (stack_pointer_rtx, want);
6223 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6228 ;; This is used by alpha_expand_prolog to do the same thing as above,
6229 ;; except we cannot at that time generate new basic blocks, so we hide
6230 ;; the loop in this one insn.
6232 (define_insn "prologue_stack_probe_loop"
6233 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6234 (match_operand:DI 1 "register_operand" "r")]
6238 operands[2] = gen_label_rtx ();
6239 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6240 CODE_LABEL_NUMBER (operands[2]));
6242 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6244 [(set_attr "length" "16")
6245 (set_attr "type" "multi")])
6247 (define_expand "prologue"
6248 [(clobber (const_int 0))]
6251 alpha_expand_prologue ();
6255 ;; These take care of emitting the ldgp insn in the prologue. This will be
6256 ;; an lda/ldah pair and we want to align them properly. So we have two
6257 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6258 ;; and the second of which emits nothing. However, both are marked as type
6259 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6262 (define_expand "prologue_ldgp"
6263 [(unspec_volatile [(const_int 0)] UNSPECV_LDGP1)
6264 (unspec_volatile [(const_int 0)] UNSPECV_LDGP2)]
6268 (define_insn "*prologue_ldgp_1_er"
6269 [(unspec_volatile [(const_int 0)] UNSPECV_LDGP1)]
6270 "TARGET_EXPLICIT_RELOCS"
6271 "ldah $29,0($27)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*\n$%~..ng:")
6273 (define_insn "*prologue_ldgp_1"
6274 [(unspec_volatile [(const_int 0)] UNSPECV_LDGP1)]
6276 "ldgp $29,0($27)\n$%~..ng:")
6278 (define_insn "*prologue_ldgp_2"
6279 [(unspec_volatile [(const_int 0)] UNSPECV_LDGP2)]
6283 ;; The _mcount profiling hook has special calling conventions, and
6284 ;; does not clobber all the registers that a normal call would. So
6285 ;; hide the fact this is a call at all.
6287 (define_insn "prologue_mcount"
6288 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6290 "lda $28,_mcount\;jsr $28,($28),_mcount"
6291 [(set_attr "type" "multi")
6292 (set_attr "length" "8")])
6294 (define_insn "init_fp"
6295 [(set (match_operand:DI 0 "register_operand" "=r")
6296 (match_operand:DI 1 "register_operand" "r"))
6297 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6301 (define_expand "epilogue"
6305 alpha_expand_epilogue ();
6308 (define_expand "sibcall_epilogue"
6312 alpha_expand_epilogue ();
6316 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
6317 ;; the frame size into a register. We use this pattern to ensure
6318 ;; we get lda instead of addq.
6319 (define_insn "nt_lda"
6320 [(set (match_operand:DI 0 "register_operand" "=r")
6321 (unspec:DI [(match_dup 0)
6322 (match_operand:DI 1 "const_int_operand" "n")]
6327 (define_expand "builtin_longjmp"
6328 [(use (match_operand:DI 0 "register_operand" "r"))]
6331 /* The elements of the buffer are, in order: */
6332 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6333 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6334 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6335 rtx pv = gen_rtx_REG (Pmode, 27);
6337 /* This bit is the same as expand_builtin_longjmp. */
6338 emit_move_insn (hard_frame_pointer_rtx, fp);
6339 emit_move_insn (pv, lab);
6340 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6341 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6342 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6344 /* Load the label we are jumping through into $27 so that we know
6345 where to look for it when we get back to setjmp's function for
6346 restoring the gp. */
6347 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6352 ;; This is effectively a copy of indirect_jump, but constrained such
6353 ;; that register renaming cannot foil our cunning plan with $27.
6354 (define_insn "builtin_longjmp_internal"
6356 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6360 [(set_attr "type" "ibr")])
6362 (define_insn "*builtin_setjmp_receiver_sub_label_er"
6363 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6364 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && TARGET_AS_CAN_SUBTRACT_LABELS"
6365 "\n$LSJ%=:\;ldah $29,0($27)\t\t!gpdisp!%*\;lda $29,$LSJ%=-%l0($29)\t\t!gpdisp!%*"
6366 [(set_attr "length" "8")
6367 (set_attr "type" "multi")])
6369 (define_insn "*builtin_setjmp_receiver_sub_label"
6370 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6371 "TARGET_ABI_OSF && TARGET_AS_CAN_SUBTRACT_LABELS"
6372 "\n$LSJ%=:\;ldgp $29,$LSJ%=-%l0($27)"
6373 [(set_attr "length" "8")
6374 (set_attr "type" "multi")])
6376 (define_insn "*builtin_setjmp_receiver_er"
6377 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6378 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6379 "br $29,$LSJ%=\n$LSJ%=:\;ldah $29,0($29)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
6380 [(set_attr "length" "12")
6381 (set_attr "type" "multi")])
6383 (define_insn "builtin_setjmp_receiver"
6384 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6386 "br $29,$LSJ%=\n$LSJ%=:\;ldgp $29,0($29)"
6387 [(set_attr "length" "12")
6388 (set_attr "type" "multi")])
6390 (define_expand "exception_receiver"
6391 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
6394 if (TARGET_LD_BUGGY_LDGP)
6395 operands[0] = alpha_gp_save_rtx ();
6397 operands[0] = const0_rtx;
6400 (define_insn "*exception_receiver_1_er"
6401 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6402 "TARGET_EXPLICIT_RELOCS && ! TARGET_LD_BUGGY_LDGP"
6403 "ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
6404 [(set_attr "length" "8")
6405 (set_attr "type" "multi")])
6407 (define_insn "*exception_receiver_1"
6408 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6409 "! TARGET_LD_BUGGY_LDGP"
6411 [(set_attr "length" "8")
6412 (set_attr "type" "multi")])
6414 ;; ??? We don't represent the usage of $29 properly in address loads
6415 ;; and function calls. This leads to the following move being deleted
6416 ;; as dead code unless it is represented as a volatile unspec.
6418 (define_insn "*exception_receiver_2"
6419 [(unspec_volatile [(match_operand:DI 0 "nonimmediate_operand" "r,m")]
6421 "TARGET_LD_BUGGY_LDGP"
6425 [(set_attr "type" "ilog,ild")])
6427 (define_expand "nonlocal_goto_receiver"
6428 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6429 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6430 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6432 "TARGET_ABI_OPEN_VMS"
6435 (define_insn "arg_home"
6436 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6451 (clobber (mem:BLK (const_int 0)))
6452 (clobber (reg:DI 24))
6453 (clobber (reg:DI 25))
6454 (clobber (reg:DI 0))]
6455 "TARGET_ABI_OPEN_VMS"
6456 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
6457 [(set_attr "length" "16")
6458 (set_attr "type" "multi")])
6460 ;; Load the CIW into r2 for calling __T3E_MISMATCH
6462 (define_expand "umk_mismatch_args"
6463 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
6464 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
6465 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
6466 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
6469 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
6470 "TARGET_ABI_UNICOSMK"
6472 operands[1] = gen_reg_rtx (DImode);
6473 operands[2] = gen_reg_rtx (DImode);
6474 operands[3] = gen_reg_rtx (DImode);
6477 (define_insn "arg_home_umk"
6478 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6493 (clobber (mem:BLK (const_int 0)))
6495 (clobber (reg:DI 22))
6496 (clobber (reg:DI 23))
6497 (clobber (reg:DI 24))
6498 (clobber (reg:DI 0))
6499 (clobber (reg:DI 1))
6500 (clobber (reg:DI 2))
6501 (clobber (reg:DI 3))
6502 (clobber (reg:DI 4))
6503 (clobber (reg:DI 5))
6504 (clobber (reg:DI 6))
6505 (clobber (reg:DI 7))
6506 (clobber (reg:DI 8))])]
6507 "TARGET_ABI_UNICOSMK"
6508 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
6509 [(set_attr "length" "16")
6510 (set_attr "type" "multi")])
6512 ;; Close the trap shadow of preceeding instructions. This is generated
6515 (define_insn "trapb"
6516 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
6519 [(set_attr "type" "misc")])
6521 ;; No-op instructions used by machine-dependant reorg to preserve
6522 ;; alignment for instruction issue.
6523 ;; The Unicos/Mk assembler does not support these opcodes.
6529 [(set_attr "type" "ilog")])
6534 "cpys $f31,$f31,$f31"
6535 [(set_attr "type" "fcpys")])
6542 ;; On Unicos/Mk we use a macro for aligning code.
6544 (define_insn "realign"
6545 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
6549 if (TARGET_ABI_UNICOSMK)
6550 return "gcc@code@align %0";
6552 return ".align %0 #realign";
6555 ;; The call patterns are at the end of the file because their
6556 ;; wildcard operand0 interferes with nice recognition.
6558 (define_insn "*call_value_umk"
6559 [(set (match_operand 0 "" "")
6560 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
6561 (match_operand 2 "" "")))
6563 (clobber (reg:DI 26))]
6564 "TARGET_ABI_UNICOSMK"
6566 [(set_attr "type" "jsr")])
6568 (define_insn "*call_value_osf_1_er"
6569 [(set (match_operand 0 "" "")
6570 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,i"))
6571 (match_operand 2 "" "")))
6572 (clobber (reg:DI 27))
6573 (clobber (reg:DI 26))]
6574 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6576 jsr $26,($27),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
6578 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),%1\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
6579 [(set_attr "type" "jsr")
6580 (set_attr "length" "12,*,16")])
6582 (define_insn "*call_value_osf_1"
6583 [(set (match_operand 0 "" "")
6584 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,i"))
6585 (match_operand 2 "" "")))
6586 (clobber (reg:DI 27))
6587 (clobber (reg:DI 26))]
6590 jsr $26,($27),0\;ldgp $29,0($26)
6592 jsr $26,%1\;ldgp $29,0($26)"
6593 [(set_attr "type" "jsr")
6594 (set_attr "length" "12,*,16")])
6596 (define_insn "*sibcall_value_osf_1"
6597 [(set (match_operand 0 "" "")
6598 (call (mem:DI (match_operand:DI 1 "current_file_function_operand" "R"))
6599 (match_operand 2 "" "")))]
6602 [(set_attr "type" "jsr")])
6604 (define_insn "*call_value_nt_1"
6605 [(set (match_operand 0 "" "")
6606 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
6607 (match_operand 2 "" "")))
6608 (clobber (reg:DI 26))]
6609 "TARGET_ABI_WINDOWS_NT"
6614 [(set_attr "type" "jsr")
6615 (set_attr "length" "*,*,12")])
6617 (define_insn "*call_value_vms_1"
6618 [(set (match_operand 0 "" "")
6619 (call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
6620 (match_operand 2 "" "")))
6621 (use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
6624 (clobber (reg:DI 27))]
6625 "TARGET_ABI_OPEN_VMS"
6627 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
6628 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
6629 [(set_attr "type" "jsr")
6630 (set_attr "length" "12,16")])