gcc/config/alpha/ev4.md

   1 ;; Scheduling description for Alpha EV4.
   2 ;;   Copyright (C) 2002, 2004, 2005 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 2, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING.  If not, write to
  18 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
  19 ;; Boston, MA 02110-1301, USA.
  20
  21 ; On EV4 there are two classes of resources to consider: resources needed
  22 ; to issue, and resources needed to execute.  IBUS[01] are in the first
  23 ; category.  ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
  24 ; (There are a few other register-like resources, but ...)
  25
  26 (define_automaton "ev4_0,ev4_1,ev4_2")
  27 (define_cpu_unit "ev4_ib0,ev4_ib1,ev4_abox,ev4_bbox" "ev4_0")
  28 (define_cpu_unit "ev4_ebox,ev4_imul" "ev4_1")
  29 (define_cpu_unit "ev4_fbox,ev4_fdiv" "ev4_2")
  30 (define_reservation "ev4_ib01" "ev4_ib0|ev4_ib1")
  31
  32 ; Assume type "multi" single issues.
  33 (define_insn_reservation "ev4_multi" 1
  34   (and (eq_attr "tune" "ev4")
  35        (eq_attr "type" "multi"))
  36   "ev4_ib0+ev4_ib1")
  37
  38 ; Loads from L0 completes in three cycles.  adjust_cost still factors
  39 ; in user-specified memory latency, so return 1 here.
  40 (define_insn_reservation "ev4_ld" 1
  41   (and (eq_attr "tune" "ev4")
  42        (eq_attr "type" "ild,fld,ldsym,ld_l"))
  43   "ev4_ib01+ev4_abox")
  44
  45 ; Stores can issue before the data (but not address) is ready.
  46 (define_insn_reservation "ev4_ist" 1
  47   (and (eq_attr "tune" "ev4")
  48        (eq_attr "type" "ist"))
  49   "ev4_ib1+ev4_abox")
  50
  51 ; ??? Separate from ev4_ist because store_data_bypass_p can't handle
  52 ; the patterns with multiple sets, like store-conditional.
  53 (define_insn_reservation "ev4_ist_c" 1
  54   (and (eq_attr "tune" "ev4")
  55        (eq_attr "type" "st_c"))
  56   "ev4_ib1+ev4_abox")
  57
  58 (define_insn_reservation "ev4_fst" 1
  59   (and (eq_attr "tune" "ev4")
  60        (eq_attr "type" "fst"))
  61   "ev4_ib0+ev4_abox")
  62
  63 ; Memory barrier blocks ABOX insns until it's acknowledged by the external
  64 ; memory bus.  This may be *quite* slow.  Setting this to 4 cycles gets
  65 ; about all the benefit without making the DFA too large.
  66 (define_insn_reservation "ev4_mb" 4
  67   (and (eq_attr "tune" "ev4")
  68        (eq_attr "type" "mb"))
  69   "ev4_ib1+ev4_abox,ev4_abox*3")
  70
  71 ; Branches have no delay cost, but do tie up the unit for two cycles.
  72 (define_insn_reservation "ev4_ibr" 2
  73   (and (eq_attr "tune" "ev4")
  74        (eq_attr "type" "ibr,jsr"))
  75   "ev4_ib1+ev4_bbox,ev4_bbox")
  76
  77 (define_insn_reservation "ev4_callpal" 2
  78   (and (eq_attr "tune" "ev4")
  79        (eq_attr "type" "callpal"))
  80   "ev4_ib1+ev4_bbox,ev4_bbox")
  81
  82 (define_insn_reservation "ev4_fbr" 2
  83   (and (eq_attr "tune" "ev4")
  84        (eq_attr "type" "fbr"))
  85   "ev4_ib0+ev4_bbox,ev4_bbox")
  86
  87 ; Arithmetic insns are normally have their results available after
  88 ; two cycles.  There are a number of exceptions.
  89
  90 (define_insn_reservation "ev4_iaddlog" 2
  91   (and (eq_attr "tune" "ev4")
  92        (eq_attr "type" "iadd,ilog"))
  93   "ev4_ib0+ev4_ebox")
  94
  95 (define_bypass 1
  96   "ev4_iaddlog"
  97   "ev4_ibr,ev4_iaddlog,ev4_shiftcm,ev4_icmp,ev4_imulsi,ev4_imuldi")
  98
  99 (define_insn_reservation "ev4_shiftcm" 2
 100   (and (eq_attr "tune" "ev4")
 101        (eq_attr "type" "shift,icmov"))
 102   "ev4_ib0+ev4_ebox")
 103
 104 (define_insn_reservation "ev4_icmp" 2
 105   (and (eq_attr "tune" "ev4")
 106        (eq_attr "type" "icmp"))
 107   "ev4_ib0+ev4_ebox")
 108
 109 (define_bypass 1 "ev4_icmp" "ev4_ibr")
 110
 111 (define_bypass 0
 112   "ev4_iaddlog,ev4_shiftcm,ev4_icmp"
 113   "ev4_ist"
 114   "store_data_bypass_p")
 115
 116 ; Multiplies use a non-pipelined imul unit.  Also, "no [ebox] insn can
 117 ; be issued exactly three cycles before an integer multiply completes".
 118
 119 (define_insn_reservation "ev4_imulsi" 21
 120   (and (eq_attr "tune" "ev4")
 121        (and (eq_attr "type" "imul")
 122             (eq_attr "opsize" "si")))
 123   "ev4_ib0+ev4_imul,ev4_imul*18,ev4_ebox")
 124
 125 (define_bypass 20 "ev4_imulsi" "ev4_ist" "store_data_bypass_p")
 126
 127 (define_insn_reservation "ev4_imuldi" 23
 128   (and (eq_attr "tune" "ev4")
 129        (and (eq_attr "type" "imul")
 130             (eq_attr "opsize" "!si")))
 131   "ev4_ib0+ev4_imul,ev4_imul*20,ev4_ebox")
 132
 133 (define_bypass 22 "ev4_imuldi" "ev4_ist" "store_data_bypass_p")
 134
 135 ; Most FP insns have a 6 cycle latency, but with a 4 cycle bypass back in.
 136 (define_insn_reservation "ev4_fpop" 6
 137   (and (eq_attr "tune" "ev4")
 138        (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
 139   "ev4_ib1+ev4_fbox")
 140
 141 (define_bypass 4 "ev4_fpop" "ev4_fpop")
 142
 143 ; The floating point divider is not pipelined.  Also, "no FPOP insn can be
 144 ; issued exactly five or exactly six cycles before an fdiv insn completes".
 145
 146 (define_insn_reservation "ev4_fdivsf" 34
 147   (and (eq_attr "tune" "ev4")
 148        (and (eq_attr "type" "fdiv")
 149             (eq_attr "opsize" "si")))
 150   "ev4_ib1+ev4_fdiv,ev4_fdiv*28,ev4_fdiv+ev4_fbox,ev4_fbox")
 151
 152 (define_insn_reservation "ev4_fdivdf" 63
 153   (and (eq_attr "tune" "ev4")
 154        (and (eq_attr "type" "fdiv")
 155             (eq_attr "opsize" "di")))
 156   "ev4_ib1+ev4_fdiv,ev4_fdiv*57,ev4_fdiv+ev4_fbox,ev4_fbox")
 157
 158 ; Traps don't consume or produce data.
 159 (define_insn_reservation "ev4_misc" 1
 160   (and (eq_attr "tune" "ev4")
 161        (eq_attr "type" "misc"))
 162   "ev4_ib1")