1 /* Subroutines used for code generation on the Argonaut ARC cpu.
2 Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* ??? This is an old port, and is undoubtedly suffering from bit rot. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
42 #include "target-def.h"
44 /* Which cpu we're compiling for (NULL(=base), ???). */
45 const char *arc_cpu_string
;
48 /* Name of mangle string to add to symbols to separate code compiled for each
50 const char *arc_mangle_cpu
;
52 /* Save the operands last given to a compare for use when we
53 generate a scc or bcc insn. */
54 rtx arc_compare_op0
, arc_compare_op1
;
56 /* Name of text, data, and rodata sections, as specified on command line.
57 Selected by -m{text,data,rodata} flags. */
58 const char *arc_text_string
= ARC_DEFAULT_TEXT_SECTION
;
59 const char *arc_data_string
= ARC_DEFAULT_DATA_SECTION
;
60 const char *arc_rodata_string
= ARC_DEFAULT_RODATA_SECTION
;
62 /* Name of text, data, and rodata sections used in varasm.c. */
63 const char *arc_text_section
;
64 const char *arc_data_section
;
65 const char *arc_rodata_section
;
67 /* Array of valid operand punctuation characters. */
68 char arc_punct_chars
[256];
70 /* Variables used by arc_final_prescan_insn to implement conditional
72 static int arc_ccfsm_state
;
73 static int arc_ccfsm_current_cc
;
74 static rtx arc_ccfsm_target_insn
;
75 static int arc_ccfsm_target_label
;
77 /* The maximum number of insns skipped which will be conditionalised if
79 #define MAX_INSNS_SKIPPED 3
81 /* A nop is needed between a 4 byte insn that sets the condition codes and
82 a branch that uses them (the same isn't true for an 8 byte insn that sets
83 the condition codes). Set by arc_final_prescan_insn. Used by
85 static int last_insn_set_cc_p
;
86 static int current_insn_set_cc_p
;
87 static void record_cc_ref
PARAMS ((rtx
));
88 static void arc_init_reg_tables
PARAMS ((void));
89 static int get_arc_condition_code
PARAMS ((rtx
));
90 const struct attribute_spec arc_attribute_table
[];
91 static tree arc_handle_interrupt_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
92 static bool arc_assemble_integer
PARAMS ((rtx
, unsigned int, int));
93 static void arc_output_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
94 static void arc_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
95 static void arc_encode_section_info
PARAMS ((tree
, int));
97 /* Initialize the GCC target structure. */
98 #undef TARGET_ASM_ALIGNED_HI_OP
99 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
100 #undef TARGET_ASM_ALIGNED_SI_OP
101 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
102 #undef TARGET_ASM_INTEGER
103 #define TARGET_ASM_INTEGER arc_assemble_integer
105 #undef TARGET_ASM_FUNCTION_PROLOGUE
106 #define TARGET_ASM_FUNCTION_PROLOGUE arc_output_function_prologue
107 #undef TARGET_ASM_FUNCTION_EPILOGUE
108 #define TARGET_ASM_FUNCTION_EPILOGUE arc_output_function_epilogue
109 #undef TARGET_ATTRIBUTE_TABLE
110 #define TARGET_ATTRIBUTE_TABLE arc_attribute_table
111 #undef TARGET_ENCODE_SECTION_INFO
112 #define TARGET_ENCODE_SECTION_INFO arc_encode_section_info
114 struct gcc_target targetm
= TARGET_INITIALIZER
;
116 /* Called by OVERRIDE_OPTIONS to initialize various things. */
123 if (arc_cpu_string
== 0
124 || !strcmp (arc_cpu_string
, "base"))
126 /* Ensure we have a printable value for the .cpu pseudo-op. */
127 arc_cpu_string
= "base";
129 arc_mangle_cpu
= NULL
;
131 else if (ARC_EXTENSION_CPU (arc_cpu_string
))
132 ; /* nothing to do */
135 error ("bad value (%s) for -mcpu switch", arc_cpu_string
);
136 arc_cpu_string
= "base";
138 arc_mangle_cpu
= NULL
;
141 /* Set the pseudo-ops for the various standard sections. */
142 arc_text_section
= tmp
= xmalloc (strlen (arc_text_string
) + sizeof (ARC_SECTION_FORMAT
) + 1);
143 sprintf (tmp
, ARC_SECTION_FORMAT
, arc_text_string
);
144 arc_data_section
= tmp
= xmalloc (strlen (arc_data_string
) + sizeof (ARC_SECTION_FORMAT
) + 1);
145 sprintf (tmp
, ARC_SECTION_FORMAT
, arc_data_string
);
146 arc_rodata_section
= tmp
= xmalloc (strlen (arc_rodata_string
) + sizeof (ARC_SECTION_FORMAT
) + 1);
147 sprintf (tmp
, ARC_SECTION_FORMAT
, arc_rodata_string
);
149 arc_init_reg_tables ();
151 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
152 memset (arc_punct_chars
, 0, sizeof (arc_punct_chars
));
153 arc_punct_chars
['#'] = 1;
154 arc_punct_chars
['*'] = 1;
155 arc_punct_chars
['?'] = 1;
156 arc_punct_chars
['!'] = 1;
157 arc_punct_chars
['~'] = 1;
160 /* The condition codes of the ARC, and the inverse function. */
161 static const char *const arc_condition_codes
[] =
163 "al", 0, "eq", "ne", "p", "n", "c", "nc", "v", "nv",
164 "gt", "le", "ge", "lt", "hi", "ls", "pnz", 0
167 #define ARC_INVERSE_CONDITION_CODE(X) ((X) ^ 1)
169 /* Returns the index of the ARC condition code string in
170 `arc_condition_codes'. COMPARISON should be an rtx like
171 `(eq (...) (...))'. */
174 get_arc_condition_code (comparison
)
177 switch (GET_CODE (comparison
))
185 case GTU
: return 14;
186 case LEU
: return 15;
195 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
196 return the mode to be used for the comparison. */
199 arc_select_cc_mode (op
, x
, y
)
201 rtx x
, y ATTRIBUTE_UNUSED
;
209 switch (GET_CODE (x
))
228 /* Vectors to keep interesting information about registers where it can easily
229 be got. We use to use the actual mode value as the bit number, but there
230 is (or may be) more than 32 modes now. Instead we use two tables: one
231 indexed by hard register number, and one indexed by mode. */
233 /* The purpose of arc_mode_class is to shrink the range of modes so that
234 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
235 mapped into one arc_mode_class mode. */
237 enum arc_mode_class
{
239 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
240 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
243 /* Modes for condition codes. */
244 #define C_MODES (1 << (int) C_MODE)
246 /* Modes for single-word and smaller quantities. */
247 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
249 /* Modes for double-word and smaller quantities. */
250 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
252 /* Modes for quad-word and smaller quantities. */
253 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
255 /* Value is 1 if register/mode pair is acceptable on arc. */
257 const unsigned int arc_hard_regno_mode_ok
[] = {
258 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
,
259 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
,
260 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, D_MODES
,
261 D_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
,
263 /* ??? Leave these as S_MODES for now. */
264 S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
,
265 S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
,
266 S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
,
267 S_MODES
, S_MODES
, S_MODES
, S_MODES
, S_MODES
, C_MODES
270 unsigned int arc_mode_class
[NUM_MACHINE_MODES
];
272 enum reg_class arc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
275 arc_init_reg_tables ()
279 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
281 switch (GET_MODE_CLASS (i
))
284 case MODE_PARTIAL_INT
:
285 case MODE_COMPLEX_INT
:
286 if (GET_MODE_SIZE (i
) <= 4)
287 arc_mode_class
[i
] = 1 << (int) S_MODE
;
288 else if (GET_MODE_SIZE (i
) == 8)
289 arc_mode_class
[i
] = 1 << (int) D_MODE
;
290 else if (GET_MODE_SIZE (i
) == 16)
291 arc_mode_class
[i
] = 1 << (int) T_MODE
;
292 else if (GET_MODE_SIZE (i
) == 32)
293 arc_mode_class
[i
] = 1 << (int) O_MODE
;
295 arc_mode_class
[i
] = 0;
298 case MODE_COMPLEX_FLOAT
:
299 if (GET_MODE_SIZE (i
) <= 4)
300 arc_mode_class
[i
] = 1 << (int) SF_MODE
;
301 else if (GET_MODE_SIZE (i
) == 8)
302 arc_mode_class
[i
] = 1 << (int) DF_MODE
;
303 else if (GET_MODE_SIZE (i
) == 16)
304 arc_mode_class
[i
] = 1 << (int) TF_MODE
;
305 else if (GET_MODE_SIZE (i
) == 32)
306 arc_mode_class
[i
] = 1 << (int) OF_MODE
;
308 arc_mode_class
[i
] = 0;
312 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
313 we must explicitly check for them here. */
314 if (i
== (int) CCmode
|| i
== (int) CCZNmode
|| i
== (int) CCZNCmode
)
315 arc_mode_class
[i
] = 1 << (int) C_MODE
;
317 arc_mode_class
[i
] = 0;
322 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
325 arc_regno_reg_class
[i
] = GENERAL_REGS
;
327 arc_regno_reg_class
[i
] = LPCOUNT_REG
;
329 arc_regno_reg_class
[i
] = NO_REGS
/* CC_REG: must be NO_REGS */;
331 arc_regno_reg_class
[i
] = NO_REGS
;
335 /* ARC specific attribute support.
337 The ARC has these attributes:
338 interrupt - for interrupt functions
341 const struct attribute_spec arc_attribute_table
[] =
343 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
344 { "interrupt", 1, 1, true, false, false, arc_handle_interrupt_attribute
},
345 { NULL
, 0, 0, false, false, false, NULL
}
348 /* Handle an "interrupt" attribute; arguments as in
349 struct attribute_spec.handler. */
351 arc_handle_interrupt_attribute (node
, name
, args
, flags
, no_add_attrs
)
352 tree
*node ATTRIBUTE_UNUSED
;
355 int flags ATTRIBUTE_UNUSED
;
358 tree value
= TREE_VALUE (args
);
360 if (TREE_CODE (value
) != STRING_CST
)
362 warning ("argument of `%s' attribute is not a string constant",
363 IDENTIFIER_POINTER (name
));
364 *no_add_attrs
= true;
366 else if (strcmp (TREE_STRING_POINTER (value
), "ilink1")
367 && strcmp (TREE_STRING_POINTER (value
), "ilink2"))
369 warning ("argument of `%s' attribute is not \"ilink1\" or \"ilink2\"",
370 IDENTIFIER_POINTER (name
));
371 *no_add_attrs
= true;
378 /* Acceptable arguments to the call insn. */
381 call_address_operand (op
, mode
)
383 enum machine_mode mode
;
385 return (symbolic_operand (op
, mode
)
386 || (GET_CODE (op
) == CONST_INT
&& LEGITIMATE_CONSTANT_P (op
))
387 || (GET_CODE (op
) == REG
));
391 call_operand (op
, mode
)
393 enum machine_mode mode
;
395 if (GET_CODE (op
) != MEM
)
398 return call_address_operand (op
, mode
);
401 /* Returns 1 if OP is a symbol reference. */
404 symbolic_operand (op
, mode
)
406 enum machine_mode mode ATTRIBUTE_UNUSED
;
408 switch (GET_CODE (op
))
419 /* Return truth value of statement that OP is a symbolic memory
420 operand of mode MODE. */
423 symbolic_memory_operand (op
, mode
)
425 enum machine_mode mode ATTRIBUTE_UNUSED
;
427 if (GET_CODE (op
) == SUBREG
)
428 op
= SUBREG_REG (op
);
429 if (GET_CODE (op
) != MEM
)
432 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
433 || GET_CODE (op
) == LABEL_REF
);
436 /* Return true if OP is a short immediate (shimm) value. */
439 short_immediate_operand (op
, mode
)
441 enum machine_mode mode ATTRIBUTE_UNUSED
;
443 if (GET_CODE (op
) != CONST_INT
)
445 return SMALL_INT (INTVAL (op
));
448 /* Return true if OP will require a long immediate (limm) value.
449 This is currently only used when calculating length attributes. */
452 long_immediate_operand (op
, mode
)
454 enum machine_mode mode ATTRIBUTE_UNUSED
;
456 switch (GET_CODE (op
))
463 return !SMALL_INT (INTVAL (op
));
465 /* These can happen because large unsigned 32 bit constants are
466 represented this way (the multiplication patterns can cause these
467 to be generated). They also occur for SFmode values. */
475 /* Return true if OP is a MEM that when used as a load or store address will
476 require an 8 byte insn.
477 Load and store instructions don't allow the same possibilities but they're
478 similar enough that this one function will do.
479 This is currently only used when calculating length attributes. */
482 long_immediate_loadstore_operand (op
, mode
)
484 enum machine_mode mode ATTRIBUTE_UNUSED
;
486 if (GET_CODE (op
) != MEM
)
490 switch (GET_CODE (op
))
497 /* This must be handled as "st c,[limm]". Ditto for load.
498 Technically, the assembler could translate some possibilities to
499 "st c,[limm/2 + limm/2]" if limm/2 will fit in a shimm, but we don't
500 assume that it does. */
503 /* These can happen because large unsigned 32 bit constants are
504 represented this way (the multiplication patterns can cause these
505 to be generated). They also occur for SFmode values. */
510 if (GET_CODE (XEXP (op
, 1)) == CONST_INT
511 && !SMALL_INT (INTVAL (XEXP (op
, 1))))
520 /* Return true if OP is an acceptable argument for a single word
524 move_src_operand (op
, mode
)
526 enum machine_mode mode
;
528 switch (GET_CODE (op
))
535 return (LARGE_INT (INTVAL (op
)));
537 /* We can handle DImode integer constants in SImode if the value
538 (signed or unsigned) will fit in 32 bits. This is needed because
539 large unsigned 32 bit constants are represented as CONST_DOUBLEs. */
541 return arc_double_limm_p (op
);
542 /* We can handle 32 bit floating point constants. */
544 return GET_MODE (op
) == SFmode
;
547 return register_operand (op
, mode
);
549 /* (subreg (mem ...) ...) can occur here if the inner part was once a
550 pseudo-reg and is now a stack slot. */
551 if (GET_CODE (SUBREG_REG (op
)) == MEM
)
552 return address_operand (XEXP (SUBREG_REG (op
), 0), mode
);
554 return register_operand (op
, mode
);
556 return address_operand (XEXP (op
, 0), mode
);
562 /* Return true if OP is an acceptable argument for a double word
566 move_double_src_operand (op
, mode
)
568 enum machine_mode mode
;
570 switch (GET_CODE (op
))
573 return register_operand (op
, mode
);
575 /* (subreg (mem ...) ...) can occur here if the inner part was once a
576 pseudo-reg and is now a stack slot. */
577 if (GET_CODE (SUBREG_REG (op
)) == MEM
)
578 return move_double_src_operand (SUBREG_REG (op
), mode
);
580 return register_operand (op
, mode
);
582 /* Disallow auto inc/dec for now. */
583 if (GET_CODE (XEXP (op
, 0)) == PRE_DEC
584 || GET_CODE (XEXP (op
, 0)) == PRE_INC
)
586 return address_operand (XEXP (op
, 0), mode
);
595 /* Return true if OP is an acceptable argument for a move destination. */
598 move_dest_operand (op
, mode
)
600 enum machine_mode mode
;
602 switch (GET_CODE (op
))
605 return register_operand (op
, mode
);
607 /* (subreg (mem ...) ...) can occur here if the inner part was once a
608 pseudo-reg and is now a stack slot. */
609 if (GET_CODE (SUBREG_REG (op
)) == MEM
)
610 return address_operand (XEXP (SUBREG_REG (op
), 0), mode
);
612 return register_operand (op
, mode
);
614 return address_operand (XEXP (op
, 0), mode
);
620 /* Return true if OP is valid load with update operand. */
623 load_update_operand (op
, mode
)
625 enum machine_mode mode
;
627 if (GET_CODE (op
) != MEM
628 || GET_MODE (op
) != mode
)
631 if (GET_CODE (op
) != PLUS
632 || GET_MODE (op
) != Pmode
633 || !register_operand (XEXP (op
, 0), Pmode
)
634 || !nonmemory_operand (XEXP (op
, 1), Pmode
))
639 /* Return true if OP is valid store with update operand. */
642 store_update_operand (op
, mode
)
644 enum machine_mode mode
;
646 if (GET_CODE (op
) != MEM
647 || GET_MODE (op
) != mode
)
650 if (GET_CODE (op
) != PLUS
651 || GET_MODE (op
) != Pmode
652 || !register_operand (XEXP (op
, 0), Pmode
)
653 || !(GET_CODE (XEXP (op
, 1)) == CONST_INT
654 && SMALL_INT (INTVAL (XEXP (op
, 1)))))
659 /* Return true if OP is a non-volatile non-immediate operand.
660 Volatile memory refs require a special "cache-bypass" instruction
661 and only the standard movXX patterns are set up to handle them. */
664 nonvol_nonimm_operand (op
, mode
)
666 enum machine_mode mode
;
668 if (GET_CODE (op
) == MEM
&& MEM_VOLATILE_P (op
))
670 return nonimmediate_operand (op
, mode
);
673 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
674 to check the range carefully since this predicate is used in DImode
678 const_sint32_operand (op
, mode
)
680 enum machine_mode mode ATTRIBUTE_UNUSED
;
682 /* All allowed constants will fit a CONST_INT. */
683 return (GET_CODE (op
) == CONST_INT
684 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));
687 /* Accept integer operands in the range 0..0xffffffff. We have to check the
688 range carefully since this predicate is used in DImode contexts. Also, we
689 need some extra crud to make it work when hosted on 64-bit machines. */
692 const_uint32_operand (op
, mode
)
694 enum machine_mode mode ATTRIBUTE_UNUSED
;
696 #if HOST_BITS_PER_WIDE_INT > 32
697 /* All allowed constants will fit a CONST_INT. */
698 return (GET_CODE (op
) == CONST_INT
699 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
701 return ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) >= 0)
702 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
706 /* Return 1 if OP is a comparison operator valid for the mode of CC.
707 This allows the use of MATCH_OPERATOR to recognize all the branch insns.
709 Some insns only set a few bits in the condition code. So only allow those
710 comparisons that use the bits that are valid. */
713 proper_comparison_operator (op
, mode
)
715 enum machine_mode mode ATTRIBUTE_UNUSED
;
717 enum rtx_code code
= GET_CODE (op
);
719 if (GET_RTX_CLASS (code
) != '<')
722 if (GET_MODE (XEXP (op
, 0)) == CCZNmode
)
723 return (code
== EQ
|| code
== NE
);
724 if (GET_MODE (XEXP (op
, 0)) == CCZNCmode
)
725 return (code
== EQ
|| code
== NE
726 || code
== LTU
|| code
== GEU
|| code
== GTU
|| code
== LEU
);
730 /* Misc. utilities. */
732 /* X and Y are two things to compare using CODE. Emit the compare insn and
733 return the rtx for the cc reg in the proper mode. */
736 gen_compare_reg (code
, x
, y
)
740 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
743 cc_reg
= gen_rtx_REG (mode
, 61);
745 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
746 gen_rtx_COMPARE (mode
, x
, y
)));
751 /* Return 1 if VALUE, a const_double, will fit in a limm (4 byte number).
752 We assume the value can be either signed or unsigned. */
755 arc_double_limm_p (value
)
758 HOST_WIDE_INT low
, high
;
760 if (GET_CODE (value
) != CONST_DOUBLE
)
763 low
= CONST_DOUBLE_LOW (value
);
764 high
= CONST_DOUBLE_HIGH (value
);
766 if (low
& 0x80000000)
768 return (((unsigned HOST_WIDE_INT
) low
<= 0xffffffff && high
== 0)
769 || (((low
& - (unsigned HOST_WIDE_INT
) 0x80000000)
770 == - (unsigned HOST_WIDE_INT
) 0x80000000)
775 return (unsigned HOST_WIDE_INT
) low
<= 0x7fffffff && high
== 0;
779 /* Do any needed setup for a variadic function. For the ARC, we must
780 create a register parameter block, and then copy any anonymous arguments
781 in registers to memory.
783 CUM has not been updated for the last named argument which has type TYPE
784 and mode MODE, and we rely on this fact.
786 We do things a little weird here. We're supposed to only allocate space
787 for the anonymous arguments. However we need to keep the stack eight byte
788 aligned. So we round the space up if necessary, and leave it to va_start
792 arc_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
793 CUMULATIVE_ARGS
*cum
;
794 enum machine_mode mode
;
795 tree type ATTRIBUTE_UNUSED
;
801 /* All BLKmode values are passed by reference. */
805 first_anon_arg
= *cum
+ ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1)
808 if (first_anon_arg
< MAX_ARC_PARM_REGS
&& !no_rtl
)
810 /* Note that first_reg_offset < MAX_ARC_PARM_REGS. */
811 int first_reg_offset
= first_anon_arg
;
812 /* Size in words to "pretend" allocate. */
813 int size
= MAX_ARC_PARM_REGS
- first_reg_offset
;
814 /* Extra slop to keep stack eight byte aligned. */
815 int align_slop
= size
& 1;
818 regblock
= gen_rtx_MEM (BLKmode
,
819 plus_constant (arg_pointer_rtx
,
820 FIRST_PARM_OFFSET (0)
821 + align_slop
* UNITS_PER_WORD
));
822 set_mem_alias_set (regblock
, get_varargs_alias_set ());
823 set_mem_align (regblock
, BITS_PER_WORD
);
824 move_block_from_reg (first_reg_offset
, regblock
,
825 MAX_ARC_PARM_REGS
- first_reg_offset
,
826 ((MAX_ARC_PARM_REGS
- first_reg_offset
)
829 *pretend_size
= ((MAX_ARC_PARM_REGS
- first_reg_offset
+ align_slop
)
834 /* Cost functions. */
836 /* Provide the costs of an addressing mode that contains ADDR.
837 If ADDR is not a valid address, its cost is irrelevant. */
840 arc_address_cost (addr
)
843 switch (GET_CODE (addr
))
846 /* This is handled in the macro that calls us.
847 It's here for documentation. */
857 register rtx plus0
= XEXP (addr
, 0);
858 register rtx plus1
= XEXP (addr
, 1);
860 if (GET_CODE (plus0
) != REG
)
863 switch (GET_CODE (plus1
))
866 return SMALL_INT (plus1
) ? 1 : 2;
883 /* Function prologue/epilogue handlers. */
885 /* ARC stack frames look like:
887 Before call After call
888 +-----------------------+ +-----------------------+
890 high | local variables, | | local variables, |
891 mem | reg save area, etc. | | reg save area, etc. |
893 +-----------------------+ +-----------------------+
895 | arguments on stack. | | arguments on stack. |
897 SP+16->+-----------------------+FP+48->+-----------------------+
898 | 4 word save area for | | reg parm save area, |
899 | return addr, prev %fp | | only created for |
900 SP+0->+-----------------------+ | variable argument |
902 FP+16->+-----------------------+
903 | 4 word save area for |
904 | return addr, prev %fp |
905 FP+0->+-----------------------+
909 +-----------------------+
911 | register save area |
913 +-----------------------+
915 | alloca allocations |
917 +-----------------------+
919 | arguments on stack |
921 SP+16->+-----------------------+
922 low | 4 word save area for |
923 memory | return addr, prev %fp |
924 SP+0->+-----------------------+
927 1) The "reg parm save area" does not exist for non variable argument fns.
928 The "reg parm save area" can be eliminated completely if we created our
929 own va-arc.h, but that has tradeoffs as well (so it's not done). */
931 /* Structure to be filled in by arc_compute_frame_size with register
932 save masks, and offsets for the current function. */
933 struct arc_frame_info
935 unsigned int total_size
; /* # bytes that the entire frame takes up. */
936 unsigned int extra_size
; /* # bytes of extra stuff. */
937 unsigned int pretend_size
; /* # bytes we push and pretend caller did. */
938 unsigned int args_size
; /* # bytes that outgoing arguments take up. */
939 unsigned int reg_size
; /* # bytes needed to store regs. */
940 unsigned int var_size
; /* # bytes that variables take up. */
941 unsigned int reg_offset
; /* Offset from new sp to store regs. */
942 unsigned int gmask
; /* Mask of saved gp registers. */
943 int initialized
; /* Nonzero if frame size already calculated. */
946 /* Current frame information calculated by arc_compute_frame_size. */
947 static struct arc_frame_info current_frame_info
;
949 /* Zero structure to initialize current_frame_info. */
950 static struct arc_frame_info zero_frame_info
;
952 /* Type of function DECL.
954 The result is cached. To reset the cache at the end of a function,
955 call with DECL = NULL_TREE. */
957 enum arc_function_type
958 arc_compute_function_type (decl
)
963 static enum arc_function_type fn_type
= ARC_FUNCTION_UNKNOWN
;
964 /* Last function we were called for. */
965 static tree last_fn
= NULL_TREE
;
967 /* Resetting the cached value? */
968 if (decl
== NULL_TREE
)
970 fn_type
= ARC_FUNCTION_UNKNOWN
;
975 if (decl
== last_fn
&& fn_type
!= ARC_FUNCTION_UNKNOWN
)
978 /* Assume we have a normal function (not an interrupt handler). */
979 fn_type
= ARC_FUNCTION_NORMAL
;
981 /* Now see if this is an interrupt handler. */
982 for (a
= DECL_ATTRIBUTES (current_function_decl
);
986 tree name
= TREE_PURPOSE (a
), args
= TREE_VALUE (a
);
988 if (name
== get_identifier ("__interrupt__")
989 && list_length (args
) == 1
990 && TREE_CODE (TREE_VALUE (args
)) == STRING_CST
)
992 tree value
= TREE_VALUE (args
);
994 if (!strcmp (TREE_STRING_POINTER (value
), "ilink1"))
995 fn_type
= ARC_FUNCTION_ILINK1
;
996 else if (!strcmp (TREE_STRING_POINTER (value
), "ilink2"))
997 fn_type
= ARC_FUNCTION_ILINK2
;
1008 #define ILINK1_REGNUM 29
1009 #define ILINK2_REGNUM 30
1010 #define RETURN_ADDR_REGNUM 31
1011 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1012 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1014 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1015 The return address and frame pointer are treated separately.
1016 Don't consider them here. */
1017 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1018 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1019 && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
1021 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM])
1023 /* Return the bytes needed to compute the frame pointer from the current
1026 SIZE is the size needed for local variables. */
1029 arc_compute_frame_size (size
)
1030 int size
; /* # of var. bytes allocated. */
1033 unsigned int total_size
, var_size
, args_size
, pretend_size
, extra_size
;
1034 unsigned int reg_size
, reg_offset
;
1036 enum arc_function_type fn_type
;
1040 args_size
= current_function_outgoing_args_size
;
1041 pretend_size
= current_function_pretend_args_size
;
1042 extra_size
= FIRST_PARM_OFFSET (0);
1043 total_size
= extra_size
+ pretend_size
+ args_size
+ var_size
;
1044 reg_offset
= FIRST_PARM_OFFSET(0) + current_function_outgoing_args_size
;
1048 /* See if this is an interrupt handler. Call used registers must be saved
1050 fn_type
= arc_compute_function_type (current_function_decl
);
1051 interrupt_p
= ARC_INTERRUPT_P (fn_type
);
1053 /* Calculate space needed for registers.
1054 ??? We ignore the extension registers for now. */
1056 for (regno
= 0; regno
<= 31; regno
++)
1058 if (MUST_SAVE_REGISTER (regno
, interrupt_p
))
1060 reg_size
+= UNITS_PER_WORD
;
1061 gmask
|= 1 << regno
;
1065 total_size
+= reg_size
;
1067 /* If the only space to allocate is the fp/blink save area this is an
1068 empty frame. However, if we'll be making a function call we need to
1069 allocate a stack frame for our callee's fp/blink save area. */
1070 if (total_size
== extra_size
1071 && !MUST_SAVE_RETURN_ADDR
)
1072 total_size
= extra_size
= 0;
1074 total_size
= ARC_STACK_ALIGN (total_size
);
1076 /* Save computed information. */
1077 current_frame_info
.total_size
= total_size
;
1078 current_frame_info
.extra_size
= extra_size
;
1079 current_frame_info
.pretend_size
= pretend_size
;
1080 current_frame_info
.var_size
= var_size
;
1081 current_frame_info
.args_size
= args_size
;
1082 current_frame_info
.reg_size
= reg_size
;
1083 current_frame_info
.reg_offset
= reg_offset
;
1084 current_frame_info
.gmask
= gmask
;
1085 current_frame_info
.initialized
= reload_completed
;
1087 /* Ok, we're done. */
1091 /* Common code to save/restore registers. */
1094 arc_save_restore (file
, base_reg
, offset
, gmask
, op
)
1096 const char *base_reg
;
1097 unsigned int offset
;
1106 for (regno
= 0; regno
<= 31; regno
++)
1108 if ((gmask
& (1L << regno
)) != 0)
1110 fprintf (file
, "\t%s %s,[%s,%d]\n",
1111 op
, reg_names
[regno
], base_reg
, offset
);
1112 offset
+= UNITS_PER_WORD
;
1117 /* Target hook to assemble an integer object. The ARC version needs to
1118 emit a special directive for references to labels and function
1122 arc_assemble_integer (x
, size
, aligned_p
)
1127 if (size
== UNITS_PER_WORD
&& aligned_p
1128 && ((GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_FLAG (x
))
1129 || GET_CODE (x
) == LABEL_REF
))
1131 fputs ("\t.word\t%st(", asm_out_file
);
1132 output_addr_const (asm_out_file
, x
);
1133 fputs (")\n", asm_out_file
);
1136 return default_assemble_integer (x
, size
, aligned_p
);
1139 /* Set up the stack and frame pointer (if desired) for the function. */
1142 arc_output_function_prologue (file
, size
)
1146 const char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
1147 const char *fp_str
= reg_names
[FRAME_POINTER_REGNUM
];
1148 unsigned int gmask
= current_frame_info
.gmask
;
1149 enum arc_function_type fn_type
= arc_compute_function_type (current_function_decl
);
1151 /* If this is an interrupt handler, set up our stack frame.
1152 ??? Optimize later. */
1153 if (ARC_INTERRUPT_P (fn_type
))
1155 fprintf (file
, "\t%s interrupt handler\n",
1157 fprintf (file
, "\tsub %s,%s,16\n", sp_str
, sp_str
);
1160 /* This is only for the human reader. */
1161 fprintf (file
, "\t%s BEGIN PROLOGUE %s vars= %d, regs= %d, args= %d, extra= %d\n",
1162 ASM_COMMENT_START
, ASM_COMMENT_START
,
1163 current_frame_info
.var_size
,
1164 current_frame_info
.reg_size
/ 4,
1165 current_frame_info
.args_size
,
1166 current_frame_info
.extra_size
);
1168 size
= ARC_STACK_ALIGN (size
);
1169 size
= (! current_frame_info
.initialized
1170 ? arc_compute_frame_size (size
)
1171 : current_frame_info
.total_size
);
1173 /* These cases shouldn't happen. Catch them now. */
1174 if (size
== 0 && gmask
)
1177 /* Allocate space for register arguments if this is a variadic function. */
1178 if (current_frame_info
.pretend_size
!= 0)
1179 fprintf (file
, "\tsub %s,%s,%d\n",
1180 sp_str
, sp_str
, current_frame_info
.pretend_size
);
1182 /* The home-grown ABI says link register is saved first. */
1183 if (MUST_SAVE_RETURN_ADDR
)
1184 fprintf (file
, "\tst %s,[%s,%d]\n",
1185 reg_names
[RETURN_ADDR_REGNUM
], sp_str
, UNITS_PER_WORD
);
1187 /* Set up the previous frame pointer next (if we need to). */
1188 if (frame_pointer_needed
)
1190 fprintf (file
, "\tst %s,[%s]\n", fp_str
, sp_str
);
1191 fprintf (file
, "\tmov %s,%s\n", fp_str
, sp_str
);
1194 /* ??? We don't handle the case where the saved regs are more than 252
1195 bytes away from sp. This can be handled by decrementing sp once, saving
1196 the regs, and then decrementing it again. The epilogue doesn't have this
1197 problem as the `ld' insn takes reg+limm values (though it would be more
1198 efficient to avoid reg+limm). */
1200 /* Allocate the stack frame. */
1201 if (size
- current_frame_info
.pretend_size
> 0)
1202 fprintf (file
, "\tsub %s,%s,%d\n",
1203 sp_str
, sp_str
, size
- current_frame_info
.pretend_size
);
1205 /* Save any needed call-saved regs (and call-used if this is an
1206 interrupt handler). */
1207 arc_save_restore (file
, sp_str
, current_frame_info
.reg_offset
,
1208 /* The zeroing of these two bits is unnecessary,
1209 but leave this in for clarity. */
1210 gmask
& ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
1213 fprintf (file
, "\t%s END PROLOGUE\n", ASM_COMMENT_START
);
1216 /* Do any necessary cleanup after a function to restore stack, frame,
1220 arc_output_function_epilogue (file
, size
)
1224 rtx epilogue_delay
= current_function_epilogue_delay_list
;
1225 int noepilogue
= FALSE
;
1226 enum arc_function_type fn_type
= arc_compute_function_type (current_function_decl
);
1228 /* This is only for the human reader. */
1229 fprintf (file
, "\t%s EPILOGUE\n", ASM_COMMENT_START
);
1231 size
= ARC_STACK_ALIGN (size
);
1232 size
= (!current_frame_info
.initialized
1233 ? arc_compute_frame_size (size
)
1234 : current_frame_info
.total_size
);
1236 if (size
== 0 && epilogue_delay
== 0)
1238 rtx insn
= get_last_insn ();
1240 /* If the last insn was a BARRIER, we don't have to write any code
1241 because a jump (aka return) was put there. */
1242 if (GET_CODE (insn
) == NOTE
)
1243 insn
= prev_nonnote_insn (insn
);
1244 if (insn
&& GET_CODE (insn
) == BARRIER
)
1250 unsigned int pretend_size
= current_frame_info
.pretend_size
;
1251 unsigned int frame_size
= size
- pretend_size
;
1252 int restored
, fp_restored_p
;
1253 int can_trust_sp_p
= !current_function_calls_alloca
;
1254 const char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
1255 const char *fp_str
= reg_names
[FRAME_POINTER_REGNUM
];
1257 /* ??? There are lots of optimizations that can be done here.
1258 EG: Use fp to restore regs if it's closer.
1259 Maybe in time we'll do them all. For now, always restore regs from
1260 sp, but don't restore sp if we don't have to. */
1262 if (!can_trust_sp_p
)
1264 if (!frame_pointer_needed
)
1266 fprintf (file
,"\tsub %s,%s,%d\t\t%s sp not trusted here\n",
1267 sp_str
, fp_str
, frame_size
, ASM_COMMENT_START
);
1270 /* Restore any saved registers. */
1271 arc_save_restore (file
, sp_str
, current_frame_info
.reg_offset
,
1272 /* The zeroing of these two bits is unnecessary,
1273 but leave this in for clarity. */
1274 current_frame_info
.gmask
& ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
1277 if (MUST_SAVE_RETURN_ADDR
)
1278 fprintf (file
, "\tld %s,[%s,%d]\n",
1279 reg_names
[RETURN_ADDR_REGNUM
],
1280 frame_pointer_needed
? fp_str
: sp_str
,
1281 UNITS_PER_WORD
+ (frame_pointer_needed
? 0 : frame_size
));
1283 /* Keep track of how much of the stack pointer we've restored.
1284 It makes the following a lot more readable. */
1288 /* We try to emit the epilogue delay slot insn right after the load
1289 of the return address register so that it can execute with the
1290 stack intact. Secondly, loads are delayed. */
1291 /* ??? If stack intactness is important, always emit now. */
1292 if (MUST_SAVE_RETURN_ADDR
&& epilogue_delay
!= NULL_RTX
)
1294 final_scan_insn (XEXP (epilogue_delay
, 0), file
, 1, -2, 1);
1295 epilogue_delay
= NULL_RTX
;
1298 if (frame_pointer_needed
)
1300 /* Try to restore the frame pointer in the delay slot. We can't,
1301 however, if any of these is true. */
1302 if (epilogue_delay
!= NULL_RTX
1303 || !SMALL_INT (frame_size
)
1305 || ARC_INTERRUPT_P (fn_type
))
1307 /* Note that we restore fp and sp here! */
1308 fprintf (file
, "\tld.a %s,[%s,%d]\n", fp_str
, sp_str
, frame_size
);
1309 restored
+= frame_size
;
1313 else if (!SMALL_INT (size
/* frame_size + pretend_size */)
1314 || ARC_INTERRUPT_P (fn_type
))
1316 fprintf (file
, "\tadd %s,%s,%d\n", sp_str
, sp_str
, frame_size
);
1317 restored
+= frame_size
;
1320 /* These must be done before the return insn because the delay slot
1321 does the final stack restore. */
1322 if (ARC_INTERRUPT_P (fn_type
))
1326 final_scan_insn (XEXP (epilogue_delay
, 0), file
, 1, -2, 1);
1330 /* Emit the return instruction. */
1332 static const int regs
[4] = {
1333 0, RETURN_ADDR_REGNUM
, ILINK1_REGNUM
, ILINK2_REGNUM
1335 fprintf (file
, "\tj.d %s\n", reg_names
[regs
[fn_type
]]);
1338 /* If the only register saved is the return address, we need a
1339 nop, unless we have an instruction to put into it. Otherwise
1340 we don't since reloading multiple registers doesn't reference
1341 the register being loaded. */
1343 if (ARC_INTERRUPT_P (fn_type
))
1344 fprintf (file
, "\tadd %s,%s,16\n", sp_str
, sp_str
);
1345 else if (epilogue_delay
!= NULL_RTX
)
1347 if (frame_pointer_needed
&& !fp_restored_p
)
1349 if (restored
< size
)
1351 final_scan_insn (XEXP (epilogue_delay
, 0), file
, 1, -2, 1);
1353 else if (frame_pointer_needed
&& !fp_restored_p
)
1355 if (!SMALL_INT (frame_size
))
1357 /* Note that we restore fp and sp here! */
1358 fprintf (file
, "\tld.a %s,[%s,%d]\n", fp_str
, sp_str
, frame_size
);
1360 else if (restored
< size
)
1362 if (!SMALL_INT (size
- restored
))
1364 fprintf (file
, "\tadd %s,%s,%d\n",
1365 sp_str
, sp_str
, size
- restored
);
1368 fprintf (file
, "\tnop\n");
1371 /* Reset state info for each function. */
1372 current_frame_info
= zero_frame_info
;
1373 arc_compute_function_type (NULL_TREE
);
1376 /* Define the number of delay slots needed for the function epilogue.
1378 Interrupt handlers can't have any epilogue delay slots (it's always needed
1379 for something else, I think). For normal functions, we have to worry about
1380 using call-saved regs as they'll be restored before the delay slot insn.
1381 Functions with non-empty frames already have enough choices for the epilogue
1382 delay slot so for now we only consider functions with empty frames. */
1385 arc_delay_slots_for_epilogue ()
1387 if (arc_compute_function_type (current_function_decl
) != ARC_FUNCTION_NORMAL
)
1389 if (!current_frame_info
.initialized
)
1390 (void) arc_compute_frame_size (get_frame_size ());
1391 if (current_frame_info
.total_size
== 0)
1396 /* Return true if TRIAL is a valid insn for the epilogue delay slot.
1397 Any single length instruction which doesn't reference the stack or frame
1398 pointer or any call-saved register is OK. SLOT will always be 0. */
1401 arc_eligible_for_epilogue_delay (trial
, slot
)
1408 if (get_attr_length (trial
) == 1
1409 /* If registers where saved, presumably there's more than enough
1410 possibilities for the delay slot. The alternative is something
1411 more complicated (of course, if we expanded the epilogue as rtl
1412 this problem would go away). */
1413 /* ??? Note that this will always be true since only functions with
1414 empty frames have epilogue delay slots. See
1415 arc_delay_slots_for_epilogue. */
1416 && current_frame_info
.gmask
== 0
1417 && ! reg_mentioned_p (stack_pointer_rtx
, PATTERN (trial
))
1418 && ! reg_mentioned_p (frame_pointer_rtx
, PATTERN (trial
)))
1425 /* Emit special PIC prologues and epilogues. */
1433 /* Return true if OP is a shift operator. */
1436 shift_operator (op
, mode
)
1438 enum machine_mode mode ATTRIBUTE_UNUSED
;
1440 switch (GET_CODE (op
))
1451 /* Output the assembler code for doing a shift.
1452 We go to a bit of trouble to generate efficient code as the ARC only has
1453 single bit shifts. This is taken from the h8300 port. We only have one
1454 mode of shifting and can't access individual bytes like the h8300 can, so
1455 this is greatly simplified (at the expense of not generating hyper-
1458 This function is not used if the variable shift insns are present. */
1460 /* ??? We assume the output operand is the same as operand 1.
1461 This can be optimized (deleted) in the case of 1 bit shifts. */
1462 /* ??? We use the loop register here. We don't use it elsewhere (yet) and
1463 using it here will give us a chance to play with it. */
1466 output_shift (operands
)
1469 rtx shift
= operands
[3];
1470 enum machine_mode mode
= GET_MODE (shift
);
1471 enum rtx_code code
= GET_CODE (shift
);
1472 const char *shift_one
;
1479 case ASHIFT
: shift_one
= "asl %0,%0"; break;
1480 case ASHIFTRT
: shift_one
= "asr %0,%0"; break;
1481 case LSHIFTRT
: shift_one
= "lsr %0,%0"; break;
1485 if (GET_CODE (operands
[2]) != CONST_INT
)
1488 output_asm_insn ("mov lp_count,%2", operands
);
1490 output_asm_insn ("mov %4,%2", operands
);
1495 int n
= INTVAL (operands
[2]);
1497 /* If the count is negative, make it 0. */
1500 /* If the count is too big, truncate it.
1501 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
1502 do the intuitive thing. */
1503 else if (n
> GET_MODE_BITSIZE (mode
))
1504 n
= GET_MODE_BITSIZE (mode
);
1506 /* First see if we can do them inline. */
1510 output_asm_insn (shift_one
, operands
);
1512 /* See if we can use a rotate/and. */
1513 else if (n
== BITS_PER_WORD
- 1)
1518 output_asm_insn ("and %0,%0,1\n\tror %0,%0", operands
);
1521 /* The ARC doesn't have a rol insn. Use something else. */
1522 output_asm_insn ("asl.f 0,%0\n\tsbc %0,0,0", operands
);
1525 /* The ARC doesn't have a rol insn. Use something else. */
1526 output_asm_insn ("asl.f 0,%0\n\tadc %0,0,0", operands
);
1538 output_asm_insn ("mov lp_count,%c2", operands
);
1540 output_asm_insn ("mov %4,%c2", operands
);
1545 sprintf (buf
, "lr %%4,[status]\n\tadd %%4,%%4,6\t%s single insn loop start",
1548 sprintf (buf
, "mov %%4,%%%%st(1f)\t%s (single insn loop start) >> 2",
1550 output_asm_insn (buf
, operands
);
1551 output_asm_insn ("sr %4,[lp_start]", operands
);
1552 output_asm_insn ("add %4,%4,1", operands
);
1553 output_asm_insn ("sr %4,[lp_end]", operands
);
1554 output_asm_insn ("nop\n\tnop", operands
);
1556 asm_fprintf (asm_out_file
, "\t%s single insn loop\n",
1559 asm_fprintf (asm_out_file
, "1:\t%s single insn loop\n",
1561 output_asm_insn (shift_one
, operands
);
1565 asm_fprintf (asm_out_file
, "1:\t%s begin shift loop\n",
1567 output_asm_insn ("sub.f %4,%4,1", operands
);
1568 output_asm_insn ("nop", operands
);
1569 output_asm_insn ("bn.nd 2f", operands
);
1570 output_asm_insn (shift_one
, operands
);
1571 output_asm_insn ("b.nd 1b", operands
);
1572 asm_fprintf (asm_out_file
, "2:\t%s end shift loop\n",
1581 /* Nested function support. */
1583 /* Emit RTL insns to initialize the variable parts of a trampoline.
1584 FNADDR is an RTX for the address of the function's pure code.
1585 CXT is an RTX for the static chain value for the function. */
1588 arc_initialize_trampoline (tramp
, fnaddr
, cxt
)
1589 rtx tramp ATTRIBUTE_UNUSED
, fnaddr ATTRIBUTE_UNUSED
, cxt ATTRIBUTE_UNUSED
;
1593 /* Set the cpu type and print out other fancy things,
1594 at the top of the file. */
1597 arc_asm_file_start (file
)
1600 fprintf (file
, "\t.cpu %s\n", arc_cpu_string
);
1603 /* Print operand X (an rtx) in assembler syntax to file FILE.
1604 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1605 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1608 arc_print_operand (file
, x
, code
)
1616 /* Conditional branches. For now these are equivalent. */
1618 /* Unconditional branches. Output the appropriate delay slot suffix. */
1619 if (!final_sequence
|| XVECLEN (final_sequence
, 0) == 1)
1621 /* There's nothing in the delay slot. */
1622 fputs (".nd", file
);
1626 rtx jump
= XVECEXP (final_sequence
, 0, 0);
1627 rtx delay
= XVECEXP (final_sequence
, 0, 1);
1628 if (INSN_ANNULLED_BRANCH_P (jump
))
1629 fputs (INSN_FROM_TARGET_P (delay
) ? ".jd" : ".nd", file
);
1634 case '?' : /* with leading "." */
1635 case '!' : /* without leading "." */
1636 /* This insn can be conditionally executed. See if the ccfsm machinery
1637 says it should be conditionalized. */
1638 if (arc_ccfsm_state
== 3 || arc_ccfsm_state
== 4)
1640 /* Is this insn in a delay slot? */
1641 if (final_sequence
&& XVECLEN (final_sequence
, 0) == 2)
1643 rtx insn
= XVECEXP (final_sequence
, 0, 1);
1645 /* If the insn is annulled and is from the target path, we need
1646 to inverse the condition test. */
1647 if (INSN_ANNULLED_BRANCH_P (insn
))
1649 if (INSN_FROM_TARGET_P (insn
))
1650 fprintf (file
, "%s%s",
1651 code
== '?' ? "." : "",
1652 arc_condition_codes
[ARC_INVERSE_CONDITION_CODE (arc_ccfsm_current_cc
)]);
1654 fprintf (file
, "%s%s",
1655 code
== '?' ? "." : "",
1656 arc_condition_codes
[arc_ccfsm_current_cc
]);
1660 /* This insn is executed for either path, so don't
1661 conditionalize it at all. */
1662 ; /* nothing to do */
1667 /* This insn isn't in a delay slot. */
1668 fprintf (file
, "%s%s",
1669 code
== '?' ? "." : "",
1670 arc_condition_codes
[arc_ccfsm_current_cc
]);
1675 /* Output a nop if we're between a set of the condition codes,
1676 and a conditional branch. */
1677 if (last_insn_set_cc_p
)
1678 fputs ("nop\n\t", file
);
1681 fputs (arc_condition_codes
[get_arc_condition_code (x
)], file
);
1684 fputs (arc_condition_codes
[ARC_INVERSE_CONDITION_CODE
1685 (get_arc_condition_code (x
))],
1689 /* Write second word of DImode or DFmode reference,
1690 register or memory. */
1691 if (GET_CODE (x
) == REG
)
1692 fputs (reg_names
[REGNO (x
)+1], file
);
1693 else if (GET_CODE (x
) == MEM
)
1696 /* Handle possible auto-increment. Since it is pre-increment and
1697 we have already done it, we can just use an offset of four. */
1698 /* ??? This is taken from rs6000.c I think. I don't think it is
1699 currently necessary, but keep it around. */
1700 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
1701 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
1702 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 4));
1704 output_address (plus_constant (XEXP (x
, 0), 4));
1708 output_operand_lossage ("invalid operand to %%R code");
1711 if ((GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_FLAG (x
))
1712 || GET_CODE (x
) == LABEL_REF
)
1714 fprintf (file
, "%%st(");
1715 output_addr_const (file
, x
);
1716 fprintf (file
, ")");
1722 if (GET_CODE (x
) == REG
)
1724 /* L = least significant word, H = most significant word */
1725 if ((TARGET_BIG_ENDIAN
!= 0) ^ (code
== 'L'))
1726 fputs (reg_names
[REGNO (x
)], file
);
1728 fputs (reg_names
[REGNO (x
)+1], file
);
1730 else if (GET_CODE (x
) == CONST_INT
1731 || GET_CODE (x
) == CONST_DOUBLE
)
1735 split_double (x
, &first
, &second
);
1736 fprintf (file
, "0x%08lx",
1737 (long)(code
== 'L' ? INTVAL (first
) : INTVAL (second
)));
1740 output_operand_lossage ("invalid operand to %%H/%%L code");
1747 if (GET_CODE (x
) != CONST_DOUBLE
1748 || GET_MODE_CLASS (GET_MODE (x
)) != MODE_FLOAT
)
1750 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1751 REAL_VALUE_TO_DECIMAL (d
, "%.20e", str
);
1752 fprintf (file
, "%s", str
);
1756 /* Output a load/store with update indicator if appropriate. */
1757 if (GET_CODE (x
) == MEM
)
1759 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
1760 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
1764 output_operand_lossage ("invalid operand to %%U code");
1767 /* Output cache bypass indicator for a load/store insn. Volatile memory
1768 refs are defined to use the cache bypass mechanism. */
1769 if (GET_CODE (x
) == MEM
)
1771 if (MEM_VOLATILE_P (x
))
1772 fputs (".di", file
);
1775 output_operand_lossage ("invalid operand to %%V code");
1778 /* Do nothing special. */
1782 output_operand_lossage ("invalid operand output code");
1785 switch (GET_CODE (x
))
1788 fputs (reg_names
[REGNO (x
)], file
);
1792 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
1793 output_address (plus_constant (XEXP (XEXP (x
, 0), 0),
1794 GET_MODE_SIZE (GET_MODE (x
))));
1795 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
1796 output_address (plus_constant (XEXP (XEXP (x
, 0), 0),
1797 - GET_MODE_SIZE (GET_MODE (x
))));
1799 output_address (XEXP (x
, 0));
1803 /* We handle SFmode constants here as output_addr_const doesn't. */
1804 if (GET_MODE (x
) == SFmode
)
1809 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1810 REAL_VALUE_TO_TARGET_SINGLE (d
, l
);
1811 fprintf (file
, "0x%08lx", l
);
1814 /* Fall through. Let output_addr_const deal with it. */
1816 output_addr_const (file
, x
);
1821 /* Print a memory address as an operand to reference that memory location. */
1824 arc_print_operand_address (file
, addr
)
1828 register rtx base
, index
= 0;
1831 switch (GET_CODE (addr
))
1834 fputs (reg_names
[REGNO (addr
)], file
);
1837 if (/*???*/ 0 && SYMBOL_REF_FLAG (addr
))
1839 fprintf (file
, "%%st(");
1840 output_addr_const (file
, addr
);
1841 fprintf (file
, ")");
1844 output_addr_const (file
, addr
);
1847 if (GET_CODE (XEXP (addr
, 0)) == CONST_INT
)
1848 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
1849 else if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
1850 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
1852 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
1853 if (GET_CODE (base
) != REG
)
1855 fputs (reg_names
[REGNO (base
)], file
);
1859 fprintf (file
, ",%d", offset
);
1861 else if (GET_CODE (index
) == REG
)
1862 fprintf (file
, ",%s", reg_names
[REGNO (index
)]);
1863 else if (GET_CODE (index
) == SYMBOL_REF
)
1864 fputc (',', file
), output_addr_const (file
, index
);
1870 /* We shouldn't get here as we've lost the mode of the memory object
1871 (which says how much to inc/dec by. */
1875 output_addr_const (file
, addr
);
1880 /* Update compare/branch separation marker. */
1883 record_cc_ref (insn
)
1886 last_insn_set_cc_p
= current_insn_set_cc_p
;
1888 switch (get_attr_cond (insn
))
1893 if (get_attr_length (insn
) == 1)
1894 current_insn_set_cc_p
= 1;
1896 current_insn_set_cc_p
= 0;
1899 current_insn_set_cc_p
= 0;
1904 /* Conditional execution support.
1906 This is based on the ARM port but for now is much simpler.
1908 A finite state machine takes care of noticing whether or not instructions
1909 can be conditionally executed, and thus decrease execution time and code
1910 size by deleting branch instructions. The fsm is controlled by
1911 final_prescan_insn, and controls the actions of PRINT_OPERAND. The patterns
1912 in the .md file for the branch insns also have a hand in this. */
1914 /* The state of the fsm controlling condition codes are:
1915 0: normal, do nothing special
1916 1: don't output this insn
1917 2: don't output this insn
1918 3: make insns conditional
1919 4: make insns conditional
1921 State transitions (state->state by whom, under what condition):
1922 0 -> 1 final_prescan_insn, if insn is conditional branch
1923 0 -> 2 final_prescan_insn, if the `target' is an unconditional branch
1924 1 -> 3 branch patterns, after having not output the conditional branch
1925 2 -> 4 branch patterns, after having not output the conditional branch
1926 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL, if the `target' label is reached
1927 (the target label has CODE_LABEL_NUMBER equal to
1928 arc_ccfsm_target_label).
1929 4 -> 0 final_prescan_insn, if `target' unconditional branch is reached
1931 If the jump clobbers the conditions then we use states 2 and 4.
1933 A similar thing can be done with conditional return insns.
1935 We also handle separating branches from sets of the condition code.
1936 This is done here because knowledge of the ccfsm state is required,
1937 we may not be outputting the branch. */
1940 arc_final_prescan_insn (insn
, opvec
, noperands
)
1942 rtx
*opvec ATTRIBUTE_UNUSED
;
1943 int noperands ATTRIBUTE_UNUSED
;
1945 /* BODY will hold the body of INSN. */
1946 register rtx body
= PATTERN (insn
);
1948 /* This will be 1 if trying to repeat the trick (ie: do the `else' part of
1949 an if/then/else), and things need to be reversed. */
1952 /* If we start with a return insn, we only succeed if we find another one. */
1953 int seeking_return
= 0;
1955 /* START_INSN will hold the insn from where we start looking. This is the
1956 first insn after the following code_label if REVERSE is true. */
1957 rtx start_insn
= insn
;
1959 /* Update compare/branch separation marker. */
1960 record_cc_ref (insn
);
1962 /* Allow -mdebug-ccfsm to turn this off so we can see how well it does.
1963 We can't do this in macro FINAL_PRESCAN_INSN because its called from
1964 final_scan_insn which has `optimize' as a local. */
1965 if (optimize
< 2 || TARGET_NO_COND_EXEC
)
1968 /* If in state 4, check if the target branch is reached, in order to
1969 change back to state 0. */
1970 if (arc_ccfsm_state
== 4)
1972 if (insn
== arc_ccfsm_target_insn
)
1974 arc_ccfsm_target_insn
= NULL
;
1975 arc_ccfsm_state
= 0;
1980 /* If in state 3, it is possible to repeat the trick, if this insn is an
1981 unconditional branch to a label, and immediately following this branch
1982 is the previous target label which is only used once, and the label this
1983 branch jumps to is not too far off. Or in other words "we've done the
1984 `then' part, see if we can do the `else' part." */
1985 if (arc_ccfsm_state
== 3)
1987 if (simplejump_p (insn
))
1989 start_insn
= next_nonnote_insn (start_insn
);
1990 if (GET_CODE (start_insn
) == BARRIER
)
1992 /* ??? Isn't this always a barrier? */
1993 start_insn
= next_nonnote_insn (start_insn
);
1995 if (GET_CODE (start_insn
) == CODE_LABEL
1996 && CODE_LABEL_NUMBER (start_insn
) == arc_ccfsm_target_label
1997 && LABEL_NUSES (start_insn
) == 1)
2002 else if (GET_CODE (body
) == RETURN
)
2004 start_insn
= next_nonnote_insn (start_insn
);
2005 if (GET_CODE (start_insn
) == BARRIER
)
2006 start_insn
= next_nonnote_insn (start_insn
);
2007 if (GET_CODE (start_insn
) == CODE_LABEL
2008 && CODE_LABEL_NUMBER (start_insn
) == arc_ccfsm_target_label
2009 && LABEL_NUSES (start_insn
) == 1)
2021 if (GET_CODE (insn
) != JUMP_INSN
)
2024 /* This jump might be paralleled with a clobber of the condition codes,
2025 the jump should always come first. */
2026 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
2027 body
= XVECEXP (body
, 0, 0);
2030 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
2031 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
2033 int insns_skipped
= 0, fail
= FALSE
, succeed
= FALSE
;
2034 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
2035 int then_not_else
= TRUE
;
2036 /* Nonzero if next insn must be the target label. */
2037 int next_must_be_target_label_p
;
2038 rtx this_insn
= start_insn
, label
= 0;
2040 /* Register the insn jumped to. */
2043 if (!seeking_return
)
2044 label
= XEXP (SET_SRC (body
), 0);
2046 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
2047 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
2048 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
2050 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
2051 then_not_else
= FALSE
;
2053 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
2055 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
2058 then_not_else
= FALSE
;
2063 /* See how many insns this branch skips, and what kind of insns. If all
2064 insns are okay, and the label or unconditional branch to the same
2065 label is not too far away, succeed. */
2066 for (insns_skipped
= 0, next_must_be_target_label_p
= FALSE
;
2067 !fail
&& !succeed
&& insns_skipped
< MAX_INSNS_SKIPPED
;
2072 this_insn
= next_nonnote_insn (this_insn
);
2076 if (next_must_be_target_label_p
)
2078 if (GET_CODE (this_insn
) == BARRIER
)
2080 if (GET_CODE (this_insn
) == CODE_LABEL
2081 && this_insn
== label
)
2083 arc_ccfsm_state
= 1;
2091 scanbody
= PATTERN (this_insn
);
2093 switch (GET_CODE (this_insn
))
2096 /* Succeed if it is the target label, otherwise fail since
2097 control falls in from somewhere else. */
2098 if (this_insn
== label
)
2100 arc_ccfsm_state
= 1;
2108 /* Succeed if the following insn is the target label.
2110 If return insns are used then the last insn in a function
2111 will be a barrier. */
2112 next_must_be_target_label_p
= TRUE
;
2116 /* Can handle a call insn if there are no insns after it.
2117 IE: The next "insn" is the target label. We don't have to
2118 worry about delay slots as such insns are SEQUENCE's inside
2119 INSN's. ??? It is possible to handle such insns though. */
2120 if (get_attr_cond (this_insn
) == COND_CANUSE
)
2121 next_must_be_target_label_p
= TRUE
;
2127 /* If this is an unconditional branch to the same label, succeed.
2128 If it is to another label, do nothing. If it is conditional,
2130 /* ??? Probably, the test for the SET and the PC are unnecessary. */
2132 if (GET_CODE (scanbody
) == SET
2133 && GET_CODE (SET_DEST (scanbody
)) == PC
)
2135 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
2136 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
2138 arc_ccfsm_state
= 2;
2141 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
2144 else if (GET_CODE (scanbody
) == RETURN
2147 arc_ccfsm_state
= 2;
2150 else if (GET_CODE (scanbody
) == PARALLEL
)
2152 if (get_attr_cond (this_insn
) != COND_CANUSE
)
2158 /* We can only do this with insns that can use the condition
2159 codes (and don't set them). */
2160 if (GET_CODE (scanbody
) == SET
2161 || GET_CODE (scanbody
) == PARALLEL
)
2163 if (get_attr_cond (this_insn
) != COND_CANUSE
)
2166 /* We can't handle other insns like sequences. */
2178 if ((!seeking_return
) && (arc_ccfsm_state
== 1 || reverse
))
2179 arc_ccfsm_target_label
= CODE_LABEL_NUMBER (label
);
2180 else if (seeking_return
|| arc_ccfsm_state
== 2)
2182 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
2184 this_insn
= next_nonnote_insn (this_insn
);
2185 if (this_insn
&& (GET_CODE (this_insn
) == BARRIER
2186 || GET_CODE (this_insn
) == CODE_LABEL
))
2191 /* Oh dear! we ran off the end, give up. */
2192 extract_insn_cached (insn
);
2193 arc_ccfsm_state
= 0;
2194 arc_ccfsm_target_insn
= NULL
;
2197 arc_ccfsm_target_insn
= this_insn
;
2202 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
2205 arc_ccfsm_current_cc
= get_arc_condition_code (XEXP (SET_SRC (body
),
2208 if (reverse
|| then_not_else
)
2209 arc_ccfsm_current_cc
= ARC_INVERSE_CONDITION_CODE (arc_ccfsm_current_cc
);
2212 /* Restore recog_data. Getting the attributes of other insns can
2213 destroy this array, but final.c assumes that it remains intact
2214 across this call. */
2215 extract_insn_cached (insn
);
2219 /* Record that we are currently outputting label NUM with prefix PREFIX.
2220 It it's the label we're looking for, reset the ccfsm machinery.
2222 Called from ASM_OUTPUT_INTERNAL_LABEL. */
2225 arc_ccfsm_at_label (prefix
, num
)
2229 if (arc_ccfsm_state
== 3 && arc_ccfsm_target_label
== num
2230 && !strcmp (prefix
, "L"))
2232 arc_ccfsm_state
= 0;
2233 arc_ccfsm_target_insn
= NULL_RTX
;
2237 /* See if the current insn, which is a conditional branch, is to be
2241 arc_ccfsm_branch_deleted_p ()
2243 if (arc_ccfsm_state
== 1 || arc_ccfsm_state
== 2)
2248 /* Record a branch isn't output because subsequent insns can be
2252 arc_ccfsm_record_branch_deleted ()
2254 /* Indicate we're conditionalizing insns now. */
2255 arc_ccfsm_state
+= 2;
2257 /* If the next insn is a subroutine call, we still need a nop between the
2258 cc setter and user. We need to undo the effect of calling record_cc_ref
2259 for the just deleted branch. */
2260 current_insn_set_cc_p
= last_insn_set_cc_p
;
2264 arc_va_start (valist
, nextarg
)
2268 /* See arc_setup_incoming_varargs for reasons for this oddity. */
2269 if (current_function_args_info
< 8
2270 && (current_function_args_info
& 1))
2271 nextarg
= plus_constant (nextarg
, UNITS_PER_WORD
);
2273 std_expand_builtin_va_start (valist
, nextarg
);
2277 arc_va_arg (valist
, type
)
2282 tree type_ptr
= build_pointer_type (type
);
2284 /* All aggregates are passed by reference. All scalar types larger
2285 than 8 bytes are passed by reference. */
2287 if (AGGREGATE_TYPE_P (type
) || int_size_in_bytes (type
) > 8)
2289 tree type_ptr_ptr
= build_pointer_type (type_ptr
);
2291 addr
= build (INDIRECT_REF
, type_ptr
,
2292 build (NOP_EXPR
, type_ptr_ptr
, valist
));
2294 incr
= build (PLUS_EXPR
, TREE_TYPE (valist
),
2295 valist
, build_int_2 (UNITS_PER_WORD
, 0));
2299 HOST_WIDE_INT align
, rounded_size
;
2301 /* Compute the rounded size of the type. */
2302 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
2303 rounded_size
= (((TREE_INT_CST_LOW (TYPE_SIZE (type
)) / BITS_PER_UNIT
2304 + align
- 1) / align
) * align
);
2306 /* Align 8 byte operands. */
2308 if (TYPE_ALIGN (type
) > BITS_PER_WORD
)
2310 /* AP = (TYPE *)(((int)AP + 7) & -8) */
2312 addr
= build (NOP_EXPR
, integer_type_node
, valist
);
2313 addr
= fold (build (PLUS_EXPR
, integer_type_node
, addr
,
2314 build_int_2 (7, 0)));
2315 addr
= fold (build (BIT_AND_EXPR
, integer_type_node
, addr
,
2316 build_int_2 (-8, 0)));
2317 addr
= fold (build (NOP_EXPR
, TREE_TYPE (valist
), addr
));
2320 /* The increment is always rounded_size past the aligned pointer. */
2321 incr
= fold (build (PLUS_EXPR
, TREE_TYPE (addr
), addr
,
2322 build_int_2 (rounded_size
, 0)));
2324 /* Adjust the pointer in big-endian mode. */
2325 if (BYTES_BIG_ENDIAN
)
2328 adj
= TREE_INT_CST_LOW (TYPE_SIZE (type
)) / BITS_PER_UNIT
;
2329 if (rounded_size
> align
)
2332 addr
= fold (build (PLUS_EXPR
, TREE_TYPE (addr
), addr
,
2333 build_int_2 (rounded_size
- adj
, 0)));
2337 /* Evaluate the data address. */
2338 addr_rtx
= expand_expr (addr
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
2339 addr_rtx
= copy_to_reg (addr_rtx
);
2341 /* Compute new value for AP. */
2342 incr
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, incr
);
2343 TREE_SIDE_EFFECTS (incr
) = 1;
2344 expand_expr (incr
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2349 /* On the ARC, function addresses are not the same as normal addresses.
2350 Branch to absolute address insns take an address that is right-shifted
2351 by 2. We encode the fact that we have a function here, and then emit a
2352 special assembler op when outputting the address. */
2355 arc_encode_section_info (decl
, first
)
2357 int first ATTRIBUTE_UNUSED
;
2359 if (TREE_CODE (decl
) == FUNCTION_DECL
)
2360 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl
), 0)) = 1;