projects / gcc.git / blob
? search:


d98cce112571d5554ac13a311305ac249cfdcc5b
[gcc.git] / gcc / config / arc / arc.h
1 /* Definitions of target machine for GNU compiler, Synopsys DesignWare ARC cpu.
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3
4 Sources derived from work done by Sankhya Technologies (www.sankhya.com) on
5 behalf of Synopsys Inc.
6
7 Position Independent Code support added,Code cleaned up,
8 Comments and Support For ARC700 instructions added by
9 Saurabh Verma (saurabh.verma@codito.com)
10 Ramana Radhakrishnan(ramana.radhakrishnan@codito.com)
11
12 This file is part of GCC.
13
14 GCC is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 3, or (at your option)
17 any later version.
18
19 GCC is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with GCC; see the file COPYING3. If not see
26 <http://www.gnu.org/licenses/>. */
27
28 #ifndef GCC_ARC_H
29 #define GCC_ARC_H
30
31 /* Things to do:
32
33 - incscc, decscc?
34
35 */
36
37 #define SYMBOL_FLAG_SHORT_CALL (SYMBOL_FLAG_MACH_DEP << 0)
38 #define SYMBOL_FLAG_MEDIUM_CALL (SYMBOL_FLAG_MACH_DEP << 1)
39 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 2)
40
41 /* Check if this symbol has a long_call attribute in its declaration */
42 #define SYMBOL_REF_LONG_CALL_P(X) \
43 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
44
45 /* Check if this symbol has a medium_call attribute in its declaration */
46 #define SYMBOL_REF_MEDIUM_CALL_P(X) \
47 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_MEDIUM_CALL) != 0)
48
49 /* Check if this symbol has a short_call attribute in its declaration */
50 #define SYMBOL_REF_SHORT_CALL_P(X) \
51 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SHORT_CALL) != 0)
52
53 #undef ASM_SPEC
54 #undef LINK_SPEC
55 #undef STARTFILE_SPEC
56 #undef ENDFILE_SPEC
57 #undef SIZE_TYPE
58 #undef PTRDIFF_TYPE
59 #undef WCHAR_TYPE
60 #undef WCHAR_TYPE_SIZE
61 #undef ASM_APP_ON
62 #undef ASM_APP_OFF
63 #undef CC1_SPEC
64
65 /* Names to predefine in the preprocessor for this target machine. */
66 #define TARGET_CPU_CPP_BUILTINS() \
67 do { \
68 builtin_define ("__arc__"); \
69 if (TARGET_A5) \
70 builtin_define ("__A5__"); \
71 else if (TARGET_ARC600) \
72 { \
73 builtin_define ("__A6__"); \
74 builtin_define ("__ARC600__"); \
75 } \
76 else if (TARGET_ARC601) \
77 { \
78 builtin_define ("__ARC601__"); \
79 } \
80 else if (TARGET_ARC700) \
81 { \
82 builtin_define ("__A7__"); \
83 builtin_define ("__ARC700__"); \
84 } \
85 if (TARGET_NORM) \
86 { \
87 builtin_define ("__ARC_NORM__");\
88 builtin_define ("__Xnorm"); \
89 } \
90 if (TARGET_MUL64_SET) \
91 builtin_define ("__ARC_MUL64__");\
92 if (TARGET_MULMAC_32BY16_SET) \
93 builtin_define ("__ARC_MUL32BY16__");\
94 if (TARGET_SIMD_SET) \
95 builtin_define ("__ARC_SIMD__"); \
96 if (TARGET_BARREL_SHIFTER) \
97 builtin_define ("__Xbarrel_shifter");\
98 builtin_assert ("cpu=arc"); \
99 builtin_assert ("machine=arc"); \
100 builtin_define (TARGET_BIG_ENDIAN \
101 ? "__BIG_ENDIAN__" : "__LITTLE_ENDIAN__"); \
102 if (TARGET_BIG_ENDIAN) \
103 builtin_define ("__big_endian__"); \
104 } while(0)
105
106 #if DEFAULT_LIBC == LIBC_UCLIBC
107
108 #define TARGET_OS_CPP_BUILTINS() \
109 do \
110 { \
111 GNU_USER_TARGET_OS_CPP_BUILTINS (); \
112 } \
113 while (0)
114 #endif
115
116 /* Match the macros used in the assembler. */
117 #define CPP_SPEC "\
118 %{msimd:-D__Xsimd} %{mno-mpy:-D__Xno_mpy} %{mswap:-D__Xswap} \
119 %{mmin-max:-D__Xmin_max} %{mEA:-D__Xea} \
120 %{mspfp*:-D__Xspfp} %{mdpfp*:-D__Xdpfp} \
121 %{mmac-d16:-D__Xxmac_d16} %{mmac-24:-D__Xxmac_24} \
122 %{mdsp-packa:-D__Xdsp_packa} %{mcrc:-D__Xcrc} %{mdvbf:-D__Xdvbf} \
123 %{mtelephony:-D__Xtelephony} %{mxy:-D__Xxy} %{mmul64: -D__Xmult32} \
124 %{mlock:-D__Xlock} %{mswape:-D__Xswape} %{mrtsc:-D__Xrtsc} \
125 "
126
127 #define CC1_SPEC "\
128 %{EB:%{EL:%emay not use both -EB and -EL}} \
129 %{EB:-mbig-endian} %{EL:-mlittle-endian} \
130 "
131
132 #define ASM_DEFAULT "-mARC700 -mEA"
133
134 #define ASM_SPEC "\
135 %{mbig-endian|EB:-EB} %{EL} \
136 %{mcpu=A5|mcpu=a5|mA5:-mA5} \
137 %{mcpu=ARC600:-mARC600} \
138 %{mcpu=ARC601:-mARC601} \
139 %{mcpu=ARC700:-mARC700} \
140 %{mcpu=ARC700:-mEA} \
141 %{!mcpu=*:" ASM_DEFAULT "} \
142 %{mbarrel-shifter} %{mno-mpy} %{mmul64} %{mmul32x16:-mdsp-packa} %{mnorm} \
143 %{mswap} %{mEA} %{mmin-max} %{mspfp*} %{mdpfp*} \
144 %{msimd} \
145 %{mmac-d16} %{mmac-24} %{mdsp-packa} %{mcrc} %{mdvbf} %{mtelephony} %{mxy} \
146 %{mcpu=ARC700|!mcpu=*:%{mlock}} \
147 %{mcpu=ARC700|!mcpu=*:%{mswape}} \
148 %{mcpu=ARC700|!mcpu=*:%{mrtsc}} \
149 "
150
151 #if DEFAULT_LIBC == LIBC_UCLIBC
152 /* Note that the default is to link against dynamic libraries, if they are
153 available. Override with -static. */
154 #define LINK_SPEC "%{h*} \
155 %{static:-Bstatic} \
156 %{symbolic:-Bsymbolic} \
157 %{rdynamic:-export-dynamic}\
158 -dynamic-linker /lib/ld-uClibc.so.0 \
159 -X %{mbig-endian:-EB} \
160 %{EB} %{EL} \
161 %{marclinux*} \
162 %{!marclinux*: %{pg|p|profile:-marclinux_prof;: -marclinux}} \
163 %{!z:-z max-page-size=0x2000 -z common-page-size=0x2000} \
164 %{shared:-shared}"
165 /* Like the standard LINK_COMMAND_SPEC, but add %G when building
166 a shared library with -nostdlib, so that the hidden functions of libgcc
167 will be incorporated.
168 N.B., we don't want a plain -lgcc, as this would lead to re-exporting
169 non-hidden functions, so we have to consider libgcc_s.so.* first, which in
170 turn should be wrapped with --as-needed. */
171 #define LINK_COMMAND_SPEC "\
172 %{!fsyntax-only:%{!c:%{!M:%{!MM:%{!E:%{!S:\
173 %(linker) %l " LINK_PIE_SPEC "%X %{o*} %{A} %{d} %{e*} %{m} %{N} %{n} %{r}\
174 %{s} %{t} %{u*} %{x} %{z} %{Z} %{!A:%{!nostdlib:%{!nostartfiles:%S}}}\
175 %{static:} %{L*} %(mfwrap) %(link_libgcc) %o\
176 %{fopenacc|fopenmp|ftree-parallelize-loops=*:%:include(libgomp.spec)%(link_gomp)}\
177 %(mflib)\
178 %{fprofile-arcs|fprofile-generate|coverage:-lgcov}\
179 %{!nostdlib:%{!nodefaultlibs:%(link_ssp) %(link_gcc_c_sequence)}}\
180 %{!A:%{!nostdlib:%{!nostartfiles:%E}}} %{T*} }}}}}}"
181
182 #else
183 #define LINK_SPEC "%{mbig-endian:-EB} %{EB} %{EL}\
184 %{pg|p:-marcelf_prof;mA7|mARC700|mcpu=arc700|mcpu=ARC700: -marcelf}"
185 #endif
186
187 #if DEFAULT_LIBC != LIBC_UCLIBC
188 #define STARTFILE_SPEC "%{!shared:crt0.o%s} crti%O%s %{pg|p:crtg.o%s} crtbegin.o%s"
189 #else
190 #define STARTFILE_SPEC "%{!shared:%{!mkernel:crt1.o%s}} crti.o%s \
191 %{!shared:%{pg|p|profile:crtg.o%s} crtbegin.o%s} %{shared:crtbeginS.o%s}"
192
193 #endif
194
195 #if DEFAULT_LIBC != LIBC_UCLIBC
196 #define ENDFILE_SPEC "%{pg|p:crtgend.o%s} crtend.o%s crtn%O%s"
197 #else
198 #define ENDFILE_SPEC "%{!shared:%{pg|p|profile:crtgend.o%s} crtend.o%s} \
199 %{shared:crtendS.o%s} crtn.o%s"
200
201 #endif
202
203 #if DEFAULT_LIBC == LIBC_UCLIBC
204 #undef LIB_SPEC
205 #define LIB_SPEC \
206 "%{pthread:-lpthread} \
207 %{shared:-lc} \
208 %{!shared:%{pg|p|profile:-lgmon -u profil --defsym __profil=profil} -lc}"
209 #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
210 #else
211 #undef LIB_SPEC
212 /* -lc_p not present for arc-elf32-* : ashwin */
213 #define LIB_SPEC "%{!shared:%{g*:-lg} %{pg|p:-lgmon} -lc}"
214 #endif
215
216 #ifndef DRIVER_ENDIAN_SELF_SPECS
217 #define DRIVER_ENDIAN_SELF_SPECS ""
218 #endif
219 #ifndef TARGET_SDATA_DEFAULT
220 #define TARGET_SDATA_DEFAULT 1
221 #endif
222 #ifndef TARGET_MMEDIUM_CALLS_DEFAULT
223 #define TARGET_MMEDIUM_CALLS_DEFAULT 0
224 #endif
225
226 #define DRIVER_SELF_SPECS DRIVER_ENDIAN_SELF_SPECS \
227 "%{mARC5|mA5: -mcpu=A5 %<mARC5 %<mA5}" \
228 "%{mARC600|mA6: -mcpu=ARC600 %<mARC600 %<mA6}" \
229 "%{mARC601: -mcpu=ARC601 %<mARC601}" \
230 "%{mARC700|mA7: -mcpu=ARC700 %<mARC700 %<mA7}" \
231 "%{mbarrel_shifte*: -mbarrel-shifte%* %<mbarrel_shifte*}" \
232 "%{mEA: -mea %<mEA}" \
233 "%{mspfp_*: -mspfp-%* %<mspfp_*}" \
234 "%{mdpfp_*: -mdpfp-%* %<mdpfp_*}" \
235 "%{mdsp_pack*: -mdsp-pack%* %<mdsp_pack*}" \
236 "%{mmac_*: -mmac-%* %<mmac_*}" \
237 "%{multcost=*: -mmultcost=%* %<multcost=*}"
238
239 /* Run-time compilation parameters selecting different hardware subsets. */
240
241 #define TARGET_MIXED_CODE (TARGET_MIXED_CODE_SET)
242
243 #define TARGET_SPFP (TARGET_SPFP_FAST_SET || TARGET_SPFP_COMPACT_SET)
244 #define TARGET_DPFP (TARGET_DPFP_FAST_SET || TARGET_DPFP_COMPACT_SET)
245
246 #define SUBTARGET_SWITCHES
247
248 /* Instruction set characteristics.
249 These are internal macros, set by the appropriate -m option. */
250
251 /* Non-zero means the cpu supports norm instruction. This flag is set by
252 default for A7, and only for pre A7 cores when -mnorm is given. */
253 #define TARGET_NORM (TARGET_ARC700 || TARGET_NORM_SET)
254 /* Indicate if an optimized floating point emulation library is available. */
255 #define TARGET_OPTFPE \
256 (TARGET_ARC700 \
257 /* We need a barrel shifter and NORM. */ \
258 || (TARGET_ARC600 && TARGET_NORM_SET))
259
260 /* Non-zero means the cpu supports swap instruction. This flag is set by
261 default for A7, and only for pre A7 cores when -mswap is given. */
262 #define TARGET_SWAP (TARGET_ARC700 || TARGET_SWAP_SET)
263
264 /* Provide some macros for size / scheduling features of the ARC700, so
265 that we can pick & choose features if we get a new cpu family member. */
266
267 /* Should we try to unalign likely taken branches without a delay slot. */
268 #define TARGET_UNALIGN_BRANCH (TARGET_ARC700 && !optimize_size)
269
270 /* Should we upsize short delayed branches with a short delay insn? */
271 #define TARGET_UPSIZE_DBR (TARGET_ARC700 && !optimize_size)
272
273 /* Should we add padding before a return insn to avoid mispredict? */
274 #define TARGET_PAD_RETURN (TARGET_ARC700 && !optimize_size)
275
276 /* For an anulled-true delay slot insn for a delayed branch, should we only
277 use conditional execution? */
278 #define TARGET_AT_DBR_CONDEXEC (!TARGET_ARC700)
279
280 #define TARGET_A5 (arc_cpu == PROCESSOR_A5)
281 #define TARGET_ARC600 (arc_cpu == PROCESSOR_ARC600)
282 #define TARGET_ARC601 (arc_cpu == PROCESSOR_ARC601)
283 #define TARGET_ARC700 (arc_cpu == PROCESSOR_ARC700)
284
285 /* Recast the cpu class to be the cpu attribute. */
286 #define arc_cpu_attr ((enum attr_cpu)arc_cpu)
287
288 #ifndef MULTILIB_DEFAULTS
289 #define MULTILIB_DEFAULTS { "mARC700" }
290 #endif
291
292 /* Target machine storage layout. */
293
294 /* We want zero_extract to mean the same
295 no matter what the byte endianness is. */
296 #define BITS_BIG_ENDIAN 0
297
298 /* Define this if most significant byte of a word is the lowest numbered. */
299 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
300
301 /* Define this if most significant word of a multiword number is the lowest
302 numbered. */
303 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
304
305 /* Width in bits of a "word", which is the contents of a machine register.
306 Note that this is not necessarily the width of data type `int';
307 if using 16-bit ints on a 68000, this would still be 32.
308 But on a machine with 16-bit registers, this would be 16. */
309 #define BITS_PER_WORD 32
310
311 /* Width of a word, in units (bytes). */
312 #define UNITS_PER_WORD 4
313
314 /* Define this macro if it is advisable to hold scalars in registers
315 in a wider mode than that declared by the program. In such cases,
316 the value is constrained to be within the bounds of the declared
317 type, but kept valid in the wider mode. The signedness of the
318 extension may differ from that of the type. */
319 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
320 if (GET_MODE_CLASS (MODE) == MODE_INT \
321 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
322 { \
323 (MODE) = SImode; \
324 }
325
326 /* Width in bits of a pointer.
327 See also the macro `Pmode' defined below. */
328 #define POINTER_SIZE 32
329
330 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
331 #define PARM_BOUNDARY 32
332
333 /* Boundary (in *bits*) on which stack pointer should be aligned. */
334 /* TOCHECK: Changed from 64 to 32 */
335 #define STACK_BOUNDARY 32
336
337 /* ALIGN FRAMES on word boundaries. */
338 #define ARC_STACK_ALIGN(LOC) \
339 (((LOC) + STACK_BOUNDARY / BITS_PER_UNIT - 1) & -STACK_BOUNDARY/BITS_PER_UNIT)
340
341 /* Allocation boundary (in *bits*) for the code of a function. */
342 #define FUNCTION_BOUNDARY 32
343
344 /* Alignment of field after `int : 0' in a structure. */
345 #define EMPTY_FIELD_BOUNDARY 32
346
347 /* Every structure's size must be a multiple of this. */
348 #define STRUCTURE_SIZE_BOUNDARY 8
349
350 /* A bitfield declared as `int' forces `int' alignment for the struct. */
351 #define PCC_BITFIELD_TYPE_MATTERS 1
352
353 /* An expression for the alignment of a structure field FIELD if the
354 alignment computed in the usual way (including applying of
355 `BIGGEST_ALIGNMENT' and `BIGGEST_FIELD_ALIGNMENT' to the
356 alignment) is COMPUTED. It overrides alignment only if the field
357 alignment has not been set by the `__attribute__ ((aligned (N)))'
358 construct.
359 */
360
361 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
362 (TYPE_MODE (strip_array_types (TREE_TYPE (FIELD))) == DFmode \
363 ? MIN ((COMPUTED), 32) : (COMPUTED))
364
365
366
367 /* No data type wants to be aligned rounder than this. */
368 /* This is bigger than currently necessary for the ARC. If 8 byte floats are
369 ever added it's not clear whether they'll need such alignment or not. For
370 now we assume they will. We can always relax it if necessary but the
371 reverse isn't true. */
372 /* TOCHECK: Changed from 64 to 32 */
373 #define BIGGEST_ALIGNMENT 32
374
375 /* The best alignment to use in cases where we have a choice. */
376 #define FASTEST_ALIGNMENT 32
377
378 /* Make strings word-aligned so strcpy from constants will be faster. */
379 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
380 ((TREE_CODE (EXP) == STRING_CST \
381 && (ALIGN) < FASTEST_ALIGNMENT) \
382 ? FASTEST_ALIGNMENT : (ALIGN))
383
384
385 /* Make arrays of chars word-aligned for the same reasons. */
386 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
387 (TREE_CODE (TYPE) == ARRAY_TYPE \
388 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
389 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
390
391 #define DATA_ALIGNMENT(TYPE, ALIGN) \
392 (TREE_CODE (TYPE) == ARRAY_TYPE \
393 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
394 && arc_size_opt_level < 3 \
395 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
396
397 /* Set this nonzero if move instructions will actually fail to work
398 when given unaligned data. */
399 /* On the ARC the lower address bits are masked to 0 as necessary. The chip
400 won't croak when given an unaligned address, but the insn will still fail
401 to produce the correct result. */
402 #define STRICT_ALIGNMENT 1
403
404 /* Layout of source language data types. */
405
406 #define SHORT_TYPE_SIZE 16
407 #define INT_TYPE_SIZE 32
408 #define LONG_TYPE_SIZE 32
409 #define LONG_LONG_TYPE_SIZE 64
410 #define FLOAT_TYPE_SIZE 32
411 #define DOUBLE_TYPE_SIZE 64
412 #define LONG_DOUBLE_TYPE_SIZE 64
413
414 /* Define this as 1 if `char' should by default be signed; else as 0. */
415 #define DEFAULT_SIGNED_CHAR 0
416
417 #define SIZE_TYPE "long unsigned int"
418 #define PTRDIFF_TYPE "long int"
419 #define WCHAR_TYPE "int"
420 #define WCHAR_TYPE_SIZE 32
421
422
423 /* ashwin : shifted from arc.c:102 */
424 #define PROGRAM_COUNTER_REGNO 63
425
426 /* Standard register usage. */
427
428 /* Number of actual hardware registers.
429 The hardware registers are assigned numbers for the compiler
430 from 0 to just below FIRST_PSEUDO_REGISTER.
431 All registers that the compiler knows about must be given numbers,
432 even those that are not normally considered general registers.
433
434 Registers 61, 62, and 63 are not really registers and we needn't treat
435 them as such. We still need a register for the condition code and
436 argument pointer. */
437
438 /* r63 is pc, r64-r127 = simd vregs, r128-r143 = simd dma config regs
439 r144, r145 = lp_start, lp_end
440 and therefore the pseudo registers start from r146. */
441 #define FIRST_PSEUDO_REGISTER 146
442
443 /* 1 for registers that have pervasive standard uses
444 and are not available for the register allocator.
445
446 0-28 - general purpose registers
447 29 - ilink1 (interrupt link register)
448 30 - ilink2 (interrupt link register)
449 31 - blink (branch link register)
450 32-59 - reserved for extensions
451 60 - LP_COUNT
452 61 - condition code
453 62 - argument pointer
454 63 - program counter
455
456 FWIW, this is how the 61-63 encodings are used by the hardware:
457 61 - reserved
458 62 - long immediate data indicator
459 63 - PCL (program counter aligned to 32 bit, read-only)
460
461 The general purpose registers are further broken down into:
462
463 0-7 - arguments/results
464 8-12 - call used (r11 - static chain pointer)
465 13-25 - call saved
466 26 - global pointer
467 27 - frame pointer
468 28 - stack pointer
469 29 - ilink1
470 30 - ilink2
471 31 - return address register
472
473 By default, the extension registers are not available. */
474 /* Present implementations only have VR0-VR23 only. */
475 /* ??? FIXME: r27 and r31 should not be fixed registers. */
476 #define FIXED_REGISTERS \
477 { 0, 0, 0, 0, 0, 0, 0, 0, \
478 0, 0, 0, 0, 0, 0, 0, 0, \
479 0, 0, 0, 0, 0, 0, 0, 0, \
480 0, 0, 1, 1, 1, 1, 1, 1, \
481 \
482 1, 1, 1, 1, 1, 1, 1, 1, \
483 0, 0, 0, 0, 1, 1, 1, 1, \
484 1, 1, 1, 1, 1, 1, 1, 1, \
485 1, 1, 1, 1, 0, 1, 1, 1, \
486 \
487 0, 0, 0, 0, 0, 0, 0, 0, \
488 0, 0, 0, 0, 0, 0, 0, 0, \
489 0, 0, 0, 0, 0, 0, 0, 0, \
490 1, 1, 1, 1, 1, 1, 1, 1, \
491 \
492 1, 1, 1, 1, 1, 1, 1, 1, \
493 1, 1, 1, 1, 1, 1, 1, 1, \
494 1, 1, 1, 1, 1, 1, 1, 1, \
495 1, 1, 1, 1, 1, 1, 1, 1, \
496 \
497 0, 0, 0, 0, 0, 0, 0, 0, \
498 0, 0, 0, 0, 0, 0, 0, 0, \
499 1, 1}
500
501 /* 1 for registers not available across function calls.
502 These must include the FIXED_REGISTERS and also any
503 registers that can be used without being saved.
504 The latter must include the registers where values are returned
505 and the register where structure-value addresses are passed.
506 Aside from that, you can include as many other registers as you like. */
507 #define CALL_USED_REGISTERS \
508 { \
509 1, 1, 1, 1, 1, 1, 1, 1, \
510 1, 1, 1, 1, 1, 0, 0, 0, \
511 0, 0, 0, 0, 0, 0, 0, 0, \
512 0, 0, 1, 1, 1, 1, 1, 1, \
513 \
514 1, 1, 1, 1, 1, 1, 1, 1, \
515 1, 1, 1, 1, 1, 1, 1, 1, \
516 1, 1, 1, 1, 1, 1, 1, 1, \
517 1, 1, 1, 1, 1, 1, 1, 1, \
518 \
519 0, 0, 0, 0, 0, 0, 0, 0, \
520 0, 0, 0, 0, 0, 0, 0, 0, \
521 0, 0, 0, 0, 0, 0, 0, 0, \
522 1, 1, 1, 1, 1, 1, 1, 1, \
523 \
524 1, 1, 1, 1, 1, 1, 1, 1, \
525 1, 1, 1, 1, 1, 1, 1, 1, \
526 1, 1, 1, 1, 1, 1, 1, 1, \
527 1, 1, 1, 1, 1, 1, 1, 1, \
528 \
529 0, 0, 0, 0, 0, 0, 0, 0, \
530 0, 0, 0, 0, 0, 0, 0, 0, \
531 1, 1}
532
533 /* If defined, an initializer for a vector of integers, containing the
534 numbers of hard registers in the order in which GCC should
535 prefer to use them (from most preferred to least). */
536 #define REG_ALLOC_ORDER \
537 { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, \
538 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \
539 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
540 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \
541 27, 28, 29, 30, 31, 63}
542
543 /* Return number of consecutive hard regs needed starting at reg REGNO
544 to hold something of mode MODE.
545 This is ordinarily the length in words of a value of mode MODE
546 but can be less for certain modes in special long registers. */
547 #define HARD_REGNO_NREGS(REGNO, MODE) \
548 ((GET_MODE_SIZE (MODE) == 16 \
549 && REGNO >= ARC_FIRST_SIMD_VR_REG && REGNO <= ARC_LAST_SIMD_VR_REG) ? 1 \
550 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
551
552 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
553 extern unsigned int arc_hard_regno_mode_ok[];
554 extern unsigned int arc_mode_class[];
555 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
556 ((arc_hard_regno_mode_ok[REGNO] & arc_mode_class[MODE]) != 0)
557
558 /* A C expression that is nonzero if it is desirable to choose
559 register allocation so as to avoid move instructions between a
560 value of mode MODE1 and a value of mode MODE2.
561
562 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
563 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
564 MODE2)' must be zero. */
565
566 /* Tie QI/HI/SI modes together. */
567 #define MODES_TIEABLE_P(MODE1, MODE2) \
568 (GET_MODE_CLASS (MODE1) == MODE_INT \
569 && GET_MODE_CLASS (MODE2) == MODE_INT \
570 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
571 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
572
573 /* Internal macros to classify a register number as to whether it's a
574 general purpose register for compact insns (r0-r3,r12-r15), or
575 stack pointer (r28). */
576
577 #define COMPACT_GP_REG_P(REGNO) \
578 (((signed)(REGNO) >= 0 && (REGNO) <= 3) || ((REGNO) >= 12 && (REGNO) <= 15))
579 #define SP_REG_P(REGNO) ((REGNO) == 28)
580
581
582
583 /* Register classes and constants. */
584
585 /* Define the classes of registers for register constraints in the
586 machine description. Also define ranges of constants.
587
588 One of the classes must always be named ALL_REGS and include all hard regs.
589 If there is more than one class, another class must be named NO_REGS
590 and contain no registers.
591
592 The name GENERAL_REGS must be the name of a class (or an alias for
593 another name such as ALL_REGS). This is the class of registers
594 that is allowed by "g" or "r" in a register constraint.
595 Also, registers outside this class are allocated only when
596 instructions express preferences for them.
597
598 The classes must be numbered in nondecreasing order; that is,
599 a larger-numbered class must never be contained completely
600 in a smaller-numbered class.
601
602 For any two classes, it is very desirable that there be another
603 class that represents their union.
604
605 It is important that any condition codes have class NO_REGS.
606 See `register_operand'. */
607
608 enum reg_class
609 {
610 NO_REGS,
611 R0_REGS, /* 'x' */
612 GP_REG, /* 'Rgp' */
613 FP_REG, /* 'f' */
614 SP_REGS, /* 'b' */
615 LPCOUNT_REG, /* 'l' */
616 LINK_REGS, /* 'k' */
617 DOUBLE_REGS, /* D0, D1 */
618 SIMD_VR_REGS, /* VR00-VR63 */
619 SIMD_DMA_CONFIG_REGS, /* DI0-DI7,DO0-DO7 */
620 ARCOMPACT16_REGS, /* 'q' */
621 AC16_BASE_REGS, /* 'e' */
622 SIBCALL_REGS, /* "Rsc" */
623 GENERAL_REGS, /* 'r' */
624 MPY_WRITABLE_CORE_REGS, /* 'W' */
625 WRITABLE_CORE_REGS, /* 'w' */
626 CHEAP_CORE_REGS, /* 'c' */
627 ALL_CORE_REGS, /* 'Rac' */
628 ALL_REGS,
629 LIM_REG_CLASSES
630 };
631
632 #define N_REG_CLASSES (int) LIM_REG_CLASSES
633
634 /* Give names of register classes as strings for dump file. */
635 #define REG_CLASS_NAMES \
636 { \
637 "NO_REGS", \
638 "R0_REGS", \
639 "GP_REG", \
640 "FP_REG", \
641 "SP_REGS", \
642 "LPCOUNT_REG", \
643 "LINK_REGS", \
644 "DOUBLE_REGS", \
645 "SIMD_VR_REGS", \
646 "SIMD_DMA_CONFIG_REGS", \
647 "ARCOMPACT16_REGS", \
648 "AC16_BASE_REGS", \
649 "SIBCALL_REGS", \
650 "GENERAL_REGS", \
651 "MPY_WRITABLE_CORE_REGS", \
652 "WRITABLE_CORE_REGS", \
653 "CHEAP_CORE_REGS", \
654 "ALL_CORE_REGS", \
655 "ALL_REGS" \
656 }
657
658 /* Define which registers fit in which classes.
659 This is an initializer for a vector of HARD_REG_SET
660 of length N_REG_CLASSES. */
661
662 #define REG_CLASS_CONTENTS \
663 { \
664 {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* No Registers */ \
665 {0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'x', r0 register , r0 */ \
666 {0x04000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rgp', Global Pointer, r26 */ \
667 {0x08000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'f', Frame Pointer, r27 */ \
668 {0x10000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'b', Stack Pointer, r28 */ \
669 {0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000}, /* 'l', LPCOUNT Register, r60 */ \
670 {0xe0000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'k', LINK Registers, r29-r31 */ \
671 {0x00000000, 0x00000f00, 0x00000000, 0x00000000, 0x00000000}, /* 'D', D1, D2 Registers */ \
672 {0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000}, /* 'V', VR00-VR63 Registers */ \
673 {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000ffff}, /* 'V', DI0-7,DO0-7 Registers */ \
674 {0x0000f00f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'q', r0-r3, r12-r15 */ \
675 {0x1000f00f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'e', r0-r3, r12-r15, sp */ \
676 {0x1c001fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* "Rsc", r0-r12 */ \
677 {0x9fffffff, 0xc0000000, 0x00000000, 0x00000000, 0x00000000}, /* 'r', r0-r28, blink, ap and pcl */ \
678 {0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'W', r0-r31 */ \
679 /* Include ap / pcl in WRITABLE_CORE_REGS for sake of symmetry. As these \
680 registers are fixed, it does not affect the literal meaning of the \
681 constraints, but it makes it a superset of GENERAL_REGS, thus \
682 enabling some operations that would otherwise not be possible. */ \
683 {0xffffffff, 0xd0000000, 0x00000000, 0x00000000, 0x00000000}, /* 'w', r0-r31, r60 */ \
684 {0xffffffff, 0xdfffffff, 0x00000000, 0x00000000, 0x00000000}, /* 'c', r0-r60, ap, pcl */ \
685 {0xffffffff, 0xdfffffff, 0x00000000, 0x00000000, 0x00000000}, /* 'Rac', r0-r60, ap, pcl */ \
686 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff} /* All Registers */ \
687 }
688
689 /* Local macros to mark the first and last regs of different classes. */
690 #define ARC_FIRST_SIMD_VR_REG 64
691 #define ARC_LAST_SIMD_VR_REG 127
692
693 #define ARC_FIRST_SIMD_DMA_CONFIG_REG 128
694 #define ARC_FIRST_SIMD_DMA_CONFIG_IN_REG 128
695 #define ARC_FIRST_SIMD_DMA_CONFIG_OUT_REG 136
696 #define ARC_LAST_SIMD_DMA_CONFIG_REG 143
697
698 /* The same information, inverted:
699 Return the class number of the smallest class containing
700 reg number REGNO. This could be a conditional expression
701 or could index an array. */
702
703 extern enum reg_class arc_regno_reg_class[];
704
705 #define REGNO_REG_CLASS(REGNO) (arc_regno_reg_class[REGNO])
706
707 /* The class value for valid index registers. An index register is
708 one used in an address where its value is either multiplied by
709 a scale factor or added to another register (as well as added to a
710 displacement). */
711
712 #define INDEX_REG_CLASS (TARGET_MIXED_CODE ? ARCOMPACT16_REGS : GENERAL_REGS)
713
714 /* The class value for valid base registers. A base register is one used in
715 an address which is the register value plus a displacement. */
716
717 #define BASE_REG_CLASS (TARGET_MIXED_CODE ? AC16_BASE_REGS : GENERAL_REGS)
718
719 /* These assume that REGNO is a hard or pseudo reg number.
720 They give nonzero only if REGNO is a hard reg of the suitable class
721 or a pseudo reg currently allocated to a suitable hard reg.
722 Since they use reg_renumber, they are safe only once reg_renumber
723 has been allocated, which happens in local-alloc.c. */
724 #define REGNO_OK_FOR_BASE_P(REGNO) \
725 ((REGNO) < 29 || ((REGNO) == ARG_POINTER_REGNUM) || ((REGNO) == 63) ||\
726 (unsigned) reg_renumber[REGNO] < 29)
727
728 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
729
730 /* Given an rtx X being reloaded into a reg required to be
731 in class CLASS, return the class of reg to actually use.
732 In general this is just CLASS; but on some machines
733 in some cases it is preferable to use a more restrictive class. */
734
735 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
736 arc_preferred_reload_class((X), (CLASS))
737
738 extern enum reg_class arc_preferred_reload_class (rtx, enum reg_class);
739
740 /* Return the maximum number of consecutive registers
741 needed to represent mode MODE in a register of class CLASS. */
742
743 #define CLASS_MAX_NREGS(CLASS, MODE) \
744 (( GET_MODE_SIZE (MODE) == 16 && CLASS == SIMD_VR_REGS) ? 1: \
745 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
746
747 #define SMALL_INT(X) ((unsigned) ((X) + 0x100) < 0x200)
748 #define SMALL_INT_RANGE(X, OFFSET, SHIFT) \
749 ((unsigned) (((X) >> (SHIFT)) + 0x100) \
750 < 0x200 - ((unsigned) (OFFSET) >> (SHIFT)))
751 #define SIGNED_INT12(X) ((unsigned) ((X) + 0x800) < 0x1000)
752 #define LARGE_INT(X) \
753 (((X) < 0) \
754 ? (X) >= (-(HOST_WIDE_INT) 0x7fffffff - 1) \
755 : (unsigned HOST_WIDE_INT) (X) <= (unsigned HOST_WIDE_INT) 0xffffffff)
756 #define UNSIGNED_INT3(X) ((unsigned) (X) < 0x8)
757 #define UNSIGNED_INT5(X) ((unsigned) (X) < 0x20)
758 #define UNSIGNED_INT6(X) ((unsigned) (X) < 0x40)
759 #define UNSIGNED_INT7(X) ((unsigned) (X) < 0x80)
760 #define UNSIGNED_INT8(X) ((unsigned) (X) < 0x100)
761 #define IS_ONE(X) ((X) == 1)
762 #define IS_ZERO(X) ((X) == 0)
763
764 /* Stack layout and stack pointer usage. */
765
766 /* Define this macro if pushing a word onto the stack moves the stack
767 pointer to a smaller address. */
768 #define STACK_GROWS_DOWNWARD 1
769
770 /* Define this if the nominal address of the stack frame
771 is at the high-address end of the local variables;
772 that is, each additional local variable allocated
773 goes at a more negative offset in the frame. */
774 #define FRAME_GROWS_DOWNWARD 1
775
776 /* Offset within stack frame to start allocating local variables at.
777 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
778 first local allocated. Otherwise, it is the offset to the BEGINNING
779 of the first local allocated. */
780 #define STARTING_FRAME_OFFSET 0
781
782 /* Offset from the stack pointer register to the first location at which
783 outgoing arguments are placed. */
784 #define STACK_POINTER_OFFSET (0)
785
786 /* Offset of first parameter from the argument pointer register value. */
787 #define FIRST_PARM_OFFSET(FNDECL) (0)
788
789 /* A C expression whose value is RTL representing the address in a
790 stack frame where the pointer to the caller's frame is stored.
791 Assume that FRAMEADDR is an RTL expression for the address of the
792 stack frame itself.
793
794 If you don't define this macro, the default is to return the value
795 of FRAMEADDR--that is, the stack frame address is also the address
796 of the stack word that points to the previous frame. */
797 /* ??? unfinished */
798 /*define DYNAMIC_CHAIN_ADDRESS (FRAMEADDR)*/
799
800 /* A C expression whose value is RTL representing the value of the
801 return address for the frame COUNT steps up from the current frame.
802 FRAMEADDR is the frame pointer of the COUNT frame, or the frame
803 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME'
804 is defined. */
805 /* The current return address is in r31. The return address of anything
806 farther back is at [%fp,4]. */
807
808 #define RETURN_ADDR_RTX(COUNT, FRAME) \
809 arc_return_addr_rtx(COUNT,FRAME)
810
811 /* Register to use for pushing function arguments. */
812 #define STACK_POINTER_REGNUM 28
813
814 /* Base register for access to local variables of the function. */
815 #define FRAME_POINTER_REGNUM 27
816
817 /* Base register for access to arguments of the function. This register
818 will be eliminated into either fp or sp. */
819 #define ARG_POINTER_REGNUM 62
820
821 #define RETURN_ADDR_REGNUM 31
822
823 /* TODO - check usage of STATIC_CHAIN_REGNUM with a testcase */
824 /* Register in which static-chain is passed to a function. This must
825 not be a register used by the prologue. */
826 #define STATIC_CHAIN_REGNUM 11
827
828 /* Function argument passing. */
829
830 /* If defined, the maximum amount of space required for outgoing
831 arguments will be computed and placed into the variable
832 `crtl->outgoing_args_size'. No space will be pushed
833 onto the stack for each call; instead, the function prologue should
834 increase the stack frame size by this amount. */
835 #define ACCUMULATE_OUTGOING_ARGS 1
836
837 /* Define a data type for recording info about an argument list
838 during the scan of that argument list. This data type should
839 hold all necessary information about the function itself
840 and about the args processed so far, enough to enable macros
841 such as FUNCTION_ARG to determine where the next arg should go. */
842 #define CUMULATIVE_ARGS int
843
844 /* Initialize a variable CUM of type CUMULATIVE_ARGS
845 for a call to a function whose data type is FNTYPE.
846 For a library call, FNTYPE is 0. */
847 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT,N_NAMED_ARGS) \
848 ((CUM) = 0)
849
850 /* The number of registers used for parameter passing. Local to this file. */
851 #define MAX_ARC_PARM_REGS 8
852
853 /* 1 if N is a possible register number for function argument passing. */
854 #define FUNCTION_ARG_REGNO_P(N) \
855 ((unsigned) (N) < MAX_ARC_PARM_REGS)
856
857 /* The ROUND_ADVANCE* macros are local to this file. */
858 /* Round SIZE up to a word boundary. */
859 #define ROUND_ADVANCE(SIZE) \
860 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
861
862 /* Round arg MODE/TYPE up to the next word boundary. */
863 #define ROUND_ADVANCE_ARG(MODE, TYPE) \
864 ((MODE) == BLKmode \
865 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
866 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
867
868 #define ARC_FUNCTION_ARG_BOUNDARY(MODE,TYPE) PARM_BOUNDARY
869 /* Round CUM up to the necessary point for argument MODE/TYPE. */
870 /* N.B. Vectors have alignment exceeding BIGGEST_ALIGNMENT.
871 ARC_FUNCTION_ARG_BOUNDARY reduces this to no more than 32 bit. */
872 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) \
873 ((((CUM) - 1) | (ARC_FUNCTION_ARG_BOUNDARY ((MODE), (TYPE)) - 1)/BITS_PER_WORD)\
874 + 1)
875
876 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in
877 a reg. This includes arguments that have to be passed by reference as the
878 pointer to them is passed in a reg if one is available (and that is what
879 we're given).
880 When passing arguments NAMED is always 1. When receiving arguments NAMED
881 is 1 for each argument except the last in a stdarg/varargs function. In
882 a stdarg function we want to treat the last named arg as named. In a
883 varargs function we want to treat the last named arg (which is
884 `__builtin_va_alist') as unnamed.
885 This macro is only used in this file. */
886 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
887 ((CUM) < MAX_ARC_PARM_REGS)
888
889
890 /* Function results. */
891
892 /* Define how to find the value returned by a library function
893 assuming the value has mode MODE. */
894 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
895
896 /* 1 if N is a possible register number for a function value
897 as seen by the caller. */
898 /* ??? What about r1 in DI/DF values. */
899 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
900
901 /* Tell GCC to use RETURN_IN_MEMORY. */
902 #define DEFAULT_PCC_STRUCT_RETURN 0
903
904 /* Register in which address to store a structure value
905 is passed to a function, or 0 to use `invisible' first argument. */
906 #define STRUCT_VALUE 0
907
908 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
909 the stack pointer does not matter. The value is tested only in
910 functions that have frame pointers.
911 No definition is equivalent to always zero. */
912 #define EXIT_IGNORE_STACK 0
913
914 #define EPILOGUE_USES(REGNO) arc_epilogue_uses ((REGNO))
915
916 /* Definitions for register eliminations.
917
918 This is an array of structures. Each structure initializes one pair
919 of eliminable registers. The "from" register number is given first,
920 followed by "to". Eliminations of the same "from" register are listed
921 in order of preference.
922
923 We have two registers that can be eliminated on the ARC. First, the
924 argument pointer register can always be eliminated in favor of the stack
925 pointer register or frame pointer register. Secondly, the frame pointer
926 register can often be eliminated in favor of the stack pointer register.
927 */
928
929 #define ELIMINABLE_REGS \
930 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
931 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
932 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
933
934 /* Define the offset between two registers, one to be eliminated, and the other
935 its replacement, at the start of a routine. */
936 extern int arc_initial_elimination_offset(int from, int to);
937 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
938 (OFFSET) = arc_initial_elimination_offset ((FROM), (TO))
939
940 /* Output assembler code to FILE to increment profiler label # LABELNO
941 for profiling a function entry.
942 We actually emit the profiler code at the call site, so leave this one
943 empty. */
944 #define FUNCTION_PROFILER(FILE, LABELNO) \
945 if (TARGET_UCB_MCOUNT) \
946 fprintf (FILE, "\t%s\n", arc_output_libcall ("__mcount"))
947
948 #define NO_PROFILE_COUNTERS 1
949
950 /* Trampolines. */
951
952 /* Length in units of the trampoline for entering a nested function. */
953 #define TRAMPOLINE_SIZE 20
954
955 /* Alignment required for a trampoline in bits . */
956 /* For actual data alignment we just need 32, no more than the stack;
957 however, to reduce cache coherency issues, we want to make sure that
958 trampoline instructions always appear the same in any given cache line. */
959 #define TRAMPOLINE_ALIGNMENT 256
960
961 /* Library calls. */
962
963 /* Addressing modes, and classification of registers for them. */
964
965 /* Maximum number of registers that can appear in a valid memory address. */
966 /* The `ld' insn allows 2, but the `st' insn only allows 1. */
967 #define MAX_REGS_PER_ADDRESS 1
968
969 /* We have pre inc/dec (load/store with update). */
970 #define HAVE_PRE_INCREMENT 1
971 #define HAVE_PRE_DECREMENT 1
972 #define HAVE_POST_INCREMENT 1
973 #define HAVE_POST_DECREMENT 1
974 #define HAVE_PRE_MODIFY_DISP 1
975 #define HAVE_POST_MODIFY_DISP 1
976 #define HAVE_PRE_MODIFY_REG 1
977 #define HAVE_POST_MODIFY_REG 1
978 /* ??? should also do PRE_MODIFY_REG / POST_MODIFY_REG, but that requires
979 a special predicate for the memory operand of stores, like for the SH. */
980
981 /* Recognize any constant value that is a valid address. */
982 #define CONSTANT_ADDRESS_P(X) \
983 (flag_pic?arc_legitimate_pic_addr_p (X): \
984 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
985 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST))
986
987 /* Is the argument a const_int rtx, containing an exact power of 2 */
988 #define IS_POWEROF2_P(X) (! ( (X) & ((X) - 1)) && (X))
989
990 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
991 and check its validity for a certain class.
992 We have two alternate definitions for each of them.
993 The *_NONSTRICT definition accepts all pseudo regs; the other rejects
994 them unless they have been allocated suitable hard regs.
995
996 Most source files want to accept pseudo regs in the hope that
997 they will get allocated to the class that the insn wants them to be in.
998 Source files for reload pass need to be strict.
999 After reload, it makes no difference, since pseudo regs have
1000 been eliminated by then. */
1001
1002 /* Nonzero if X is a hard reg that can be used as an index
1003 or if it is a pseudo reg. */
1004 #define REG_OK_FOR_INDEX_P_NONSTRICT(X) \
1005 ((unsigned) REGNO (X) >= FIRST_PSEUDO_REGISTER || \
1006 (unsigned) REGNO (X) < 29 || \
1007 (unsigned) REGNO (X) == 63 || \
1008 (unsigned) REGNO (X) == ARG_POINTER_REGNUM)
1009 /* Nonzero if X is a hard reg that can be used as a base reg
1010 or if it is a pseudo reg. */
1011 #define REG_OK_FOR_BASE_P_NONSTRICT(X) \
1012 ((unsigned) REGNO (X) >= FIRST_PSEUDO_REGISTER || \
1013 (unsigned) REGNO (X) < 29 || \
1014 (unsigned) REGNO (X) == 63 || \
1015 (unsigned) REGNO (X) == ARG_POINTER_REGNUM)
1016
1017 /* Nonzero if X is a hard reg that can be used as an index. */
1018 #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1019 /* Nonzero if X is a hard reg that can be used as a base reg. */
1020 #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1021
1022 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1023 that is a valid memory address for an instruction.
1024 The MODE argument is the machine mode for the MEM expression
1025 that wants to use this address. */
1026 /* The `ld' insn allows [reg],[reg+shimm],[reg+limm],[reg+reg],[limm]
1027 but the `st' insn only allows [reg],[reg+shimm],[limm].
1028 The only thing we can do is only allow the most strict case `st' and hope
1029 other parts optimize out the restrictions for `ld'. */
1030
1031 #define RTX_OK_FOR_BASE_P(X, STRICT) \
1032 (REG_P (X) \
1033 && ((STRICT) ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P_NONSTRICT (X)))
1034
1035 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
1036 (REG_P (X) \
1037 && ((STRICT) ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P_NONSTRICT (X)))
1038
1039 /* A C compound statement that attempts to replace X, which is an address
1040 that needs reloading, with a valid memory address for an operand of
1041 mode MODE. WIN is a C statement label elsewhere in the code.
1042
1043 We try to get a normal form
1044 of the address. That will allow inheritance of the address reloads. */
1045
1046 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1047 do { \
1048 if (arc_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \
1049 goto WIN; \
1050 } while (0)
1051
1052 /* Reading lp_count for anything but the lp instruction is very slow on the
1053 ARC700. */
1054 #define DONT_REALLOC(REGNO,MODE) \
1055 (TARGET_ARC700 && (REGNO) == 60)
1056
1057
1058 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1059 return the mode to be used for the comparison. */
1060 /*extern machine_mode arc_select_cc_mode ();*/
1061 #define SELECT_CC_MODE(OP, X, Y) \
1062 arc_select_cc_mode (OP, X, Y)
1063
1064 /* Return non-zero if SELECT_CC_MODE will never return MODE for a
1065 floating point inequality comparison. */
1066 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
1067
1068 /* Costs. */
1069
1070 /* Compute extra cost of moving data between one register class
1071 and another. */
1072 #define REGISTER_MOVE_COST(MODE, CLASS, TO_CLASS) \
1073 arc_register_move_cost ((MODE), (CLASS), (TO_CLASS))
1074
1075 /* Compute the cost of moving data between registers and memory. */
1076 /* Memory is 3 times as expensive as registers.
1077 ??? Is that the right way to look at it? */
1078 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
1079 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
1080
1081 /* The cost of a branch insn. */
1082 /* ??? What's the right value here? Branches are certainly more
1083 expensive than reg->reg moves. */
1084 #define BRANCH_COST(speed_p, predictable_p) 2
1085
1086 /* Scc sets the destination to 1 and then conditionally zeroes it.
1087 Best case, ORed SCCs can be made into clear - condset - condset.
1088 But it could also end up as five insns. So say it costs four on
1089 average.
1090 These extra instructions - and the second comparison - will also be
1091 an extra cost if the first comparison would have been decisive.
1092 So get an average saving, with a probability of the first branch
1093 beging decisive of p0, we want:
1094 p0 * (branch_cost - 4) > (1 - p0) * 5
1095 ??? We don't get to see that probability to evaluate, so we can
1096 only wildly guess that it might be 50%.
1097 ??? The compiler also lacks the notion of branch predictability. */
1098 #define LOGICAL_OP_NON_SHORT_CIRCUIT \
1099 (BRANCH_COST (optimize_function_for_speed_p (cfun), \
1100 false) > 9)
1101
1102 /* Nonzero if access to memory by bytes is slow and undesirable.
1103 For RISC chips, it means that access to memory by bytes is no
1104 better than access by words when possible, so grab a whole word
1105 and maybe make use of that. */
1106 #define SLOW_BYTE_ACCESS 0
1107
1108 /* Define this macro if it is as good or better to call a constant
1109 function address than to call an address kept in a register. */
1110 /* On the ARC, calling through registers is slow. */
1111 #define NO_FUNCTION_CSE 1
1112
1113 /* Section selection. */
1114 /* WARNING: These section names also appear in dwarfout.c. */
1115
1116 #define TEXT_SECTION_ASM_OP "\t.section\t.text"
1117 #define DATA_SECTION_ASM_OP "\t.section\t.data"
1118
1119 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
1120 #define SDATA_SECTION_ASM_OP "\t.section\t.sdata"
1121 #define SBSS_SECTION_ASM_OP "\t.section\t.sbss"
1122
1123 /* Expression whose value is a string, including spacing, containing the
1124 assembler operation to identify the following data as initialization/termination
1125 code. If not defined, GCC will assume such a section does not exist. */
1126 #define INIT_SECTION_ASM_OP "\t.section\t.init"
1127 #define FINI_SECTION_ASM_OP "\t.section\t.fini"
1128
1129 /* Define this macro if jump tables (for tablejump insns) should be
1130 output in the text section, along with the assembler instructions.
1131 Otherwise, the readonly data section is used.
1132 This macro is irrelevant if there is no separate readonly data section. */
1133 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic || CASE_VECTOR_PC_RELATIVE)
1134
1135 /* For DWARF. Marginally different than default so output is "prettier"
1136 (and consistent with above). */
1137 #define PUSHSECTION_FORMAT "\t%s %s\n"
1138
1139 /* Tell crtstuff.c we're using ELF. */
1140 #define OBJECT_FORMAT_ELF
1141
1142 /* PIC */
1143
1144 /* The register number of the register used to address a table of static
1145 data addresses in memory. In some cases this register is defined by a
1146 processor's ``application binary interface'' (ABI). When this macro
1147 is defined, RTL is generated for this register once, as with the stack
1148 pointer and frame pointer registers. If this macro is not defined, it
1149 is up to the machine-dependent files to allocate such a register (if
1150 necessary). */
1151 #define PIC_OFFSET_TABLE_REGNUM 26
1152
1153 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
1154 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM
1155 is not defined. */
1156 /* This register is call-saved on the ARC. */
1157 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
1158
1159 /* A C expression that is nonzero if X is a legitimate immediate
1160 operand on the target machine when generating position independent code.
1161 You can assume that X satisfies CONSTANT_P, so you need not
1162 check this. You can also assume `flag_pic' is true, so you need not
1163 check it either. You need not define this macro if all constants
1164 (including SYMBOL_REF) can be immediate operands when generating
1165 position independent code. */
1166 #define LEGITIMATE_PIC_OPERAND_P(X) (arc_legitimate_pic_operand_p(X))
1167
1168 /* PIC and small data don't mix on ARC because they use the same register. */
1169 #define SDATA_BASE_REGNUM 26
1170
1171 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1172 (flag_pic \
1173 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
1174 : DW_EH_PE_absptr)
1175
1176 /* Control the assembler format that we output. */
1177
1178 /* A C string constant describing how to begin a comment in the target
1179 assembler language. The compiler assumes that the comment will
1180 end at the end of the line. */
1181 /* Gas needs this to be "#" in order to recognize line directives. */
1182 #define ASM_COMMENT_START "#"
1183
1184 /* Output to assembler file text saying following lines
1185 may contain character constants, extra white space, comments, etc. */
1186 #define ASM_APP_ON ""
1187
1188 /* Output to assembler file text saying following lines
1189 no longer contain unusual constructs. */
1190 #define ASM_APP_OFF ""
1191
1192 /* Globalizing directive for a label. */
1193 #define GLOBAL_ASM_OP "\t.global\t"
1194
1195 /* This is how to output an assembler line defining a `char' constant. */
1196 #define ASM_OUTPUT_CHAR(FILE, VALUE) \
1197 ( fprintf (FILE, "\t.byte\t"), \
1198 output_addr_const (FILE, (VALUE)), \
1199 fprintf (FILE, "\n"))
1200
1201 /* This is how to output an assembler line defining a `short' constant. */
1202 #define ASM_OUTPUT_SHORT(FILE, VALUE) \
1203 ( fprintf (FILE, "\t.hword\t"), \
1204 output_addr_const (FILE, (VALUE)), \
1205 fprintf (FILE, "\n"))
1206
1207 /* This is how to output an assembler line defining an `int' constant.
1208 We also handle symbol output here. Code addresses must be right shifted
1209 by 2 because that's how the jump instruction wants them. */
1210 #define ASM_OUTPUT_INT(FILE, VALUE) \
1211 do { \
1212 fprintf (FILE, "\t.word\t"); \
1213 if (GET_CODE (VALUE) == LABEL_REF) \
1214 { \
1215 fprintf (FILE, "%%st(@"); \
1216 output_addr_const (FILE, (VALUE)); \
1217 fprintf (FILE, ")"); \
1218 } \
1219 else \
1220 output_addr_const (FILE, (VALUE)); \
1221 fprintf (FILE, "\n"); \
1222 } while (0)
1223
1224 /* This is how to output an assembler line defining a `float' constant. */
1225 #define ASM_OUTPUT_FLOAT(FILE, VALUE) \
1226 { \
1227 long t; \
1228 char str[30]; \
1229 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
1230 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
1231 fprintf (FILE, "\t.word\t0x%lx %s %s\n", \
1232 t, ASM_COMMENT_START, str); \
1233 }
1234
1235 /* This is how to output an assembler line defining a `double' constant. */
1236 #define ASM_OUTPUT_DOUBLE(FILE, VALUE) \
1237 { \
1238 long t[2]; \
1239 char str[30]; \
1240 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
1241 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
1242 fprintf (FILE, "\t.word\t0x%lx %s %s\n\t.word\t0x%lx\n", \
1243 t[0], ASM_COMMENT_START, str, t[1]); \
1244 }
1245
1246 /* This is how to output the definition of a user-level label named NAME,
1247 such as the label on a static function or variable NAME. */
1248 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1249 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1250
1251 #define ASM_NAME_P(NAME) ( NAME[0]=='*')
1252
1253 /* This is how to output a reference to a user-level label named NAME.
1254 `assemble_name' uses this. */
1255 /* We work around a dwarfout.c deficiency by watching for labels from it and
1256 not adding the '_' prefix. There is a comment in
1257 dwarfout.c that says it should be using ASM_OUTPUT_INTERNAL_LABEL. */
1258 #define ASM_OUTPUT_LABELREF(FILE, NAME1) \
1259 do { \
1260 const char *NAME; \
1261 NAME = (*targetm.strip_name_encoding)(NAME1); \
1262 if ((NAME)[0] == '.' && (NAME)[1] == 'L') \
1263 fprintf (FILE, "%s", NAME); \
1264 else \
1265 { \
1266 if (!ASM_NAME_P (NAME1)) \
1267 fprintf (FILE, "%s", user_label_prefix); \
1268 fprintf (FILE, "%s", NAME); \
1269 } \
1270 } while (0)
1271
1272 /* This is how to output a reference to a symbol_ref / label_ref as
1273 (part of) an operand. To disambiguate from register names like
1274 a1 / a2 / status etc, symbols are preceded by '@'. */
1275 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
1276 ASM_OUTPUT_LABEL_REF ((FILE), XSTR ((SYM), 0))
1277 #define ASM_OUTPUT_LABEL_REF(FILE,STR) \
1278 do \
1279 { \
1280 fputc ('@', file); \
1281 assemble_name ((FILE), (STR)); \
1282 } \
1283 while (0)
1284
1285 /* Store in OUTPUT a string (made with alloca) containing
1286 an assembler-name for a local static variable named NAME.
1287 LABELNO is an integer which is different for each call. */
1288 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1289 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1290 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1291
1292 /* The following macro defines the format used to output the second
1293 operand of the .type assembler directive. Different svr4 assemblers
1294 expect various different forms for this operand. The one given here
1295 is just a default. You may need to override it in your machine-
1296 specific tm.h file (depending upon the particulars of your assembler). */
1297
1298 #undef TYPE_OPERAND_FMT
1299 #define TYPE_OPERAND_FMT "@%s"
1300
1301 /* A C string containing the appropriate assembler directive to
1302 specify the size of a symbol, without any arguments. On systems
1303 that use ELF, the default (in `config/elfos.h') is `"\t.size\t"';
1304 on other systems, the default is not to define this macro. */
1305 #undef SIZE_ASM_OP
1306 #define SIZE_ASM_OP "\t.size\t"
1307
1308 /* Assembler pseudo-op to equate one value with another. */
1309 /* ??? This is needed because dwarfout.c provides a default definition too
1310 late for defaults.h (which contains the default definition of ASM_OTPUT_DEF
1311 that we use). */
1312 #ifdef SET_ASM_OP
1313 #undef SET_ASM_OP
1314 #endif
1315 #define SET_ASM_OP "\t.set\t"
1316
1317 extern char rname56[], rname57[], rname58[], rname59[];
1318 /* How to refer to registers in assembler output.
1319 This sequence is indexed by compiler's hard-register-number (see above). */
1320 #define REGISTER_NAMES \
1321 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1322 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1323 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
1324 "r24", "r25", "gp", "fp", "sp", "ilink1", "ilink2", "blink", \
1325 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
1326 "d1", "d1", "d2", "d2", "r44", "r45", "r46", "r47", \
1327 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
1328 rname56,rname57,rname58,rname59,"lp_count", "cc", "ap", "pcl", \
1329 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", \
1330 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15", \
1331 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23", \
1332 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31", \
1333 "vr32", "vr33", "vr34", "vr35", "vr36", "vr37", "vr38", "vr39", \
1334 "vr40", "vr41", "vr42", "vr43", "vr44", "vr45", "vr46", "vr47", \
1335 "vr48", "vr49", "vr50", "vr51", "vr52", "vr53", "vr54", "vr55", \
1336 "vr56", "vr57", "vr58", "vr59", "vr60", "vr61", "vr62", "vr63", \
1337 "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", \
1338 "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", \
1339 "lp_start", "lp_end" \
1340 }
1341
1342 /* Entry to the insn conditionalizer. */
1343 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1344 arc_final_prescan_insn (INSN, OPVEC, NOPERANDS)
1345
1346 /* A C expression which evaluates to true if CODE is a valid
1347 punctuation character for use in the `PRINT_OPERAND' macro. */
1348 extern char arc_punct_chars[];
1349 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1350 arc_punct_chars[(unsigned char) (CHAR)]
1351
1352 /* Print operand X (an rtx) in assembler syntax to file FILE.
1353 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1354 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1355 #define PRINT_OPERAND(FILE, X, CODE) \
1356 arc_print_operand (FILE, X, CODE)
1357
1358 /* A C compound statement to output to stdio stream STREAM the
1359 assembler syntax for an instruction operand that is a memory
1360 reference whose address is ADDR. ADDR is an RTL expression.
1361
1362 On some machines, the syntax for a symbolic address depends on
1363 the section that the address refers to. On these machines,
1364 define the macro `ENCODE_SECTION_INFO' to store the information
1365 into the `symbol_ref', and then check for it here. */
1366 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1367 arc_print_operand_address (FILE, ADDR)
1368
1369 /* This is how to output an element of a case-vector that is absolute. */
1370 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1371 do { \
1372 char label[30]; \
1373 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1374 fprintf (FILE, "\t.word "); \
1375 assemble_name (FILE, label); \
1376 fprintf(FILE, "\n"); \
1377 } while (0)
1378
1379 /* This is how to output an element of a case-vector that is relative. */
1380 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1381 do { \
1382 char label[30]; \
1383 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1384 switch (GET_MODE (BODY)) \
1385 { \
1386 case QImode: fprintf (FILE, "\t.byte "); break; \
1387 case HImode: fprintf (FILE, "\t.hword "); break; \
1388 case SImode: fprintf (FILE, "\t.word "); break; \
1389 default: gcc_unreachable (); \
1390 } \
1391 assemble_name (FILE, label); \
1392 fprintf (FILE, "-"); \
1393 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \
1394 assemble_name (FILE, label); \
1395 if (TARGET_COMPACT_CASESI) \
1396 fprintf (FILE, " + %d", 4 + arc_get_unalign ()); \
1397 fprintf(FILE, "\n"); \
1398 } while (0)
1399
1400 /* ADDR_DIFF_VECs are in the text section and thus can affect the
1401 current alignment. */
1402 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
1403 do \
1404 { \
1405 if (GET_CODE (PATTERN (JUMPTABLE)) == ADDR_DIFF_VEC \
1406 && ((GET_MODE_SIZE (GET_MODE (PATTERN (JUMPTABLE))) \
1407 * XVECLEN (PATTERN (JUMPTABLE), 1) + 1) \
1408 & 2)) \
1409 arc_toggle_unalign (); \
1410 } \
1411 while (0)
1412
1413 #define JUMP_ALIGN(LABEL) (arc_size_opt_level < 2 ? 2 : 0)
1414 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \
1415 (JUMP_ALIGN(LABEL) \
1416 ? JUMP_ALIGN(LABEL) \
1417 : GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \
1418 ? 1 : 0)
1419 /* The desired alignment for the location counter at the beginning
1420 of a loop. */
1421 /* On the ARC, align loops to 4 byte boundaries unless doing all-out size
1422 optimization. */
1423 #define LOOP_ALIGN JUMP_ALIGN
1424
1425 #define LABEL_ALIGN(LABEL) (arc_label_align (LABEL))
1426
1427 /* This is how to output an assembler line
1428 that says to advance the location counter
1429 to a multiple of 2**LOG bytes. */
1430 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1431 do { \
1432 if ((LOG) != 0) fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
1433 if ((LOG) > 1) \
1434 arc_clear_unalign (); \
1435 } while (0)
1436
1437 /* ASM_OUTPUT_ALIGNED_DECL_LOCAL (STREAM, DECL, NAME, SIZE, ALIGNMENT)
1438 Define this macro when you need to see the variable's decl in order to
1439 chose what to output. */
1440 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
1441 arc_asm_output_aligned_decl_local (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
1442
1443 /* To translate the return value of arc_function_type into a register number
1444 to jump through for function return. */
1445 extern int arc_return_address_regs[4];
1446
1447 /* Debugging information. */
1448
1449 /* Generate DBX and DWARF debugging information. */
1450 #ifdef DBX_DEBUGGING_INFO
1451 #undef DBX_DEBUGGING_INFO
1452 #endif
1453 #define DBX_DEBUGGING_INFO
1454
1455 #ifdef DWARF2_DEBUGGING_INFO
1456 #undef DWARF2_DEBUGGING_INFO
1457 #endif
1458 #define DWARF2_DEBUGGING_INFO
1459
1460 /* Prefer STABS (for now). */
1461 #undef PREFERRED_DEBUGGING_TYPE
1462 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1463
1464 /* How to renumber registers for dbx and gdb. */
1465 #define DBX_REGISTER_NUMBER(REGNO) \
1466 ((TARGET_MULMAC_32BY16_SET && (REGNO) >= 56 && (REGNO) <= 57) \
1467 ? ((REGNO) ^ !TARGET_BIG_ENDIAN) \
1468 : (TARGET_MUL64_SET && (REGNO) >= 57 && (REGNO) <= 59) \
1469 ? ((REGNO) == 57 \
1470 ? 58 /* MMED */ \
1471 : ((REGNO) & 1) ^ TARGET_BIG_ENDIAN \
1472 ? 59 /* MHI */ \
1473 : 57 + !!TARGET_MULMAC_32BY16_SET) /* MLO */ \
1474 : (REGNO))
1475
1476 #define DWARF_FRAME_REGNUM(REG) (REG)
1477
1478 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (31)
1479
1480 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 31)
1481
1482 /* Frame info. */
1483
1484 /* Define this macro to 0 if your target supports DWARF 2 frame unwind
1485 information, but it does not yet work with exception handling. */
1486 /* N.B. the below test is valid in an #if, but not in a C expression. */
1487 #if DEFAULT_LIBC == LIBC_UCLIBC
1488 #define DWARF2_UNWIND_INFO 1
1489 #else
1490 #define DWARF2_UNWIND_INFO 0
1491 #endif
1492
1493 #define EH_RETURN_DATA_REGNO(N) \
1494 ((N) < 4 ? (N) : INVALID_REGNUM)
1495
1496 /* Turn off splitting of long stabs. */
1497 #define DBX_CONTIN_LENGTH 0
1498
1499 /* Miscellaneous. */
1500
1501 /* Specify the machine mode that this machine uses
1502 for the index in the tablejump instruction.
1503 If we have pc relative case vectors, we start the case vector shortening
1504 with QImode. */
1505 #define CASE_VECTOR_MODE \
1506 ((optimize && (CASE_VECTOR_PC_RELATIVE || flag_pic)) ? QImode : Pmode)
1507
1508 /* Define as C expression which evaluates to nonzero if the tablejump
1509 instruction expects the table to contain offsets from the address of the
1510 table.
1511 Do not define this if the table should contain absolute addresses. */
1512 #define CASE_VECTOR_PC_RELATIVE TARGET_CASE_VECTOR_PC_RELATIVE
1513
1514 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
1515 CASE_VECTOR_SHORTEN_MODE_1 \
1516 (MIN_OFFSET, TARGET_COMPACT_CASESI ? MAX_OFFSET + 6 : MAX_OFFSET, BODY)
1517
1518 #define CASE_VECTOR_SHORTEN_MODE_1(MIN_OFFSET, MAX_OFFSET, BODY) \
1519 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
1520 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
1521 : (MIN_OFFSET) >= -128 && (MAX_OFFSET) <= 127 \
1522 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
1523 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 65535 \
1524 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, HImode) \
1525 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 \
1526 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, HImode) \
1527 : SImode)
1528
1529 #define ADDR_VEC_ALIGN(VEC_INSN) \
1530 (exact_log2 (GET_MODE_SIZE (GET_MODE (PATTERN (VEC_INSN)))))
1531 #undef ASM_OUTPUT_BEFORE_CASE_LABEL
1532 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) \
1533 ASM_OUTPUT_ALIGN ((FILE), ADDR_VEC_ALIGN (TABLE));
1534
1535 #define INSN_LENGTH_ALIGNMENT(INSN) \
1536 ((JUMP_P (INSN) \
1537 && GET_CODE (PATTERN (INSN)) == ADDR_DIFF_VEC \
1538 && GET_MODE (PATTERN (INSN)) == QImode) \
1539 ? 0 : length_unit_log)
1540
1541 /* Define if operations between registers always perform the operation
1542 on the full register even if a narrower mode is specified. */
1543 #define WORD_REGISTER_OPERATIONS 1
1544
1545 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1546 will either zero-extend or sign-extend. The value of this macro should
1547 be the code that says which one of the two operations is implicitly
1548 done, NIL if none. */
1549 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1550
1551
1552 /* Max number of bytes we can move from memory to memory
1553 in one reasonably fast instruction. */
1554 #define MOVE_MAX 4
1555
1556 /* Undo the effects of the movmem pattern presence on STORE_BY_PIECES_P . */
1557 #define MOVE_RATIO(SPEED) ((SPEED) ? 15 : 3)
1558
1559 /* Define this to be nonzero if shift instructions ignore all but the low-order
1560 few bits. Changed from 1 to 0 for rotate pattern testcases
1561 (e.g. 20020226-1.c). This change truncates the upper 27 bits of a word
1562 while rotating a word. Came to notice through a combine phase
1563 optimization viz. a << (32-b) is equivalent to a << (-b).
1564 */
1565 #define SHIFT_COUNT_TRUNCATED 0
1566
1567 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1568 is done just by pretending it is already truncated. */
1569 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1570
1571 /* We assume that the store-condition-codes instructions store 0 for false
1572 and some other value for true. This is the value stored for true. */
1573 #define STORE_FLAG_VALUE 1
1574
1575 /* Specify the machine mode that pointers have.
1576 After generation of rtl, the compiler makes no further distinction
1577 between pointers and any other objects of this machine mode. */
1578 /* ARCompact has full 32-bit pointers. */
1579 #define Pmode SImode
1580
1581 /* A function address in a call instruction. */
1582 #define FUNCTION_MODE SImode
1583
1584 /* Define the information needed to generate branch and scc insns. This is
1585 stored from the compare operation. Note that we can't use "rtx" here
1586 since it hasn't been defined! */
1587 extern struct rtx_def *arc_compare_op0, *arc_compare_op1;
1588
1589 /* ARC function types. */
1590 enum arc_function_type {
1591 ARC_FUNCTION_UNKNOWN, ARC_FUNCTION_NORMAL,
1592 /* These are interrupt handlers. The name corresponds to the register
1593 name that contains the return address. */
1594 ARC_FUNCTION_ILINK1, ARC_FUNCTION_ILINK2
1595 };
1596 #define ARC_INTERRUPT_P(TYPE) \
1597 ((TYPE) == ARC_FUNCTION_ILINK1 || (TYPE) == ARC_FUNCTION_ILINK2)
1598
1599 /* Compute the type of a function from its DECL. Needed for EPILOGUE_USES. */
1600 struct function;
1601 extern enum arc_function_type arc_compute_function_type (struct function *);
1602
1603 /* Called by crtstuff.c to make calls to function FUNCTION that are defined in
1604 SECTION_OP, and then to switch back to text section. */
1605 #undef CRT_CALL_STATIC_FUNCTION
1606 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
1607 asm (SECTION_OP "\n\t" \
1608 "bl @" USER_LABEL_PREFIX #FUNC "\n" \
1609 TEXT_SECTION_ASM_OP);
1610
1611 /* This macro expands to the name of the scratch register r12, used for
1612 temporary calculations according to the ABI. */
1613 #define ARC_TEMP_SCRATCH_REG "r12"
1614
1615 /* The C++ compiler must use one bit to indicate whether the function
1616 that will be called through a pointer-to-member-function is
1617 virtual. Normally, we assume that the low-order bit of a function
1618 pointer must always be zero. Then, by ensuring that the
1619 vtable_index is odd, we can distinguish which variant of the union
1620 is in use. But, on some platforms function pointers can be odd,
1621 and so this doesn't work. In that case, we use the low-order bit
1622 of the `delta' field, and shift the remainder of the `delta' field
1623 to the left. We needed to do this for A4 because the address was always
1624 shifted and thus could be odd. */
1625 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
1626 (ptrmemfunc_vbit_in_pfn)
1627
1628 #define INSN_SETS_ARE_DELAYED(X) \
1629 (GET_CODE (X) == INSN \
1630 && GET_CODE (PATTERN (X)) != SEQUENCE \
1631 && GET_CODE (PATTERN (X)) != USE \
1632 && GET_CODE (PATTERN (X)) != CLOBBER \
1633 && (get_attr_type (X) == TYPE_CALL || get_attr_type (X) == TYPE_SFUNC))
1634
1635 #define INSN_REFERENCES_ARE_DELAYED(insn) INSN_SETS_ARE_DELAYED (insn)
1636
1637 #define CALL_ATTR(X, NAME) \
1638 ((CALL_P (X) || NONJUMP_INSN_P (X)) \
1639 && GET_CODE (PATTERN (X)) != USE \
1640 && GET_CODE (PATTERN (X)) != CLOBBER \
1641 && get_attr_is_##NAME (X) == IS_##NAME##_YES) \
1642
1643 #define REVERSE_CONDITION(CODE,MODE) \
1644 (((MODE) == CC_FP_GTmode || (MODE) == CC_FP_GEmode \
1645 || (MODE) == CC_FP_UNEQmode || (MODE) == CC_FP_ORDmode \
1646 || (MODE) == CC_FPXmode) \
1647 ? reverse_condition_maybe_unordered ((CODE)) \
1648 : reverse_condition ((CODE)))
1649
1650 #define ADJUST_INSN_LENGTH(X, LENGTH) \
1651 ((LENGTH) \
1652 = (GET_CODE (PATTERN (X)) == SEQUENCE \
1653 ? ((LENGTH) \
1654 + arc_adjust_insn_length ( \
1655 as_a <rtx_sequence *> (PATTERN (X))->insn (0), \
1656 get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (0)), \
1657 true) \
1658 - get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (0)) \
1659 + arc_adjust_insn_length ( \
1660 as_a <rtx_sequence *> (PATTERN (X))->insn (1), \
1661 get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (1)), \
1662 true) \
1663 - get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (1))) \
1664 : arc_adjust_insn_length ((X), (LENGTH), false)))
1665
1666 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C,STR) ((C) == '`')
1667
1668 #define INIT_EXPANDERS arc_init_expanders ()
1669
1670 #define CFA_FRAME_BASE_OFFSET(FUNDECL) (-arc_decl_pretend_args ((FUNDECL)))
1671
1672 #define ARG_POINTER_CFA_OFFSET(FNDECL) \
1673 (FIRST_PARM_OFFSET (FNDECL) + arc_decl_pretend_args ((FNDECL)))
1674
1675 enum
1676 {
1677 ARC_LRA_PRIORITY_NONE, ARC_LRA_PRIORITY_NONCOMPACT, ARC_LRA_PRIORITY_COMPACT
1678 };
1679
1680 /* The define_cond_exec construct is rather crude, as we can't have
1681 different ones with different conditions apply to different sets
1682 of instructions. We can't use an attribute test inside the condition,
1683 because that would lead to infinite recursion as the attribute test
1684 needs to recognize the insn. So, instead we have a clause for
1685 the pattern condition of all sfunc patterns which is only relevant for
1686 the predicated varaint. */
1687 #define SFUNC_CHECK_PREDICABLE \
1688 (GET_CODE (PATTERN (insn)) != COND_EXEC || !flag_pic || !TARGET_MEDIUM_CALLS)
1689
1690 #endif /* GCC_ARC_H */