1 /* Definitions of target machine for GNU compiler, Argonaut ARC cpu.
2 Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2004, 2005,
3 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 /* ??? This is an old port, and is undoubtedly suffering from bit rot. */
26 - print active compiler options in assembler output
38 #undef WCHAR_TYPE_SIZE
39 #undef ASM_OUTPUT_LABELREF
41 /* Print subsidiary information on the compiler version in use. */
42 #define TARGET_VERSION fprintf (stderr, " (arc)")
44 /* Names to predefine in the preprocessor for this target machine. */
45 #define TARGET_CPU_CPP_BUILTINS() \
48 builtin_define ("__arc__"); \
49 if (TARGET_BIG_ENDIAN) \
50 builtin_define ("__big_endian__"); \
51 if (arc_cpu_type == 0) \
52 builtin_define ("__base__"); \
53 builtin_assert ("cpu=arc"); \
54 builtin_assert ("machine=arc"); \
57 /* Pass -mmangle-cpu if we get -mcpu=*.
58 Doing it this way lets one have it on as default with -mcpu=*,
59 but also lets one turn it off with -mno-mangle-cpu. */
61 %{mcpu=*:-mmangle-cpu} \
62 %{EB:%{EL:%emay not use both -EB and -EL}} \
63 %{EB:-mbig-endian} %{EL:-mlittle-endian} \
66 #define ASM_SPEC "%{EB} %{EL}"
68 #define LINK_SPEC "%{v} %{EB} %{EL}"
70 #define LIB_SPEC "-lc"
72 #define STARTFILE_SPEC "%{!shared:crt0.o%s} crtinit.o%s"
74 #define ENDFILE_SPEC "crtfini.o%s"
76 /* Instruction set characteristics.
77 These are internal macros, set by the appropriate -mcpu= option. */
79 /* Nonzero means the cpu has a barrel shifter. */
80 #define TARGET_SHIFTER 0
82 /* Which cpu we're compiling for. */
83 extern int arc_cpu_type
;
85 /* Check if CPU is an extension and set `arc_cpu_type' and `arc_mangle_cpu'
86 appropriately. The result should be nonzero if the cpu is recognized,
87 otherwise zero. This is intended to be redefined in a cover file.
88 This is used by arc_handle_option. */
89 #define ARC_EXTENSION_CPU(cpu) 0
92 /* Target machine storage layout. */
94 /* Define this if most significant bit is lowest numbered
95 in instructions that operate on numbered bit-fields. */
96 #define BITS_BIG_ENDIAN 1
98 /* Define this if most significant byte of a word is the lowest numbered. */
99 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
101 /* Define this if most significant word of a multiword number is the lowest
103 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
105 /* Width of a word, in units (bytes). */
106 #define UNITS_PER_WORD 4
108 /* Define this macro if it is advisable to hold scalars in registers
109 in a wider mode than that declared by the program. In such cases,
110 the value is constrained to be within the bounds of the declared
111 type, but kept valid in the wider mode. The signedness of the
112 extension may differ from that of the type. */
113 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
114 if (GET_MODE_CLASS (MODE) == MODE_INT \
115 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
120 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
121 #define PARM_BOUNDARY 32
123 /* Boundary (in *bits*) on which stack pointer should be aligned. */
124 #define STACK_BOUNDARY 64
126 /* ALIGN FRAMES on word boundaries */
127 #define ARC_STACK_ALIGN(LOC) (((LOC)+7) & ~7)
129 /* Allocation boundary (in *bits*) for the code of a function. */
130 #define FUNCTION_BOUNDARY 32
132 /* Alignment of field after `int : 0' in a structure. */
133 #define EMPTY_FIELD_BOUNDARY 32
135 /* Every structure's size must be a multiple of this. */
136 #define STRUCTURE_SIZE_BOUNDARY 8
138 /* A bit-field declared as `int' forces `int' alignment for the struct. */
139 #define PCC_BITFIELD_TYPE_MATTERS 1
141 /* No data type wants to be aligned rounder than this. */
142 /* This is bigger than currently necessary for the ARC. If 8 byte floats are
143 ever added it's not clear whether they'll need such alignment or not. For
144 now we assume they will. We can always relax it if necessary but the
145 reverse isn't true. */
146 #define BIGGEST_ALIGNMENT 64
148 /* The best alignment to use in cases where we have a choice. */
149 #define FASTEST_ALIGNMENT 32
151 /* Make strings word-aligned so strcpy from constants will be faster. */
152 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
153 ((TREE_CODE (EXP) == STRING_CST \
154 && (ALIGN) < FASTEST_ALIGNMENT) \
155 ? FASTEST_ALIGNMENT : (ALIGN))
157 /* Make arrays of chars word-aligned for the same reasons. */
158 #define DATA_ALIGNMENT(TYPE, ALIGN) \
159 (TREE_CODE (TYPE) == ARRAY_TYPE \
160 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
161 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
163 /* Set this nonzero if move instructions will actually fail to work
164 when given unaligned data. */
165 /* On the ARC the lower address bits are masked to 0 as necessary. The chip
166 won't croak when given an unaligned address, but the insn will still fail
167 to produce the correct result. */
168 #define STRICT_ALIGNMENT 1
170 /* Layout of source language data types. */
172 #define SHORT_TYPE_SIZE 16
173 #define INT_TYPE_SIZE 32
174 #define LONG_TYPE_SIZE 32
175 #define LONG_LONG_TYPE_SIZE 64
176 #define FLOAT_TYPE_SIZE 32
177 #define DOUBLE_TYPE_SIZE 64
178 #define LONG_DOUBLE_TYPE_SIZE 64
180 /* Define this as 1 if `char' should by default be signed; else as 0. */
181 #define DEFAULT_SIGNED_CHAR 1
183 #define SIZE_TYPE "long unsigned int"
184 #define PTRDIFF_TYPE "long int"
185 #define WCHAR_TYPE "short unsigned int"
186 #define WCHAR_TYPE_SIZE 16
188 /* Standard register usage. */
190 /* Number of actual hardware registers.
191 The hardware registers are assigned numbers for the compiler
192 from 0 to just below FIRST_PSEUDO_REGISTER.
193 All registers that the compiler knows about must be given numbers,
194 even those that are not normally considered general registers. */
195 /* Registers 61, 62, and 63 are not really registers and we needn't treat
196 them as such. We still need a register for the condition code. */
197 #define FIRST_PSEUDO_REGISTER 62
199 /* 1 for registers that have pervasive standard uses
200 and are not available for the register allocator.
202 0-28 - general purpose registers
203 29 - ilink1 (interrupt link register)
204 30 - ilink2 (interrupt link register)
205 31 - blink (branch link register)
206 32-59 - reserved for extensions
211 61 - short immediate data indicator (setting flags)
212 62 - long immediate data indicator
213 63 - short immediate data indicator (not setting flags).
215 The general purpose registers are further broken down into:
216 0-7 - arguments/results
219 24 - call used, static chain pointer
220 25 - call used, gptmp
225 By default, the extension registers are not available. */
227 #define FIXED_REGISTERS \
228 { 0, 0, 0, 0, 0, 0, 0, 0, \
229 0, 0, 0, 0, 0, 0, 0, 0, \
230 0, 0, 0, 0, 0, 0, 0, 0, \
231 0, 0, 0, 1, 1, 1, 1, 0, \
233 1, 1, 1, 1, 1, 1, 1, 1, \
234 1, 1, 1, 1, 1, 1, 1, 1, \
235 1, 1, 1, 1, 1, 1, 1, 1, \
238 /* 1 for registers not available across function calls.
239 These must include the FIXED_REGISTERS and also any
240 registers that can be used without being saved.
241 The latter must include the registers where values are returned
242 and the register where structure-value addresses are passed.
243 Aside from that, you can include as many other registers as you like. */
245 #define CALL_USED_REGISTERS \
246 { 1, 1, 1, 1, 1, 1, 1, 1, \
247 1, 1, 1, 1, 1, 1, 1, 1, \
248 0, 0, 0, 0, 0, 0, 0, 0, \
249 1, 1, 1, 1, 1, 1, 1, 1, \
251 1, 1, 1, 1, 1, 1, 1, 1, \
252 1, 1, 1, 1, 1, 1, 1, 1, \
253 1, 1, 1, 1, 1, 1, 1, 1, \
256 /* If defined, an initializer for a vector of integers, containing the
257 numbers of hard registers in the order in which GCC should
258 prefer to use them (from most preferred to least). */
259 #define REG_ALLOC_ORDER \
260 { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, \
261 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 31, \
262 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
263 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, \
266 /* Return number of consecutive hard regs needed starting at reg REGNO
267 to hold something of mode MODE.
268 This is ordinarily the length in words of a value of mode MODE
269 but can be less for certain modes in special long registers. */
270 #define HARD_REGNO_NREGS(REGNO, MODE) \
271 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
273 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
274 extern const unsigned int arc_hard_regno_mode_ok
[];
275 extern unsigned int arc_mode_class
[];
276 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
277 ((arc_hard_regno_mode_ok[REGNO] & arc_mode_class[MODE]) != 0)
279 /* A C expression that is nonzero if it is desirable to choose
280 register allocation so as to avoid move instructions between a
281 value of mode MODE1 and a value of mode MODE2.
283 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
284 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
285 MODE2)' must be zero. */
287 /* Tie QI/HI/SI modes together. */
288 #define MODES_TIEABLE_P(MODE1, MODE2) \
289 (GET_MODE_CLASS (MODE1) == MODE_INT \
290 && GET_MODE_CLASS (MODE2) == MODE_INT \
291 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
292 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
294 /* Register classes and constants. */
296 /* Define the classes of registers for register constraints in the
297 machine description. Also define ranges of constants.
299 One of the classes must always be named ALL_REGS and include all hard regs.
300 If there is more than one class, another class must be named NO_REGS
301 and contain no registers.
303 The name GENERAL_REGS must be the name of a class (or an alias for
304 another name such as ALL_REGS). This is the class of registers
305 that is allowed by "g" or "r" in a register constraint.
306 Also, registers outside this class are allocated only when
307 instructions express preferences for them.
309 The classes must be numbered in nondecreasing order; that is,
310 a larger-numbered class must never be contained completely
311 in a smaller-numbered class.
313 For any two classes, it is very desirable that there be another
314 class that represents their union.
316 It is important that any condition codes have class NO_REGS.
317 See `register_operand'. */
320 NO_REGS
, LPCOUNT_REG
, GENERAL_REGS
, ALL_REGS
, LIM_REG_CLASSES
323 #define N_REG_CLASSES (int) LIM_REG_CLASSES
325 /* Give names of register classes as strings for dump file. */
326 #define REG_CLASS_NAMES \
327 { "NO_REGS", "LPCOUNT_REG", "GENERAL_REGS", "ALL_REGS" }
329 /* Define which registers fit in which classes.
330 This is an initializer for a vector of HARD_REG_SET
331 of length N_REG_CLASSES. */
333 #define REG_CLASS_CONTENTS \
334 { {0, 0}, {0, 0x10000000}, {0xffffffff, 0xfffffff}, \
335 {0xffffffff, 0x1fffffff} }
337 /* The same information, inverted:
338 Return the class number of the smallest class containing
339 reg number REGNO. This could be a conditional expression
340 or could index an array. */
341 extern enum reg_class arc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
342 #define REGNO_REG_CLASS(REGNO) \
343 (arc_regno_reg_class[REGNO])
345 /* The class value for index registers, and the one for base regs. */
346 #define INDEX_REG_CLASS GENERAL_REGS
347 #define BASE_REG_CLASS GENERAL_REGS
349 /* Get reg_class from a letter such as appears in the machine description. */
350 #define REG_CLASS_FROM_LETTER(C) \
351 ((C) == 'l' ? LPCOUNT_REG /* ??? needed? */ \
354 /* These assume that REGNO is a hard or pseudo reg number.
355 They give nonzero only if REGNO is a hard reg of the suitable class
356 or a pseudo reg currently allocated to a suitable hard reg.
357 Since they use reg_renumber, they are safe only once reg_renumber
358 has been allocated, which happens in local-alloc.c. */
359 #define REGNO_OK_FOR_BASE_P(REGNO) \
360 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
361 #define REGNO_OK_FOR_INDEX_P(REGNO) \
362 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
364 /* Return the maximum number of consecutive registers
365 needed to represent mode MODE in a register of class CLASS. */
366 #define CLASS_MAX_NREGS(CLASS, MODE) \
367 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
369 /* The letters I, J, K, L, M, N, O, P in a register constraint string
370 can be used to stand for particular ranges of immediate operands.
371 This macro defines what the ranges are.
372 C is the letter, and VALUE is a constant value.
373 Return 1 if VALUE is in the range specified by C. */
374 /* 'I' is used for short immediates (always signed).
375 'J' is used for long immediates.
376 'K' is used for any constant up to 64 bits (for 64x32 situations?). */
378 /* local to this file */
379 #define SMALL_INT(X) ((unsigned) ((X) + 0x100) < 0x200)
380 /* local to this file */
381 #define LARGE_INT(X) \
382 ((X) >= (-(HOST_WIDE_INT) 0x7fffffff - 1) \
383 && (unsigned HOST_WIDE_INT)(X) <= (unsigned HOST_WIDE_INT) 0xffffffff)
385 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
386 ((C) == 'I' ? SMALL_INT (VALUE) \
387 : (C) == 'J' ? LARGE_INT (VALUE) \
391 /* Similar, but for floating constants, and defining letters G and H.
392 Here VALUE is the CONST_DOUBLE rtx itself. */
393 /* 'G' is used for integer values for the multiplication insns where the
394 operands are extended from 4 bytes to 8 bytes.
395 'H' is used when any 64-bit constant is allowed. */
396 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
397 ((C) == 'G' ? arc_double_limm_p (VALUE) \
401 /* A C expression that defines the optional machine-dependent constraint
402 letters that can be used to segregate specific types of operands,
403 usually memory references, for the target machine. It should return 1 if
404 VALUE corresponds to the operand type represented by the constraint letter
405 C. If C is not defined as an extra constraint, the value returned should
406 be 0 regardless of VALUE. */
407 /* ??? This currently isn't used. Waiting for PIC. */
409 #define EXTRA_CONSTRAINT(VALUE, C) \
410 ((C) == 'R' ? (SYMBOL_REF_FUNCTION_P (VALUE) || GET_CODE (VALUE) == LABEL_REF) \
414 /* Stack layout and stack pointer usage. */
416 /* Define this macro if pushing a word onto the stack moves the stack
417 pointer to a smaller address. */
418 #define STACK_GROWS_DOWNWARD
420 /* Define this to nonzero if the nominal address of the stack frame
421 is at the high-address end of the local variables;
422 that is, each additional local variable allocated
423 goes at a more negative offset in the frame. */
424 #define FRAME_GROWS_DOWNWARD 1
426 /* Offset within stack frame to start allocating local variables at.
427 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
428 first local allocated. Otherwise, it is the offset to the BEGINNING
429 of the first local allocated. */
430 #define STARTING_FRAME_OFFSET 0
432 /* Offset from the stack pointer register to the first location at which
433 outgoing arguments are placed. */
434 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET (0)
436 /* Offset of first parameter from the argument pointer register value. */
437 /* 4 bytes for each of previous fp, return address, and previous gp.
438 4 byte reserved area for future considerations. */
439 #define FIRST_PARM_OFFSET(FNDECL) 16
441 /* A C expression whose value is RTL representing the address in a
442 stack frame where the pointer to the caller's frame is stored.
443 Assume that FRAMEADDR is an RTL expression for the address of the
446 If you don't define this macro, the default is to return the value
447 of FRAMEADDR--that is, the stack frame address is also the address
448 of the stack word that points to the previous frame. */
450 /*define DYNAMIC_CHAIN_ADDRESS (FRAMEADDR)*/
452 /* A C expression whose value is RTL representing the value of the
453 return address for the frame COUNT steps up from the current frame.
454 FRAMEADDR is the frame pointer of the COUNT frame, or the frame
455 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME'
457 /* The current return address is in r31. The return address of anything
458 farther back is at [%fp,4]. */
459 #if 0 /* The default value should work. */
460 #define RETURN_ADDR_RTX(COUNT, FRAME) \
462 ? gen_rtx_REG (Pmode, 31) \
463 : copy_to_reg (gen_rtx_MEM (Pmode, \
464 memory_address (Pmode, \
465 plus_constant ((FRAME), \
469 /* Register to use for pushing function arguments. */
470 #define STACK_POINTER_REGNUM 28
472 /* Base register for access to local variables of the function. */
473 #define FRAME_POINTER_REGNUM 27
475 /* Base register for access to arguments of the function. */
476 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
478 /* Register in which static-chain is passed to a function. This must
479 not be a register used by the prologue. */
480 #define STATIC_CHAIN_REGNUM 24
482 /* C statement to store the difference between the frame pointer
483 and the stack pointer values immediately after the function prologue. */
484 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
485 ((VAR) = arc_compute_frame_size (get_frame_size ()))
487 /* Function argument passing. */
489 /* If defined, the maximum amount of space required for outgoing
490 arguments will be computed and placed into the variable
491 `crtl->outgoing_args_size'. No space will be pushed
492 onto the stack for each call; instead, the function prologue should
493 increase the stack frame size by this amount. */
494 #define ACCUMULATE_OUTGOING_ARGS 1
496 /* Define a data type for recording info about an argument list
497 during the scan of that argument list. This data type should
498 hold all necessary information about the function itself
499 and about the args processed so far, enough to enable macros
500 such as FUNCTION_ARG to determine where the next arg should go. */
501 #define CUMULATIVE_ARGS int
503 /* Initialize a variable CUM of type CUMULATIVE_ARGS
504 for a call to a function whose data type is FNTYPE.
505 For a library call, FNTYPE is 0. */
506 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
509 /* The number of registers used for parameter passing. Local to this file. */
510 #define MAX_ARC_PARM_REGS 8
512 /* 1 if N is a possible register number for function argument passing. */
513 #define FUNCTION_ARG_REGNO_P(N) \
514 ((unsigned) (N) < MAX_ARC_PARM_REGS)
517 /* Function results. */
519 /* Define how to find the value returned by a function.
520 VALTYPE is the data type of the value (as a tree).
521 If the precise function being called is known, FUNC is its FUNCTION_DECL;
522 otherwise, FUNC is 0. */
523 #define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
525 /* Define how to find the value returned by a library function
526 assuming the value has mode MODE. */
527 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
529 /* 1 if N is a possible register number for a function value
530 as seen by the caller. */
531 /* ??? What about r1 in DI/DF values. */
532 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
534 /* Tell GCC to use TARGET_RETURN_IN_MEMORY. */
535 #define DEFAULT_PCC_STRUCT_RETURN 0
537 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
538 the stack pointer does not matter. The value is tested only in
539 functions that have frame pointers.
540 No definition is equivalent to always zero. */
541 #define EXIT_IGNORE_STACK 0
543 /* Epilogue delay slots. */
544 #define DELAY_SLOTS_FOR_EPILOGUE arc_delay_slots_for_epilogue ()
546 #define ELIGIBLE_FOR_EPILOGUE_DELAY(TRIAL, SLOTS_FILLED) \
547 arc_eligible_for_epilogue_delay (TRIAL, SLOTS_FILLED)
549 /* Output assembler code to FILE to increment profiler label # LABELNO
550 for profiling a function entry. */
551 #define FUNCTION_PROFILER(FILE, LABELNO)
553 #define TRAMPOLINE_ALIGNMENT 32
554 #define TRAMPOLINE_SIZE 16
556 /* Addressing modes, and classification of registers for them. */
558 /* Maximum number of registers that can appear in a valid memory address. */
559 /* The `ld' insn allows 2, but the `st' insn only allows 1. */
560 #define MAX_REGS_PER_ADDRESS 1
562 /* We have pre inc/dec (load/store with update). */
563 #define HAVE_PRE_INCREMENT 1
564 #define HAVE_PRE_DECREMENT 1
566 /* Recognize any constant value that is a valid address. */
567 #define CONSTANT_ADDRESS_P(X) \
568 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
569 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)
571 /* Nonzero if the constant value X is a legitimate general operand.
572 We can handle any 32- or 64-bit constant. */
573 /* "1" should work since the largest constant should be a 64 bit critter. */
574 /* ??? Not sure what to do for 64x32 compiler. */
575 #define LEGITIMATE_CONSTANT_P(X) 1
577 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
578 and check its validity for a certain class.
579 We have two alternate definitions for each of them.
580 The usual definition accepts all pseudo regs; the other rejects
581 them unless they have been allocated suitable hard regs.
582 The symbol REG_OK_STRICT causes the latter definition to be used.
584 Most source files want to accept pseudo regs in the hope that
585 they will get allocated to the class that the insn wants them to be in.
586 Source files for reload pass need to be strict.
587 After reload, it makes no difference, since pseudo regs have
588 been eliminated by then. */
590 #ifndef REG_OK_STRICT
592 /* Nonzero if X is a hard reg that can be used as an index
593 or if it is a pseudo reg. */
594 #define REG_OK_FOR_INDEX_P(X) \
595 ((unsigned) REGNO (X) - 32 >= FIRST_PSEUDO_REGISTER - 32)
596 /* Nonzero if X is a hard reg that can be used as a base reg
597 or if it is a pseudo reg. */
598 #define REG_OK_FOR_BASE_P(X) \
599 ((unsigned) REGNO (X) - 32 >= FIRST_PSEUDO_REGISTER - 32)
603 /* Nonzero if X is a hard reg that can be used as an index. */
604 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
605 /* Nonzero if X is a hard reg that can be used as a base reg. */
606 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
610 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
611 that is a valid memory address for an instruction.
612 The MODE argument is the machine mode for the MEM expression
613 that wants to use this address. */
614 /* The `ld' insn allows [reg],[reg+shimm],[reg+limm],[reg+reg],[limm]
615 but the `st' insn only allows [reg],[reg+shimm],[limm].
616 The only thing we can do is only allow the most strict case `st' and hope
617 other parts optimize out the restrictions for `ld'. */
619 /* local to this file */
620 #define RTX_OK_FOR_BASE_P(X) \
621 (REG_P (X) && REG_OK_FOR_BASE_P (X))
623 /* local to this file */
624 #define RTX_OK_FOR_INDEX_P(X) \
625 (0 && /*???*/ REG_P (X) && REG_OK_FOR_INDEX_P (X))
627 /* local to this file */
628 /* ??? Loads can handle any constant, stores can only handle small ones. */
629 #define RTX_OK_FOR_OFFSET_P(X) \
630 (GET_CODE (X) == CONST_INT && SMALL_INT (INTVAL (X)))
632 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \
633 (GET_CODE (X) == PLUS \
634 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
635 && (RTX_OK_FOR_INDEX_P (XEXP (X, 1)) \
636 || RTX_OK_FOR_OFFSET_P (XEXP (X, 1))))
638 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
639 { if (RTX_OK_FOR_BASE_P (X)) \
641 if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X))) \
643 if (GET_CODE (X) == CONST_INT && LARGE_INT (INTVAL (X))) \
645 if (GET_CODE (X) == SYMBOL_REF \
646 || GET_CODE (X) == LABEL_REF \
647 || GET_CODE (X) == CONST) \
649 if ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
650 /* We're restricted here by the `st' insn. */ \
651 && RTX_OK_FOR_BASE_P (XEXP ((X), 0))) \
655 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
656 return the mode to be used for the comparison. */
657 #define SELECT_CC_MODE(OP, X, Y) \
658 arc_select_cc_mode (OP, X, Y)
660 /* Return nonzero if SELECT_CC_MODE will never return MODE for a
661 floating point inequality comparison. */
662 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
666 /* Compute extra cost of moving data between one register class
668 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 2
670 /* Compute the cost of moving data between registers and memory. */
671 /* Memory is 3 times as expensive as registers.
672 ??? Is that the right way to look at it? */
673 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
674 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
676 /* The cost of a branch insn. */
677 /* ??? What's the right value here? Branches are certainly more
678 expensive than reg->reg moves. */
679 #define BRANCH_COST(speed_p, predictable_p) 2
681 /* Nonzero if access to memory by bytes is slow and undesirable.
682 For RISC chips, it means that access to memory by bytes is no
683 better than access by words when possible, so grab a whole word
684 and maybe make use of that. */
685 #define SLOW_BYTE_ACCESS 1
687 /* Define this macro if it is as good or better to call a constant
688 function address than to call an address kept in a register. */
689 /* On the ARC, calling through registers is slow. */
690 #define NO_FUNCTION_CSE
692 /* Section selection. */
693 /* WARNING: These section names also appear in dwarfout.c. */
695 /* The names of the text, data, and readonly-data sections are runtime
698 #define ARC_SECTION_FORMAT "\t.section %s"
699 #define ARC_DEFAULT_TEXT_SECTION ".text"
700 #define ARC_DEFAULT_DATA_SECTION ".data"
701 #define ARC_DEFAULT_RODATA_SECTION ".rodata"
703 extern const char *arc_text_section
, *arc_data_section
, *arc_rodata_section
;
705 /* initfini.c uses this in an asm. */
706 #if defined (CRT_INIT) || defined (CRT_FINI)
707 #define TEXT_SECTION_ASM_OP "\t.section .text"
709 #define TEXT_SECTION_ASM_OP arc_text_section
711 #define DATA_SECTION_ASM_OP arc_data_section
713 #undef READONLY_DATA_SECTION_ASM_OP
714 #define READONLY_DATA_SECTION_ASM_OP arc_rodata_section
716 #define BSS_SECTION_ASM_OP "\t.section .bss"
718 /* Define this macro if jump tables (for tablejump insns) should be
719 output in the text section, along with the assembler instructions.
720 Otherwise, the readonly data section is used.
721 This macro is irrelevant if there is no separate readonly data section. */
722 /*#define JUMP_TABLES_IN_TEXT_SECTION*/
724 /* For DWARF. Marginally different than default so output is "prettier"
725 (and consistent with above). */
726 #define PUSHSECTION_ASM_OP "\t.section "
728 /* Tell crtstuff.c we're using ELF. */
729 #define OBJECT_FORMAT_ELF
733 /* The register number of the register used to address a table of static
734 data addresses in memory. In some cases this register is defined by a
735 processor's ``application binary interface'' (ABI). When this macro
736 is defined, RTL is generated for this register once, as with the stack
737 pointer and frame pointer registers. If this macro is not defined, it
738 is up to the machine-dependent files to allocate such a register (if
740 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 26 : INVALID_REGNUM)
742 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
743 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM
745 /* This register is call-saved on the ARC. */
746 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
748 /* A C expression that is nonzero if X is a legitimate immediate
749 operand on the target machine when generating position independent code.
750 You can assume that X satisfies CONSTANT_P, so you need not
751 check this. You can also assume `flag_pic' is true, so you need not
752 check it either. You need not define this macro if all constants
753 (including SYMBOL_REF) can be immediate operands when generating
754 position independent code. */
755 /*#define LEGITIMATE_PIC_OPERAND_P(X)*/
757 /* Control the assembler format that we output. */
759 /* A C string constant describing how to begin a comment in the target
760 assembler language. The compiler assumes that the comment will
761 end at the end of the line. */
762 #define ASM_COMMENT_START ";"
764 /* Output to assembler file text saying following lines
765 may contain character constants, extra white space, comments, etc. */
766 #define ASM_APP_ON ""
768 /* Output to assembler file text saying following lines
769 no longer contain unusual constructs. */
770 #define ASM_APP_OFF ""
772 /* Globalizing directive for a label. */
773 #define GLOBAL_ASM_OP "\t.global\t"
775 /* This is how to output a reference to a user-level label named NAME.
776 `assemble_name' uses this. */
777 /* We mangle all user labels to provide protection from linking code
778 compiled for different cpus. */
779 /* We work around a dwarfout.c deficiency by watching for labels from it and
780 not adding the '_' prefix nor the cpu suffix. There is a comment in
781 dwarfout.c that says it should be using (*targetm.asm_out.internal_label). */
782 extern const char *arc_mangle_cpu
;
783 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
785 if ((NAME)[0] == '.' && (NAME)[1] == 'L') \
786 fprintf (FILE, "%s", NAME); \
790 if (TARGET_MANGLE_CPU && arc_mangle_cpu != NULL) \
791 fprintf (FILE, "%s_", arc_mangle_cpu); \
792 fprintf (FILE, "%s", NAME); \
796 /* Assembler pseudo-op to equate one value with another. */
797 /* ??? This is needed because dwarfout.c provides a default definition too
798 late for defaults.h (which contains the default definition of ASM_OUTPUT_DEF
800 #define SET_ASM_OP "\t.set\t"
802 /* How to refer to registers in assembler output.
803 This sequence is indexed by compiler's hard-register-number (see above). */
804 #define REGISTER_NAMES \
805 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
806 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
807 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
808 "r24", "r25", "r26", "fp", "sp", "ilink1", "ilink2", "blink", \
809 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
810 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
811 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
812 "r56", "r57", "r58", "r59", "lp_count", "cc"}
814 /* Entry to the insn conditionalizer. */
815 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
816 arc_final_prescan_insn (INSN, OPVEC, NOPERANDS)
818 /* A C expression which evaluates to true if CODE is a valid
819 punctuation character for use in the `PRINT_OPERAND' macro. */
820 extern char arc_punct_chars
[256];
821 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
822 arc_punct_chars[(unsigned char) (CHAR)]
824 /* Print operand X (an rtx) in assembler syntax to file FILE.
825 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
826 For `%' followed by punctuation, CODE is the punctuation and X is null. */
827 #define PRINT_OPERAND(FILE, X, CODE) \
828 arc_print_operand (FILE, X, CODE)
830 /* A C compound statement to output to stdio stream STREAM the
831 assembler syntax for an instruction operand that is a memory
832 reference whose address is ADDR. ADDR is an RTL expression. */
833 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
834 arc_print_operand_address (FILE, ADDR)
836 /* This is how to output an element of a case-vector that is absolute. */
837 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
840 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
841 fprintf (FILE, "\t.word %%st("); \
842 assemble_name (FILE, label); \
843 fprintf (FILE, ")\n"); \
846 /* This is how to output an element of a case-vector that is relative. */
847 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
850 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
851 fprintf (FILE, "\t.word %%st("); \
852 assemble_name (FILE, label); \
853 fprintf (FILE, "-"); \
854 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \
855 assemble_name (FILE, label); \
856 fprintf (FILE, ")\n"); \
859 /* The desired alignment for the location counter at the beginning
861 /* On the ARC, align loops to 32 byte boundaries (cache line size)
863 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0)
865 /* This is how to output an assembler line
866 that says to advance the location counter
867 to a multiple of 2**LOG bytes. */
868 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
869 do { if ((LOG) != 0) fprintf (FILE, "\t.align %d\n", 1 << (LOG)); } while (0)
871 /* Debugging information. */
873 /* Generate DBX and DWARF debugging information. */
874 #define DBX_DEBUGGING_INFO 1
876 /* Prefer STABS (for now). */
877 #undef PREFERRED_DEBUGGING_TYPE
878 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
880 /* Turn off splitting of long stabs. */
881 #define DBX_CONTIN_LENGTH 0
885 /* Specify the machine mode that this machine uses
886 for the index in the tablejump instruction. */
887 #define CASE_VECTOR_MODE Pmode
889 /* Define if operations between registers always perform the operation
890 on the full register even if a narrower mode is specified. */
891 #define WORD_REGISTER_OPERATIONS
893 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
894 will either zero-extend or sign-extend. The value of this macro should
895 be the code that says which one of the two operations is implicitly
896 done, UNKNOWN if none. */
897 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
899 /* Max number of bytes we can move from memory to memory
900 in one reasonably fast instruction. */
903 /* Define this to be nonzero if shift instructions ignore all but the low-order
905 #define SHIFT_COUNT_TRUNCATED 1
907 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
908 is done just by pretending it is already truncated. */
909 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
911 /* Specify the machine mode that pointers have.
912 After generation of rtl, the compiler makes no further distinction
913 between pointers and any other objects of this machine mode. */
914 /* ??? The arc doesn't have full 32-bit pointers, but making this PSImode has
915 its own problems (you have to add extendpsisi2 and trucnsipsi2 but how does
916 one do it without getting excess code?). Try to avoid it. */
919 /* A function address in a call instruction. */
920 #define FUNCTION_MODE SImode
922 /* alloca should avoid clobbering the old register save area. */
923 /* ??? Not defined in tm.texi. */
924 #define SETJMP_VIA_SAVE_AREA
926 /* ARC function types. */
927 enum arc_function_type
{
928 ARC_FUNCTION_UNKNOWN
, ARC_FUNCTION_NORMAL
,
929 /* These are interrupt handlers. The name corresponds to the register
930 name that contains the return address. */
931 ARC_FUNCTION_ILINK1
, ARC_FUNCTION_ILINK2
933 #define ARC_INTERRUPT_P(TYPE) \
934 ((TYPE) == ARC_FUNCTION_ILINK1 || (TYPE) == ARC_FUNCTION_ILINK2)
935 /* Compute the type of a function from its DECL. */