gcc/config/arc/arc.opt

   1 ; Options for the Synopsys DesignWare ARC port of the compiler
   2 ;
   3 ; Copyright (C) 2005-2015 Free Software Foundation, Inc.
   4 ;
   5 ; This file is part of GCC.
   6 ;
   7 ; GCC is free software; you can redistribute it and/or modify it under
   8 ; the terms of the GNU General Public License as published by the Free
   9 ; Software Foundation; either version 3, or (at your option) any later
  10 ; version.
  11 ;
  12 ; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ; License for more details.
  16 ;
  17 ; You should have received a copy of the GNU General Public License
  18 ; along with GCC; see the file COPYING3.  If not see
  19 ; <http://www.gnu.org/licenses/>.
  20
  21 HeaderInclude
  22 config/arc/arc-opts.h
  23
  24 mbig-endian
  25 Target Report RejectNegative Mask(BIG_ENDIAN)
  26 Compile code for big endian mode
  27
  28 mlittle-endian
  29 Target Report RejectNegative InverseMask(BIG_ENDIAN)
  30 Compile code for little endian mode.  This is the default
  31
  32 mno-cond-exec
  33 Target Report RejectNegative Mask(NO_COND_EXEC)
  34 Disable ARCompact specific pass to generate conditional execution instructions
  35
  36 mA5
  37 Target Report
  38 Generate ARCompact 32-bit code for ARCtangent-A5 processor
  39
  40 mA6
  41 Target Report
  42 Generate ARCompact 32-bit code for ARC600 processor
  43
  44 mARC600
  45 Target Report
  46 Same as -mA6
  47
  48 mARC601
  49 Target Report
  50 Generate ARCompact 32-bit code for ARC601 processor
  51
  52 mA7
  53 Target Report
  54 Generate ARCompact 32-bit code for ARC700 processor
  55
  56 mARC700
  57 Target Report
  58 Same as -mA7
  59
  60 mmixed-code
  61 Target Report Mask(MIXED_CODE_SET)
  62 Tweak register allocation to help 16-bit instruction generation
  63 ; originally this was:
  64 ;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions for ARCtangent-A5 and higher processors
  65 ; but we do that without -mmixed-code, too, it's just a different instruction
  66 ; count / size tradeoff.
  67
  68 ; We use an explict definition for the negative form because that is the
  69 ; actually interesting option, and we want that to have its own comment.
  70 mvolatile-cache
  71 Target Report RejectNegative Mask(VOLATILE_CACHE_SET)
  72 Use ordinarily cached memory accesses for volatile references
  73
  74 mno-volatile-cache
  75 Target Report RejectNegative InverseMask(VOLATILE_CACHE_SET)
  76 Enable cache bypass for volatile references
  77
  78 mbarrel-shifter
  79 Target Report Mask(BARREL_SHIFTER)
  80 Generate instructions supported by barrel shifter
  81
  82 mnorm
  83 Target Report Mask(NORM_SET)
  84 Generate norm instruction
  85
  86 mswap
  87 Target Report Mask(SWAP_SET)
  88 Generate swap instruction
  89
  90 mmul64
  91 Target Report Mask(MUL64_SET)
  92 Generate mul64 and mulu64 instructions
  93
  94 mno-mpy
  95 Target Report Mask(NOMPY_SET)
  96 Do not generate mpy instructions for ARC700
  97
  98 mea
  99 Target Report Mask(EA_SET)
 100 Generate Extended arithmetic instructions.  Currently only divaw, adds, subs and sat16 are supported
 101
 102 msoft-float
 103 Target Report Mask(0)
 104 Dummy flag. This is the default unless FPX switches are provided explicitly
 105
 106 mlong-calls
 107 Target Report Mask(LONG_CALLS_SET)
 108 Generate call insns as register indirect calls
 109
 110 mno-brcc
 111 Target Report Mask(NO_BRCC_SET)
 112 Do no generate BRcc instructions in arc_reorg.
 113
 114 msdata
 115 Target Report InverseMask(NO_SDATA_SET)
 116 Generate sdata references.  This is the default, unless you compile for PIC.
 117
 118 mno-millicode
 119 Target Report Mask(NO_MILLICODE_THUNK_SET)
 120 Do not generate millicode thunks (needed only with -Os)
 121
 122 mspfp
 123 Target Report Mask(SPFP_COMPACT_SET)
 124 FPX: Generate Single Precision FPX (compact) instructions.
 125
 126 mspfp-compact
 127 Target Report Mask(SPFP_COMPACT_SET) MaskExists
 128 FPX: Generate Single Precision FPX (compact) instructions.
 129
 130 mspfp-fast
 131 Target Report Mask(SPFP_FAST_SET)
 132 FPX: Generate Single Precision FPX (fast) instructions.
 133
 134 margonaut
 135 Target Report Mask(ARGONAUT_SET)
 136 FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
 137
 138 mdpfp
 139 Target Report Mask(DPFP_COMPACT_SET)
 140 FPX: Generate Double Precision FPX (compact) instructions.
 141
 142 mdpfp-compact
 143 Target Report Mask(DPFP_COMPACT_SET) MaskExists
 144 FPX: Generate Double Precision FPX (compact) instructions.
 145
 146 mdpfp-fast
 147 Target Report Mask(DPFP_FAST_SET)
 148 FPX: Generate Double Precision FPX (fast) instructions.
 149
 150 mno-dpfp-lrsr
 151 Target Report Mask(DPFP_DISABLE_LRSR)
 152 Disable LR and SR instructions from using FPX extension aux registers.
 153
 154 msimd
 155 Target Report Mask(SIMD_SET)
 156 Enable generation of ARC SIMD instructions via target-specific builtins.
 157
 158 mcpu=
 159 Target RejectNegative Joined Var(arc_cpu) Enum(processor_type) Init(PROCESSOR_NONE)
 160 -mcpu=CPU       Compile code for ARC variant CPU
 161
 162 Enum
 163 Name(processor_type) Type(enum processor_type)
 164
 165 EnumValue
 166 Enum(processor_type) String(A5) Value(PROCESSOR_A5)
 167
 168 EnumValue
 169 Enum(processor_type) String(ARC600) Value(PROCESSOR_ARC600)
 170
 171 EnumValue
 172 Enum(processor_type) String(ARC601) Value(PROCESSOR_ARC601)
 173
 174 EnumValue
 175 Enum(processor_type) String(ARC700) Value(PROCESSOR_ARC700)
 176
 177 msize-level=
 178 Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1)
 179 size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os
 180
 181 misize
 182 Target Report PchIgnore Var(TARGET_DUMPISIZE)
 183 Annotate assembler instructions with estimated addresses
 184
 185 mmultcost=
 186 Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1)
 187 Cost to assume for a multiply instruction, with 4 being equal to a normal insn.
 188
 189 mtune=ARC600
 190 Target RejectNegative Var(arc_tune, TUNE_ARC600)
 191 Tune for ARC600 cpu.
 192
 193 mtune=ARC601
 194 Target RejectNegative Var(arc_tune, TUNE_ARC600)
 195 Tune for ARC601 cpu.
 196
 197 mtune=ARC700
 198 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_STD)
 199 Tune for ARC700 R4.2 Cpu with standard multiplier block.
 200
 201 mtune=ARC700-xmac
 202 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
 203 Tune for ARC700 R4.2 Cpu with XMAC block.
 204
 205 mtune=ARC725D
 206 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
 207 Tune for ARC700 R4.2 Cpu with XMAC block.
 208
 209 mtune=ARC750D
 210 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
 211 Tune for ARC700 R4.2 Cpu with XMAC block.
 212
 213 mindexed-loads
 214 Target Var(TARGET_INDEXED_LOADS)
 215 Enable the use of indexed loads
 216
 217 mauto-modify-reg
 218 Target Var(TARGET_AUTO_MODIFY_REG)
 219 Enable the use of pre/post modify with register displacement.
 220
 221 mmul32x16
 222 Target Report Mask(MULMAC_32BY16_SET)
 223 Generate 32x16 multiply and mac instructions
 224
 225 ; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) ,
 226 ; alas, basic-block.h is not included in options.c .
 227 munalign-prob-threshold=
 228 Target RejectNegative Joined UInteger Var(arc_unalign_prob_threshold) Init(10000/2)
 229 Set probability threshold for unaligning branches
 230
 231 mmedium-calls
 232 Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT)
 233 Don't use less than 25 bit addressing range for calls.
 234
 235 mannotate-align
 236 Target Var(TARGET_ANNOTATE_ALIGN)
 237 Explain what alignment considerations lead to the decision to make an insn short or long.
 238
 239 malign-call
 240 Target Var(TARGET_ALIGN_CALL)
 241 Do alignment optimizations for call instructions.
 242
 243 mRcq
 244 Target Var(TARGET_Rcq)
 245 Enable Rcq constraint handling - most short code generation depends on this.
 246
 247 mRcw
 248 Target Var(TARGET_Rcw)
 249 Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
 250
 251 mearly-cbranchsi
 252 Target Var(TARGET_EARLY_CBRANCHSI)
 253 Enable pre-reload use of cbranchsi pattern
 254
 255 mbbit-peephole
 256 Target Var(TARGET_BBIT_PEEPHOLE)
 257 Enable bbit peephole2
 258
 259 mcase-vector-pcrel
 260 Target Var(TARGET_CASE_VECTOR_PC_RELATIVE)
 261 Use pc-relative switch case tables - this enables case table shortening.
 262
 263 mcompact-casesi
 264 Target Var(TARGET_COMPACT_CASESI)
 265 Enable compact casesi pattern
 266
 267 mq-class
 268 Target Var(TARGET_Q_CLASS)
 269 Enable 'q' instruction alternatives.
 270
 271 mexpand-adddi
 272 Target Var(TARGET_EXPAND_ADDDI)
 273 Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc.
 274
 275
 276 ; Flags used by the assembler, but for which we define preprocessor
 277 ; macro symbols as well.
 278 mcrc
 279 Target Report
 280 Enable variable polynomial CRC extension
 281
 282 mdsp-packa
 283 Target Report
 284 Enable DSP 3.1 Pack A extensions
 285
 286 mdvbf
 287 Target Report
 288 Enable dual viterbi butterfly extension
 289
 290 mmac-d16
 291 Target Report Undocumented
 292
 293 mmac-24
 294 Target Report Undocumented
 295
 296 mtelephony
 297 Target Report RejectNegative
 298 Enable Dual and Single Operand Instructions for Telephony
 299
 300 mxy
 301 Target Report
 302 Enable XY Memory extension (DSP version 3)
 303
 304 ; ARC700 4.10 extension instructions
 305 mlock
 306 Target Report
 307 Enable Locked Load/Store Conditional extension
 308
 309 mswape
 310 Target Report
 311 Enable swap byte ordering extension instruction
 312
 313 mrtsc
 314 Target Report
 315 Enable 64-bit Time-Stamp Counter extension instruction
 316
 317 mno-epilogue-cfi
 318 Target Report RejectNegative InverseMask(EPILOGUE_CFI)
 319 Disable generation of cfi for epilogues.
 320
 321 mepilogue-cfi
 322 Target RejectNegative Mask(EPILOGUE_CFI)
 323 Enable generation of cfi for epilogues.
 324
 325 EB
 326 Target
 327 Pass -EB option through to linker.
 328
 329 EL
 330 Target
 331 Pass -EL option through to linker.
 332
 333 marclinux
 334 target
 335 Pass -marclinux option through to linker.
 336
 337 marclinux_prof
 338 target
 339 Pass -marclinux_prof option through to linker.
 340
 341 ;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra.
 342 ;Target InverseMask(NO_LRA)
 343 ; lra still won't allow to configure libgcc; see PR rtl-optimization/55464.
 344 ; so don't enable by default.
 345 mlra
 346 Target Mask(LRA)
 347 Enable lra
 348
 349 mlra-priority-none
 350 Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE)
 351 Don't indicate any priority with TARGET_REGISTER_PRIORITY
 352
 353 mlra-priority-compact
 354 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_COMPACT)
 355 Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY
 356
 357 mlra-priority-noncompact
 358 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_NONCOMPACT)
 359 Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY
 360
 361 mucb-mcount
 362 Target Report Var(TARGET_UCB_MCOUNT)
 363 instrument with mcount calls as in the ucb code
 364
 365 ; backward-compatibility aliases, translated by DRIVER_SELF_SPECS
 366
 367 mEA
 368 Target
 369
 370 multcost=
 371 Target RejectNegative Joined
 372
 373 ; Unfortunately, listing the full option name gives us clashes
 374 ; with OPT_opt_name being claimed for both opt_name and opt-name,
 375 ; so we leave out the last character or more.
 376 mbarrel_shifte
 377 Target Joined
 378
 379 mspfp_
 380 Target Joined
 381
 382 mdpfp_
 383 Target Joined
 384
 385 mdsp_pack
 386 Target Joined
 387
 388 mmac_
 389 Target Joined
 390