1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
6 and Martin Simmons (@harleqn.co.uk).
7 More major hacks by Richard Earnshaw (rearnsha@arm.com).
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 3, or (at your
14 option) any later version.
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING3. If not see
23 <http://www.gnu.org/licenses/>. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
43 #include "diagnostic-core.h"
48 #include "c-family/c-pragma.h" /* ??? */
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
61 /* Forward definitions of types. */
62 typedef struct minipool_node Mnode
;
63 typedef struct minipool_fixup Mfix
;
65 void (*arm_lang_output_object_attributes_hook
)(void);
67 /* Forward function declarations. */
68 static bool arm_needs_doubleword_align (enum machine_mode
, const_tree
);
69 static int arm_compute_static_chain_stack_bytes (void);
70 static arm_stack_offsets
*arm_get_frame_offsets (void);
71 static void arm_add_gc_roots (void);
72 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, rtx
,
73 HOST_WIDE_INT
, rtx
, rtx
, int, int);
74 static unsigned bit_count (unsigned long);
75 static int arm_address_register_rtx_p (rtx
, int);
76 static int arm_legitimate_index_p (enum machine_mode
, rtx
, RTX_CODE
, int);
77 static int thumb2_legitimate_index_p (enum machine_mode
, rtx
, int);
78 static int thumb1_base_register_rtx_p (rtx
, enum machine_mode
, int);
79 static rtx
arm_legitimize_address (rtx
, rtx
, enum machine_mode
);
80 static rtx
thumb_legitimize_address (rtx
, rtx
, enum machine_mode
);
81 inline static int thumb1_index_register_rtx_p (rtx
, int);
82 static bool arm_legitimate_address_p (enum machine_mode
, rtx
, bool);
83 static int thumb_far_jump_used_p (void);
84 static bool thumb_force_lr_save (void);
85 static int const_ok_for_op (HOST_WIDE_INT
, enum rtx_code
);
86 static rtx
emit_sfm (int, int);
87 static unsigned arm_size_return_regs (void);
88 static bool arm_assemble_integer (rtx
, unsigned int, int);
89 static void arm_print_operand (FILE *, rtx
, int);
90 static void arm_print_operand_address (FILE *, rtx
);
91 static bool arm_print_operand_punct_valid_p (unsigned char code
);
92 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
93 static arm_cc
get_arm_condition_code (rtx
);
94 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
95 static rtx
is_jump_table (rtx
);
96 static const char *output_multi_immediate (rtx
*, const char *, const char *,
98 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
99 static struct machine_function
*arm_init_machine_status (void);
100 static void thumb_exit (FILE *, int);
101 static rtx
is_jump_table (rtx
);
102 static HOST_WIDE_INT
get_jump_table_size (rtx
);
103 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
104 static Mnode
*add_minipool_forward_ref (Mfix
*);
105 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
106 static Mnode
*add_minipool_backward_ref (Mfix
*);
107 static void assign_minipool_offsets (Mfix
*);
108 static void arm_print_value (FILE *, rtx
);
109 static void dump_minipool (rtx
);
110 static int arm_barrier_cost (rtx
);
111 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
112 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
113 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
115 static void arm_reorg (void);
116 static bool note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
117 static unsigned long arm_compute_save_reg0_reg12_mask (void);
118 static unsigned long arm_compute_save_reg_mask (void);
119 static unsigned long arm_isr_value (tree
);
120 static unsigned long arm_compute_func_type (void);
121 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
122 static tree
arm_handle_pcs_attribute (tree
*, tree
, tree
, int, bool *);
123 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
124 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
125 static tree
arm_handle_notshared_attribute (tree
*, tree
, tree
, int, bool *);
127 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
128 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
129 static void thumb1_output_function_prologue (FILE *, HOST_WIDE_INT
);
130 static int arm_comp_type_attributes (const_tree
, const_tree
);
131 static void arm_set_default_type_attributes (tree
);
132 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
133 static int count_insns_for_constant (HOST_WIDE_INT
, int);
134 static int arm_get_strip_length (int);
135 static bool arm_function_ok_for_sibcall (tree
, tree
);
136 static enum machine_mode
arm_promote_function_mode (const_tree
,
137 enum machine_mode
, int *,
139 static bool arm_return_in_memory (const_tree
, const_tree
);
140 static rtx
arm_function_value (const_tree
, const_tree
, bool);
141 static rtx
arm_libcall_value (enum machine_mode
, const_rtx
);
143 static void arm_internal_label (FILE *, const char *, unsigned long);
144 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
146 static bool arm_have_conditional_execution (void);
147 static bool arm_cannot_force_const_mem (enum machine_mode
, rtx
);
148 static bool arm_legitimate_constant_p (enum machine_mode
, rtx
);
149 static bool arm_rtx_costs_1 (rtx
, enum rtx_code
, int*, bool);
150 static bool arm_size_rtx_costs (rtx
, enum rtx_code
, enum rtx_code
, int *);
151 static bool arm_slowmul_rtx_costs (rtx
, enum rtx_code
, enum rtx_code
, int *, bool);
152 static bool arm_fastmul_rtx_costs (rtx
, enum rtx_code
, enum rtx_code
, int *, bool);
153 static bool arm_xscale_rtx_costs (rtx
, enum rtx_code
, enum rtx_code
, int *, bool);
154 static bool arm_9e_rtx_costs (rtx
, enum rtx_code
, enum rtx_code
, int *, bool);
155 static bool arm_rtx_costs (rtx
, int, int, int *, bool);
156 static int arm_address_cost (rtx
, bool);
157 static bool arm_memory_load_p (rtx
);
158 static bool arm_cirrus_insn_p (rtx
);
159 static void cirrus_reorg (rtx
);
160 static void arm_init_builtins (void);
161 static void arm_init_iwmmxt_builtins (void);
162 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
163 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
164 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
165 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
166 static tree
arm_builtin_decl (unsigned, bool);
167 static void emit_constant_insn (rtx cond
, rtx pattern
);
168 static rtx
emit_set_insn (rtx
, rtx
);
169 static int arm_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
171 static rtx
arm_function_arg (CUMULATIVE_ARGS
*, enum machine_mode
,
173 static void arm_function_arg_advance (CUMULATIVE_ARGS
*, enum machine_mode
,
175 static unsigned int arm_function_arg_boundary (enum machine_mode
, const_tree
);
176 static rtx
aapcs_allocate_return_reg (enum machine_mode
, const_tree
,
178 static int aapcs_select_return_coproc (const_tree
, const_tree
);
180 #ifdef OBJECT_FORMAT_ELF
181 static void arm_elf_asm_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
182 static void arm_elf_asm_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
185 static void arm_encode_section_info (tree
, rtx
, int);
188 static void arm_file_end (void);
189 static void arm_file_start (void);
191 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
193 static bool arm_pass_by_reference (CUMULATIVE_ARGS
*,
194 enum machine_mode
, const_tree
, bool);
195 static bool arm_promote_prototypes (const_tree
);
196 static bool arm_default_short_enums (void);
197 static bool arm_align_anon_bitfield (void);
198 static bool arm_return_in_msb (const_tree
);
199 static bool arm_must_pass_in_stack (enum machine_mode
, const_tree
);
200 static bool arm_return_in_memory (const_tree
, const_tree
);
202 static void arm_unwind_emit (FILE *, rtx
);
203 static bool arm_output_ttype (rtx
);
204 static void arm_asm_emit_except_personality (rtx
);
205 static void arm_asm_init_sections (void);
207 static enum unwind_info_type
arm_except_unwind_info (struct gcc_options
*);
208 static void arm_dwarf_handle_frame_unspec (const char *, rtx
, int);
209 static rtx
arm_dwarf_register_span (rtx
);
211 static tree
arm_cxx_guard_type (void);
212 static bool arm_cxx_guard_mask_bit (void);
213 static tree
arm_get_cookie_size (tree
);
214 static bool arm_cookie_has_size (void);
215 static bool arm_cxx_cdtor_returns_this (void);
216 static bool arm_cxx_key_method_may_be_inline (void);
217 static void arm_cxx_determine_class_data_visibility (tree
);
218 static bool arm_cxx_class_data_always_comdat (void);
219 static bool arm_cxx_use_aeabi_atexit (void);
220 static void arm_init_libfuncs (void);
221 static tree
arm_build_builtin_va_list (void);
222 static void arm_expand_builtin_va_start (tree
, rtx
);
223 static tree
arm_gimplify_va_arg_expr (tree
, tree
, gimple_seq
*, gimple_seq
*);
224 static void arm_option_override (void);
225 static unsigned HOST_WIDE_INT
arm_shift_truncation_mask (enum machine_mode
);
226 static bool arm_cannot_copy_insn_p (rtx
);
227 static bool arm_tls_symbol_p (rtx x
);
228 static int arm_issue_rate (void);
229 static void arm_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
230 static bool arm_output_addr_const_extra (FILE *, rtx
);
231 static bool arm_allocate_stack_slots_for_args (void);
232 static const char *arm_invalid_parameter_type (const_tree t
);
233 static const char *arm_invalid_return_type (const_tree t
);
234 static tree
arm_promoted_type (const_tree t
);
235 static tree
arm_convert_to_type (tree type
, tree expr
);
236 static bool arm_scalar_mode_supported_p (enum machine_mode
);
237 static bool arm_frame_pointer_required (void);
238 static bool arm_can_eliminate (const int, const int);
239 static void arm_asm_trampoline_template (FILE *);
240 static void arm_trampoline_init (rtx
, tree
, rtx
);
241 static rtx
arm_trampoline_adjust_address (rtx
);
242 static rtx
arm_pic_static_addr (rtx orig
, rtx reg
);
243 static bool cortex_a9_sched_adjust_cost (rtx
, rtx
, rtx
, int *);
244 static bool xscale_sched_adjust_cost (rtx
, rtx
, rtx
, int *);
245 static bool fa726te_sched_adjust_cost (rtx
, rtx
, rtx
, int *);
246 static bool arm_array_mode_supported_p (enum machine_mode
,
247 unsigned HOST_WIDE_INT
);
248 static enum machine_mode
arm_preferred_simd_mode (enum machine_mode
);
249 static bool arm_class_likely_spilled_p (reg_class_t
);
250 static bool arm_vector_alignment_reachable (const_tree type
, bool is_packed
);
251 static bool arm_builtin_support_vector_misalignment (enum machine_mode mode
,
255 static void arm_conditional_register_usage (void);
256 static reg_class_t
arm_preferred_rename_class (reg_class_t rclass
);
257 static unsigned int arm_autovectorize_vector_sizes (void);
260 /* Table of machine attributes. */
261 static const struct attribute_spec arm_attribute_table
[] =
263 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
264 affects_type_identity } */
265 /* Function calls made to this symbol must be done indirectly, because
266 it may lie outside of the 26 bit addressing range of a normal function
268 { "long_call", 0, 0, false, true, true, NULL
, false },
269 /* Whereas these functions are always known to reside within the 26 bit
271 { "short_call", 0, 0, false, true, true, NULL
, false },
272 /* Specify the procedure call conventions for a function. */
273 { "pcs", 1, 1, false, true, true, arm_handle_pcs_attribute
,
275 /* Interrupt Service Routines have special prologue and epilogue requirements. */
276 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
,
278 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
,
280 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
,
283 /* ARM/PE has three new attributes:
285 dllexport - for exporting a function/variable that will live in a dll
286 dllimport - for importing a function/variable from a dll
288 Microsoft allows multiple declspecs in one __declspec, separating
289 them with spaces. We do NOT support this. Instead, use __declspec
292 { "dllimport", 0, 0, true, false, false, NULL
, false },
293 { "dllexport", 0, 0, true, false, false, NULL
, false },
294 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
,
296 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
297 { "dllimport", 0, 0, false, false, false, handle_dll_attribute
, false },
298 { "dllexport", 0, 0, false, false, false, handle_dll_attribute
, false },
299 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute
,
302 { NULL
, 0, 0, false, false, false, NULL
, false }
305 /* Set default optimization options. */
306 static const struct default_options arm_option_optimization_table
[] =
308 /* Enable section anchors by default at -O1 or higher. */
309 { OPT_LEVELS_1_PLUS
, OPT_fsection_anchors
, NULL
, 1 },
310 { OPT_LEVELS_1_PLUS
, OPT_fomit_frame_pointer
, NULL
, 1 },
311 { OPT_LEVELS_NONE
, 0, NULL
, 0 }
314 /* Initialize the GCC target structure. */
315 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
316 #undef TARGET_MERGE_DECL_ATTRIBUTES
317 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
320 #undef TARGET_LEGITIMIZE_ADDRESS
321 #define TARGET_LEGITIMIZE_ADDRESS arm_legitimize_address
323 #undef TARGET_ATTRIBUTE_TABLE
324 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
326 #undef TARGET_ASM_FILE_START
327 #define TARGET_ASM_FILE_START arm_file_start
328 #undef TARGET_ASM_FILE_END
329 #define TARGET_ASM_FILE_END arm_file_end
331 #undef TARGET_ASM_ALIGNED_SI_OP
332 #define TARGET_ASM_ALIGNED_SI_OP NULL
333 #undef TARGET_ASM_INTEGER
334 #define TARGET_ASM_INTEGER arm_assemble_integer
336 #undef TARGET_PRINT_OPERAND
337 #define TARGET_PRINT_OPERAND arm_print_operand
338 #undef TARGET_PRINT_OPERAND_ADDRESS
339 #define TARGET_PRINT_OPERAND_ADDRESS arm_print_operand_address
340 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
341 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P arm_print_operand_punct_valid_p
343 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
344 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA arm_output_addr_const_extra
346 #undef TARGET_ASM_FUNCTION_PROLOGUE
347 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
349 #undef TARGET_ASM_FUNCTION_EPILOGUE
350 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
352 #undef TARGET_DEFAULT_TARGET_FLAGS
353 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
354 #undef TARGET_OPTION_OVERRIDE
355 #define TARGET_OPTION_OVERRIDE arm_option_override
356 #undef TARGET_OPTION_OPTIMIZATION_TABLE
357 #define TARGET_OPTION_OPTIMIZATION_TABLE arm_option_optimization_table
359 #undef TARGET_COMP_TYPE_ATTRIBUTES
360 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
362 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
363 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
365 #undef TARGET_SCHED_ADJUST_COST
366 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
368 #undef TARGET_ENCODE_SECTION_INFO
370 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
372 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
375 #undef TARGET_STRIP_NAME_ENCODING
376 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
378 #undef TARGET_ASM_INTERNAL_LABEL
379 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
381 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
382 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
384 #undef TARGET_FUNCTION_VALUE
385 #define TARGET_FUNCTION_VALUE arm_function_value
387 #undef TARGET_LIBCALL_VALUE
388 #define TARGET_LIBCALL_VALUE arm_libcall_value
390 #undef TARGET_ASM_OUTPUT_MI_THUNK
391 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
392 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
393 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
395 #undef TARGET_RTX_COSTS
396 #define TARGET_RTX_COSTS arm_rtx_costs
397 #undef TARGET_ADDRESS_COST
398 #define TARGET_ADDRESS_COST arm_address_cost
400 #undef TARGET_SHIFT_TRUNCATION_MASK
401 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
402 #undef TARGET_VECTOR_MODE_SUPPORTED_P
403 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
404 #undef TARGET_ARRAY_MODE_SUPPORTED_P
405 #define TARGET_ARRAY_MODE_SUPPORTED_P arm_array_mode_supported_p
406 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
407 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE arm_preferred_simd_mode
408 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
409 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
410 arm_autovectorize_vector_sizes
412 #undef TARGET_MACHINE_DEPENDENT_REORG
413 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
415 #undef TARGET_INIT_BUILTINS
416 #define TARGET_INIT_BUILTINS arm_init_builtins
417 #undef TARGET_EXPAND_BUILTIN
418 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
419 #undef TARGET_BUILTIN_DECL
420 #define TARGET_BUILTIN_DECL arm_builtin_decl
422 #undef TARGET_INIT_LIBFUNCS
423 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
425 #undef TARGET_PROMOTE_FUNCTION_MODE
426 #define TARGET_PROMOTE_FUNCTION_MODE arm_promote_function_mode
427 #undef TARGET_PROMOTE_PROTOTYPES
428 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
429 #undef TARGET_PASS_BY_REFERENCE
430 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
431 #undef TARGET_ARG_PARTIAL_BYTES
432 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
433 #undef TARGET_FUNCTION_ARG
434 #define TARGET_FUNCTION_ARG arm_function_arg
435 #undef TARGET_FUNCTION_ARG_ADVANCE
436 #define TARGET_FUNCTION_ARG_ADVANCE arm_function_arg_advance
437 #undef TARGET_FUNCTION_ARG_BOUNDARY
438 #define TARGET_FUNCTION_ARG_BOUNDARY arm_function_arg_boundary
440 #undef TARGET_SETUP_INCOMING_VARARGS
441 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
443 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
444 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS arm_allocate_stack_slots_for_args
446 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
447 #define TARGET_ASM_TRAMPOLINE_TEMPLATE arm_asm_trampoline_template
448 #undef TARGET_TRAMPOLINE_INIT
449 #define TARGET_TRAMPOLINE_INIT arm_trampoline_init
450 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
451 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS arm_trampoline_adjust_address
453 #undef TARGET_DEFAULT_SHORT_ENUMS
454 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
456 #undef TARGET_ALIGN_ANON_BITFIELD
457 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
459 #undef TARGET_NARROW_VOLATILE_BITFIELD
460 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
462 #undef TARGET_CXX_GUARD_TYPE
463 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
465 #undef TARGET_CXX_GUARD_MASK_BIT
466 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
468 #undef TARGET_CXX_GET_COOKIE_SIZE
469 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
471 #undef TARGET_CXX_COOKIE_HAS_SIZE
472 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
474 #undef TARGET_CXX_CDTOR_RETURNS_THIS
475 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
477 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
478 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
480 #undef TARGET_CXX_USE_AEABI_ATEXIT
481 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
483 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
484 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
485 arm_cxx_determine_class_data_visibility
487 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
488 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
490 #undef TARGET_RETURN_IN_MSB
491 #define TARGET_RETURN_IN_MSB arm_return_in_msb
493 #undef TARGET_RETURN_IN_MEMORY
494 #define TARGET_RETURN_IN_MEMORY arm_return_in_memory
496 #undef TARGET_MUST_PASS_IN_STACK
497 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
500 #undef TARGET_ASM_UNWIND_EMIT
501 #define TARGET_ASM_UNWIND_EMIT arm_unwind_emit
503 /* EABI unwinding tables use a different format for the typeinfo tables. */
504 #undef TARGET_ASM_TTYPE
505 #define TARGET_ASM_TTYPE arm_output_ttype
507 #undef TARGET_ARM_EABI_UNWINDER
508 #define TARGET_ARM_EABI_UNWINDER true
510 #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY
511 #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY arm_asm_emit_except_personality
513 #undef TARGET_ASM_INIT_SECTIONS
514 #define TARGET_ASM_INIT_SECTIONS arm_asm_init_sections
515 #endif /* ARM_UNWIND_INFO */
517 #undef TARGET_EXCEPT_UNWIND_INFO
518 #define TARGET_EXCEPT_UNWIND_INFO arm_except_unwind_info
520 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
521 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec
523 #undef TARGET_DWARF_REGISTER_SPAN
524 #define TARGET_DWARF_REGISTER_SPAN arm_dwarf_register_span
526 #undef TARGET_CANNOT_COPY_INSN_P
527 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
530 #undef TARGET_HAVE_TLS
531 #define TARGET_HAVE_TLS true
534 #undef TARGET_HAVE_CONDITIONAL_EXECUTION
535 #define TARGET_HAVE_CONDITIONAL_EXECUTION arm_have_conditional_execution
537 #undef TARGET_LEGITIMATE_CONSTANT_P
538 #define TARGET_LEGITIMATE_CONSTANT_P arm_legitimate_constant_p
540 #undef TARGET_CANNOT_FORCE_CONST_MEM
541 #define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem
543 #undef TARGET_MAX_ANCHOR_OFFSET
544 #define TARGET_MAX_ANCHOR_OFFSET 4095
546 /* The minimum is set such that the total size of the block
547 for a particular anchor is -4088 + 1 + 4095 bytes, which is
548 divisible by eight, ensuring natural spacing of anchors. */
549 #undef TARGET_MIN_ANCHOR_OFFSET
550 #define TARGET_MIN_ANCHOR_OFFSET -4088
552 #undef TARGET_SCHED_ISSUE_RATE
553 #define TARGET_SCHED_ISSUE_RATE arm_issue_rate
555 #undef TARGET_MANGLE_TYPE
556 #define TARGET_MANGLE_TYPE arm_mangle_type
558 #undef TARGET_BUILD_BUILTIN_VA_LIST
559 #define TARGET_BUILD_BUILTIN_VA_LIST arm_build_builtin_va_list
560 #undef TARGET_EXPAND_BUILTIN_VA_START
561 #define TARGET_EXPAND_BUILTIN_VA_START arm_expand_builtin_va_start
562 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
563 #define TARGET_GIMPLIFY_VA_ARG_EXPR arm_gimplify_va_arg_expr
566 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
567 #define TARGET_ASM_OUTPUT_DWARF_DTPREL arm_output_dwarf_dtprel
570 #undef TARGET_LEGITIMATE_ADDRESS_P
571 #define TARGET_LEGITIMATE_ADDRESS_P arm_legitimate_address_p
573 #undef TARGET_INVALID_PARAMETER_TYPE
574 #define TARGET_INVALID_PARAMETER_TYPE arm_invalid_parameter_type
576 #undef TARGET_INVALID_RETURN_TYPE
577 #define TARGET_INVALID_RETURN_TYPE arm_invalid_return_type
579 #undef TARGET_PROMOTED_TYPE
580 #define TARGET_PROMOTED_TYPE arm_promoted_type
582 #undef TARGET_CONVERT_TO_TYPE
583 #define TARGET_CONVERT_TO_TYPE arm_convert_to_type
585 #undef TARGET_SCALAR_MODE_SUPPORTED_P
586 #define TARGET_SCALAR_MODE_SUPPORTED_P arm_scalar_mode_supported_p
588 #undef TARGET_FRAME_POINTER_REQUIRED
589 #define TARGET_FRAME_POINTER_REQUIRED arm_frame_pointer_required
591 #undef TARGET_CAN_ELIMINATE
592 #define TARGET_CAN_ELIMINATE arm_can_eliminate
594 #undef TARGET_CONDITIONAL_REGISTER_USAGE
595 #define TARGET_CONDITIONAL_REGISTER_USAGE arm_conditional_register_usage
597 #undef TARGET_CLASS_LIKELY_SPILLED_P
598 #define TARGET_CLASS_LIKELY_SPILLED_P arm_class_likely_spilled_p
600 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
601 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
602 arm_vector_alignment_reachable
604 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
605 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
606 arm_builtin_support_vector_misalignment
608 #undef TARGET_PREFERRED_RENAME_CLASS
609 #define TARGET_PREFERRED_RENAME_CLASS \
610 arm_preferred_rename_class
612 struct gcc_target targetm
= TARGET_INITIALIZER
;
614 /* Obstack for minipool constant handling. */
615 static struct obstack minipool_obstack
;
616 static char * minipool_startobj
;
618 /* The maximum number of insns skipped which
619 will be conditionalised if possible. */
620 static int max_insns_skipped
= 5;
622 extern FILE * asm_out_file
;
624 /* True if we are currently building a constant table. */
625 int making_const_table
;
627 /* The processor for which instructions should be scheduled. */
628 enum processor_type arm_tune
= arm_none
;
630 /* The current tuning set. */
631 const struct tune_params
*current_tune
;
633 /* Which floating point hardware to schedule for. */
636 /* Which floating popint hardware to use. */
637 const struct arm_fpu_desc
*arm_fpu_desc
;
639 /* Used for Thumb call_via trampolines. */
640 rtx thumb_call_via_label
[14];
641 static int thumb_call_reg_needed
;
643 /* Bit values used to identify processor capabilities. */
644 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
645 #define FL_ARCH3M (1 << 1) /* Extended multiply */
646 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
647 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
648 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
649 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
650 #define FL_THUMB (1 << 6) /* Thumb aware */
651 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
652 #define FL_STRONG (1 << 8) /* StrongARM */
653 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
654 #define FL_XSCALE (1 << 10) /* XScale */
655 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
656 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
657 media instructions. */
658 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
659 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
660 Note: ARM6 & 7 derivatives only. */
661 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
662 #define FL_THUMB2 (1 << 16) /* Thumb-2. */
663 #define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
665 #define FL_DIV (1 << 18) /* Hardware divide. */
666 #define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */
667 #define FL_NEON (1 << 20) /* Neon instructions. */
668 #define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M
670 #define FL_ARCH7 (1 << 22) /* Architecture 7. */
672 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
674 /* Flags that only effect tuning, not available instructions. */
675 #define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
678 #define FL_FOR_ARCH2 FL_NOTM
679 #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
680 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
681 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
682 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
683 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
684 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
685 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
686 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
687 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
688 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
689 #define FL_FOR_ARCH6J FL_FOR_ARCH6
690 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
691 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
692 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
693 #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
694 #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
695 #define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
696 #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
697 #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV)
698 #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV)
699 #define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
701 /* The bits in this mask specify which
702 instructions we are allowed to generate. */
703 static unsigned long insn_flags
= 0;
705 /* The bits in this mask specify which instruction scheduling options should
707 static unsigned long tune_flags
= 0;
709 /* The following are used in the arm.md file as equivalents to bits
710 in the above two flag variables. */
712 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
715 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
718 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
721 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
724 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
727 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
730 /* Nonzero if this chip supports the ARM 6K extensions. */
733 /* Nonzero if this chip supports the ARM 7 extensions. */
736 /* Nonzero if instructions not present in the 'M' profile can be used. */
737 int arm_arch_notm
= 0;
739 /* Nonzero if instructions present in ARMv7E-M can be used. */
742 /* Nonzero if this chip can benefit from load scheduling. */
743 int arm_ld_sched
= 0;
745 /* Nonzero if this chip is a StrongARM. */
746 int arm_tune_strongarm
= 0;
748 /* Nonzero if this chip is a Cirrus variant. */
749 int arm_arch_cirrus
= 0;
751 /* Nonzero if this chip supports Intel Wireless MMX technology. */
752 int arm_arch_iwmmxt
= 0;
754 /* Nonzero if this chip is an XScale. */
755 int arm_arch_xscale
= 0;
757 /* Nonzero if tuning for XScale */
758 int arm_tune_xscale
= 0;
760 /* Nonzero if we want to tune for stores that access the write-buffer.
761 This typically means an ARM6 or ARM7 with MMU or MPU. */
762 int arm_tune_wbuf
= 0;
764 /* Nonzero if tuning for Cortex-A9. */
765 int arm_tune_cortex_a9
= 0;
767 /* Nonzero if generating Thumb instructions. */
770 /* Nonzero if generating Thumb-1 instructions. */
773 /* Nonzero if we should define __THUMB_INTERWORK__ in the
775 XXX This is a bit of a hack, it's intended to help work around
776 problems in GLD which doesn't understand that armv5t code is
777 interworking clean. */
778 int arm_cpp_interwork
= 0;
780 /* Nonzero if chip supports Thumb 2. */
783 /* Nonzero if chip supports integer division instruction. */
786 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference,
787 we must report the mode of the memory reference from
788 TARGET_PRINT_OPERAND to TARGET_PRINT_OPERAND_ADDRESS. */
789 enum machine_mode output_memory_reference_mode
;
791 /* The register number to be used for the PIC offset register. */
792 unsigned arm_pic_register
= INVALID_REGNUM
;
794 /* Set to 1 after arm_reorg has started. Reset to start at the start of
795 the next function. */
796 static int after_arm_reorg
= 0;
798 enum arm_pcs arm_pcs_default
;
800 /* For an explanation of these variables, see final_prescan_insn below. */
802 /* arm_current_cc is also used for Thumb-2 cond_exec blocks. */
803 enum arm_cond_code arm_current_cc
;
806 int arm_target_label
;
807 /* The number of conditionally executed insns, including the current insn. */
808 int arm_condexec_count
= 0;
809 /* A bitmask specifying the patterns for the IT block.
810 Zero means do not output an IT block before this insn. */
811 int arm_condexec_mask
= 0;
812 /* The number of bits used in arm_condexec_mask. */
813 int arm_condexec_masklen
= 0;
815 /* The condition codes of the ARM, and the inverse function. */
816 static const char * const arm_condition_codes
[] =
818 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
819 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
822 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */
823 int arm_regs_in_sequence
[] =
825 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
828 #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl")
829 #define streq(string1, string2) (strcmp (string1, string2) == 0)
831 #define THUMB2_WORK_REGS (0xff & ~( (1 << THUMB_HARD_FRAME_POINTER_REGNUM) \
832 | (1 << SP_REGNUM) | (1 << PC_REGNUM) \
833 | (1 << PIC_OFFSET_TABLE_REGNUM)))
835 /* Initialization code. */
839 const char *const name
;
840 enum processor_type core
;
842 const unsigned long flags
;
843 const struct tune_params
*const tune
;
847 #define ARM_PREFETCH_NOT_BENEFICIAL 0, -1, -1
848 #define ARM_PREFETCH_BENEFICIAL(prefetch_slots,l1_size,l1_line_size) \
853 const struct tune_params arm_slowmul_tune
=
855 arm_slowmul_rtx_costs
,
858 ARM_PREFETCH_NOT_BENEFICIAL
861 const struct tune_params arm_fastmul_tune
=
863 arm_fastmul_rtx_costs
,
866 ARM_PREFETCH_NOT_BENEFICIAL
869 const struct tune_params arm_xscale_tune
=
871 arm_xscale_rtx_costs
,
872 xscale_sched_adjust_cost
,
874 ARM_PREFETCH_NOT_BENEFICIAL
877 const struct tune_params arm_9e_tune
=
882 ARM_PREFETCH_NOT_BENEFICIAL
885 const struct tune_params arm_cortex_a9_tune
=
888 cortex_a9_sched_adjust_cost
,
890 ARM_PREFETCH_BENEFICIAL(4,32,32)
893 const struct tune_params arm_fa726te_tune
=
896 fa726te_sched_adjust_cost
,
898 ARM_PREFETCH_NOT_BENEFICIAL
902 /* Not all of these give usefully different compilation alternatives,
903 but there is no simple way of generalizing them. */
904 static const struct processors all_cores
[] =
907 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
908 {NAME, IDENT, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, &arm_##COSTS##_tune},
909 #include "arm-cores.def"
911 {NULL
, arm_none
, NULL
, 0, NULL
}
914 static const struct processors all_architectures
[] =
916 /* ARM Architectures */
917 /* We don't specify tuning costs here as it will be figured out
920 #define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \
921 {NAME, CORE, #ARCH, FLAGS, NULL},
922 #include "arm-arches.def"
924 {NULL
, arm_none
, NULL
, 0 , NULL
}
928 /* These are populated as commandline arguments are processed, or NULL
930 static const struct processors
*arm_selected_arch
;
931 static const struct processors
*arm_selected_cpu
;
932 static const struct processors
*arm_selected_tune
;
934 /* The name of the preprocessor macro to define for this architecture. */
936 char arm_arch_name
[] = "__ARM_ARCH_0UNK__";
938 /* Available values for -mfpu=. */
940 static const struct arm_fpu_desc all_fpus
[] =
942 #define ARM_FPU(NAME, MODEL, REV, VFP_REGS, NEON, FP16) \
943 { NAME, MODEL, REV, VFP_REGS, NEON, FP16 },
944 #include "arm-fpus.def"
949 /* Supported TLS relocations. */
959 /* The maximum number of insns to be used when loading a constant. */
961 arm_constant_limit (bool size_p
)
963 return size_p
? 1 : current_tune
->constant_limit
;
966 /* Emit an insn that's a simple single-set. Both the operands must be known
969 emit_set_insn (rtx x
, rtx y
)
971 return emit_insn (gen_rtx_SET (VOIDmode
, x
, y
));
974 /* Return the number of bits set in VALUE. */
976 bit_count (unsigned long value
)
978 unsigned long count
= 0;
983 value
&= value
- 1; /* Clear the least-significant set bit. */
989 /* Set up library functions unique to ARM. */
992 arm_init_libfuncs (void)
994 /* There are no special library functions unless we are using the
999 /* The functions below are described in Section 4 of the "Run-Time
1000 ABI for the ARM architecture", Version 1.0. */
1002 /* Double-precision floating-point arithmetic. Table 2. */
1003 set_optab_libfunc (add_optab
, DFmode
, "__aeabi_dadd");
1004 set_optab_libfunc (sdiv_optab
, DFmode
, "__aeabi_ddiv");
1005 set_optab_libfunc (smul_optab
, DFmode
, "__aeabi_dmul");
1006 set_optab_libfunc (neg_optab
, DFmode
, "__aeabi_dneg");
1007 set_optab_libfunc (sub_optab
, DFmode
, "__aeabi_dsub");
1009 /* Double-precision comparisons. Table 3. */
1010 set_optab_libfunc (eq_optab
, DFmode
, "__aeabi_dcmpeq");
1011 set_optab_libfunc (ne_optab
, DFmode
, NULL
);
1012 set_optab_libfunc (lt_optab
, DFmode
, "__aeabi_dcmplt");
1013 set_optab_libfunc (le_optab
, DFmode
, "__aeabi_dcmple");
1014 set_optab_libfunc (ge_optab
, DFmode
, "__aeabi_dcmpge");
1015 set_optab_libfunc (gt_optab
, DFmode
, "__aeabi_dcmpgt");
1016 set_optab_libfunc (unord_optab
, DFmode
, "__aeabi_dcmpun");
1018 /* Single-precision floating-point arithmetic. Table 4. */
1019 set_optab_libfunc (add_optab
, SFmode
, "__aeabi_fadd");
1020 set_optab_libfunc (sdiv_optab
, SFmode
, "__aeabi_fdiv");
1021 set_optab_libfunc (smul_optab
, SFmode
, "__aeabi_fmul");
1022 set_optab_libfunc (neg_optab
, SFmode
, "__aeabi_fneg");
1023 set_optab_libfunc (sub_optab
, SFmode
, "__aeabi_fsub");
1025 /* Single-precision comparisons. Table 5. */
1026 set_optab_libfunc (eq_optab
, SFmode
, "__aeabi_fcmpeq");
1027 set_optab_libfunc (ne_optab
, SFmode
, NULL
);
1028 set_optab_libfunc (lt_optab
, SFmode
, "__aeabi_fcmplt");
1029 set_optab_libfunc (le_optab
, SFmode
, "__aeabi_fcmple");
1030 set_optab_libfunc (ge_optab
, SFmode
, "__aeabi_fcmpge");
1031 set_optab_libfunc (gt_optab
, SFmode
, "__aeabi_fcmpgt");
1032 set_optab_libfunc (unord_optab
, SFmode
, "__aeabi_fcmpun");
1034 /* Floating-point to integer conversions. Table 6. */
1035 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__aeabi_d2iz");
1036 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__aeabi_d2uiz");
1037 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__aeabi_d2lz");
1038 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__aeabi_d2ulz");
1039 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__aeabi_f2iz");
1040 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__aeabi_f2uiz");
1041 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__aeabi_f2lz");
1042 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__aeabi_f2ulz");
1044 /* Conversions between floating types. Table 7. */
1045 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__aeabi_d2f");
1046 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__aeabi_f2d");
1048 /* Integer to floating-point conversions. Table 8. */
1049 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__aeabi_i2d");
1050 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
, "__aeabi_ui2d");
1051 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__aeabi_l2d");
1052 set_conv_libfunc (ufloat_optab
, DFmode
, DImode
, "__aeabi_ul2d");
1053 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__aeabi_i2f");
1054 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__aeabi_ui2f");
1055 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__aeabi_l2f");
1056 set_conv_libfunc (ufloat_optab
, SFmode
, DImode
, "__aeabi_ul2f");
1058 /* Long long. Table 9. */
1059 set_optab_libfunc (smul_optab
, DImode
, "__aeabi_lmul");
1060 set_optab_libfunc (sdivmod_optab
, DImode
, "__aeabi_ldivmod");
1061 set_optab_libfunc (udivmod_optab
, DImode
, "__aeabi_uldivmod");
1062 set_optab_libfunc (ashl_optab
, DImode
, "__aeabi_llsl");
1063 set_optab_libfunc (lshr_optab
, DImode
, "__aeabi_llsr");
1064 set_optab_libfunc (ashr_optab
, DImode
, "__aeabi_lasr");
1065 set_optab_libfunc (cmp_optab
, DImode
, "__aeabi_lcmp");
1066 set_optab_libfunc (ucmp_optab
, DImode
, "__aeabi_ulcmp");
1068 /* Integer (32/32->32) division. \S 4.3.1. */
1069 set_optab_libfunc (sdivmod_optab
, SImode
, "__aeabi_idivmod");
1070 set_optab_libfunc (udivmod_optab
, SImode
, "__aeabi_uidivmod");
1072 /* The divmod functions are designed so that they can be used for
1073 plain division, even though they return both the quotient and the
1074 remainder. The quotient is returned in the usual location (i.e.,
1075 r0 for SImode, {r0, r1} for DImode), just as would be expected
1076 for an ordinary division routine. Because the AAPCS calling
1077 conventions specify that all of { r0, r1, r2, r3 } are
1078 callee-saved registers, there is no need to tell the compiler
1079 explicitly that those registers are clobbered by these
1081 set_optab_libfunc (sdiv_optab
, DImode
, "__aeabi_ldivmod");
1082 set_optab_libfunc (udiv_optab
, DImode
, "__aeabi_uldivmod");
1084 /* For SImode division the ABI provides div-without-mod routines,
1085 which are faster. */
1086 set_optab_libfunc (sdiv_optab
, SImode
, "__aeabi_idiv");
1087 set_optab_libfunc (udiv_optab
, SImode
, "__aeabi_uidiv");
1089 /* We don't have mod libcalls. Fortunately gcc knows how to use the
1090 divmod libcalls instead. */
1091 set_optab_libfunc (smod_optab
, DImode
, NULL
);
1092 set_optab_libfunc (umod_optab
, DImode
, NULL
);
1093 set_optab_libfunc (smod_optab
, SImode
, NULL
);
1094 set_optab_libfunc (umod_optab
, SImode
, NULL
);
1096 /* Half-precision float operations. The compiler handles all operations
1097 with NULL libfuncs by converting the SFmode. */
1098 switch (arm_fp16_format
)
1100 case ARM_FP16_FORMAT_IEEE
:
1101 case ARM_FP16_FORMAT_ALTERNATIVE
:
1104 set_conv_libfunc (trunc_optab
, HFmode
, SFmode
,
1105 (arm_fp16_format
== ARM_FP16_FORMAT_IEEE
1107 : "__gnu_f2h_alternative"));
1108 set_conv_libfunc (sext_optab
, SFmode
, HFmode
,
1109 (arm_fp16_format
== ARM_FP16_FORMAT_IEEE
1111 : "__gnu_h2f_alternative"));
1114 set_optab_libfunc (add_optab
, HFmode
, NULL
);
1115 set_optab_libfunc (sdiv_optab
, HFmode
, NULL
);
1116 set_optab_libfunc (smul_optab
, HFmode
, NULL
);
1117 set_optab_libfunc (neg_optab
, HFmode
, NULL
);
1118 set_optab_libfunc (sub_optab
, HFmode
, NULL
);
1121 set_optab_libfunc (eq_optab
, HFmode
, NULL
);
1122 set_optab_libfunc (ne_optab
, HFmode
, NULL
);
1123 set_optab_libfunc (lt_optab
, HFmode
, NULL
);
1124 set_optab_libfunc (le_optab
, HFmode
, NULL
);
1125 set_optab_libfunc (ge_optab
, HFmode
, NULL
);
1126 set_optab_libfunc (gt_optab
, HFmode
, NULL
);
1127 set_optab_libfunc (unord_optab
, HFmode
, NULL
);
1134 if (TARGET_AAPCS_BASED
)
1135 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
1138 /* On AAPCS systems, this is the "struct __va_list". */
1139 static GTY(()) tree va_list_type
;
1141 /* Return the type to use as __builtin_va_list. */
1143 arm_build_builtin_va_list (void)
1148 if (!TARGET_AAPCS_BASED
)
1149 return std_build_builtin_va_list ();
1151 /* AAPCS \S 7.1.4 requires that va_list be a typedef for a type
1159 The C Library ABI further reinforces this definition in \S
1162 We must follow this definition exactly. The structure tag
1163 name is visible in C++ mangled names, and thus forms a part
1164 of the ABI. The field name may be used by people who
1165 #include <stdarg.h>. */
1166 /* Create the type. */
1167 va_list_type
= lang_hooks
.types
.make_type (RECORD_TYPE
);
1168 /* Give it the required name. */
1169 va_list_name
= build_decl (BUILTINS_LOCATION
,
1171 get_identifier ("__va_list"),
1173 DECL_ARTIFICIAL (va_list_name
) = 1;
1174 TYPE_NAME (va_list_type
) = va_list_name
;
1175 TYPE_STUB_DECL (va_list_type
) = va_list_name
;
1176 /* Create the __ap field. */
1177 ap_field
= build_decl (BUILTINS_LOCATION
,
1179 get_identifier ("__ap"),
1181 DECL_ARTIFICIAL (ap_field
) = 1;
1182 DECL_FIELD_CONTEXT (ap_field
) = va_list_type
;
1183 TYPE_FIELDS (va_list_type
) = ap_field
;
1184 /* Compute its layout. */
1185 layout_type (va_list_type
);
1187 return va_list_type
;
1190 /* Return an expression of type "void *" pointing to the next
1191 available argument in a variable-argument list. VALIST is the
1192 user-level va_list object, of type __builtin_va_list. */
1194 arm_extract_valist_ptr (tree valist
)
1196 if (TREE_TYPE (valist
) == error_mark_node
)
1197 return error_mark_node
;
1199 /* On an AAPCS target, the pointer is stored within "struct
1201 if (TARGET_AAPCS_BASED
)
1203 tree ap_field
= TYPE_FIELDS (TREE_TYPE (valist
));
1204 valist
= build3 (COMPONENT_REF
, TREE_TYPE (ap_field
),
1205 valist
, ap_field
, NULL_TREE
);
1211 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
1213 arm_expand_builtin_va_start (tree valist
, rtx nextarg
)
1215 valist
= arm_extract_valist_ptr (valist
);
1216 std_expand_builtin_va_start (valist
, nextarg
);
1219 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
1221 arm_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
1224 valist
= arm_extract_valist_ptr (valist
);
1225 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
1228 /* Fix up any incompatible options that the user has specified. */
1230 arm_option_override (void)
1232 if (global_options_set
.x_arm_arch_option
)
1233 arm_selected_arch
= &all_architectures
[arm_arch_option
];
1235 if (global_options_set
.x_arm_cpu_option
)
1236 arm_selected_cpu
= &all_cores
[(int) arm_cpu_option
];
1238 if (global_options_set
.x_arm_tune_option
)
1239 arm_selected_tune
= &all_cores
[(int) arm_tune_option
];
1241 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1242 SUBTARGET_OVERRIDE_OPTIONS
;
1245 if (arm_selected_arch
)
1247 if (arm_selected_cpu
)
1249 /* Check for conflict between mcpu and march. */
1250 if ((arm_selected_cpu
->flags
^ arm_selected_arch
->flags
) & ~FL_TUNE
)
1252 warning (0, "switch -mcpu=%s conflicts with -march=%s switch",
1253 arm_selected_cpu
->name
, arm_selected_arch
->name
);
1254 /* -march wins for code generation.
1255 -mcpu wins for default tuning. */
1256 if (!arm_selected_tune
)
1257 arm_selected_tune
= arm_selected_cpu
;
1259 arm_selected_cpu
= arm_selected_arch
;
1263 arm_selected_arch
= NULL
;
1266 /* Pick a CPU based on the architecture. */
1267 arm_selected_cpu
= arm_selected_arch
;
1270 /* If the user did not specify a processor, choose one for them. */
1271 if (!arm_selected_cpu
)
1273 const struct processors
* sel
;
1274 unsigned int sought
;
1276 arm_selected_cpu
= &all_cores
[TARGET_CPU_DEFAULT
];
1277 if (!arm_selected_cpu
->name
)
1279 #ifdef SUBTARGET_CPU_DEFAULT
1280 /* Use the subtarget default CPU if none was specified by
1282 arm_selected_cpu
= &all_cores
[SUBTARGET_CPU_DEFAULT
];
1284 /* Default to ARM6. */
1285 if (!arm_selected_cpu
->name
)
1286 arm_selected_cpu
= &all_cores
[arm6
];
1289 sel
= arm_selected_cpu
;
1290 insn_flags
= sel
->flags
;
1292 /* Now check to see if the user has specified some command line
1293 switch that require certain abilities from the cpu. */
1296 if (TARGET_INTERWORK
|| TARGET_THUMB
)
1298 sought
|= (FL_THUMB
| FL_MODE32
);
1300 /* There are no ARM processors that support both APCS-26 and
1301 interworking. Therefore we force FL_MODE26 to be removed
1302 from insn_flags here (if it was set), so that the search
1303 below will always be able to find a compatible processor. */
1304 insn_flags
&= ~FL_MODE26
;
1307 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
1309 /* Try to locate a CPU type that supports all of the abilities
1310 of the default CPU, plus the extra abilities requested by
1312 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
1313 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
1316 if (sel
->name
== NULL
)
1318 unsigned current_bit_count
= 0;
1319 const struct processors
* best_fit
= NULL
;
1321 /* Ideally we would like to issue an error message here
1322 saying that it was not possible to find a CPU compatible
1323 with the default CPU, but which also supports the command
1324 line options specified by the programmer, and so they
1325 ought to use the -mcpu=<name> command line option to
1326 override the default CPU type.
1328 If we cannot find a cpu that has both the
1329 characteristics of the default cpu and the given
1330 command line options we scan the array again looking
1331 for a best match. */
1332 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
1333 if ((sel
->flags
& sought
) == sought
)
1337 count
= bit_count (sel
->flags
& insn_flags
);
1339 if (count
>= current_bit_count
)
1342 current_bit_count
= count
;
1346 gcc_assert (best_fit
);
1350 arm_selected_cpu
= sel
;
1354 gcc_assert (arm_selected_cpu
);
1355 /* The selected cpu may be an architecture, so lookup tuning by core ID. */
1356 if (!arm_selected_tune
)
1357 arm_selected_tune
= &all_cores
[arm_selected_cpu
->core
];
1359 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", arm_selected_cpu
->arch
);
1360 insn_flags
= arm_selected_cpu
->flags
;
1362 arm_tune
= arm_selected_tune
->core
;
1363 tune_flags
= arm_selected_tune
->flags
;
1364 current_tune
= arm_selected_tune
->tune
;
1366 /* Make sure that the processor choice does not conflict with any of the
1367 other command line choices. */
1368 if (TARGET_ARM
&& !(insn_flags
& FL_NOTM
))
1369 error ("target CPU does not support ARM mode");
1371 /* BPABI targets use linker tricks to allow interworking on cores
1372 without thumb support. */
1373 if (TARGET_INTERWORK
&& !((insn_flags
& FL_THUMB
) || TARGET_BPABI
))
1375 warning (0, "target CPU does not support interworking" );
1376 target_flags
&= ~MASK_INTERWORK
;
1379 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
1381 warning (0, "target CPU does not support THUMB instructions");
1382 target_flags
&= ~MASK_THUMB
;
1385 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
1387 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1388 target_flags
&= ~MASK_APCS_FRAME
;
1391 /* Callee super interworking implies thumb interworking. Adding
1392 this to the flags here simplifies the logic elsewhere. */
1393 if (TARGET_THUMB
&& TARGET_CALLEE_INTERWORKING
)
1394 target_flags
|= MASK_INTERWORK
;
1396 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1397 from here where no function is being compiled currently. */
1398 if ((TARGET_TPCS_FRAME
|| TARGET_TPCS_LEAF_FRAME
) && TARGET_ARM
)
1399 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1401 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
1402 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1404 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
1406 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1407 target_flags
|= MASK_APCS_FRAME
;
1410 if (TARGET_POKE_FUNCTION_NAME
)
1411 target_flags
|= MASK_APCS_FRAME
;
1413 if (TARGET_APCS_REENT
&& flag_pic
)
1414 error ("-fpic and -mapcs-reent are incompatible");
1416 if (TARGET_APCS_REENT
)
1417 warning (0, "APCS reentrant code not supported. Ignored");
1419 /* If this target is normally configured to use APCS frames, warn if they
1420 are turned off and debugging is turned on. */
1422 && write_symbols
!= NO_DEBUG
1423 && !TARGET_APCS_FRAME
1424 && (TARGET_DEFAULT
& MASK_APCS_FRAME
))
1425 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1427 if (TARGET_APCS_FLOAT
)
1428 warning (0, "passing floating point arguments in fp regs not yet supported");
1430 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1431 arm_arch3m
= (insn_flags
& FL_ARCH3M
) != 0;
1432 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
1433 arm_arch4t
= arm_arch4
& ((insn_flags
& FL_THUMB
) != 0);
1434 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
1435 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
1436 arm_arch6
= (insn_flags
& FL_ARCH6
) != 0;
1437 arm_arch6k
= (insn_flags
& FL_ARCH6K
) != 0;
1438 arm_arch_notm
= (insn_flags
& FL_NOTM
) != 0;
1439 arm_arch7
= (insn_flags
& FL_ARCH7
) != 0;
1440 arm_arch7em
= (insn_flags
& FL_ARCH7EM
) != 0;
1441 arm_arch_thumb2
= (insn_flags
& FL_THUMB2
) != 0;
1442 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
1443 arm_arch_cirrus
= (insn_flags
& FL_CIRRUS
) != 0;
1445 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
1446 arm_tune_strongarm
= (tune_flags
& FL_STRONG
) != 0;
1447 thumb_code
= TARGET_ARM
== 0;
1448 thumb1_code
= TARGET_THUMB1
!= 0;
1449 arm_tune_wbuf
= (tune_flags
& FL_WBUF
) != 0;
1450 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
1451 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
1452 arm_arch_hwdiv
= (insn_flags
& FL_DIV
) != 0;
1453 arm_tune_cortex_a9
= (arm_tune
== cortexa9
) != 0;
1455 /* If we are not using the default (ARM mode) section anchor offset
1456 ranges, then set the correct ranges now. */
1459 /* Thumb-1 LDR instructions cannot have negative offsets.
1460 Permissible positive offset ranges are 5-bit (for byte loads),
1461 6-bit (for halfword loads), or 7-bit (for word loads).
1462 Empirical results suggest a 7-bit anchor range gives the best
1463 overall code size. */
1464 targetm
.min_anchor_offset
= 0;
1465 targetm
.max_anchor_offset
= 127;
1467 else if (TARGET_THUMB2
)
1469 /* The minimum is set such that the total size of the block
1470 for a particular anchor is 248 + 1 + 4095 bytes, which is
1471 divisible by eight, ensuring natural spacing of anchors. */
1472 targetm
.min_anchor_offset
= -248;
1473 targetm
.max_anchor_offset
= 4095;
1476 /* V5 code we generate is completely interworking capable, so we turn off
1477 TARGET_INTERWORK here to avoid many tests later on. */
1479 /* XXX However, we must pass the right pre-processor defines to CPP
1480 or GLD can get confused. This is a hack. */
1481 if (TARGET_INTERWORK
)
1482 arm_cpp_interwork
= 1;
1485 target_flags
&= ~MASK_INTERWORK
;
1487 if (TARGET_IWMMXT
&& !ARM_DOUBLEWORD_ALIGN
)
1488 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1490 if (TARGET_IWMMXT_ABI
&& !TARGET_IWMMXT
)
1491 error ("iwmmxt abi requires an iwmmxt capable cpu");
1493 if (!global_options_set
.x_arm_fpu_index
)
1495 const char *target_fpu_name
;
1498 #ifdef FPUTYPE_DEFAULT
1499 target_fpu_name
= FPUTYPE_DEFAULT
;
1501 if (arm_arch_cirrus
)
1502 target_fpu_name
= "maverick";
1504 target_fpu_name
= "fpe2";
1507 ok
= opt_enum_arg_to_value (OPT_mfpu_
, target_fpu_name
, &arm_fpu_index
,
1512 arm_fpu_desc
= &all_fpus
[arm_fpu_index
];
1514 switch (arm_fpu_desc
->model
)
1516 case ARM_FP_MODEL_FPA
:
1517 if (arm_fpu_desc
->rev
== 2)
1518 arm_fpu_attr
= FPU_FPE2
;
1519 else if (arm_fpu_desc
->rev
== 3)
1520 arm_fpu_attr
= FPU_FPE3
;
1522 arm_fpu_attr
= FPU_FPA
;
1525 case ARM_FP_MODEL_MAVERICK
:
1526 arm_fpu_attr
= FPU_MAVERICK
;
1529 case ARM_FP_MODEL_VFP
:
1530 arm_fpu_attr
= FPU_VFP
;
1537 if (TARGET_AAPCS_BASED
1538 && (arm_fpu_desc
->model
== ARM_FP_MODEL_FPA
))
1539 error ("FPA is unsupported in the AAPCS");
1541 if (TARGET_AAPCS_BASED
)
1543 if (TARGET_CALLER_INTERWORKING
)
1544 error ("AAPCS does not support -mcaller-super-interworking");
1546 if (TARGET_CALLEE_INTERWORKING
)
1547 error ("AAPCS does not support -mcallee-super-interworking");
1550 /* FPA and iWMMXt are incompatible because the insn encodings overlap.
1551 VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon
1552 will ever exist. GCC makes no attempt to support this combination. */
1553 if (TARGET_IWMMXT
&& !TARGET_SOFT_FLOAT
)
1554 sorry ("iWMMXt and hardware floating point");
1556 /* ??? iWMMXt insn patterns need auditing for Thumb-2. */
1557 if (TARGET_THUMB2
&& TARGET_IWMMXT
)
1558 sorry ("Thumb-2 iWMMXt");
1560 /* __fp16 support currently assumes the core has ldrh. */
1561 if (!arm_arch4
&& arm_fp16_format
!= ARM_FP16_FORMAT_NONE
)
1562 sorry ("__fp16 and no ldrh");
1564 /* If soft-float is specified then don't use FPU. */
1565 if (TARGET_SOFT_FLOAT
)
1566 arm_fpu_attr
= FPU_NONE
;
1568 if (TARGET_AAPCS_BASED
)
1570 if (arm_abi
== ARM_ABI_IWMMXT
)
1571 arm_pcs_default
= ARM_PCS_AAPCS_IWMMXT
;
1572 else if (arm_float_abi
== ARM_FLOAT_ABI_HARD
1573 && TARGET_HARD_FLOAT
1575 arm_pcs_default
= ARM_PCS_AAPCS_VFP
;
1577 arm_pcs_default
= ARM_PCS_AAPCS
;
1581 if (arm_float_abi
== ARM_FLOAT_ABI_HARD
&& TARGET_VFP
)
1582 sorry ("-mfloat-abi=hard and VFP");
1584 if (arm_abi
== ARM_ABI_APCS
)
1585 arm_pcs_default
= ARM_PCS_APCS
;
1587 arm_pcs_default
= ARM_PCS_ATPCS
;
1590 /* For arm2/3 there is no need to do any scheduling if there is only
1591 a floating point emulator, or we are doing software floating-point. */
1592 if ((TARGET_SOFT_FLOAT
1593 || (TARGET_FPA
&& arm_fpu_desc
->rev
))
1594 && (tune_flags
& FL_MODE32
) == 0)
1595 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
1597 /* Use the cp15 method if it is available. */
1598 if (target_thread_pointer
== TP_AUTO
)
1600 if (arm_arch6k
&& !TARGET_THUMB1
)
1601 target_thread_pointer
= TP_CP15
;
1603 target_thread_pointer
= TP_SOFT
;
1606 if (TARGET_HARD_TP
&& TARGET_THUMB1
)
1607 error ("can not use -mtp=cp15 with 16-bit Thumb");
1609 /* Override the default structure alignment for AAPCS ABI. */
1610 if (!global_options_set
.x_arm_structure_size_boundary
)
1612 if (TARGET_AAPCS_BASED
)
1613 arm_structure_size_boundary
= 8;
1617 if (arm_structure_size_boundary
!= 8
1618 && arm_structure_size_boundary
!= 32
1619 && !(ARM_DOUBLEWORD_ALIGN
&& arm_structure_size_boundary
== 64))
1621 if (ARM_DOUBLEWORD_ALIGN
)
1623 "structure size boundary can only be set to 8, 32 or 64");
1625 warning (0, "structure size boundary can only be set to 8 or 32");
1626 arm_structure_size_boundary
1627 = (TARGET_AAPCS_BASED
? 8 : DEFAULT_STRUCTURE_SIZE_BOUNDARY
);
1631 if (!TARGET_ARM
&& TARGET_VXWORKS_RTP
&& flag_pic
)
1633 error ("RTP PIC is incompatible with Thumb");
1637 /* If stack checking is disabled, we can use r10 as the PIC register,
1638 which keeps r9 available. The EABI specifies r9 as the PIC register. */
1639 if (flag_pic
&& TARGET_SINGLE_PIC_BASE
)
1641 if (TARGET_VXWORKS_RTP
)
1642 warning (0, "RTP PIC is incompatible with -msingle-pic-base");
1643 arm_pic_register
= (TARGET_APCS_STACK
|| TARGET_AAPCS_BASED
) ? 9 : 10;
1646 if (flag_pic
&& TARGET_VXWORKS_RTP
)
1647 arm_pic_register
= 9;
1649 if (arm_pic_register_string
!= NULL
)
1651 int pic_register
= decode_reg_name (arm_pic_register_string
);
1654 warning (0, "-mpic-register= is useless without -fpic");
1656 /* Prevent the user from choosing an obviously stupid PIC register. */
1657 else if (pic_register
< 0 || call_used_regs
[pic_register
]
1658 || pic_register
== HARD_FRAME_POINTER_REGNUM
1659 || pic_register
== STACK_POINTER_REGNUM
1660 || pic_register
>= PC_REGNUM
1661 || (TARGET_VXWORKS_RTP
1662 && (unsigned int) pic_register
!= arm_pic_register
))
1663 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
1665 arm_pic_register
= pic_register
;
1668 /* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */
1669 if (fix_cm3_ldrd
== 2)
1671 if (arm_selected_cpu
->core
== cortexm3
)
1677 if (TARGET_THUMB1
&& flag_schedule_insns
)
1679 /* Don't warn since it's on by default in -O2. */
1680 flag_schedule_insns
= 0;
1685 /* If optimizing for size, bump the number of instructions that we
1686 are prepared to conditionally execute (even on a StrongARM). */
1687 max_insns_skipped
= 6;
1691 /* StrongARM has early execution of branches, so a sequence
1692 that is worth skipping is shorter. */
1693 if (arm_tune_strongarm
)
1694 max_insns_skipped
= 3;
1697 /* Hot/Cold partitioning is not currently supported, since we can't
1698 handle literal pool placement in that case. */
1699 if (flag_reorder_blocks_and_partition
)
1701 inform (input_location
,
1702 "-freorder-blocks-and-partition not supported on this architecture");
1703 flag_reorder_blocks_and_partition
= 0;
1704 flag_reorder_blocks
= 1;
1708 /* Hoisting PIC address calculations more aggressively provides a small,
1709 but measurable, size reduction for PIC code. Therefore, we decrease
1710 the bar for unrestricted expression hoisting to the cost of PIC address
1711 calculation, which is 2 instructions. */
1712 maybe_set_param_value (PARAM_GCSE_UNRESTRICTED_COST
, 2,
1713 global_options
.x_param_values
,
1714 global_options_set
.x_param_values
);
1716 /* ARM EABI defaults to strict volatile bitfields. */
1717 if (TARGET_AAPCS_BASED
&& flag_strict_volatile_bitfields
< 0)
1718 flag_strict_volatile_bitfields
= 1;
1720 /* Enable sw prefetching at -O3 for CPUS that have prefetch, and we have deemed
1721 it beneficial (signified by setting num_prefetch_slots to 1 or more.) */
1722 if (flag_prefetch_loop_arrays
< 0
1725 && current_tune
->num_prefetch_slots
> 0)
1726 flag_prefetch_loop_arrays
= 1;
1728 /* Set up parameters to be used in prefetching algorithm. Do not override the
1729 defaults unless we are tuning for a core we have researched values for. */
1730 if (current_tune
->num_prefetch_slots
> 0)
1731 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
1732 current_tune
->num_prefetch_slots
,
1733 global_options
.x_param_values
,
1734 global_options_set
.x_param_values
);
1735 if (current_tune
->l1_cache_line_size
>= 0)
1736 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
1737 current_tune
->l1_cache_line_size
,
1738 global_options
.x_param_values
,
1739 global_options_set
.x_param_values
);
1740 if (current_tune
->l1_cache_size
>= 0)
1741 maybe_set_param_value (PARAM_L1_CACHE_SIZE
,
1742 current_tune
->l1_cache_size
,
1743 global_options
.x_param_values
,
1744 global_options_set
.x_param_values
);
1746 /* Register global variables with the garbage collector. */
1747 arm_add_gc_roots ();
1751 arm_add_gc_roots (void)
1753 gcc_obstack_init(&minipool_obstack
);
1754 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
1757 /* A table of known ARM exception types.
1758 For use with the interrupt function attribute. */
1762 const char *const arg
;
1763 const unsigned long return_value
;
1767 static const isr_attribute_arg isr_attribute_args
[] =
1769 { "IRQ", ARM_FT_ISR
},
1770 { "irq", ARM_FT_ISR
},
1771 { "FIQ", ARM_FT_FIQ
},
1772 { "fiq", ARM_FT_FIQ
},
1773 { "ABORT", ARM_FT_ISR
},
1774 { "abort", ARM_FT_ISR
},
1775 { "ABORT", ARM_FT_ISR
},
1776 { "abort", ARM_FT_ISR
},
1777 { "UNDEF", ARM_FT_EXCEPTION
},
1778 { "undef", ARM_FT_EXCEPTION
},
1779 { "SWI", ARM_FT_EXCEPTION
},
1780 { "swi", ARM_FT_EXCEPTION
},
1781 { NULL
, ARM_FT_NORMAL
}
1784 /* Returns the (interrupt) function type of the current
1785 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1787 static unsigned long
1788 arm_isr_value (tree argument
)
1790 const isr_attribute_arg
* ptr
;
1794 return ARM_FT_NORMAL
| ARM_FT_STACKALIGN
;
1796 /* No argument - default to IRQ. */
1797 if (argument
== NULL_TREE
)
1800 /* Get the value of the argument. */
1801 if (TREE_VALUE (argument
) == NULL_TREE
1802 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
1803 return ARM_FT_UNKNOWN
;
1805 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
1807 /* Check it against the list of known arguments. */
1808 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
1809 if (streq (arg
, ptr
->arg
))
1810 return ptr
->return_value
;
1812 /* An unrecognized interrupt type. */
1813 return ARM_FT_UNKNOWN
;
1816 /* Computes the type of the current function. */
1818 static unsigned long
1819 arm_compute_func_type (void)
1821 unsigned long type
= ARM_FT_UNKNOWN
;
1825 gcc_assert (TREE_CODE (current_function_decl
) == FUNCTION_DECL
);
1827 /* Decide if the current function is volatile. Such functions
1828 never return, and many memory cycles can be saved by not storing
1829 register values that will never be needed again. This optimization
1830 was added to speed up context switching in a kernel application. */
1832 && (TREE_NOTHROW (current_function_decl
)
1833 || !(flag_unwind_tables
1835 && arm_except_unwind_info (&global_options
) != UI_SJLJ
)))
1836 && TREE_THIS_VOLATILE (current_function_decl
))
1837 type
|= ARM_FT_VOLATILE
;
1839 if (cfun
->static_chain_decl
!= NULL
)
1840 type
|= ARM_FT_NESTED
;
1842 attr
= DECL_ATTRIBUTES (current_function_decl
);
1844 a
= lookup_attribute ("naked", attr
);
1846 type
|= ARM_FT_NAKED
;
1848 a
= lookup_attribute ("isr", attr
);
1850 a
= lookup_attribute ("interrupt", attr
);
1853 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
1855 type
|= arm_isr_value (TREE_VALUE (a
));
1860 /* Returns the type of the current function. */
1863 arm_current_func_type (void)
1865 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
1866 cfun
->machine
->func_type
= arm_compute_func_type ();
1868 return cfun
->machine
->func_type
;
1872 arm_allocate_stack_slots_for_args (void)
1874 /* Naked functions should not allocate stack slots for arguments. */
1875 return !IS_NAKED (arm_current_func_type ());
1879 /* Output assembler code for a block containing the constant parts
1880 of a trampoline, leaving space for the variable parts.
1882 On the ARM, (if r8 is the static chain regnum, and remembering that
1883 referencing pc adds an offset of 8) the trampoline looks like:
1886 .word static chain value
1887 .word function's address
1888 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1891 arm_asm_trampoline_template (FILE *f
)
1895 asm_fprintf (f
, "\tldr\t%r, [%r, #0]\n", STATIC_CHAIN_REGNUM
, PC_REGNUM
);
1896 asm_fprintf (f
, "\tldr\t%r, [%r, #0]\n", PC_REGNUM
, PC_REGNUM
);
1898 else if (TARGET_THUMB2
)
1900 /* The Thumb-2 trampoline is similar to the arm implementation.
1901 Unlike 16-bit Thumb, we enter the stub in thumb mode. */
1902 asm_fprintf (f
, "\tldr.w\t%r, [%r, #4]\n",
1903 STATIC_CHAIN_REGNUM
, PC_REGNUM
);
1904 asm_fprintf (f
, "\tldr.w\t%r, [%r, #4]\n", PC_REGNUM
, PC_REGNUM
);
1908 ASM_OUTPUT_ALIGN (f
, 2);
1909 fprintf (f
, "\t.code\t16\n");
1910 fprintf (f
, ".Ltrampoline_start:\n");
1911 asm_fprintf (f
, "\tpush\t{r0, r1}\n");
1912 asm_fprintf (f
, "\tldr\tr0, [%r, #8]\n", PC_REGNUM
);
1913 asm_fprintf (f
, "\tmov\t%r, r0\n", STATIC_CHAIN_REGNUM
);
1914 asm_fprintf (f
, "\tldr\tr0, [%r, #8]\n", PC_REGNUM
);
1915 asm_fprintf (f
, "\tstr\tr0, [%r, #4]\n", SP_REGNUM
);
1916 asm_fprintf (f
, "\tpop\t{r0, %r}\n", PC_REGNUM
);
1918 assemble_aligned_integer (UNITS_PER_WORD
, const0_rtx
);
1919 assemble_aligned_integer (UNITS_PER_WORD
, const0_rtx
);
1922 /* Emit RTL insns to initialize the variable parts of a trampoline. */
1925 arm_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
1927 rtx fnaddr
, mem
, a_tramp
;
1929 emit_block_move (m_tramp
, assemble_trampoline_template (),
1930 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
1932 mem
= adjust_address (m_tramp
, SImode
, TARGET_32BIT
? 8 : 12);
1933 emit_move_insn (mem
, chain_value
);
1935 mem
= adjust_address (m_tramp
, SImode
, TARGET_32BIT
? 12 : 16);
1936 fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
1937 emit_move_insn (mem
, fnaddr
);
1939 a_tramp
= XEXP (m_tramp
, 0);
1940 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__clear_cache"),
1941 LCT_NORMAL
, VOIDmode
, 2, a_tramp
, Pmode
,
1942 plus_constant (a_tramp
, TRAMPOLINE_SIZE
), Pmode
);
1945 /* Thumb trampolines should be entered in thumb mode, so set
1946 the bottom bit of the address. */
1949 arm_trampoline_adjust_address (rtx addr
)
1952 addr
= expand_simple_binop (Pmode
, IOR
, addr
, const1_rtx
,
1953 NULL
, 0, OPTAB_LIB_WIDEN
);
1957 /* Return 1 if it is possible to return using a single instruction.
1958 If SIBLING is non-null, this is a test for a return before a sibling
1959 call. SIBLING is the call insn, so we can examine its register usage. */
1962 use_return_insn (int iscond
, rtx sibling
)
1965 unsigned int func_type
;
1966 unsigned long saved_int_regs
;
1967 unsigned HOST_WIDE_INT stack_adjust
;
1968 arm_stack_offsets
*offsets
;
1970 /* Never use a return instruction before reload has run. */
1971 if (!reload_completed
)
1974 func_type
= arm_current_func_type ();
1976 /* Naked, volatile and stack alignment functions need special
1978 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
| ARM_FT_STACKALIGN
))
1981 /* So do interrupt functions that use the frame pointer and Thumb
1982 interrupt functions. */
1983 if (IS_INTERRUPT (func_type
) && (frame_pointer_needed
|| TARGET_THUMB
))
1986 offsets
= arm_get_frame_offsets ();
1987 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
1989 /* As do variadic functions. */
1990 if (crtl
->args
.pretend_args_size
1991 || cfun
->machine
->uses_anonymous_args
1992 /* Or if the function calls __builtin_eh_return () */
1993 || crtl
->calls_eh_return
1994 /* Or if the function calls alloca */
1995 || cfun
->calls_alloca
1996 /* Or if there is a stack adjustment. However, if the stack pointer
1997 is saved on the stack, we can use a pre-incrementing stack load. */
1998 || !(stack_adjust
== 0 || (TARGET_APCS_FRAME
&& frame_pointer_needed
1999 && stack_adjust
== 4)))
2002 saved_int_regs
= offsets
->saved_regs_mask
;
2004 /* Unfortunately, the insn
2006 ldmib sp, {..., sp, ...}
2008 triggers a bug on most SA-110 based devices, such that the stack
2009 pointer won't be correctly restored if the instruction takes a
2010 page fault. We work around this problem by popping r3 along with
2011 the other registers, since that is never slower than executing
2012 another instruction.
2014 We test for !arm_arch5 here, because code for any architecture
2015 less than this could potentially be run on one of the buggy
2017 if (stack_adjust
== 4 && !arm_arch5
&& TARGET_ARM
)
2019 /* Validate that r3 is a call-clobbered register (always true in
2020 the default abi) ... */
2021 if (!call_used_regs
[3])
2024 /* ... that it isn't being used for a return value ... */
2025 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD
))
2028 /* ... or for a tail-call argument ... */
2031 gcc_assert (GET_CODE (sibling
) == CALL_INSN
);
2033 if (find_regno_fusage (sibling
, USE
, 3))
2037 /* ... and that there are no call-saved registers in r0-r2
2038 (always true in the default ABI). */
2039 if (saved_int_regs
& 0x7)
2043 /* Can't be done if interworking with Thumb, and any registers have been
2045 if (TARGET_INTERWORK
&& saved_int_regs
!= 0 && !IS_INTERRUPT(func_type
))
2048 /* On StrongARM, conditional returns are expensive if they aren't
2049 taken and multiple registers have been stacked. */
2050 if (iscond
&& arm_tune_strongarm
)
2052 /* Conditional return when just the LR is stored is a simple
2053 conditional-load instruction, that's not expensive. */
2054 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
2058 && arm_pic_register
!= INVALID_REGNUM
2059 && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
2063 /* If there are saved registers but the LR isn't saved, then we need
2064 two instructions for the return. */
2065 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
2068 /* Can't be done if any of the FPA regs are pushed,
2069 since this also requires an insn. */
2070 if (TARGET_HARD_FLOAT
&& TARGET_FPA
)
2071 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
2072 if (df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
2075 /* Likewise VFP regs. */
2076 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
2077 for (regno
= FIRST_VFP_REGNUM
; regno
<= LAST_VFP_REGNUM
; regno
++)
2078 if (df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
2081 if (TARGET_REALLY_IWMMXT
)
2082 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
2083 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
2089 /* Return TRUE if int I is a valid immediate ARM constant. */
2092 const_ok_for_arm (HOST_WIDE_INT i
)
2096 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
2097 be all zero, or all one. */
2098 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
2099 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
2100 != ((~(unsigned HOST_WIDE_INT
) 0)
2101 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
2104 i
&= (unsigned HOST_WIDE_INT
) 0xffffffff;
2106 /* Fast return for 0 and small values. We must do this for zero, since
2107 the code below can't handle that one case. */
2108 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xff) == 0)
2111 /* Get the number of trailing zeros. */
2112 lowbit
= ffs((int) i
) - 1;
2114 /* Only even shifts are allowed in ARM mode so round down to the
2115 nearest even number. */
2119 if ((i
& ~(((unsigned HOST_WIDE_INT
) 0xff) << lowbit
)) == 0)
2124 /* Allow rotated constants in ARM mode. */
2126 && ((i
& ~0xc000003f) == 0
2127 || (i
& ~0xf000000f) == 0
2128 || (i
& ~0xfc000003) == 0))
2135 /* Allow repeated patterns 0x00XY00XY or 0xXYXYXYXY. */
2138 if (i
== v
|| i
== (v
| (v
<< 8)))
2141 /* Allow repeated pattern 0xXY00XY00. */
2151 /* Return true if I is a valid constant for the operation CODE. */
2153 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
2155 if (const_ok_for_arm (i
))
2161 /* See if we can use movw. */
2162 if (arm_arch_thumb2
&& (i
& 0xffff0000) == 0)
2186 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
2188 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
2194 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
2198 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
2205 /* Emit a sequence of insns to handle a large constant.
2206 CODE is the code of the operation required, it can be any of SET, PLUS,
2207 IOR, AND, XOR, MINUS;
2208 MODE is the mode in which the operation is being performed;
2209 VAL is the integer to operate on;
2210 SOURCE is the other operand (a register, or a null-pointer for SET);
2211 SUBTARGETS means it is safe to create scratch registers if that will
2212 either produce a simpler sequence, or we will want to cse the values.
2213 Return value is the number of insns emitted. */
2215 /* ??? Tweak this for thumb2. */
2217 arm_split_constant (enum rtx_code code
, enum machine_mode mode
, rtx insn
,
2218 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
2222 if (insn
&& GET_CODE (PATTERN (insn
)) == COND_EXEC
)
2223 cond
= COND_EXEC_TEST (PATTERN (insn
));
2227 if (subtargets
|| code
== SET
2228 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
2229 && REGNO (target
) != REGNO (source
)))
2231 /* After arm_reorg has been called, we can't fix up expensive
2232 constants by pushing them into memory so we must synthesize
2233 them in-line, regardless of the cost. This is only likely to
2234 be more costly on chips that have load delay slots and we are
2235 compiling without running the scheduler (so no splitting
2236 occurred before the final instruction emission).
2238 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
2240 if (!after_arm_reorg
2242 && (arm_gen_constant (code
, mode
, NULL_RTX
, val
, target
, source
,
2244 > (arm_constant_limit (optimize_function_for_size_p (cfun
))
2249 /* Currently SET is the only monadic value for CODE, all
2250 the rest are diadic. */
2251 if (TARGET_USE_MOVT
)
2252 arm_emit_movpair (target
, GEN_INT (val
));
2254 emit_set_insn (target
, GEN_INT (val
));
2260 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
2262 if (TARGET_USE_MOVT
)
2263 arm_emit_movpair (temp
, GEN_INT (val
));
2265 emit_set_insn (temp
, GEN_INT (val
));
2267 /* For MINUS, the value is subtracted from, since we never
2268 have subtraction of a constant. */
2270 emit_set_insn (target
, gen_rtx_MINUS (mode
, temp
, source
));
2272 emit_set_insn (target
,
2273 gen_rtx_fmt_ee (code
, mode
, source
, temp
));
2279 return arm_gen_constant (code
, mode
, cond
, val
, target
, source
, subtargets
,
2283 /* Return the number of instructions required to synthesize the given
2284 constant, if we start emitting them from bit-position I. */
2286 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
2288 HOST_WIDE_INT temp1
;
2289 int step_size
= TARGET_ARM
? 2 : 1;
2292 gcc_assert (TARGET_ARM
|| i
== 0);
2300 if (remainder
& (((1 << step_size
) - 1) << (i
- step_size
)))
2305 temp1
= remainder
& ((0x0ff << end
)
2306 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
2307 remainder
&= ~temp1
;
2312 } while (remainder
);
2317 find_best_start (unsigned HOST_WIDE_INT remainder
)
2319 int best_consecutive_zeros
= 0;
2323 /* If we aren't targetting ARM, the best place to start is always at
2328 for (i
= 0; i
< 32; i
+= 2)
2330 int consecutive_zeros
= 0;
2332 if (!(remainder
& (3 << i
)))
2334 while ((i
< 32) && !(remainder
& (3 << i
)))
2336 consecutive_zeros
+= 2;
2339 if (consecutive_zeros
> best_consecutive_zeros
)
2341 best_consecutive_zeros
= consecutive_zeros
;
2342 best_start
= i
- consecutive_zeros
;
2348 /* So long as it won't require any more insns to do so, it's
2349 desirable to emit a small constant (in bits 0...9) in the last
2350 insn. This way there is more chance that it can be combined with
2351 a later addressing insn to form a pre-indexed load or store
2352 operation. Consider:
2354 *((volatile int *)0xe0000100) = 1;
2355 *((volatile int *)0xe0000110) = 2;
2357 We want this to wind up as:
2361 str rB, [rA, #0x100]
2363 str rB, [rA, #0x110]
2365 rather than having to synthesize both large constants from scratch.
2367 Therefore, we calculate how many insns would be required to emit
2368 the constant starting from `best_start', and also starting from
2369 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2370 yield a shorter sequence, we may as well use zero. */
2372 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
2373 && (count_insns_for_constant (remainder
, 0) <=
2374 count_insns_for_constant (remainder
, best_start
)))
2380 /* Emit an instruction with the indicated PATTERN. If COND is
2381 non-NULL, conditionalize the execution of the instruction on COND
2385 emit_constant_insn (rtx cond
, rtx pattern
)
2388 pattern
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
), pattern
);
2389 emit_insn (pattern
);
2392 /* As above, but extra parameter GENERATE which, if clear, suppresses
2394 /* ??? This needs more work for thumb2. */
2397 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
, rtx cond
,
2398 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
2403 int final_invert
= 0;
2405 int num_bits_set
= 0;
2406 int set_sign_bit_copies
= 0;
2407 int clear_sign_bit_copies
= 0;
2408 int clear_zero_bit_copies
= 0;
2409 int set_zero_bit_copies
= 0;
2411 unsigned HOST_WIDE_INT temp1
, temp2
;
2412 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
2413 int step_size
= TARGET_ARM
? 2 : 1;
2415 /* Find out which operations are safe for a given CODE. Also do a quick
2416 check for degenerate cases; these can occur when DImode operations
2430 if (remainder
== 0xffffffff)
2433 emit_constant_insn (cond
,
2434 gen_rtx_SET (VOIDmode
, target
,
2435 GEN_INT (ARM_SIGN_EXTEND (val
))));
2441 if (reload_completed
&& rtx_equal_p (target
, source
))
2445 emit_constant_insn (cond
,
2446 gen_rtx_SET (VOIDmode
, target
, source
));
2455 emit_constant_insn (cond
,
2456 gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
2459 if (remainder
== 0xffffffff)
2461 if (reload_completed
&& rtx_equal_p (target
, source
))
2464 emit_constant_insn (cond
,
2465 gen_rtx_SET (VOIDmode
, target
, source
));
2474 if (reload_completed
&& rtx_equal_p (target
, source
))
2477 emit_constant_insn (cond
,
2478 gen_rtx_SET (VOIDmode
, target
, source
));
2482 if (remainder
== 0xffffffff)
2485 emit_constant_insn (cond
,
2486 gen_rtx_SET (VOIDmode
, target
,
2487 gen_rtx_NOT (mode
, source
)));
2493 /* We treat MINUS as (val - source), since (source - val) is always
2494 passed as (source + (-val)). */
2498 emit_constant_insn (cond
,
2499 gen_rtx_SET (VOIDmode
, target
,
2500 gen_rtx_NEG (mode
, source
)));
2503 if (const_ok_for_arm (val
))
2506 emit_constant_insn (cond
,
2507 gen_rtx_SET (VOIDmode
, target
,
2508 gen_rtx_MINUS (mode
, GEN_INT (val
),
2520 /* If we can do it in one insn get out quickly. */
2521 if (const_ok_for_op (val
, code
))
2524 emit_constant_insn (cond
,
2525 gen_rtx_SET (VOIDmode
, target
,
2527 ? gen_rtx_fmt_ee (code
, mode
, source
,
2533 /* Calculate a few attributes that may be useful for specific
2535 /* Count number of leading zeros. */
2536 for (i
= 31; i
>= 0; i
--)
2538 if ((remainder
& (1 << i
)) == 0)
2539 clear_sign_bit_copies
++;
2544 /* Count number of leading 1's. */
2545 for (i
= 31; i
>= 0; i
--)
2547 if ((remainder
& (1 << i
)) != 0)
2548 set_sign_bit_copies
++;
2553 /* Count number of trailing zero's. */
2554 for (i
= 0; i
<= 31; i
++)
2556 if ((remainder
& (1 << i
)) == 0)
2557 clear_zero_bit_copies
++;
2562 /* Count number of trailing 1's. */
2563 for (i
= 0; i
<= 31; i
++)
2565 if ((remainder
& (1 << i
)) != 0)
2566 set_zero_bit_copies
++;
2574 /* See if we can do this by sign_extending a constant that is known
2575 to be negative. This is a good, way of doing it, since the shift
2576 may well merge into a subsequent insn. */
2577 if (set_sign_bit_copies
> 1)
2579 if (const_ok_for_arm
2580 (temp1
= ARM_SIGN_EXTEND (remainder
2581 << (set_sign_bit_copies
- 1))))
2585 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2586 emit_constant_insn (cond
,
2587 gen_rtx_SET (VOIDmode
, new_src
,
2589 emit_constant_insn (cond
,
2590 gen_ashrsi3 (target
, new_src
,
2591 GEN_INT (set_sign_bit_copies
- 1)));
2595 /* For an inverted constant, we will need to set the low bits,
2596 these will be shifted out of harm's way. */
2597 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
2598 if (const_ok_for_arm (~temp1
))
2602 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2603 emit_constant_insn (cond
,
2604 gen_rtx_SET (VOIDmode
, new_src
,
2606 emit_constant_insn (cond
,
2607 gen_ashrsi3 (target
, new_src
,
2608 GEN_INT (set_sign_bit_copies
- 1)));
2614 /* See if we can calculate the value as the difference between two
2615 valid immediates. */
2616 if (clear_sign_bit_copies
+ clear_zero_bit_copies
<= 16)
2618 int topshift
= clear_sign_bit_copies
& ~1;
2620 temp1
= ARM_SIGN_EXTEND ((remainder
+ (0x00800000 >> topshift
))
2621 & (0xff000000 >> topshift
));
2623 /* If temp1 is zero, then that means the 9 most significant
2624 bits of remainder were 1 and we've caused it to overflow.
2625 When topshift is 0 we don't need to do anything since we
2626 can borrow from 'bit 32'. */
2627 if (temp1
== 0 && topshift
!= 0)
2628 temp1
= 0x80000000 >> (topshift
- 1);
2630 temp2
= ARM_SIGN_EXTEND (temp1
- remainder
);
2632 if (const_ok_for_arm (temp2
))
2636 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2637 emit_constant_insn (cond
,
2638 gen_rtx_SET (VOIDmode
, new_src
,
2640 emit_constant_insn (cond
,
2641 gen_addsi3 (target
, new_src
,
2649 /* See if we can generate this by setting the bottom (or the top)
2650 16 bits, and then shifting these into the other half of the
2651 word. We only look for the simplest cases, to do more would cost
2652 too much. Be careful, however, not to generate this when the
2653 alternative would take fewer insns. */
2654 if (val
& 0xffff0000)
2656 temp1
= remainder
& 0xffff0000;
2657 temp2
= remainder
& 0x0000ffff;
2659 /* Overlaps outside this range are best done using other methods. */
2660 for (i
= 9; i
< 24; i
++)
2662 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
2663 && !const_ok_for_arm (temp2
))
2665 rtx new_src
= (subtargets
2666 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2668 insns
= arm_gen_constant (code
, mode
, cond
, temp2
, new_src
,
2669 source
, subtargets
, generate
);
2677 gen_rtx_ASHIFT (mode
, source
,
2684 /* Don't duplicate cases already considered. */
2685 for (i
= 17; i
< 24; i
++)
2687 if (((temp1
| (temp1
>> i
)) == remainder
)
2688 && !const_ok_for_arm (temp1
))
2690 rtx new_src
= (subtargets
2691 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2693 insns
= arm_gen_constant (code
, mode
, cond
, temp1
, new_src
,
2694 source
, subtargets
, generate
);
2699 gen_rtx_SET (VOIDmode
, target
,
2702 gen_rtx_LSHIFTRT (mode
, source
,
2713 /* If we have IOR or XOR, and the constant can be loaded in a
2714 single instruction, and we can find a temporary to put it in,
2715 then this can be done in two instructions instead of 3-4. */
2717 /* TARGET can't be NULL if SUBTARGETS is 0 */
2718 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
2720 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
2724 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2726 emit_constant_insn (cond
,
2727 gen_rtx_SET (VOIDmode
, sub
,
2729 emit_constant_insn (cond
,
2730 gen_rtx_SET (VOIDmode
, target
,
2731 gen_rtx_fmt_ee (code
, mode
,
2742 x = y | constant ( which is composed of set_sign_bit_copies of leading 1s
2743 and the remainder 0s for e.g. 0xfff00000)
2744 x = ~(~(y ashift set_sign_bit_copies) lshiftrt set_sign_bit_copies)
2746 This can be done in 2 instructions by using shifts with mov or mvn.
2751 mvn r0, r0, lsr #12 */
2752 if (set_sign_bit_copies
> 8
2753 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
2757 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2758 rtx shift
= GEN_INT (set_sign_bit_copies
);
2762 gen_rtx_SET (VOIDmode
, sub
,
2764 gen_rtx_ASHIFT (mode
,
2769 gen_rtx_SET (VOIDmode
, target
,
2771 gen_rtx_LSHIFTRT (mode
, sub
,
2778 x = y | constant (which has set_zero_bit_copies number of trailing ones).
2780 x = ~((~y lshiftrt set_zero_bit_copies) ashift set_zero_bit_copies).
2782 For eg. r0 = r0 | 0xfff
2787 if (set_zero_bit_copies
> 8
2788 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
2792 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2793 rtx shift
= GEN_INT (set_zero_bit_copies
);
2797 gen_rtx_SET (VOIDmode
, sub
,
2799 gen_rtx_LSHIFTRT (mode
,
2804 gen_rtx_SET (VOIDmode
, target
,
2806 gen_rtx_ASHIFT (mode
, sub
,
2812 /* This will never be reached for Thumb2 because orn is a valid
2813 instruction. This is for Thumb1 and the ARM 32 bit cases.
2815 x = y | constant (such that ~constant is a valid constant)
2817 x = ~(~y & ~constant).
2819 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
2823 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2824 emit_constant_insn (cond
,
2825 gen_rtx_SET (VOIDmode
, sub
,
2826 gen_rtx_NOT (mode
, source
)));
2829 sub
= gen_reg_rtx (mode
);
2830 emit_constant_insn (cond
,
2831 gen_rtx_SET (VOIDmode
, sub
,
2832 gen_rtx_AND (mode
, source
,
2834 emit_constant_insn (cond
,
2835 gen_rtx_SET (VOIDmode
, target
,
2836 gen_rtx_NOT (mode
, sub
)));
2843 /* See if two shifts will do 2 or more insn's worth of work. */
2844 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
2846 HOST_WIDE_INT shift_mask
= ((0xffffffff
2847 << (32 - clear_sign_bit_copies
))
2850 if ((remainder
| shift_mask
) != 0xffffffff)
2854 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2855 insns
= arm_gen_constant (AND
, mode
, cond
,
2856 remainder
| shift_mask
,
2857 new_src
, source
, subtargets
, 1);
2862 rtx targ
= subtargets
? NULL_RTX
: target
;
2863 insns
= arm_gen_constant (AND
, mode
, cond
,
2864 remainder
| shift_mask
,
2865 targ
, source
, subtargets
, 0);
2871 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2872 rtx shift
= GEN_INT (clear_sign_bit_copies
);
2874 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
2875 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
2881 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
2883 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
2885 if ((remainder
| shift_mask
) != 0xffffffff)
2889 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2891 insns
= arm_gen_constant (AND
, mode
, cond
,
2892 remainder
| shift_mask
,
2893 new_src
, source
, subtargets
, 1);
2898 rtx targ
= subtargets
? NULL_RTX
: target
;
2900 insns
= arm_gen_constant (AND
, mode
, cond
,
2901 remainder
| shift_mask
,
2902 targ
, source
, subtargets
, 0);
2908 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2909 rtx shift
= GEN_INT (clear_zero_bit_copies
);
2911 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
2912 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
2924 for (i
= 0; i
< 32; i
++)
2925 if (remainder
& (1 << i
))
2928 if ((code
== AND
) || (can_invert
&& num_bits_set
> 16))
2929 remainder
^= 0xffffffff;
2930 else if (code
== PLUS
&& num_bits_set
> 16)
2931 remainder
= (-remainder
) & 0xffffffff;
2933 /* For XOR, if more than half the bits are set and there's a sequence
2934 of more than 8 consecutive ones in the pattern then we can XOR by the
2935 inverted constant and then invert the final result; this may save an
2936 instruction and might also lead to the final mvn being merged with
2937 some other operation. */
2938 else if (code
== XOR
&& num_bits_set
> 16
2939 && (count_insns_for_constant (remainder
^ 0xffffffff,
2941 (remainder
^ 0xffffffff))
2942 < count_insns_for_constant (remainder
,
2943 find_best_start (remainder
))))
2945 remainder
^= 0xffffffff;
2954 /* Now try and find a way of doing the job in either two or three
2956 We start by looking for the largest block of zeros that are aligned on
2957 a 2-bit boundary, we then fill up the temps, wrapping around to the
2958 top of the word when we drop off the bottom.
2959 In the worst case this code should produce no more than four insns.
2960 Thumb-2 constants are shifted, not rotated, so the MSB is always the
2961 best place to start. */
2963 /* ??? Use thumb2 replicated constants when the high and low halfwords are
2966 /* Now start emitting the insns. */
2967 i
= find_best_start (remainder
);
2974 if (remainder
& (3 << (i
- 2)))
2979 temp1
= remainder
& ((0x0ff << end
)
2980 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
2981 remainder
&= ~temp1
;
2985 rtx new_src
, temp1_rtx
;
2987 if (code
== SET
|| code
== MINUS
)
2989 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
2990 if (can_invert
&& code
!= MINUS
)
2995 if ((final_invert
|| remainder
) && subtargets
)
2996 new_src
= gen_reg_rtx (mode
);
3001 else if (can_negate
)
3005 temp1
= trunc_int_for_mode (temp1
, mode
);
3006 temp1_rtx
= GEN_INT (temp1
);
3010 else if (code
== MINUS
)
3011 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
3013 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
3015 emit_constant_insn (cond
,
3016 gen_rtx_SET (VOIDmode
, new_src
,
3026 else if (code
== MINUS
)
3032 /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitrary
3042 emit_constant_insn (cond
, gen_rtx_SET (VOIDmode
, target
,
3043 gen_rtx_NOT (mode
, source
)));
3050 /* Canonicalize a comparison so that we are more likely to recognize it.
3051 This can be done for a few constant compares, where we can make the
3052 immediate value easier to load. */
3055 arm_canonicalize_comparison (enum rtx_code code
, rtx
*op0
, rtx
*op1
)
3057 enum machine_mode mode
;
3058 unsigned HOST_WIDE_INT i
, maxval
;
3060 mode
= GET_MODE (*op0
);
3061 if (mode
== VOIDmode
)
3062 mode
= GET_MODE (*op1
);
3064 maxval
= (((unsigned HOST_WIDE_INT
) 1) << (GET_MODE_BITSIZE(mode
) - 1)) - 1;
3066 /* For DImode, we have GE/LT/GEU/LTU comparisons. In ARM mode
3067 we can also use cmp/cmpeq for GTU/LEU. GT/LE must be either
3068 reversed or (for constant OP1) adjusted to GE/LT. Similarly
3069 for GTU/LEU in Thumb mode. */
3074 /* To keep things simple, always use the Cirrus cfcmp64 if it is
3076 if (TARGET_ARM
&& TARGET_HARD_FLOAT
&& TARGET_MAVERICK
)
3079 if (code
== GT
|| code
== LE
3080 || (!TARGET_ARM
&& (code
== GTU
|| code
== LEU
)))
3082 /* Missing comparison. First try to use an available
3084 if (GET_CODE (*op1
) == CONST_INT
)
3092 && arm_const_double_by_immediates (GEN_INT (i
+ 1)))
3094 *op1
= GEN_INT (i
+ 1);
3095 return code
== GT
? GE
: LT
;
3100 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
3101 && arm_const_double_by_immediates (GEN_INT (i
+ 1)))
3103 *op1
= GEN_INT (i
+ 1);
3104 return code
== GTU
? GEU
: LTU
;
3112 /* If that did not work, reverse the condition. */
3116 return swap_condition (code
);
3122 /* Comparisons smaller than DImode. Only adjust comparisons against
3123 an out-of-range constant. */
3124 if (GET_CODE (*op1
) != CONST_INT
3125 || const_ok_for_arm (INTVAL (*op1
))
3126 || const_ok_for_arm (- INTVAL (*op1
)))
3140 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
3142 *op1
= GEN_INT (i
+ 1);
3143 return code
== GT
? GE
: LT
;
3150 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
3152 *op1
= GEN_INT (i
- 1);
3153 return code
== GE
? GT
: LE
;
3159 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
3160 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
3162 *op1
= GEN_INT (i
+ 1);
3163 return code
== GTU
? GEU
: LTU
;
3170 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
3172 *op1
= GEN_INT (i
- 1);
3173 return code
== GEU
? GTU
: LEU
;
3185 /* Define how to find the value returned by a function. */
3188 arm_function_value(const_tree type
, const_tree func
,
3189 bool outgoing ATTRIBUTE_UNUSED
)
3191 enum machine_mode mode
;
3192 int unsignedp ATTRIBUTE_UNUSED
;
3193 rtx r ATTRIBUTE_UNUSED
;
3195 mode
= TYPE_MODE (type
);
3197 if (TARGET_AAPCS_BASED
)
3198 return aapcs_allocate_return_reg (mode
, type
, func
);
3200 /* Promote integer types. */
3201 if (INTEGRAL_TYPE_P (type
))
3202 mode
= arm_promote_function_mode (type
, mode
, &unsignedp
, func
, 1);
3204 /* Promotes small structs returned in a register to full-word size
3205 for big-endian AAPCS. */
3206 if (arm_return_in_msb (type
))
3208 HOST_WIDE_INT size
= int_size_in_bytes (type
);
3209 if (size
% UNITS_PER_WORD
!= 0)
3211 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
3212 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
3216 return LIBCALL_VALUE (mode
);
3220 libcall_eq (const void *p1
, const void *p2
)
3222 return rtx_equal_p ((const_rtx
) p1
, (const_rtx
) p2
);
3226 libcall_hash (const void *p1
)
3228 return hash_rtx ((const_rtx
) p1
, VOIDmode
, NULL
, NULL
, FALSE
);
3232 add_libcall (htab_t htab
, rtx libcall
)
3234 *htab_find_slot (htab
, libcall
, INSERT
) = libcall
;
3238 arm_libcall_uses_aapcs_base (const_rtx libcall
)
3240 static bool init_done
= false;
3241 static htab_t libcall_htab
;
3247 libcall_htab
= htab_create (31, libcall_hash
, libcall_eq
,
3249 add_libcall (libcall_htab
,
3250 convert_optab_libfunc (sfloat_optab
, SFmode
, SImode
));
3251 add_libcall (libcall_htab
,
3252 convert_optab_libfunc (sfloat_optab
, DFmode
, SImode
));
3253 add_libcall (libcall_htab
,
3254 convert_optab_libfunc (sfloat_optab
, SFmode
, DImode
));
3255 add_libcall (libcall_htab
,
3256 convert_optab_libfunc (sfloat_optab
, DFmode
, DImode
));
3258 add_libcall (libcall_htab
,
3259 convert_optab_libfunc (ufloat_optab
, SFmode
, SImode
));
3260 add_libcall (libcall_htab
,
3261 convert_optab_libfunc (ufloat_optab
, DFmode
, SImode
));
3262 add_libcall (libcall_htab
,
3263 convert_optab_libfunc (ufloat_optab
, SFmode
, DImode
));
3264 add_libcall (libcall_htab
,
3265 convert_optab_libfunc (ufloat_optab
, DFmode
, DImode
));
3267 add_libcall (libcall_htab
,
3268 convert_optab_libfunc (sext_optab
, SFmode
, HFmode
));
3269 add_libcall (libcall_htab
,
3270 convert_optab_libfunc (trunc_optab
, HFmode
, SFmode
));
3271 add_libcall (libcall_htab
,
3272 convert_optab_libfunc (sfix_optab
, DImode
, DFmode
));
3273 add_libcall (libcall_htab
,
3274 convert_optab_libfunc (ufix_optab
, DImode
, DFmode
));
3275 add_libcall (libcall_htab
,
3276 convert_optab_libfunc (sfix_optab
, DImode
, SFmode
));
3277 add_libcall (libcall_htab
,
3278 convert_optab_libfunc (ufix_optab
, DImode
, SFmode
));
3281 return libcall
&& htab_find (libcall_htab
, libcall
) != NULL
;
3285 arm_libcall_value (enum machine_mode mode
, const_rtx libcall
)
3287 if (TARGET_AAPCS_BASED
&& arm_pcs_default
!= ARM_PCS_AAPCS
3288 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3290 /* The following libcalls return their result in integer registers,
3291 even though they return a floating point value. */
3292 if (arm_libcall_uses_aapcs_base (libcall
))
3293 return gen_rtx_REG (mode
, ARG_REGISTER(1));
3297 return LIBCALL_VALUE (mode
);
3300 /* Determine the amount of memory needed to store the possible return
3301 registers of an untyped call. */
3303 arm_apply_result_size (void)
3309 if (TARGET_HARD_FLOAT_ABI
)
3315 if (TARGET_MAVERICK
)
3318 if (TARGET_IWMMXT_ABI
)
3325 /* Decide whether TYPE should be returned in memory (true)
3326 or in a register (false). FNTYPE is the type of the function making
3329 arm_return_in_memory (const_tree type
, const_tree fntype
)
3333 size
= int_size_in_bytes (type
); /* Negative if not fixed size. */
3335 if (TARGET_AAPCS_BASED
)
3337 /* Simple, non-aggregate types (ie not including vectors and
3338 complex) are always returned in a register (or registers).
3339 We don't care about which register here, so we can short-cut
3340 some of the detail. */
3341 if (!AGGREGATE_TYPE_P (type
)
3342 && TREE_CODE (type
) != VECTOR_TYPE
3343 && TREE_CODE (type
) != COMPLEX_TYPE
)
3346 /* Any return value that is no larger than one word can be
3348 if (((unsigned HOST_WIDE_INT
) size
) <= UNITS_PER_WORD
)
3351 /* Check any available co-processors to see if they accept the
3352 type as a register candidate (VFP, for example, can return
3353 some aggregates in consecutive registers). These aren't
3354 available if the call is variadic. */
3355 if (aapcs_select_return_coproc (type
, fntype
) >= 0)
3358 /* Vector values should be returned using ARM registers, not
3359 memory (unless they're over 16 bytes, which will break since
3360 we only have four call-clobbered registers to play with). */
3361 if (TREE_CODE (type
) == VECTOR_TYPE
)
3362 return (size
< 0 || size
> (4 * UNITS_PER_WORD
));
3364 /* The rest go in memory. */
3368 if (TREE_CODE (type
) == VECTOR_TYPE
)
3369 return (size
< 0 || size
> (4 * UNITS_PER_WORD
));
3371 if (!AGGREGATE_TYPE_P (type
) &&
3372 (TREE_CODE (type
) != VECTOR_TYPE
))
3373 /* All simple types are returned in registers. */
3376 if (arm_abi
!= ARM_ABI_APCS
)
3378 /* ATPCS and later return aggregate types in memory only if they are
3379 larger than a word (or are variable size). */
3380 return (size
< 0 || size
> UNITS_PER_WORD
);
3383 /* For the arm-wince targets we choose to be compatible with Microsoft's
3384 ARM and Thumb compilers, which always return aggregates in memory. */
3386 /* All structures/unions bigger than one word are returned in memory.
3387 Also catch the case where int_size_in_bytes returns -1. In this case
3388 the aggregate is either huge or of variable size, and in either case
3389 we will want to return it via memory and not in a register. */
3390 if (size
< 0 || size
> UNITS_PER_WORD
)
3393 if (TREE_CODE (type
) == RECORD_TYPE
)
3397 /* For a struct the APCS says that we only return in a register
3398 if the type is 'integer like' and every addressable element
3399 has an offset of zero. For practical purposes this means
3400 that the structure can have at most one non bit-field element
3401 and that this element must be the first one in the structure. */
3403 /* Find the first field, ignoring non FIELD_DECL things which will
3404 have been created by C++. */
3405 for (field
= TYPE_FIELDS (type
);
3406 field
&& TREE_CODE (field
) != FIELD_DECL
;
3407 field
= DECL_CHAIN (field
))
3411 return false; /* An empty structure. Allowed by an extension to ANSI C. */
3413 /* Check that the first field is valid for returning in a register. */
3415 /* ... Floats are not allowed */
3416 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
3419 /* ... Aggregates that are not themselves valid for returning in
3420 a register are not allowed. */
3421 if (arm_return_in_memory (TREE_TYPE (field
), NULL_TREE
))
3424 /* Now check the remaining fields, if any. Only bitfields are allowed,
3425 since they are not addressable. */
3426 for (field
= DECL_CHAIN (field
);
3428 field
= DECL_CHAIN (field
))
3430 if (TREE_CODE (field
) != FIELD_DECL
)
3433 if (!DECL_BIT_FIELD_TYPE (field
))
3440 if (TREE_CODE (type
) == UNION_TYPE
)
3444 /* Unions can be returned in registers if every element is
3445 integral, or can be returned in an integer register. */
3446 for (field
= TYPE_FIELDS (type
);
3448 field
= DECL_CHAIN (field
))
3450 if (TREE_CODE (field
) != FIELD_DECL
)
3453 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
3456 if (arm_return_in_memory (TREE_TYPE (field
), NULL_TREE
))
3462 #endif /* not ARM_WINCE */
3464 /* Return all other types in memory. */
3468 /* Indicate whether or not words of a double are in big-endian order. */
3471 arm_float_words_big_endian (void)
3473 if (TARGET_MAVERICK
)
3476 /* For FPA, float words are always big-endian. For VFP, floats words
3477 follow the memory system mode. */
3485 return (TARGET_BIG_END
? 1 : 0);
3490 const struct pcs_attribute_arg
3494 } pcs_attribute_args
[] =
3496 {"aapcs", ARM_PCS_AAPCS
},
3497 {"aapcs-vfp", ARM_PCS_AAPCS_VFP
},
3499 /* We could recognize these, but changes would be needed elsewhere
3500 * to implement them. */
3501 {"aapcs-iwmmxt", ARM_PCS_AAPCS_IWMMXT
},
3502 {"atpcs", ARM_PCS_ATPCS
},
3503 {"apcs", ARM_PCS_APCS
},
3505 {NULL
, ARM_PCS_UNKNOWN
}
3509 arm_pcs_from_attribute (tree attr
)
3511 const struct pcs_attribute_arg
*ptr
;
3514 /* Get the value of the argument. */
3515 if (TREE_VALUE (attr
) == NULL_TREE
3516 || TREE_CODE (TREE_VALUE (attr
)) != STRING_CST
)
3517 return ARM_PCS_UNKNOWN
;
3519 arg
= TREE_STRING_POINTER (TREE_VALUE (attr
));
3521 /* Check it against the list of known arguments. */
3522 for (ptr
= pcs_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
3523 if (streq (arg
, ptr
->arg
))
3526 /* An unrecognized interrupt type. */
3527 return ARM_PCS_UNKNOWN
;
3530 /* Get the PCS variant to use for this call. TYPE is the function's type
3531 specification, DECL is the specific declartion. DECL may be null if
3532 the call could be indirect or if this is a library call. */
3534 arm_get_pcs_model (const_tree type
, const_tree decl
)
3536 bool user_convention
= false;
3537 enum arm_pcs user_pcs
= arm_pcs_default
;
3542 attr
= lookup_attribute ("pcs", TYPE_ATTRIBUTES (type
));
3545 user_pcs
= arm_pcs_from_attribute (TREE_VALUE (attr
));
3546 user_convention
= true;
3549 if (TARGET_AAPCS_BASED
)
3551 /* Detect varargs functions. These always use the base rules
3552 (no argument is ever a candidate for a co-processor
3554 bool base_rules
= stdarg_p (type
);
3556 if (user_convention
)
3558 if (user_pcs
> ARM_PCS_AAPCS_LOCAL
)
3559 sorry ("non-AAPCS derived PCS variant");
3560 else if (base_rules
&& user_pcs
!= ARM_PCS_AAPCS
)
3561 error ("variadic functions must use the base AAPCS variant");
3565 return ARM_PCS_AAPCS
;
3566 else if (user_convention
)
3568 else if (decl
&& flag_unit_at_a_time
)
3570 /* Local functions never leak outside this compilation unit,
3571 so we are free to use whatever conventions are
3573 /* FIXME: remove CONST_CAST_TREE when cgraph is constified. */
3574 struct cgraph_local_info
*i
= cgraph_local_info (CONST_CAST_TREE(decl
));
3576 return ARM_PCS_AAPCS_LOCAL
;
3579 else if (user_convention
&& user_pcs
!= arm_pcs_default
)
3580 sorry ("PCS variant");
3582 /* For everything else we use the target's default. */
3583 return arm_pcs_default
;
3588 aapcs_vfp_cum_init (CUMULATIVE_ARGS
*pcum ATTRIBUTE_UNUSED
,
3589 const_tree fntype ATTRIBUTE_UNUSED
,
3590 rtx libcall ATTRIBUTE_UNUSED
,
3591 const_tree fndecl ATTRIBUTE_UNUSED
)
3593 /* Record the unallocated VFP registers. */
3594 pcum
->aapcs_vfp_regs_free
= (1 << NUM_VFP_ARG_REGS
) - 1;
3595 pcum
->aapcs_vfp_reg_alloc
= 0;
3598 /* Walk down the type tree of TYPE counting consecutive base elements.
3599 If *MODEP is VOIDmode, then set it to the first valid floating point
3600 type. If a non-floating point type is found, or if a floating point
3601 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
3602 otherwise return the count in the sub-tree. */
3604 aapcs_vfp_sub_candidate (const_tree type
, enum machine_mode
*modep
)
3606 enum machine_mode mode
;
3609 switch (TREE_CODE (type
))
3612 mode
= TYPE_MODE (type
);
3613 if (mode
!= DFmode
&& mode
!= SFmode
)
3616 if (*modep
== VOIDmode
)
3625 mode
= TYPE_MODE (TREE_TYPE (type
));
3626 if (mode
!= DFmode
&& mode
!= SFmode
)
3629 if (*modep
== VOIDmode
)
3638 /* Use V2SImode and V4SImode as representatives of all 64-bit
3639 and 128-bit vector types, whether or not those modes are
3640 supported with the present options. */
3641 size
= int_size_in_bytes (type
);
3654 if (*modep
== VOIDmode
)
3657 /* Vector modes are considered to be opaque: two vectors are
3658 equivalent for the purposes of being homogeneous aggregates
3659 if they are the same size. */
3668 tree index
= TYPE_DOMAIN (type
);
3670 /* Can't handle incomplete types. */
3671 if (!COMPLETE_TYPE_P(type
))
3674 count
= aapcs_vfp_sub_candidate (TREE_TYPE (type
), modep
);
3677 || !TYPE_MAX_VALUE (index
)
3678 || !host_integerp (TYPE_MAX_VALUE (index
), 1)
3679 || !TYPE_MIN_VALUE (index
)
3680 || !host_integerp (TYPE_MIN_VALUE (index
), 1)
3684 count
*= (1 + tree_low_cst (TYPE_MAX_VALUE (index
), 1)
3685 - tree_low_cst (TYPE_MIN_VALUE (index
), 1));
3687 /* There must be no padding. */
3688 if (!host_integerp (TYPE_SIZE (type
), 1)
3689 || (tree_low_cst (TYPE_SIZE (type
), 1)
3690 != count
* GET_MODE_BITSIZE (*modep
)))
3702 /* Can't handle incomplete types. */
3703 if (!COMPLETE_TYPE_P(type
))
3706 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
3708 if (TREE_CODE (field
) != FIELD_DECL
)
3711 sub_count
= aapcs_vfp_sub_candidate (TREE_TYPE (field
), modep
);
3717 /* There must be no padding. */
3718 if (!host_integerp (TYPE_SIZE (type
), 1)
3719 || (tree_low_cst (TYPE_SIZE (type
), 1)
3720 != count
* GET_MODE_BITSIZE (*modep
)))
3727 case QUAL_UNION_TYPE
:
3729 /* These aren't very interesting except in a degenerate case. */
3734 /* Can't handle incomplete types. */
3735 if (!COMPLETE_TYPE_P(type
))
3738 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
3740 if (TREE_CODE (field
) != FIELD_DECL
)
3743 sub_count
= aapcs_vfp_sub_candidate (TREE_TYPE (field
), modep
);
3746 count
= count
> sub_count
? count
: sub_count
;
3749 /* There must be no padding. */
3750 if (!host_integerp (TYPE_SIZE (type
), 1)
3751 || (tree_low_cst (TYPE_SIZE (type
), 1)
3752 != count
* GET_MODE_BITSIZE (*modep
)))
3765 /* Return true if PCS_VARIANT should use VFP registers. */
3767 use_vfp_abi (enum arm_pcs pcs_variant
, bool is_double
)
3769 if (pcs_variant
== ARM_PCS_AAPCS_VFP
)
3771 static bool seen_thumb1_vfp
= false;
3773 if (TARGET_THUMB1
&& !seen_thumb1_vfp
)
3775 sorry ("Thumb-1 hard-float VFP ABI");
3776 /* sorry() is not immediately fatal, so only display this once. */
3777 seen_thumb1_vfp
= true;
3783 if (pcs_variant
!= ARM_PCS_AAPCS_LOCAL
)
3786 return (TARGET_32BIT
&& TARGET_VFP
&& TARGET_HARD_FLOAT
&&
3787 (TARGET_VFP_DOUBLE
|| !is_double
));
3791 aapcs_vfp_is_call_or_return_candidate (enum arm_pcs pcs_variant
,
3792 enum machine_mode mode
, const_tree type
,
3793 enum machine_mode
*base_mode
, int *count
)
3795 enum machine_mode new_mode
= VOIDmode
;
3797 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
3798 || GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
3799 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
3804 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
3807 new_mode
= (mode
== DCmode
? DFmode
: SFmode
);
3809 else if (type
&& (mode
== BLKmode
|| TREE_CODE (type
) == VECTOR_TYPE
))
3811 int ag_count
= aapcs_vfp_sub_candidate (type
, &new_mode
);
3813 if (ag_count
> 0 && ag_count
<= 4)
3822 if (!use_vfp_abi (pcs_variant
, ARM_NUM_REGS (new_mode
) > 1))
3825 *base_mode
= new_mode
;
3830 aapcs_vfp_is_return_candidate (enum arm_pcs pcs_variant
,
3831 enum machine_mode mode
, const_tree type
)
3833 int count ATTRIBUTE_UNUSED
;
3834 enum machine_mode ag_mode ATTRIBUTE_UNUSED
;
3836 if (!use_vfp_abi (pcs_variant
, false))
3838 return aapcs_vfp_is_call_or_return_candidate (pcs_variant
, mode
, type
,
3843 aapcs_vfp_is_call_candidate (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
3846 if (!use_vfp_abi (pcum
->pcs_variant
, false))
3849 return aapcs_vfp_is_call_or_return_candidate (pcum
->pcs_variant
, mode
, type
,
3850 &pcum
->aapcs_vfp_rmode
,
3851 &pcum
->aapcs_vfp_rcount
);
3855 aapcs_vfp_allocate (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
3856 const_tree type ATTRIBUTE_UNUSED
)
3858 int shift
= GET_MODE_SIZE (pcum
->aapcs_vfp_rmode
) / GET_MODE_SIZE (SFmode
);
3859 unsigned mask
= (1 << (shift
* pcum
->aapcs_vfp_rcount
)) - 1;
3862 for (regno
= 0; regno
< NUM_VFP_ARG_REGS
; regno
+= shift
)
3863 if (((pcum
->aapcs_vfp_regs_free
>> regno
) & mask
) == mask
)
3865 pcum
->aapcs_vfp_reg_alloc
= mask
<< regno
;
3866 if (mode
== BLKmode
|| (mode
== TImode
&& !TARGET_NEON
))
3869 int rcount
= pcum
->aapcs_vfp_rcount
;
3871 enum machine_mode rmode
= pcum
->aapcs_vfp_rmode
;
3875 /* Avoid using unsupported vector modes. */
3876 if (rmode
== V2SImode
)
3878 else if (rmode
== V4SImode
)
3885 par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (rcount
));
3886 for (i
= 0; i
< rcount
; i
++)
3888 rtx tmp
= gen_rtx_REG (rmode
,
3889 FIRST_VFP_REGNUM
+ regno
+ i
* rshift
);
3890 tmp
= gen_rtx_EXPR_LIST
3892 GEN_INT (i
* GET_MODE_SIZE (rmode
)));
3893 XVECEXP (par
, 0, i
) = tmp
;
3896 pcum
->aapcs_reg
= par
;
3899 pcum
->aapcs_reg
= gen_rtx_REG (mode
, FIRST_VFP_REGNUM
+ regno
);
3906 aapcs_vfp_allocate_return_reg (enum arm_pcs pcs_variant ATTRIBUTE_UNUSED
,
3907 enum machine_mode mode
,
3908 const_tree type ATTRIBUTE_UNUSED
)
3910 if (!use_vfp_abi (pcs_variant
, false))
3913 if (mode
== BLKmode
|| (mode
== TImode
&& !TARGET_NEON
))
3916 enum machine_mode ag_mode
;
3921 aapcs_vfp_is_call_or_return_candidate (pcs_variant
, mode
, type
,
3926 if (ag_mode
== V2SImode
)
3928 else if (ag_mode
== V4SImode
)
3934 shift
= GET_MODE_SIZE(ag_mode
) / GET_MODE_SIZE(SFmode
);
3935 par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (count
));
3936 for (i
= 0; i
< count
; i
++)
3938 rtx tmp
= gen_rtx_REG (ag_mode
, FIRST_VFP_REGNUM
+ i
* shift
);
3939 tmp
= gen_rtx_EXPR_LIST (VOIDmode
, tmp
,
3940 GEN_INT (i
* GET_MODE_SIZE (ag_mode
)));
3941 XVECEXP (par
, 0, i
) = tmp
;
3947 return gen_rtx_REG (mode
, FIRST_VFP_REGNUM
);
3951 aapcs_vfp_advance (CUMULATIVE_ARGS
*pcum ATTRIBUTE_UNUSED
,
3952 enum machine_mode mode ATTRIBUTE_UNUSED
,
3953 const_tree type ATTRIBUTE_UNUSED
)
3955 pcum
->aapcs_vfp_regs_free
&= ~pcum
->aapcs_vfp_reg_alloc
;
3956 pcum
->aapcs_vfp_reg_alloc
= 0;
3960 #define AAPCS_CP(X) \
3962 aapcs_ ## X ## _cum_init, \
3963 aapcs_ ## X ## _is_call_candidate, \
3964 aapcs_ ## X ## _allocate, \
3965 aapcs_ ## X ## _is_return_candidate, \
3966 aapcs_ ## X ## _allocate_return_reg, \
3967 aapcs_ ## X ## _advance \
3970 /* Table of co-processors that can be used to pass arguments in
3971 registers. Idealy no arugment should be a candidate for more than
3972 one co-processor table entry, but the table is processed in order
3973 and stops after the first match. If that entry then fails to put
3974 the argument into a co-processor register, the argument will go on
3978 /* Initialize co-processor related state in CUMULATIVE_ARGS structure. */
3979 void (*cum_init
) (CUMULATIVE_ARGS
*, const_tree
, rtx
, const_tree
);
3981 /* Return true if an argument of mode MODE (or type TYPE if MODE is
3982 BLKmode) is a candidate for this co-processor's registers; this
3983 function should ignore any position-dependent state in
3984 CUMULATIVE_ARGS and only use call-type dependent information. */
3985 bool (*is_call_candidate
) (CUMULATIVE_ARGS
*, enum machine_mode
, const_tree
);
3987 /* Return true if the argument does get a co-processor register; it
3988 should set aapcs_reg to an RTX of the register allocated as is
3989 required for a return from FUNCTION_ARG. */
3990 bool (*allocate
) (CUMULATIVE_ARGS
*, enum machine_mode
, const_tree
);
3992 /* Return true if a result of mode MODE (or type TYPE if MODE is
3993 BLKmode) is can be returned in this co-processor's registers. */
3994 bool (*is_return_candidate
) (enum arm_pcs
, enum machine_mode
, const_tree
);
3996 /* Allocate and return an RTX element to hold the return type of a
3997 call, this routine must not fail and will only be called if
3998 is_return_candidate returned true with the same parameters. */
3999 rtx (*allocate_return_reg
) (enum arm_pcs
, enum machine_mode
, const_tree
);
4001 /* Finish processing this argument and prepare to start processing
4003 void (*advance
) (CUMULATIVE_ARGS
*, enum machine_mode
, const_tree
);
4004 } aapcs_cp_arg_layout
[ARM_NUM_COPROC_SLOTS
] =
4012 aapcs_select_call_coproc (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
4017 for (i
= 0; i
< ARM_NUM_COPROC_SLOTS
; i
++)
4018 if (aapcs_cp_arg_layout
[i
].is_call_candidate (pcum
, mode
, type
))
4025 aapcs_select_return_coproc (const_tree type
, const_tree fntype
)
4027 /* We aren't passed a decl, so we can't check that a call is local.
4028 However, it isn't clear that that would be a win anyway, since it
4029 might limit some tail-calling opportunities. */
4030 enum arm_pcs pcs_variant
;
4034 const_tree fndecl
= NULL_TREE
;
4036 if (TREE_CODE (fntype
) == FUNCTION_DECL
)
4039 fntype
= TREE_TYPE (fntype
);
4042 pcs_variant
= arm_get_pcs_model (fntype
, fndecl
);
4045 pcs_variant
= arm_pcs_default
;
4047 if (pcs_variant
!= ARM_PCS_AAPCS
)
4051 for (i
= 0; i
< ARM_NUM_COPROC_SLOTS
; i
++)
4052 if (aapcs_cp_arg_layout
[i
].is_return_candidate (pcs_variant
,
4061 aapcs_allocate_return_reg (enum machine_mode mode
, const_tree type
,
4064 /* We aren't passed a decl, so we can't check that a call is local.
4065 However, it isn't clear that that would be a win anyway, since it
4066 might limit some tail-calling opportunities. */
4067 enum arm_pcs pcs_variant
;
4068 int unsignedp ATTRIBUTE_UNUSED
;
4072 const_tree fndecl
= NULL_TREE
;
4074 if (TREE_CODE (fntype
) == FUNCTION_DECL
)
4077 fntype
= TREE_TYPE (fntype
);
4080 pcs_variant
= arm_get_pcs_model (fntype
, fndecl
);
4083 pcs_variant
= arm_pcs_default
;
4085 /* Promote integer types. */
4086 if (type
&& INTEGRAL_TYPE_P (type
))
4087 mode
= arm_promote_function_mode (type
, mode
, &unsignedp
, fntype
, 1);
4089 if (pcs_variant
!= ARM_PCS_AAPCS
)
4093 for (i
= 0; i
< ARM_NUM_COPROC_SLOTS
; i
++)
4094 if (aapcs_cp_arg_layout
[i
].is_return_candidate (pcs_variant
, mode
,
4096 return aapcs_cp_arg_layout
[i
].allocate_return_reg (pcs_variant
,
4100 /* Promotes small structs returned in a register to full-word size
4101 for big-endian AAPCS. */
4102 if (type
&& arm_return_in_msb (type
))
4104 HOST_WIDE_INT size
= int_size_in_bytes (type
);
4105 if (size
% UNITS_PER_WORD
!= 0)
4107 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
4108 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
4112 return gen_rtx_REG (mode
, R0_REGNUM
);
4116 aapcs_libcall_value (enum machine_mode mode
)
4118 return aapcs_allocate_return_reg (mode
, NULL_TREE
, NULL_TREE
);
4121 /* Lay out a function argument using the AAPCS rules. The rule
4122 numbers referred to here are those in the AAPCS. */
4124 aapcs_layout_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
4125 const_tree type
, bool named
)
4130 /* We only need to do this once per argument. */
4131 if (pcum
->aapcs_arg_processed
)
4134 pcum
->aapcs_arg_processed
= true;
4136 /* Special case: if named is false then we are handling an incoming
4137 anonymous argument which is on the stack. */
4141 /* Is this a potential co-processor register candidate? */
4142 if (pcum
->pcs_variant
!= ARM_PCS_AAPCS
)
4144 int slot
= aapcs_select_call_coproc (pcum
, mode
, type
);
4145 pcum
->aapcs_cprc_slot
= slot
;
4147 /* We don't have to apply any of the rules from part B of the
4148 preparation phase, these are handled elsewhere in the
4153 /* A Co-processor register candidate goes either in its own
4154 class of registers or on the stack. */
4155 if (!pcum
->aapcs_cprc_failed
[slot
])
4157 /* C1.cp - Try to allocate the argument to co-processor
4159 if (aapcs_cp_arg_layout
[slot
].allocate (pcum
, mode
, type
))
4162 /* C2.cp - Put the argument on the stack and note that we
4163 can't assign any more candidates in this slot. We also
4164 need to note that we have allocated stack space, so that
4165 we won't later try to split a non-cprc candidate between
4166 core registers and the stack. */
4167 pcum
->aapcs_cprc_failed
[slot
] = true;
4168 pcum
->can_split
= false;
4171 /* We didn't get a register, so this argument goes on the
4173 gcc_assert (pcum
->can_split
== false);
4178 /* C3 - For double-word aligned arguments, round the NCRN up to the
4179 next even number. */
4180 ncrn
= pcum
->aapcs_ncrn
;
4181 if ((ncrn
& 1) && arm_needs_doubleword_align (mode
, type
))
4184 nregs
= ARM_NUM_REGS2(mode
, type
);
4186 /* Sigh, this test should really assert that nregs > 0, but a GCC
4187 extension allows empty structs and then gives them empty size; it
4188 then allows such a structure to be passed by value. For some of
4189 the code below we have to pretend that such an argument has
4190 non-zero size so that we 'locate' it correctly either in
4191 registers or on the stack. */
4192 gcc_assert (nregs
>= 0);
4194 nregs2
= nregs
? nregs
: 1;
4196 /* C4 - Argument fits entirely in core registers. */
4197 if (ncrn
+ nregs2
<= NUM_ARG_REGS
)
4199 pcum
->aapcs_reg
= gen_rtx_REG (mode
, ncrn
);
4200 pcum
->aapcs_next_ncrn
= ncrn
+ nregs
;
4204 /* C5 - Some core registers left and there are no arguments already
4205 on the stack: split this argument between the remaining core
4206 registers and the stack. */
4207 if (ncrn
< NUM_ARG_REGS
&& pcum
->can_split
)
4209 pcum
->aapcs_reg
= gen_rtx_REG (mode
, ncrn
);
4210 pcum
->aapcs_next_ncrn
= NUM_ARG_REGS
;
4211 pcum
->aapcs_partial
= (NUM_ARG_REGS
- ncrn
) * UNITS_PER_WORD
;
4215 /* C6 - NCRN is set to 4. */
4216 pcum
->aapcs_next_ncrn
= NUM_ARG_REGS
;
4218 /* C7,C8 - arugment goes on the stack. We have nothing to do here. */
4222 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4223 for a call to a function whose data type is FNTYPE.
4224 For a library call, FNTYPE is NULL. */
4226 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
4228 tree fndecl ATTRIBUTE_UNUSED
)
4230 /* Long call handling. */
4232 pcum
->pcs_variant
= arm_get_pcs_model (fntype
, fndecl
);
4234 pcum
->pcs_variant
= arm_pcs_default
;
4236 if (pcum
->pcs_variant
<= ARM_PCS_AAPCS_LOCAL
)
4238 if (arm_libcall_uses_aapcs_base (libname
))
4239 pcum
->pcs_variant
= ARM_PCS_AAPCS
;
4241 pcum
->aapcs_ncrn
= pcum
->aapcs_next_ncrn
= 0;
4242 pcum
->aapcs_reg
= NULL_RTX
;
4243 pcum
->aapcs_partial
= 0;
4244 pcum
->aapcs_arg_processed
= false;
4245 pcum
->aapcs_cprc_slot
= -1;
4246 pcum
->can_split
= true;
4248 if (pcum
->pcs_variant
!= ARM_PCS_AAPCS
)
4252 for (i
= 0; i
< ARM_NUM_COPROC_SLOTS
; i
++)
4254 pcum
->aapcs_cprc_failed
[i
] = false;
4255 aapcs_cp_arg_layout
[i
].cum_init (pcum
, fntype
, libname
, fndecl
);
4263 /* On the ARM, the offset starts at 0. */
4265 pcum
->iwmmxt_nregs
= 0;
4266 pcum
->can_split
= true;
4268 /* Varargs vectors are treated the same as long long.
4269 named_count avoids having to change the way arm handles 'named' */
4270 pcum
->named_count
= 0;
4273 if (TARGET_REALLY_IWMMXT
&& fntype
)
4277 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
4279 fn_arg
= TREE_CHAIN (fn_arg
))
4280 pcum
->named_count
+= 1;
4282 if (! pcum
->named_count
)
4283 pcum
->named_count
= INT_MAX
;
4288 /* Return true if mode/type need doubleword alignment. */
4290 arm_needs_doubleword_align (enum machine_mode mode
, const_tree type
)
4292 return (GET_MODE_ALIGNMENT (mode
) > PARM_BOUNDARY
4293 || (type
&& TYPE_ALIGN (type
) > PARM_BOUNDARY
));
4297 /* Determine where to put an argument to a function.
4298 Value is zero to push the argument on the stack,
4299 or a hard register in which to store the argument.
4301 MODE is the argument's machine mode.
4302 TYPE is the data type of the argument (as a tree).
4303 This is null for libcalls where that information may
4305 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4306 the preceding args and about the function being called.
4307 NAMED is nonzero if this argument is a named parameter
4308 (otherwise it is an extra parameter matching an ellipsis).
4310 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
4311 other arguments are passed on the stack. If (NAMED == 0) (which happens
4312 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
4313 defined), say it is passed in the stack (function_prologue will
4314 indeed make it pass in the stack if necessary). */
4317 arm_function_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
4318 const_tree type
, bool named
)
4322 /* Handle the special case quickly. Pick an arbitrary value for op2 of
4323 a call insn (op3 of a call_value insn). */
4324 if (mode
== VOIDmode
)
4327 if (pcum
->pcs_variant
<= ARM_PCS_AAPCS_LOCAL
)
4329 aapcs_layout_arg (pcum
, mode
, type
, named
);
4330 return pcum
->aapcs_reg
;
4333 /* Varargs vectors are treated the same as long long.
4334 named_count avoids having to change the way arm handles 'named' */
4335 if (TARGET_IWMMXT_ABI
4336 && arm_vector_mode_supported_p (mode
)
4337 && pcum
->named_count
> pcum
->nargs
+ 1)
4339 if (pcum
->iwmmxt_nregs
<= 9)
4340 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
4343 pcum
->can_split
= false;
4348 /* Put doubleword aligned quantities in even register pairs. */
4350 && ARM_DOUBLEWORD_ALIGN
4351 && arm_needs_doubleword_align (mode
, type
))
4354 /* Only allow splitting an arg between regs and memory if all preceding
4355 args were allocated to regs. For args passed by reference we only count
4356 the reference pointer. */
4357 if (pcum
->can_split
)
4360 nregs
= ARM_NUM_REGS2 (mode
, type
);
4362 if (!named
|| pcum
->nregs
+ nregs
> NUM_ARG_REGS
)
4365 return gen_rtx_REG (mode
, pcum
->nregs
);
4369 arm_function_arg_boundary (enum machine_mode mode
, const_tree type
)
4371 return (ARM_DOUBLEWORD_ALIGN
&& arm_needs_doubleword_align (mode
, type
)
4372 ? DOUBLEWORD_ALIGNMENT
4377 arm_arg_partial_bytes (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
4378 tree type
, bool named
)
4380 int nregs
= pcum
->nregs
;
4382 if (pcum
->pcs_variant
<= ARM_PCS_AAPCS_LOCAL
)
4384 aapcs_layout_arg (pcum
, mode
, type
, named
);
4385 return pcum
->aapcs_partial
;
4388 if (TARGET_IWMMXT_ABI
&& arm_vector_mode_supported_p (mode
))
4391 if (NUM_ARG_REGS
> nregs
4392 && (NUM_ARG_REGS
< nregs
+ ARM_NUM_REGS2 (mode
, type
))
4394 return (NUM_ARG_REGS
- nregs
) * UNITS_PER_WORD
;
4399 /* Update the data in PCUM to advance over an argument
4400 of mode MODE and data type TYPE.
4401 (TYPE is null for libcalls where that information may not be available.) */
4404 arm_function_arg_advance (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
4405 const_tree type
, bool named
)
4407 if (pcum
->pcs_variant
<= ARM_PCS_AAPCS_LOCAL
)
4409 aapcs_layout_arg (pcum
, mode
, type
, named
);
4411 if (pcum
->aapcs_cprc_slot
>= 0)
4413 aapcs_cp_arg_layout
[pcum
->aapcs_cprc_slot
].advance (pcum
, mode
,
4415 pcum
->aapcs_cprc_slot
= -1;
4418 /* Generic stuff. */
4419 pcum
->aapcs_arg_processed
= false;
4420 pcum
->aapcs_ncrn
= pcum
->aapcs_next_ncrn
;
4421 pcum
->aapcs_reg
= NULL_RTX
;
4422 pcum
->aapcs_partial
= 0;
4427 if (arm_vector_mode_supported_p (mode
)
4428 && pcum
->named_count
> pcum
->nargs
4429 && TARGET_IWMMXT_ABI
)
4430 pcum
->iwmmxt_nregs
+= 1;
4432 pcum
->nregs
+= ARM_NUM_REGS2 (mode
, type
);
4436 /* Variable sized types are passed by reference. This is a GCC
4437 extension to the ARM ABI. */
4440 arm_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
4441 enum machine_mode mode ATTRIBUTE_UNUSED
,
4442 const_tree type
, bool named ATTRIBUTE_UNUSED
)
4444 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
4447 /* Encode the current state of the #pragma [no_]long_calls. */
4450 OFF
, /* No #pragma [no_]long_calls is in effect. */
4451 LONG
, /* #pragma long_calls is in effect. */
4452 SHORT
/* #pragma no_long_calls is in effect. */
4455 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
4458 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
4460 arm_pragma_long_calls
= LONG
;
4464 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
4466 arm_pragma_long_calls
= SHORT
;
4470 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
4472 arm_pragma_long_calls
= OFF
;
4475 /* Handle an attribute requiring a FUNCTION_DECL;
4476 arguments as in struct attribute_spec.handler. */
4478 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
4479 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
4481 if (TREE_CODE (*node
) != FUNCTION_DECL
)
4483 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
4485 *no_add_attrs
= true;
4491 /* Handle an "interrupt" or "isr" attribute;
4492 arguments as in struct attribute_spec.handler. */
4494 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
4499 if (TREE_CODE (*node
) != FUNCTION_DECL
)
4501 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
4503 *no_add_attrs
= true;
4505 /* FIXME: the argument if any is checked for type attributes;
4506 should it be checked for decl ones? */
4510 if (TREE_CODE (*node
) == FUNCTION_TYPE
4511 || TREE_CODE (*node
) == METHOD_TYPE
)
4513 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
4515 warning (OPT_Wattributes
, "%qE attribute ignored",
4517 *no_add_attrs
= true;
4520 else if (TREE_CODE (*node
) == POINTER_TYPE
4521 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
4522 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
4523 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
4525 *node
= build_variant_type_copy (*node
);
4526 TREE_TYPE (*node
) = build_type_attribute_variant
4528 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
4529 *no_add_attrs
= true;
4533 /* Possibly pass this attribute on from the type to a decl. */
4534 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
4535 | (int) ATTR_FLAG_FUNCTION_NEXT
4536 | (int) ATTR_FLAG_ARRAY_NEXT
))
4538 *no_add_attrs
= true;
4539 return tree_cons (name
, args
, NULL_TREE
);
4543 warning (OPT_Wattributes
, "%qE attribute ignored",
4552 /* Handle a "pcs" attribute; arguments as in struct
4553 attribute_spec.handler. */
4555 arm_handle_pcs_attribute (tree
*node ATTRIBUTE_UNUSED
, tree name
, tree args
,
4556 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
4558 if (arm_pcs_from_attribute (args
) == ARM_PCS_UNKNOWN
)
4560 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
4561 *no_add_attrs
= true;
4566 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
4567 /* Handle the "notshared" attribute. This attribute is another way of
4568 requesting hidden visibility. ARM's compiler supports
4569 "__declspec(notshared)"; we support the same thing via an
4573 arm_handle_notshared_attribute (tree
*node
,
4574 tree name ATTRIBUTE_UNUSED
,
4575 tree args ATTRIBUTE_UNUSED
,
4576 int flags ATTRIBUTE_UNUSED
,
4579 tree decl
= TYPE_NAME (*node
);
4583 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
4584 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
4585 *no_add_attrs
= false;
4591 /* Return 0 if the attributes for two types are incompatible, 1 if they
4592 are compatible, and 2 if they are nearly compatible (which causes a
4593 warning to be generated). */
4595 arm_comp_type_attributes (const_tree type1
, const_tree type2
)
4599 /* Check for mismatch of non-default calling convention. */
4600 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
4603 /* Check for mismatched call attributes. */
4604 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
4605 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
4606 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
4607 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
4609 /* Only bother to check if an attribute is defined. */
4610 if (l1
| l2
| s1
| s2
)
4612 /* If one type has an attribute, the other must have the same attribute. */
4613 if ((l1
!= l2
) || (s1
!= s2
))
4616 /* Disallow mixed attributes. */
4617 if ((l1
& s2
) || (l2
& s1
))
4621 /* Check for mismatched ISR attribute. */
4622 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
4624 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
4625 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
4627 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
4634 /* Assigns default attributes to newly defined type. This is used to
4635 set short_call/long_call attributes for function types of
4636 functions defined inside corresponding #pragma scopes. */
4638 arm_set_default_type_attributes (tree type
)
4640 /* Add __attribute__ ((long_call)) to all functions, when
4641 inside #pragma long_calls or __attribute__ ((short_call)),
4642 when inside #pragma no_long_calls. */
4643 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
4645 tree type_attr_list
, attr_name
;
4646 type_attr_list
= TYPE_ATTRIBUTES (type
);
4648 if (arm_pragma_long_calls
== LONG
)
4649 attr_name
= get_identifier ("long_call");
4650 else if (arm_pragma_long_calls
== SHORT
)
4651 attr_name
= get_identifier ("short_call");
4655 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
4656 TYPE_ATTRIBUTES (type
) = type_attr_list
;
4660 /* Return true if DECL is known to be linked into section SECTION. */
4663 arm_function_in_section_p (tree decl
, section
*section
)
4665 /* We can only be certain about functions defined in the same
4666 compilation unit. */
4667 if (!TREE_STATIC (decl
))
4670 /* Make sure that SYMBOL always binds to the definition in this
4671 compilation unit. */
4672 if (!targetm
.binds_local_p (decl
))
4675 /* If DECL_SECTION_NAME is set, assume it is trustworthy. */
4676 if (!DECL_SECTION_NAME (decl
))
4678 /* Make sure that we will not create a unique section for DECL. */
4679 if (flag_function_sections
|| DECL_ONE_ONLY (decl
))
4683 return function_section (decl
) == section
;
4686 /* Return nonzero if a 32-bit "long_call" should be generated for
4687 a call from the current function to DECL. We generate a long_call
4690 a. has an __attribute__((long call))
4691 or b. is within the scope of a #pragma long_calls
4692 or c. the -mlong-calls command line switch has been specified
4694 However we do not generate a long call if the function:
4696 d. has an __attribute__ ((short_call))
4697 or e. is inside the scope of a #pragma no_long_calls
4698 or f. is defined in the same section as the current function. */
4701 arm_is_long_call_p (tree decl
)
4706 return TARGET_LONG_CALLS
;
4708 attrs
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
4709 if (lookup_attribute ("short_call", attrs
))
4712 /* For "f", be conservative, and only cater for cases in which the
4713 whole of the current function is placed in the same section. */
4714 if (!flag_reorder_blocks_and_partition
4715 && TREE_CODE (decl
) == FUNCTION_DECL
4716 && arm_function_in_section_p (decl
, current_function_section ()))
4719 if (lookup_attribute ("long_call", attrs
))
4722 return TARGET_LONG_CALLS
;
4725 /* Return nonzero if it is ok to make a tail-call to DECL. */
4727 arm_function_ok_for_sibcall (tree decl
, tree exp
)
4729 unsigned long func_type
;
4731 if (cfun
->machine
->sibcall_blocked
)
4734 /* Never tailcall something for which we have no decl, or if we
4735 are generating code for Thumb-1. */
4736 if (decl
== NULL
|| TARGET_THUMB1
)
4739 /* The PIC register is live on entry to VxWorks PLT entries, so we
4740 must make the call before restoring the PIC register. */
4741 if (TARGET_VXWORKS_RTP
&& flag_pic
&& !targetm
.binds_local_p (decl
))
4744 /* Cannot tail-call to long calls, since these are out of range of
4745 a branch instruction. */
4746 if (arm_is_long_call_p (decl
))
4749 /* If we are interworking and the function is not declared static
4750 then we can't tail-call it unless we know that it exists in this
4751 compilation unit (since it might be a Thumb routine). */
4752 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
4755 func_type
= arm_current_func_type ();
4756 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
4757 if (IS_INTERRUPT (func_type
))
4760 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
4762 /* Check that the return value locations are the same. For
4763 example that we aren't returning a value from the sibling in
4764 a VFP register but then need to transfer it to a core
4768 a
= arm_function_value (TREE_TYPE (exp
), decl
, false);
4769 b
= arm_function_value (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
4771 if (!rtx_equal_p (a
, b
))
4775 /* Never tailcall if function may be called with a misaligned SP. */
4776 if (IS_STACKALIGN (func_type
))
4779 /* Everything else is ok. */
4784 /* Addressing mode support functions. */
4786 /* Return nonzero if X is a legitimate immediate operand when compiling
4787 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */
4789 legitimate_pic_operand_p (rtx x
)
4791 if (GET_CODE (x
) == SYMBOL_REF
4792 || (GET_CODE (x
) == CONST
4793 && GET_CODE (XEXP (x
, 0)) == PLUS
4794 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
))
4800 /* Record that the current function needs a PIC register. Initialize
4801 cfun->machine->pic_reg if we have not already done so. */
4804 require_pic_register (void)
4806 /* A lot of the logic here is made obscure by the fact that this
4807 routine gets called as part of the rtx cost estimation process.
4808 We don't want those calls to affect any assumptions about the real
4809 function; and further, we can't call entry_of_function() until we
4810 start the real expansion process. */
4811 if (!crtl
->uses_pic_offset_table
)
4813 gcc_assert (can_create_pseudo_p ());
4814 if (arm_pic_register
!= INVALID_REGNUM
)
4816 if (!cfun
->machine
->pic_reg
)
4817 cfun
->machine
->pic_reg
= gen_rtx_REG (Pmode
, arm_pic_register
);
4819 /* Play games to avoid marking the function as needing pic
4820 if we are being called as part of the cost-estimation
4822 if (current_ir_type () != IR_GIMPLE
|| currently_expanding_to_rtl
)
4823 crtl
->uses_pic_offset_table
= 1;
4829 if (!cfun
->machine
->pic_reg
)
4830 cfun
->machine
->pic_reg
= gen_reg_rtx (Pmode
);
4832 /* Play games to avoid marking the function as needing pic
4833 if we are being called as part of the cost-estimation
4835 if (current_ir_type () != IR_GIMPLE
|| currently_expanding_to_rtl
)
4837 crtl
->uses_pic_offset_table
= 1;
4840 arm_load_pic_register (0UL);
4845 for (insn
= seq
; insn
; insn
= NEXT_INSN (insn
))
4847 INSN_LOCATOR (insn
) = prologue_locator
;
4849 /* We can be called during expansion of PHI nodes, where
4850 we can't yet emit instructions directly in the final
4851 insn stream. Queue the insns on the entry edge, they will
4852 be committed after everything else is expanded. */
4853 insert_insn_on_edge (seq
, single_succ_edge (ENTRY_BLOCK_PTR
));
4860 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
4862 if (GET_CODE (orig
) == SYMBOL_REF
4863 || GET_CODE (orig
) == LABEL_REF
)
4869 gcc_assert (can_create_pseudo_p ());
4870 reg
= gen_reg_rtx (Pmode
);
4873 /* VxWorks does not impose a fixed gap between segments; the run-time
4874 gap can be different from the object-file gap. We therefore can't
4875 use GOTOFF unless we are absolutely sure that the symbol is in the
4876 same segment as the GOT. Unfortunately, the flexibility of linker
4877 scripts means that we can't be sure of that in general, so assume
4878 that GOTOFF is never valid on VxWorks. */
4879 if ((GET_CODE (orig
) == LABEL_REF
4880 || (GET_CODE (orig
) == SYMBOL_REF
&&
4881 SYMBOL_REF_LOCAL_P (orig
)))
4883 && !TARGET_VXWORKS_RTP
)
4884 insn
= arm_pic_static_addr (orig
, reg
);
4890 /* If this function doesn't have a pic register, create one now. */
4891 require_pic_register ();
4893 pat
= gen_calculate_pic_address (reg
, cfun
->machine
->pic_reg
, orig
);
4895 /* Make the MEM as close to a constant as possible. */
4896 mem
= SET_SRC (pat
);
4897 gcc_assert (MEM_P (mem
) && !MEM_VOLATILE_P (mem
));
4898 MEM_READONLY_P (mem
) = 1;
4899 MEM_NOTRAP_P (mem
) = 1;
4901 insn
= emit_insn (pat
);
4904 /* Put a REG_EQUAL note on this insn, so that it can be optimized
4906 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
4910 else if (GET_CODE (orig
) == CONST
)
4914 if (GET_CODE (XEXP (orig
, 0)) == PLUS
4915 && XEXP (XEXP (orig
, 0), 0) == cfun
->machine
->pic_reg
)
4918 /* Handle the case where we have: const (UNSPEC_TLS). */
4919 if (GET_CODE (XEXP (orig
, 0)) == UNSPEC
4920 && XINT (XEXP (orig
, 0), 1) == UNSPEC_TLS
)
4923 /* Handle the case where we have:
4924 const (plus (UNSPEC_TLS) (ADDEND)). The ADDEND must be a
4926 if (GET_CODE (XEXP (orig
, 0)) == PLUS
4927 && GET_CODE (XEXP (XEXP (orig
, 0), 0)) == UNSPEC
4928 && XINT (XEXP (XEXP (orig
, 0), 0), 1) == UNSPEC_TLS
)
4930 gcc_assert (GET_CODE (XEXP (XEXP (orig
, 0), 1)) == CONST_INT
);
4936 gcc_assert (can_create_pseudo_p ());
4937 reg
= gen_reg_rtx (Pmode
);
4940 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
4942 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
4943 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
4944 base
== reg
? 0 : reg
);
4946 if (GET_CODE (offset
) == CONST_INT
)
4948 /* The base register doesn't really matter, we only want to
4949 test the index for the appropriate mode. */
4950 if (!arm_legitimate_index_p (mode
, offset
, SET
, 0))
4952 gcc_assert (can_create_pseudo_p ());
4953 offset
= force_reg (Pmode
, offset
);
4956 if (GET_CODE (offset
) == CONST_INT
)
4957 return plus_constant (base
, INTVAL (offset
));
4960 if (GET_MODE_SIZE (mode
) > 4
4961 && (GET_MODE_CLASS (mode
) == MODE_INT
4962 || TARGET_SOFT_FLOAT
))
4964 emit_insn (gen_addsi3 (reg
, base
, offset
));
4968 return gen_rtx_PLUS (Pmode
, base
, offset
);
4975 /* Find a spare register to use during the prolog of a function. */
4978 thumb_find_work_register (unsigned long pushed_regs_mask
)
4982 /* Check the argument registers first as these are call-used. The
4983 register allocation order means that sometimes r3 might be used
4984 but earlier argument registers might not, so check them all. */
4985 for (reg
= LAST_ARG_REGNUM
; reg
>= 0; reg
--)
4986 if (!df_regs_ever_live_p (reg
))
4989 /* Before going on to check the call-saved registers we can try a couple
4990 more ways of deducing that r3 is available. The first is when we are
4991 pushing anonymous arguments onto the stack and we have less than 4
4992 registers worth of fixed arguments(*). In this case r3 will be part of
4993 the variable argument list and so we can be sure that it will be
4994 pushed right at the start of the function. Hence it will be available
4995 for the rest of the prologue.
4996 (*): ie crtl->args.pretend_args_size is greater than 0. */
4997 if (cfun
->machine
->uses_anonymous_args
4998 && crtl
->args
.pretend_args_size
> 0)
4999 return LAST_ARG_REGNUM
;
5001 /* The other case is when we have fixed arguments but less than 4 registers
5002 worth. In this case r3 might be used in the body of the function, but
5003 it is not being used to convey an argument into the function. In theory
5004 we could just check crtl->args.size to see how many bytes are
5005 being passed in argument registers, but it seems that it is unreliable.
5006 Sometimes it will have the value 0 when in fact arguments are being
5007 passed. (See testcase execute/20021111-1.c for an example). So we also
5008 check the args_info.nregs field as well. The problem with this field is
5009 that it makes no allowances for arguments that are passed to the
5010 function but which are not used. Hence we could miss an opportunity
5011 when a function has an unused argument in r3. But it is better to be
5012 safe than to be sorry. */
5013 if (! cfun
->machine
->uses_anonymous_args
5014 && crtl
->args
.size
>= 0
5015 && crtl
->args
.size
<= (LAST_ARG_REGNUM
* UNITS_PER_WORD
)
5016 && crtl
->args
.info
.nregs
< 4)
5017 return LAST_ARG_REGNUM
;
5019 /* Otherwise look for a call-saved register that is going to be pushed. */
5020 for (reg
= LAST_LO_REGNUM
; reg
> LAST_ARG_REGNUM
; reg
--)
5021 if (pushed_regs_mask
& (1 << reg
))
5026 /* Thumb-2 can use high regs. */
5027 for (reg
= FIRST_HI_REGNUM
; reg
< 15; reg
++)
5028 if (pushed_regs_mask
& (1 << reg
))
5031 /* Something went wrong - thumb_compute_save_reg_mask()
5032 should have arranged for a suitable register to be pushed. */
5036 static GTY(()) int pic_labelno
;
5038 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
5042 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED
)
5044 rtx l1
, labelno
, pic_tmp
, pic_rtx
, pic_reg
;
5046 if (crtl
->uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
5049 gcc_assert (flag_pic
);
5051 pic_reg
= cfun
->machine
->pic_reg
;
5052 if (TARGET_VXWORKS_RTP
)
5054 pic_rtx
= gen_rtx_SYMBOL_REF (Pmode
, VXWORKS_GOTT_BASE
);
5055 pic_rtx
= gen_rtx_CONST (Pmode
, pic_rtx
);
5056 emit_insn (gen_pic_load_addr_32bit (pic_reg
, pic_rtx
));
5058 emit_insn (gen_rtx_SET (Pmode
, pic_reg
, gen_rtx_MEM (Pmode
, pic_reg
)));
5060 pic_tmp
= gen_rtx_SYMBOL_REF (Pmode
, VXWORKS_GOTT_INDEX
);
5061 emit_insn (gen_pic_offset_arm (pic_reg
, pic_reg
, pic_tmp
));
5065 /* We use an UNSPEC rather than a LABEL_REF because this label
5066 never appears in the code stream. */
5068 labelno
= GEN_INT (pic_labelno
++);
5069 l1
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
5070 l1
= gen_rtx_CONST (VOIDmode
, l1
);
5072 /* On the ARM the PC register contains 'dot + 8' at the time of the
5073 addition, on the Thumb it is 'dot + 4'. */
5074 pic_rtx
= plus_constant (l1
, TARGET_ARM
? 8 : 4);
5075 pic_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, pic_rtx
),
5077 pic_rtx
= gen_rtx_CONST (Pmode
, pic_rtx
);
5081 emit_insn (gen_pic_load_addr_32bit (pic_reg
, pic_rtx
));
5083 emit_insn (gen_pic_add_dot_plus_eight (pic_reg
, pic_reg
, labelno
));
5085 emit_insn (gen_pic_add_dot_plus_four (pic_reg
, pic_reg
, labelno
));
5087 else /* TARGET_THUMB1 */
5089 if (arm_pic_register
!= INVALID_REGNUM
5090 && REGNO (pic_reg
) > LAST_LO_REGNUM
)
5092 /* We will have pushed the pic register, so we should always be
5093 able to find a work register. */
5094 pic_tmp
= gen_rtx_REG (SImode
,
5095 thumb_find_work_register (saved_regs
));
5096 emit_insn (gen_pic_load_addr_thumb1 (pic_tmp
, pic_rtx
));
5097 emit_insn (gen_movsi (pic_offset_table_rtx
, pic_tmp
));
5100 emit_insn (gen_pic_load_addr_thumb1 (pic_reg
, pic_rtx
));
5101 emit_insn (gen_pic_add_dot_plus_four (pic_reg
, pic_reg
, labelno
));
5105 /* Need to emit this whether or not we obey regdecls,
5106 since setjmp/longjmp can cause life info to screw up. */
5110 /* Generate code to load the address of a static var when flag_pic is set. */
5112 arm_pic_static_addr (rtx orig
, rtx reg
)
5114 rtx l1
, labelno
, offset_rtx
, insn
;
5116 gcc_assert (flag_pic
);
5118 /* We use an UNSPEC rather than a LABEL_REF because this label
5119 never appears in the code stream. */
5120 labelno
= GEN_INT (pic_labelno
++);
5121 l1
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
5122 l1
= gen_rtx_CONST (VOIDmode
, l1
);
5124 /* On the ARM the PC register contains 'dot + 8' at the time of the
5125 addition, on the Thumb it is 'dot + 4'. */
5126 offset_rtx
= plus_constant (l1
, TARGET_ARM
? 8 : 4);
5127 offset_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, orig
, offset_rtx
),
5128 UNSPEC_SYMBOL_OFFSET
);
5129 offset_rtx
= gen_rtx_CONST (Pmode
, offset_rtx
);
5133 emit_insn (gen_pic_load_addr_32bit (reg
, offset_rtx
));
5135 insn
= emit_insn (gen_pic_add_dot_plus_eight (reg
, reg
, labelno
));
5137 insn
= emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
5139 else /* TARGET_THUMB1 */
5141 emit_insn (gen_pic_load_addr_thumb1 (reg
, offset_rtx
));
5142 insn
= emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
5148 /* Return nonzero if X is valid as an ARM state addressing register. */
5150 arm_address_register_rtx_p (rtx x
, int strict_p
)
5154 if (GET_CODE (x
) != REG
)
5160 return ARM_REGNO_OK_FOR_BASE_P (regno
);
5162 return (regno
<= LAST_ARM_REGNUM
5163 || regno
>= FIRST_PSEUDO_REGISTER
5164 || regno
== FRAME_POINTER_REGNUM
5165 || regno
== ARG_POINTER_REGNUM
);
5168 /* Return TRUE if this rtx is the difference of a symbol and a label,
5169 and will reduce to a PC-relative relocation in the object file.
5170 Expressions like this can be left alone when generating PIC, rather
5171 than forced through the GOT. */
5173 pcrel_constant_p (rtx x
)
5175 if (GET_CODE (x
) == MINUS
)
5176 return symbol_mentioned_p (XEXP (x
, 0)) && label_mentioned_p (XEXP (x
, 1));
5181 /* Return true if X will surely end up in an index register after next
5184 will_be_in_index_register (const_rtx x
)
5186 /* arm.md: calculate_pic_address will split this into a register. */
5187 return GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_PIC_SYM
;
5190 /* Return nonzero if X is a valid ARM state address operand. */
5192 arm_legitimate_address_outer_p (enum machine_mode mode
, rtx x
, RTX_CODE outer
,
5196 enum rtx_code code
= GET_CODE (x
);
5198 if (arm_address_register_rtx_p (x
, strict_p
))
5201 use_ldrd
= (TARGET_LDRD
5203 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
5205 if (code
== POST_INC
|| code
== PRE_DEC
5206 || ((code
== PRE_INC
|| code
== POST_DEC
)
5207 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
5208 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
5210 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
5211 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
5212 && GET_CODE (XEXP (x
, 1)) == PLUS
5213 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5215 rtx addend
= XEXP (XEXP (x
, 1), 1);
5217 /* Don't allow ldrd post increment by register because it's hard
5218 to fixup invalid register choices. */
5220 && GET_CODE (x
) == POST_MODIFY
5221 && GET_CODE (addend
) == REG
)
5224 return ((use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)
5225 && arm_legitimate_index_p (mode
, addend
, outer
, strict_p
));
5228 /* After reload constants split into minipools will have addresses
5229 from a LABEL_REF. */
5230 else if (reload_completed
5231 && (code
== LABEL_REF
5233 && GET_CODE (XEXP (x
, 0)) == PLUS
5234 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
5235 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5238 else if (mode
== TImode
|| (TARGET_NEON
&& VALID_NEON_STRUCT_MODE (mode
)))
5241 else if (code
== PLUS
)
5243 rtx xop0
= XEXP (x
, 0);
5244 rtx xop1
= XEXP (x
, 1);
5246 return ((arm_address_register_rtx_p (xop0
, strict_p
)
5247 && ((GET_CODE(xop1
) == CONST_INT
5248 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
))
5249 || (!strict_p
&& will_be_in_index_register (xop1
))))
5250 || (arm_address_register_rtx_p (xop1
, strict_p
)
5251 && arm_legitimate_index_p (mode
, xop0
, outer
, strict_p
)));
5255 /* Reload currently can't handle MINUS, so disable this for now */
5256 else if (GET_CODE (x
) == MINUS
)
5258 rtx xop0
= XEXP (x
, 0);
5259 rtx xop1
= XEXP (x
, 1);
5261 return (arm_address_register_rtx_p (xop0
, strict_p
)
5262 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
));
5266 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
5267 && code
== SYMBOL_REF
5268 && CONSTANT_POOL_ADDRESS_P (x
)
5270 && symbol_mentioned_p (get_pool_constant (x
))
5271 && ! pcrel_constant_p (get_pool_constant (x
))))
5277 /* Return nonzero if X is a valid Thumb-2 address operand. */
5279 thumb2_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
5282 enum rtx_code code
= GET_CODE (x
);
5284 if (arm_address_register_rtx_p (x
, strict_p
))
5287 use_ldrd
= (TARGET_LDRD
5289 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
5291 if (code
== POST_INC
|| code
== PRE_DEC
5292 || ((code
== PRE_INC
|| code
== POST_DEC
)
5293 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
5294 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
5296 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
5297 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
5298 && GET_CODE (XEXP (x
, 1)) == PLUS
5299 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5301 /* Thumb-2 only has autoincrement by constant. */
5302 rtx addend
= XEXP (XEXP (x
, 1), 1);
5303 HOST_WIDE_INT offset
;
5305 if (GET_CODE (addend
) != CONST_INT
)
5308 offset
= INTVAL(addend
);
5309 if (GET_MODE_SIZE (mode
) <= 4)
5310 return (offset
> -256 && offset
< 256);
5312 return (use_ldrd
&& offset
> -1024 && offset
< 1024
5313 && (offset
& 3) == 0);
5316 /* After reload constants split into minipools will have addresses
5317 from a LABEL_REF. */
5318 else if (reload_completed
5319 && (code
== LABEL_REF
5321 && GET_CODE (XEXP (x
, 0)) == PLUS
5322 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
5323 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5326 else if (mode
== TImode
|| (TARGET_NEON
&& VALID_NEON_STRUCT_MODE (mode
)))
5329 else if (code
== PLUS
)
5331 rtx xop0
= XEXP (x
, 0);
5332 rtx xop1
= XEXP (x
, 1);
5334 return ((arm_address_register_rtx_p (xop0
, strict_p
)
5335 && (thumb2_legitimate_index_p (mode
, xop1
, strict_p
)
5336 || (!strict_p
&& will_be_in_index_register (xop1
))))
5337 || (arm_address_register_rtx_p (xop1
, strict_p
)
5338 && thumb2_legitimate_index_p (mode
, xop0
, strict_p
)));
5341 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
5342 && code
== SYMBOL_REF
5343 && CONSTANT_POOL_ADDRESS_P (x
)
5345 && symbol_mentioned_p (get_pool_constant (x
))
5346 && ! pcrel_constant_p (get_pool_constant (x
))))
5352 /* Return nonzero if INDEX is valid for an address index operand in
5355 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, RTX_CODE outer
,
5358 HOST_WIDE_INT range
;
5359 enum rtx_code code
= GET_CODE (index
);
5361 /* Standard coprocessor addressing modes. */
5362 if (TARGET_HARD_FLOAT
5363 && (TARGET_VFP
|| TARGET_FPA
|| TARGET_MAVERICK
)
5364 && (mode
== SFmode
|| mode
== DFmode
5365 || (TARGET_MAVERICK
&& mode
== DImode
)))
5366 return (code
== CONST_INT
&& INTVAL (index
) < 1024
5367 && INTVAL (index
) > -1024
5368 && (INTVAL (index
) & 3) == 0);
5370 /* For quad modes, we restrict the constant offset to be slightly less
5371 than what the instruction format permits. We do this because for
5372 quad mode moves, we will actually decompose them into two separate
5373 double-mode reads or writes. INDEX must therefore be a valid
5374 (double-mode) offset and so should INDEX+8. */
5375 if (TARGET_NEON
&& VALID_NEON_QREG_MODE (mode
))
5376 return (code
== CONST_INT
5377 && INTVAL (index
) < 1016
5378 && INTVAL (index
) > -1024
5379 && (INTVAL (index
) & 3) == 0);
5381 /* We have no such constraint on double mode offsets, so we permit the
5382 full range of the instruction format. */
5383 if (TARGET_NEON
&& VALID_NEON_DREG_MODE (mode
))
5384 return (code
== CONST_INT
5385 && INTVAL (index
) < 1024
5386 && INTVAL (index
) > -1024
5387 && (INTVAL (index
) & 3) == 0);
5389 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
5390 return (code
== CONST_INT
5391 && INTVAL (index
) < 1024
5392 && INTVAL (index
) > -1024
5393 && (INTVAL (index
) & 3) == 0);
5395 if (arm_address_register_rtx_p (index
, strict_p
)
5396 && (GET_MODE_SIZE (mode
) <= 4))
5399 if (mode
== DImode
|| mode
== DFmode
)
5401 if (code
== CONST_INT
)
5403 HOST_WIDE_INT val
= INTVAL (index
);
5406 return val
> -256 && val
< 256;
5408 return val
> -4096 && val
< 4092;
5411 return TARGET_LDRD
&& arm_address_register_rtx_p (index
, strict_p
);
5414 if (GET_MODE_SIZE (mode
) <= 4
5418 || (mode
== QImode
&& outer
== SIGN_EXTEND
))))
5422 rtx xiop0
= XEXP (index
, 0);
5423 rtx xiop1
= XEXP (index
, 1);
5425 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
5426 && power_of_two_operand (xiop1
, SImode
))
5427 || (arm_address_register_rtx_p (xiop1
, strict_p
)
5428 && power_of_two_operand (xiop0
, SImode
)));
5430 else if (code
== LSHIFTRT
|| code
== ASHIFTRT
5431 || code
== ASHIFT
|| code
== ROTATERT
)
5433 rtx op
= XEXP (index
, 1);
5435 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
5436 && GET_CODE (op
) == CONST_INT
5438 && INTVAL (op
) <= 31);
5442 /* For ARM v4 we may be doing a sign-extend operation during the
5448 || (outer
== SIGN_EXTEND
&& mode
== QImode
))
5454 range
= (mode
== HImode
|| mode
== HFmode
) ? 4095 : 4096;
5456 return (code
== CONST_INT
5457 && INTVAL (index
) < range
5458 && INTVAL (index
) > -range
);
5461 /* Return true if OP is a valid index scaling factor for Thumb-2 address
5462 index operand. i.e. 1, 2, 4 or 8. */
5464 thumb2_index_mul_operand (rtx op
)
5468 if (GET_CODE(op
) != CONST_INT
)
5472 return (val
== 1 || val
== 2 || val
== 4 || val
== 8);
5475 /* Return nonzero if INDEX is a valid Thumb-2 address index operand. */
5477 thumb2_legitimate_index_p (enum machine_mode mode
, rtx index
, int strict_p
)
5479 enum rtx_code code
= GET_CODE (index
);
5481 /* ??? Combine arm and thumb2 coprocessor addressing modes. */
5482 /* Standard coprocessor addressing modes. */
5483 if (TARGET_HARD_FLOAT
5484 && (TARGET_VFP
|| TARGET_FPA
|| TARGET_MAVERICK
)
5485 && (mode
== SFmode
|| mode
== DFmode
5486 || (TARGET_MAVERICK
&& mode
== DImode
)))
5487 return (code
== CONST_INT
&& INTVAL (index
) < 1024
5488 /* Thumb-2 allows only > -256 index range for it's core register
5489 load/stores. Since we allow SF/DF in core registers, we have
5490 to use the intersection between -256~4096 (core) and -1024~1024
5492 && INTVAL (index
) > -256
5493 && (INTVAL (index
) & 3) == 0);
5495 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
5497 /* For DImode assume values will usually live in core regs
5498 and only allow LDRD addressing modes. */
5499 if (!TARGET_LDRD
|| mode
!= DImode
)
5500 return (code
== CONST_INT
5501 && INTVAL (index
) < 1024
5502 && INTVAL (index
) > -1024
5503 && (INTVAL (index
) & 3) == 0);
5506 /* For quad modes, we restrict the constant offset to be slightly less
5507 than what the instruction format permits. We do this because for
5508 quad mode moves, we will actually decompose them into two separate
5509 double-mode reads or writes. INDEX must therefore be a valid
5510 (double-mode) offset and so should INDEX+8. */
5511 if (TARGET_NEON
&& VALID_NEON_QREG_MODE (mode
))
5512 return (code
== CONST_INT
5513 && INTVAL (index
) < 1016
5514 && INTVAL (index
) > -1024
5515 && (INTVAL (index
) & 3) == 0);
5517 /* We have no such constraint on double mode offsets, so we permit the
5518 full range of the instruction format. */
5519 if (TARGET_NEON
&& VALID_NEON_DREG_MODE (mode
))
5520 return (code
== CONST_INT
5521 && INTVAL (index
) < 1024
5522 && INTVAL (index
) > -1024
5523 && (INTVAL (index
) & 3) == 0);
5525 if (arm_address_register_rtx_p (index
, strict_p
)
5526 && (GET_MODE_SIZE (mode
) <= 4))
5529 if (mode
== DImode
|| mode
== DFmode
)
5531 if (code
== CONST_INT
)
5533 HOST_WIDE_INT val
= INTVAL (index
);
5534 /* ??? Can we assume ldrd for thumb2? */
5535 /* Thumb-2 ldrd only has reg+const addressing modes. */
5536 /* ldrd supports offsets of +-1020.
5537 However the ldr fallback does not. */
5538 return val
> -256 && val
< 256 && (val
& 3) == 0;
5546 rtx xiop0
= XEXP (index
, 0);
5547 rtx xiop1
= XEXP (index
, 1);
5549 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
5550 && thumb2_index_mul_operand (xiop1
))
5551 || (arm_address_register_rtx_p (xiop1
, strict_p
)
5552 && thumb2_index_mul_operand (xiop0
)));
5554 else if (code
== ASHIFT
)
5556 rtx op
= XEXP (index
, 1);
5558 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
5559 && GET_CODE (op
) == CONST_INT
5561 && INTVAL (op
) <= 3);
5564 return (code
== CONST_INT
5565 && INTVAL (index
) < 4096
5566 && INTVAL (index
) > -256);
5569 /* Return nonzero if X is valid as a 16-bit Thumb state base register. */
5571 thumb1_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
5575 if (GET_CODE (x
) != REG
)
5581 return THUMB1_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
5583 return (regno
<= LAST_LO_REGNUM
5584 || regno
> LAST_VIRTUAL_REGISTER
5585 || regno
== FRAME_POINTER_REGNUM
5586 || (GET_MODE_SIZE (mode
) >= 4
5587 && (regno
== STACK_POINTER_REGNUM
5588 || regno
>= FIRST_PSEUDO_REGISTER
5589 || x
== hard_frame_pointer_rtx
5590 || x
== arg_pointer_rtx
)));
5593 /* Return nonzero if x is a legitimate index register. This is the case
5594 for any base register that can access a QImode object. */
5596 thumb1_index_register_rtx_p (rtx x
, int strict_p
)
5598 return thumb1_base_register_rtx_p (x
, QImode
, strict_p
);
5601 /* Return nonzero if x is a legitimate 16-bit Thumb-state address.
5603 The AP may be eliminated to either the SP or the FP, so we use the
5604 least common denominator, e.g. SImode, and offsets from 0 to 64.
5606 ??? Verify whether the above is the right approach.
5608 ??? Also, the FP may be eliminated to the SP, so perhaps that
5609 needs special handling also.
5611 ??? Look at how the mips16 port solves this problem. It probably uses
5612 better ways to solve some of these problems.
5614 Although it is not incorrect, we don't accept QImode and HImode
5615 addresses based on the frame pointer or arg pointer until the
5616 reload pass starts. This is so that eliminating such addresses
5617 into stack based ones won't produce impossible code. */
5619 thumb1_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
5621 /* ??? Not clear if this is right. Experiment. */
5622 if (GET_MODE_SIZE (mode
) < 4
5623 && !(reload_in_progress
|| reload_completed
)
5624 && (reg_mentioned_p (frame_pointer_rtx
, x
)
5625 || reg_mentioned_p (arg_pointer_rtx
, x
)
5626 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
5627 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
5628 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
5629 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
5632 /* Accept any base register. SP only in SImode or larger. */
5633 else if (thumb1_base_register_rtx_p (x
, mode
, strict_p
))
5636 /* This is PC relative data before arm_reorg runs. */
5637 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
5638 && GET_CODE (x
) == SYMBOL_REF
5639 && CONSTANT_POOL_ADDRESS_P (x
) && !flag_pic
)
5642 /* This is PC relative data after arm_reorg runs. */
5643 else if ((GET_MODE_SIZE (mode
) >= 4 || mode
== HFmode
)
5645 && (GET_CODE (x
) == LABEL_REF
5646 || (GET_CODE (x
) == CONST
5647 && GET_CODE (XEXP (x
, 0)) == PLUS
5648 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
5649 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5652 /* Post-inc indexing only supported for SImode and larger. */
5653 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
5654 && thumb1_index_register_rtx_p (XEXP (x
, 0), strict_p
))
5657 else if (GET_CODE (x
) == PLUS
)
5659 /* REG+REG address can be any two index registers. */
5660 /* We disallow FRAME+REG addressing since we know that FRAME
5661 will be replaced with STACK, and SP relative addressing only
5662 permits SP+OFFSET. */
5663 if (GET_MODE_SIZE (mode
) <= 4
5664 && XEXP (x
, 0) != frame_pointer_rtx
5665 && XEXP (x
, 1) != frame_pointer_rtx
5666 && thumb1_index_register_rtx_p (XEXP (x
, 0), strict_p
)
5667 && (thumb1_index_register_rtx_p (XEXP (x
, 1), strict_p
)
5668 || (!strict_p
&& will_be_in_index_register (XEXP (x
, 1)))))
5671 /* REG+const has 5-7 bit offset for non-SP registers. */
5672 else if ((thumb1_index_register_rtx_p (XEXP (x
, 0), strict_p
)
5673 || XEXP (x
, 0) == arg_pointer_rtx
)
5674 && GET_CODE (XEXP (x
, 1)) == CONST_INT
5675 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
5678 /* REG+const has 10-bit offset for SP, but only SImode and
5679 larger is supported. */
5680 /* ??? Should probably check for DI/DFmode overflow here
5681 just like GO_IF_LEGITIMATE_OFFSET does. */
5682 else if (GET_CODE (XEXP (x
, 0)) == REG
5683 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
5684 && GET_MODE_SIZE (mode
) >= 4
5685 && GET_CODE (XEXP (x
, 1)) == CONST_INT
5686 && INTVAL (XEXP (x
, 1)) >= 0
5687 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
5688 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
5691 else if (GET_CODE (XEXP (x
, 0)) == REG
5692 && (REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
5693 || REGNO (XEXP (x
, 0)) == ARG_POINTER_REGNUM
5694 || (REGNO (XEXP (x
, 0)) >= FIRST_VIRTUAL_REGISTER
5695 && REGNO (XEXP (x
, 0))
5696 <= LAST_VIRTUAL_POINTER_REGISTER
))
5697 && GET_MODE_SIZE (mode
) >= 4
5698 && GET_CODE (XEXP (x
, 1)) == CONST_INT
5699 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
5703 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
5704 && GET_MODE_SIZE (mode
) == 4
5705 && GET_CODE (x
) == SYMBOL_REF
5706 && CONSTANT_POOL_ADDRESS_P (x
)
5708 && symbol_mentioned_p (get_pool_constant (x
))
5709 && ! pcrel_constant_p (get_pool_constant (x
))))
5715 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
5716 instruction of mode MODE. */
5718 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
5720 switch (GET_MODE_SIZE (mode
))
5723 return val
>= 0 && val
< 32;
5726 return val
>= 0 && val
< 64 && (val
& 1) == 0;
5730 && (val
+ GET_MODE_SIZE (mode
)) <= 128
5736 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
5739 return arm_legitimate_address_outer_p (mode
, x
, SET
, strict_p
);
5740 else if (TARGET_THUMB2
)
5741 return thumb2_legitimate_address_p (mode
, x
, strict_p
);
5742 else /* if (TARGET_THUMB1) */
5743 return thumb1_legitimate_address_p (mode
, x
, strict_p
);
5746 /* Build the SYMBOL_REF for __tls_get_addr. */
5748 static GTY(()) rtx tls_get_addr_libfunc
;
5751 get_tls_get_addr (void)
5753 if (!tls_get_addr_libfunc
)
5754 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
5755 return tls_get_addr_libfunc
;
5759 arm_load_tp (rtx target
)
5762 target
= gen_reg_rtx (SImode
);
5766 /* Can return in any reg. */
5767 emit_insn (gen_load_tp_hard (target
));
5771 /* Always returned in r0. Immediately copy the result into a pseudo,
5772 otherwise other uses of r0 (e.g. setting up function arguments) may
5773 clobber the value. */
5777 emit_insn (gen_load_tp_soft ());
5779 tmp
= gen_rtx_REG (SImode
, 0);
5780 emit_move_insn (target
, tmp
);
5786 load_tls_operand (rtx x
, rtx reg
)
5790 if (reg
== NULL_RTX
)
5791 reg
= gen_reg_rtx (SImode
);
5793 tmp
= gen_rtx_CONST (SImode
, x
);
5795 emit_move_insn (reg
, tmp
);
5801 arm_call_tls_get_addr (rtx x
, rtx reg
, rtx
*valuep
, int reloc
)
5803 rtx insns
, label
, labelno
, sum
;
5807 labelno
= GEN_INT (pic_labelno
++);
5808 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
5809 label
= gen_rtx_CONST (VOIDmode
, label
);
5811 sum
= gen_rtx_UNSPEC (Pmode
,
5812 gen_rtvec (4, x
, GEN_INT (reloc
), label
,
5813 GEN_INT (TARGET_ARM
? 8 : 4)),
5815 reg
= load_tls_operand (sum
, reg
);
5818 emit_insn (gen_pic_add_dot_plus_eight (reg
, reg
, labelno
));
5819 else if (TARGET_THUMB2
)
5820 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
5821 else /* TARGET_THUMB1 */
5822 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
5824 *valuep
= emit_library_call_value (get_tls_get_addr (), NULL_RTX
, LCT_PURE
, /* LCT_CONST? */
5825 Pmode
, 1, reg
, Pmode
);
5827 insns
= get_insns ();
5834 legitimize_tls_address (rtx x
, rtx reg
)
5836 rtx dest
, tp
, label
, labelno
, sum
, insns
, ret
, eqv
, addend
;
5837 unsigned int model
= SYMBOL_REF_TLS_MODEL (x
);
5841 case TLS_MODEL_GLOBAL_DYNAMIC
:
5842 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_GD32
);
5843 dest
= gen_reg_rtx (Pmode
);
5844 emit_libcall_block (insns
, dest
, ret
, x
);
5847 case TLS_MODEL_LOCAL_DYNAMIC
:
5848 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_LDM32
);
5850 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
5851 share the LDM result with other LD model accesses. */
5852 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
),
5854 dest
= gen_reg_rtx (Pmode
);
5855 emit_libcall_block (insns
, dest
, ret
, eqv
);
5857 /* Load the addend. */
5858 addend
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (TLS_LDO32
)),
5860 addend
= force_reg (SImode
, gen_rtx_CONST (SImode
, addend
));
5861 return gen_rtx_PLUS (Pmode
, dest
, addend
);
5863 case TLS_MODEL_INITIAL_EXEC
:
5864 labelno
= GEN_INT (pic_labelno
++);
5865 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
5866 label
= gen_rtx_CONST (VOIDmode
, label
);
5867 sum
= gen_rtx_UNSPEC (Pmode
,
5868 gen_rtvec (4, x
, GEN_INT (TLS_IE32
), label
,
5869 GEN_INT (TARGET_ARM
? 8 : 4)),
5871 reg
= load_tls_operand (sum
, reg
);
5874 emit_insn (gen_tls_load_dot_plus_eight (reg
, reg
, labelno
));
5875 else if (TARGET_THUMB2
)
5876 emit_insn (gen_tls_load_dot_plus_four (reg
, NULL
, reg
, labelno
));
5879 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
5880 emit_move_insn (reg
, gen_const_mem (SImode
, reg
));
5883 tp
= arm_load_tp (NULL_RTX
);
5885 return gen_rtx_PLUS (Pmode
, tp
, reg
);
5887 case TLS_MODEL_LOCAL_EXEC
:
5888 tp
= arm_load_tp (NULL_RTX
);
5890 reg
= gen_rtx_UNSPEC (Pmode
,
5891 gen_rtvec (2, x
, GEN_INT (TLS_LE32
)),
5893 reg
= force_reg (SImode
, gen_rtx_CONST (SImode
, reg
));
5895 return gen_rtx_PLUS (Pmode
, tp
, reg
);
5902 /* Try machine-dependent ways of modifying an illegitimate address
5903 to be legitimate. If we find one, return the new, valid address. */
5905 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
5909 /* TODO: legitimize_address for Thumb2. */
5912 return thumb_legitimize_address (x
, orig_x
, mode
);
5915 if (arm_tls_symbol_p (x
))
5916 return legitimize_tls_address (x
, NULL_RTX
);
5918 if (GET_CODE (x
) == PLUS
)
5920 rtx xop0
= XEXP (x
, 0);
5921 rtx xop1
= XEXP (x
, 1);
5923 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
5924 xop0
= force_reg (SImode
, xop0
);
5926 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
5927 xop1
= force_reg (SImode
, xop1
);
5929 if (ARM_BASE_REGISTER_RTX_P (xop0
)
5930 && GET_CODE (xop1
) == CONST_INT
)
5932 HOST_WIDE_INT n
, low_n
;
5936 /* VFP addressing modes actually allow greater offsets, but for
5937 now we just stick with the lowest common denominator. */
5939 || ((TARGET_SOFT_FLOAT
|| TARGET_VFP
) && mode
== DFmode
))
5951 low_n
= ((mode
) == TImode
? 0
5952 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
5956 base_reg
= gen_reg_rtx (SImode
);
5957 val
= force_operand (plus_constant (xop0
, n
), NULL_RTX
);
5958 emit_move_insn (base_reg
, val
);
5959 x
= plus_constant (base_reg
, low_n
);
5961 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
5962 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
5965 /* XXX We don't allow MINUS any more -- see comment in
5966 arm_legitimate_address_outer_p (). */
5967 else if (GET_CODE (x
) == MINUS
)
5969 rtx xop0
= XEXP (x
, 0);
5970 rtx xop1
= XEXP (x
, 1);
5972 if (CONSTANT_P (xop0
))
5973 xop0
= force_reg (SImode
, xop0
);
5975 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
5976 xop1
= force_reg (SImode
, xop1
);
5978 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
5979 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
5982 /* Make sure to take full advantage of the pre-indexed addressing mode
5983 with absolute addresses which often allows for the base register to
5984 be factorized for multiple adjacent memory references, and it might
5985 even allows for the mini pool to be avoided entirely. */
5986 else if (GET_CODE (x
) == CONST_INT
&& optimize
> 0)
5989 HOST_WIDE_INT mask
, base
, index
;
5992 /* ldr and ldrb can use a 12-bit index, ldrsb and the rest can only
5993 use a 8-bit index. So let's use a 12-bit index for SImode only and
5994 hope that arm_gen_constant will enable ldrb to use more bits. */
5995 bits
= (mode
== SImode
) ? 12 : 8;
5996 mask
= (1 << bits
) - 1;
5997 base
= INTVAL (x
) & ~mask
;
5998 index
= INTVAL (x
) & mask
;
5999 if (bit_count (base
& 0xffffffff) > (32 - bits
)/2)
6001 /* It'll most probably be more efficient to generate the base
6002 with more bits set and use a negative index instead. */
6006 base_reg
= force_reg (SImode
, GEN_INT (base
));
6007 x
= plus_constant (base_reg
, index
);
6012 /* We need to find and carefully transform any SYMBOL and LABEL
6013 references; so go back to the original address expression. */
6014 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
6016 if (new_x
!= orig_x
)
6024 /* Try machine-dependent ways of modifying an illegitimate Thumb address
6025 to be legitimate. If we find one, return the new, valid address. */
6027 thumb_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
6029 if (arm_tls_symbol_p (x
))
6030 return legitimize_tls_address (x
, NULL_RTX
);
6032 if (GET_CODE (x
) == PLUS
6033 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6034 && (INTVAL (XEXP (x
, 1)) >= 32 * GET_MODE_SIZE (mode
)
6035 || INTVAL (XEXP (x
, 1)) < 0))
6037 rtx xop0
= XEXP (x
, 0);
6038 rtx xop1
= XEXP (x
, 1);
6039 HOST_WIDE_INT offset
= INTVAL (xop1
);
6041 /* Try and fold the offset into a biasing of the base register and
6042 then offsetting that. Don't do this when optimizing for space
6043 since it can cause too many CSEs. */
6044 if (optimize_size
&& offset
>= 0
6045 && offset
< 256 + 31 * GET_MODE_SIZE (mode
))
6047 HOST_WIDE_INT delta
;
6050 delta
= offset
- (256 - GET_MODE_SIZE (mode
));
6051 else if (offset
< 32 * GET_MODE_SIZE (mode
) + 8)
6052 delta
= 31 * GET_MODE_SIZE (mode
);
6054 delta
= offset
& (~31 * GET_MODE_SIZE (mode
));
6056 xop0
= force_operand (plus_constant (xop0
, offset
- delta
),
6058 x
= plus_constant (xop0
, delta
);
6060 else if (offset
< 0 && offset
> -256)
6061 /* Small negative offsets are best done with a subtract before the
6062 dereference, forcing these into a register normally takes two
6064 x
= force_operand (x
, NULL_RTX
);
6067 /* For the remaining cases, force the constant into a register. */
6068 xop1
= force_reg (SImode
, xop1
);
6069 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
6072 else if (GET_CODE (x
) == PLUS
6073 && s_register_operand (XEXP (x
, 1), SImode
)
6074 && !s_register_operand (XEXP (x
, 0), SImode
))
6076 rtx xop0
= force_operand (XEXP (x
, 0), NULL_RTX
);
6078 x
= gen_rtx_PLUS (SImode
, xop0
, XEXP (x
, 1));
6083 /* We need to find and carefully transform any SYMBOL and LABEL
6084 references; so go back to the original address expression. */
6085 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
6087 if (new_x
!= orig_x
)
6095 arm_legitimize_reload_address (rtx
*p
,
6096 enum machine_mode mode
,
6097 int opnum
, int type
,
6098 int ind_levels ATTRIBUTE_UNUSED
)
6100 if (GET_CODE (*p
) == PLUS
6101 && GET_CODE (XEXP (*p
, 0)) == REG
6102 && ARM_REGNO_OK_FOR_BASE_P (REGNO (XEXP (*p
, 0)))
6103 && GET_CODE (XEXP (*p
, 1)) == CONST_INT
)
6105 HOST_WIDE_INT val
= INTVAL (XEXP (*p
, 1));
6106 HOST_WIDE_INT low
, high
;
6108 /* Detect coprocessor load/stores. */
6109 bool coproc_p
= ((TARGET_HARD_FLOAT
6110 && (TARGET_VFP
|| TARGET_FPA
|| TARGET_MAVERICK
)
6111 && (mode
== SFmode
|| mode
== DFmode
6112 || (mode
== DImode
&& TARGET_MAVERICK
)))
6113 || (TARGET_REALLY_IWMMXT
6114 && VALID_IWMMXT_REG_MODE (mode
))
6116 && (VALID_NEON_DREG_MODE (mode
)
6117 || VALID_NEON_QREG_MODE (mode
))));
6119 /* For some conditions, bail out when lower two bits are unaligned. */
6120 if ((val
& 0x3) != 0
6121 /* Coprocessor load/store indexes are 8-bits + '00' appended. */
6123 /* For DI, and DF under soft-float: */
6124 || ((mode
== DImode
|| mode
== DFmode
)
6125 /* Without ldrd, we use stm/ldm, which does not
6126 fair well with unaligned bits. */
6128 /* Thumb-2 ldrd/strd is [-1020,+1020] in steps of 4. */
6129 || TARGET_THUMB2
))))
6132 /* When breaking down a [reg+index] reload address into [(reg+high)+low],
6133 of which the (reg+high) gets turned into a reload add insn,
6134 we try to decompose the index into high/low values that can often
6135 also lead to better reload CSE.
6137 ldr r0, [r2, #4100] // Offset too large
6138 ldr r1, [r2, #4104] // Offset too large
6140 is best reloaded as:
6146 which post-reload CSE can simplify in most cases to eliminate the
6147 second add instruction:
6152 The idea here is that we want to split out the bits of the constant
6153 as a mask, rather than as subtracting the maximum offset that the
6154 respective type of load/store used can handle.
6156 When encountering negative offsets, we can still utilize it even if
6157 the overall offset is positive; sometimes this may lead to an immediate
6158 that can be constructed with fewer instructions.
6160 ldr r0, [r2, #0x3FFFFC]
6162 This is best reloaded as:
6163 add t1, r2, #0x400000
6166 The trick for spotting this for a load insn with N bits of offset
6167 (i.e. bits N-1:0) is to look at bit N; if it is set, then chose a
6168 negative offset that is going to make bit N and all the bits below
6169 it become zero in the remainder part.
6171 The SIGN_MAG_LOW_ADDR_BITS macro below implements this, with respect
6172 to sign-magnitude addressing (i.e. separate +- bit, or 1's complement),
6173 used in most cases of ARM load/store instructions. */
6175 #define SIGN_MAG_LOW_ADDR_BITS(VAL, N) \
6176 (((VAL) & ((1 << (N)) - 1)) \
6177 ? (((VAL) & ((1 << ((N) + 1)) - 1)) ^ (1 << (N))) - (1 << (N)) \
6182 low
= SIGN_MAG_LOW_ADDR_BITS (val
, 10);
6184 /* NEON quad-word load/stores are made of two double-word accesses,
6185 so the valid index range is reduced by 8. Treat as 9-bit range if
6187 if (TARGET_NEON
&& VALID_NEON_QREG_MODE (mode
) && low
>= 1016)
6188 low
= SIGN_MAG_LOW_ADDR_BITS (val
, 9);
6190 else if (GET_MODE_SIZE (mode
) == 8)
6193 low
= (TARGET_THUMB2
6194 ? SIGN_MAG_LOW_ADDR_BITS (val
, 10)
6195 : SIGN_MAG_LOW_ADDR_BITS (val
, 8));
6197 /* For pre-ARMv5TE (without ldrd), we use ldm/stm(db/da/ib)
6198 to access doublewords. The supported load/store offsets are
6199 -8, -4, and 4, which we try to produce here. */
6200 low
= ((val
& 0xf) ^ 0x8) - 0x8;
6202 else if (GET_MODE_SIZE (mode
) < 8)
6204 /* NEON element load/stores do not have an offset. */
6205 if (TARGET_NEON_FP16
&& mode
== HFmode
)
6210 /* Thumb-2 has an asymmetrical index range of (-256,4096).
6211 Try the wider 12-bit range first, and re-try if the result
6213 low
= SIGN_MAG_LOW_ADDR_BITS (val
, 12);
6215 low
= SIGN_MAG_LOW_ADDR_BITS (val
, 8);
6219 if (mode
== HImode
|| mode
== HFmode
)
6222 low
= SIGN_MAG_LOW_ADDR_BITS (val
, 8);
6225 /* The storehi/movhi_bytes fallbacks can use only
6226 [-4094,+4094] of the full ldrb/strb index range. */
6227 low
= SIGN_MAG_LOW_ADDR_BITS (val
, 12);
6228 if (low
== 4095 || low
== -4095)
6233 low
= SIGN_MAG_LOW_ADDR_BITS (val
, 12);
6239 high
= ((((val
- low
) & (unsigned HOST_WIDE_INT
) 0xffffffff)
6240 ^ (unsigned HOST_WIDE_INT
) 0x80000000)
6241 - (unsigned HOST_WIDE_INT
) 0x80000000);
6242 /* Check for overflow or zero */
6243 if (low
== 0 || high
== 0 || (high
+ low
!= val
))
6246 /* Reload the high part into a base reg; leave the low part
6248 *p
= gen_rtx_PLUS (GET_MODE (*p
),
6249 gen_rtx_PLUS (GET_MODE (*p
), XEXP (*p
, 0),
6252 push_reload (XEXP (*p
, 0), NULL_RTX
, &XEXP (*p
, 0), NULL
,
6253 MODE_BASE_REG_CLASS (mode
), GET_MODE (*p
),
6254 VOIDmode
, 0, 0, opnum
, (enum reload_type
) type
);
6262 thumb_legitimize_reload_address (rtx
*x_p
,
6263 enum machine_mode mode
,
6264 int opnum
, int type
,
6265 int ind_levels ATTRIBUTE_UNUSED
)
6269 if (GET_CODE (x
) == PLUS
6270 && GET_MODE_SIZE (mode
) < 4
6271 && REG_P (XEXP (x
, 0))
6272 && XEXP (x
, 0) == stack_pointer_rtx
6273 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6274 && !thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
6279 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
6280 Pmode
, VOIDmode
, 0, 0, opnum
, (enum reload_type
) type
);
6284 /* If both registers are hi-regs, then it's better to reload the
6285 entire expression rather than each register individually. That
6286 only requires one reload register rather than two. */
6287 if (GET_CODE (x
) == PLUS
6288 && REG_P (XEXP (x
, 0))
6289 && REG_P (XEXP (x
, 1))
6290 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 0), mode
)
6291 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 1), mode
))
6296 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
6297 Pmode
, VOIDmode
, 0, 0, opnum
, (enum reload_type
) type
);
6304 /* Test for various thread-local symbols. */
6306 /* Return TRUE if X is a thread-local symbol. */
6309 arm_tls_symbol_p (rtx x
)
6311 if (! TARGET_HAVE_TLS
)
6314 if (GET_CODE (x
) != SYMBOL_REF
)
6317 return SYMBOL_REF_TLS_MODEL (x
) != 0;
6320 /* Helper for arm_tls_referenced_p. */
6323 arm_tls_operand_p_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
6325 if (GET_CODE (*x
) == SYMBOL_REF
)
6326 return SYMBOL_REF_TLS_MODEL (*x
) != 0;
6328 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
6329 TLS offsets, not real symbol references. */
6330 if (GET_CODE (*x
) == UNSPEC
6331 && XINT (*x
, 1) == UNSPEC_TLS
)
6337 /* Return TRUE if X contains any TLS symbol references. */
6340 arm_tls_referenced_p (rtx x
)
6342 if (! TARGET_HAVE_TLS
)
6345 return for_each_rtx (&x
, arm_tls_operand_p_1
, NULL
);
6348 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
6350 On the ARM, allow any integer (invalid ones are removed later by insn
6351 patterns), nice doubles and symbol_refs which refer to the function's
6354 When generating pic allow anything. */
6357 arm_legitimate_constant_p_1 (enum machine_mode mode
, rtx x
)
6359 /* At present, we have no support for Neon structure constants, so forbid
6360 them here. It might be possible to handle simple cases like 0 and -1
6362 if (TARGET_NEON
&& VALID_NEON_STRUCT_MODE (mode
))
6365 return flag_pic
|| !label_mentioned_p (x
);
6369 thumb_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
6371 return (GET_CODE (x
) == CONST_INT
6372 || GET_CODE (x
) == CONST_DOUBLE
6373 || CONSTANT_ADDRESS_P (x
)
6378 arm_legitimate_constant_p (enum machine_mode mode
, rtx x
)
6380 return (!arm_cannot_force_const_mem (mode
, x
)
6382 ? arm_legitimate_constant_p_1 (mode
, x
)
6383 : thumb_legitimate_constant_p (mode
, x
)));
6386 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
6389 arm_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
6393 if (ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
6395 split_const (x
, &base
, &offset
);
6396 if (GET_CODE (base
) == SYMBOL_REF
6397 && !offset_within_block_p (base
, INTVAL (offset
)))
6400 return arm_tls_referenced_p (x
);
6403 #define REG_OR_SUBREG_REG(X) \
6404 (GET_CODE (X) == REG \
6405 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
6407 #define REG_OR_SUBREG_RTX(X) \
6408 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
6411 thumb1_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
6413 enum machine_mode mode
= GET_MODE (x
);
6427 return COSTS_N_INSNS (1);
6430 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6433 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
6440 return COSTS_N_INSNS (2) + cycles
;
6442 return COSTS_N_INSNS (1) + 16;
6445 return (COSTS_N_INSNS (1)
6446 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
6447 + GET_CODE (SET_DEST (x
)) == MEM
));
6452 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
6454 if (thumb_shiftable_const (INTVAL (x
)))
6455 return COSTS_N_INSNS (2);
6456 return COSTS_N_INSNS (3);
6458 else if ((outer
== PLUS
|| outer
== COMPARE
)
6459 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
6461 else if ((outer
== IOR
|| outer
== XOR
|| outer
== AND
)
6462 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
6463 return COSTS_N_INSNS (1);
6464 else if (outer
== AND
)
6467 /* This duplicates the tests in the andsi3 expander. */
6468 for (i
= 9; i
<= 31; i
++)
6469 if ((((HOST_WIDE_INT
) 1) << i
) - 1 == INTVAL (x
)
6470 || (((HOST_WIDE_INT
) 1) << i
) - 1 == ~INTVAL (x
))
6471 return COSTS_N_INSNS (2);
6473 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
6474 || outer
== LSHIFTRT
)
6476 return COSTS_N_INSNS (2);
6482 return COSTS_N_INSNS (3);
6500 /* XXX another guess. */
6501 /* Memory costs quite a lot for the first word, but subsequent words
6502 load at the equivalent of a single insn each. */
6503 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
6504 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
6509 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
6515 total
= mode
== DImode
? COSTS_N_INSNS (1) : 0;
6516 total
+= thumb1_rtx_costs (XEXP (x
, 0), GET_CODE (XEXP (x
, 0)), code
);
6522 return total
+ COSTS_N_INSNS (1);
6524 /* Assume a two-shift sequence. Increase the cost slightly so
6525 we prefer actual shifts over an extend operation. */
6526 return total
+ 1 + COSTS_N_INSNS (2);
6534 arm_rtx_costs_1 (rtx x
, enum rtx_code outer
, int* total
, bool speed
)
6536 enum machine_mode mode
= GET_MODE (x
);
6537 enum rtx_code subcode
;
6539 enum rtx_code code
= GET_CODE (x
);
6545 /* Memory costs quite a lot for the first word, but subsequent words
6546 load at the equivalent of a single insn each. */
6547 *total
= COSTS_N_INSNS (2 + ARM_NUM_REGS (mode
));
6554 if (TARGET_HARD_FLOAT
&& mode
== SFmode
)
6555 *total
= COSTS_N_INSNS (2);
6556 else if (TARGET_HARD_FLOAT
&& mode
== DFmode
&& !TARGET_VFP_SINGLE
)
6557 *total
= COSTS_N_INSNS (4);
6559 *total
= COSTS_N_INSNS (20);
6563 if (GET_CODE (XEXP (x
, 1)) == REG
)
6564 *total
= COSTS_N_INSNS (1); /* Need to subtract from 32 */
6565 else if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6566 *total
= rtx_cost (XEXP (x
, 1), code
, speed
);
6572 *total
+= COSTS_N_INSNS (4);
6577 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
6578 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
6581 *total
+= COSTS_N_INSNS (3);
6585 *total
+= COSTS_N_INSNS (1);
6586 /* Increase the cost of complex shifts because they aren't any faster,
6587 and reduce dual issue opportunities. */
6588 if (arm_tune_cortex_a9
6589 && outer
!= SET
&& GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6597 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
6598 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6599 && const_ok_for_arm (INTVAL (XEXP (x
, 0))))
6601 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
6605 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6606 && const_ok_for_arm (INTVAL (XEXP (x
, 1))))
6608 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
6615 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
6617 if (TARGET_HARD_FLOAT
6619 || (mode
== DFmode
&& !TARGET_VFP_SINGLE
)))
6621 *total
= COSTS_N_INSNS (1);
6622 if (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
6623 && arm_const_double_rtx (XEXP (x
, 0)))
6625 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
6629 if (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
6630 && arm_const_double_rtx (XEXP (x
, 1)))
6632 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
6638 *total
= COSTS_N_INSNS (20);
6642 *total
= COSTS_N_INSNS (1);
6643 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6644 && const_ok_for_arm (INTVAL (XEXP (x
, 0))))
6646 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
6650 subcode
= GET_CODE (XEXP (x
, 1));
6651 if (subcode
== ASHIFT
|| subcode
== ASHIFTRT
6652 || subcode
== LSHIFTRT
6653 || subcode
== ROTATE
|| subcode
== ROTATERT
)
6655 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
6656 *total
+= rtx_cost (XEXP (XEXP (x
, 1), 0), subcode
, speed
);
6660 /* A shift as a part of RSB costs no more than RSB itself. */
6661 if (GET_CODE (XEXP (x
, 0)) == MULT
6662 && power_of_two_operand (XEXP (XEXP (x
, 0), 1), SImode
))
6664 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), code
, speed
);
6665 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
6670 && power_of_two_operand (XEXP (XEXP (x
, 1), 1), SImode
))
6672 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
6673 *total
+= rtx_cost (XEXP (XEXP (x
, 1), 0), subcode
, speed
);
6677 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == RTX_COMPARE
6678 || GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == RTX_COMM_COMPARE
)
6680 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
, speed
);
6681 if (GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
6682 && REGNO (XEXP (XEXP (x
, 1), 0)) != CC_REGNUM
)
6683 *total
+= COSTS_N_INSNS (1);
6691 if (code
== PLUS
&& arm_arch6
&& mode
== SImode
6692 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
6693 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
6695 *total
= COSTS_N_INSNS (1);
6696 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), GET_CODE (XEXP (x
, 0)),
6698 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
6702 /* MLA: All arguments must be registers. We filter out
6703 multiplication by a power of two, so that we fall down into
6705 if (GET_CODE (XEXP (x
, 0)) == MULT
6706 && !power_of_two_operand (XEXP (XEXP (x
, 0), 1), SImode
))
6708 /* The cost comes from the cost of the multiply. */
6712 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
6714 if (TARGET_HARD_FLOAT
6716 || (mode
== DFmode
&& !TARGET_VFP_SINGLE
)))
6718 *total
= COSTS_N_INSNS (1);
6719 if (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
6720 && arm_const_double_rtx (XEXP (x
, 1)))
6722 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
6729 *total
= COSTS_N_INSNS (20);
6733 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == RTX_COMPARE
6734 || GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == RTX_COMM_COMPARE
)
6736 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 1), code
, speed
);
6737 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
6738 && REGNO (XEXP (XEXP (x
, 0), 0)) != CC_REGNUM
)
6739 *total
+= COSTS_N_INSNS (1);
6745 case AND
: case XOR
: case IOR
:
6747 /* Normally the frame registers will be spilt into reg+const during
6748 reload, so it is a bad idea to combine them with other instructions,
6749 since then they might not be moved outside of loops. As a compromise
6750 we allow integration with ops that have a constant as their second
6752 if (REG_OR_SUBREG_REG (XEXP (x
, 0))
6753 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
6754 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6755 *total
= COSTS_N_INSNS (1);
6759 *total
+= COSTS_N_INSNS (2);
6760 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6761 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
))
6763 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
6770 *total
+= COSTS_N_INSNS (1);
6771 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6772 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
))
6774 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
6777 subcode
= GET_CODE (XEXP (x
, 0));
6778 if (subcode
== ASHIFT
|| subcode
== ASHIFTRT
6779 || subcode
== LSHIFTRT
6780 || subcode
== ROTATE
|| subcode
== ROTATERT
)
6782 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
6783 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), subcode
, speed
);
6788 && power_of_two_operand (XEXP (XEXP (x
, 0), 1), SImode
))
6790 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
6791 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), subcode
, speed
);
6795 if (subcode
== UMIN
|| subcode
== UMAX
6796 || subcode
== SMIN
|| subcode
== SMAX
)
6798 *total
= COSTS_N_INSNS (3);
6805 /* This should have been handled by the CPU specific routines. */
6809 if (arm_arch3m
&& mode
== SImode
6810 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6811 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
6812 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
6813 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
6814 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
6815 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
6817 *total
= rtx_cost (XEXP (XEXP (x
, 0), 0), LSHIFTRT
, speed
);
6820 *total
= COSTS_N_INSNS (2); /* Plus the cost of the MULT */
6824 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
6826 if (TARGET_HARD_FLOAT
6828 || (mode
== DFmode
&& !TARGET_VFP_SINGLE
)))
6830 *total
= COSTS_N_INSNS (1);
6833 *total
= COSTS_N_INSNS (2);
6839 *total
= COSTS_N_INSNS (ARM_NUM_REGS(mode
));
6840 if (mode
== SImode
&& code
== NOT
)
6842 subcode
= GET_CODE (XEXP (x
, 0));
6843 if (subcode
== ASHIFT
|| subcode
== ASHIFTRT
6844 || subcode
== LSHIFTRT
6845 || subcode
== ROTATE
|| subcode
== ROTATERT
6847 && power_of_two_operand (XEXP (XEXP (x
, 0), 1), SImode
)))
6849 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), subcode
, speed
);
6850 /* Register shifts cost an extra cycle. */
6851 if (GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
6852 *total
+= COSTS_N_INSNS (1) + rtx_cost (XEXP (XEXP (x
, 0), 1),
6861 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
6863 *total
= COSTS_N_INSNS (4);
6867 operand
= XEXP (x
, 0);
6869 if (!((GET_RTX_CLASS (GET_CODE (operand
)) == RTX_COMPARE
6870 || GET_RTX_CLASS (GET_CODE (operand
)) == RTX_COMM_COMPARE
)
6871 && GET_CODE (XEXP (operand
, 0)) == REG
6872 && REGNO (XEXP (operand
, 0)) == CC_REGNUM
))
6873 *total
+= COSTS_N_INSNS (1);
6874 *total
+= (rtx_cost (XEXP (x
, 1), code
, speed
)
6875 + rtx_cost (XEXP (x
, 2), code
, speed
));
6879 if (mode
== SImode
&& XEXP (x
, 1) == const0_rtx
)
6881 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
, speed
);
6887 if ((GET_CODE (XEXP (x
, 0)) != REG
|| REGNO (XEXP (x
, 0)) != CC_REGNUM
)
6888 && mode
== SImode
&& XEXP (x
, 1) == const0_rtx
)
6890 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
, speed
);
6896 if ((GET_CODE (XEXP (x
, 0)) != REG
|| REGNO (XEXP (x
, 0)) != CC_REGNUM
)
6897 && mode
== SImode
&& XEXP (x
, 1) == const0_rtx
)
6899 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
, speed
);
6919 /* SCC insns. In the case where the comparison has already been
6920 performed, then they cost 2 instructions. Otherwise they need
6921 an additional comparison before them. */
6922 *total
= COSTS_N_INSNS (2);
6923 if (GET_CODE (XEXP (x
, 0)) == REG
&& REGNO (XEXP (x
, 0)) == CC_REGNUM
)
6930 if (GET_CODE (XEXP (x
, 0)) == REG
&& REGNO (XEXP (x
, 0)) == CC_REGNUM
)
6936 *total
+= COSTS_N_INSNS (1);
6937 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6938 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
))
6940 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
6944 subcode
= GET_CODE (XEXP (x
, 0));
6945 if (subcode
== ASHIFT
|| subcode
== ASHIFTRT
6946 || subcode
== LSHIFTRT
6947 || subcode
== ROTATE
|| subcode
== ROTATERT
)
6949 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
6950 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), subcode
, speed
);
6955 && power_of_two_operand (XEXP (XEXP (x
, 0), 1), SImode
))
6957 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
6958 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), subcode
, speed
);
6968 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
, speed
);
6969 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
6970 || !const_ok_for_arm (INTVAL (XEXP (x
, 1))))
6971 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
6975 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
6977 if (TARGET_HARD_FLOAT
6979 || (mode
== DFmode
&& !TARGET_VFP_SINGLE
)))
6981 *total
= COSTS_N_INSNS (1);
6984 *total
= COSTS_N_INSNS (20);
6987 *total
= COSTS_N_INSNS (1);
6989 *total
+= COSTS_N_INSNS (3);
6995 if (GET_MODE_CLASS (mode
) == MODE_INT
)
6997 rtx op
= XEXP (x
, 0);
6998 enum machine_mode opmode
= GET_MODE (op
);
7001 *total
+= COSTS_N_INSNS (1);
7003 if (opmode
!= SImode
)
7007 /* If !arm_arch4, we use one of the extendhisi2_mem
7008 or movhi_bytes patterns for HImode. For a QImode
7009 sign extension, we first zero-extend from memory
7010 and then perform a shift sequence. */
7011 if (!arm_arch4
&& (opmode
!= QImode
|| code
== SIGN_EXTEND
))
7012 *total
+= COSTS_N_INSNS (2);
7015 *total
+= COSTS_N_INSNS (1);
7017 /* We don't have the necessary insn, so we need to perform some
7019 else if (TARGET_ARM
&& code
== ZERO_EXTEND
&& mode
== QImode
)
7020 /* An and with constant 255. */
7021 *total
+= COSTS_N_INSNS (1);
7023 /* A shift sequence. Increase costs slightly to avoid
7024 combining two shifts into an extend operation. */
7025 *total
+= COSTS_N_INSNS (2) + 1;
7031 switch (GET_MODE (XEXP (x
, 0)))
7038 *total
= COSTS_N_INSNS (1);
7048 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
, speed
);
7052 if (const_ok_for_arm (INTVAL (x
))
7053 || const_ok_for_arm (~INTVAL (x
)))
7054 *total
= COSTS_N_INSNS (1);
7056 *total
= COSTS_N_INSNS (arm_gen_constant (SET
, mode
, NULL_RTX
,
7057 INTVAL (x
), NULL_RTX
,
7064 *total
= COSTS_N_INSNS (3);
7068 *total
= COSTS_N_INSNS (1);
7072 *total
= COSTS_N_INSNS (1);
7073 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
7077 if (TARGET_HARD_FLOAT
&& vfp3_const_double_rtx (x
)
7078 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
7079 *total
= COSTS_N_INSNS (1);
7081 *total
= COSTS_N_INSNS (4);
7085 *total
= COSTS_N_INSNS (4);
7090 /* Estimates the size cost of thumb1 instructions.
7091 For now most of the code is copied from thumb1_rtx_costs. We need more
7092 fine grain tuning when we have more related test cases. */
7094 thumb1_size_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
7096 enum machine_mode mode
= GET_MODE (x
);
7109 return COSTS_N_INSNS (1);
7112 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7114 /* Thumb1 mul instruction can't operate on const. We must Load it
7115 into a register first. */
7116 int const_size
= thumb1_size_rtx_costs (XEXP (x
, 1), CONST_INT
, SET
);
7117 return COSTS_N_INSNS (1) + const_size
;
7119 return COSTS_N_INSNS (1);
7122 return (COSTS_N_INSNS (1)
7123 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
7124 + GET_CODE (SET_DEST (x
)) == MEM
));
7129 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
7130 return COSTS_N_INSNS (1);
7131 /* See split "TARGET_THUMB1 && satisfies_constraint_J". */
7132 if (INTVAL (x
) >= -255 && INTVAL (x
) <= -1)
7133 return COSTS_N_INSNS (2);
7134 /* See split "TARGET_THUMB1 && satisfies_constraint_K". */
7135 if (thumb_shiftable_const (INTVAL (x
)))
7136 return COSTS_N_INSNS (2);
7137 return COSTS_N_INSNS (3);
7139 else if ((outer
== PLUS
|| outer
== COMPARE
)
7140 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
7142 else if ((outer
== IOR
|| outer
== XOR
|| outer
== AND
)
7143 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
7144 return COSTS_N_INSNS (1);
7145 else if (outer
== AND
)
7148 /* This duplicates the tests in the andsi3 expander. */
7149 for (i
= 9; i
<= 31; i
++)
7150 if ((((HOST_WIDE_INT
) 1) << i
) - 1 == INTVAL (x
)
7151 || (((HOST_WIDE_INT
) 1) << i
) - 1 == ~INTVAL (x
))
7152 return COSTS_N_INSNS (2);
7154 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
7155 || outer
== LSHIFTRT
)
7157 return COSTS_N_INSNS (2);
7163 return COSTS_N_INSNS (3);
7181 /* XXX another guess. */
7182 /* Memory costs quite a lot for the first word, but subsequent words
7183 load at the equivalent of a single insn each. */
7184 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
7185 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
7190 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
7195 /* XXX still guessing. */
7196 switch (GET_MODE (XEXP (x
, 0)))
7199 return (1 + (mode
== DImode
? 4 : 0)
7200 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
7203 return (4 + (mode
== DImode
? 4 : 0)
7204 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
7207 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
7218 /* RTX costs when optimizing for size. */
7220 arm_size_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer_code
,
7223 enum machine_mode mode
= GET_MODE (x
);
7226 *total
= thumb1_size_rtx_costs (x
, code
, outer_code
);
7230 /* FIXME: This makes no attempt to prefer narrow Thumb-2 instructions. */
7234 /* A memory access costs 1 insn if the mode is small, or the address is
7235 a single register, otherwise it costs one insn per word. */
7236 if (REG_P (XEXP (x
, 0)))
7237 *total
= COSTS_N_INSNS (1);
7239 && GET_CODE (XEXP (x
, 0)) == PLUS
7240 && will_be_in_index_register (XEXP (XEXP (x
, 0), 1)))
7241 /* This will be split into two instructions.
7242 See arm.md:calculate_pic_address. */
7243 *total
= COSTS_N_INSNS (2);
7245 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
7252 /* Needs a libcall, so it costs about this. */
7253 *total
= COSTS_N_INSNS (2);
7257 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
7259 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
, false);
7267 if (mode
== DImode
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7269 *total
= COSTS_N_INSNS (3) + rtx_cost (XEXP (x
, 0), code
, false);
7272 else if (mode
== SImode
)
7274 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
, false);
7275 /* Slightly disparage register shifts, but not by much. */
7276 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
7277 *total
+= 1 + rtx_cost (XEXP (x
, 1), code
, false);
7281 /* Needs a libcall. */
7282 *total
= COSTS_N_INSNS (2);
7286 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
7287 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
7289 *total
= COSTS_N_INSNS (1);
7295 enum rtx_code subcode0
= GET_CODE (XEXP (x
, 0));
7296 enum rtx_code subcode1
= GET_CODE (XEXP (x
, 1));
7298 if (subcode0
== ROTATE
|| subcode0
== ROTATERT
|| subcode0
== ASHIFT
7299 || subcode0
== LSHIFTRT
|| subcode0
== ASHIFTRT
7300 || subcode1
== ROTATE
|| subcode1
== ROTATERT
7301 || subcode1
== ASHIFT
|| subcode1
== LSHIFTRT
7302 || subcode1
== ASHIFTRT
)
7304 /* It's just the cost of the two operands. */
7309 *total
= COSTS_N_INSNS (1);
7313 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
7317 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
7318 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
7320 *total
= COSTS_N_INSNS (1);
7324 /* A shift as a part of ADD costs nothing. */
7325 if (GET_CODE (XEXP (x
, 0)) == MULT
7326 && power_of_two_operand (XEXP (XEXP (x
, 0), 1), SImode
))
7328 *total
= COSTS_N_INSNS (TARGET_THUMB2
? 2 : 1);
7329 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), code
, false);
7330 *total
+= rtx_cost (XEXP (x
, 1), code
, false);
7335 case AND
: case XOR
: case IOR
:
7338 enum rtx_code subcode
= GET_CODE (XEXP (x
, 0));
7340 if (subcode
== ROTATE
|| subcode
== ROTATERT
|| subcode
== ASHIFT
7341 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
7342 || (code
== AND
&& subcode
== NOT
))
7344 /* It's just the cost of the two operands. */
7350 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
7354 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
7358 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
7359 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
7361 *total
= COSTS_N_INSNS (1);
7367 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
7376 if (cc_register (XEXP (x
, 0), VOIDmode
))
7379 *total
= COSTS_N_INSNS (1);
7383 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
7384 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
7385 *total
= COSTS_N_INSNS (1);
7387 *total
= COSTS_N_INSNS (1 + ARM_NUM_REGS (mode
));
7392 return arm_rtx_costs_1 (x
, outer_code
, total
, 0);
7395 if (const_ok_for_arm (INTVAL (x
)))
7396 /* A multiplication by a constant requires another instruction
7397 to load the constant to a register. */
7398 *total
= COSTS_N_INSNS ((outer_code
== SET
|| outer_code
== MULT
)
7400 else if (const_ok_for_arm (~INTVAL (x
)))
7401 *total
= COSTS_N_INSNS (outer_code
== AND
? 0 : 1);
7402 else if (const_ok_for_arm (-INTVAL (x
)))
7404 if (outer_code
== COMPARE
|| outer_code
== PLUS
7405 || outer_code
== MINUS
)
7408 *total
= COSTS_N_INSNS (1);
7411 *total
= COSTS_N_INSNS (2);
7417 *total
= COSTS_N_INSNS (2);
7421 *total
= COSTS_N_INSNS (4);
7426 /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the
7427 cost of these slightly. */
7428 *total
= COSTS_N_INSNS (1) + 1;
7432 if (mode
!= VOIDmode
)
7433 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
7435 *total
= COSTS_N_INSNS (4); /* How knows? */
7440 /* RTX costs when optimizing for size. */
7442 arm_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
7446 return arm_size_rtx_costs (x
, (enum rtx_code
) code
,
7447 (enum rtx_code
) outer_code
, total
);
7449 return current_tune
->rtx_costs (x
, (enum rtx_code
) code
,
7450 (enum rtx_code
) outer_code
,
7454 /* RTX costs for cores with a slow MUL implementation. Thumb-2 is not
7455 supported on any "slowmul" cores, so it can be ignored. */
7458 arm_slowmul_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer_code
,
7459 int *total
, bool speed
)
7461 enum machine_mode mode
= GET_MODE (x
);
7465 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
7472 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
7475 *total
= COSTS_N_INSNS (20);
7479 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7481 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
7482 & (unsigned HOST_WIDE_INT
) 0xffffffff);
7483 int cost
, const_ok
= const_ok_for_arm (i
);
7484 int j
, booth_unit_size
;
7486 /* Tune as appropriate. */
7487 cost
= const_ok
? 4 : 8;
7488 booth_unit_size
= 2;
7489 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
7491 i
>>= booth_unit_size
;
7495 *total
= COSTS_N_INSNS (cost
);
7496 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
7500 *total
= COSTS_N_INSNS (20);
7504 return arm_rtx_costs_1 (x
, outer_code
, total
, speed
);;
7509 /* RTX cost for cores with a fast multiply unit (M variants). */
7512 arm_fastmul_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer_code
,
7513 int *total
, bool speed
)
7515 enum machine_mode mode
= GET_MODE (x
);
7519 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
7523 /* ??? should thumb2 use different costs? */
7527 /* There is no point basing this on the tuning, since it is always the
7528 fast variant if it exists at all. */
7530 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
7531 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
7532 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
7534 *total
= COSTS_N_INSNS(2);
7541 *total
= COSTS_N_INSNS (5);
7545 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7547 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
7548 & (unsigned HOST_WIDE_INT
) 0xffffffff);
7549 int cost
, const_ok
= const_ok_for_arm (i
);
7550 int j
, booth_unit_size
;
7552 /* Tune as appropriate. */
7553 cost
= const_ok
? 4 : 8;
7554 booth_unit_size
= 8;
7555 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
7557 i
>>= booth_unit_size
;
7561 *total
= COSTS_N_INSNS(cost
);
7567 *total
= COSTS_N_INSNS (4);
7571 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
7573 if (TARGET_HARD_FLOAT
7575 || (mode
== DFmode
&& !TARGET_VFP_SINGLE
)))
7577 *total
= COSTS_N_INSNS (1);
7582 /* Requires a lib call */
7583 *total
= COSTS_N_INSNS (20);
7587 return arm_rtx_costs_1 (x
, outer_code
, total
, speed
);
7592 /* RTX cost for XScale CPUs. Thumb-2 is not supported on any xscale cores,
7593 so it can be ignored. */
7596 arm_xscale_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer_code
,
7597 int *total
, bool speed
)
7599 enum machine_mode mode
= GET_MODE (x
);
7603 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
7610 if (GET_CODE (XEXP (x
, 0)) != MULT
)
7611 return arm_rtx_costs_1 (x
, outer_code
, total
, speed
);
7613 /* A COMPARE of a MULT is slow on XScale; the muls instruction
7614 will stall until the multiplication is complete. */
7615 *total
= COSTS_N_INSNS (3);
7619 /* There is no point basing this on the tuning, since it is always the
7620 fast variant if it exists at all. */
7622 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
7623 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
7624 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
7626 *total
= COSTS_N_INSNS (2);
7633 *total
= COSTS_N_INSNS (5);
7637 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7639 /* If operand 1 is a constant we can more accurately
7640 calculate the cost of the multiply. The multiplier can
7641 retire 15 bits on the first cycle and a further 12 on the
7642 second. We do, of course, have to load the constant into
7643 a register first. */
7644 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
7645 /* There's a general overhead of one cycle. */
7647 unsigned HOST_WIDE_INT masked_const
;
7652 i
&= (unsigned HOST_WIDE_INT
) 0xffffffff;
7654 masked_const
= i
& 0xffff8000;
7655 if (masked_const
!= 0)
7658 masked_const
= i
& 0xf8000000;
7659 if (masked_const
!= 0)
7662 *total
= COSTS_N_INSNS (cost
);
7668 *total
= COSTS_N_INSNS (3);
7672 /* Requires a lib call */
7673 *total
= COSTS_N_INSNS (20);
7677 return arm_rtx_costs_1 (x
, outer_code
, total
, speed
);
7682 /* RTX costs for 9e (and later) cores. */
7685 arm_9e_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer_code
,
7686 int *total
, bool speed
)
7688 enum machine_mode mode
= GET_MODE (x
);
7695 *total
= COSTS_N_INSNS (3);
7699 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
7707 /* There is no point basing this on the tuning, since it is always the
7708 fast variant if it exists at all. */
7710 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
7711 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
7712 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
7714 *total
= COSTS_N_INSNS (2);
7721 *total
= COSTS_N_INSNS (5);
7727 *total
= COSTS_N_INSNS (2);
7731 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
7733 if (TARGET_HARD_FLOAT
7735 || (mode
== DFmode
&& !TARGET_VFP_SINGLE
)))
7737 *total
= COSTS_N_INSNS (1);
7742 *total
= COSTS_N_INSNS (20);
7746 return arm_rtx_costs_1 (x
, outer_code
, total
, speed
);
7749 /* All address computations that can be done are free, but rtx cost returns
7750 the same for practically all of them. So we weight the different types
7751 of address here in the order (most pref first):
7752 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
7754 arm_arm_address_cost (rtx x
)
7756 enum rtx_code c
= GET_CODE (x
);
7758 if (c
== PRE_INC
|| c
== PRE_DEC
|| c
== POST_INC
|| c
== POST_DEC
)
7760 if (c
== MEM
|| c
== LABEL_REF
|| c
== SYMBOL_REF
)
7765 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7768 if (ARITHMETIC_P (XEXP (x
, 0)) || ARITHMETIC_P (XEXP (x
, 1)))
7778 arm_thumb_address_cost (rtx x
)
7780 enum rtx_code c
= GET_CODE (x
);
7785 && GET_CODE (XEXP (x
, 0)) == REG
7786 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7793 arm_address_cost (rtx x
, bool speed ATTRIBUTE_UNUSED
)
7795 return TARGET_32BIT
? arm_arm_address_cost (x
) : arm_thumb_address_cost (x
);
7798 /* Adjust cost hook for XScale. */
7800 xscale_sched_adjust_cost (rtx insn
, rtx link
, rtx dep
, int * cost
)
7802 /* Some true dependencies can have a higher cost depending
7803 on precisely how certain input operands are used. */
7804 if (REG_NOTE_KIND(link
) == 0
7805 && recog_memoized (insn
) >= 0
7806 && recog_memoized (dep
) >= 0)
7808 int shift_opnum
= get_attr_shift (insn
);
7809 enum attr_type attr_type
= get_attr_type (dep
);
7811 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
7812 operand for INSN. If we have a shifted input operand and the
7813 instruction we depend on is another ALU instruction, then we may
7814 have to account for an additional stall. */
7815 if (shift_opnum
!= 0
7816 && (attr_type
== TYPE_ALU_SHIFT
|| attr_type
== TYPE_ALU_SHIFT_REG
))
7818 rtx shifted_operand
;
7821 /* Get the shifted operand. */
7822 extract_insn (insn
);
7823 shifted_operand
= recog_data
.operand
[shift_opnum
];
7825 /* Iterate over all the operands in DEP. If we write an operand
7826 that overlaps with SHIFTED_OPERAND, then we have increase the
7827 cost of this dependency. */
7829 preprocess_constraints ();
7830 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
7832 /* We can ignore strict inputs. */
7833 if (recog_data
.operand_type
[opno
] == OP_IN
)
7836 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
7848 /* Adjust cost hook for Cortex A9. */
7850 cortex_a9_sched_adjust_cost (rtx insn
, rtx link
, rtx dep
, int * cost
)
7852 switch (REG_NOTE_KIND (link
))
7859 case REG_DEP_OUTPUT
:
7860 if (recog_memoized (insn
) >= 0
7861 && recog_memoized (dep
) >= 0)
7863 if (GET_CODE (PATTERN (insn
)) == SET
)
7866 (GET_MODE (SET_DEST (PATTERN (insn
)))) == MODE_FLOAT
7868 (GET_MODE (SET_SRC (PATTERN (insn
)))) == MODE_FLOAT
)
7870 enum attr_type attr_type_insn
= get_attr_type (insn
);
7871 enum attr_type attr_type_dep
= get_attr_type (dep
);
7873 /* By default all dependencies of the form
7876 have an extra latency of 1 cycle because
7877 of the input and output dependency in this
7878 case. However this gets modeled as an true
7879 dependency and hence all these checks. */
7880 if (REG_P (SET_DEST (PATTERN (insn
)))
7881 && REG_P (SET_DEST (PATTERN (dep
)))
7882 && reg_overlap_mentioned_p (SET_DEST (PATTERN (insn
)),
7883 SET_DEST (PATTERN (dep
))))
7885 /* FMACS is a special case where the dependant
7886 instruction can be issued 3 cycles before
7887 the normal latency in case of an output
7889 if ((attr_type_insn
== TYPE_FMACS
7890 || attr_type_insn
== TYPE_FMACD
)
7891 && (attr_type_dep
== TYPE_FMACS
7892 || attr_type_dep
== TYPE_FMACD
))
7894 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
7895 *cost
= insn_default_latency (dep
) - 3;
7897 *cost
= insn_default_latency (dep
);
7902 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
7903 *cost
= insn_default_latency (dep
) + 1;
7905 *cost
= insn_default_latency (dep
);
7921 /* Adjust cost hook for FA726TE. */
7923 fa726te_sched_adjust_cost (rtx insn
, rtx link
, rtx dep
, int * cost
)
7925 /* For FA726TE, true dependency on CPSR (i.e. set cond followed by predicated)
7926 have penalty of 3. */
7927 if (REG_NOTE_KIND (link
) == REG_DEP_TRUE
7928 && recog_memoized (insn
) >= 0
7929 && recog_memoized (dep
) >= 0
7930 && get_attr_conds (dep
) == CONDS_SET
)
7932 /* Use of carry (e.g. 64-bit arithmetic) in ALU: 3-cycle latency. */
7933 if (get_attr_conds (insn
) == CONDS_USE
7934 && get_attr_type (insn
) != TYPE_BRANCH
)
7940 if (GET_CODE (PATTERN (insn
)) == COND_EXEC
7941 || get_attr_conds (insn
) == CONDS_USE
)
7951 /* This function implements the target macro TARGET_SCHED_ADJUST_COST.
7952 It corrects the value of COST based on the relationship between
7953 INSN and DEP through the dependence LINK. It returns the new
7954 value. There is a per-core adjust_cost hook to adjust scheduler costs
7955 and the per-core hook can choose to completely override the generic
7956 adjust_cost function. Only put bits of code into arm_adjust_cost that
7957 are common across all cores. */
7959 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
7963 /* When generating Thumb-1 code, we want to place flag-setting operations
7964 close to a conditional branch which depends on them, so that we can
7965 omit the comparison. */
7967 && REG_NOTE_KIND (link
) == 0
7968 && recog_memoized (insn
) == CODE_FOR_cbranchsi4_insn
7969 && recog_memoized (dep
) >= 0
7970 && get_attr_conds (dep
) == CONDS_SET
)
7973 if (current_tune
->sched_adjust_cost
!= NULL
)
7975 if (!current_tune
->sched_adjust_cost (insn
, link
, dep
, &cost
))
7979 /* XXX This is not strictly true for the FPA. */
7980 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
7981 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
7984 /* Call insns don't incur a stall, even if they follow a load. */
7985 if (REG_NOTE_KIND (link
) == 0
7986 && GET_CODE (insn
) == CALL_INSN
)
7989 if ((i_pat
= single_set (insn
)) != NULL
7990 && GET_CODE (SET_SRC (i_pat
)) == MEM
7991 && (d_pat
= single_set (dep
)) != NULL
7992 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
7994 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
7995 /* This is a load after a store, there is no conflict if the load reads
7996 from a cached area. Assume that loads from the stack, and from the
7997 constant pool are cached, and that others will miss. This is a
8000 if ((GET_CODE (src_mem
) == SYMBOL_REF
8001 && CONSTANT_POOL_ADDRESS_P (src_mem
))
8002 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
8003 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
8004 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
8011 static int fp_consts_inited
= 0;
8013 /* Only zero is valid for VFP. Other values are also valid for FPA. */
8014 static const char * const strings_fp
[8] =
8017 "4", "5", "0.5", "10"
8020 static REAL_VALUE_TYPE values_fp
[8];
8023 init_fp_table (void)
8029 fp_consts_inited
= 1;
8031 fp_consts_inited
= 8;
8033 for (i
= 0; i
< fp_consts_inited
; i
++)
8035 r
= REAL_VALUE_ATOF (strings_fp
[i
], DFmode
);
8040 /* Return TRUE if rtx X is a valid immediate FP constant. */
8042 arm_const_double_rtx (rtx x
)
8047 if (!fp_consts_inited
)
8050 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
8051 if (REAL_VALUE_MINUS_ZERO (r
))
8054 for (i
= 0; i
< fp_consts_inited
; i
++)
8055 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
8061 /* Return TRUE if rtx X is a valid immediate FPA constant. */
8063 neg_const_double_rtx_ok_for_fpa (rtx x
)
8068 if (!fp_consts_inited
)
8071 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
8072 r
= real_value_negate (&r
);
8073 if (REAL_VALUE_MINUS_ZERO (r
))
8076 for (i
= 0; i
< 8; i
++)
8077 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
8084 /* VFPv3 has a fairly wide range of representable immediates, formed from
8085 "quarter-precision" floating-point values. These can be evaluated using this
8086 formula (with ^ for exponentiation):
8090 Where 's' is a sign bit (0/1), 'n' and 'r' are integers such that
8091 16 <= n <= 31 and 0 <= r <= 7.
8093 These values are mapped onto an 8-bit integer ABCDEFGH s.t.
8095 - A (most-significant) is the sign bit.
8096 - BCD are the exponent (encoded as r XOR 3).
8097 - EFGH are the mantissa (encoded as n - 16).
8100 /* Return an integer index for a VFPv3 immediate operand X suitable for the
8101 fconst[sd] instruction, or -1 if X isn't suitable. */
8103 vfp3_const_double_index (rtx x
)
8105 REAL_VALUE_TYPE r
, m
;
8107 unsigned HOST_WIDE_INT mantissa
, mant_hi
;
8108 unsigned HOST_WIDE_INT mask
;
8109 HOST_WIDE_INT m1
, m2
;
8110 int point_pos
= 2 * HOST_BITS_PER_WIDE_INT
- 1;
8112 if (!TARGET_VFP3
|| GET_CODE (x
) != CONST_DOUBLE
)
8115 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
8117 /* We can't represent these things, so detect them first. */
8118 if (REAL_VALUE_ISINF (r
) || REAL_VALUE_ISNAN (r
) || REAL_VALUE_MINUS_ZERO (r
))
8121 /* Extract sign, exponent and mantissa. */
8122 sign
= REAL_VALUE_NEGATIVE (r
) ? 1 : 0;
8123 r
= real_value_abs (&r
);
8124 exponent
= REAL_EXP (&r
);
8125 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
8126 highest (sign) bit, with a fixed binary point at bit point_pos.
8127 WARNING: If there's ever a VFP version which uses more than 2 * H_W_I - 1
8128 bits for the mantissa, this may fail (low bits would be lost). */
8129 real_ldexp (&m
, &r
, point_pos
- exponent
);
8130 REAL_VALUE_TO_INT (&m1
, &m2
, m
);
8134 /* If there are bits set in the low part of the mantissa, we can't
8135 represent this value. */
8139 /* Now make it so that mantissa contains the most-significant bits, and move
8140 the point_pos to indicate that the least-significant bits have been
8142 point_pos
-= HOST_BITS_PER_WIDE_INT
;
8145 /* We can permit four significant bits of mantissa only, plus a high bit
8146 which is always 1. */
8147 mask
= ((unsigned HOST_WIDE_INT
)1 << (point_pos
- 5)) - 1;
8148 if ((mantissa
& mask
) != 0)
8151 /* Now we know the mantissa is in range, chop off the unneeded bits. */
8152 mantissa
>>= point_pos
- 5;
8154 /* The mantissa may be zero. Disallow that case. (It's possible to load the
8155 floating-point immediate zero with Neon using an integer-zero load, but
8156 that case is handled elsewhere.) */
8160 gcc_assert (mantissa
>= 16 && mantissa
<= 31);
8162 /* The value of 5 here would be 4 if GCC used IEEE754-like encoding (where
8163 normalized significands are in the range [1, 2). (Our mantissa is shifted
8164 left 4 places at this point relative to normalized IEEE754 values). GCC
8165 internally uses [0.5, 1) (see real.c), so the exponent returned from
8166 REAL_EXP must be altered. */
8167 exponent
= 5 - exponent
;
8169 if (exponent
< 0 || exponent
> 7)
8172 /* Sign, mantissa and exponent are now in the correct form to plug into the
8173 formula described in the comment above. */
8174 return (sign
<< 7) | ((exponent
^ 3) << 4) | (mantissa
- 16);
8177 /* Return TRUE if rtx X is a valid immediate VFPv3 constant. */
8179 vfp3_const_double_rtx (rtx x
)
8184 return vfp3_const_double_index (x
) != -1;
8187 /* Recognize immediates which can be used in various Neon instructions. Legal
8188 immediates are described by the following table (for VMVN variants, the
8189 bitwise inverse of the constant shown is recognized. In either case, VMOV
8190 is output and the correct instruction to use for a given constant is chosen
8191 by the assembler). The constant shown is replicated across all elements of
8192 the destination vector.
8194 insn elems variant constant (binary)
8195 ---- ----- ------- -----------------
8196 vmov i32 0 00000000 00000000 00000000 abcdefgh
8197 vmov i32 1 00000000 00000000 abcdefgh 00000000
8198 vmov i32 2 00000000 abcdefgh 00000000 00000000
8199 vmov i32 3 abcdefgh 00000000 00000000 00000000
8200 vmov i16 4 00000000 abcdefgh
8201 vmov i16 5 abcdefgh 00000000
8202 vmvn i32 6 00000000 00000000 00000000 abcdefgh
8203 vmvn i32 7 00000000 00000000 abcdefgh 00000000
8204 vmvn i32 8 00000000 abcdefgh 00000000 00000000
8205 vmvn i32 9 abcdefgh 00000000 00000000 00000000
8206 vmvn i16 10 00000000 abcdefgh
8207 vmvn i16 11 abcdefgh 00000000
8208 vmov i32 12 00000000 00000000 abcdefgh 11111111
8209 vmvn i32 13 00000000 00000000 abcdefgh 11111111
8210 vmov i32 14 00000000 abcdefgh 11111111 11111111
8211 vmvn i32 15 00000000 abcdefgh 11111111 11111111
8213 vmov i64 17 aaaaaaaa bbbbbbbb cccccccc dddddddd
8214 eeeeeeee ffffffff gggggggg hhhhhhhh
8215 vmov f32 18 aBbbbbbc defgh000 00000000 00000000
8217 For case 18, B = !b. Representable values are exactly those accepted by
8218 vfp3_const_double_index, but are output as floating-point numbers rather
8221 Variants 0-5 (inclusive) may also be used as immediates for the second
8222 operand of VORR/VBIC instructions.
8224 The INVERSE argument causes the bitwise inverse of the given operand to be
8225 recognized instead (used for recognizing legal immediates for the VAND/VORN
8226 pseudo-instructions). If INVERSE is true, the value placed in *MODCONST is
8227 *not* inverted (i.e. the pseudo-instruction forms vand/vorn should still be
8228 output, rather than the real insns vbic/vorr).
8230 INVERSE makes no difference to the recognition of float vectors.
8232 The return value is the variant of immediate as shown in the above table, or
8233 -1 if the given value doesn't match any of the listed patterns.
8236 neon_valid_immediate (rtx op
, enum machine_mode mode
, int inverse
,
8237 rtx
*modconst
, int *elementwidth
)
8239 #define CHECK(STRIDE, ELSIZE, CLASS, TEST) \
8241 for (i = 0; i < idx; i += (STRIDE)) \
8246 immtype = (CLASS); \
8247 elsize = (ELSIZE); \
8251 unsigned int i
, elsize
= 0, idx
= 0, n_elts
= CONST_VECTOR_NUNITS (op
);
8252 unsigned int innersize
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
8253 unsigned char bytes
[16];
8254 int immtype
= -1, matches
;
8255 unsigned int invmask
= inverse
? 0xff : 0;
8257 /* Vectors of float constants. */
8258 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
8260 rtx el0
= CONST_VECTOR_ELT (op
, 0);
8263 if (!vfp3_const_double_rtx (el0
))
8266 REAL_VALUE_FROM_CONST_DOUBLE (r0
, el0
);
8268 for (i
= 1; i
< n_elts
; i
++)
8270 rtx elt
= CONST_VECTOR_ELT (op
, i
);
8273 REAL_VALUE_FROM_CONST_DOUBLE (re
, elt
);
8275 if (!REAL_VALUES_EQUAL (r0
, re
))
8280 *modconst
= CONST_VECTOR_ELT (op
, 0);
8288 /* Splat vector constant out into a byte vector. */
8289 for (i
= 0; i
< n_elts
; i
++)
8291 rtx el
= CONST_VECTOR_ELT (op
, i
);
8292 unsigned HOST_WIDE_INT elpart
;
8293 unsigned int part
, parts
;
8295 if (GET_CODE (el
) == CONST_INT
)
8297 elpart
= INTVAL (el
);
8300 else if (GET_CODE (el
) == CONST_DOUBLE
)
8302 elpart
= CONST_DOUBLE_LOW (el
);
8308 for (part
= 0; part
< parts
; part
++)
8311 for (byte
= 0; byte
< innersize
; byte
++)
8313 bytes
[idx
++] = (elpart
& 0xff) ^ invmask
;
8314 elpart
>>= BITS_PER_UNIT
;
8316 if (GET_CODE (el
) == CONST_DOUBLE
)
8317 elpart
= CONST_DOUBLE_HIGH (el
);
8322 gcc_assert (idx
== GET_MODE_SIZE (mode
));
8326 CHECK (4, 32, 0, bytes
[i
] == bytes
[0] && bytes
[i
+ 1] == 0
8327 && bytes
[i
+ 2] == 0 && bytes
[i
+ 3] == 0);
8329 CHECK (4, 32, 1, bytes
[i
] == 0 && bytes
[i
+ 1] == bytes
[1]
8330 && bytes
[i
+ 2] == 0 && bytes
[i
+ 3] == 0);
8332 CHECK (4, 32, 2, bytes
[i
] == 0 && bytes
[i
+ 1] == 0
8333 && bytes
[i
+ 2] == bytes
[2] && bytes
[i
+ 3] == 0);
8335 CHECK (4, 32, 3, bytes
[i
] == 0 && bytes
[i
+ 1] == 0
8336 && bytes
[i
+ 2] == 0 && bytes
[i
+ 3] == bytes
[3]);
8338 CHECK (2, 16, 4, bytes
[i
] == bytes
[0] && bytes
[i
+ 1] == 0);
8340 CHECK (2, 16, 5, bytes
[i
] == 0 && bytes
[i
+ 1] == bytes
[1]);
8342 CHECK (4, 32, 6, bytes
[i
] == bytes
[0] && bytes
[i
+ 1] == 0xff
8343 && bytes
[i
+ 2] == 0xff && bytes
[i
+ 3] == 0xff);
8345 CHECK (4, 32, 7, bytes
[i
] == 0xff && bytes
[i
+ 1] == bytes
[1]
8346 && bytes
[i
+ 2] == 0xff && bytes
[i
+ 3] == 0xff);
8348 CHECK (4, 32, 8, bytes
[i
] == 0xff && bytes
[i
+ 1] == 0xff
8349 && bytes
[i
+ 2] == bytes
[2] && bytes
[i
+ 3] == 0xff);
8351 CHECK (4, 32, 9, bytes
[i
] == 0xff && bytes
[i
+ 1] == 0xff
8352 && bytes
[i
+ 2] == 0xff && bytes
[i
+ 3] == bytes
[3]);
8354 CHECK (2, 16, 10, bytes
[i
] == bytes
[0] && bytes
[i
+ 1] == 0xff);
8356 CHECK (2, 16, 11, bytes
[i
] == 0xff && bytes
[i
+ 1] == bytes
[1]);
8358 CHECK (4, 32, 12, bytes
[i
] == 0xff && bytes
[i
+ 1] == bytes
[1]
8359 && bytes
[i
+ 2] == 0 && bytes
[i
+ 3] == 0);
8361 CHECK (4, 32, 13, bytes
[i
] == 0 && bytes
[i
+ 1] == bytes
[1]
8362 && bytes
[i
+ 2] == 0xff && bytes
[i
+ 3] == 0xff);
8364 CHECK (4, 32, 14, bytes
[i
] == 0xff && bytes
[i
+ 1] == 0xff
8365 && bytes
[i
+ 2] == bytes
[2] && bytes
[i
+ 3] == 0);
8367 CHECK (4, 32, 15, bytes
[i
] == 0 && bytes
[i
+ 1] == 0
8368 && bytes
[i
+ 2] == bytes
[2] && bytes
[i
+ 3] == 0xff);
8370 CHECK (1, 8, 16, bytes
[i
] == bytes
[0]);
8372 CHECK (1, 64, 17, (bytes
[i
] == 0 || bytes
[i
] == 0xff)
8373 && bytes
[i
] == bytes
[(i
+ 8) % idx
]);
8381 *elementwidth
= elsize
;
8385 unsigned HOST_WIDE_INT imm
= 0;
8387 /* Un-invert bytes of recognized vector, if necessary. */
8389 for (i
= 0; i
< idx
; i
++)
8390 bytes
[i
] ^= invmask
;
8394 /* FIXME: Broken on 32-bit H_W_I hosts. */
8395 gcc_assert (sizeof (HOST_WIDE_INT
) == 8);
8397 for (i
= 0; i
< 8; i
++)
8398 imm
|= (unsigned HOST_WIDE_INT
) (bytes
[i
] ? 0xff : 0)
8399 << (i
* BITS_PER_UNIT
);
8401 *modconst
= GEN_INT (imm
);
8405 unsigned HOST_WIDE_INT imm
= 0;
8407 for (i
= 0; i
< elsize
/ BITS_PER_UNIT
; i
++)
8408 imm
|= (unsigned HOST_WIDE_INT
) bytes
[i
] << (i
* BITS_PER_UNIT
);
8410 *modconst
= GEN_INT (imm
);
8418 /* Return TRUE if rtx X is legal for use as either a Neon VMOV (or, implicitly,
8419 VMVN) immediate. Write back width per element to *ELEMENTWIDTH (or zero for
8420 float elements), and a modified constant (whatever should be output for a
8421 VMOV) in *MODCONST. */
8424 neon_immediate_valid_for_move (rtx op
, enum machine_mode mode
,
8425 rtx
*modconst
, int *elementwidth
)
8429 int retval
= neon_valid_immediate (op
, mode
, 0, &tmpconst
, &tmpwidth
);
8435 *modconst
= tmpconst
;
8438 *elementwidth
= tmpwidth
;
8443 /* Return TRUE if rtx X is legal for use in a VORR or VBIC instruction. If
8444 the immediate is valid, write a constant suitable for using as an operand
8445 to VORR/VBIC/VAND/VORN to *MODCONST and the corresponding element width to
8446 *ELEMENTWIDTH. See neon_valid_immediate for description of INVERSE. */
8449 neon_immediate_valid_for_logic (rtx op
, enum machine_mode mode
, int inverse
,
8450 rtx
*modconst
, int *elementwidth
)
8454 int retval
= neon_valid_immediate (op
, mode
, inverse
, &tmpconst
, &tmpwidth
);
8456 if (retval
< 0 || retval
> 5)
8460 *modconst
= tmpconst
;
8463 *elementwidth
= tmpwidth
;
8468 /* Return a string suitable for output of Neon immediate logic operation
8472 neon_output_logic_immediate (const char *mnem
, rtx
*op2
, enum machine_mode mode
,
8473 int inverse
, int quad
)
8475 int width
, is_valid
;
8476 static char templ
[40];
8478 is_valid
= neon_immediate_valid_for_logic (*op2
, mode
, inverse
, op2
, &width
);
8480 gcc_assert (is_valid
!= 0);
8483 sprintf (templ
, "%s.i%d\t%%q0, %%2", mnem
, width
);
8485 sprintf (templ
, "%s.i%d\t%%P0, %%2", mnem
, width
);
8490 /* Output a sequence of pairwise operations to implement a reduction.
8491 NOTE: We do "too much work" here, because pairwise operations work on two
8492 registers-worth of operands in one go. Unfortunately we can't exploit those
8493 extra calculations to do the full operation in fewer steps, I don't think.
8494 Although all vector elements of the result but the first are ignored, we
8495 actually calculate the same result in each of the elements. An alternative
8496 such as initially loading a vector with zero to use as each of the second
8497 operands would use up an additional register and take an extra instruction,
8498 for no particular gain. */
8501 neon_pairwise_reduce (rtx op0
, rtx op1
, enum machine_mode mode
,
8502 rtx (*reduc
) (rtx
, rtx
, rtx
))
8504 enum machine_mode inner
= GET_MODE_INNER (mode
);
8505 unsigned int i
, parts
= GET_MODE_SIZE (mode
) / GET_MODE_SIZE (inner
);
8508 for (i
= parts
/ 2; i
>= 1; i
/= 2)
8510 rtx dest
= (i
== 1) ? op0
: gen_reg_rtx (mode
);
8511 emit_insn (reduc (dest
, tmpsum
, tmpsum
));
8516 /* If VALS is a vector constant that can be loaded into a register
8517 using VDUP, generate instructions to do so and return an RTX to
8518 assign to the register. Otherwise return NULL_RTX. */
8521 neon_vdup_constant (rtx vals
)
8523 enum machine_mode mode
= GET_MODE (vals
);
8524 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
8525 int n_elts
= GET_MODE_NUNITS (mode
);
8526 bool all_same
= true;
8530 if (GET_CODE (vals
) != CONST_VECTOR
|| GET_MODE_SIZE (inner_mode
) > 4)
8533 for (i
= 0; i
< n_elts
; ++i
)
8535 x
= XVECEXP (vals
, 0, i
);
8536 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
8541 /* The elements are not all the same. We could handle repeating
8542 patterns of a mode larger than INNER_MODE here (e.g. int8x8_t
8543 {0, C, 0, C, 0, C, 0, C} which can be loaded using
8547 /* We can load this constant by using VDUP and a constant in a
8548 single ARM register. This will be cheaper than a vector
8551 x
= copy_to_mode_reg (inner_mode
, XVECEXP (vals
, 0, 0));
8552 return gen_rtx_VEC_DUPLICATE (mode
, x
);
8555 /* Generate code to load VALS, which is a PARALLEL containing only
8556 constants (for vec_init) or CONST_VECTOR, efficiently into a
8557 register. Returns an RTX to copy into the register, or NULL_RTX
8558 for a PARALLEL that can not be converted into a CONST_VECTOR. */
8561 neon_make_constant (rtx vals
)
8563 enum machine_mode mode
= GET_MODE (vals
);
8565 rtx const_vec
= NULL_RTX
;
8566 int n_elts
= GET_MODE_NUNITS (mode
);
8570 if (GET_CODE (vals
) == CONST_VECTOR
)
8572 else if (GET_CODE (vals
) == PARALLEL
)
8574 /* A CONST_VECTOR must contain only CONST_INTs and
8575 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
8576 Only store valid constants in a CONST_VECTOR. */
8577 for (i
= 0; i
< n_elts
; ++i
)
8579 rtx x
= XVECEXP (vals
, 0, i
);
8580 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
8583 if (n_const
== n_elts
)
8584 const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
8589 if (const_vec
!= NULL
8590 && neon_immediate_valid_for_move (const_vec
, mode
, NULL
, NULL
))
8591 /* Load using VMOV. On Cortex-A8 this takes one cycle. */
8593 else if ((target
= neon_vdup_constant (vals
)) != NULL_RTX
)
8594 /* Loaded using VDUP. On Cortex-A8 the VDUP takes one NEON
8595 pipeline cycle; creating the constant takes one or two ARM
8598 else if (const_vec
!= NULL_RTX
)
8599 /* Load from constant pool. On Cortex-A8 this takes two cycles
8600 (for either double or quad vectors). We can not take advantage
8601 of single-cycle VLD1 because we need a PC-relative addressing
8605 /* A PARALLEL containing something not valid inside CONST_VECTOR.
8606 We can not construct an initializer. */
8610 /* Initialize vector TARGET to VALS. */
8613 neon_expand_vector_init (rtx target
, rtx vals
)
8615 enum machine_mode mode
= GET_MODE (target
);
8616 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
8617 int n_elts
= GET_MODE_NUNITS (mode
);
8618 int n_var
= 0, one_var
= -1;
8619 bool all_same
= true;
8623 for (i
= 0; i
< n_elts
; ++i
)
8625 x
= XVECEXP (vals
, 0, i
);
8626 if (!CONSTANT_P (x
))
8627 ++n_var
, one_var
= i
;
8629 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
8635 rtx constant
= neon_make_constant (vals
);
8636 if (constant
!= NULL_RTX
)
8638 emit_move_insn (target
, constant
);
8643 /* Splat a single non-constant element if we can. */
8644 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
8646 x
= copy_to_mode_reg (inner_mode
, XVECEXP (vals
, 0, 0));
8647 emit_insn (gen_rtx_SET (VOIDmode
, target
,
8648 gen_rtx_VEC_DUPLICATE (mode
, x
)));
8652 /* One field is non-constant. Load constant then overwrite varying
8653 field. This is more efficient than using the stack. */
8656 rtx copy
= copy_rtx (vals
);
8657 rtx index
= GEN_INT (one_var
);
8659 /* Load constant part of vector, substitute neighboring value for
8661 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
8662 neon_expand_vector_init (target
, copy
);
8664 /* Insert variable. */
8665 x
= copy_to_mode_reg (inner_mode
, XVECEXP (vals
, 0, one_var
));
8669 emit_insn (gen_neon_vset_lanev8qi (target
, x
, target
, index
));
8672 emit_insn (gen_neon_vset_lanev16qi (target
, x
, target
, index
));
8675 emit_insn (gen_neon_vset_lanev4hi (target
, x
, target
, index
));
8678 emit_insn (gen_neon_vset_lanev8hi (target
, x
, target
, index
));
8681 emit_insn (gen_neon_vset_lanev2si (target
, x
, target
, index
));
8684 emit_insn (gen_neon_vset_lanev4si (target
, x
, target
, index
));
8687 emit_insn (gen_neon_vset_lanev2sf (target
, x
, target
, index
));
8690 emit_insn (gen_neon_vset_lanev4sf (target
, x
, target
, index
));
8693 emit_insn (gen_neon_vset_lanev2di (target
, x
, target
, index
));
8701 /* Construct the vector in memory one field at a time
8702 and load the whole vector. */
8703 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
8704 for (i
= 0; i
< n_elts
; i
++)
8705 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
8706 i
* GET_MODE_SIZE (inner_mode
)),
8707 XVECEXP (vals
, 0, i
));
8708 emit_move_insn (target
, mem
);
8711 /* Ensure OPERAND lies between LOW (inclusive) and HIGH (exclusive). Raise
8712 ERR if it doesn't. FIXME: NEON bounds checks occur late in compilation, so
8713 reported source locations are bogus. */
8716 bounds_check (rtx operand
, HOST_WIDE_INT low
, HOST_WIDE_INT high
,
8721 gcc_assert (GET_CODE (operand
) == CONST_INT
);
8723 lane
= INTVAL (operand
);
8725 if (lane
< low
|| lane
>= high
)
8729 /* Bounds-check lanes. */
8732 neon_lane_bounds (rtx operand
, HOST_WIDE_INT low
, HOST_WIDE_INT high
)
8734 bounds_check (operand
, low
, high
, "lane out of range");
8737 /* Bounds-check constants. */
8740 neon_const_bounds (rtx operand
, HOST_WIDE_INT low
, HOST_WIDE_INT high
)
8742 bounds_check (operand
, low
, high
, "constant out of range");
8746 neon_element_bits (enum machine_mode mode
)
8749 return GET_MODE_BITSIZE (mode
);
8751 return GET_MODE_BITSIZE (GET_MODE_INNER (mode
));
8755 /* Predicates for `match_operand' and `match_operator'. */
8757 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
8759 cirrus_memory_offset (rtx op
)
8761 /* Reject eliminable registers. */
8762 if (! (reload_in_progress
|| reload_completed
)
8763 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
8764 || reg_mentioned_p (arg_pointer_rtx
, op
)
8765 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
8766 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
8767 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
8768 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
8771 if (GET_CODE (op
) == MEM
)
8777 /* Match: (mem (reg)). */
8778 if (GET_CODE (ind
) == REG
)
8784 if (GET_CODE (ind
) == PLUS
8785 && GET_CODE (XEXP (ind
, 0)) == REG
8786 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
8787 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
8794 /* Return TRUE if OP is a valid coprocessor memory address pattern.
8795 WB is true if full writeback address modes are allowed and is false
8796 if limited writeback address modes (POST_INC and PRE_DEC) are
8800 arm_coproc_mem_operand (rtx op
, bool wb
)
8804 /* Reject eliminable registers. */
8805 if (! (reload_in_progress
|| reload_completed
)
8806 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
8807 || reg_mentioned_p (arg_pointer_rtx
, op
)
8808 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
8809 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
8810 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
8811 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
8814 /* Constants are converted into offsets from labels. */
8815 if (GET_CODE (op
) != MEM
)
8820 if (reload_completed
8821 && (GET_CODE (ind
) == LABEL_REF
8822 || (GET_CODE (ind
) == CONST
8823 && GET_CODE (XEXP (ind
, 0)) == PLUS
8824 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
8825 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
8828 /* Match: (mem (reg)). */
8829 if (GET_CODE (ind
) == REG
)
8830 return arm_address_register_rtx_p (ind
, 0);
8832 /* Autoincremment addressing modes. POST_INC and PRE_DEC are
8833 acceptable in any case (subject to verification by
8834 arm_address_register_rtx_p). We need WB to be true to accept
8835 PRE_INC and POST_DEC. */
8836 if (GET_CODE (ind
) == POST_INC
8837 || GET_CODE (ind
) == PRE_DEC
8839 && (GET_CODE (ind
) == PRE_INC
8840 || GET_CODE (ind
) == POST_DEC
)))
8841 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
8844 && (GET_CODE (ind
) == POST_MODIFY
|| GET_CODE (ind
) == PRE_MODIFY
)
8845 && arm_address_register_rtx_p (XEXP (ind
, 0), 0)
8846 && GET_CODE (XEXP (ind
, 1)) == PLUS
8847 && rtx_equal_p (XEXP (XEXP (ind
, 1), 0), XEXP (ind
, 0)))
8848 ind
= XEXP (ind
, 1);
8853 if (GET_CODE (ind
) == PLUS
8854 && GET_CODE (XEXP (ind
, 0)) == REG
8855 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
8856 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
8857 && INTVAL (XEXP (ind
, 1)) > -1024
8858 && INTVAL (XEXP (ind
, 1)) < 1024
8859 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
8865 /* Return TRUE if OP is a memory operand which we can load or store a vector
8866 to/from. TYPE is one of the following values:
8867 0 - Vector load/stor (vldr)
8868 1 - Core registers (ldm)
8869 2 - Element/structure loads (vld1)
8872 neon_vector_mem_operand (rtx op
, int type
)
8876 /* Reject eliminable registers. */
8877 if (! (reload_in_progress
|| reload_completed
)
8878 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
8879 || reg_mentioned_p (arg_pointer_rtx
, op
)
8880 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
8881 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
8882 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
8883 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
8886 /* Constants are converted into offsets from labels. */
8887 if (GET_CODE (op
) != MEM
)
8892 if (reload_completed
8893 && (GET_CODE (ind
) == LABEL_REF
8894 || (GET_CODE (ind
) == CONST
8895 && GET_CODE (XEXP (ind
, 0)) == PLUS
8896 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
8897 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
8900 /* Match: (mem (reg)). */
8901 if (GET_CODE (ind
) == REG
)
8902 return arm_address_register_rtx_p (ind
, 0);
8904 /* Allow post-increment with Neon registers. */
8905 if ((type
!= 1 && GET_CODE (ind
) == POST_INC
)
8906 || (type
== 0 && GET_CODE (ind
) == PRE_DEC
))
8907 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
8909 /* FIXME: vld1 allows register post-modify. */
8915 && GET_CODE (ind
) == PLUS
8916 && GET_CODE (XEXP (ind
, 0)) == REG
8917 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
8918 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
8919 && INTVAL (XEXP (ind
, 1)) > -1024
8920 && INTVAL (XEXP (ind
, 1)) < 1016
8921 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
8927 /* Return TRUE if OP is a mem suitable for loading/storing a Neon struct
8930 neon_struct_mem_operand (rtx op
)
8934 /* Reject eliminable registers. */
8935 if (! (reload_in_progress
|| reload_completed
)
8936 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
8937 || reg_mentioned_p (arg_pointer_rtx
, op
)
8938 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
8939 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
8940 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
8941 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
8944 /* Constants are converted into offsets from labels. */
8945 if (GET_CODE (op
) != MEM
)
8950 if (reload_completed
8951 && (GET_CODE (ind
) == LABEL_REF
8952 || (GET_CODE (ind
) == CONST
8953 && GET_CODE (XEXP (ind
, 0)) == PLUS
8954 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
8955 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
8958 /* Match: (mem (reg)). */
8959 if (GET_CODE (ind
) == REG
)
8960 return arm_address_register_rtx_p (ind
, 0);
8962 /* vldm/vstm allows POST_INC (ia) and PRE_DEC (db). */
8963 if (GET_CODE (ind
) == POST_INC
8964 || GET_CODE (ind
) == PRE_DEC
)
8965 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
8970 /* Return true if X is a register that will be eliminated later on. */
8972 arm_eliminable_register (rtx x
)
8974 return REG_P (x
) && (REGNO (x
) == FRAME_POINTER_REGNUM
8975 || REGNO (x
) == ARG_POINTER_REGNUM
8976 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
8977 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
));
8980 /* Return GENERAL_REGS if a scratch register required to reload x to/from
8981 coprocessor registers. Otherwise return NO_REGS. */
8984 coproc_secondary_reload_class (enum machine_mode mode
, rtx x
, bool wb
)
8988 if (!TARGET_NEON_FP16
)
8989 return GENERAL_REGS
;
8990 if (s_register_operand (x
, mode
) || neon_vector_mem_operand (x
, 2))
8992 return GENERAL_REGS
;
8995 /* The neon move patterns handle all legitimate vector and struct
8999 && (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
9000 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
9001 || VALID_NEON_STRUCT_MODE (mode
)))
9004 if (arm_coproc_mem_operand (x
, wb
) || s_register_operand (x
, mode
))
9007 return GENERAL_REGS
;
9010 /* Values which must be returned in the most-significant end of the return
9014 arm_return_in_msb (const_tree valtype
)
9016 return (TARGET_AAPCS_BASED
9018 && (AGGREGATE_TYPE_P (valtype
)
9019 || TREE_CODE (valtype
) == COMPLEX_TYPE
));
9022 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
9023 Use by the Cirrus Maverick code which has to workaround
9024 a hardware bug triggered by such instructions. */
9026 arm_memory_load_p (rtx insn
)
9028 rtx body
, lhs
, rhs
;;
9030 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
9033 body
= PATTERN (insn
);
9035 if (GET_CODE (body
) != SET
)
9038 lhs
= XEXP (body
, 0);
9039 rhs
= XEXP (body
, 1);
9041 lhs
= REG_OR_SUBREG_RTX (lhs
);
9043 /* If the destination is not a general purpose
9044 register we do not have to worry. */
9045 if (GET_CODE (lhs
) != REG
9046 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
9049 /* As well as loads from memory we also have to react
9050 to loads of invalid constants which will be turned
9051 into loads from the minipool. */
9052 return (GET_CODE (rhs
) == MEM
9053 || GET_CODE (rhs
) == SYMBOL_REF
9054 || note_invalid_constants (insn
, -1, false));
9057 /* Return TRUE if INSN is a Cirrus instruction. */
9059 arm_cirrus_insn_p (rtx insn
)
9061 enum attr_cirrus attr
;
9063 /* get_attr cannot accept USE or CLOBBER. */
9065 || GET_CODE (insn
) != INSN
9066 || GET_CODE (PATTERN (insn
)) == USE
9067 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
9070 attr
= get_attr_cirrus (insn
);
9072 return attr
!= CIRRUS_NOT
;
9075 /* Cirrus reorg for invalid instruction combinations. */
9077 cirrus_reorg (rtx first
)
9079 enum attr_cirrus attr
;
9080 rtx body
= PATTERN (first
);
9084 /* Any branch must be followed by 2 non Cirrus instructions. */
9085 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
9088 t
= next_nonnote_insn (first
);
9090 if (arm_cirrus_insn_p (t
))
9093 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
9097 emit_insn_after (gen_nop (), first
);
9102 /* (float (blah)) is in parallel with a clobber. */
9103 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
9104 body
= XVECEXP (body
, 0, 0);
9106 if (GET_CODE (body
) == SET
)
9108 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
9110 /* cfldrd, cfldr64, cfstrd, cfstr64 must
9111 be followed by a non Cirrus insn. */
9112 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
9114 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
9115 emit_insn_after (gen_nop (), first
);
9119 else if (arm_memory_load_p (first
))
9121 unsigned int arm_regno
;
9123 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
9124 ldr/cfmv64hr combination where the Rd field is the same
9125 in both instructions must be split with a non Cirrus
9132 /* Get Arm register number for ldr insn. */
9133 if (GET_CODE (lhs
) == REG
)
9134 arm_regno
= REGNO (lhs
);
9137 gcc_assert (GET_CODE (rhs
) == REG
);
9138 arm_regno
= REGNO (rhs
);
9142 first
= next_nonnote_insn (first
);
9144 if (! arm_cirrus_insn_p (first
))
9147 body
= PATTERN (first
);
9149 /* (float (blah)) is in parallel with a clobber. */
9150 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
9151 body
= XVECEXP (body
, 0, 0);
9153 if (GET_CODE (body
) == FLOAT
)
9154 body
= XEXP (body
, 0);
9156 if (get_attr_cirrus (first
) == CIRRUS_MOVE
9157 && GET_CODE (XEXP (body
, 1)) == REG
9158 && arm_regno
== REGNO (XEXP (body
, 1)))
9159 emit_insn_after (gen_nop (), first
);
9165 /* get_attr cannot accept USE or CLOBBER. */
9167 || GET_CODE (first
) != INSN
9168 || GET_CODE (PATTERN (first
)) == USE
9169 || GET_CODE (PATTERN (first
)) == CLOBBER
)
9172 attr
= get_attr_cirrus (first
);
9174 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
9175 must be followed by a non-coprocessor instruction. */
9176 if (attr
== CIRRUS_COMPARE
)
9180 t
= next_nonnote_insn (first
);
9182 if (arm_cirrus_insn_p (t
))
9185 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
9189 emit_insn_after (gen_nop (), first
);
9195 /* Return TRUE if X references a SYMBOL_REF. */
9197 symbol_mentioned_p (rtx x
)
9202 if (GET_CODE (x
) == SYMBOL_REF
)
9205 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
9206 are constant offsets, not symbols. */
9207 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
9210 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
9212 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
9218 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9219 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
9222 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
9229 /* Return TRUE if X references a LABEL_REF. */
9231 label_mentioned_p (rtx x
)
9236 if (GET_CODE (x
) == LABEL_REF
)
9239 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
9240 instruction, but they are constant offsets, not symbols. */
9241 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
9244 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
9245 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
9251 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9252 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
9255 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
9263 tls_mentioned_p (rtx x
)
9265 switch (GET_CODE (x
))
9268 return tls_mentioned_p (XEXP (x
, 0));
9271 if (XINT (x
, 1) == UNSPEC_TLS
)
9279 /* Must not copy any rtx that uses a pc-relative address. */
9282 arm_note_pic_base (rtx
*x
, void *date ATTRIBUTE_UNUSED
)
9284 if (GET_CODE (*x
) == UNSPEC
9285 && XINT (*x
, 1) == UNSPEC_PIC_BASE
)
9291 arm_cannot_copy_insn_p (rtx insn
)
9293 return for_each_rtx (&PATTERN (insn
), arm_note_pic_base
, NULL
);
9299 enum rtx_code code
= GET_CODE (x
);
9316 /* Return 1 if memory locations are adjacent. */
9318 adjacent_mem_locations (rtx a
, rtx b
)
9320 /* We don't guarantee to preserve the order of these memory refs. */
9321 if (volatile_refs_p (a
) || volatile_refs_p (b
))
9324 if ((GET_CODE (XEXP (a
, 0)) == REG
9325 || (GET_CODE (XEXP (a
, 0)) == PLUS
9326 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
9327 && (GET_CODE (XEXP (b
, 0)) == REG
9328 || (GET_CODE (XEXP (b
, 0)) == PLUS
9329 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
9331 HOST_WIDE_INT val0
= 0, val1
= 0;
9335 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
9337 reg0
= XEXP (XEXP (a
, 0), 0);
9338 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
9343 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
9345 reg1
= XEXP (XEXP (b
, 0), 0);
9346 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
9351 /* Don't accept any offset that will require multiple
9352 instructions to handle, since this would cause the
9353 arith_adjacentmem pattern to output an overlong sequence. */
9354 if (!const_ok_for_op (val0
, PLUS
) || !const_ok_for_op (val1
, PLUS
))
9357 /* Don't allow an eliminable register: register elimination can make
9358 the offset too large. */
9359 if (arm_eliminable_register (reg0
))
9362 val_diff
= val1
- val0
;
9366 /* If the target has load delay slots, then there's no benefit
9367 to using an ldm instruction unless the offset is zero and
9368 we are optimizing for size. */
9369 return (optimize_size
&& (REGNO (reg0
) == REGNO (reg1
))
9370 && (val0
== 0 || val1
== 0 || val0
== 4 || val1
== 4)
9371 && (val_diff
== 4 || val_diff
== -4));
9374 return ((REGNO (reg0
) == REGNO (reg1
))
9375 && (val_diff
== 4 || val_diff
== -4));
9381 /* Return true iff it would be profitable to turn a sequence of NOPS loads
9382 or stores (depending on IS_STORE) into a load-multiple or store-multiple
9383 instruction. ADD_OFFSET is nonzero if the base address register needs
9384 to be modified with an add instruction before we can use it. */
9387 multiple_operation_profitable_p (bool is_store ATTRIBUTE_UNUSED
,
9388 int nops
, HOST_WIDE_INT add_offset
)
9390 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
9391 if the offset isn't small enough. The reason 2 ldrs are faster
9392 is because these ARMs are able to do more than one cache access
9393 in a single cycle. The ARM9 and StrongARM have Harvard caches,
9394 whilst the ARM8 has a double bandwidth cache. This means that
9395 these cores can do both an instruction fetch and a data fetch in
9396 a single cycle, so the trick of calculating the address into a
9397 scratch register (one of the result regs) and then doing a load
9398 multiple actually becomes slower (and no smaller in code size).
9399 That is the transformation
9401 ldr rd1, [rbase + offset]
9402 ldr rd2, [rbase + offset + 4]
9406 add rd1, rbase, offset
9407 ldmia rd1, {rd1, rd2}
9409 produces worse code -- '3 cycles + any stalls on rd2' instead of
9410 '2 cycles + any stalls on rd2'. On ARMs with only one cache
9411 access per cycle, the first sequence could never complete in less
9412 than 6 cycles, whereas the ldm sequence would only take 5 and
9413 would make better use of sequential accesses if not hitting the
9416 We cheat here and test 'arm_ld_sched' which we currently know to
9417 only be true for the ARM8, ARM9 and StrongARM. If this ever
9418 changes, then the test below needs to be reworked. */
9419 if (nops
== 2 && arm_ld_sched
&& add_offset
!= 0)
9422 /* XScale has load-store double instructions, but they have stricter
9423 alignment requirements than load-store multiple, so we cannot
9426 For XScale ldm requires 2 + NREGS cycles to complete and blocks
9427 the pipeline until completion.
9435 An ldr instruction takes 1-3 cycles, but does not block the
9444 Best case ldr will always win. However, the more ldr instructions
9445 we issue, the less likely we are to be able to schedule them well.
9446 Using ldr instructions also increases code size.
9448 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
9449 for counts of 3 or 4 regs. */
9450 if (nops
<= 2 && arm_tune_xscale
&& !optimize_size
)
9455 /* Subroutine of load_multiple_sequence and store_multiple_sequence.
9456 Given an array of UNSORTED_OFFSETS, of which there are NOPS, compute
9457 an array ORDER which describes the sequence to use when accessing the
9458 offsets that produces an ascending order. In this sequence, each
9459 offset must be larger by exactly 4 than the previous one. ORDER[0]
9460 must have been filled in with the lowest offset by the caller.
9461 If UNSORTED_REGS is nonnull, it is an array of register numbers that
9462 we use to verify that ORDER produces an ascending order of registers.
9463 Return true if it was possible to construct such an order, false if
9467 compute_offset_order (int nops
, HOST_WIDE_INT
*unsorted_offsets
, int *order
,
9471 for (i
= 1; i
< nops
; i
++)
9475 order
[i
] = order
[i
- 1];
9476 for (j
= 0; j
< nops
; j
++)
9477 if (unsorted_offsets
[j
] == unsorted_offsets
[order
[i
- 1]] + 4)
9479 /* We must find exactly one offset that is higher than the
9480 previous one by 4. */
9481 if (order
[i
] != order
[i
- 1])
9485 if (order
[i
] == order
[i
- 1])
9487 /* The register numbers must be ascending. */
9488 if (unsorted_regs
!= NULL
9489 && unsorted_regs
[order
[i
]] <= unsorted_regs
[order
[i
- 1]])
9495 /* Used to determine in a peephole whether a sequence of load
9496 instructions can be changed into a load-multiple instruction.
9497 NOPS is the number of separate load instructions we are examining. The
9498 first NOPS entries in OPERANDS are the destination registers, the
9499 next NOPS entries are memory operands. If this function is
9500 successful, *BASE is set to the common base register of the memory
9501 accesses; *LOAD_OFFSET is set to the first memory location's offset
9502 from that base register.
9503 REGS is an array filled in with the destination register numbers.
9504 SAVED_ORDER (if nonnull), is an array filled in with an order that maps
9505 insn numbers to an ascending order of stores. If CHECK_REGS is true,
9506 the sequence of registers in REGS matches the loads from ascending memory
9507 locations, and the function verifies that the register numbers are
9508 themselves ascending. If CHECK_REGS is false, the register numbers
9509 are stored in the order they are found in the operands. */
9511 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *saved_order
,
9512 int *base
, HOST_WIDE_INT
*load_offset
, bool check_regs
)
9514 int unsorted_regs
[MAX_LDM_STM_OPS
];
9515 HOST_WIDE_INT unsorted_offsets
[MAX_LDM_STM_OPS
];
9516 int order
[MAX_LDM_STM_OPS
];
9517 rtx base_reg_rtx
= NULL
;
9521 /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be
9522 easily extended if required. */
9523 gcc_assert (nops
>= 2 && nops
<= MAX_LDM_STM_OPS
);
9525 memset (order
, 0, MAX_LDM_STM_OPS
* sizeof (int));
9527 /* Loop over the operands and check that the memory references are
9528 suitable (i.e. immediate offsets from the same base register). At
9529 the same time, extract the target register, and the memory
9531 for (i
= 0; i
< nops
; i
++)
9536 /* Convert a subreg of a mem into the mem itself. */
9537 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
9538 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
9540 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
9542 /* Don't reorder volatile memory references; it doesn't seem worth
9543 looking for the case where the order is ok anyway. */
9544 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
9547 offset
= const0_rtx
;
9549 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
9550 || (GET_CODE (reg
) == SUBREG
9551 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
9552 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
9553 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
9555 || (GET_CODE (reg
) == SUBREG
9556 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
9557 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
9562 base_reg
= REGNO (reg
);
9564 if (TARGET_THUMB1
&& base_reg
> LAST_LO_REGNUM
)
9567 else if (base_reg
!= (int) REGNO (reg
))
9568 /* Not addressed from the same base register. */
9571 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
9572 ? REGNO (operands
[i
])
9573 : REGNO (SUBREG_REG (operands
[i
])));
9575 /* If it isn't an integer register, or if it overwrites the
9576 base register but isn't the last insn in the list, then
9577 we can't do this. */
9578 if (unsorted_regs
[i
] < 0
9579 || (TARGET_THUMB1
&& unsorted_regs
[i
] > LAST_LO_REGNUM
)
9580 || unsorted_regs
[i
] > 14
9581 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
9584 unsorted_offsets
[i
] = INTVAL (offset
);
9585 if (i
== 0 || unsorted_offsets
[i
] < unsorted_offsets
[order
[0]])
9589 /* Not a suitable memory address. */
9593 /* All the useful information has now been extracted from the
9594 operands into unsorted_regs and unsorted_offsets; additionally,
9595 order[0] has been set to the lowest offset in the list. Sort
9596 the offsets into order, verifying that they are adjacent, and
9597 check that the register numbers are ascending. */
9598 if (!compute_offset_order (nops
, unsorted_offsets
, order
,
9599 check_regs
? unsorted_regs
: NULL
))
9603 memcpy (saved_order
, order
, sizeof order
);
9609 for (i
= 0; i
< nops
; i
++)
9610 regs
[i
] = unsorted_regs
[check_regs
? order
[i
] : i
];
9612 *load_offset
= unsorted_offsets
[order
[0]];
9616 && !peep2_reg_dead_p (nops
, base_reg_rtx
))
9619 if (unsorted_offsets
[order
[0]] == 0)
9620 ldm_case
= 1; /* ldmia */
9621 else if (TARGET_ARM
&& unsorted_offsets
[order
[0]] == 4)
9622 ldm_case
= 2; /* ldmib */
9623 else if (TARGET_ARM
&& unsorted_offsets
[order
[nops
- 1]] == 0)
9624 ldm_case
= 3; /* ldmda */
9625 else if (TARGET_32BIT
&& unsorted_offsets
[order
[nops
- 1]] == -4)
9626 ldm_case
= 4; /* ldmdb */
9627 else if (const_ok_for_arm (unsorted_offsets
[order
[0]])
9628 || const_ok_for_arm (-unsorted_offsets
[order
[0]]))
9633 if (!multiple_operation_profitable_p (false, nops
,
9635 ? unsorted_offsets
[order
[0]] : 0))
9641 /* Used to determine in a peephole whether a sequence of store instructions can
9642 be changed into a store-multiple instruction.
9643 NOPS is the number of separate store instructions we are examining.
9644 NOPS_TOTAL is the total number of instructions recognized by the peephole
9646 The first NOPS entries in OPERANDS are the source registers, the next
9647 NOPS entries are memory operands. If this function is successful, *BASE is
9648 set to the common base register of the memory accesses; *LOAD_OFFSET is set
9649 to the first memory location's offset from that base register. REGS is an
9650 array filled in with the source register numbers, REG_RTXS (if nonnull) is
9651 likewise filled with the corresponding rtx's.
9652 SAVED_ORDER (if nonnull), is an array filled in with an order that maps insn
9653 numbers to an ascending order of stores.
9654 If CHECK_REGS is true, the sequence of registers in *REGS matches the stores
9655 from ascending memory locations, and the function verifies that the register
9656 numbers are themselves ascending. If CHECK_REGS is false, the register
9657 numbers are stored in the order they are found in the operands. */
9659 store_multiple_sequence (rtx
*operands
, int nops
, int nops_total
,
9660 int *regs
, rtx
*reg_rtxs
, int *saved_order
, int *base
,
9661 HOST_WIDE_INT
*load_offset
, bool check_regs
)
9663 int unsorted_regs
[MAX_LDM_STM_OPS
];
9664 rtx unsorted_reg_rtxs
[MAX_LDM_STM_OPS
];
9665 HOST_WIDE_INT unsorted_offsets
[MAX_LDM_STM_OPS
];
9666 int order
[MAX_LDM_STM_OPS
];
9668 rtx base_reg_rtx
= NULL
;
9671 /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be
9672 easily extended if required. */
9673 gcc_assert (nops
>= 2 && nops
<= MAX_LDM_STM_OPS
);
9675 memset (order
, 0, MAX_LDM_STM_OPS
* sizeof (int));
9677 /* Loop over the operands and check that the memory references are
9678 suitable (i.e. immediate offsets from the same base register). At
9679 the same time, extract the target register, and the memory
9681 for (i
= 0; i
< nops
; i
++)
9686 /* Convert a subreg of a mem into the mem itself. */
9687 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
9688 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
9690 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
9692 /* Don't reorder volatile memory references; it doesn't seem worth
9693 looking for the case where the order is ok anyway. */
9694 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
9697 offset
= const0_rtx
;
9699 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
9700 || (GET_CODE (reg
) == SUBREG
9701 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
9702 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
9703 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
9705 || (GET_CODE (reg
) == SUBREG
9706 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
9707 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
9710 unsorted_reg_rtxs
[i
] = (GET_CODE (operands
[i
]) == REG
9711 ? operands
[i
] : SUBREG_REG (operands
[i
]));
9712 unsorted_regs
[i
] = REGNO (unsorted_reg_rtxs
[i
]);
9716 base_reg
= REGNO (reg
);
9718 if (TARGET_THUMB1
&& base_reg
> LAST_LO_REGNUM
)
9721 else if (base_reg
!= (int) REGNO (reg
))
9722 /* Not addressed from the same base register. */
9725 /* If it isn't an integer register, then we can't do this. */
9726 if (unsorted_regs
[i
] < 0
9727 || (TARGET_THUMB1
&& unsorted_regs
[i
] > LAST_LO_REGNUM
)
9728 || (TARGET_THUMB2
&& unsorted_regs
[i
] == base_reg
)
9729 || (TARGET_THUMB2
&& unsorted_regs
[i
] == SP_REGNUM
)
9730 || unsorted_regs
[i
] > 14)
9733 unsorted_offsets
[i
] = INTVAL (offset
);
9734 if (i
== 0 || unsorted_offsets
[i
] < unsorted_offsets
[order
[0]])
9738 /* Not a suitable memory address. */
9742 /* All the useful information has now been extracted from the
9743 operands into unsorted_regs and unsorted_offsets; additionally,
9744 order[0] has been set to the lowest offset in the list. Sort
9745 the offsets into order, verifying that they are adjacent, and
9746 check that the register numbers are ascending. */
9747 if (!compute_offset_order (nops
, unsorted_offsets
, order
,
9748 check_regs
? unsorted_regs
: NULL
))
9752 memcpy (saved_order
, order
, sizeof order
);
9758 for (i
= 0; i
< nops
; i
++)
9760 regs
[i
] = unsorted_regs
[check_regs
? order
[i
] : i
];
9762 reg_rtxs
[i
] = unsorted_reg_rtxs
[check_regs
? order
[i
] : i
];
9765 *load_offset
= unsorted_offsets
[order
[0]];
9769 && !peep2_reg_dead_p (nops_total
, base_reg_rtx
))
9772 if (unsorted_offsets
[order
[0]] == 0)
9773 stm_case
= 1; /* stmia */
9774 else if (TARGET_ARM
&& unsorted_offsets
[order
[0]] == 4)
9775 stm_case
= 2; /* stmib */
9776 else if (TARGET_ARM
&& unsorted_offsets
[order
[nops
- 1]] == 0)
9777 stm_case
= 3; /* stmda */
9778 else if (TARGET_32BIT
&& unsorted_offsets
[order
[nops
- 1]] == -4)
9779 stm_case
= 4; /* stmdb */
9783 if (!multiple_operation_profitable_p (false, nops
, 0))
9789 /* Routines for use in generating RTL. */
9791 /* Generate a load-multiple instruction. COUNT is the number of loads in
9792 the instruction; REGS and MEMS are arrays containing the operands.
9793 BASEREG is the base register to be used in addressing the memory operands.
9794 WBACK_OFFSET is nonzero if the instruction should update the base
9798 arm_gen_load_multiple_1 (int count
, int *regs
, rtx
*mems
, rtx basereg
,
9799 HOST_WIDE_INT wback_offset
)
9804 if (!multiple_operation_profitable_p (false, count
, 0))
9810 for (i
= 0; i
< count
; i
++)
9811 emit_move_insn (gen_rtx_REG (SImode
, regs
[i
]), mems
[i
]);
9813 if (wback_offset
!= 0)
9814 emit_move_insn (basereg
, plus_constant (basereg
, wback_offset
));
9822 result
= gen_rtx_PARALLEL (VOIDmode
,
9823 rtvec_alloc (count
+ (wback_offset
!= 0 ? 1 : 0)));
9824 if (wback_offset
!= 0)
9826 XVECEXP (result
, 0, 0)
9827 = gen_rtx_SET (VOIDmode
, basereg
,
9828 plus_constant (basereg
, wback_offset
));
9833 for (j
= 0; i
< count
; i
++, j
++)
9834 XVECEXP (result
, 0, i
)
9835 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, regs
[j
]), mems
[j
]);
9840 /* Generate a store-multiple instruction. COUNT is the number of stores in
9841 the instruction; REGS and MEMS are arrays containing the operands.
9842 BASEREG is the base register to be used in addressing the memory operands.
9843 WBACK_OFFSET is nonzero if the instruction should update the base
9847 arm_gen_store_multiple_1 (int count
, int *regs
, rtx
*mems
, rtx basereg
,
9848 HOST_WIDE_INT wback_offset
)
9853 if (GET_CODE (basereg
) == PLUS
)
9854 basereg
= XEXP (basereg
, 0);
9856 if (!multiple_operation_profitable_p (false, count
, 0))
9862 for (i
= 0; i
< count
; i
++)
9863 emit_move_insn (mems
[i
], gen_rtx_REG (SImode
, regs
[i
]));
9865 if (wback_offset
!= 0)
9866 emit_move_insn (basereg
, plus_constant (basereg
, wback_offset
));
9874 result
= gen_rtx_PARALLEL (VOIDmode
,
9875 rtvec_alloc (count
+ (wback_offset
!= 0 ? 1 : 0)));
9876 if (wback_offset
!= 0)
9878 XVECEXP (result
, 0, 0)
9879 = gen_rtx_SET (VOIDmode
, basereg
,
9880 plus_constant (basereg
, wback_offset
));
9885 for (j
= 0; i
< count
; i
++, j
++)
9886 XVECEXP (result
, 0, i
)
9887 = gen_rtx_SET (VOIDmode
, mems
[j
], gen_rtx_REG (SImode
, regs
[j
]));
9892 /* Generate either a load-multiple or a store-multiple instruction. This
9893 function can be used in situations where we can start with a single MEM
9894 rtx and adjust its address upwards.
9895 COUNT is the number of operations in the instruction, not counting a
9896 possible update of the base register. REGS is an array containing the
9898 BASEREG is the base register to be used in addressing the memory operands,
9899 which are constructed from BASEMEM.
9900 WRITE_BACK specifies whether the generated instruction should include an
9901 update of the base register.
9902 OFFSETP is used to pass an offset to and from this function; this offset
9903 is not used when constructing the address (instead BASEMEM should have an
9904 appropriate offset in its address), it is used only for setting
9905 MEM_OFFSET. It is updated only if WRITE_BACK is true.*/
9908 arm_gen_multiple_op (bool is_load
, int *regs
, int count
, rtx basereg
,
9909 bool write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
9911 rtx mems
[MAX_LDM_STM_OPS
];
9912 HOST_WIDE_INT offset
= *offsetp
;
9915 gcc_assert (count
<= MAX_LDM_STM_OPS
);
9917 if (GET_CODE (basereg
) == PLUS
)
9918 basereg
= XEXP (basereg
, 0);
9920 for (i
= 0; i
< count
; i
++)
9922 rtx addr
= plus_constant (basereg
, i
* 4);
9923 mems
[i
] = adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
9931 return arm_gen_load_multiple_1 (count
, regs
, mems
, basereg
,
9932 write_back
? 4 * count
: 0);
9934 return arm_gen_store_multiple_1 (count
, regs
, mems
, basereg
,
9935 write_back
? 4 * count
: 0);
9939 arm_gen_load_multiple (int *regs
, int count
, rtx basereg
, int write_back
,
9940 rtx basemem
, HOST_WIDE_INT
*offsetp
)
9942 return arm_gen_multiple_op (TRUE
, regs
, count
, basereg
, write_back
, basemem
,
9947 arm_gen_store_multiple (int *regs
, int count
, rtx basereg
, int write_back
,
9948 rtx basemem
, HOST_WIDE_INT
*offsetp
)
9950 return arm_gen_multiple_op (FALSE
, regs
, count
, basereg
, write_back
, basemem
,
9954 /* Called from a peephole2 expander to turn a sequence of loads into an
9955 LDM instruction. OPERANDS are the operands found by the peephole matcher;
9956 NOPS indicates how many separate loads we are trying to combine. SORT_REGS
9957 is true if we can reorder the registers because they are used commutatively
9959 Returns true iff we could generate a new instruction. */
9962 gen_ldm_seq (rtx
*operands
, int nops
, bool sort_regs
)
9964 int regs
[MAX_LDM_STM_OPS
], mem_order
[MAX_LDM_STM_OPS
];
9965 rtx mems
[MAX_LDM_STM_OPS
];
9968 HOST_WIDE_INT offset
;
9969 int write_back
= FALSE
;
9973 ldm_case
= load_multiple_sequence (operands
, nops
, regs
, mem_order
,
9974 &base_reg
, &offset
, !sort_regs
);
9980 for (i
= 0; i
< nops
- 1; i
++)
9981 for (j
= i
+ 1; j
< nops
; j
++)
9982 if (regs
[i
] > regs
[j
])
9988 base_reg_rtx
= gen_rtx_REG (Pmode
, base_reg
);
9992 gcc_assert (peep2_reg_dead_p (nops
, base_reg_rtx
));
9993 gcc_assert (ldm_case
== 1 || ldm_case
== 5);
9999 rtx newbase
= TARGET_THUMB1
? base_reg_rtx
: gen_rtx_REG (SImode
, regs
[0]);
10000 emit_insn (gen_addsi3 (newbase
, base_reg_rtx
, GEN_INT (offset
)));
10002 if (!TARGET_THUMB1
)
10004 base_reg
= regs
[0];
10005 base_reg_rtx
= newbase
;
10009 for (i
= 0; i
< nops
; i
++)
10011 addr
= plus_constant (base_reg_rtx
, offset
+ i
* 4);
10012 mems
[i
] = adjust_automodify_address_nv (operands
[nops
+ mem_order
[i
]],
10015 emit_insn (arm_gen_load_multiple_1 (nops
, regs
, mems
, base_reg_rtx
,
10016 write_back
? offset
+ i
* 4 : 0));
10020 /* Called from a peephole2 expander to turn a sequence of stores into an
10021 STM instruction. OPERANDS are the operands found by the peephole matcher;
10022 NOPS indicates how many separate stores we are trying to combine.
10023 Returns true iff we could generate a new instruction. */
10026 gen_stm_seq (rtx
*operands
, int nops
)
10029 int regs
[MAX_LDM_STM_OPS
], mem_order
[MAX_LDM_STM_OPS
];
10030 rtx mems
[MAX_LDM_STM_OPS
];
10033 HOST_WIDE_INT offset
;
10034 int write_back
= FALSE
;
10037 bool base_reg_dies
;
10039 stm_case
= store_multiple_sequence (operands
, nops
, nops
, regs
, NULL
,
10040 mem_order
, &base_reg
, &offset
, true);
10045 base_reg_rtx
= gen_rtx_REG (Pmode
, base_reg
);
10047 base_reg_dies
= peep2_reg_dead_p (nops
, base_reg_rtx
);
10050 gcc_assert (base_reg_dies
);
10056 gcc_assert (base_reg_dies
);
10057 emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, GEN_INT (offset
)));
10061 addr
= plus_constant (base_reg_rtx
, offset
);
10063 for (i
= 0; i
< nops
; i
++)
10065 addr
= plus_constant (base_reg_rtx
, offset
+ i
* 4);
10066 mems
[i
] = adjust_automodify_address_nv (operands
[nops
+ mem_order
[i
]],
10069 emit_insn (arm_gen_store_multiple_1 (nops
, regs
, mems
, base_reg_rtx
,
10070 write_back
? offset
+ i
* 4 : 0));
10074 /* Called from a peephole2 expander to turn a sequence of stores that are
10075 preceded by constant loads into an STM instruction. OPERANDS are the
10076 operands found by the peephole matcher; NOPS indicates how many
10077 separate stores we are trying to combine; there are 2 * NOPS
10078 instructions in the peephole.
10079 Returns true iff we could generate a new instruction. */
10082 gen_const_stm_seq (rtx
*operands
, int nops
)
10084 int regs
[MAX_LDM_STM_OPS
], sorted_regs
[MAX_LDM_STM_OPS
];
10085 int reg_order
[MAX_LDM_STM_OPS
], mem_order
[MAX_LDM_STM_OPS
];
10086 rtx reg_rtxs
[MAX_LDM_STM_OPS
], orig_reg_rtxs
[MAX_LDM_STM_OPS
];
10087 rtx mems
[MAX_LDM_STM_OPS
];
10090 HOST_WIDE_INT offset
;
10091 int write_back
= FALSE
;
10094 bool base_reg_dies
;
10096 HARD_REG_SET allocated
;
10098 stm_case
= store_multiple_sequence (operands
, nops
, 2 * nops
, regs
, reg_rtxs
,
10099 mem_order
, &base_reg
, &offset
, false);
10104 memcpy (orig_reg_rtxs
, reg_rtxs
, sizeof orig_reg_rtxs
);
10106 /* If the same register is used more than once, try to find a free
10108 CLEAR_HARD_REG_SET (allocated
);
10109 for (i
= 0; i
< nops
; i
++)
10111 for (j
= i
+ 1; j
< nops
; j
++)
10112 if (regs
[i
] == regs
[j
])
10114 rtx t
= peep2_find_free_register (0, nops
* 2,
10115 TARGET_THUMB1
? "l" : "r",
10116 SImode
, &allocated
);
10120 regs
[i
] = REGNO (t
);
10124 /* Compute an ordering that maps the register numbers to an ascending
10127 for (i
= 0; i
< nops
; i
++)
10128 if (regs
[i
] < regs
[reg_order
[0]])
10131 for (i
= 1; i
< nops
; i
++)
10133 int this_order
= reg_order
[i
- 1];
10134 for (j
= 0; j
< nops
; j
++)
10135 if (regs
[j
] > regs
[reg_order
[i
- 1]]
10136 && (this_order
== reg_order
[i
- 1]
10137 || regs
[j
] < regs
[this_order
]))
10139 reg_order
[i
] = this_order
;
10142 /* Ensure that registers that must be live after the instruction end
10143 up with the correct value. */
10144 for (i
= 0; i
< nops
; i
++)
10146 int this_order
= reg_order
[i
];
10147 if ((this_order
!= mem_order
[i
]
10148 || orig_reg_rtxs
[this_order
] != reg_rtxs
[this_order
])
10149 && !peep2_reg_dead_p (nops
* 2, orig_reg_rtxs
[this_order
]))
10153 /* Load the constants. */
10154 for (i
= 0; i
< nops
; i
++)
10156 rtx op
= operands
[2 * nops
+ mem_order
[i
]];
10157 sorted_regs
[i
] = regs
[reg_order
[i
]];
10158 emit_move_insn (reg_rtxs
[reg_order
[i
]], op
);
10161 base_reg_rtx
= gen_rtx_REG (Pmode
, base_reg
);
10163 base_reg_dies
= peep2_reg_dead_p (nops
* 2, base_reg_rtx
);
10166 gcc_assert (base_reg_dies
);
10172 gcc_assert (base_reg_dies
);
10173 emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, GEN_INT (offset
)));
10177 addr
= plus_constant (base_reg_rtx
, offset
);
10179 for (i
= 0; i
< nops
; i
++)
10181 addr
= plus_constant (base_reg_rtx
, offset
+ i
* 4);
10182 mems
[i
] = adjust_automodify_address_nv (operands
[nops
+ mem_order
[i
]],
10185 emit_insn (arm_gen_store_multiple_1 (nops
, sorted_regs
, mems
, base_reg_rtx
,
10186 write_back
? offset
+ i
* 4 : 0));
10191 arm_gen_movmemqi (rtx
*operands
)
10193 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
10194 HOST_WIDE_INT srcoffset
, dstoffset
;
10196 rtx src
, dst
, srcbase
, dstbase
;
10197 rtx part_bytes_reg
= NULL
;
10200 if (GET_CODE (operands
[2]) != CONST_INT
10201 || GET_CODE (operands
[3]) != CONST_INT
10202 || INTVAL (operands
[2]) > 64
10203 || INTVAL (operands
[3]) & 3)
10206 dstbase
= operands
[0];
10207 srcbase
= operands
[1];
10209 dst
= copy_to_mode_reg (SImode
, XEXP (dstbase
, 0));
10210 src
= copy_to_mode_reg (SImode
, XEXP (srcbase
, 0));
10212 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
10213 out_words_to_go
= INTVAL (operands
[2]) / 4;
10214 last_bytes
= INTVAL (operands
[2]) & 3;
10215 dstoffset
= srcoffset
= 0;
10217 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
10218 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
10220 for (i
= 0; in_words_to_go
>= 2; i
+=4)
10222 if (in_words_to_go
> 4)
10223 emit_insn (arm_gen_load_multiple (arm_regs_in_sequence
, 4, src
,
10224 TRUE
, srcbase
, &srcoffset
));
10226 emit_insn (arm_gen_load_multiple (arm_regs_in_sequence
, in_words_to_go
,
10227 src
, FALSE
, srcbase
,
10230 if (out_words_to_go
)
10232 if (out_words_to_go
> 4)
10233 emit_insn (arm_gen_store_multiple (arm_regs_in_sequence
, 4, dst
,
10234 TRUE
, dstbase
, &dstoffset
));
10235 else if (out_words_to_go
!= 1)
10236 emit_insn (arm_gen_store_multiple (arm_regs_in_sequence
,
10237 out_words_to_go
, dst
,
10240 dstbase
, &dstoffset
));
10243 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
10244 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
10245 if (last_bytes
!= 0)
10247 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
10253 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
10254 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
10257 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
10258 if (out_words_to_go
)
10262 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
10263 sreg
= copy_to_reg (mem
);
10265 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
10266 emit_move_insn (mem
, sreg
);
10269 gcc_assert (!in_words_to_go
); /* Sanity check */
10272 if (in_words_to_go
)
10274 gcc_assert (in_words_to_go
> 0);
10276 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
10277 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
10280 gcc_assert (!last_bytes
|| part_bytes_reg
);
10282 if (BYTES_BIG_ENDIAN
&& last_bytes
)
10284 rtx tmp
= gen_reg_rtx (SImode
);
10286 /* The bytes we want are in the top end of the word. */
10287 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
10288 GEN_INT (8 * (4 - last_bytes
))));
10289 part_bytes_reg
= tmp
;
10293 mem
= adjust_automodify_address (dstbase
, QImode
,
10294 plus_constant (dst
, last_bytes
- 1),
10295 dstoffset
+ last_bytes
- 1);
10296 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
10300 tmp
= gen_reg_rtx (SImode
);
10301 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
10302 part_bytes_reg
= tmp
;
10309 if (last_bytes
> 1)
10311 mem
= adjust_automodify_address (dstbase
, HImode
, dst
, dstoffset
);
10312 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
10316 rtx tmp
= gen_reg_rtx (SImode
);
10317 emit_insn (gen_addsi3 (dst
, dst
, const2_rtx
));
10318 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
10319 part_bytes_reg
= tmp
;
10326 mem
= adjust_automodify_address (dstbase
, QImode
, dst
, dstoffset
);
10327 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
10334 /* Select a dominance comparison mode if possible for a test of the general
10335 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
10336 COND_OR == DOM_CC_X_AND_Y => (X && Y)
10337 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
10338 COND_OR == DOM_CC_X_OR_Y => (X || Y)
10339 In all cases OP will be either EQ or NE, but we don't need to know which
10340 here. If we are unable to support a dominance comparison we return
10341 CC mode. This will then fail to match for the RTL expressions that
10342 generate this call. */
10344 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
10346 enum rtx_code cond1
, cond2
;
10349 /* Currently we will probably get the wrong result if the individual
10350 comparisons are not simple. This also ensures that it is safe to
10351 reverse a comparison if necessary. */
10352 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
10354 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
10358 /* The if_then_else variant of this tests the second condition if the
10359 first passes, but is true if the first fails. Reverse the first
10360 condition to get a true "inclusive-or" expression. */
10361 if (cond_or
== DOM_CC_NX_OR_Y
)
10362 cond1
= reverse_condition (cond1
);
10364 /* If the comparisons are not equal, and one doesn't dominate the other,
10365 then we can't do this. */
10367 && !comparison_dominates_p (cond1
, cond2
)
10368 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
10373 enum rtx_code temp
= cond1
;
10381 if (cond_or
== DOM_CC_X_AND_Y
)
10386 case EQ
: return CC_DEQmode
;
10387 case LE
: return CC_DLEmode
;
10388 case LEU
: return CC_DLEUmode
;
10389 case GE
: return CC_DGEmode
;
10390 case GEU
: return CC_DGEUmode
;
10391 default: gcc_unreachable ();
10395 if (cond_or
== DOM_CC_X_AND_Y
)
10407 gcc_unreachable ();
10411 if (cond_or
== DOM_CC_X_AND_Y
)
10423 gcc_unreachable ();
10427 if (cond_or
== DOM_CC_X_AND_Y
)
10428 return CC_DLTUmode
;
10433 return CC_DLTUmode
;
10435 return CC_DLEUmode
;
10439 gcc_unreachable ();
10443 if (cond_or
== DOM_CC_X_AND_Y
)
10444 return CC_DGTUmode
;
10449 return CC_DGTUmode
;
10451 return CC_DGEUmode
;
10455 gcc_unreachable ();
10458 /* The remaining cases only occur when both comparisons are the
10461 gcc_assert (cond1
== cond2
);
10465 gcc_assert (cond1
== cond2
);
10469 gcc_assert (cond1
== cond2
);
10473 gcc_assert (cond1
== cond2
);
10474 return CC_DLEUmode
;
10477 gcc_assert (cond1
== cond2
);
10478 return CC_DGEUmode
;
10481 gcc_unreachable ();
10486 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
10488 /* All floating point compares return CCFP if it is an equality
10489 comparison, and CCFPE otherwise. */
10490 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
10510 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
)
10515 gcc_unreachable ();
10519 /* A compare with a shifted operand. Because of canonicalization, the
10520 comparison will have to be swapped when we emit the assembler. */
10521 if (GET_MODE (y
) == SImode
10522 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
))
10523 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
10524 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
10525 || GET_CODE (x
) == ROTATERT
))
10528 /* This operation is performed swapped, but since we only rely on the Z
10529 flag we don't need an additional mode. */
10530 if (GET_MODE (y
) == SImode
10531 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
))
10532 && GET_CODE (x
) == NEG
10533 && (op
== EQ
|| op
== NE
))
10536 /* This is a special case that is used by combine to allow a
10537 comparison of a shifted byte load to be split into a zero-extend
10538 followed by a comparison of the shifted integer (only valid for
10539 equalities and unsigned inequalities). */
10540 if (GET_MODE (x
) == SImode
10541 && GET_CODE (x
) == ASHIFT
10542 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
10543 && GET_CODE (XEXP (x
, 0)) == SUBREG
10544 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
10545 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
10546 && (op
== EQ
|| op
== NE
10547 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
10548 && GET_CODE (y
) == CONST_INT
)
10551 /* A construct for a conditional compare, if the false arm contains
10552 0, then both conditions must be true, otherwise either condition
10553 must be true. Not all conditions are possible, so CCmode is
10554 returned if it can't be done. */
10555 if (GET_CODE (x
) == IF_THEN_ELSE
10556 && (XEXP (x
, 2) == const0_rtx
10557 || XEXP (x
, 2) == const1_rtx
)
10558 && COMPARISON_P (XEXP (x
, 0))
10559 && COMPARISON_P (XEXP (x
, 1)))
10560 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
10561 INTVAL (XEXP (x
, 2)));
10563 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
10564 if (GET_CODE (x
) == AND
10565 && (op
== EQ
|| op
== NE
)
10566 && COMPARISON_P (XEXP (x
, 0))
10567 && COMPARISON_P (XEXP (x
, 1)))
10568 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
10571 if (GET_CODE (x
) == IOR
10572 && (op
== EQ
|| op
== NE
)
10573 && COMPARISON_P (XEXP (x
, 0))
10574 && COMPARISON_P (XEXP (x
, 1)))
10575 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
10578 /* An operation (on Thumb) where we want to test for a single bit.
10579 This is done by shifting that bit up into the top bit of a
10580 scratch register; we can then branch on the sign bit. */
10582 && GET_MODE (x
) == SImode
10583 && (op
== EQ
|| op
== NE
)
10584 && GET_CODE (x
) == ZERO_EXTRACT
10585 && XEXP (x
, 1) == const1_rtx
)
10588 /* An operation that sets the condition codes as a side-effect, the
10589 V flag is not set correctly, so we can only use comparisons where
10590 this doesn't matter. (For LT and GE we can use "mi" and "pl"
10592 /* ??? Does the ZERO_EXTRACT case really apply to thumb2? */
10593 if (GET_MODE (x
) == SImode
10595 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
10596 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
10597 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
10598 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
10599 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
10600 || GET_CODE (x
) == LSHIFTRT
10601 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
10602 || GET_CODE (x
) == ROTATERT
10603 || (TARGET_32BIT
&& GET_CODE (x
) == ZERO_EXTRACT
)))
10604 return CC_NOOVmode
;
10606 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
10609 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
10610 && GET_CODE (x
) == PLUS
10611 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
10614 if (GET_MODE (x
) == DImode
|| GET_MODE (y
) == DImode
)
10616 /* To keep things simple, always use the Cirrus cfcmp64 if it is
10618 if (TARGET_ARM
&& TARGET_HARD_FLOAT
&& TARGET_MAVERICK
)
10625 /* A DImode comparison against zero can be implemented by
10626 or'ing the two halves together. */
10627 if (y
== const0_rtx
)
10630 /* We can do an equality test in three Thumb instructions. */
10640 /* DImode unsigned comparisons can be implemented by cmp +
10641 cmpeq without a scratch register. Not worth doing in
10652 /* DImode signed and unsigned comparisons can be implemented
10653 by cmp + sbcs with a scratch register, but that does not
10654 set the Z flag - we must reverse GT/LE/GTU/LEU. */
10655 gcc_assert (op
!= EQ
&& op
!= NE
);
10659 gcc_unreachable ();
10666 /* X and Y are two things to compare using CODE. Emit the compare insn and
10667 return the rtx for register 0 in the proper mode. FP means this is a
10668 floating point compare: I don't think that it is needed on the arm. */
10670 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
10672 enum machine_mode mode
;
10674 int dimode_comparison
= GET_MODE (x
) == DImode
|| GET_MODE (y
) == DImode
;
10676 /* We might have X as a constant, Y as a register because of the predicates
10677 used for cmpdi. If so, force X to a register here. */
10678 if (dimode_comparison
&& !REG_P (x
))
10679 x
= force_reg (DImode
, x
);
10681 mode
= SELECT_CC_MODE (code
, x
, y
);
10682 cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
10684 if (dimode_comparison
10685 && !(TARGET_HARD_FLOAT
&& TARGET_MAVERICK
)
10686 && mode
!= CC_CZmode
)
10690 /* To compare two non-zero values for equality, XOR them and
10691 then compare against zero. Not used for ARM mode; there
10692 CC_CZmode is cheaper. */
10693 if (mode
== CC_Zmode
&& y
!= const0_rtx
)
10695 x
= expand_binop (DImode
, xor_optab
, x
, y
, NULL_RTX
, 0, OPTAB_WIDEN
);
10698 /* A scratch register is required. */
10699 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (SImode
));
10700 set
= gen_rtx_SET (VOIDmode
, cc_reg
, gen_rtx_COMPARE (mode
, x
, y
));
10701 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
10704 emit_set_insn (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
));
10709 /* Generate a sequence of insns that will generate the correct return
10710 address mask depending on the physical architecture that the program
10713 arm_gen_return_addr_mask (void)
10715 rtx reg
= gen_reg_rtx (Pmode
);
10717 emit_insn (gen_return_addr_mask (reg
));
10722 arm_reload_in_hi (rtx
*operands
)
10724 rtx ref
= operands
[1];
10726 HOST_WIDE_INT offset
= 0;
10728 if (GET_CODE (ref
) == SUBREG
)
10730 offset
= SUBREG_BYTE (ref
);
10731 ref
= SUBREG_REG (ref
);
10734 if (GET_CODE (ref
) == REG
)
10736 /* We have a pseudo which has been spilt onto the stack; there
10737 are two cases here: the first where there is a simple
10738 stack-slot replacement and a second where the stack-slot is
10739 out of range, or is used as a subreg. */
10740 if (reg_equiv_mem (REGNO (ref
)))
10742 ref
= reg_equiv_mem (REGNO (ref
));
10743 base
= find_replacement (&XEXP (ref
, 0));
10746 /* The slot is out of range, or was dressed up in a SUBREG. */
10747 base
= reg_equiv_address (REGNO (ref
));
10750 base
= find_replacement (&XEXP (ref
, 0));
10752 /* Handle the case where the address is too complex to be offset by 1. */
10753 if (GET_CODE (base
) == MINUS
10754 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
10756 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
10758 emit_set_insn (base_plus
, base
);
10761 else if (GET_CODE (base
) == PLUS
)
10763 /* The addend must be CONST_INT, or we would have dealt with it above. */
10764 HOST_WIDE_INT hi
, lo
;
10766 offset
+= INTVAL (XEXP (base
, 1));
10767 base
= XEXP (base
, 0);
10769 /* Rework the address into a legal sequence of insns. */
10770 /* Valid range for lo is -4095 -> 4095 */
10773 : -((-offset
) & 0xfff));
10775 /* Corner case, if lo is the max offset then we would be out of range
10776 once we have added the additional 1 below, so bump the msb into the
10777 pre-loading insn(s). */
10781 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
10782 ^ (HOST_WIDE_INT
) 0x80000000)
10783 - (HOST_WIDE_INT
) 0x80000000);
10785 gcc_assert (hi
+ lo
== offset
);
10789 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
10791 /* Get the base address; addsi3 knows how to handle constants
10792 that require more than one insn. */
10793 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
10799 /* Operands[2] may overlap operands[0] (though it won't overlap
10800 operands[1]), that's why we asked for a DImode reg -- so we can
10801 use the bit that does not overlap. */
10802 if (REGNO (operands
[2]) == REGNO (operands
[0]))
10803 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
10805 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
10807 emit_insn (gen_zero_extendqisi2 (scratch
,
10808 gen_rtx_MEM (QImode
,
10809 plus_constant (base
,
10811 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
10812 gen_rtx_MEM (QImode
,
10813 plus_constant (base
,
10815 if (!BYTES_BIG_ENDIAN
)
10816 emit_set_insn (gen_rtx_SUBREG (SImode
, operands
[0], 0),
10817 gen_rtx_IOR (SImode
,
10820 gen_rtx_SUBREG (SImode
, operands
[0], 0),
10824 emit_set_insn (gen_rtx_SUBREG (SImode
, operands
[0], 0),
10825 gen_rtx_IOR (SImode
,
10826 gen_rtx_ASHIFT (SImode
, scratch
,
10828 gen_rtx_SUBREG (SImode
, operands
[0], 0)));
10831 /* Handle storing a half-word to memory during reload by synthesizing as two
10832 byte stores. Take care not to clobber the input values until after we
10833 have moved them somewhere safe. This code assumes that if the DImode
10834 scratch in operands[2] overlaps either the input value or output address
10835 in some way, then that value must die in this insn (we absolutely need
10836 two scratch registers for some corner cases). */
10838 arm_reload_out_hi (rtx
*operands
)
10840 rtx ref
= operands
[0];
10841 rtx outval
= operands
[1];
10843 HOST_WIDE_INT offset
= 0;
10845 if (GET_CODE (ref
) == SUBREG
)
10847 offset
= SUBREG_BYTE (ref
);
10848 ref
= SUBREG_REG (ref
);
10851 if (GET_CODE (ref
) == REG
)
10853 /* We have a pseudo which has been spilt onto the stack; there
10854 are two cases here: the first where there is a simple
10855 stack-slot replacement and a second where the stack-slot is
10856 out of range, or is used as a subreg. */
10857 if (reg_equiv_mem (REGNO (ref
)))
10859 ref
= reg_equiv_mem (REGNO (ref
));
10860 base
= find_replacement (&XEXP (ref
, 0));
10863 /* The slot is out of range, or was dressed up in a SUBREG. */
10864 base
= reg_equiv_address (REGNO (ref
));
10867 base
= find_replacement (&XEXP (ref
, 0));
10869 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
10871 /* Handle the case where the address is too complex to be offset by 1. */
10872 if (GET_CODE (base
) == MINUS
10873 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
10875 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
10877 /* Be careful not to destroy OUTVAL. */
10878 if (reg_overlap_mentioned_p (base_plus
, outval
))
10880 /* Updating base_plus might destroy outval, see if we can
10881 swap the scratch and base_plus. */
10882 if (!reg_overlap_mentioned_p (scratch
, outval
))
10885 scratch
= base_plus
;
10890 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
10892 /* Be conservative and copy OUTVAL into the scratch now,
10893 this should only be necessary if outval is a subreg
10894 of something larger than a word. */
10895 /* XXX Might this clobber base? I can't see how it can,
10896 since scratch is known to overlap with OUTVAL, and
10897 must be wider than a word. */
10898 emit_insn (gen_movhi (scratch_hi
, outval
));
10899 outval
= scratch_hi
;
10903 emit_set_insn (base_plus
, base
);
10906 else if (GET_CODE (base
) == PLUS
)
10908 /* The addend must be CONST_INT, or we would have dealt with it above. */
10909 HOST_WIDE_INT hi
, lo
;
10911 offset
+= INTVAL (XEXP (base
, 1));
10912 base
= XEXP (base
, 0);
10914 /* Rework the address into a legal sequence of insns. */
10915 /* Valid range for lo is -4095 -> 4095 */
10918 : -((-offset
) & 0xfff));
10920 /* Corner case, if lo is the max offset then we would be out of range
10921 once we have added the additional 1 below, so bump the msb into the
10922 pre-loading insn(s). */
10926 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
10927 ^ (HOST_WIDE_INT
) 0x80000000)
10928 - (HOST_WIDE_INT
) 0x80000000);
10930 gcc_assert (hi
+ lo
== offset
);
10934 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
10936 /* Be careful not to destroy OUTVAL. */
10937 if (reg_overlap_mentioned_p (base_plus
, outval
))
10939 /* Updating base_plus might destroy outval, see if we
10940 can swap the scratch and base_plus. */
10941 if (!reg_overlap_mentioned_p (scratch
, outval
))
10944 scratch
= base_plus
;
10949 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
10951 /* Be conservative and copy outval into scratch now,
10952 this should only be necessary if outval is a
10953 subreg of something larger than a word. */
10954 /* XXX Might this clobber base? I can't see how it
10955 can, since scratch is known to overlap with
10957 emit_insn (gen_movhi (scratch_hi
, outval
));
10958 outval
= scratch_hi
;
10962 /* Get the base address; addsi3 knows how to handle constants
10963 that require more than one insn. */
10964 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
10970 if (BYTES_BIG_ENDIAN
)
10972 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
10973 plus_constant (base
, offset
+ 1)),
10974 gen_lowpart (QImode
, outval
)));
10975 emit_insn (gen_lshrsi3 (scratch
,
10976 gen_rtx_SUBREG (SImode
, outval
, 0),
10978 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
10979 gen_lowpart (QImode
, scratch
)));
10983 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
10984 gen_lowpart (QImode
, outval
)));
10985 emit_insn (gen_lshrsi3 (scratch
,
10986 gen_rtx_SUBREG (SImode
, outval
, 0),
10988 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
10989 plus_constant (base
, offset
+ 1)),
10990 gen_lowpart (QImode
, scratch
)));
10994 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
10995 (padded to the size of a word) should be passed in a register. */
10998 arm_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
11000 if (TARGET_AAPCS_BASED
)
11001 return must_pass_in_stack_var_size (mode
, type
);
11003 return must_pass_in_stack_var_size_or_pad (mode
, type
);
11007 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
11008 Return true if an argument passed on the stack should be padded upwards,
11009 i.e. if the least-significant byte has useful data.
11010 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
11011 aggregate types are placed in the lowest memory address. */
11014 arm_pad_arg_upward (enum machine_mode mode
, const_tree type
)
11016 if (!TARGET_AAPCS_BASED
)
11017 return DEFAULT_FUNCTION_ARG_PADDING(mode
, type
) == upward
;
11019 if (type
&& BYTES_BIG_ENDIAN
&& INTEGRAL_TYPE_P (type
))
11026 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
11027 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
11028 byte of the register has useful data, and return the opposite if the
11029 most significant byte does.
11030 For AAPCS, small aggregates and small complex types are always padded
11034 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED
,
11035 tree type
, int first ATTRIBUTE_UNUSED
)
11037 if (TARGET_AAPCS_BASED
11038 && BYTES_BIG_ENDIAN
11039 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == COMPLEX_TYPE
)
11040 && int_size_in_bytes (type
) <= 4)
11043 /* Otherwise, use default padding. */
11044 return !BYTES_BIG_ENDIAN
;
11048 /* Print a symbolic form of X to the debug file, F. */
11050 arm_print_value (FILE *f
, rtx x
)
11052 switch (GET_CODE (x
))
11055 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
11059 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
11067 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
11069 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
11070 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
11078 fprintf (f
, "\"%s\"", XSTR (x
, 0));
11082 fprintf (f
, "`%s'", XSTR (x
, 0));
11086 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
11090 arm_print_value (f
, XEXP (x
, 0));
11094 arm_print_value (f
, XEXP (x
, 0));
11096 arm_print_value (f
, XEXP (x
, 1));
11104 fprintf (f
, "????");
11109 /* Routines for manipulation of the constant pool. */
11111 /* Arm instructions cannot load a large constant directly into a
11112 register; they have to come from a pc relative load. The constant
11113 must therefore be placed in the addressable range of the pc
11114 relative load. Depending on the precise pc relative load
11115 instruction the range is somewhere between 256 bytes and 4k. This
11116 means that we often have to dump a constant inside a function, and
11117 generate code to branch around it.
11119 It is important to minimize this, since the branches will slow
11120 things down and make the code larger.
11122 Normally we can hide the table after an existing unconditional
11123 branch so that there is no interruption of the flow, but in the
11124 worst case the code looks like this:
11142 We fix this by performing a scan after scheduling, which notices
11143 which instructions need to have their operands fetched from the
11144 constant table and builds the table.
11146 The algorithm starts by building a table of all the constants that
11147 need fixing up and all the natural barriers in the function (places
11148 where a constant table can be dropped without breaking the flow).
11149 For each fixup we note how far the pc-relative replacement will be
11150 able to reach and the offset of the instruction into the function.
11152 Having built the table we then group the fixes together to form
11153 tables that are as large as possible (subject to addressing
11154 constraints) and emit each table of constants after the last
11155 barrier that is within range of all the instructions in the group.
11156 If a group does not contain a barrier, then we forcibly create one
11157 by inserting a jump instruction into the flow. Once the table has
11158 been inserted, the insns are then modified to reference the
11159 relevant entry in the pool.
11161 Possible enhancements to the algorithm (not implemented) are:
11163 1) For some processors and object formats, there may be benefit in
11164 aligning the pools to the start of cache lines; this alignment
11165 would need to be taken into account when calculating addressability
11168 /* These typedefs are located at the start of this file, so that
11169 they can be used in the prototypes there. This comment is to
11170 remind readers of that fact so that the following structures
11171 can be understood more easily.
11173 typedef struct minipool_node Mnode;
11174 typedef struct minipool_fixup Mfix; */
11176 struct minipool_node
11178 /* Doubly linked chain of entries. */
11181 /* The maximum offset into the code that this entry can be placed. While
11182 pushing fixes for forward references, all entries are sorted in order
11183 of increasing max_address. */
11184 HOST_WIDE_INT max_address
;
11185 /* Similarly for an entry inserted for a backwards ref. */
11186 HOST_WIDE_INT min_address
;
11187 /* The number of fixes referencing this entry. This can become zero
11188 if we "unpush" an entry. In this case we ignore the entry when we
11189 come to emit the code. */
11191 /* The offset from the start of the minipool. */
11192 HOST_WIDE_INT offset
;
11193 /* The value in table. */
11195 /* The mode of value. */
11196 enum machine_mode mode
;
11197 /* The size of the value. With iWMMXt enabled
11198 sizes > 4 also imply an alignment of 8-bytes. */
11202 struct minipool_fixup
11206 HOST_WIDE_INT address
;
11208 enum machine_mode mode
;
11212 HOST_WIDE_INT forwards
;
11213 HOST_WIDE_INT backwards
;
11216 /* Fixes less than a word need padding out to a word boundary. */
11217 #define MINIPOOL_FIX_SIZE(mode) \
11218 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
11220 static Mnode
* minipool_vector_head
;
11221 static Mnode
* minipool_vector_tail
;
11222 static rtx minipool_vector_label
;
11223 static int minipool_pad
;
11225 /* The linked list of all minipool fixes required for this function. */
11226 Mfix
* minipool_fix_head
;
11227 Mfix
* minipool_fix_tail
;
11228 /* The fix entry for the current minipool, once it has been placed. */
11229 Mfix
* minipool_barrier
;
11231 /* Determines if INSN is the start of a jump table. Returns the end
11232 of the TABLE or NULL_RTX. */
11234 is_jump_table (rtx insn
)
11238 if (GET_CODE (insn
) == JUMP_INSN
11239 && JUMP_LABEL (insn
) != NULL
11240 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
11241 == next_real_insn (insn
))
11243 && GET_CODE (table
) == JUMP_INSN
11244 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
11245 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
11251 #ifndef JUMP_TABLES_IN_TEXT_SECTION
11252 #define JUMP_TABLES_IN_TEXT_SECTION 0
11255 static HOST_WIDE_INT
11256 get_jump_table_size (rtx insn
)
11258 /* ADDR_VECs only take room if read-only data does into the text
11260 if (JUMP_TABLES_IN_TEXT_SECTION
|| readonly_data_section
== text_section
)
11262 rtx body
= PATTERN (insn
);
11263 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
11264 HOST_WIDE_INT size
;
11265 HOST_WIDE_INT modesize
;
11267 modesize
= GET_MODE_SIZE (GET_MODE (body
));
11268 size
= modesize
* XVECLEN (body
, elt
);
11272 /* Round up size of TBB table to a halfword boundary. */
11273 size
= (size
+ 1) & ~(HOST_WIDE_INT
)1;
11276 /* No padding necessary for TBH. */
11279 /* Add two bytes for alignment on Thumb. */
11284 gcc_unreachable ();
11292 /* Move a minipool fix MP from its current location to before MAX_MP.
11293 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
11294 constraints may need updating. */
11296 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
11297 HOST_WIDE_INT max_address
)
11299 /* The code below assumes these are different. */
11300 gcc_assert (mp
!= max_mp
);
11302 if (max_mp
== NULL
)
11304 if (max_address
< mp
->max_address
)
11305 mp
->max_address
= max_address
;
11309 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
11310 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
11312 mp
->max_address
= max_address
;
11314 /* Unlink MP from its current position. Since max_mp is non-null,
11315 mp->prev must be non-null. */
11316 mp
->prev
->next
= mp
->next
;
11317 if (mp
->next
!= NULL
)
11318 mp
->next
->prev
= mp
->prev
;
11320 minipool_vector_tail
= mp
->prev
;
11322 /* Re-insert it before MAX_MP. */
11324 mp
->prev
= max_mp
->prev
;
11327 if (mp
->prev
!= NULL
)
11328 mp
->prev
->next
= mp
;
11330 minipool_vector_head
= mp
;
11333 /* Save the new entry. */
11336 /* Scan over the preceding entries and adjust their addresses as
11338 while (mp
->prev
!= NULL
11339 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
11341 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
11348 /* Add a constant to the minipool for a forward reference. Returns the
11349 node added or NULL if the constant will not fit in this pool. */
11351 add_minipool_forward_ref (Mfix
*fix
)
11353 /* If set, max_mp is the first pool_entry that has a lower
11354 constraint than the one we are trying to add. */
11355 Mnode
* max_mp
= NULL
;
11356 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
- minipool_pad
;
11359 /* If the minipool starts before the end of FIX->INSN then this FIX
11360 can not be placed into the current pool. Furthermore, adding the
11361 new constant pool entry may cause the pool to start FIX_SIZE bytes
11363 if (minipool_vector_head
&&
11364 (fix
->address
+ get_attr_length (fix
->insn
)
11365 >= minipool_vector_head
->max_address
- fix
->fix_size
))
11368 /* Scan the pool to see if a constant with the same value has
11369 already been added. While we are doing this, also note the
11370 location where we must insert the constant if it doesn't already
11372 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
11374 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
11375 && fix
->mode
== mp
->mode
11376 && (GET_CODE (fix
->value
) != CODE_LABEL
11377 || (CODE_LABEL_NUMBER (fix
->value
)
11378 == CODE_LABEL_NUMBER (mp
->value
)))
11379 && rtx_equal_p (fix
->value
, mp
->value
))
11381 /* More than one fix references this entry. */
11383 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
11386 /* Note the insertion point if necessary. */
11388 && mp
->max_address
> max_address
)
11391 /* If we are inserting an 8-bytes aligned quantity and
11392 we have not already found an insertion point, then
11393 make sure that all such 8-byte aligned quantities are
11394 placed at the start of the pool. */
11395 if (ARM_DOUBLEWORD_ALIGN
11397 && fix
->fix_size
>= 8
11398 && mp
->fix_size
< 8)
11401 max_address
= mp
->max_address
;
11405 /* The value is not currently in the minipool, so we need to create
11406 a new entry for it. If MAX_MP is NULL, the entry will be put on
11407 the end of the list since the placement is less constrained than
11408 any existing entry. Otherwise, we insert the new fix before
11409 MAX_MP and, if necessary, adjust the constraints on the other
11412 mp
->fix_size
= fix
->fix_size
;
11413 mp
->mode
= fix
->mode
;
11414 mp
->value
= fix
->value
;
11416 /* Not yet required for a backwards ref. */
11417 mp
->min_address
= -65536;
11419 if (max_mp
== NULL
)
11421 mp
->max_address
= max_address
;
11423 mp
->prev
= minipool_vector_tail
;
11425 if (mp
->prev
== NULL
)
11427 minipool_vector_head
= mp
;
11428 minipool_vector_label
= gen_label_rtx ();
11431 mp
->prev
->next
= mp
;
11433 minipool_vector_tail
= mp
;
11437 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
11438 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
11440 mp
->max_address
= max_address
;
11443 mp
->prev
= max_mp
->prev
;
11445 if (mp
->prev
!= NULL
)
11446 mp
->prev
->next
= mp
;
11448 minipool_vector_head
= mp
;
11451 /* Save the new entry. */
11454 /* Scan over the preceding entries and adjust their addresses as
11456 while (mp
->prev
!= NULL
11457 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
11459 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
11467 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
11468 HOST_WIDE_INT min_address
)
11470 HOST_WIDE_INT offset
;
11472 /* The code below assumes these are different. */
11473 gcc_assert (mp
!= min_mp
);
11475 if (min_mp
== NULL
)
11477 if (min_address
> mp
->min_address
)
11478 mp
->min_address
= min_address
;
11482 /* We will adjust this below if it is too loose. */
11483 mp
->min_address
= min_address
;
11485 /* Unlink MP from its current position. Since min_mp is non-null,
11486 mp->next must be non-null. */
11487 mp
->next
->prev
= mp
->prev
;
11488 if (mp
->prev
!= NULL
)
11489 mp
->prev
->next
= mp
->next
;
11491 minipool_vector_head
= mp
->next
;
11493 /* Reinsert it after MIN_MP. */
11495 mp
->next
= min_mp
->next
;
11497 if (mp
->next
!= NULL
)
11498 mp
->next
->prev
= mp
;
11500 minipool_vector_tail
= mp
;
11506 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
11508 mp
->offset
= offset
;
11509 if (mp
->refcount
> 0)
11510 offset
+= mp
->fix_size
;
11512 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
11513 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
11519 /* Add a constant to the minipool for a backward reference. Returns the
11520 node added or NULL if the constant will not fit in this pool.
11522 Note that the code for insertion for a backwards reference can be
11523 somewhat confusing because the calculated offsets for each fix do
11524 not take into account the size of the pool (which is still under
11527 add_minipool_backward_ref (Mfix
*fix
)
11529 /* If set, min_mp is the last pool_entry that has a lower constraint
11530 than the one we are trying to add. */
11531 Mnode
*min_mp
= NULL
;
11532 /* This can be negative, since it is only a constraint. */
11533 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
11536 /* If we can't reach the current pool from this insn, or if we can't
11537 insert this entry at the end of the pool without pushing other
11538 fixes out of range, then we don't try. This ensures that we
11539 can't fail later on. */
11540 if (min_address
>= minipool_barrier
->address
11541 || (minipool_vector_tail
->min_address
+ fix
->fix_size
11542 >= minipool_barrier
->address
))
11545 /* Scan the pool to see if a constant with the same value has
11546 already been added. While we are doing this, also note the
11547 location where we must insert the constant if it doesn't already
11549 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
11551 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
11552 && fix
->mode
== mp
->mode
11553 && (GET_CODE (fix
->value
) != CODE_LABEL
11554 || (CODE_LABEL_NUMBER (fix
->value
)
11555 == CODE_LABEL_NUMBER (mp
->value
)))
11556 && rtx_equal_p (fix
->value
, mp
->value
)
11557 /* Check that there is enough slack to move this entry to the
11558 end of the table (this is conservative). */
11559 && (mp
->max_address
11560 > (minipool_barrier
->address
11561 + minipool_vector_tail
->offset
11562 + minipool_vector_tail
->fix_size
)))
11565 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
11568 if (min_mp
!= NULL
)
11569 mp
->min_address
+= fix
->fix_size
;
11572 /* Note the insertion point if necessary. */
11573 if (mp
->min_address
< min_address
)
11575 /* For now, we do not allow the insertion of 8-byte alignment
11576 requiring nodes anywhere but at the start of the pool. */
11577 if (ARM_DOUBLEWORD_ALIGN
11578 && fix
->fix_size
>= 8 && mp
->fix_size
< 8)
11583 else if (mp
->max_address
11584 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
11586 /* Inserting before this entry would push the fix beyond
11587 its maximum address (which can happen if we have
11588 re-located a forwards fix); force the new fix to come
11590 if (ARM_DOUBLEWORD_ALIGN
11591 && fix
->fix_size
>= 8 && mp
->fix_size
< 8)
11596 min_address
= mp
->min_address
+ fix
->fix_size
;
11599 /* Do not insert a non-8-byte aligned quantity before 8-byte
11600 aligned quantities. */
11601 else if (ARM_DOUBLEWORD_ALIGN
11602 && fix
->fix_size
< 8
11603 && mp
->fix_size
>= 8)
11606 min_address
= mp
->min_address
+ fix
->fix_size
;
11611 /* We need to create a new entry. */
11613 mp
->fix_size
= fix
->fix_size
;
11614 mp
->mode
= fix
->mode
;
11615 mp
->value
= fix
->value
;
11617 mp
->max_address
= minipool_barrier
->address
+ 65536;
11619 mp
->min_address
= min_address
;
11621 if (min_mp
== NULL
)
11624 mp
->next
= minipool_vector_head
;
11626 if (mp
->next
== NULL
)
11628 minipool_vector_tail
= mp
;
11629 minipool_vector_label
= gen_label_rtx ();
11632 mp
->next
->prev
= mp
;
11634 minipool_vector_head
= mp
;
11638 mp
->next
= min_mp
->next
;
11642 if (mp
->next
!= NULL
)
11643 mp
->next
->prev
= mp
;
11645 minipool_vector_tail
= mp
;
11648 /* Save the new entry. */
11656 /* Scan over the following entries and adjust their offsets. */
11657 while (mp
->next
!= NULL
)
11659 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
11660 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
11663 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
11665 mp
->next
->offset
= mp
->offset
;
11674 assign_minipool_offsets (Mfix
*barrier
)
11676 HOST_WIDE_INT offset
= 0;
11679 minipool_barrier
= barrier
;
11681 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
11683 mp
->offset
= offset
;
11685 if (mp
->refcount
> 0)
11686 offset
+= mp
->fix_size
;
11690 /* Output the literal table */
11692 dump_minipool (rtx scan
)
11698 if (ARM_DOUBLEWORD_ALIGN
)
11699 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
11700 if (mp
->refcount
> 0 && mp
->fix_size
>= 8)
11707 fprintf (dump_file
,
11708 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
11709 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
11711 scan
= emit_label_after (gen_label_rtx (), scan
);
11712 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
11713 scan
= emit_label_after (minipool_vector_label
, scan
);
11715 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
11717 if (mp
->refcount
> 0)
11721 fprintf (dump_file
,
11722 ";; Offset %u, min %ld, max %ld ",
11723 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
11724 (unsigned long) mp
->max_address
);
11725 arm_print_value (dump_file
, mp
->value
);
11726 fputc ('\n', dump_file
);
11729 switch (mp
->fix_size
)
11731 #ifdef HAVE_consttable_1
11733 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
11737 #ifdef HAVE_consttable_2
11739 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
11743 #ifdef HAVE_consttable_4
11745 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
11749 #ifdef HAVE_consttable_8
11751 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
11755 #ifdef HAVE_consttable_16
11757 scan
= emit_insn_after (gen_consttable_16 (mp
->value
), scan
);
11762 gcc_unreachable ();
11770 minipool_vector_head
= minipool_vector_tail
= NULL
;
11771 scan
= emit_insn_after (gen_consttable_end (), scan
);
11772 scan
= emit_barrier_after (scan
);
11775 /* Return the cost of forcibly inserting a barrier after INSN. */
11777 arm_barrier_cost (rtx insn
)
11779 /* Basing the location of the pool on the loop depth is preferable,
11780 but at the moment, the basic block information seems to be
11781 corrupt by this stage of the compilation. */
11782 int base_cost
= 50;
11783 rtx next
= next_nonnote_insn (insn
);
11785 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
11788 switch (GET_CODE (insn
))
11791 /* It will always be better to place the table before the label, rather
11800 return base_cost
- 10;
11803 return base_cost
+ 10;
11807 /* Find the best place in the insn stream in the range
11808 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
11809 Create the barrier by inserting a jump and add a new fix entry for
11812 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
11814 HOST_WIDE_INT count
= 0;
11816 rtx from
= fix
->insn
;
11817 /* The instruction after which we will insert the jump. */
11818 rtx selected
= NULL
;
11820 /* The address at which the jump instruction will be placed. */
11821 HOST_WIDE_INT selected_address
;
11823 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
11824 rtx label
= gen_label_rtx ();
11826 selected_cost
= arm_barrier_cost (from
);
11827 selected_address
= fix
->address
;
11829 while (from
&& count
< max_count
)
11834 /* This code shouldn't have been called if there was a natural barrier
11836 gcc_assert (GET_CODE (from
) != BARRIER
);
11838 /* Count the length of this insn. */
11839 count
+= get_attr_length (from
);
11841 /* If there is a jump table, add its length. */
11842 tmp
= is_jump_table (from
);
11845 count
+= get_jump_table_size (tmp
);
11847 /* Jump tables aren't in a basic block, so base the cost on
11848 the dispatch insn. If we select this location, we will
11849 still put the pool after the table. */
11850 new_cost
= arm_barrier_cost (from
);
11852 if (count
< max_count
11853 && (!selected
|| new_cost
<= selected_cost
))
11856 selected_cost
= new_cost
;
11857 selected_address
= fix
->address
+ count
;
11860 /* Continue after the dispatch table. */
11861 from
= NEXT_INSN (tmp
);
11865 new_cost
= arm_barrier_cost (from
);
11867 if (count
< max_count
11868 && (!selected
|| new_cost
<= selected_cost
))
11871 selected_cost
= new_cost
;
11872 selected_address
= fix
->address
+ count
;
11875 from
= NEXT_INSN (from
);
11878 /* Make sure that we found a place to insert the jump. */
11879 gcc_assert (selected
);
11881 /* Make sure we do not split a call and its corresponding
11882 CALL_ARG_LOCATION note. */
11883 if (CALL_P (selected
))
11885 rtx next
= NEXT_INSN (selected
);
11886 if (next
&& NOTE_P (next
)
11887 && NOTE_KIND (next
) == NOTE_INSN_CALL_ARG_LOCATION
)
11891 /* Create a new JUMP_INSN that branches around a barrier. */
11892 from
= emit_jump_insn_after (gen_jump (label
), selected
);
11893 JUMP_LABEL (from
) = label
;
11894 barrier
= emit_barrier_after (from
);
11895 emit_label_after (label
, barrier
);
11897 /* Create a minipool barrier entry for the new barrier. */
11898 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
11899 new_fix
->insn
= barrier
;
11900 new_fix
->address
= selected_address
;
11901 new_fix
->next
= fix
->next
;
11902 fix
->next
= new_fix
;
11907 /* Record that there is a natural barrier in the insn stream at
11910 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
11912 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
11915 fix
->address
= address
;
11918 if (minipool_fix_head
!= NULL
)
11919 minipool_fix_tail
->next
= fix
;
11921 minipool_fix_head
= fix
;
11923 minipool_fix_tail
= fix
;
11926 /* Record INSN, which will need fixing up to load a value from the
11927 minipool. ADDRESS is the offset of the insn since the start of the
11928 function; LOC is a pointer to the part of the insn which requires
11929 fixing; VALUE is the constant that must be loaded, which is of type
11932 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
11933 enum machine_mode mode
, rtx value
)
11935 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
11938 fix
->address
= address
;
11941 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
11942 fix
->value
= value
;
11943 fix
->forwards
= get_attr_pool_range (insn
);
11944 fix
->backwards
= get_attr_neg_pool_range (insn
);
11945 fix
->minipool
= NULL
;
11947 /* If an insn doesn't have a range defined for it, then it isn't
11948 expecting to be reworked by this code. Better to stop now than
11949 to generate duff assembly code. */
11950 gcc_assert (fix
->forwards
|| fix
->backwards
);
11952 /* If an entry requires 8-byte alignment then assume all constant pools
11953 require 4 bytes of padding. Trying to do this later on a per-pool
11954 basis is awkward because existing pool entries have to be modified. */
11955 if (ARM_DOUBLEWORD_ALIGN
&& fix
->fix_size
>= 8)
11960 fprintf (dump_file
,
11961 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
11962 GET_MODE_NAME (mode
),
11963 INSN_UID (insn
), (unsigned long) address
,
11964 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
11965 arm_print_value (dump_file
, fix
->value
);
11966 fprintf (dump_file
, "\n");
11969 /* Add it to the chain of fixes. */
11972 if (minipool_fix_head
!= NULL
)
11973 minipool_fix_tail
->next
= fix
;
11975 minipool_fix_head
= fix
;
11977 minipool_fix_tail
= fix
;
11980 /* Return the cost of synthesizing a 64-bit constant VAL inline.
11981 Returns the number of insns needed, or 99 if we don't know how to
11984 arm_const_double_inline_cost (rtx val
)
11986 rtx lowpart
, highpart
;
11987 enum machine_mode mode
;
11989 mode
= GET_MODE (val
);
11991 if (mode
== VOIDmode
)
11994 gcc_assert (GET_MODE_SIZE (mode
) == 8);
11996 lowpart
= gen_lowpart (SImode
, val
);
11997 highpart
= gen_highpart_mode (SImode
, mode
, val
);
11999 gcc_assert (GET_CODE (lowpart
) == CONST_INT
);
12000 gcc_assert (GET_CODE (highpart
) == CONST_INT
);
12002 return (arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (lowpart
),
12003 NULL_RTX
, NULL_RTX
, 0, 0)
12004 + arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (highpart
),
12005 NULL_RTX
, NULL_RTX
, 0, 0));
12008 /* Return true if it is worthwhile to split a 64-bit constant into two
12009 32-bit operations. This is the case if optimizing for size, or
12010 if we have load delay slots, or if one 32-bit part can be done with
12011 a single data operation. */
12013 arm_const_double_by_parts (rtx val
)
12015 enum machine_mode mode
= GET_MODE (val
);
12018 if (optimize_size
|| arm_ld_sched
)
12021 if (mode
== VOIDmode
)
12024 part
= gen_highpart_mode (SImode
, mode
, val
);
12026 gcc_assert (GET_CODE (part
) == CONST_INT
);
12028 if (const_ok_for_arm (INTVAL (part
))
12029 || const_ok_for_arm (~INTVAL (part
)))
12032 part
= gen_lowpart (SImode
, val
);
12034 gcc_assert (GET_CODE (part
) == CONST_INT
);
12036 if (const_ok_for_arm (INTVAL (part
))
12037 || const_ok_for_arm (~INTVAL (part
)))
12043 /* Return true if it is possible to inline both the high and low parts
12044 of a 64-bit constant into 32-bit data processing instructions. */
12046 arm_const_double_by_immediates (rtx val
)
12048 enum machine_mode mode
= GET_MODE (val
);
12051 if (mode
== VOIDmode
)
12054 part
= gen_highpart_mode (SImode
, mode
, val
);
12056 gcc_assert (GET_CODE (part
) == CONST_INT
);
12058 if (!const_ok_for_arm (INTVAL (part
)))
12061 part
= gen_lowpart (SImode
, val
);
12063 gcc_assert (GET_CODE (part
) == CONST_INT
);
12065 if (!const_ok_for_arm (INTVAL (part
)))
12071 /* Scan INSN and note any of its operands that need fixing.
12072 If DO_PUSHES is false we do not actually push any of the fixups
12073 needed. The function returns TRUE if any fixups were needed/pushed.
12074 This is used by arm_memory_load_p() which needs to know about loads
12075 of constants that will be converted into minipool loads. */
12077 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
12079 bool result
= false;
12082 extract_insn (insn
);
12084 if (!constrain_operands (1))
12085 fatal_insn_not_found (insn
);
12087 if (recog_data
.n_alternatives
== 0)
12090 /* Fill in recog_op_alt with information about the constraints of
12092 preprocess_constraints ();
12094 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
12096 /* Things we need to fix can only occur in inputs. */
12097 if (recog_data
.operand_type
[opno
] != OP_IN
)
12100 /* If this alternative is a memory reference, then any mention
12101 of constants in this alternative is really to fool reload
12102 into allowing us to accept one there. We need to fix them up
12103 now so that we output the right code. */
12104 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
12106 rtx op
= recog_data
.operand
[opno
];
12108 if (CONSTANT_P (op
))
12111 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
12112 recog_data
.operand_mode
[opno
], op
);
12115 else if (GET_CODE (op
) == MEM
12116 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
12117 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
12121 rtx cop
= avoid_constant_pool_reference (op
);
12123 /* Casting the address of something to a mode narrower
12124 than a word can cause avoid_constant_pool_reference()
12125 to return the pool reference itself. That's no good to
12126 us here. Lets just hope that we can use the
12127 constant pool value directly. */
12129 cop
= get_pool_constant (XEXP (op
, 0));
12131 push_minipool_fix (insn
, address
,
12132 recog_data
.operand_loc
[opno
],
12133 recog_data
.operand_mode
[opno
], cop
);
12144 /* Convert instructions to their cc-clobbering variant if possible, since
12145 that allows us to use smaller encodings. */
12148 thumb2_reorg (void)
12153 INIT_REG_SET (&live
);
12155 /* We are freeing block_for_insn in the toplev to keep compatibility
12156 with old MDEP_REORGS that are not CFG based. Recompute it now. */
12157 compute_bb_for_insn ();
12164 COPY_REG_SET (&live
, DF_LR_OUT (bb
));
12165 df_simulate_initialize_backwards (bb
, &live
);
12166 FOR_BB_INSNS_REVERSE (bb
, insn
)
12168 if (NONJUMP_INSN_P (insn
)
12169 && !REGNO_REG_SET_P (&live
, CC_REGNUM
))
12171 rtx pat
= PATTERN (insn
);
12172 if (GET_CODE (pat
) == SET
12173 && low_register_operand (XEXP (pat
, 0), SImode
)
12174 && thumb_16bit_operator (XEXP (pat
, 1), SImode
)
12175 && low_register_operand (XEXP (XEXP (pat
, 1), 0), SImode
)
12176 && low_register_operand (XEXP (XEXP (pat
, 1), 1), SImode
))
12178 rtx dst
= XEXP (pat
, 0);
12179 rtx src
= XEXP (pat
, 1);
12180 rtx op0
= XEXP (src
, 0);
12181 rtx op1
= (GET_RTX_CLASS (GET_CODE (src
)) == RTX_COMM_ARITH
12182 ? XEXP (src
, 1) : NULL
);
12184 if (rtx_equal_p (dst
, op0
)
12185 || GET_CODE (src
) == PLUS
|| GET_CODE (src
) == MINUS
)
12187 rtx ccreg
= gen_rtx_REG (CCmode
, CC_REGNUM
);
12188 rtx clobber
= gen_rtx_CLOBBER (VOIDmode
, ccreg
);
12189 rtvec vec
= gen_rtvec (2, pat
, clobber
);
12191 PATTERN (insn
) = gen_rtx_PARALLEL (VOIDmode
, vec
);
12192 INSN_CODE (insn
) = -1;
12194 /* We can also handle a commutative operation where the
12195 second operand matches the destination. */
12196 else if (op1
&& rtx_equal_p (dst
, op1
))
12198 rtx ccreg
= gen_rtx_REG (CCmode
, CC_REGNUM
);
12199 rtx clobber
= gen_rtx_CLOBBER (VOIDmode
, ccreg
);
12202 src
= copy_rtx (src
);
12203 XEXP (src
, 0) = op1
;
12204 XEXP (src
, 1) = op0
;
12205 pat
= gen_rtx_SET (VOIDmode
, dst
, src
);
12206 vec
= gen_rtvec (2, pat
, clobber
);
12207 PATTERN (insn
) = gen_rtx_PARALLEL (VOIDmode
, vec
);
12208 INSN_CODE (insn
) = -1;
12213 if (NONDEBUG_INSN_P (insn
))
12214 df_simulate_one_insn_backwards (bb
, insn
, &live
);
12218 CLEAR_REG_SET (&live
);
12221 /* Gcc puts the pool in the wrong place for ARM, since we can only
12222 load addresses a limited distance around the pc. We do some
12223 special munging to move the constant pool values to the correct
12224 point in the code. */
12229 HOST_WIDE_INT address
= 0;
12235 minipool_fix_head
= minipool_fix_tail
= NULL
;
12237 /* The first insn must always be a note, or the code below won't
12238 scan it properly. */
12239 insn
= get_insns ();
12240 gcc_assert (GET_CODE (insn
) == NOTE
);
12243 /* Scan all the insns and record the operands that will need fixing. */
12244 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
12246 if (TARGET_CIRRUS_FIX_INVALID_INSNS
12247 && (arm_cirrus_insn_p (insn
)
12248 || GET_CODE (insn
) == JUMP_INSN
12249 || arm_memory_load_p (insn
)))
12250 cirrus_reorg (insn
);
12252 if (GET_CODE (insn
) == BARRIER
)
12253 push_minipool_barrier (insn
, address
);
12254 else if (INSN_P (insn
))
12258 note_invalid_constants (insn
, address
, true);
12259 address
+= get_attr_length (insn
);
12261 /* If the insn is a vector jump, add the size of the table
12262 and skip the table. */
12263 if ((table
= is_jump_table (insn
)) != NULL
)
12265 address
+= get_jump_table_size (table
);
12271 fix
= minipool_fix_head
;
12273 /* Now scan the fixups and perform the required changes. */
12278 Mfix
* last_added_fix
;
12279 Mfix
* last_barrier
= NULL
;
12282 /* Skip any further barriers before the next fix. */
12283 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
12286 /* No more fixes. */
12290 last_added_fix
= NULL
;
12292 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
12294 if (GET_CODE (ftmp
->insn
) == BARRIER
)
12296 if (ftmp
->address
>= minipool_vector_head
->max_address
)
12299 last_barrier
= ftmp
;
12301 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
12304 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
12307 /* If we found a barrier, drop back to that; any fixes that we
12308 could have reached but come after the barrier will now go in
12309 the next mini-pool. */
12310 if (last_barrier
!= NULL
)
12312 /* Reduce the refcount for those fixes that won't go into this
12314 for (fdel
= last_barrier
->next
;
12315 fdel
&& fdel
!= ftmp
;
12318 fdel
->minipool
->refcount
--;
12319 fdel
->minipool
= NULL
;
12322 ftmp
= last_barrier
;
12326 /* ftmp is first fix that we can't fit into this pool and
12327 there no natural barriers that we could use. Insert a
12328 new barrier in the code somewhere between the previous
12329 fix and this one, and arrange to jump around it. */
12330 HOST_WIDE_INT max_address
;
12332 /* The last item on the list of fixes must be a barrier, so
12333 we can never run off the end of the list of fixes without
12334 last_barrier being set. */
12337 max_address
= minipool_vector_head
->max_address
;
12338 /* Check that there isn't another fix that is in range that
12339 we couldn't fit into this pool because the pool was
12340 already too large: we need to put the pool before such an
12341 instruction. The pool itself may come just after the
12342 fix because create_fix_barrier also allows space for a
12343 jump instruction. */
12344 if (ftmp
->address
< max_address
)
12345 max_address
= ftmp
->address
+ 1;
12347 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
12350 assign_minipool_offsets (last_barrier
);
12354 if (GET_CODE (ftmp
->insn
) != BARRIER
12355 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
12362 /* Scan over the fixes we have identified for this pool, fixing them
12363 up and adding the constants to the pool itself. */
12364 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
12365 this_fix
= this_fix
->next
)
12366 if (GET_CODE (this_fix
->insn
) != BARRIER
)
12369 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
12370 minipool_vector_label
),
12371 this_fix
->minipool
->offset
);
12372 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
12375 dump_minipool (last_barrier
->insn
);
12379 /* From now on we must synthesize any constants that we can't handle
12380 directly. This can happen if the RTL gets split during final
12381 instruction generation. */
12382 after_arm_reorg
= 1;
12384 /* Free the minipool memory. */
12385 obstack_free (&minipool_obstack
, minipool_startobj
);
12388 /* Routines to output assembly language. */
12390 /* If the rtx is the correct value then return the string of the number.
12391 In this way we can ensure that valid double constants are generated even
12392 when cross compiling. */
12394 fp_immediate_constant (rtx x
)
12399 if (!fp_consts_inited
)
12402 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
12403 for (i
= 0; i
< 8; i
++)
12404 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
12405 return strings_fp
[i
];
12407 gcc_unreachable ();
12410 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
12411 static const char *
12412 fp_const_from_val (REAL_VALUE_TYPE
*r
)
12416 if (!fp_consts_inited
)
12419 for (i
= 0; i
< 8; i
++)
12420 if (REAL_VALUES_EQUAL (*r
, values_fp
[i
]))
12421 return strings_fp
[i
];
12423 gcc_unreachable ();
12426 /* Output the operands of a LDM/STM instruction to STREAM.
12427 MASK is the ARM register set mask of which only bits 0-15 are important.
12428 REG is the base register, either the frame pointer or the stack pointer,
12429 INSTR is the possibly suffixed load or store instruction.
12430 RFE is nonzero if the instruction should also copy spsr to cpsr. */
12433 print_multi_reg (FILE *stream
, const char *instr
, unsigned reg
,
12434 unsigned long mask
, int rfe
)
12437 bool not_first
= FALSE
;
12439 gcc_assert (!rfe
|| (mask
& (1 << PC_REGNUM
)));
12440 fputc ('\t', stream
);
12441 asm_fprintf (stream
, instr
, reg
);
12442 fputc ('{', stream
);
12444 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
12445 if (mask
& (1 << i
))
12448 fprintf (stream
, ", ");
12450 asm_fprintf (stream
, "%r", i
);
12455 fprintf (stream
, "}^\n");
12457 fprintf (stream
, "}\n");
12461 /* Output a FLDMD instruction to STREAM.
12462 BASE if the register containing the address.
12463 REG and COUNT specify the register range.
12464 Extra registers may be added to avoid hardware bugs.
12466 We output FLDMD even for ARMv5 VFP implementations. Although
12467 FLDMD is technically not supported until ARMv6, it is believed
12468 that all VFP implementations support its use in this context. */
12471 vfp_output_fldmd (FILE * stream
, unsigned int base
, int reg
, int count
)
12475 /* Workaround ARM10 VFPr1 bug. */
12476 if (count
== 2 && !arm_arch6
)
12483 /* FLDMD may not load more than 16 doubleword registers at a time. Split the
12484 load into multiple parts if we have to handle more than 16 registers. */
12487 vfp_output_fldmd (stream
, base
, reg
, 16);
12488 vfp_output_fldmd (stream
, base
, reg
+ 16, count
- 16);
12492 fputc ('\t', stream
);
12493 asm_fprintf (stream
, "fldmfdd\t%r!, {", base
);
12495 for (i
= reg
; i
< reg
+ count
; i
++)
12498 fputs (", ", stream
);
12499 asm_fprintf (stream
, "d%d", i
);
12501 fputs ("}\n", stream
);
12506 /* Output the assembly for a store multiple. */
12509 vfp_output_fstmd (rtx
* operands
)
12516 strcpy (pattern
, "fstmfdd\t%m0!, {%P1");
12517 p
= strlen (pattern
);
12519 gcc_assert (GET_CODE (operands
[1]) == REG
);
12521 base
= (REGNO (operands
[1]) - FIRST_VFP_REGNUM
) / 2;
12522 for (i
= 1; i
< XVECLEN (operands
[2], 0); i
++)
12524 p
+= sprintf (&pattern
[p
], ", d%d", base
+ i
);
12526 strcpy (&pattern
[p
], "}");
12528 output_asm_insn (pattern
, operands
);
12533 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
12534 number of bytes pushed. */
12537 vfp_emit_fstmd (int base_reg
, int count
)
12544 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
12545 register pairs are stored by a store multiple insn. We avoid this
12546 by pushing an extra pair. */
12547 if (count
== 2 && !arm_arch6
)
12549 if (base_reg
== LAST_VFP_REGNUM
- 3)
12554 /* FSTMD may not store more than 16 doubleword registers at once. Split
12555 larger stores into multiple parts (up to a maximum of two, in
12560 /* NOTE: base_reg is an internal register number, so each D register
12562 saved
= vfp_emit_fstmd (base_reg
+ 32, count
- 16);
12563 saved
+= vfp_emit_fstmd (base_reg
, 16);
12567 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
12568 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
12570 reg
= gen_rtx_REG (DFmode
, base_reg
);
12573 XVECEXP (par
, 0, 0)
12574 = gen_rtx_SET (VOIDmode
,
12577 gen_rtx_PRE_MODIFY (Pmode
,
12580 (stack_pointer_rtx
,
12583 gen_rtx_UNSPEC (BLKmode
,
12584 gen_rtvec (1, reg
),
12585 UNSPEC_PUSH_MULT
));
12587 tmp
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
12588 plus_constant (stack_pointer_rtx
, -(count
* 8)));
12589 RTX_FRAME_RELATED_P (tmp
) = 1;
12590 XVECEXP (dwarf
, 0, 0) = tmp
;
12592 tmp
= gen_rtx_SET (VOIDmode
,
12593 gen_frame_mem (DFmode
, stack_pointer_rtx
),
12595 RTX_FRAME_RELATED_P (tmp
) = 1;
12596 XVECEXP (dwarf
, 0, 1) = tmp
;
12598 for (i
= 1; i
< count
; i
++)
12600 reg
= gen_rtx_REG (DFmode
, base_reg
);
12602 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
12604 tmp
= gen_rtx_SET (VOIDmode
,
12605 gen_frame_mem (DFmode
,
12606 plus_constant (stack_pointer_rtx
,
12609 RTX_FRAME_RELATED_P (tmp
) = 1;
12610 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
12613 par
= emit_insn (par
);
12614 add_reg_note (par
, REG_FRAME_RELATED_EXPR
, dwarf
);
12615 RTX_FRAME_RELATED_P (par
) = 1;
12620 /* Emit a call instruction with pattern PAT. ADDR is the address of
12621 the call target. */
12624 arm_emit_call_insn (rtx pat
, rtx addr
)
12628 insn
= emit_call_insn (pat
);
12630 /* The PIC register is live on entry to VxWorks PIC PLT entries.
12631 If the call might use such an entry, add a use of the PIC register
12632 to the instruction's CALL_INSN_FUNCTION_USAGE. */
12633 if (TARGET_VXWORKS_RTP
12635 && GET_CODE (addr
) == SYMBOL_REF
12636 && (SYMBOL_REF_DECL (addr
)
12637 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
12638 : !SYMBOL_REF_LOCAL_P (addr
)))
12640 require_pic_register ();
12641 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), cfun
->machine
->pic_reg
);
12645 /* Output a 'call' insn. */
12647 output_call (rtx
*operands
)
12649 gcc_assert (!arm_arch5
); /* Patterns should call blx <reg> directly. */
12651 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
12652 if (REGNO (operands
[0]) == LR_REGNUM
)
12654 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
12655 output_asm_insn ("mov%?\t%0, %|lr", operands
);
12658 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
12660 if (TARGET_INTERWORK
|| arm_arch4t
)
12661 output_asm_insn ("bx%?\t%0", operands
);
12663 output_asm_insn ("mov%?\t%|pc, %0", operands
);
12668 /* Output a 'call' insn that is a reference in memory. This is
12669 disabled for ARMv5 and we prefer a blx instead because otherwise
12670 there's a significant performance overhead. */
12672 output_call_mem (rtx
*operands
)
12674 gcc_assert (!arm_arch5
);
12675 if (TARGET_INTERWORK
)
12677 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
12678 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
12679 output_asm_insn ("bx%?\t%|ip", operands
);
12681 else if (regno_use_in (LR_REGNUM
, operands
[0]))
12683 /* LR is used in the memory address. We load the address in the
12684 first instruction. It's safe to use IP as the target of the
12685 load since the call will kill it anyway. */
12686 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
12687 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
12689 output_asm_insn ("bx%?\t%|ip", operands
);
12691 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
12695 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
12696 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
12703 /* Output a move from arm registers to an fpa registers.
12704 OPERANDS[0] is an fpa register.
12705 OPERANDS[1] is the first registers of an arm register pair. */
12707 output_mov_long_double_fpa_from_arm (rtx
*operands
)
12709 int arm_reg0
= REGNO (operands
[1]);
12712 gcc_assert (arm_reg0
!= IP_REGNUM
);
12714 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
12715 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
12716 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
12718 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1, %2}", ops
);
12719 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
12724 /* Output a move from an fpa register to arm registers.
12725 OPERANDS[0] is the first registers of an arm register pair.
12726 OPERANDS[1] is an fpa register. */
12728 output_mov_long_double_arm_from_fpa (rtx
*operands
)
12730 int arm_reg0
= REGNO (operands
[0]);
12733 gcc_assert (arm_reg0
!= IP_REGNUM
);
12735 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
12736 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
12737 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
12739 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
12740 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1, %2}", ops
);
12744 /* Output a move from arm registers to arm registers of a long double
12745 OPERANDS[0] is the destination.
12746 OPERANDS[1] is the source. */
12748 output_mov_long_double_arm_from_arm (rtx
*operands
)
12750 /* We have to be careful here because the two might overlap. */
12751 int dest_start
= REGNO (operands
[0]);
12752 int src_start
= REGNO (operands
[1]);
12756 if (dest_start
< src_start
)
12758 for (i
= 0; i
< 3; i
++)
12760 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
12761 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
12762 output_asm_insn ("mov%?\t%0, %1", ops
);
12767 for (i
= 2; i
>= 0; i
--)
12769 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
12770 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
12771 output_asm_insn ("mov%?\t%0, %1", ops
);
12779 arm_emit_movpair (rtx dest
, rtx src
)
12781 /* If the src is an immediate, simplify it. */
12782 if (CONST_INT_P (src
))
12784 HOST_WIDE_INT val
= INTVAL (src
);
12785 emit_set_insn (dest
, GEN_INT (val
& 0x0000ffff));
12786 if ((val
>> 16) & 0x0000ffff)
12787 emit_set_insn (gen_rtx_ZERO_EXTRACT (SImode
, dest
, GEN_INT (16),
12789 GEN_INT ((val
>> 16) & 0x0000ffff));
12792 emit_set_insn (dest
, gen_rtx_HIGH (SImode
, src
));
12793 emit_set_insn (dest
, gen_rtx_LO_SUM (SImode
, dest
, src
));
12796 /* Output a move from arm registers to an fpa registers.
12797 OPERANDS[0] is an fpa register.
12798 OPERANDS[1] is the first registers of an arm register pair. */
12800 output_mov_double_fpa_from_arm (rtx
*operands
)
12802 int arm_reg0
= REGNO (operands
[1]);
12805 gcc_assert (arm_reg0
!= IP_REGNUM
);
12807 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
12808 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
12809 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1}", ops
);
12810 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
12814 /* Output a move from an fpa register to arm registers.
12815 OPERANDS[0] is the first registers of an arm register pair.
12816 OPERANDS[1] is an fpa register. */
12818 output_mov_double_arm_from_fpa (rtx
*operands
)
12820 int arm_reg0
= REGNO (operands
[0]);
12823 gcc_assert (arm_reg0
!= IP_REGNUM
);
12825 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
12826 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
12827 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
12828 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1}", ops
);
12832 /* Output a move between double words. It must be REG<-MEM
12835 output_move_double (rtx
*operands
)
12837 enum rtx_code code0
= GET_CODE (operands
[0]);
12838 enum rtx_code code1
= GET_CODE (operands
[1]);
12843 unsigned int reg0
= REGNO (operands
[0]);
12845 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
12847 gcc_assert (code1
== MEM
); /* Constraints should ensure this. */
12849 switch (GET_CODE (XEXP (operands
[1], 0)))
12853 && !(fix_cm3_ldrd
&& reg0
== REGNO(XEXP (operands
[1], 0))))
12854 output_asm_insn ("ldr%(d%)\t%0, [%m1]", operands
);
12856 output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands
);
12860 gcc_assert (TARGET_LDRD
);
12861 output_asm_insn ("ldr%(d%)\t%0, [%m1, #8]!", operands
);
12866 output_asm_insn ("ldr%(d%)\t%0, [%m1, #-8]!", operands
);
12868 output_asm_insn ("ldm%(db%)\t%m1!, %M0", operands
);
12873 output_asm_insn ("ldr%(d%)\t%0, [%m1], #8", operands
);
12875 output_asm_insn ("ldm%(ia%)\t%m1!, %M0", operands
);
12879 gcc_assert (TARGET_LDRD
);
12880 output_asm_insn ("ldr%(d%)\t%0, [%m1], #-8", operands
);
12885 /* Autoicrement addressing modes should never have overlapping
12886 base and destination registers, and overlapping index registers
12887 are already prohibited, so this doesn't need to worry about
12889 otherops
[0] = operands
[0];
12890 otherops
[1] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 0);
12891 otherops
[2] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 1);
12893 if (GET_CODE (XEXP (operands
[1], 0)) == PRE_MODIFY
)
12895 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
12897 /* Registers overlap so split out the increment. */
12898 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
12899 output_asm_insn ("ldr%(d%)\t%0, [%1] @split", otherops
);
12903 /* Use a single insn if we can.
12904 FIXME: IWMMXT allows offsets larger than ldrd can
12905 handle, fix these up with a pair of ldr. */
12907 || GET_CODE (otherops
[2]) != CONST_INT
12908 || (INTVAL (otherops
[2]) > -256
12909 && INTVAL (otherops
[2]) < 256))
12910 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]!", otherops
);
12913 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops
);
12914 output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops
);
12920 /* Use a single insn if we can.
12921 FIXME: IWMMXT allows offsets larger than ldrd can handle,
12922 fix these up with a pair of ldr. */
12924 || GET_CODE (otherops
[2]) != CONST_INT
12925 || (INTVAL (otherops
[2]) > -256
12926 && INTVAL (otherops
[2]) < 256))
12927 output_asm_insn ("ldr%(d%)\t%0, [%1], %2", otherops
);
12930 output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops
);
12931 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops
);
12938 /* We might be able to use ldrd %0, %1 here. However the range is
12939 different to ldr/adr, and it is broken on some ARMv7-M
12940 implementations. */
12941 /* Use the second register of the pair to avoid problematic
12943 otherops
[1] = operands
[1];
12944 output_asm_insn ("adr%?\t%0, %1", otherops
);
12945 operands
[1] = otherops
[0];
12947 output_asm_insn ("ldr%(d%)\t%0, [%1]", operands
);
12949 output_asm_insn ("ldm%(ia%)\t%1, %M0", operands
);
12952 /* ??? This needs checking for thumb2. */
12954 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
12955 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
12957 otherops
[0] = operands
[0];
12958 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
12959 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
12961 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
12963 if (GET_CODE (otherops
[2]) == CONST_INT
&& !TARGET_LDRD
)
12965 switch ((int) INTVAL (otherops
[2]))
12968 output_asm_insn ("ldm%(db%)\t%1, %M0", otherops
);
12973 output_asm_insn ("ldm%(da%)\t%1, %M0", otherops
);
12978 output_asm_insn ("ldm%(ib%)\t%1, %M0", otherops
);
12982 otherops
[0] = gen_rtx_REG(SImode
, REGNO(operands
[0]) + 1);
12983 operands
[1] = otherops
[0];
12985 && (GET_CODE (otherops
[2]) == REG
12987 || (GET_CODE (otherops
[2]) == CONST_INT
12988 && INTVAL (otherops
[2]) > -256
12989 && INTVAL (otherops
[2]) < 256)))
12991 if (reg_overlap_mentioned_p (operands
[0],
12995 /* Swap base and index registers over to
12996 avoid a conflict. */
12998 otherops
[1] = otherops
[2];
13001 /* If both registers conflict, it will usually
13002 have been fixed by a splitter. */
13003 if (reg_overlap_mentioned_p (operands
[0], otherops
[2])
13004 || (fix_cm3_ldrd
&& reg0
== REGNO (otherops
[1])))
13006 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
13007 output_asm_insn ("ldr%(d%)\t%0, [%1]", operands
);
13011 otherops
[0] = operands
[0];
13012 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]", otherops
);
13017 if (GET_CODE (otherops
[2]) == CONST_INT
)
13019 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
13020 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
13022 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
13025 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
13028 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
13031 return "ldr%(d%)\t%0, [%1]";
13033 return "ldm%(ia%)\t%1, %M0";
13037 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
13038 /* Take care of overlapping base/data reg. */
13039 if (reg_mentioned_p (operands
[0], operands
[1]))
13041 output_asm_insn ("ldr%?\t%0, %1", otherops
);
13042 output_asm_insn ("ldr%?\t%0, %1", operands
);
13046 output_asm_insn ("ldr%?\t%0, %1", operands
);
13047 output_asm_insn ("ldr%?\t%0, %1", otherops
);
13054 /* Constraints should ensure this. */
13055 gcc_assert (code0
== MEM
&& code1
== REG
);
13056 gcc_assert (REGNO (operands
[1]) != IP_REGNUM
);
13058 switch (GET_CODE (XEXP (operands
[0], 0)))
13062 output_asm_insn ("str%(d%)\t%1, [%m0]", operands
);
13064 output_asm_insn ("stm%(ia%)\t%m0, %M1", operands
);
13068 gcc_assert (TARGET_LDRD
);
13069 output_asm_insn ("str%(d%)\t%1, [%m0, #8]!", operands
);
13074 output_asm_insn ("str%(d%)\t%1, [%m0, #-8]!", operands
);
13076 output_asm_insn ("stm%(db%)\t%m0!, %M1", operands
);
13081 output_asm_insn ("str%(d%)\t%1, [%m0], #8", operands
);
13083 output_asm_insn ("stm%(ia%)\t%m0!, %M1", operands
);
13087 gcc_assert (TARGET_LDRD
);
13088 output_asm_insn ("str%(d%)\t%1, [%m0], #-8", operands
);
13093 otherops
[0] = operands
[1];
13094 otherops
[1] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 0);
13095 otherops
[2] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 1);
13097 /* IWMMXT allows offsets larger than ldrd can handle,
13098 fix these up with a pair of ldr. */
13100 && GET_CODE (otherops
[2]) == CONST_INT
13101 && (INTVAL(otherops
[2]) <= -256
13102 || INTVAL(otherops
[2]) >= 256))
13104 if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
13106 output_asm_insn ("str%?\t%0, [%1, %2]!", otherops
);
13107 output_asm_insn ("str%?\t%H0, [%1, #4]", otherops
);
13111 output_asm_insn ("str%?\t%H0, [%1, #4]", otherops
);
13112 output_asm_insn ("str%?\t%0, [%1], %2", otherops
);
13115 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
13116 output_asm_insn ("str%(d%)\t%0, [%1, %2]!", otherops
);
13118 output_asm_insn ("str%(d%)\t%0, [%1], %2", otherops
);
13122 otherops
[2] = XEXP (XEXP (operands
[0], 0), 1);
13123 if (GET_CODE (otherops
[2]) == CONST_INT
&& !TARGET_LDRD
)
13125 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
13128 output_asm_insn ("stm%(db%)\t%m0, %M1", operands
);
13134 output_asm_insn ("stm%(da%)\t%m0, %M1", operands
);
13140 output_asm_insn ("stm%(ib%)\t%m0, %M1", operands
);
13145 && (GET_CODE (otherops
[2]) == REG
13147 || (GET_CODE (otherops
[2]) == CONST_INT
13148 && INTVAL (otherops
[2]) > -256
13149 && INTVAL (otherops
[2]) < 256)))
13151 otherops
[0] = operands
[1];
13152 otherops
[1] = XEXP (XEXP (operands
[0], 0), 0);
13153 output_asm_insn ("str%(d%)\t%0, [%1, %2]", otherops
);
13159 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
13160 otherops
[1] = operands
[1];
13161 output_asm_insn ("str%?\t%1, %0", operands
);
13162 output_asm_insn ("str%?\t%H1, %0", otherops
);
13169 /* Output a move, load or store for quad-word vectors in ARM registers. Only
13170 handles MEMs accepted by neon_vector_mem_operand with TYPE=1. */
13173 output_move_quad (rtx
*operands
)
13175 if (REG_P (operands
[0]))
13177 /* Load, or reg->reg move. */
13179 if (MEM_P (operands
[1]))
13181 switch (GET_CODE (XEXP (operands
[1], 0)))
13184 output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands
);
13189 output_asm_insn ("adr%?\t%0, %1", operands
);
13190 output_asm_insn ("ldm%(ia%)\t%0, %M0", operands
);
13194 gcc_unreachable ();
13202 gcc_assert (REG_P (operands
[1]));
13204 dest
= REGNO (operands
[0]);
13205 src
= REGNO (operands
[1]);
13207 /* This seems pretty dumb, but hopefully GCC won't try to do it
13210 for (i
= 0; i
< 4; i
++)
13212 ops
[0] = gen_rtx_REG (SImode
, dest
+ i
);
13213 ops
[1] = gen_rtx_REG (SImode
, src
+ i
);
13214 output_asm_insn ("mov%?\t%0, %1", ops
);
13217 for (i
= 3; i
>= 0; i
--)
13219 ops
[0] = gen_rtx_REG (SImode
, dest
+ i
);
13220 ops
[1] = gen_rtx_REG (SImode
, src
+ i
);
13221 output_asm_insn ("mov%?\t%0, %1", ops
);
13227 gcc_assert (MEM_P (operands
[0]));
13228 gcc_assert (REG_P (operands
[1]));
13229 gcc_assert (!reg_overlap_mentioned_p (operands
[1], operands
[0]));
13231 switch (GET_CODE (XEXP (operands
[0], 0)))
13234 output_asm_insn ("stm%(ia%)\t%m0, %M1", operands
);
13238 gcc_unreachable ();
13245 /* Output a VFP load or store instruction. */
13248 output_move_vfp (rtx
*operands
)
13250 rtx reg
, mem
, addr
, ops
[2];
13251 int load
= REG_P (operands
[0]);
13252 int dp
= GET_MODE_SIZE (GET_MODE (operands
[0])) == 8;
13253 int integer_p
= GET_MODE_CLASS (GET_MODE (operands
[0])) == MODE_INT
;
13256 enum machine_mode mode
;
13258 reg
= operands
[!load
];
13259 mem
= operands
[load
];
13261 mode
= GET_MODE (reg
);
13263 gcc_assert (REG_P (reg
));
13264 gcc_assert (IS_VFP_REGNUM (REGNO (reg
)));
13265 gcc_assert (mode
== SFmode
13269 || (TARGET_NEON
&& VALID_NEON_DREG_MODE (mode
)));
13270 gcc_assert (MEM_P (mem
));
13272 addr
= XEXP (mem
, 0);
13274 switch (GET_CODE (addr
))
13277 templ
= "f%smdb%c%%?\t%%0!, {%%%s1}%s";
13278 ops
[0] = XEXP (addr
, 0);
13283 templ
= "f%smia%c%%?\t%%0!, {%%%s1}%s";
13284 ops
[0] = XEXP (addr
, 0);
13289 templ
= "f%s%c%%?\t%%%s0, %%1%s";
13295 sprintf (buff
, templ
,
13296 load
? "ld" : "st",
13299 integer_p
? "\t%@ int" : "");
13300 output_asm_insn (buff
, ops
);
13305 /* Output a Neon quad-word load or store, or a load or store for
13306 larger structure modes.
13308 WARNING: The ordering of elements is weird in big-endian mode,
13309 because we use VSTM, as required by the EABI. GCC RTL defines
13310 element ordering based on in-memory order. This can be differ
13311 from the architectural ordering of elements within a NEON register.
13312 The intrinsics defined in arm_neon.h use the NEON register element
13313 ordering, not the GCC RTL element ordering.
13315 For example, the in-memory ordering of a big-endian a quadword
13316 vector with 16-bit elements when stored from register pair {d0,d1}
13317 will be (lowest address first, d0[N] is NEON register element N):
13319 [d0[3], d0[2], d0[1], d0[0], d1[7], d1[6], d1[5], d1[4]]
13321 When necessary, quadword registers (dN, dN+1) are moved to ARM
13322 registers from rN in the order:
13324 dN -> (rN+1, rN), dN+1 -> (rN+3, rN+2)
13326 So that STM/LDM can be used on vectors in ARM registers, and the
13327 same memory layout will result as if VSTM/VLDM were used. */
13330 output_move_neon (rtx
*operands
)
13332 rtx reg
, mem
, addr
, ops
[2];
13333 int regno
, load
= REG_P (operands
[0]);
13336 enum machine_mode mode
;
13338 reg
= operands
[!load
];
13339 mem
= operands
[load
];
13341 mode
= GET_MODE (reg
);
13343 gcc_assert (REG_P (reg
));
13344 regno
= REGNO (reg
);
13345 gcc_assert (VFP_REGNO_OK_FOR_DOUBLE (regno
)
13346 || NEON_REGNO_OK_FOR_QUAD (regno
));
13347 gcc_assert (VALID_NEON_DREG_MODE (mode
)
13348 || VALID_NEON_QREG_MODE (mode
)
13349 || VALID_NEON_STRUCT_MODE (mode
));
13350 gcc_assert (MEM_P (mem
));
13352 addr
= XEXP (mem
, 0);
13354 /* Strip off const from addresses like (const (plus (...))). */
13355 if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
)
13356 addr
= XEXP (addr
, 0);
13358 switch (GET_CODE (addr
))
13361 templ
= "v%smia%%?\t%%0!, %%h1";
13362 ops
[0] = XEXP (addr
, 0);
13367 /* FIXME: We should be using vld1/vst1 here in BE mode? */
13368 templ
= "v%smdb%%?\t%%0!, %%h1";
13369 ops
[0] = XEXP (addr
, 0);
13374 /* FIXME: Not currently enabled in neon_vector_mem_operand. */
13375 gcc_unreachable ();
13380 int nregs
= HARD_REGNO_NREGS (REGNO (reg
), mode
) / 2;
13383 for (i
= 0; i
< nregs
; i
++)
13385 /* We're only using DImode here because it's a convenient size. */
13386 ops
[0] = gen_rtx_REG (DImode
, REGNO (reg
) + 2 * i
);
13387 ops
[1] = adjust_address (mem
, DImode
, 8 * i
);
13388 if (reg_overlap_mentioned_p (ops
[0], mem
))
13390 gcc_assert (overlap
== -1);
13395 sprintf (buff
, "v%sr%%?\t%%P0, %%1", load
? "ld" : "st");
13396 output_asm_insn (buff
, ops
);
13401 ops
[0] = gen_rtx_REG (DImode
, REGNO (reg
) + 2 * overlap
);
13402 ops
[1] = adjust_address (mem
, SImode
, 8 * overlap
);
13403 sprintf (buff
, "v%sr%%?\t%%P0, %%1", load
? "ld" : "st");
13404 output_asm_insn (buff
, ops
);
13411 templ
= "v%smia%%?\t%%m0, %%h1";
13416 sprintf (buff
, templ
, load
? "ld" : "st");
13417 output_asm_insn (buff
, ops
);
13422 /* Compute and return the length of neon_mov<mode>, where <mode> is
13423 one of VSTRUCT modes: EI, OI, CI or XI. */
13425 arm_attr_length_move_neon (rtx insn
)
13427 rtx reg
, mem
, addr
;
13429 enum machine_mode mode
;
13431 extract_insn_cached (insn
);
13433 if (REG_P (recog_data
.operand
[0]) && REG_P (recog_data
.operand
[1]))
13435 mode
= GET_MODE (recog_data
.operand
[0]);
13446 gcc_unreachable ();
13450 load
= REG_P (recog_data
.operand
[0]);
13451 reg
= recog_data
.operand
[!load
];
13452 mem
= recog_data
.operand
[load
];
13454 gcc_assert (MEM_P (mem
));
13456 mode
= GET_MODE (reg
);
13457 addr
= XEXP (mem
, 0);
13459 /* Strip off const from addresses like (const (plus (...))). */
13460 if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
)
13461 addr
= XEXP (addr
, 0);
13463 if (GET_CODE (addr
) == LABEL_REF
|| GET_CODE (addr
) == PLUS
)
13465 int insns
= HARD_REGNO_NREGS (REGNO (reg
), mode
) / 2;
13472 /* Return nonzero if the offset in the address is an immediate. Otherwise,
13476 arm_address_offset_is_imm (rtx insn
)
13480 extract_insn_cached (insn
);
13482 if (REG_P (recog_data
.operand
[0]))
13485 mem
= recog_data
.operand
[0];
13487 gcc_assert (MEM_P (mem
));
13489 addr
= XEXP (mem
, 0);
13491 if (GET_CODE (addr
) == REG
13492 || (GET_CODE (addr
) == PLUS
13493 && GET_CODE (XEXP (addr
, 0)) == REG
13494 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
))
13500 /* Output an ADD r, s, #n where n may be too big for one instruction.
13501 If adding zero to one register, output nothing. */
13503 output_add_immediate (rtx
*operands
)
13505 HOST_WIDE_INT n
= INTVAL (operands
[2]);
13507 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
13510 output_multi_immediate (operands
,
13511 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
13514 output_multi_immediate (operands
,
13515 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
13522 /* Output a multiple immediate operation.
13523 OPERANDS is the vector of operands referred to in the output patterns.
13524 INSTR1 is the output pattern to use for the first constant.
13525 INSTR2 is the output pattern to use for subsequent constants.
13526 IMMED_OP is the index of the constant slot in OPERANDS.
13527 N is the constant value. */
13528 static const char *
13529 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
13530 int immed_op
, HOST_WIDE_INT n
)
13532 #if HOST_BITS_PER_WIDE_INT > 32
13538 /* Quick and easy output. */
13539 operands
[immed_op
] = const0_rtx
;
13540 output_asm_insn (instr1
, operands
);
13545 const char * instr
= instr1
;
13547 /* Note that n is never zero here (which would give no output). */
13548 for (i
= 0; i
< 32; i
+= 2)
13552 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
13553 output_asm_insn (instr
, operands
);
13563 /* Return the name of a shifter operation. */
13564 static const char *
13565 arm_shift_nmem(enum rtx_code code
)
13570 return ARM_LSL_NAME
;
13586 /* Return the appropriate ARM instruction for the operation code.
13587 The returned result should not be overwritten. OP is the rtx of the
13588 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
13591 arithmetic_instr (rtx op
, int shift_first_arg
)
13593 switch (GET_CODE (op
))
13599 return shift_first_arg
? "rsb" : "sub";
13614 return arm_shift_nmem(GET_CODE(op
));
13617 gcc_unreachable ();
13621 /* Ensure valid constant shifts and return the appropriate shift mnemonic
13622 for the operation code. The returned result should not be overwritten.
13623 OP is the rtx code of the shift.
13624 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
13626 static const char *
13627 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
13630 enum rtx_code code
= GET_CODE (op
);
13632 switch (GET_CODE (XEXP (op
, 1)))
13640 *amountp
= INTVAL (XEXP (op
, 1));
13644 gcc_unreachable ();
13650 gcc_assert (*amountp
!= -1);
13651 *amountp
= 32 - *amountp
;
13654 /* Fall through. */
13660 mnem
= arm_shift_nmem(code
);
13664 /* We never have to worry about the amount being other than a
13665 power of 2, since this case can never be reloaded from a reg. */
13666 gcc_assert (*amountp
!= -1);
13667 *amountp
= int_log2 (*amountp
);
13668 return ARM_LSL_NAME
;
13671 gcc_unreachable ();
13674 if (*amountp
!= -1)
13676 /* This is not 100% correct, but follows from the desire to merge
13677 multiplication by a power of 2 with the recognizer for a
13678 shift. >=32 is not a valid shift for "lsl", so we must try and
13679 output a shift that produces the correct arithmetical result.
13680 Using lsr #32 is identical except for the fact that the carry bit
13681 is not set correctly if we set the flags; but we never use the
13682 carry bit from such an operation, so we can ignore that. */
13683 if (code
== ROTATERT
)
13684 /* Rotate is just modulo 32. */
13686 else if (*amountp
!= (*amountp
& 31))
13688 if (code
== ASHIFT
)
13693 /* Shifts of 0 are no-ops. */
13701 /* Obtain the shift from the POWER of two. */
13703 static HOST_WIDE_INT
13704 int_log2 (HOST_WIDE_INT power
)
13706 HOST_WIDE_INT shift
= 0;
13708 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
13710 gcc_assert (shift
<= 31);
13717 /* Output a .ascii pseudo-op, keeping track of lengths. This is
13718 because /bin/as is horribly restrictive. The judgement about
13719 whether or not each character is 'printable' (and can be output as
13720 is) or not (and must be printed with an octal escape) must be made
13721 with reference to the *host* character set -- the situation is
13722 similar to that discussed in the comments above pp_c_char in
13723 c-pretty-print.c. */
13725 #define MAX_ASCII_LEN 51
13728 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
13731 int len_so_far
= 0;
13733 fputs ("\t.ascii\t\"", stream
);
13735 for (i
= 0; i
< len
; i
++)
13739 if (len_so_far
>= MAX_ASCII_LEN
)
13741 fputs ("\"\n\t.ascii\t\"", stream
);
13747 if (c
== '\\' || c
== '\"')
13749 putc ('\\', stream
);
13757 fprintf (stream
, "\\%03o", c
);
13762 fputs ("\"\n", stream
);
13765 /* Compute the register save mask for registers 0 through 12
13766 inclusive. This code is used by arm_compute_save_reg_mask. */
13768 static unsigned long
13769 arm_compute_save_reg0_reg12_mask (void)
13771 unsigned long func_type
= arm_current_func_type ();
13772 unsigned long save_reg_mask
= 0;
13775 if (IS_INTERRUPT (func_type
))
13777 unsigned int max_reg
;
13778 /* Interrupt functions must not corrupt any registers,
13779 even call clobbered ones. If this is a leaf function
13780 we can just examine the registers used by the RTL, but
13781 otherwise we have to assume that whatever function is
13782 called might clobber anything, and so we have to save
13783 all the call-clobbered registers as well. */
13784 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
13785 /* FIQ handlers have registers r8 - r12 banked, so
13786 we only need to check r0 - r7, Normal ISRs only
13787 bank r14 and r15, so we must check up to r12.
13788 r13 is the stack pointer which is always preserved,
13789 so we do not need to consider it here. */
13794 for (reg
= 0; reg
<= max_reg
; reg
++)
13795 if (df_regs_ever_live_p (reg
)
13796 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
13797 save_reg_mask
|= (1 << reg
);
13799 /* Also save the pic base register if necessary. */
13801 && !TARGET_SINGLE_PIC_BASE
13802 && arm_pic_register
!= INVALID_REGNUM
13803 && crtl
->uses_pic_offset_table
)
13804 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
13806 else if (IS_VOLATILE(func_type
))
13808 /* For noreturn functions we historically omitted register saves
13809 altogether. However this really messes up debugging. As a
13810 compromise save just the frame pointers. Combined with the link
13811 register saved elsewhere this should be sufficient to get
13813 if (frame_pointer_needed
)
13814 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
13815 if (df_regs_ever_live_p (ARM_HARD_FRAME_POINTER_REGNUM
))
13816 save_reg_mask
|= 1 << ARM_HARD_FRAME_POINTER_REGNUM
;
13817 if (df_regs_ever_live_p (THUMB_HARD_FRAME_POINTER_REGNUM
))
13818 save_reg_mask
|= 1 << THUMB_HARD_FRAME_POINTER_REGNUM
;
13822 /* In the normal case we only need to save those registers
13823 which are call saved and which are used by this function. */
13824 for (reg
= 0; reg
<= 11; reg
++)
13825 if (df_regs_ever_live_p (reg
) && ! call_used_regs
[reg
])
13826 save_reg_mask
|= (1 << reg
);
13828 /* Handle the frame pointer as a special case. */
13829 if (frame_pointer_needed
)
13830 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
13832 /* If we aren't loading the PIC register,
13833 don't stack it even though it may be live. */
13835 && !TARGET_SINGLE_PIC_BASE
13836 && arm_pic_register
!= INVALID_REGNUM
13837 && (df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
)
13838 || crtl
->uses_pic_offset_table
))
13839 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
13841 /* The prologue will copy SP into R0, so save it. */
13842 if (IS_STACKALIGN (func_type
))
13843 save_reg_mask
|= 1;
13846 /* Save registers so the exception handler can modify them. */
13847 if (crtl
->calls_eh_return
)
13853 reg
= EH_RETURN_DATA_REGNO (i
);
13854 if (reg
== INVALID_REGNUM
)
13856 save_reg_mask
|= 1 << reg
;
13860 return save_reg_mask
;
13864 /* Compute the number of bytes used to store the static chain register on the
13865 stack, above the stack frame. We need to know this accurately to get the
13866 alignment of the rest of the stack frame correct. */
13868 static int arm_compute_static_chain_stack_bytes (void)
13870 unsigned long func_type
= arm_current_func_type ();
13871 int static_chain_stack_bytes
= 0;
13873 if (TARGET_APCS_FRAME
&& frame_pointer_needed
&& TARGET_ARM
&&
13874 IS_NESTED (func_type
) &&
13875 df_regs_ever_live_p (3) && crtl
->args
.pretend_args_size
== 0)
13876 static_chain_stack_bytes
= 4;
13878 return static_chain_stack_bytes
;
13882 /* Compute a bit mask of which registers need to be
13883 saved on the stack for the current function.
13884 This is used by arm_get_frame_offsets, which may add extra registers. */
13886 static unsigned long
13887 arm_compute_save_reg_mask (void)
13889 unsigned int save_reg_mask
= 0;
13890 unsigned long func_type
= arm_current_func_type ();
13893 if (IS_NAKED (func_type
))
13894 /* This should never really happen. */
13897 /* If we are creating a stack frame, then we must save the frame pointer,
13898 IP (which will hold the old stack pointer), LR and the PC. */
13899 if (TARGET_APCS_FRAME
&& frame_pointer_needed
&& TARGET_ARM
)
13901 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
13904 | (1 << PC_REGNUM
);
13906 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
13908 /* Decide if we need to save the link register.
13909 Interrupt routines have their own banked link register,
13910 so they never need to save it.
13911 Otherwise if we do not use the link register we do not need to save
13912 it. If we are pushing other registers onto the stack however, we
13913 can save an instruction in the epilogue by pushing the link register
13914 now and then popping it back into the PC. This incurs extra memory
13915 accesses though, so we only do it when optimizing for size, and only
13916 if we know that we will not need a fancy return sequence. */
13917 if (df_regs_ever_live_p (LR_REGNUM
)
13920 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
13921 && !crtl
->calls_eh_return
))
13922 save_reg_mask
|= 1 << LR_REGNUM
;
13924 if (cfun
->machine
->lr_save_eliminated
)
13925 save_reg_mask
&= ~ (1 << LR_REGNUM
);
13927 if (TARGET_REALLY_IWMMXT
13928 && ((bit_count (save_reg_mask
)
13929 + ARM_NUM_INTS (crtl
->args
.pretend_args_size
+
13930 arm_compute_static_chain_stack_bytes())
13933 /* The total number of registers that are going to be pushed
13934 onto the stack is odd. We need to ensure that the stack
13935 is 64-bit aligned before we start to save iWMMXt registers,
13936 and also before we start to create locals. (A local variable
13937 might be a double or long long which we will load/store using
13938 an iWMMXt instruction). Therefore we need to push another
13939 ARM register, so that the stack will be 64-bit aligned. We
13940 try to avoid using the arg registers (r0 -r3) as they might be
13941 used to pass values in a tail call. */
13942 for (reg
= 4; reg
<= 12; reg
++)
13943 if ((save_reg_mask
& (1 << reg
)) == 0)
13947 save_reg_mask
|= (1 << reg
);
13950 cfun
->machine
->sibcall_blocked
= 1;
13951 save_reg_mask
|= (1 << 3);
13955 /* We may need to push an additional register for use initializing the
13956 PIC base register. */
13957 if (TARGET_THUMB2
&& IS_NESTED (func_type
) && flag_pic
13958 && (save_reg_mask
& THUMB2_WORK_REGS
) == 0)
13960 reg
= thumb_find_work_register (1 << 4);
13961 if (!call_used_regs
[reg
])
13962 save_reg_mask
|= (1 << reg
);
13965 return save_reg_mask
;
13969 /* Compute a bit mask of which registers need to be
13970 saved on the stack for the current function. */
13971 static unsigned long
13972 thumb1_compute_save_reg_mask (void)
13974 unsigned long mask
;
13978 for (reg
= 0; reg
< 12; reg
++)
13979 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
13983 && !TARGET_SINGLE_PIC_BASE
13984 && arm_pic_register
!= INVALID_REGNUM
13985 && crtl
->uses_pic_offset_table
)
13986 mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
13988 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
13989 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
13990 mask
|= 1 << ARM_HARD_FRAME_POINTER_REGNUM
;
13992 /* LR will also be pushed if any lo regs are pushed. */
13993 if (mask
& 0xff || thumb_force_lr_save ())
13994 mask
|= (1 << LR_REGNUM
);
13996 /* Make sure we have a low work register if we need one.
13997 We will need one if we are going to push a high register,
13998 but we are not currently intending to push a low register. */
13999 if ((mask
& 0xff) == 0
14000 && ((mask
& 0x0f00) || TARGET_BACKTRACE
))
14002 /* Use thumb_find_work_register to choose which register
14003 we will use. If the register is live then we will
14004 have to push it. Use LAST_LO_REGNUM as our fallback
14005 choice for the register to select. */
14006 reg
= thumb_find_work_register (1 << LAST_LO_REGNUM
);
14007 /* Make sure the register returned by thumb_find_work_register is
14008 not part of the return value. */
14009 if (reg
* UNITS_PER_WORD
<= (unsigned) arm_size_return_regs ())
14010 reg
= LAST_LO_REGNUM
;
14012 if (! call_used_regs
[reg
])
14016 /* The 504 below is 8 bytes less than 512 because there are two possible
14017 alignment words. We can't tell here if they will be present or not so we
14018 have to play it safe and assume that they are. */
14019 if ((CALLER_INTERWORKING_SLOT_SIZE
+
14020 ROUND_UP_WORD (get_frame_size ()) +
14021 crtl
->outgoing_args_size
) >= 504)
14023 /* This is the same as the code in thumb1_expand_prologue() which
14024 determines which register to use for stack decrement. */
14025 for (reg
= LAST_ARG_REGNUM
+ 1; reg
<= LAST_LO_REGNUM
; reg
++)
14026 if (mask
& (1 << reg
))
14029 if (reg
> LAST_LO_REGNUM
)
14031 /* Make sure we have a register available for stack decrement. */
14032 mask
|= 1 << LAST_LO_REGNUM
;
14040 /* Return the number of bytes required to save VFP registers. */
14042 arm_get_vfp_saved_size (void)
14044 unsigned int regno
;
14049 /* Space for saved VFP registers. */
14050 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
14053 for (regno
= FIRST_VFP_REGNUM
;
14054 regno
< LAST_VFP_REGNUM
;
14057 if ((!df_regs_ever_live_p (regno
) || call_used_regs
[regno
])
14058 && (!df_regs_ever_live_p (regno
+ 1) || call_used_regs
[regno
+ 1]))
14062 /* Workaround ARM10 VFPr1 bug. */
14063 if (count
== 2 && !arm_arch6
)
14065 saved
+= count
* 8;
14074 if (count
== 2 && !arm_arch6
)
14076 saved
+= count
* 8;
14083 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
14084 everything bar the final return instruction. */
14086 output_return_instruction (rtx operand
, int really_return
, int reverse
)
14088 char conditional
[10];
14091 unsigned long live_regs_mask
;
14092 unsigned long func_type
;
14093 arm_stack_offsets
*offsets
;
14095 func_type
= arm_current_func_type ();
14097 if (IS_NAKED (func_type
))
14100 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
14102 /* If this function was declared non-returning, and we have
14103 found a tail call, then we have to trust that the called
14104 function won't return. */
14109 /* Otherwise, trap an attempted return by aborting. */
14111 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
14113 assemble_external_libcall (ops
[1]);
14114 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
14120 gcc_assert (!cfun
->calls_alloca
|| really_return
);
14122 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
14124 cfun
->machine
->return_used_this_function
= 1;
14126 offsets
= arm_get_frame_offsets ();
14127 live_regs_mask
= offsets
->saved_regs_mask
;
14129 if (live_regs_mask
)
14131 const char * return_reg
;
14133 /* If we do not have any special requirements for function exit
14134 (e.g. interworking) then we can load the return address
14135 directly into the PC. Otherwise we must load it into LR. */
14137 && (IS_INTERRUPT (func_type
) || !TARGET_INTERWORK
))
14138 return_reg
= reg_names
[PC_REGNUM
];
14140 return_reg
= reg_names
[LR_REGNUM
];
14142 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
14144 /* There are three possible reasons for the IP register
14145 being saved. 1) a stack frame was created, in which case
14146 IP contains the old stack pointer, or 2) an ISR routine
14147 corrupted it, or 3) it was saved to align the stack on
14148 iWMMXt. In case 1, restore IP into SP, otherwise just
14150 if (frame_pointer_needed
)
14152 live_regs_mask
&= ~ (1 << IP_REGNUM
);
14153 live_regs_mask
|= (1 << SP_REGNUM
);
14156 gcc_assert (IS_INTERRUPT (func_type
) || TARGET_REALLY_IWMMXT
);
14159 /* On some ARM architectures it is faster to use LDR rather than
14160 LDM to load a single register. On other architectures, the
14161 cost is the same. In 26 bit mode, or for exception handlers,
14162 we have to use LDM to load the PC so that the CPSR is also
14164 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
14165 if (live_regs_mask
== (1U << reg
))
14168 if (reg
<= LAST_ARM_REGNUM
14169 && (reg
!= LR_REGNUM
14171 || ! IS_INTERRUPT (func_type
)))
14173 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
14174 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
14181 /* Generate the load multiple instruction to restore the
14182 registers. Note we can get here, even if
14183 frame_pointer_needed is true, but only if sp already
14184 points to the base of the saved core registers. */
14185 if (live_regs_mask
& (1 << SP_REGNUM
))
14187 unsigned HOST_WIDE_INT stack_adjust
;
14189 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
14190 gcc_assert (stack_adjust
== 0 || stack_adjust
== 4);
14192 if (stack_adjust
&& arm_arch5
&& TARGET_ARM
)
14193 if (TARGET_UNIFIED_ASM
)
14194 sprintf (instr
, "ldmib%s\t%%|sp, {", conditional
);
14196 sprintf (instr
, "ldm%sib\t%%|sp, {", conditional
);
14199 /* If we can't use ldmib (SA110 bug),
14200 then try to pop r3 instead. */
14202 live_regs_mask
|= 1 << 3;
14204 if (TARGET_UNIFIED_ASM
)
14205 sprintf (instr
, "ldmfd%s\t%%|sp, {", conditional
);
14207 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
14211 if (TARGET_UNIFIED_ASM
)
14212 sprintf (instr
, "pop%s\t{", conditional
);
14214 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
14216 p
= instr
+ strlen (instr
);
14218 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
14219 if (live_regs_mask
& (1 << reg
))
14221 int l
= strlen (reg_names
[reg
]);
14227 memcpy (p
, ", ", 2);
14231 memcpy (p
, "%|", 2);
14232 memcpy (p
+ 2, reg_names
[reg
], l
);
14236 if (live_regs_mask
& (1 << LR_REGNUM
))
14238 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
14239 /* If returning from an interrupt, restore the CPSR. */
14240 if (IS_INTERRUPT (func_type
))
14247 output_asm_insn (instr
, & operand
);
14249 /* See if we need to generate an extra instruction to
14250 perform the actual function return. */
14252 && func_type
!= ARM_FT_INTERWORKED
14253 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
14255 /* The return has already been handled
14256 by loading the LR into the PC. */
14263 switch ((int) ARM_FUNC_TYPE (func_type
))
14267 /* ??? This is wrong for unified assembly syntax. */
14268 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
14271 case ARM_FT_INTERWORKED
:
14272 sprintf (instr
, "bx%s\t%%|lr", conditional
);
14275 case ARM_FT_EXCEPTION
:
14276 /* ??? This is wrong for unified assembly syntax. */
14277 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
14281 /* Use bx if it's available. */
14282 if (arm_arch5
|| arm_arch4t
)
14283 sprintf (instr
, "bx%s\t%%|lr", conditional
);
14285 sprintf (instr
, "mov%s\t%%|pc, %%|lr", conditional
);
14289 output_asm_insn (instr
, & operand
);
14295 /* Write the function name into the code section, directly preceding
14296 the function prologue.
14298 Code will be output similar to this:
14300 .ascii "arm_poke_function_name", 0
14303 .word 0xff000000 + (t1 - t0)
14304 arm_poke_function_name
14306 stmfd sp!, {fp, ip, lr, pc}
14309 When performing a stack backtrace, code can inspect the value
14310 of 'pc' stored at 'fp' + 0. If the trace function then looks
14311 at location pc - 12 and the top 8 bits are set, then we know
14312 that there is a function name embedded immediately preceding this
14313 location and has length ((pc[-3]) & 0xff000000).
14315 We assume that pc is declared as a pointer to an unsigned long.
14317 It is of no benefit to output the function name if we are assembling
14318 a leaf function. These function types will not contain a stack
14319 backtrace structure, therefore it is not possible to determine the
14322 arm_poke_function_name (FILE *stream
, const char *name
)
14324 unsigned long alignlength
;
14325 unsigned long length
;
14328 length
= strlen (name
) + 1;
14329 alignlength
= ROUND_UP_WORD (length
);
14331 ASM_OUTPUT_ASCII (stream
, name
, length
);
14332 ASM_OUTPUT_ALIGN (stream
, 2);
14333 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
14334 assemble_aligned_integer (UNITS_PER_WORD
, x
);
14337 /* Place some comments into the assembler stream
14338 describing the current function. */
14340 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
14342 unsigned long func_type
;
14346 thumb1_output_function_prologue (f
, frame_size
);
14350 /* Sanity check. */
14351 gcc_assert (!arm_ccfsm_state
&& !arm_target_insn
);
14353 func_type
= arm_current_func_type ();
14355 switch ((int) ARM_FUNC_TYPE (func_type
))
14358 case ARM_FT_NORMAL
:
14360 case ARM_FT_INTERWORKED
:
14361 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
14364 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
14367 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
14369 case ARM_FT_EXCEPTION
:
14370 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
14374 if (IS_NAKED (func_type
))
14375 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
14377 if (IS_VOLATILE (func_type
))
14378 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
14380 if (IS_NESTED (func_type
))
14381 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
14382 if (IS_STACKALIGN (func_type
))
14383 asm_fprintf (f
, "\t%@ Stack Align: May be called with mis-aligned SP.\n");
14385 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
14387 crtl
->args
.pretend_args_size
, frame_size
);
14389 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
14390 frame_pointer_needed
,
14391 cfun
->machine
->uses_anonymous_args
);
14393 if (cfun
->machine
->lr_save_eliminated
)
14394 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
14396 if (crtl
->calls_eh_return
)
14397 asm_fprintf (f
, "\t@ Calls __builtin_eh_return.\n");
14402 arm_output_epilogue (rtx sibling
)
14405 unsigned long saved_regs_mask
;
14406 unsigned long func_type
;
14407 /* Floats_offset is the offset from the "virtual" frame. In an APCS
14408 frame that is $fp + 4 for a non-variadic function. */
14409 int floats_offset
= 0;
14411 FILE * f
= asm_out_file
;
14412 unsigned int lrm_count
= 0;
14413 int really_return
= (sibling
== NULL
);
14415 arm_stack_offsets
*offsets
;
14417 /* If we have already generated the return instruction
14418 then it is futile to generate anything else. */
14419 if (use_return_insn (FALSE
, sibling
) &&
14420 (cfun
->machine
->return_used_this_function
!= 0))
14423 func_type
= arm_current_func_type ();
14425 if (IS_NAKED (func_type
))
14426 /* Naked functions don't have epilogues. */
14429 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
14433 /* A volatile function should never return. Call abort. */
14434 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
14435 assemble_external_libcall (op
);
14436 output_asm_insn ("bl\t%a0", &op
);
14441 /* If we are throwing an exception, then we really must be doing a
14442 return, so we can't tail-call. */
14443 gcc_assert (!crtl
->calls_eh_return
|| really_return
);
14445 offsets
= arm_get_frame_offsets ();
14446 saved_regs_mask
= offsets
->saved_regs_mask
;
14449 lrm_count
= bit_count (saved_regs_mask
);
14451 floats_offset
= offsets
->saved_args
;
14452 /* Compute how far away the floats will be. */
14453 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
14454 if (saved_regs_mask
& (1 << reg
))
14455 floats_offset
+= 4;
14457 if (TARGET_APCS_FRAME
&& frame_pointer_needed
&& TARGET_ARM
)
14459 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
14460 int vfp_offset
= offsets
->frame
;
14462 if (TARGET_FPA_EMU2
)
14464 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
14465 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
14467 floats_offset
+= 12;
14468 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
14469 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
14474 start_reg
= LAST_FPA_REGNUM
;
14476 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
14478 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
14480 floats_offset
+= 12;
14482 /* We can't unstack more than four registers at once. */
14483 if (start_reg
- reg
== 3)
14485 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
14486 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
14487 start_reg
= reg
- 1;
14492 if (reg
!= start_reg
)
14493 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
14494 reg
+ 1, start_reg
- reg
,
14495 FP_REGNUM
, floats_offset
- vfp_offset
);
14496 start_reg
= reg
- 1;
14500 /* Just in case the last register checked also needs unstacking. */
14501 if (reg
!= start_reg
)
14502 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
14503 reg
+ 1, start_reg
- reg
,
14504 FP_REGNUM
, floats_offset
- vfp_offset
);
14507 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
14511 /* The fldmd insns do not have base+offset addressing
14512 modes, so we use IP to hold the address. */
14513 saved_size
= arm_get_vfp_saved_size ();
14515 if (saved_size
> 0)
14517 floats_offset
+= saved_size
;
14518 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", IP_REGNUM
,
14519 FP_REGNUM
, floats_offset
- vfp_offset
);
14521 start_reg
= FIRST_VFP_REGNUM
;
14522 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
14524 if ((!df_regs_ever_live_p (reg
) || call_used_regs
[reg
])
14525 && (!df_regs_ever_live_p (reg
+ 1) || call_used_regs
[reg
+ 1]))
14527 if (start_reg
!= reg
)
14528 vfp_output_fldmd (f
, IP_REGNUM
,
14529 (start_reg
- FIRST_VFP_REGNUM
) / 2,
14530 (reg
- start_reg
) / 2);
14531 start_reg
= reg
+ 2;
14534 if (start_reg
!= reg
)
14535 vfp_output_fldmd (f
, IP_REGNUM
,
14536 (start_reg
- FIRST_VFP_REGNUM
) / 2,
14537 (reg
- start_reg
) / 2);
14542 /* The frame pointer is guaranteed to be non-double-word aligned.
14543 This is because it is set to (old_stack_pointer - 4) and the
14544 old_stack_pointer was double word aligned. Thus the offset to
14545 the iWMMXt registers to be loaded must also be non-double-word
14546 sized, so that the resultant address *is* double-word aligned.
14547 We can ignore floats_offset since that was already included in
14548 the live_regs_mask. */
14549 lrm_count
+= (lrm_count
% 2 ? 2 : 1);
14551 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
14552 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
14554 asm_fprintf (f
, "\twldrd\t%r, [%r, #-%d]\n",
14555 reg
, FP_REGNUM
, lrm_count
* 4);
14560 /* saved_regs_mask should contain the IP, which at the time of stack
14561 frame generation actually contains the old stack pointer. So a
14562 quick way to unwind the stack is just pop the IP register directly
14563 into the stack pointer. */
14564 gcc_assert (saved_regs_mask
& (1 << IP_REGNUM
));
14565 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
14566 saved_regs_mask
|= (1 << SP_REGNUM
);
14568 /* There are two registers left in saved_regs_mask - LR and PC. We
14569 only need to restore the LR register (the return address), but to
14570 save time we can load it directly into the PC, unless we need a
14571 special function exit sequence, or we are not really returning. */
14573 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
14574 && !crtl
->calls_eh_return
)
14575 /* Delete the LR from the register mask, so that the LR on
14576 the stack is loaded into the PC in the register mask. */
14577 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
14579 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
14581 /* We must use SP as the base register, because SP is one of the
14582 registers being restored. If an interrupt or page fault
14583 happens in the ldm instruction, the SP might or might not
14584 have been restored. That would be bad, as then SP will no
14585 longer indicate the safe area of stack, and we can get stack
14586 corruption. Using SP as the base register means that it will
14587 be reset correctly to the original value, should an interrupt
14588 occur. If the stack pointer already points at the right
14589 place, then omit the subtraction. */
14590 if (offsets
->outgoing_args
!= (1 + (int) bit_count (saved_regs_mask
))
14591 || cfun
->calls_alloca
)
14592 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", SP_REGNUM
, FP_REGNUM
,
14593 4 * bit_count (saved_regs_mask
));
14594 print_multi_reg (f
, "ldmfd\t%r, ", SP_REGNUM
, saved_regs_mask
, 0);
14596 if (IS_INTERRUPT (func_type
))
14597 /* Interrupt handlers will have pushed the
14598 IP onto the stack, so restore it now. */
14599 print_multi_reg (f
, "ldmfd\t%r!, ", SP_REGNUM
, 1 << IP_REGNUM
, 0);
14603 /* This branch is executed for ARM mode (non-apcs frames) and
14604 Thumb-2 mode. Frame layout is essentially the same for those
14605 cases, except that in ARM mode frame pointer points to the
14606 first saved register, while in Thumb-2 mode the frame pointer points
14607 to the last saved register.
14609 It is possible to make frame pointer point to last saved
14610 register in both cases, and remove some conditionals below.
14611 That means that fp setup in prologue would be just "mov fp, sp"
14612 and sp restore in epilogue would be just "mov sp, fp", whereas
14613 now we have to use add/sub in those cases. However, the value
14614 of that would be marginal, as both mov and add/sub are 32-bit
14615 in ARM mode, and it would require extra conditionals
14616 in arm_expand_prologue to distingish ARM-apcs-frame case
14617 (where frame pointer is required to point at first register)
14618 and ARM-non-apcs-frame. Therefore, such change is postponed
14619 until real need arise. */
14620 unsigned HOST_WIDE_INT amount
;
14622 /* Restore stack pointer if necessary. */
14623 if (TARGET_ARM
&& frame_pointer_needed
)
14625 operands
[0] = stack_pointer_rtx
;
14626 operands
[1] = hard_frame_pointer_rtx
;
14628 operands
[2] = GEN_INT (offsets
->frame
- offsets
->saved_regs
);
14629 output_add_immediate (operands
);
14633 if (frame_pointer_needed
)
14635 /* For Thumb-2 restore sp from the frame pointer.
14636 Operand restrictions mean we have to incrememnt FP, then copy
14638 amount
= offsets
->locals_base
- offsets
->saved_regs
;
14639 operands
[0] = hard_frame_pointer_rtx
;
14643 unsigned long count
;
14644 operands
[0] = stack_pointer_rtx
;
14645 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
14646 /* pop call clobbered registers if it avoids a
14647 separate stack adjustment. */
14648 count
= offsets
->saved_regs
- offsets
->saved_args
;
14651 && !crtl
->calls_eh_return
14652 && bit_count(saved_regs_mask
) * 4 == count
14653 && !IS_INTERRUPT (func_type
)
14654 && !crtl
->tail_call_emit
)
14656 unsigned long mask
;
14657 /* Preserve return values, of any size. */
14658 mask
= (1 << ((arm_size_return_regs() + 3) / 4)) - 1;
14660 mask
&= ~saved_regs_mask
;
14662 while (bit_count (mask
) * 4 > amount
)
14664 while ((mask
& (1 << reg
)) == 0)
14666 mask
&= ~(1 << reg
);
14668 if (bit_count (mask
) * 4 == amount
) {
14670 saved_regs_mask
|= mask
;
14677 operands
[1] = operands
[0];
14678 operands
[2] = GEN_INT (amount
);
14679 output_add_immediate (operands
);
14681 if (frame_pointer_needed
)
14682 asm_fprintf (f
, "\tmov\t%r, %r\n",
14683 SP_REGNUM
, HARD_FRAME_POINTER_REGNUM
);
14686 if (TARGET_FPA_EMU2
)
14688 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
14689 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
14690 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
14695 start_reg
= FIRST_FPA_REGNUM
;
14697 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
14699 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
14701 if (reg
- start_reg
== 3)
14703 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
14704 start_reg
, SP_REGNUM
);
14705 start_reg
= reg
+ 1;
14710 if (reg
!= start_reg
)
14711 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
14712 start_reg
, reg
- start_reg
,
14715 start_reg
= reg
+ 1;
14719 /* Just in case the last register checked also needs unstacking. */
14720 if (reg
!= start_reg
)
14721 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
14722 start_reg
, reg
- start_reg
, SP_REGNUM
);
14725 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
14727 int end_reg
= LAST_VFP_REGNUM
+ 1;
14729 /* Scan the registers in reverse order. We need to match
14730 any groupings made in the prologue and generate matching
14732 for (reg
= LAST_VFP_REGNUM
- 1; reg
>= FIRST_VFP_REGNUM
; reg
-= 2)
14734 if ((!df_regs_ever_live_p (reg
) || call_used_regs
[reg
])
14735 && (!df_regs_ever_live_p (reg
+ 1)
14736 || call_used_regs
[reg
+ 1]))
14738 if (end_reg
> reg
+ 2)
14739 vfp_output_fldmd (f
, SP_REGNUM
,
14740 (reg
+ 2 - FIRST_VFP_REGNUM
) / 2,
14741 (end_reg
- (reg
+ 2)) / 2);
14745 if (end_reg
> reg
+ 2)
14746 vfp_output_fldmd (f
, SP_REGNUM
, 0,
14747 (end_reg
- (reg
+ 2)) / 2);
14751 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
14752 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
14753 asm_fprintf (f
, "\twldrd\t%r, [%r], #8\n", reg
, SP_REGNUM
);
14755 /* If we can, restore the LR into the PC. */
14756 if (ARM_FUNC_TYPE (func_type
) != ARM_FT_INTERWORKED
14757 && (TARGET_ARM
|| ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
)
14758 && !IS_STACKALIGN (func_type
)
14760 && crtl
->args
.pretend_args_size
== 0
14761 && saved_regs_mask
& (1 << LR_REGNUM
)
14762 && !crtl
->calls_eh_return
)
14764 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
14765 saved_regs_mask
|= (1 << PC_REGNUM
);
14766 rfe
= IS_INTERRUPT (func_type
);
14771 /* Load the registers off the stack. If we only have one register
14772 to load use the LDR instruction - it is faster. For Thumb-2
14773 always use pop and the assembler will pick the best instruction.*/
14774 if (TARGET_ARM
&& saved_regs_mask
== (1 << LR_REGNUM
)
14775 && !IS_INTERRUPT(func_type
))
14777 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
14779 else if (saved_regs_mask
)
14781 if (saved_regs_mask
& (1 << SP_REGNUM
))
14782 /* Note - write back to the stack register is not enabled
14783 (i.e. "ldmfd sp!..."). We know that the stack pointer is
14784 in the list of registers and if we add writeback the
14785 instruction becomes UNPREDICTABLE. */
14786 print_multi_reg (f
, "ldmfd\t%r, ", SP_REGNUM
, saved_regs_mask
,
14788 else if (TARGET_ARM
)
14789 print_multi_reg (f
, "ldmfd\t%r!, ", SP_REGNUM
, saved_regs_mask
,
14792 print_multi_reg (f
, "pop\t", SP_REGNUM
, saved_regs_mask
, 0);
14795 if (crtl
->args
.pretend_args_size
)
14797 /* Unwind the pre-pushed regs. */
14798 operands
[0] = operands
[1] = stack_pointer_rtx
;
14799 operands
[2] = GEN_INT (crtl
->args
.pretend_args_size
);
14800 output_add_immediate (operands
);
14804 /* We may have already restored PC directly from the stack. */
14805 if (!really_return
|| saved_regs_mask
& (1 << PC_REGNUM
))
14808 /* Stack adjustment for exception handler. */
14809 if (crtl
->calls_eh_return
)
14810 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
14811 ARM_EH_STACKADJ_REGNUM
);
14813 /* Generate the return instruction. */
14814 switch ((int) ARM_FUNC_TYPE (func_type
))
14818 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
14821 case ARM_FT_EXCEPTION
:
14822 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
14825 case ARM_FT_INTERWORKED
:
14826 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
14830 if (IS_STACKALIGN (func_type
))
14832 /* See comment in arm_expand_prologue. */
14833 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, 0);
14835 if (arm_arch5
|| arm_arch4t
)
14836 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
14838 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
14846 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
14847 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED
)
14849 arm_stack_offsets
*offsets
;
14855 /* Emit any call-via-reg trampolines that are needed for v4t support
14856 of call_reg and call_value_reg type insns. */
14857 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
14859 rtx label
= cfun
->machine
->call_via
[regno
];
14863 switch_to_section (function_section (current_function_decl
));
14864 targetm
.asm_out
.internal_label (asm_out_file
, "L",
14865 CODE_LABEL_NUMBER (label
));
14866 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
14870 /* ??? Probably not safe to set this here, since it assumes that a
14871 function will be emitted as assembly immediately after we generate
14872 RTL for it. This does not happen for inline functions. */
14873 cfun
->machine
->return_used_this_function
= 0;
14875 else /* TARGET_32BIT */
14877 /* We need to take into account any stack-frame rounding. */
14878 offsets
= arm_get_frame_offsets ();
14880 gcc_assert (!use_return_insn (FALSE
, NULL
)
14881 || (cfun
->machine
->return_used_this_function
!= 0)
14882 || offsets
->saved_regs
== offsets
->outgoing_args
14883 || frame_pointer_needed
);
14885 /* Reset the ARM-specific per-function variables. */
14886 after_arm_reorg
= 0;
14890 /* Generate and emit an insn that we will recognize as a push_multi.
14891 Unfortunately, since this insn does not reflect very well the actual
14892 semantics of the operation, we need to annotate the insn for the benefit
14893 of DWARF2 frame unwind information. */
14895 emit_multi_reg_push (unsigned long mask
)
14898 int num_dwarf_regs
;
14902 int dwarf_par_index
;
14905 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
14906 if (mask
& (1 << i
))
14909 gcc_assert (num_regs
&& num_regs
<= 16);
14911 /* We don't record the PC in the dwarf frame information. */
14912 num_dwarf_regs
= num_regs
;
14913 if (mask
& (1 << PC_REGNUM
))
14916 /* For the body of the insn we are going to generate an UNSPEC in
14917 parallel with several USEs. This allows the insn to be recognized
14918 by the push_multi pattern in the arm.md file.
14920 The body of the insn looks something like this:
14923 (set (mem:BLK (pre_modify:SI (reg:SI sp)
14924 (const_int:SI <num>)))
14925 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
14931 For the frame note however, we try to be more explicit and actually
14932 show each register being stored into the stack frame, plus a (single)
14933 decrement of the stack pointer. We do it this way in order to be
14934 friendly to the stack unwinding code, which only wants to see a single
14935 stack decrement per instruction. The RTL we generate for the note looks
14936 something like this:
14939 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
14940 (set (mem:SI (reg:SI sp)) (reg:SI r4))
14941 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI XX))
14942 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI YY))
14946 FIXME:: In an ideal world the PRE_MODIFY would not exist and
14947 instead we'd have a parallel expression detailing all
14948 the stores to the various memory addresses so that debug
14949 information is more up-to-date. Remember however while writing
14950 this to take care of the constraints with the push instruction.
14952 Note also that this has to be taken care of for the VFP registers.
14954 For more see PR43399. */
14956 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
14957 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
14958 dwarf_par_index
= 1;
14960 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
14962 if (mask
& (1 << i
))
14964 reg
= gen_rtx_REG (SImode
, i
);
14966 XVECEXP (par
, 0, 0)
14967 = gen_rtx_SET (VOIDmode
,
14970 gen_rtx_PRE_MODIFY (Pmode
,
14973 (stack_pointer_rtx
,
14976 gen_rtx_UNSPEC (BLKmode
,
14977 gen_rtvec (1, reg
),
14978 UNSPEC_PUSH_MULT
));
14980 if (i
!= PC_REGNUM
)
14982 tmp
= gen_rtx_SET (VOIDmode
,
14983 gen_frame_mem (SImode
, stack_pointer_rtx
),
14985 RTX_FRAME_RELATED_P (tmp
) = 1;
14986 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
14994 for (j
= 1, i
++; j
< num_regs
; i
++)
14996 if (mask
& (1 << i
))
14998 reg
= gen_rtx_REG (SImode
, i
);
15000 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
15002 if (i
!= PC_REGNUM
)
15005 = gen_rtx_SET (VOIDmode
,
15008 plus_constant (stack_pointer_rtx
,
15011 RTX_FRAME_RELATED_P (tmp
) = 1;
15012 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
15019 par
= emit_insn (par
);
15021 tmp
= gen_rtx_SET (VOIDmode
,
15023 plus_constant (stack_pointer_rtx
, -4 * num_regs
));
15024 RTX_FRAME_RELATED_P (tmp
) = 1;
15025 XVECEXP (dwarf
, 0, 0) = tmp
;
15027 add_reg_note (par
, REG_FRAME_RELATED_EXPR
, dwarf
);
15032 /* Calculate the size of the return value that is passed in registers. */
15034 arm_size_return_regs (void)
15036 enum machine_mode mode
;
15038 if (crtl
->return_rtx
!= 0)
15039 mode
= GET_MODE (crtl
->return_rtx
);
15041 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
15043 return GET_MODE_SIZE (mode
);
15047 emit_sfm (int base_reg
, int count
)
15054 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
15055 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
15057 reg
= gen_rtx_REG (XFmode
, base_reg
++);
15059 XVECEXP (par
, 0, 0)
15060 = gen_rtx_SET (VOIDmode
,
15063 gen_rtx_PRE_MODIFY (Pmode
,
15066 (stack_pointer_rtx
,
15069 gen_rtx_UNSPEC (BLKmode
,
15070 gen_rtvec (1, reg
),
15071 UNSPEC_PUSH_MULT
));
15072 tmp
= gen_rtx_SET (VOIDmode
,
15073 gen_frame_mem (XFmode
, stack_pointer_rtx
), reg
);
15074 RTX_FRAME_RELATED_P (tmp
) = 1;
15075 XVECEXP (dwarf
, 0, 1) = tmp
;
15077 for (i
= 1; i
< count
; i
++)
15079 reg
= gen_rtx_REG (XFmode
, base_reg
++);
15080 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
15082 tmp
= gen_rtx_SET (VOIDmode
,
15083 gen_frame_mem (XFmode
,
15084 plus_constant (stack_pointer_rtx
,
15087 RTX_FRAME_RELATED_P (tmp
) = 1;
15088 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
15091 tmp
= gen_rtx_SET (VOIDmode
,
15093 plus_constant (stack_pointer_rtx
, -12 * count
));
15095 RTX_FRAME_RELATED_P (tmp
) = 1;
15096 XVECEXP (dwarf
, 0, 0) = tmp
;
15098 par
= emit_insn (par
);
15099 add_reg_note (par
, REG_FRAME_RELATED_EXPR
, dwarf
);
15105 /* Return true if the current function needs to save/restore LR. */
15108 thumb_force_lr_save (void)
15110 return !cfun
->machine
->lr_save_eliminated
15111 && (!leaf_function_p ()
15112 || thumb_far_jump_used_p ()
15113 || df_regs_ever_live_p (LR_REGNUM
));
15117 /* Return true if r3 is used by any of the tail call insns in the
15118 current function. */
15121 any_sibcall_uses_r3 (void)
15126 if (!crtl
->tail_call_emit
)
15128 FOR_EACH_EDGE (e
, ei
, EXIT_BLOCK_PTR
->preds
)
15129 if (e
->flags
& EDGE_SIBCALL
)
15131 rtx call
= BB_END (e
->src
);
15132 if (!CALL_P (call
))
15133 call
= prev_nonnote_nondebug_insn (call
);
15134 gcc_assert (CALL_P (call
) && SIBLING_CALL_P (call
));
15135 if (find_regno_fusage (call
, USE
, 3))
15142 /* Compute the distance from register FROM to register TO.
15143 These can be the arg pointer (26), the soft frame pointer (25),
15144 the stack pointer (13) or the hard frame pointer (11).
15145 In thumb mode r7 is used as the soft frame pointer, if needed.
15146 Typical stack layout looks like this:
15148 old stack pointer -> | |
15151 | | saved arguments for
15152 | | vararg functions
15155 hard FP & arg pointer -> | | \
15163 soft frame pointer -> | | /
15168 locals base pointer -> | | /
15173 current stack pointer -> | | /
15176 For a given function some or all of these stack components
15177 may not be needed, giving rise to the possibility of
15178 eliminating some of the registers.
15180 The values returned by this function must reflect the behavior
15181 of arm_expand_prologue() and arm_compute_save_reg_mask().
15183 The sign of the number returned reflects the direction of stack
15184 growth, so the values are positive for all eliminations except
15185 from the soft frame pointer to the hard frame pointer.
15187 SFP may point just inside the local variables block to ensure correct
15191 /* Calculate stack offsets. These are used to calculate register elimination
15192 offsets and in prologue/epilogue code. Also calculates which registers
15193 should be saved. */
15195 static arm_stack_offsets
*
15196 arm_get_frame_offsets (void)
15198 struct arm_stack_offsets
*offsets
;
15199 unsigned long func_type
;
15203 HOST_WIDE_INT frame_size
;
15206 offsets
= &cfun
->machine
->stack_offsets
;
15208 /* We need to know if we are a leaf function. Unfortunately, it
15209 is possible to be called after start_sequence has been called,
15210 which causes get_insns to return the insns for the sequence,
15211 not the function, which will cause leaf_function_p to return
15212 the incorrect result.
15214 to know about leaf functions once reload has completed, and the
15215 frame size cannot be changed after that time, so we can safely
15216 use the cached value. */
15218 if (reload_completed
)
15221 /* Initially this is the size of the local variables. It will translated
15222 into an offset once we have determined the size of preceding data. */
15223 frame_size
= ROUND_UP_WORD (get_frame_size ());
15225 leaf
= leaf_function_p ();
15227 /* Space for variadic functions. */
15228 offsets
->saved_args
= crtl
->args
.pretend_args_size
;
15230 /* In Thumb mode this is incorrect, but never used. */
15231 offsets
->frame
= offsets
->saved_args
+ (frame_pointer_needed
? 4 : 0) +
15232 arm_compute_static_chain_stack_bytes();
15236 unsigned int regno
;
15238 offsets
->saved_regs_mask
= arm_compute_save_reg_mask ();
15239 core_saved
= bit_count (offsets
->saved_regs_mask
) * 4;
15240 saved
= core_saved
;
15242 /* We know that SP will be doubleword aligned on entry, and we must
15243 preserve that condition at any subroutine call. We also require the
15244 soft frame pointer to be doubleword aligned. */
15246 if (TARGET_REALLY_IWMMXT
)
15248 /* Check for the call-saved iWMMXt registers. */
15249 for (regno
= FIRST_IWMMXT_REGNUM
;
15250 regno
<= LAST_IWMMXT_REGNUM
;
15252 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
15256 func_type
= arm_current_func_type ();
15257 if (! IS_VOLATILE (func_type
))
15259 /* Space for saved FPA registers. */
15260 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
15261 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
15264 /* Space for saved VFP registers. */
15265 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
15266 saved
+= arm_get_vfp_saved_size ();
15269 else /* TARGET_THUMB1 */
15271 offsets
->saved_regs_mask
= thumb1_compute_save_reg_mask ();
15272 core_saved
= bit_count (offsets
->saved_regs_mask
) * 4;
15273 saved
= core_saved
;
15274 if (TARGET_BACKTRACE
)
15278 /* Saved registers include the stack frame. */
15279 offsets
->saved_regs
= offsets
->saved_args
+ saved
+
15280 arm_compute_static_chain_stack_bytes();
15281 offsets
->soft_frame
= offsets
->saved_regs
+ CALLER_INTERWORKING_SLOT_SIZE
;
15282 /* A leaf function does not need any stack alignment if it has nothing
15284 if (leaf
&& frame_size
== 0
15285 /* However if it calls alloca(), we have a dynamically allocated
15286 block of BIGGEST_ALIGNMENT on stack, so still do stack alignment. */
15287 && ! cfun
->calls_alloca
)
15289 offsets
->outgoing_args
= offsets
->soft_frame
;
15290 offsets
->locals_base
= offsets
->soft_frame
;
15294 /* Ensure SFP has the correct alignment. */
15295 if (ARM_DOUBLEWORD_ALIGN
15296 && (offsets
->soft_frame
& 7))
15298 offsets
->soft_frame
+= 4;
15299 /* Try to align stack by pushing an extra reg. Don't bother doing this
15300 when there is a stack frame as the alignment will be rolled into
15301 the normal stack adjustment. */
15302 if (frame_size
+ crtl
->outgoing_args_size
== 0)
15306 /* If it is safe to use r3, then do so. This sometimes
15307 generates better code on Thumb-2 by avoiding the need to
15308 use 32-bit push/pop instructions. */
15309 if (! any_sibcall_uses_r3 ()
15310 && arm_size_return_regs () <= 12
15311 && (offsets
->saved_regs_mask
& (1 << 3)) == 0)
15316 for (i
= 4; i
<= (TARGET_THUMB1
? LAST_LO_REGNUM
: 11); i
++)
15318 if ((offsets
->saved_regs_mask
& (1 << i
)) == 0)
15327 offsets
->saved_regs
+= 4;
15328 offsets
->saved_regs_mask
|= (1 << reg
);
15333 offsets
->locals_base
= offsets
->soft_frame
+ frame_size
;
15334 offsets
->outgoing_args
= (offsets
->locals_base
15335 + crtl
->outgoing_args_size
);
15337 if (ARM_DOUBLEWORD_ALIGN
)
15339 /* Ensure SP remains doubleword aligned. */
15340 if (offsets
->outgoing_args
& 7)
15341 offsets
->outgoing_args
+= 4;
15342 gcc_assert (!(offsets
->outgoing_args
& 7));
15349 /* Calculate the relative offsets for the different stack pointers. Positive
15350 offsets are in the direction of stack growth. */
15353 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
15355 arm_stack_offsets
*offsets
;
15357 offsets
= arm_get_frame_offsets ();
15359 /* OK, now we have enough information to compute the distances.
15360 There must be an entry in these switch tables for each pair
15361 of registers in ELIMINABLE_REGS, even if some of the entries
15362 seem to be redundant or useless. */
15365 case ARG_POINTER_REGNUM
:
15368 case THUMB_HARD_FRAME_POINTER_REGNUM
:
15371 case FRAME_POINTER_REGNUM
:
15372 /* This is the reverse of the soft frame pointer
15373 to hard frame pointer elimination below. */
15374 return offsets
->soft_frame
- offsets
->saved_args
;
15376 case ARM_HARD_FRAME_POINTER_REGNUM
:
15377 /* This is only non-zero in the case where the static chain register
15378 is stored above the frame. */
15379 return offsets
->frame
- offsets
->saved_args
- 4;
15381 case STACK_POINTER_REGNUM
:
15382 /* If nothing has been pushed on the stack at all
15383 then this will return -4. This *is* correct! */
15384 return offsets
->outgoing_args
- (offsets
->saved_args
+ 4);
15387 gcc_unreachable ();
15389 gcc_unreachable ();
15391 case FRAME_POINTER_REGNUM
:
15394 case THUMB_HARD_FRAME_POINTER_REGNUM
:
15397 case ARM_HARD_FRAME_POINTER_REGNUM
:
15398 /* The hard frame pointer points to the top entry in the
15399 stack frame. The soft frame pointer to the bottom entry
15400 in the stack frame. If there is no stack frame at all,
15401 then they are identical. */
15403 return offsets
->frame
- offsets
->soft_frame
;
15405 case STACK_POINTER_REGNUM
:
15406 return offsets
->outgoing_args
- offsets
->soft_frame
;
15409 gcc_unreachable ();
15411 gcc_unreachable ();
15414 /* You cannot eliminate from the stack pointer.
15415 In theory you could eliminate from the hard frame
15416 pointer to the stack pointer, but this will never
15417 happen, since if a stack frame is not needed the
15418 hard frame pointer will never be used. */
15419 gcc_unreachable ();
15423 /* Given FROM and TO register numbers, say whether this elimination is
15424 allowed. Frame pointer elimination is automatically handled.
15426 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
15427 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
15428 pointer, we must eliminate FRAME_POINTER_REGNUM into
15429 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
15430 ARG_POINTER_REGNUM. */
15433 arm_can_eliminate (const int from
, const int to
)
15435 return ((to
== FRAME_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
) ? false :
15436 (to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
) ? false :
15437 (to
== ARM_HARD_FRAME_POINTER_REGNUM
&& TARGET_THUMB
) ? false :
15438 (to
== THUMB_HARD_FRAME_POINTER_REGNUM
&& TARGET_ARM
) ? false :
15442 /* Emit RTL to save coprocessor registers on function entry. Returns the
15443 number of bytes pushed. */
15446 arm_save_coproc_regs(void)
15448 int saved_size
= 0;
15450 unsigned start_reg
;
15453 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
15454 if (df_regs_ever_live_p (reg
) && ! call_used_regs
[reg
])
15456 insn
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
15457 insn
= gen_rtx_MEM (V2SImode
, insn
);
15458 insn
= emit_set_insn (insn
, gen_rtx_REG (V2SImode
, reg
));
15459 RTX_FRAME_RELATED_P (insn
) = 1;
15463 /* Save any floating point call-saved registers used by this
15465 if (TARGET_FPA_EMU2
)
15467 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
15468 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
15470 insn
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
15471 insn
= gen_rtx_MEM (XFmode
, insn
);
15472 insn
= emit_set_insn (insn
, gen_rtx_REG (XFmode
, reg
));
15473 RTX_FRAME_RELATED_P (insn
) = 1;
15479 start_reg
= LAST_FPA_REGNUM
;
15481 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
15483 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
15485 if (start_reg
- reg
== 3)
15487 insn
= emit_sfm (reg
, 4);
15488 RTX_FRAME_RELATED_P (insn
) = 1;
15490 start_reg
= reg
- 1;
15495 if (start_reg
!= reg
)
15497 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
15498 RTX_FRAME_RELATED_P (insn
) = 1;
15499 saved_size
+= (start_reg
- reg
) * 12;
15501 start_reg
= reg
- 1;
15505 if (start_reg
!= reg
)
15507 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
15508 saved_size
+= (start_reg
- reg
) * 12;
15509 RTX_FRAME_RELATED_P (insn
) = 1;
15512 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
15514 start_reg
= FIRST_VFP_REGNUM
;
15516 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
15518 if ((!df_regs_ever_live_p (reg
) || call_used_regs
[reg
])
15519 && (!df_regs_ever_live_p (reg
+ 1) || call_used_regs
[reg
+ 1]))
15521 if (start_reg
!= reg
)
15522 saved_size
+= vfp_emit_fstmd (start_reg
,
15523 (reg
- start_reg
) / 2);
15524 start_reg
= reg
+ 2;
15527 if (start_reg
!= reg
)
15528 saved_size
+= vfp_emit_fstmd (start_reg
,
15529 (reg
- start_reg
) / 2);
15535 /* Set the Thumb frame pointer from the stack pointer. */
15538 thumb_set_frame_pointer (arm_stack_offsets
*offsets
)
15540 HOST_WIDE_INT amount
;
15543 amount
= offsets
->outgoing_args
- offsets
->locals_base
;
15545 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
15546 stack_pointer_rtx
, GEN_INT (amount
)));
15549 emit_insn (gen_movsi (hard_frame_pointer_rtx
, GEN_INT (amount
)));
15550 /* Thumb-2 RTL patterns expect sp as the first input. Thumb-1
15551 expects the first two operands to be the same. */
15554 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
15556 hard_frame_pointer_rtx
));
15560 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
15561 hard_frame_pointer_rtx
,
15562 stack_pointer_rtx
));
15564 dwarf
= gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
15565 plus_constant (stack_pointer_rtx
, amount
));
15566 RTX_FRAME_RELATED_P (dwarf
) = 1;
15567 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
15570 RTX_FRAME_RELATED_P (insn
) = 1;
15573 /* Generate the prologue instructions for entry into an ARM or Thumb-2
15576 arm_expand_prologue (void)
15581 unsigned long live_regs_mask
;
15582 unsigned long func_type
;
15584 int saved_pretend_args
= 0;
15585 int saved_regs
= 0;
15586 unsigned HOST_WIDE_INT args_to_push
;
15587 arm_stack_offsets
*offsets
;
15589 func_type
= arm_current_func_type ();
15591 /* Naked functions don't have prologues. */
15592 if (IS_NAKED (func_type
))
15595 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
15596 args_to_push
= crtl
->args
.pretend_args_size
;
15598 /* Compute which register we will have to save onto the stack. */
15599 offsets
= arm_get_frame_offsets ();
15600 live_regs_mask
= offsets
->saved_regs_mask
;
15602 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
15604 if (IS_STACKALIGN (func_type
))
15609 /* Handle a word-aligned stack pointer. We generate the following:
15614 <save and restore r0 in normal prologue/epilogue>
15618 The unwinder doesn't need to know about the stack realignment.
15619 Just tell it we saved SP in r0. */
15620 gcc_assert (TARGET_THUMB2
&& !arm_arch_notm
&& args_to_push
== 0);
15622 r0
= gen_rtx_REG (SImode
, 0);
15623 r1
= gen_rtx_REG (SImode
, 1);
15624 /* Use a real rtvec rather than NULL_RTVEC so the rest of the
15625 compiler won't choke. */
15626 dwarf
= gen_rtx_UNSPEC (SImode
, rtvec_alloc (0), UNSPEC_STACK_ALIGN
);
15627 dwarf
= gen_rtx_SET (VOIDmode
, r0
, dwarf
);
15628 insn
= gen_movsi (r0
, stack_pointer_rtx
);
15629 RTX_FRAME_RELATED_P (insn
) = 1;
15630 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
15632 emit_insn (gen_andsi3 (r1
, r0
, GEN_INT (~(HOST_WIDE_INT
)7)));
15633 emit_insn (gen_movsi (stack_pointer_rtx
, r1
));
15636 /* For APCS frames, if IP register is clobbered
15637 when creating frame, save that register in a special
15639 if (TARGET_APCS_FRAME
&& frame_pointer_needed
&& TARGET_ARM
)
15641 if (IS_INTERRUPT (func_type
))
15643 /* Interrupt functions must not corrupt any registers.
15644 Creating a frame pointer however, corrupts the IP
15645 register, so we must push it first. */
15646 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
15648 /* Do not set RTX_FRAME_RELATED_P on this insn.
15649 The dwarf stack unwinding code only wants to see one
15650 stack decrement per function, and this is not it. If
15651 this instruction is labeled as being part of the frame
15652 creation sequence then dwarf2out_frame_debug_expr will
15653 die when it encounters the assignment of IP to FP
15654 later on, since the use of SP here establishes SP as
15655 the CFA register and not IP.
15657 Anyway this instruction is not really part of the stack
15658 frame creation although it is part of the prologue. */
15660 else if (IS_NESTED (func_type
))
15662 /* The Static chain register is the same as the IP register
15663 used as a scratch register during stack frame creation.
15664 To get around this need to find somewhere to store IP
15665 whilst the frame is being created. We try the following
15668 1. The last argument register.
15669 2. A slot on the stack above the frame. (This only
15670 works if the function is not a varargs function).
15671 3. Register r3, after pushing the argument registers
15674 Note - we only need to tell the dwarf2 backend about the SP
15675 adjustment in the second variant; the static chain register
15676 doesn't need to be unwound, as it doesn't contain a value
15677 inherited from the caller. */
15679 if (df_regs_ever_live_p (3) == false)
15680 insn
= emit_set_insn (gen_rtx_REG (SImode
, 3), ip_rtx
);
15681 else if (args_to_push
== 0)
15685 gcc_assert(arm_compute_static_chain_stack_bytes() == 4);
15688 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
15689 insn
= emit_set_insn (gen_frame_mem (SImode
, insn
), ip_rtx
);
15692 /* Just tell the dwarf backend that we adjusted SP. */
15693 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
15694 plus_constant (stack_pointer_rtx
,
15696 RTX_FRAME_RELATED_P (insn
) = 1;
15697 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
15701 /* Store the args on the stack. */
15702 if (cfun
->machine
->uses_anonymous_args
)
15703 insn
= emit_multi_reg_push
15704 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
15707 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
15708 GEN_INT (- args_to_push
)));
15710 RTX_FRAME_RELATED_P (insn
) = 1;
15712 saved_pretend_args
= 1;
15713 fp_offset
= args_to_push
;
15716 /* Now reuse r3 to preserve IP. */
15717 emit_set_insn (gen_rtx_REG (SImode
, 3), ip_rtx
);
15721 insn
= emit_set_insn (ip_rtx
,
15722 plus_constant (stack_pointer_rtx
, fp_offset
));
15723 RTX_FRAME_RELATED_P (insn
) = 1;
15728 /* Push the argument registers, or reserve space for them. */
15729 if (cfun
->machine
->uses_anonymous_args
)
15730 insn
= emit_multi_reg_push
15731 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
15734 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
15735 GEN_INT (- args_to_push
)));
15736 RTX_FRAME_RELATED_P (insn
) = 1;
15739 /* If this is an interrupt service routine, and the link register
15740 is going to be pushed, and we're not generating extra
15741 push of IP (needed when frame is needed and frame layout if apcs),
15742 subtracting four from LR now will mean that the function return
15743 can be done with a single instruction. */
15744 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
15745 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
15746 && !(frame_pointer_needed
&& TARGET_APCS_FRAME
)
15749 rtx lr
= gen_rtx_REG (SImode
, LR_REGNUM
);
15751 emit_set_insn (lr
, plus_constant (lr
, -4));
15754 if (live_regs_mask
)
15756 saved_regs
+= bit_count (live_regs_mask
) * 4;
15757 if (optimize_size
&& !frame_pointer_needed
15758 && saved_regs
== offsets
->saved_regs
- offsets
->saved_args
)
15760 /* If no coprocessor registers are being pushed and we don't have
15761 to worry about a frame pointer then push extra registers to
15762 create the stack frame. This is done is a way that does not
15763 alter the frame layout, so is independent of the epilogue. */
15767 while (n
< 8 && (live_regs_mask
& (1 << n
)) == 0)
15769 frame
= offsets
->outgoing_args
- (offsets
->saved_args
+ saved_regs
);
15770 if (frame
&& n
* 4 >= frame
)
15773 live_regs_mask
|= (1 << n
) - 1;
15774 saved_regs
+= frame
;
15777 insn
= emit_multi_reg_push (live_regs_mask
);
15778 RTX_FRAME_RELATED_P (insn
) = 1;
15781 if (! IS_VOLATILE (func_type
))
15782 saved_regs
+= arm_save_coproc_regs ();
15784 if (frame_pointer_needed
&& TARGET_ARM
)
15786 /* Create the new frame pointer. */
15787 if (TARGET_APCS_FRAME
)
15789 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
15790 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
15791 RTX_FRAME_RELATED_P (insn
) = 1;
15793 if (IS_NESTED (func_type
))
15795 /* Recover the static chain register. */
15796 if (!df_regs_ever_live_p (3)
15797 || saved_pretend_args
)
15798 insn
= gen_rtx_REG (SImode
, 3);
15799 else /* if (crtl->args.pretend_args_size == 0) */
15801 insn
= plus_constant (hard_frame_pointer_rtx
, 4);
15802 insn
= gen_frame_mem (SImode
, insn
);
15804 emit_set_insn (ip_rtx
, insn
);
15805 /* Add a USE to stop propagate_one_insn() from barfing. */
15806 emit_insn (gen_prologue_use (ip_rtx
));
15811 insn
= GEN_INT (saved_regs
- 4);
15812 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
15813 stack_pointer_rtx
, insn
));
15814 RTX_FRAME_RELATED_P (insn
) = 1;
15818 if (flag_stack_usage_info
)
15819 current_function_static_stack_size
15820 = offsets
->outgoing_args
- offsets
->saved_args
;
15822 if (offsets
->outgoing_args
!= offsets
->saved_args
+ saved_regs
)
15824 /* This add can produce multiple insns for a large constant, so we
15825 need to get tricky. */
15826 rtx last
= get_last_insn ();
15828 amount
= GEN_INT (offsets
->saved_args
+ saved_regs
15829 - offsets
->outgoing_args
);
15831 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
15835 last
= last
? NEXT_INSN (last
) : get_insns ();
15836 RTX_FRAME_RELATED_P (last
) = 1;
15838 while (last
!= insn
);
15840 /* If the frame pointer is needed, emit a special barrier that
15841 will prevent the scheduler from moving stores to the frame
15842 before the stack adjustment. */
15843 if (frame_pointer_needed
)
15844 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
15845 hard_frame_pointer_rtx
));
15849 if (frame_pointer_needed
&& TARGET_THUMB2
)
15850 thumb_set_frame_pointer (offsets
);
15852 if (flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
15854 unsigned long mask
;
15856 mask
= live_regs_mask
;
15857 mask
&= THUMB2_WORK_REGS
;
15858 if (!IS_NESTED (func_type
))
15859 mask
|= (1 << IP_REGNUM
);
15860 arm_load_pic_register (mask
);
15863 /* If we are profiling, make sure no instructions are scheduled before
15864 the call to mcount. Similarly if the user has requested no
15865 scheduling in the prolog. Similarly if we want non-call exceptions
15866 using the EABI unwinder, to prevent faulting instructions from being
15867 swapped with a stack adjustment. */
15868 if (crtl
->profile
|| !TARGET_SCHED_PROLOG
15869 || (arm_except_unwind_info (&global_options
) == UI_TARGET
15870 && cfun
->can_throw_non_call_exceptions
))
15871 emit_insn (gen_blockage ());
15873 /* If the link register is being kept alive, with the return address in it,
15874 then make sure that it does not get reused by the ce2 pass. */
15875 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
15876 cfun
->machine
->lr_save_eliminated
= 1;
15879 /* Print condition code to STREAM. Helper function for arm_print_operand. */
15881 arm_print_condition (FILE *stream
)
15883 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
15885 /* Branch conversion is not implemented for Thumb-2. */
15888 output_operand_lossage ("predicated Thumb instruction");
15891 if (current_insn_predicate
!= NULL
)
15893 output_operand_lossage
15894 ("predicated instruction in conditional sequence");
15898 fputs (arm_condition_codes
[arm_current_cc
], stream
);
15900 else if (current_insn_predicate
)
15902 enum arm_cond_code code
;
15906 output_operand_lossage ("predicated Thumb instruction");
15910 code
= get_arm_condition_code (current_insn_predicate
);
15911 fputs (arm_condition_codes
[code
], stream
);
15916 /* If CODE is 'd', then the X is a condition operand and the instruction
15917 should only be executed if the condition is true.
15918 if CODE is 'D', then the X is a condition operand and the instruction
15919 should only be executed if the condition is false: however, if the mode
15920 of the comparison is CCFPEmode, then always execute the instruction -- we
15921 do this because in these circumstances !GE does not necessarily imply LT;
15922 in these cases the instruction pattern will take care to make sure that
15923 an instruction containing %d will follow, thereby undoing the effects of
15924 doing this instruction unconditionally.
15925 If CODE is 'N' then X is a floating point operand that must be negated
15927 If CODE is 'B' then output a bitwise inverted value of X (a const int).
15928 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
15930 arm_print_operand (FILE *stream
, rtx x
, int code
)
15935 fputs (ASM_COMMENT_START
, stream
);
15939 fputs (user_label_prefix
, stream
);
15943 fputs (REGISTER_PREFIX
, stream
);
15947 arm_print_condition (stream
);
15951 /* Nothing in unified syntax, otherwise the current condition code. */
15952 if (!TARGET_UNIFIED_ASM
)
15953 arm_print_condition (stream
);
15957 /* The current condition code in unified syntax, otherwise nothing. */
15958 if (TARGET_UNIFIED_ASM
)
15959 arm_print_condition (stream
);
15963 /* The current condition code for a condition code setting instruction.
15964 Preceded by 's' in unified syntax, otherwise followed by 's'. */
15965 if (TARGET_UNIFIED_ASM
)
15967 fputc('s', stream
);
15968 arm_print_condition (stream
);
15972 arm_print_condition (stream
);
15973 fputc('s', stream
);
15978 /* If the instruction is conditionally executed then print
15979 the current condition code, otherwise print 's'. */
15980 gcc_assert (TARGET_THUMB2
&& TARGET_UNIFIED_ASM
);
15981 if (current_insn_predicate
)
15982 arm_print_condition (stream
);
15984 fputc('s', stream
);
15987 /* %# is a "break" sequence. It doesn't output anything, but is used to
15988 separate e.g. operand numbers from following text, if that text consists
15989 of further digits which we don't want to be part of the operand
15997 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
15998 r
= real_value_negate (&r
);
15999 fprintf (stream
, "%s", fp_const_from_val (&r
));
16003 /* An integer or symbol address without a preceding # sign. */
16005 switch (GET_CODE (x
))
16008 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
16012 output_addr_const (stream
, x
);
16016 gcc_unreachable ();
16021 if (GET_CODE (x
) == CONST_INT
)
16024 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
16025 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
16029 putc ('~', stream
);
16030 output_addr_const (stream
, x
);
16035 /* The low 16 bits of an immediate constant. */
16036 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL(x
) & 0xffff);
16040 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
16043 /* Truncate Cirrus shift counts. */
16045 if (GET_CODE (x
) == CONST_INT
)
16047 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
16050 arm_print_operand (stream
, x
, 0);
16054 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
16062 if (!shift_operator (x
, SImode
))
16064 output_operand_lossage ("invalid shift operand");
16068 shift
= shift_op (x
, &val
);
16072 fprintf (stream
, ", %s ", shift
);
16074 arm_print_operand (stream
, XEXP (x
, 1), 0);
16076 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
16081 /* An explanation of the 'Q', 'R' and 'H' register operands:
16083 In a pair of registers containing a DI or DF value the 'Q'
16084 operand returns the register number of the register containing
16085 the least significant part of the value. The 'R' operand returns
16086 the register number of the register containing the most
16087 significant part of the value.
16089 The 'H' operand returns the higher of the two register numbers.
16090 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
16091 same as the 'Q' operand, since the most significant part of the
16092 value is held in the lower number register. The reverse is true
16093 on systems where WORDS_BIG_ENDIAN is false.
16095 The purpose of these operands is to distinguish between cases
16096 where the endian-ness of the values is important (for example
16097 when they are added together), and cases where the endian-ness
16098 is irrelevant, but the order of register operations is important.
16099 For example when loading a value from memory into a register
16100 pair, the endian-ness does not matter. Provided that the value
16101 from the lower memory address is put into the lower numbered
16102 register, and the value from the higher address is put into the
16103 higher numbered register, the load will work regardless of whether
16104 the value being loaded is big-wordian or little-wordian. The
16105 order of the two register loads can matter however, if the address
16106 of the memory location is actually held in one of the registers
16107 being overwritten by the load.
16109 The 'Q' and 'R' constraints are also available for 64-bit
16112 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
16114 rtx part
= gen_lowpart (SImode
, x
);
16115 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, INTVAL (part
));
16119 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
16121 output_operand_lossage ("invalid operand for code '%c'", code
);
16125 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
16129 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
16131 enum machine_mode mode
= GET_MODE (x
);
16134 if (mode
== VOIDmode
)
16136 part
= gen_highpart_mode (SImode
, mode
, x
);
16137 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, INTVAL (part
));
16141 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
16143 output_operand_lossage ("invalid operand for code '%c'", code
);
16147 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
16151 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
16153 output_operand_lossage ("invalid operand for code '%c'", code
);
16157 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
16161 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
16163 output_operand_lossage ("invalid operand for code '%c'", code
);
16167 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 3 : 2));
16171 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
16173 output_operand_lossage ("invalid operand for code '%c'", code
);
16177 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 2 : 3));
16181 asm_fprintf (stream
, "%r",
16182 GET_CODE (XEXP (x
, 0)) == REG
16183 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
16187 asm_fprintf (stream
, "{%r-%r}",
16189 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
16192 /* Like 'M', but writing doubleword vector registers, for use by Neon
16196 int regno
= (REGNO (x
) - FIRST_VFP_REGNUM
) / 2;
16197 int numregs
= ARM_NUM_REGS (GET_MODE (x
)) / 2;
16199 asm_fprintf (stream
, "{d%d}", regno
);
16201 asm_fprintf (stream
, "{d%d-d%d}", regno
, regno
+ numregs
- 1);
16206 /* CONST_TRUE_RTX means always -- that's the default. */
16207 if (x
== const_true_rtx
)
16210 if (!COMPARISON_P (x
))
16212 output_operand_lossage ("invalid operand for code '%c'", code
);
16216 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
16221 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
16222 want to do that. */
16223 if (x
== const_true_rtx
)
16225 output_operand_lossage ("instruction never executed");
16228 if (!COMPARISON_P (x
))
16230 output_operand_lossage ("invalid operand for code '%c'", code
);
16234 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
16235 (get_arm_condition_code (x
))],
16239 /* Cirrus registers can be accessed in a variety of ways:
16240 single floating point (f)
16241 double floating point (d)
16243 64bit integer (dx). */
16244 case 'W': /* Cirrus register in F mode. */
16245 case 'X': /* Cirrus register in D mode. */
16246 case 'Y': /* Cirrus register in FX mode. */
16247 case 'Z': /* Cirrus register in DX mode. */
16248 gcc_assert (GET_CODE (x
) == REG
16249 && REGNO_REG_CLASS (REGNO (x
)) == CIRRUS_REGS
);
16251 fprintf (stream
, "mv%s%s",
16253 : code
== 'X' ? "d"
16254 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
16258 /* Print cirrus register in the mode specified by the register's mode. */
16261 int mode
= GET_MODE (x
);
16263 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
16265 output_operand_lossage ("invalid operand for code '%c'", code
);
16269 fprintf (stream
, "mv%s%s",
16270 mode
== DFmode
? "d"
16271 : mode
== SImode
? "fx"
16272 : mode
== DImode
? "dx"
16273 : "f", reg_names
[REGNO (x
)] + 2);
16279 if (GET_CODE (x
) != REG
16280 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
16281 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
16282 /* Bad value for wCG register number. */
16284 output_operand_lossage ("invalid operand for code '%c'", code
);
16289 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
16292 /* Print an iWMMXt control register name. */
16294 if (GET_CODE (x
) != CONST_INT
16296 || INTVAL (x
) >= 16)
16297 /* Bad value for wC register number. */
16299 output_operand_lossage ("invalid operand for code '%c'", code
);
16305 static const char * wc_reg_names
[16] =
16307 "wCID", "wCon", "wCSSF", "wCASF",
16308 "wC4", "wC5", "wC6", "wC7",
16309 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
16310 "wC12", "wC13", "wC14", "wC15"
16313 fprintf (stream
, wc_reg_names
[INTVAL (x
)]);
16317 /* Print the high single-precision register of a VFP double-precision
16321 int mode
= GET_MODE (x
);
16324 if (GET_MODE_SIZE (mode
) != 8 || GET_CODE (x
) != REG
)
16326 output_operand_lossage ("invalid operand for code '%c'", code
);
16331 if (!VFP_REGNO_OK_FOR_DOUBLE (regno
))
16333 output_operand_lossage ("invalid operand for code '%c'", code
);
16337 fprintf (stream
, "s%d", regno
- FIRST_VFP_REGNUM
+ 1);
16341 /* Print a VFP/Neon double precision or quad precision register name. */
16345 int mode
= GET_MODE (x
);
16346 int is_quad
= (code
== 'q');
16349 if (GET_MODE_SIZE (mode
) != (is_quad
? 16 : 8))
16351 output_operand_lossage ("invalid operand for code '%c'", code
);
16355 if (GET_CODE (x
) != REG
16356 || !IS_VFP_REGNUM (REGNO (x
)))
16358 output_operand_lossage ("invalid operand for code '%c'", code
);
16363 if ((is_quad
&& !NEON_REGNO_OK_FOR_QUAD (regno
))
16364 || (!is_quad
&& !VFP_REGNO_OK_FOR_DOUBLE (regno
)))
16366 output_operand_lossage ("invalid operand for code '%c'", code
);
16370 fprintf (stream
, "%c%d", is_quad
? 'q' : 'd',
16371 (regno
- FIRST_VFP_REGNUM
) >> (is_quad
? 2 : 1));
16375 /* These two codes print the low/high doubleword register of a Neon quad
16376 register, respectively. For pair-structure types, can also print
16377 low/high quadword registers. */
16381 int mode
= GET_MODE (x
);
16384 if ((GET_MODE_SIZE (mode
) != 16
16385 && GET_MODE_SIZE (mode
) != 32) || GET_CODE (x
) != REG
)
16387 output_operand_lossage ("invalid operand for code '%c'", code
);
16392 if (!NEON_REGNO_OK_FOR_QUAD (regno
))
16394 output_operand_lossage ("invalid operand for code '%c'", code
);
16398 if (GET_MODE_SIZE (mode
) == 16)
16399 fprintf (stream
, "d%d", ((regno
- FIRST_VFP_REGNUM
) >> 1)
16400 + (code
== 'f' ? 1 : 0));
16402 fprintf (stream
, "q%d", ((regno
- FIRST_VFP_REGNUM
) >> 2)
16403 + (code
== 'f' ? 1 : 0));
16407 /* Print a VFPv3 floating-point constant, represented as an integer
16411 int index
= vfp3_const_double_index (x
);
16412 gcc_assert (index
!= -1);
16413 fprintf (stream
, "%d", index
);
16417 /* Print bits representing opcode features for Neon.
16419 Bit 0 is 1 for signed, 0 for unsigned. Floats count as signed
16420 and polynomials as unsigned.
16422 Bit 1 is 1 for floats and polynomials, 0 for ordinary integers.
16424 Bit 2 is 1 for rounding functions, 0 otherwise. */
16426 /* Identify the type as 's', 'u', 'p' or 'f'. */
16429 HOST_WIDE_INT bits
= INTVAL (x
);
16430 fputc ("uspf"[bits
& 3], stream
);
16434 /* Likewise, but signed and unsigned integers are both 'i'. */
16437 HOST_WIDE_INT bits
= INTVAL (x
);
16438 fputc ("iipf"[bits
& 3], stream
);
16442 /* As for 'T', but emit 'u' instead of 'p'. */
16445 HOST_WIDE_INT bits
= INTVAL (x
);
16446 fputc ("usuf"[bits
& 3], stream
);
16450 /* Bit 2: rounding (vs none). */
16453 HOST_WIDE_INT bits
= INTVAL (x
);
16454 fputs ((bits
& 4) != 0 ? "r" : "", stream
);
16458 /* Memory operand for vld1/vst1 instruction. */
16462 bool postinc
= FALSE
;
16463 unsigned align
, memsize
, align_bits
;
16465 gcc_assert (GET_CODE (x
) == MEM
);
16466 addr
= XEXP (x
, 0);
16467 if (GET_CODE (addr
) == POST_INC
)
16470 addr
= XEXP (addr
, 0);
16472 asm_fprintf (stream
, "[%r", REGNO (addr
));
16474 /* We know the alignment of this access, so we can emit a hint in the
16475 instruction (for some alignments) as an aid to the memory subsystem
16477 align
= MEM_ALIGN (x
) >> 3;
16478 memsize
= INTVAL (MEM_SIZE (x
));
16480 /* Only certain alignment specifiers are supported by the hardware. */
16481 if (memsize
== 16 && (align
% 32) == 0)
16483 else if ((memsize
== 8 || memsize
== 16) && (align
% 16) == 0)
16485 else if ((align
% 8) == 0)
16490 if (align_bits
!= 0)
16491 asm_fprintf (stream
, ":%d", align_bits
);
16493 asm_fprintf (stream
, "]");
16496 fputs("!", stream
);
16504 gcc_assert (GET_CODE (x
) == MEM
);
16505 addr
= XEXP (x
, 0);
16506 gcc_assert (GET_CODE (addr
) == REG
);
16507 asm_fprintf (stream
, "[%r]", REGNO (addr
));
16511 /* Translate an S register number into a D register number and element index. */
16514 int mode
= GET_MODE (x
);
16517 if (GET_MODE_SIZE (mode
) != 4 || GET_CODE (x
) != REG
)
16519 output_operand_lossage ("invalid operand for code '%c'", code
);
16524 if (!VFP_REGNO_OK_FOR_SINGLE (regno
))
16526 output_operand_lossage ("invalid operand for code '%c'", code
);
16530 regno
= regno
- FIRST_VFP_REGNUM
;
16531 fprintf (stream
, "d%d[%d]", regno
/ 2, regno
% 2);
16535 /* Register specifier for vld1.16/vst1.16. Translate the S register
16536 number into a D register number and element index. */
16539 int mode
= GET_MODE (x
);
16542 if (GET_MODE_SIZE (mode
) != 2 || GET_CODE (x
) != REG
)
16544 output_operand_lossage ("invalid operand for code '%c'", code
);
16549 if (!VFP_REGNO_OK_FOR_SINGLE (regno
))
16551 output_operand_lossage ("invalid operand for code '%c'", code
);
16555 regno
= regno
- FIRST_VFP_REGNUM
;
16556 fprintf (stream
, "d%d[%d]", regno
/2, ((regno
% 2) ? 2 : 0));
16563 output_operand_lossage ("missing operand");
16567 switch (GET_CODE (x
))
16570 asm_fprintf (stream
, "%r", REGNO (x
));
16574 output_memory_reference_mode
= GET_MODE (x
);
16575 output_address (XEXP (x
, 0));
16582 real_to_decimal (fpstr
, CONST_DOUBLE_REAL_VALUE (x
),
16583 sizeof (fpstr
), 0, 1);
16584 fprintf (stream
, "#%s", fpstr
);
16587 fprintf (stream
, "#%s", fp_immediate_constant (x
));
16591 gcc_assert (GET_CODE (x
) != NEG
);
16592 fputc ('#', stream
);
16593 if (GET_CODE (x
) == HIGH
)
16595 fputs (":lower16:", stream
);
16599 output_addr_const (stream
, x
);
16605 /* Target hook for printing a memory address. */
16607 arm_print_operand_address (FILE *stream
, rtx x
)
16611 int is_minus
= GET_CODE (x
) == MINUS
;
16613 if (GET_CODE (x
) == REG
)
16614 asm_fprintf (stream
, "[%r, #0]", REGNO (x
));
16615 else if (GET_CODE (x
) == PLUS
|| is_minus
)
16617 rtx base
= XEXP (x
, 0);
16618 rtx index
= XEXP (x
, 1);
16619 HOST_WIDE_INT offset
= 0;
16620 if (GET_CODE (base
) != REG
16621 || (GET_CODE (index
) == REG
&& REGNO (index
) == SP_REGNUM
))
16623 /* Ensure that BASE is a register. */
16624 /* (one of them must be). */
16625 /* Also ensure the SP is not used as in index register. */
16630 switch (GET_CODE (index
))
16633 offset
= INTVAL (index
);
16636 asm_fprintf (stream
, "[%r, #%wd]",
16637 REGNO (base
), offset
);
16641 asm_fprintf (stream
, "[%r, %s%r]",
16642 REGNO (base
), is_minus
? "-" : "",
16652 asm_fprintf (stream
, "[%r, %s%r",
16653 REGNO (base
), is_minus
? "-" : "",
16654 REGNO (XEXP (index
, 0)));
16655 arm_print_operand (stream
, index
, 'S');
16656 fputs ("]", stream
);
16661 gcc_unreachable ();
16664 else if (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == POST_INC
16665 || GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_DEC
)
16667 extern enum machine_mode output_memory_reference_mode
;
16669 gcc_assert (GET_CODE (XEXP (x
, 0)) == REG
);
16671 if (GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == PRE_INC
)
16672 asm_fprintf (stream
, "[%r, #%s%d]!",
16673 REGNO (XEXP (x
, 0)),
16674 GET_CODE (x
) == PRE_DEC
? "-" : "",
16675 GET_MODE_SIZE (output_memory_reference_mode
));
16677 asm_fprintf (stream
, "[%r], #%s%d",
16678 REGNO (XEXP (x
, 0)),
16679 GET_CODE (x
) == POST_DEC
? "-" : "",
16680 GET_MODE_SIZE (output_memory_reference_mode
));
16682 else if (GET_CODE (x
) == PRE_MODIFY
)
16684 asm_fprintf (stream
, "[%r, ", REGNO (XEXP (x
, 0)));
16685 if (GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
16686 asm_fprintf (stream
, "#%wd]!",
16687 INTVAL (XEXP (XEXP (x
, 1), 1)));
16689 asm_fprintf (stream
, "%r]!",
16690 REGNO (XEXP (XEXP (x
, 1), 1)));
16692 else if (GET_CODE (x
) == POST_MODIFY
)
16694 asm_fprintf (stream
, "[%r], ", REGNO (XEXP (x
, 0)));
16695 if (GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
16696 asm_fprintf (stream
, "#%wd",
16697 INTVAL (XEXP (XEXP (x
, 1), 1)));
16699 asm_fprintf (stream
, "%r",
16700 REGNO (XEXP (XEXP (x
, 1), 1)));
16702 else output_addr_const (stream
, x
);
16706 if (GET_CODE (x
) == REG
)
16707 asm_fprintf (stream
, "[%r]", REGNO (x
));
16708 else if (GET_CODE (x
) == POST_INC
)
16709 asm_fprintf (stream
, "%r!", REGNO (XEXP (x
, 0)));
16710 else if (GET_CODE (x
) == PLUS
)
16712 gcc_assert (GET_CODE (XEXP (x
, 0)) == REG
);
16713 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
16714 asm_fprintf (stream
, "[%r, #%wd]",
16715 REGNO (XEXP (x
, 0)),
16716 INTVAL (XEXP (x
, 1)));
16718 asm_fprintf (stream
, "[%r, %r]",
16719 REGNO (XEXP (x
, 0)),
16720 REGNO (XEXP (x
, 1)));
16723 output_addr_const (stream
, x
);
16727 /* Target hook for indicating whether a punctuation character for
16728 TARGET_PRINT_OPERAND is valid. */
16730 arm_print_operand_punct_valid_p (unsigned char code
)
16732 return (code
== '@' || code
== '|' || code
== '.'
16733 || code
== '(' || code
== ')' || code
== '#'
16734 || (TARGET_32BIT
&& (code
== '?'))
16735 || (TARGET_THUMB2
&& (code
== '!'))
16736 || (TARGET_THUMB
&& (code
== '_')));
16739 /* Target hook for assembling integer objects. The ARM version needs to
16740 handle word-sized values specially. */
16742 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
16744 enum machine_mode mode
;
16746 if (size
== UNITS_PER_WORD
&& aligned_p
)
16748 fputs ("\t.word\t", asm_out_file
);
16749 output_addr_const (asm_out_file
, x
);
16751 /* Mark symbols as position independent. We only do this in the
16752 .text segment, not in the .data segment. */
16753 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
16754 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
16756 /* See legitimize_pic_address for an explanation of the
16757 TARGET_VXWORKS_RTP check. */
16758 if (TARGET_VXWORKS_RTP
16759 || (GET_CODE (x
) == SYMBOL_REF
&& !SYMBOL_REF_LOCAL_P (x
)))
16760 fputs ("(GOT)", asm_out_file
);
16762 fputs ("(GOTOFF)", asm_out_file
);
16764 fputc ('\n', asm_out_file
);
16768 mode
= GET_MODE (x
);
16770 if (arm_vector_mode_supported_p (mode
))
16774 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
16776 units
= CONST_VECTOR_NUNITS (x
);
16777 size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
16779 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
16780 for (i
= 0; i
< units
; i
++)
16782 rtx elt
= CONST_VECTOR_ELT (x
, i
);
16784 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
16787 for (i
= 0; i
< units
; i
++)
16789 rtx elt
= CONST_VECTOR_ELT (x
, i
);
16790 REAL_VALUE_TYPE rval
;
16792 REAL_VALUE_FROM_CONST_DOUBLE (rval
, elt
);
16795 (rval
, GET_MODE_INNER (mode
),
16796 i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
);
16802 return default_assemble_integer (x
, size
, aligned_p
);
16806 arm_elf_asm_cdtor (rtx symbol
, int priority
, bool is_ctor
)
16810 if (!TARGET_AAPCS_BASED
)
16813 default_named_section_asm_out_constructor
16814 : default_named_section_asm_out_destructor
) (symbol
, priority
);
16818 /* Put these in the .init_array section, using a special relocation. */
16819 if (priority
!= DEFAULT_INIT_PRIORITY
)
16822 sprintf (buf
, "%s.%.5u",
16823 is_ctor
? ".init_array" : ".fini_array",
16825 s
= get_section (buf
, SECTION_WRITE
, NULL_TREE
);
16832 switch_to_section (s
);
16833 assemble_align (POINTER_SIZE
);
16834 fputs ("\t.word\t", asm_out_file
);
16835 output_addr_const (asm_out_file
, symbol
);
16836 fputs ("(target1)\n", asm_out_file
);
16839 /* Add a function to the list of static constructors. */
16842 arm_elf_asm_constructor (rtx symbol
, int priority
)
16844 arm_elf_asm_cdtor (symbol
, priority
, /*is_ctor=*/true);
16847 /* Add a function to the list of static destructors. */
16850 arm_elf_asm_destructor (rtx symbol
, int priority
)
16852 arm_elf_asm_cdtor (symbol
, priority
, /*is_ctor=*/false);
16855 /* A finite state machine takes care of noticing whether or not instructions
16856 can be conditionally executed, and thus decrease execution time and code
16857 size by deleting branch instructions. The fsm is controlled by
16858 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
16860 /* The state of the fsm controlling condition codes are:
16861 0: normal, do nothing special
16862 1: make ASM_OUTPUT_OPCODE not output this instruction
16863 2: make ASM_OUTPUT_OPCODE not output this instruction
16864 3: make instructions conditional
16865 4: make instructions conditional
16867 State transitions (state->state by whom under condition):
16868 0 -> 1 final_prescan_insn if the `target' is a label
16869 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
16870 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
16871 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
16872 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
16873 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
16874 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
16875 (the target insn is arm_target_insn).
16877 If the jump clobbers the conditions then we use states 2 and 4.
16879 A similar thing can be done with conditional return insns.
16881 XXX In case the `target' is an unconditional branch, this conditionalising
16882 of the instructions always reduces code size, but not always execution
16883 time. But then, I want to reduce the code size to somewhere near what
16884 /bin/cc produces. */
16886 /* In addition to this, state is maintained for Thumb-2 COND_EXEC
16887 instructions. When a COND_EXEC instruction is seen the subsequent
16888 instructions are scanned so that multiple conditional instructions can be
16889 combined into a single IT block. arm_condexec_count and arm_condexec_mask
16890 specify the length and true/false mask for the IT block. These will be
16891 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
16893 /* Returns the index of the ARM condition code string in
16894 `arm_condition_codes'. COMPARISON should be an rtx like
16895 `(eq (...) (...))'. */
16896 static enum arm_cond_code
16897 get_arm_condition_code (rtx comparison
)
16899 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
16900 enum arm_cond_code code
;
16901 enum rtx_code comp_code
= GET_CODE (comparison
);
16903 if (GET_MODE_CLASS (mode
) != MODE_CC
)
16904 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
16905 XEXP (comparison
, 1));
16909 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
16910 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
16911 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
16912 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
16913 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
16914 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
16915 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
16916 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
16917 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
16918 case CC_DLTUmode
: code
= ARM_CC
;
16921 gcc_assert (comp_code
== EQ
|| comp_code
== NE
);
16923 if (comp_code
== EQ
)
16924 return ARM_INVERSE_CONDITION_CODE (code
);
16930 case NE
: return ARM_NE
;
16931 case EQ
: return ARM_EQ
;
16932 case GE
: return ARM_PL
;
16933 case LT
: return ARM_MI
;
16934 default: gcc_unreachable ();
16940 case NE
: return ARM_NE
;
16941 case EQ
: return ARM_EQ
;
16942 default: gcc_unreachable ();
16948 case NE
: return ARM_MI
;
16949 case EQ
: return ARM_PL
;
16950 default: gcc_unreachable ();
16955 /* These encodings assume that AC=1 in the FPA system control
16956 byte. This allows us to handle all cases except UNEQ and
16960 case GE
: return ARM_GE
;
16961 case GT
: return ARM_GT
;
16962 case LE
: return ARM_LS
;
16963 case LT
: return ARM_MI
;
16964 case NE
: return ARM_NE
;
16965 case EQ
: return ARM_EQ
;
16966 case ORDERED
: return ARM_VC
;
16967 case UNORDERED
: return ARM_VS
;
16968 case UNLT
: return ARM_LT
;
16969 case UNLE
: return ARM_LE
;
16970 case UNGT
: return ARM_HI
;
16971 case UNGE
: return ARM_PL
;
16972 /* UNEQ and LTGT do not have a representation. */
16973 case UNEQ
: /* Fall through. */
16974 case LTGT
: /* Fall through. */
16975 default: gcc_unreachable ();
16981 case NE
: return ARM_NE
;
16982 case EQ
: return ARM_EQ
;
16983 case GE
: return ARM_LE
;
16984 case GT
: return ARM_LT
;
16985 case LE
: return ARM_GE
;
16986 case LT
: return ARM_GT
;
16987 case GEU
: return ARM_LS
;
16988 case GTU
: return ARM_CC
;
16989 case LEU
: return ARM_CS
;
16990 case LTU
: return ARM_HI
;
16991 default: gcc_unreachable ();
16997 case LTU
: return ARM_CS
;
16998 case GEU
: return ARM_CC
;
16999 default: gcc_unreachable ();
17005 case NE
: return ARM_NE
;
17006 case EQ
: return ARM_EQ
;
17007 case GEU
: return ARM_CS
;
17008 case GTU
: return ARM_HI
;
17009 case LEU
: return ARM_LS
;
17010 case LTU
: return ARM_CC
;
17011 default: gcc_unreachable ();
17017 case GE
: return ARM_GE
;
17018 case LT
: return ARM_LT
;
17019 case GEU
: return ARM_CS
;
17020 case LTU
: return ARM_CC
;
17021 default: gcc_unreachable ();
17027 case NE
: return ARM_NE
;
17028 case EQ
: return ARM_EQ
;
17029 case GE
: return ARM_GE
;
17030 case GT
: return ARM_GT
;
17031 case LE
: return ARM_LE
;
17032 case LT
: return ARM_LT
;
17033 case GEU
: return ARM_CS
;
17034 case GTU
: return ARM_HI
;
17035 case LEU
: return ARM_LS
;
17036 case LTU
: return ARM_CC
;
17037 default: gcc_unreachable ();
17040 default: gcc_unreachable ();
17044 /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
17047 thumb2_final_prescan_insn (rtx insn
)
17049 rtx first_insn
= insn
;
17050 rtx body
= PATTERN (insn
);
17052 enum arm_cond_code code
;
17056 /* Remove the previous insn from the count of insns to be output. */
17057 if (arm_condexec_count
)
17058 arm_condexec_count
--;
17060 /* Nothing to do if we are already inside a conditional block. */
17061 if (arm_condexec_count
)
17064 if (GET_CODE (body
) != COND_EXEC
)
17067 /* Conditional jumps are implemented directly. */
17068 if (GET_CODE (insn
) == JUMP_INSN
)
17071 predicate
= COND_EXEC_TEST (body
);
17072 arm_current_cc
= get_arm_condition_code (predicate
);
17074 n
= get_attr_ce_count (insn
);
17075 arm_condexec_count
= 1;
17076 arm_condexec_mask
= (1 << n
) - 1;
17077 arm_condexec_masklen
= n
;
17078 /* See if subsequent instructions can be combined into the same block. */
17081 insn
= next_nonnote_insn (insn
);
17083 /* Jumping into the middle of an IT block is illegal, so a label or
17084 barrier terminates the block. */
17085 if (GET_CODE (insn
) != INSN
&& GET_CODE(insn
) != JUMP_INSN
)
17088 body
= PATTERN (insn
);
17089 /* USE and CLOBBER aren't really insns, so just skip them. */
17090 if (GET_CODE (body
) == USE
17091 || GET_CODE (body
) == CLOBBER
)
17094 /* ??? Recognize conditional jumps, and combine them with IT blocks. */
17095 if (GET_CODE (body
) != COND_EXEC
)
17097 /* Allow up to 4 conditionally executed instructions in a block. */
17098 n
= get_attr_ce_count (insn
);
17099 if (arm_condexec_masklen
+ n
> 4)
17102 predicate
= COND_EXEC_TEST (body
);
17103 code
= get_arm_condition_code (predicate
);
17104 mask
= (1 << n
) - 1;
17105 if (arm_current_cc
== code
)
17106 arm_condexec_mask
|= (mask
<< arm_condexec_masklen
);
17107 else if (arm_current_cc
!= ARM_INVERSE_CONDITION_CODE(code
))
17110 arm_condexec_count
++;
17111 arm_condexec_masklen
+= n
;
17113 /* A jump must be the last instruction in a conditional block. */
17114 if (GET_CODE(insn
) == JUMP_INSN
)
17117 /* Restore recog_data (getting the attributes of other insns can
17118 destroy this array, but final.c assumes that it remains intact
17119 across this call). */
17120 extract_constrain_insn_cached (first_insn
);
17124 arm_final_prescan_insn (rtx insn
)
17126 /* BODY will hold the body of INSN. */
17127 rtx body
= PATTERN (insn
);
17129 /* This will be 1 if trying to repeat the trick, and things need to be
17130 reversed if it appears to fail. */
17133 /* If we start with a return insn, we only succeed if we find another one. */
17134 int seeking_return
= 0;
17136 /* START_INSN will hold the insn from where we start looking. This is the
17137 first insn after the following code_label if REVERSE is true. */
17138 rtx start_insn
= insn
;
17140 /* If in state 4, check if the target branch is reached, in order to
17141 change back to state 0. */
17142 if (arm_ccfsm_state
== 4)
17144 if (insn
== arm_target_insn
)
17146 arm_target_insn
= NULL
;
17147 arm_ccfsm_state
= 0;
17152 /* If in state 3, it is possible to repeat the trick, if this insn is an
17153 unconditional branch to a label, and immediately following this branch
17154 is the previous target label which is only used once, and the label this
17155 branch jumps to is not too far off. */
17156 if (arm_ccfsm_state
== 3)
17158 if (simplejump_p (insn
))
17160 start_insn
= next_nonnote_insn (start_insn
);
17161 if (GET_CODE (start_insn
) == BARRIER
)
17163 /* XXX Isn't this always a barrier? */
17164 start_insn
= next_nonnote_insn (start_insn
);
17166 if (GET_CODE (start_insn
) == CODE_LABEL
17167 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
17168 && LABEL_NUSES (start_insn
) == 1)
17173 else if (GET_CODE (body
) == RETURN
)
17175 start_insn
= next_nonnote_insn (start_insn
);
17176 if (GET_CODE (start_insn
) == BARRIER
)
17177 start_insn
= next_nonnote_insn (start_insn
);
17178 if (GET_CODE (start_insn
) == CODE_LABEL
17179 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
17180 && LABEL_NUSES (start_insn
) == 1)
17183 seeking_return
= 1;
17192 gcc_assert (!arm_ccfsm_state
|| reverse
);
17193 if (GET_CODE (insn
) != JUMP_INSN
)
17196 /* This jump might be paralleled with a clobber of the condition codes
17197 the jump should always come first */
17198 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
17199 body
= XVECEXP (body
, 0, 0);
17202 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
17203 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
17206 int fail
= FALSE
, succeed
= FALSE
;
17207 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
17208 int then_not_else
= TRUE
;
17209 rtx this_insn
= start_insn
, label
= 0;
17211 /* Register the insn jumped to. */
17214 if (!seeking_return
)
17215 label
= XEXP (SET_SRC (body
), 0);
17217 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
17218 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
17219 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
17221 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
17222 then_not_else
= FALSE
;
17224 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
17225 seeking_return
= 1;
17226 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
17228 seeking_return
= 1;
17229 then_not_else
= FALSE
;
17232 gcc_unreachable ();
17234 /* See how many insns this branch skips, and what kind of insns. If all
17235 insns are okay, and the label or unconditional branch to the same
17236 label is not too far away, succeed. */
17237 for (insns_skipped
= 0;
17238 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
17242 this_insn
= next_nonnote_insn (this_insn
);
17246 switch (GET_CODE (this_insn
))
17249 /* Succeed if it is the target label, otherwise fail since
17250 control falls in from somewhere else. */
17251 if (this_insn
== label
)
17253 arm_ccfsm_state
= 1;
17261 /* Succeed if the following insn is the target label.
17263 If return insns are used then the last insn in a function
17264 will be a barrier. */
17265 this_insn
= next_nonnote_insn (this_insn
);
17266 if (this_insn
&& this_insn
== label
)
17268 arm_ccfsm_state
= 1;
17276 /* The AAPCS says that conditional calls should not be
17277 used since they make interworking inefficient (the
17278 linker can't transform BL<cond> into BLX). That's
17279 only a problem if the machine has BLX. */
17286 /* Succeed if the following insn is the target label, or
17287 if the following two insns are a barrier and the
17289 this_insn
= next_nonnote_insn (this_insn
);
17290 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
17291 this_insn
= next_nonnote_insn (this_insn
);
17293 if (this_insn
&& this_insn
== label
17294 && insns_skipped
< max_insns_skipped
)
17296 arm_ccfsm_state
= 1;
17304 /* If this is an unconditional branch to the same label, succeed.
17305 If it is to another label, do nothing. If it is conditional,
17307 /* XXX Probably, the tests for SET and the PC are
17310 scanbody
= PATTERN (this_insn
);
17311 if (GET_CODE (scanbody
) == SET
17312 && GET_CODE (SET_DEST (scanbody
)) == PC
)
17314 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
17315 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
17317 arm_ccfsm_state
= 2;
17320 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
17323 /* Fail if a conditional return is undesirable (e.g. on a
17324 StrongARM), but still allow this if optimizing for size. */
17325 else if (GET_CODE (scanbody
) == RETURN
17326 && !use_return_insn (TRUE
, NULL
)
17329 else if (GET_CODE (scanbody
) == RETURN
17332 arm_ccfsm_state
= 2;
17335 else if (GET_CODE (scanbody
) == PARALLEL
)
17337 switch (get_attr_conds (this_insn
))
17347 fail
= TRUE
; /* Unrecognized jump (e.g. epilogue). */
17352 /* Instructions using or affecting the condition codes make it
17354 scanbody
= PATTERN (this_insn
);
17355 if (!(GET_CODE (scanbody
) == SET
17356 || GET_CODE (scanbody
) == PARALLEL
)
17357 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
17360 /* A conditional cirrus instruction must be followed by
17361 a non Cirrus instruction. However, since we
17362 conditionalize instructions in this function and by
17363 the time we get here we can't add instructions
17364 (nops), because shorten_branches() has already been
17365 called, we will disable conditionalizing Cirrus
17366 instructions to be safe. */
17367 if (GET_CODE (scanbody
) != USE
17368 && GET_CODE (scanbody
) != CLOBBER
17369 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
17379 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
17380 arm_target_label
= CODE_LABEL_NUMBER (label
);
17383 gcc_assert (seeking_return
|| arm_ccfsm_state
== 2);
17385 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
17387 this_insn
= next_nonnote_insn (this_insn
);
17388 gcc_assert (!this_insn
17389 || (GET_CODE (this_insn
) != BARRIER
17390 && GET_CODE (this_insn
) != CODE_LABEL
));
17394 /* Oh, dear! we ran off the end.. give up. */
17395 extract_constrain_insn_cached (insn
);
17396 arm_ccfsm_state
= 0;
17397 arm_target_insn
= NULL
;
17400 arm_target_insn
= this_insn
;
17403 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
17406 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
), 0));
17408 if (reverse
|| then_not_else
)
17409 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
17412 /* Restore recog_data (getting the attributes of other insns can
17413 destroy this array, but final.c assumes that it remains intact
17414 across this call. */
17415 extract_constrain_insn_cached (insn
);
17419 /* Output IT instructions. */
17421 thumb2_asm_output_opcode (FILE * stream
)
17426 if (arm_condexec_mask
)
17428 for (n
= 0; n
< arm_condexec_masklen
; n
++)
17429 buff
[n
] = (arm_condexec_mask
& (1 << n
)) ? 't' : 'e';
17431 asm_fprintf(stream
, "i%s\t%s\n\t", buff
,
17432 arm_condition_codes
[arm_current_cc
]);
17433 arm_condexec_mask
= 0;
17437 /* Returns true if REGNO is a valid register
17438 for holding a quantity of type MODE. */
17440 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
17442 if (GET_MODE_CLASS (mode
) == MODE_CC
)
17443 return (regno
== CC_REGNUM
17444 || (TARGET_HARD_FLOAT
&& TARGET_VFP
17445 && regno
== VFPCC_REGNUM
));
17448 /* For the Thumb we only allow values bigger than SImode in
17449 registers 0 - 6, so that there is always a second low
17450 register available to hold the upper part of the value.
17451 We probably we ought to ensure that the register is the
17452 start of an even numbered register pair. */
17453 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
17455 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
17456 && IS_CIRRUS_REGNUM (regno
))
17457 /* We have outlawed SI values in Cirrus registers because they
17458 reside in the lower 32 bits, but SF values reside in the
17459 upper 32 bits. This causes gcc all sorts of grief. We can't
17460 even split the registers into pairs because Cirrus SI values
17461 get sign extended to 64bits-- aldyh. */
17462 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
17464 if (TARGET_HARD_FLOAT
&& TARGET_VFP
17465 && IS_VFP_REGNUM (regno
))
17467 if (mode
== SFmode
|| mode
== SImode
)
17468 return VFP_REGNO_OK_FOR_SINGLE (regno
);
17470 if (mode
== DFmode
)
17471 return VFP_REGNO_OK_FOR_DOUBLE (regno
);
17473 /* VFP registers can hold HFmode values, but there is no point in
17474 putting them there unless we have hardware conversion insns. */
17475 if (mode
== HFmode
)
17476 return TARGET_FP16
&& VFP_REGNO_OK_FOR_SINGLE (regno
);
17479 return (VALID_NEON_DREG_MODE (mode
) && VFP_REGNO_OK_FOR_DOUBLE (regno
))
17480 || (VALID_NEON_QREG_MODE (mode
)
17481 && NEON_REGNO_OK_FOR_QUAD (regno
))
17482 || (mode
== TImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 2))
17483 || (mode
== EImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 3))
17484 || (mode
== OImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 4))
17485 || (mode
== CImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 6))
17486 || (mode
== XImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 8));
17491 if (TARGET_REALLY_IWMMXT
)
17493 if (IS_IWMMXT_GR_REGNUM (regno
))
17494 return mode
== SImode
;
17496 if (IS_IWMMXT_REGNUM (regno
))
17497 return VALID_IWMMXT_REG_MODE (mode
);
17500 /* We allow almost any value to be stored in the general registers.
17501 Restrict doubleword quantities to even register pairs so that we can
17502 use ldrd. Do not allow very large Neon structure opaque modes in
17503 general registers; they would use too many. */
17504 if (regno
<= LAST_ARM_REGNUM
)
17505 return !(TARGET_LDRD
&& GET_MODE_SIZE (mode
) > 4 && (regno
& 1) != 0)
17506 && ARM_NUM_REGS (mode
) <= 4;
17508 if (regno
== FRAME_POINTER_REGNUM
17509 || regno
== ARG_POINTER_REGNUM
)
17510 /* We only allow integers in the fake hard registers. */
17511 return GET_MODE_CLASS (mode
) == MODE_INT
;
17513 /* The only registers left are the FPA registers
17514 which we only allow to hold FP values. */
17515 return (TARGET_HARD_FLOAT
&& TARGET_FPA
17516 && GET_MODE_CLASS (mode
) == MODE_FLOAT
17517 && regno
>= FIRST_FPA_REGNUM
17518 && regno
<= LAST_FPA_REGNUM
);
17521 /* For efficiency and historical reasons LO_REGS, HI_REGS and CC_REGS are
17522 not used in arm mode. */
17525 arm_regno_class (int regno
)
17529 if (regno
== STACK_POINTER_REGNUM
)
17531 if (regno
== CC_REGNUM
)
17538 if (TARGET_THUMB2
&& regno
< 8)
17541 if ( regno
<= LAST_ARM_REGNUM
17542 || regno
== FRAME_POINTER_REGNUM
17543 || regno
== ARG_POINTER_REGNUM
)
17544 return TARGET_THUMB2
? HI_REGS
: GENERAL_REGS
;
17546 if (regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
)
17547 return TARGET_THUMB2
? CC_REG
: NO_REGS
;
17549 if (IS_CIRRUS_REGNUM (regno
))
17550 return CIRRUS_REGS
;
17552 if (IS_VFP_REGNUM (regno
))
17554 if (regno
<= D7_VFP_REGNUM
)
17555 return VFP_D0_D7_REGS
;
17556 else if (regno
<= LAST_LO_VFP_REGNUM
)
17557 return VFP_LO_REGS
;
17559 return VFP_HI_REGS
;
17562 if (IS_IWMMXT_REGNUM (regno
))
17563 return IWMMXT_REGS
;
17565 if (IS_IWMMXT_GR_REGNUM (regno
))
17566 return IWMMXT_GR_REGS
;
17571 /* Handle a special case when computing the offset
17572 of an argument from the frame pointer. */
17574 arm_debugger_arg_offset (int value
, rtx addr
)
17578 /* We are only interested if dbxout_parms() failed to compute the offset. */
17582 /* We can only cope with the case where the address is held in a register. */
17583 if (GET_CODE (addr
) != REG
)
17586 /* If we are using the frame pointer to point at the argument, then
17587 an offset of 0 is correct. */
17588 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
17591 /* If we are using the stack pointer to point at the
17592 argument, then an offset of 0 is correct. */
17593 /* ??? Check this is consistent with thumb2 frame layout. */
17594 if ((TARGET_THUMB
|| !frame_pointer_needed
)
17595 && REGNO (addr
) == SP_REGNUM
)
17598 /* Oh dear. The argument is pointed to by a register rather
17599 than being held in a register, or being stored at a known
17600 offset from the frame pointer. Since GDB only understands
17601 those two kinds of argument we must translate the address
17602 held in the register into an offset from the frame pointer.
17603 We do this by searching through the insns for the function
17604 looking to see where this register gets its value. If the
17605 register is initialized from the frame pointer plus an offset
17606 then we are in luck and we can continue, otherwise we give up.
17608 This code is exercised by producing debugging information
17609 for a function with arguments like this:
17611 double func (double a, double b, int c, double d) {return d;}
17613 Without this code the stab for parameter 'd' will be set to
17614 an offset of 0 from the frame pointer, rather than 8. */
17616 /* The if() statement says:
17618 If the insn is a normal instruction
17619 and if the insn is setting the value in a register
17620 and if the register being set is the register holding the address of the argument
17621 and if the address is computing by an addition
17622 that involves adding to a register
17623 which is the frame pointer
17628 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
17630 if ( GET_CODE (insn
) == INSN
17631 && GET_CODE (PATTERN (insn
)) == SET
17632 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
17633 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
17634 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
17635 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
17636 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
17639 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
17648 warning (0, "unable to compute real location of stacked parameter");
17649 value
= 8; /* XXX magic hack */
17669 T_MAX
/* Size of enum. Keep last. */
17670 } neon_builtin_type_mode
;
17672 #define TYPE_MODE_BIT(X) (1 << (X))
17674 #define TB_DREG (TYPE_MODE_BIT (T_V8QI) | TYPE_MODE_BIT (T_V4HI) \
17675 | TYPE_MODE_BIT (T_V2SI) | TYPE_MODE_BIT (T_V2SF) \
17676 | TYPE_MODE_BIT (T_DI))
17677 #define TB_QREG (TYPE_MODE_BIT (T_V16QI) | TYPE_MODE_BIT (T_V8HI) \
17678 | TYPE_MODE_BIT (T_V4SI) | TYPE_MODE_BIT (T_V4SF) \
17679 | TYPE_MODE_BIT (T_V2DI) | TYPE_MODE_BIT (T_TI))
17681 #define v8qi_UP T_V8QI
17682 #define v4hi_UP T_V4HI
17683 #define v2si_UP T_V2SI
17684 #define v2sf_UP T_V2SF
17686 #define v16qi_UP T_V16QI
17687 #define v8hi_UP T_V8HI
17688 #define v4si_UP T_V4SI
17689 #define v4sf_UP T_V4SF
17690 #define v2di_UP T_V2DI
17695 #define UP(X) X##_UP
17728 NEON_LOADSTRUCTLANE
,
17730 NEON_STORESTRUCTLANE
,
17739 const neon_itype itype
;
17740 const neon_builtin_type_mode mode
;
17741 const enum insn_code code
;
17742 unsigned int fcode
;
17743 } neon_builtin_datum
;
17745 #define CF(N,X) CODE_FOR_neon_##N##X
17747 #define VAR1(T, N, A) \
17748 {#N, NEON_##T, UP (A), CF (N, A), 0}
17749 #define VAR2(T, N, A, B) \
17751 {#N, NEON_##T, UP (B), CF (N, B), 0}
17752 #define VAR3(T, N, A, B, C) \
17753 VAR2 (T, N, A, B), \
17754 {#N, NEON_##T, UP (C), CF (N, C), 0}
17755 #define VAR4(T, N, A, B, C, D) \
17756 VAR3 (T, N, A, B, C), \
17757 {#N, NEON_##T, UP (D), CF (N, D), 0}
17758 #define VAR5(T, N, A, B, C, D, E) \
17759 VAR4 (T, N, A, B, C, D), \
17760 {#N, NEON_##T, UP (E), CF (N, E), 0}
17761 #define VAR6(T, N, A, B, C, D, E, F) \
17762 VAR5 (T, N, A, B, C, D, E), \
17763 {#N, NEON_##T, UP (F), CF (N, F), 0}
17764 #define VAR7(T, N, A, B, C, D, E, F, G) \
17765 VAR6 (T, N, A, B, C, D, E, F), \
17766 {#N, NEON_##T, UP (G), CF (N, G), 0}
17767 #define VAR8(T, N, A, B, C, D, E, F, G, H) \
17768 VAR7 (T, N, A, B, C, D, E, F, G), \
17769 {#N, NEON_##T, UP (H), CF (N, H), 0}
17770 #define VAR9(T, N, A, B, C, D, E, F, G, H, I) \
17771 VAR8 (T, N, A, B, C, D, E, F, G, H), \
17772 {#N, NEON_##T, UP (I), CF (N, I), 0}
17773 #define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \
17774 VAR9 (T, N, A, B, C, D, E, F, G, H, I), \
17775 {#N, NEON_##T, UP (J), CF (N, J), 0}
17777 /* The mode entries in the following table correspond to the "key" type of the
17778 instruction variant, i.e. equivalent to that which would be specified after
17779 the assembler mnemonic, which usually refers to the last vector operand.
17780 (Signed/unsigned/polynomial types are not differentiated between though, and
17781 are all mapped onto the same mode for a given element size.) The modes
17782 listed per instruction should be the same as those defined for that
17783 instruction's pattern in neon.md. */
17785 static neon_builtin_datum neon_builtin_data
[] =
17787 VAR10 (BINOP
, vadd
,
17788 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17789 VAR3 (BINOP
, vaddl
, v8qi
, v4hi
, v2si
),
17790 VAR3 (BINOP
, vaddw
, v8qi
, v4hi
, v2si
),
17791 VAR6 (BINOP
, vhadd
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
),
17792 VAR8 (BINOP
, vqadd
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
),
17793 VAR3 (BINOP
, vaddhn
, v8hi
, v4si
, v2di
),
17794 VAR8 (BINOP
, vmul
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
),
17795 VAR8 (TERNOP
, vmla
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
),
17796 VAR3 (TERNOP
, vmlal
, v8qi
, v4hi
, v2si
),
17797 VAR8 (TERNOP
, vmls
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
),
17798 VAR3 (TERNOP
, vmlsl
, v8qi
, v4hi
, v2si
),
17799 VAR4 (BINOP
, vqdmulh
, v4hi
, v2si
, v8hi
, v4si
),
17800 VAR2 (TERNOP
, vqdmlal
, v4hi
, v2si
),
17801 VAR2 (TERNOP
, vqdmlsl
, v4hi
, v2si
),
17802 VAR3 (BINOP
, vmull
, v8qi
, v4hi
, v2si
),
17803 VAR2 (SCALARMULL
, vmull_n
, v4hi
, v2si
),
17804 VAR2 (LANEMULL
, vmull_lane
, v4hi
, v2si
),
17805 VAR2 (SCALARMULL
, vqdmull_n
, v4hi
, v2si
),
17806 VAR2 (LANEMULL
, vqdmull_lane
, v4hi
, v2si
),
17807 VAR4 (SCALARMULH
, vqdmulh_n
, v4hi
, v2si
, v8hi
, v4si
),
17808 VAR4 (LANEMULH
, vqdmulh_lane
, v4hi
, v2si
, v8hi
, v4si
),
17809 VAR2 (BINOP
, vqdmull
, v4hi
, v2si
),
17810 VAR8 (BINOP
, vshl
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
),
17811 VAR8 (BINOP
, vqshl
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
),
17812 VAR8 (SHIFTIMM
, vshr_n
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
),
17813 VAR3 (SHIFTIMM
, vshrn_n
, v8hi
, v4si
, v2di
),
17814 VAR3 (SHIFTIMM
, vqshrn_n
, v8hi
, v4si
, v2di
),
17815 VAR3 (SHIFTIMM
, vqshrun_n
, v8hi
, v4si
, v2di
),
17816 VAR8 (SHIFTIMM
, vshl_n
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
),
17817 VAR8 (SHIFTIMM
, vqshl_n
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
),
17818 VAR8 (SHIFTIMM
, vqshlu_n
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
),
17819 VAR3 (SHIFTIMM
, vshll_n
, v8qi
, v4hi
, v2si
),
17820 VAR8 (SHIFTACC
, vsra_n
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
),
17821 VAR10 (BINOP
, vsub
,
17822 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17823 VAR3 (BINOP
, vsubl
, v8qi
, v4hi
, v2si
),
17824 VAR3 (BINOP
, vsubw
, v8qi
, v4hi
, v2si
),
17825 VAR8 (BINOP
, vqsub
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
),
17826 VAR6 (BINOP
, vhsub
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
),
17827 VAR3 (BINOP
, vsubhn
, v8hi
, v4si
, v2di
),
17828 VAR8 (BINOP
, vceq
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
),
17829 VAR8 (BINOP
, vcge
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
),
17830 VAR8 (BINOP
, vcgt
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
),
17831 VAR2 (BINOP
, vcage
, v2sf
, v4sf
),
17832 VAR2 (BINOP
, vcagt
, v2sf
, v4sf
),
17833 VAR6 (BINOP
, vtst
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
),
17834 VAR8 (BINOP
, vabd
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
),
17835 VAR3 (BINOP
, vabdl
, v8qi
, v4hi
, v2si
),
17836 VAR6 (TERNOP
, vaba
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
),
17837 VAR3 (TERNOP
, vabal
, v8qi
, v4hi
, v2si
),
17838 VAR8 (BINOP
, vmax
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
),
17839 VAR8 (BINOP
, vmin
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
),
17840 VAR4 (BINOP
, vpadd
, v8qi
, v4hi
, v2si
, v2sf
),
17841 VAR6 (UNOP
, vpaddl
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
),
17842 VAR6 (BINOP
, vpadal
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
),
17843 VAR4 (BINOP
, vpmax
, v8qi
, v4hi
, v2si
, v2sf
),
17844 VAR4 (BINOP
, vpmin
, v8qi
, v4hi
, v2si
, v2sf
),
17845 VAR2 (BINOP
, vrecps
, v2sf
, v4sf
),
17846 VAR2 (BINOP
, vrsqrts
, v2sf
, v4sf
),
17847 VAR8 (SHIFTINSERT
, vsri_n
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
),
17848 VAR8 (SHIFTINSERT
, vsli_n
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
),
17849 VAR8 (UNOP
, vabs
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
),
17850 VAR6 (UNOP
, vqabs
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
),
17851 VAR8 (UNOP
, vneg
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
),
17852 VAR6 (UNOP
, vqneg
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
),
17853 VAR6 (UNOP
, vcls
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
),
17854 VAR6 (UNOP
, vclz
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
),
17855 VAR2 (UNOP
, vcnt
, v8qi
, v16qi
),
17856 VAR4 (UNOP
, vrecpe
, v2si
, v2sf
, v4si
, v4sf
),
17857 VAR4 (UNOP
, vrsqrte
, v2si
, v2sf
, v4si
, v4sf
),
17858 VAR6 (UNOP
, vmvn
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
),
17859 /* FIXME: vget_lane supports more variants than this! */
17860 VAR10 (GETLANE
, vget_lane
,
17861 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17862 VAR10 (SETLANE
, vset_lane
,
17863 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17864 VAR5 (CREATE
, vcreate
, v8qi
, v4hi
, v2si
, v2sf
, di
),
17865 VAR10 (DUP
, vdup_n
,
17866 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17867 VAR10 (DUPLANE
, vdup_lane
,
17868 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17869 VAR5 (COMBINE
, vcombine
, v8qi
, v4hi
, v2si
, v2sf
, di
),
17870 VAR5 (SPLIT
, vget_high
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17871 VAR5 (SPLIT
, vget_low
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17872 VAR3 (UNOP
, vmovn
, v8hi
, v4si
, v2di
),
17873 VAR3 (UNOP
, vqmovn
, v8hi
, v4si
, v2di
),
17874 VAR3 (UNOP
, vqmovun
, v8hi
, v4si
, v2di
),
17875 VAR3 (UNOP
, vmovl
, v8qi
, v4hi
, v2si
),
17876 VAR6 (LANEMUL
, vmul_lane
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
),
17877 VAR6 (LANEMAC
, vmla_lane
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
),
17878 VAR2 (LANEMAC
, vmlal_lane
, v4hi
, v2si
),
17879 VAR2 (LANEMAC
, vqdmlal_lane
, v4hi
, v2si
),
17880 VAR6 (LANEMAC
, vmls_lane
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
),
17881 VAR2 (LANEMAC
, vmlsl_lane
, v4hi
, v2si
),
17882 VAR2 (LANEMAC
, vqdmlsl_lane
, v4hi
, v2si
),
17883 VAR6 (SCALARMUL
, vmul_n
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
),
17884 VAR6 (SCALARMAC
, vmla_n
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
),
17885 VAR2 (SCALARMAC
, vmlal_n
, v4hi
, v2si
),
17886 VAR2 (SCALARMAC
, vqdmlal_n
, v4hi
, v2si
),
17887 VAR6 (SCALARMAC
, vmls_n
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
),
17888 VAR2 (SCALARMAC
, vmlsl_n
, v4hi
, v2si
),
17889 VAR2 (SCALARMAC
, vqdmlsl_n
, v4hi
, v2si
),
17890 VAR10 (BINOP
, vext
,
17891 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17892 VAR8 (UNOP
, vrev64
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
),
17893 VAR4 (UNOP
, vrev32
, v8qi
, v4hi
, v16qi
, v8hi
),
17894 VAR2 (UNOP
, vrev16
, v8qi
, v16qi
),
17895 VAR4 (CONVERT
, vcvt
, v2si
, v2sf
, v4si
, v4sf
),
17896 VAR4 (FIXCONV
, vcvt_n
, v2si
, v2sf
, v4si
, v4sf
),
17897 VAR10 (SELECT
, vbsl
,
17898 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17899 VAR1 (VTBL
, vtbl1
, v8qi
),
17900 VAR1 (VTBL
, vtbl2
, v8qi
),
17901 VAR1 (VTBL
, vtbl3
, v8qi
),
17902 VAR1 (VTBL
, vtbl4
, v8qi
),
17903 VAR1 (VTBX
, vtbx1
, v8qi
),
17904 VAR1 (VTBX
, vtbx2
, v8qi
),
17905 VAR1 (VTBX
, vtbx3
, v8qi
),
17906 VAR1 (VTBX
, vtbx4
, v8qi
),
17907 VAR8 (RESULTPAIR
, vtrn
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
),
17908 VAR8 (RESULTPAIR
, vzip
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
),
17909 VAR8 (RESULTPAIR
, vuzp
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
),
17910 VAR5 (REINTERP
, vreinterpretv8qi
, v8qi
, v4hi
, v2si
, v2sf
, di
),
17911 VAR5 (REINTERP
, vreinterpretv4hi
, v8qi
, v4hi
, v2si
, v2sf
, di
),
17912 VAR5 (REINTERP
, vreinterpretv2si
, v8qi
, v4hi
, v2si
, v2sf
, di
),
17913 VAR5 (REINTERP
, vreinterpretv2sf
, v8qi
, v4hi
, v2si
, v2sf
, di
),
17914 VAR5 (REINTERP
, vreinterpretdi
, v8qi
, v4hi
, v2si
, v2sf
, di
),
17915 VAR5 (REINTERP
, vreinterpretv16qi
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17916 VAR5 (REINTERP
, vreinterpretv8hi
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17917 VAR5 (REINTERP
, vreinterpretv4si
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17918 VAR5 (REINTERP
, vreinterpretv4sf
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17919 VAR5 (REINTERP
, vreinterpretv2di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17920 VAR10 (LOAD1
, vld1
,
17921 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17922 VAR10 (LOAD1LANE
, vld1_lane
,
17923 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17924 VAR10 (LOAD1
, vld1_dup
,
17925 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17926 VAR10 (STORE1
, vst1
,
17927 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17928 VAR10 (STORE1LANE
, vst1_lane
,
17929 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17931 vld2
, v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
),
17932 VAR7 (LOADSTRUCTLANE
, vld2_lane
,
17933 v8qi
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
),
17934 VAR5 (LOADSTRUCT
, vld2_dup
, v8qi
, v4hi
, v2si
, v2sf
, di
),
17935 VAR9 (STORESTRUCT
, vst2
,
17936 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
),
17937 VAR7 (STORESTRUCTLANE
, vst2_lane
,
17938 v8qi
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
),
17940 vld3
, v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
),
17941 VAR7 (LOADSTRUCTLANE
, vld3_lane
,
17942 v8qi
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
),
17943 VAR5 (LOADSTRUCT
, vld3_dup
, v8qi
, v4hi
, v2si
, v2sf
, di
),
17944 VAR9 (STORESTRUCT
, vst3
,
17945 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
),
17946 VAR7 (STORESTRUCTLANE
, vst3_lane
,
17947 v8qi
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
),
17948 VAR9 (LOADSTRUCT
, vld4
,
17949 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
),
17950 VAR7 (LOADSTRUCTLANE
, vld4_lane
,
17951 v8qi
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
),
17952 VAR5 (LOADSTRUCT
, vld4_dup
, v8qi
, v4hi
, v2si
, v2sf
, di
),
17953 VAR9 (STORESTRUCT
, vst4
,
17954 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
),
17955 VAR7 (STORESTRUCTLANE
, vst4_lane
,
17956 v8qi
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
),
17957 VAR10 (LOGICBINOP
, vand
,
17958 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17959 VAR10 (LOGICBINOP
, vorr
,
17960 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17961 VAR10 (BINOP
, veor
,
17962 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17963 VAR10 (LOGICBINOP
, vbic
,
17964 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
),
17965 VAR10 (LOGICBINOP
, vorn
,
17966 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
)
17981 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
17982 symbolic names defined here (which would require too much duplication).
17986 ARM_BUILTIN_GETWCX
,
17987 ARM_BUILTIN_SETWCX
,
17991 ARM_BUILTIN_WAVG2BR
,
17992 ARM_BUILTIN_WAVG2HR
,
17993 ARM_BUILTIN_WAVG2B
,
17994 ARM_BUILTIN_WAVG2H
,
18001 ARM_BUILTIN_WMACSZ
,
18003 ARM_BUILTIN_WMACUZ
,
18006 ARM_BUILTIN_WSADBZ
,
18008 ARM_BUILTIN_WSADHZ
,
18010 ARM_BUILTIN_WALIGN
,
18013 ARM_BUILTIN_TMIAPH
,
18014 ARM_BUILTIN_TMIABB
,
18015 ARM_BUILTIN_TMIABT
,
18016 ARM_BUILTIN_TMIATB
,
18017 ARM_BUILTIN_TMIATT
,
18019 ARM_BUILTIN_TMOVMSKB
,
18020 ARM_BUILTIN_TMOVMSKH
,
18021 ARM_BUILTIN_TMOVMSKW
,
18023 ARM_BUILTIN_TBCSTB
,
18024 ARM_BUILTIN_TBCSTH
,
18025 ARM_BUILTIN_TBCSTW
,
18027 ARM_BUILTIN_WMADDS
,
18028 ARM_BUILTIN_WMADDU
,
18030 ARM_BUILTIN_WPACKHSS
,
18031 ARM_BUILTIN_WPACKWSS
,
18032 ARM_BUILTIN_WPACKDSS
,
18033 ARM_BUILTIN_WPACKHUS
,
18034 ARM_BUILTIN_WPACKWUS
,
18035 ARM_BUILTIN_WPACKDUS
,
18040 ARM_BUILTIN_WADDSSB
,
18041 ARM_BUILTIN_WADDSSH
,
18042 ARM_BUILTIN_WADDSSW
,
18043 ARM_BUILTIN_WADDUSB
,
18044 ARM_BUILTIN_WADDUSH
,
18045 ARM_BUILTIN_WADDUSW
,
18049 ARM_BUILTIN_WSUBSSB
,
18050 ARM_BUILTIN_WSUBSSH
,
18051 ARM_BUILTIN_WSUBSSW
,
18052 ARM_BUILTIN_WSUBUSB
,
18053 ARM_BUILTIN_WSUBUSH
,
18054 ARM_BUILTIN_WSUBUSW
,
18061 ARM_BUILTIN_WCMPEQB
,
18062 ARM_BUILTIN_WCMPEQH
,
18063 ARM_BUILTIN_WCMPEQW
,
18064 ARM_BUILTIN_WCMPGTUB
,
18065 ARM_BUILTIN_WCMPGTUH
,
18066 ARM_BUILTIN_WCMPGTUW
,
18067 ARM_BUILTIN_WCMPGTSB
,
18068 ARM_BUILTIN_WCMPGTSH
,
18069 ARM_BUILTIN_WCMPGTSW
,
18071 ARM_BUILTIN_TEXTRMSB
,
18072 ARM_BUILTIN_TEXTRMSH
,
18073 ARM_BUILTIN_TEXTRMSW
,
18074 ARM_BUILTIN_TEXTRMUB
,
18075 ARM_BUILTIN_TEXTRMUH
,
18076 ARM_BUILTIN_TEXTRMUW
,
18077 ARM_BUILTIN_TINSRB
,
18078 ARM_BUILTIN_TINSRH
,
18079 ARM_BUILTIN_TINSRW
,
18081 ARM_BUILTIN_WMAXSW
,
18082 ARM_BUILTIN_WMAXSH
,
18083 ARM_BUILTIN_WMAXSB
,
18084 ARM_BUILTIN_WMAXUW
,
18085 ARM_BUILTIN_WMAXUH
,
18086 ARM_BUILTIN_WMAXUB
,
18087 ARM_BUILTIN_WMINSW
,
18088 ARM_BUILTIN_WMINSH
,
18089 ARM_BUILTIN_WMINSB
,
18090 ARM_BUILTIN_WMINUW
,
18091 ARM_BUILTIN_WMINUH
,
18092 ARM_BUILTIN_WMINUB
,
18094 ARM_BUILTIN_WMULUM
,
18095 ARM_BUILTIN_WMULSM
,
18096 ARM_BUILTIN_WMULUL
,
18098 ARM_BUILTIN_PSADBH
,
18099 ARM_BUILTIN_WSHUFH
,
18113 ARM_BUILTIN_WSLLHI
,
18114 ARM_BUILTIN_WSLLWI
,
18115 ARM_BUILTIN_WSLLDI
,
18116 ARM_BUILTIN_WSRAHI
,
18117 ARM_BUILTIN_WSRAWI
,
18118 ARM_BUILTIN_WSRADI
,
18119 ARM_BUILTIN_WSRLHI
,
18120 ARM_BUILTIN_WSRLWI
,
18121 ARM_BUILTIN_WSRLDI
,
18122 ARM_BUILTIN_WRORHI
,
18123 ARM_BUILTIN_WRORWI
,
18124 ARM_BUILTIN_WRORDI
,
18126 ARM_BUILTIN_WUNPCKIHB
,
18127 ARM_BUILTIN_WUNPCKIHH
,
18128 ARM_BUILTIN_WUNPCKIHW
,
18129 ARM_BUILTIN_WUNPCKILB
,
18130 ARM_BUILTIN_WUNPCKILH
,
18131 ARM_BUILTIN_WUNPCKILW
,
18133 ARM_BUILTIN_WUNPCKEHSB
,
18134 ARM_BUILTIN_WUNPCKEHSH
,
18135 ARM_BUILTIN_WUNPCKEHSW
,
18136 ARM_BUILTIN_WUNPCKEHUB
,
18137 ARM_BUILTIN_WUNPCKEHUH
,
18138 ARM_BUILTIN_WUNPCKEHUW
,
18139 ARM_BUILTIN_WUNPCKELSB
,
18140 ARM_BUILTIN_WUNPCKELSH
,
18141 ARM_BUILTIN_WUNPCKELSW
,
18142 ARM_BUILTIN_WUNPCKELUB
,
18143 ARM_BUILTIN_WUNPCKELUH
,
18144 ARM_BUILTIN_WUNPCKELUW
,
18146 ARM_BUILTIN_THREAD_POINTER
,
18148 ARM_BUILTIN_NEON_BASE
,
18150 ARM_BUILTIN_MAX
= ARM_BUILTIN_NEON_BASE
+ ARRAY_SIZE (neon_builtin_data
)
18153 static GTY(()) tree arm_builtin_decls
[ARM_BUILTIN_MAX
];
18156 arm_init_neon_builtins (void)
18158 unsigned int i
, fcode
;
18161 tree neon_intQI_type_node
;
18162 tree neon_intHI_type_node
;
18163 tree neon_polyQI_type_node
;
18164 tree neon_polyHI_type_node
;
18165 tree neon_intSI_type_node
;
18166 tree neon_intDI_type_node
;
18167 tree neon_float_type_node
;
18169 tree intQI_pointer_node
;
18170 tree intHI_pointer_node
;
18171 tree intSI_pointer_node
;
18172 tree intDI_pointer_node
;
18173 tree float_pointer_node
;
18175 tree const_intQI_node
;
18176 tree const_intHI_node
;
18177 tree const_intSI_node
;
18178 tree const_intDI_node
;
18179 tree const_float_node
;
18181 tree const_intQI_pointer_node
;
18182 tree const_intHI_pointer_node
;
18183 tree const_intSI_pointer_node
;
18184 tree const_intDI_pointer_node
;
18185 tree const_float_pointer_node
;
18187 tree V8QI_type_node
;
18188 tree V4HI_type_node
;
18189 tree V2SI_type_node
;
18190 tree V2SF_type_node
;
18191 tree V16QI_type_node
;
18192 tree V8HI_type_node
;
18193 tree V4SI_type_node
;
18194 tree V4SF_type_node
;
18195 tree V2DI_type_node
;
18197 tree intUQI_type_node
;
18198 tree intUHI_type_node
;
18199 tree intUSI_type_node
;
18200 tree intUDI_type_node
;
18202 tree intEI_type_node
;
18203 tree intOI_type_node
;
18204 tree intCI_type_node
;
18205 tree intXI_type_node
;
18207 tree V8QI_pointer_node
;
18208 tree V4HI_pointer_node
;
18209 tree V2SI_pointer_node
;
18210 tree V2SF_pointer_node
;
18211 tree V16QI_pointer_node
;
18212 tree V8HI_pointer_node
;
18213 tree V4SI_pointer_node
;
18214 tree V4SF_pointer_node
;
18215 tree V2DI_pointer_node
;
18217 tree void_ftype_pv8qi_v8qi_v8qi
;
18218 tree void_ftype_pv4hi_v4hi_v4hi
;
18219 tree void_ftype_pv2si_v2si_v2si
;
18220 tree void_ftype_pv2sf_v2sf_v2sf
;
18221 tree void_ftype_pdi_di_di
;
18222 tree void_ftype_pv16qi_v16qi_v16qi
;
18223 tree void_ftype_pv8hi_v8hi_v8hi
;
18224 tree void_ftype_pv4si_v4si_v4si
;
18225 tree void_ftype_pv4sf_v4sf_v4sf
;
18226 tree void_ftype_pv2di_v2di_v2di
;
18228 tree reinterp_ftype_dreg
[5][5];
18229 tree reinterp_ftype_qreg
[5][5];
18230 tree dreg_types
[5], qreg_types
[5];
18232 /* Create distinguished type nodes for NEON vector element types,
18233 and pointers to values of such types, so we can detect them later. */
18234 neon_intQI_type_node
= make_signed_type (GET_MODE_PRECISION (QImode
));
18235 neon_intHI_type_node
= make_signed_type (GET_MODE_PRECISION (HImode
));
18236 neon_polyQI_type_node
= make_signed_type (GET_MODE_PRECISION (QImode
));
18237 neon_polyHI_type_node
= make_signed_type (GET_MODE_PRECISION (HImode
));
18238 neon_intSI_type_node
= make_signed_type (GET_MODE_PRECISION (SImode
));
18239 neon_intDI_type_node
= make_signed_type (GET_MODE_PRECISION (DImode
));
18240 neon_float_type_node
= make_node (REAL_TYPE
);
18241 TYPE_PRECISION (neon_float_type_node
) = FLOAT_TYPE_SIZE
;
18242 layout_type (neon_float_type_node
);
18244 /* Define typedefs which exactly correspond to the modes we are basing vector
18245 types on. If you change these names you'll need to change
18246 the table used by arm_mangle_type too. */
18247 (*lang_hooks
.types
.register_builtin_type
) (neon_intQI_type_node
,
18248 "__builtin_neon_qi");
18249 (*lang_hooks
.types
.register_builtin_type
) (neon_intHI_type_node
,
18250 "__builtin_neon_hi");
18251 (*lang_hooks
.types
.register_builtin_type
) (neon_intSI_type_node
,
18252 "__builtin_neon_si");
18253 (*lang_hooks
.types
.register_builtin_type
) (neon_float_type_node
,
18254 "__builtin_neon_sf");
18255 (*lang_hooks
.types
.register_builtin_type
) (neon_intDI_type_node
,
18256 "__builtin_neon_di");
18257 (*lang_hooks
.types
.register_builtin_type
) (neon_polyQI_type_node
,
18258 "__builtin_neon_poly8");
18259 (*lang_hooks
.types
.register_builtin_type
) (neon_polyHI_type_node
,
18260 "__builtin_neon_poly16");
18262 intQI_pointer_node
= build_pointer_type (neon_intQI_type_node
);
18263 intHI_pointer_node
= build_pointer_type (neon_intHI_type_node
);
18264 intSI_pointer_node
= build_pointer_type (neon_intSI_type_node
);
18265 intDI_pointer_node
= build_pointer_type (neon_intDI_type_node
);
18266 float_pointer_node
= build_pointer_type (neon_float_type_node
);
18268 /* Next create constant-qualified versions of the above types. */
18269 const_intQI_node
= build_qualified_type (neon_intQI_type_node
,
18271 const_intHI_node
= build_qualified_type (neon_intHI_type_node
,
18273 const_intSI_node
= build_qualified_type (neon_intSI_type_node
,
18275 const_intDI_node
= build_qualified_type (neon_intDI_type_node
,
18277 const_float_node
= build_qualified_type (neon_float_type_node
,
18280 const_intQI_pointer_node
= build_pointer_type (const_intQI_node
);
18281 const_intHI_pointer_node
= build_pointer_type (const_intHI_node
);
18282 const_intSI_pointer_node
= build_pointer_type (const_intSI_node
);
18283 const_intDI_pointer_node
= build_pointer_type (const_intDI_node
);
18284 const_float_pointer_node
= build_pointer_type (const_float_node
);
18286 /* Now create vector types based on our NEON element types. */
18287 /* 64-bit vectors. */
18289 build_vector_type_for_mode (neon_intQI_type_node
, V8QImode
);
18291 build_vector_type_for_mode (neon_intHI_type_node
, V4HImode
);
18293 build_vector_type_for_mode (neon_intSI_type_node
, V2SImode
);
18295 build_vector_type_for_mode (neon_float_type_node
, V2SFmode
);
18296 /* 128-bit vectors. */
18298 build_vector_type_for_mode (neon_intQI_type_node
, V16QImode
);
18300 build_vector_type_for_mode (neon_intHI_type_node
, V8HImode
);
18302 build_vector_type_for_mode (neon_intSI_type_node
, V4SImode
);
18304 build_vector_type_for_mode (neon_float_type_node
, V4SFmode
);
18306 build_vector_type_for_mode (neon_intDI_type_node
, V2DImode
);
18308 /* Unsigned integer types for various mode sizes. */
18309 intUQI_type_node
= make_unsigned_type (GET_MODE_PRECISION (QImode
));
18310 intUHI_type_node
= make_unsigned_type (GET_MODE_PRECISION (HImode
));
18311 intUSI_type_node
= make_unsigned_type (GET_MODE_PRECISION (SImode
));
18312 intUDI_type_node
= make_unsigned_type (GET_MODE_PRECISION (DImode
));
18314 (*lang_hooks
.types
.register_builtin_type
) (intUQI_type_node
,
18315 "__builtin_neon_uqi");
18316 (*lang_hooks
.types
.register_builtin_type
) (intUHI_type_node
,
18317 "__builtin_neon_uhi");
18318 (*lang_hooks
.types
.register_builtin_type
) (intUSI_type_node
,
18319 "__builtin_neon_usi");
18320 (*lang_hooks
.types
.register_builtin_type
) (intUDI_type_node
,
18321 "__builtin_neon_udi");
18323 /* Opaque integer types for structures of vectors. */
18324 intEI_type_node
= make_signed_type (GET_MODE_PRECISION (EImode
));
18325 intOI_type_node
= make_signed_type (GET_MODE_PRECISION (OImode
));
18326 intCI_type_node
= make_signed_type (GET_MODE_PRECISION (CImode
));
18327 intXI_type_node
= make_signed_type (GET_MODE_PRECISION (XImode
));
18329 (*lang_hooks
.types
.register_builtin_type
) (intTI_type_node
,
18330 "__builtin_neon_ti");
18331 (*lang_hooks
.types
.register_builtin_type
) (intEI_type_node
,
18332 "__builtin_neon_ei");
18333 (*lang_hooks
.types
.register_builtin_type
) (intOI_type_node
,
18334 "__builtin_neon_oi");
18335 (*lang_hooks
.types
.register_builtin_type
) (intCI_type_node
,
18336 "__builtin_neon_ci");
18337 (*lang_hooks
.types
.register_builtin_type
) (intXI_type_node
,
18338 "__builtin_neon_xi");
18340 /* Pointers to vector types. */
18341 V8QI_pointer_node
= build_pointer_type (V8QI_type_node
);
18342 V4HI_pointer_node
= build_pointer_type (V4HI_type_node
);
18343 V2SI_pointer_node
= build_pointer_type (V2SI_type_node
);
18344 V2SF_pointer_node
= build_pointer_type (V2SF_type_node
);
18345 V16QI_pointer_node
= build_pointer_type (V16QI_type_node
);
18346 V8HI_pointer_node
= build_pointer_type (V8HI_type_node
);
18347 V4SI_pointer_node
= build_pointer_type (V4SI_type_node
);
18348 V4SF_pointer_node
= build_pointer_type (V4SF_type_node
);
18349 V2DI_pointer_node
= build_pointer_type (V2DI_type_node
);
18351 /* Operations which return results as pairs. */
18352 void_ftype_pv8qi_v8qi_v8qi
=
18353 build_function_type_list (void_type_node
, V8QI_pointer_node
, V8QI_type_node
,
18354 V8QI_type_node
, NULL
);
18355 void_ftype_pv4hi_v4hi_v4hi
=
18356 build_function_type_list (void_type_node
, V4HI_pointer_node
, V4HI_type_node
,
18357 V4HI_type_node
, NULL
);
18358 void_ftype_pv2si_v2si_v2si
=
18359 build_function_type_list (void_type_node
, V2SI_pointer_node
, V2SI_type_node
,
18360 V2SI_type_node
, NULL
);
18361 void_ftype_pv2sf_v2sf_v2sf
=
18362 build_function_type_list (void_type_node
, V2SF_pointer_node
, V2SF_type_node
,
18363 V2SF_type_node
, NULL
);
18364 void_ftype_pdi_di_di
=
18365 build_function_type_list (void_type_node
, intDI_pointer_node
,
18366 neon_intDI_type_node
, neon_intDI_type_node
, NULL
);
18367 void_ftype_pv16qi_v16qi_v16qi
=
18368 build_function_type_list (void_type_node
, V16QI_pointer_node
,
18369 V16QI_type_node
, V16QI_type_node
, NULL
);
18370 void_ftype_pv8hi_v8hi_v8hi
=
18371 build_function_type_list (void_type_node
, V8HI_pointer_node
, V8HI_type_node
,
18372 V8HI_type_node
, NULL
);
18373 void_ftype_pv4si_v4si_v4si
=
18374 build_function_type_list (void_type_node
, V4SI_pointer_node
, V4SI_type_node
,
18375 V4SI_type_node
, NULL
);
18376 void_ftype_pv4sf_v4sf_v4sf
=
18377 build_function_type_list (void_type_node
, V4SF_pointer_node
, V4SF_type_node
,
18378 V4SF_type_node
, NULL
);
18379 void_ftype_pv2di_v2di_v2di
=
18380 build_function_type_list (void_type_node
, V2DI_pointer_node
, V2DI_type_node
,
18381 V2DI_type_node
, NULL
);
18383 dreg_types
[0] = V8QI_type_node
;
18384 dreg_types
[1] = V4HI_type_node
;
18385 dreg_types
[2] = V2SI_type_node
;
18386 dreg_types
[3] = V2SF_type_node
;
18387 dreg_types
[4] = neon_intDI_type_node
;
18389 qreg_types
[0] = V16QI_type_node
;
18390 qreg_types
[1] = V8HI_type_node
;
18391 qreg_types
[2] = V4SI_type_node
;
18392 qreg_types
[3] = V4SF_type_node
;
18393 qreg_types
[4] = V2DI_type_node
;
18395 for (i
= 0; i
< 5; i
++)
18398 for (j
= 0; j
< 5; j
++)
18400 reinterp_ftype_dreg
[i
][j
]
18401 = build_function_type_list (dreg_types
[i
], dreg_types
[j
], NULL
);
18402 reinterp_ftype_qreg
[i
][j
]
18403 = build_function_type_list (qreg_types
[i
], qreg_types
[j
], NULL
);
18407 for (i
= 0, fcode
= ARM_BUILTIN_NEON_BASE
;
18408 i
< ARRAY_SIZE (neon_builtin_data
);
18411 neon_builtin_datum
*d
= &neon_builtin_data
[i
];
18413 const char* const modenames
[] = {
18414 "v8qi", "v4hi", "v2si", "v2sf", "di",
18415 "v16qi", "v8hi", "v4si", "v4sf", "v2di",
18420 int is_load
= 0, is_store
= 0;
18422 gcc_assert (ARRAY_SIZE (modenames
) == T_MAX
);
18429 case NEON_LOAD1LANE
:
18430 case NEON_LOADSTRUCT
:
18431 case NEON_LOADSTRUCTLANE
:
18433 /* Fall through. */
18435 case NEON_STORE1LANE
:
18436 case NEON_STORESTRUCT
:
18437 case NEON_STORESTRUCTLANE
:
18440 /* Fall through. */
18443 case NEON_LOGICBINOP
:
18444 case NEON_SHIFTINSERT
:
18451 case NEON_SHIFTIMM
:
18452 case NEON_SHIFTACC
:
18458 case NEON_LANEMULL
:
18459 case NEON_LANEMULH
:
18461 case NEON_SCALARMUL
:
18462 case NEON_SCALARMULL
:
18463 case NEON_SCALARMULH
:
18464 case NEON_SCALARMAC
:
18470 tree return_type
= void_type_node
, args
= void_list_node
;
18472 /* Build a function type directly from the insn_data for
18473 this builtin. The build_function_type() function takes
18474 care of removing duplicates for us. */
18475 for (k
= insn_data
[d
->code
].n_generator_args
- 1; k
>= 0; k
--)
18479 if (is_load
&& k
== 1)
18481 /* Neon load patterns always have the memory
18482 operand in the operand 1 position. */
18483 gcc_assert (insn_data
[d
->code
].operand
[k
].predicate
18484 == neon_struct_operand
);
18490 eltype
= const_intQI_pointer_node
;
18495 eltype
= const_intHI_pointer_node
;
18500 eltype
= const_intSI_pointer_node
;
18505 eltype
= const_float_pointer_node
;
18510 eltype
= const_intDI_pointer_node
;
18513 default: gcc_unreachable ();
18516 else if (is_store
&& k
== 0)
18518 /* Similarly, Neon store patterns use operand 0 as
18519 the memory location to store to. */
18520 gcc_assert (insn_data
[d
->code
].operand
[k
].predicate
18521 == neon_struct_operand
);
18527 eltype
= intQI_pointer_node
;
18532 eltype
= intHI_pointer_node
;
18537 eltype
= intSI_pointer_node
;
18542 eltype
= float_pointer_node
;
18547 eltype
= intDI_pointer_node
;
18550 default: gcc_unreachable ();
18555 switch (insn_data
[d
->code
].operand
[k
].mode
)
18557 case VOIDmode
: eltype
= void_type_node
; break;
18559 case QImode
: eltype
= neon_intQI_type_node
; break;
18560 case HImode
: eltype
= neon_intHI_type_node
; break;
18561 case SImode
: eltype
= neon_intSI_type_node
; break;
18562 case SFmode
: eltype
= neon_float_type_node
; break;
18563 case DImode
: eltype
= neon_intDI_type_node
; break;
18564 case TImode
: eltype
= intTI_type_node
; break;
18565 case EImode
: eltype
= intEI_type_node
; break;
18566 case OImode
: eltype
= intOI_type_node
; break;
18567 case CImode
: eltype
= intCI_type_node
; break;
18568 case XImode
: eltype
= intXI_type_node
; break;
18569 /* 64-bit vectors. */
18570 case V8QImode
: eltype
= V8QI_type_node
; break;
18571 case V4HImode
: eltype
= V4HI_type_node
; break;
18572 case V2SImode
: eltype
= V2SI_type_node
; break;
18573 case V2SFmode
: eltype
= V2SF_type_node
; break;
18574 /* 128-bit vectors. */
18575 case V16QImode
: eltype
= V16QI_type_node
; break;
18576 case V8HImode
: eltype
= V8HI_type_node
; break;
18577 case V4SImode
: eltype
= V4SI_type_node
; break;
18578 case V4SFmode
: eltype
= V4SF_type_node
; break;
18579 case V2DImode
: eltype
= V2DI_type_node
; break;
18580 default: gcc_unreachable ();
18584 if (k
== 0 && !is_store
)
18585 return_type
= eltype
;
18587 args
= tree_cons (NULL_TREE
, eltype
, args
);
18590 ftype
= build_function_type (return_type
, args
);
18594 case NEON_RESULTPAIR
:
18596 switch (insn_data
[d
->code
].operand
[1].mode
)
18598 case V8QImode
: ftype
= void_ftype_pv8qi_v8qi_v8qi
; break;
18599 case V4HImode
: ftype
= void_ftype_pv4hi_v4hi_v4hi
; break;
18600 case V2SImode
: ftype
= void_ftype_pv2si_v2si_v2si
; break;
18601 case V2SFmode
: ftype
= void_ftype_pv2sf_v2sf_v2sf
; break;
18602 case DImode
: ftype
= void_ftype_pdi_di_di
; break;
18603 case V16QImode
: ftype
= void_ftype_pv16qi_v16qi_v16qi
; break;
18604 case V8HImode
: ftype
= void_ftype_pv8hi_v8hi_v8hi
; break;
18605 case V4SImode
: ftype
= void_ftype_pv4si_v4si_v4si
; break;
18606 case V4SFmode
: ftype
= void_ftype_pv4sf_v4sf_v4sf
; break;
18607 case V2DImode
: ftype
= void_ftype_pv2di_v2di_v2di
; break;
18608 default: gcc_unreachable ();
18613 case NEON_REINTERP
:
18615 /* We iterate over 5 doubleword types, then 5 quadword
18617 int rhs
= d
->mode
% 5;
18618 switch (insn_data
[d
->code
].operand
[0].mode
)
18620 case V8QImode
: ftype
= reinterp_ftype_dreg
[0][rhs
]; break;
18621 case V4HImode
: ftype
= reinterp_ftype_dreg
[1][rhs
]; break;
18622 case V2SImode
: ftype
= reinterp_ftype_dreg
[2][rhs
]; break;
18623 case V2SFmode
: ftype
= reinterp_ftype_dreg
[3][rhs
]; break;
18624 case DImode
: ftype
= reinterp_ftype_dreg
[4][rhs
]; break;
18625 case V16QImode
: ftype
= reinterp_ftype_qreg
[0][rhs
]; break;
18626 case V8HImode
: ftype
= reinterp_ftype_qreg
[1][rhs
]; break;
18627 case V4SImode
: ftype
= reinterp_ftype_qreg
[2][rhs
]; break;
18628 case V4SFmode
: ftype
= reinterp_ftype_qreg
[3][rhs
]; break;
18629 case V2DImode
: ftype
= reinterp_ftype_qreg
[4][rhs
]; break;
18630 default: gcc_unreachable ();
18636 gcc_unreachable ();
18639 gcc_assert (ftype
!= NULL
);
18641 sprintf (namebuf
, "__builtin_neon_%s%s", d
->name
, modenames
[d
->mode
]);
18643 decl
= add_builtin_function (namebuf
, ftype
, fcode
, BUILT_IN_MD
, NULL
,
18645 arm_builtin_decls
[fcode
] = decl
;
18649 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
18652 if ((MASK) & insn_flags) \
18655 bdecl = add_builtin_function ((NAME), (TYPE), (CODE), \
18656 BUILT_IN_MD, NULL, NULL_TREE); \
18657 arm_builtin_decls[CODE] = bdecl; \
18662 struct builtin_description
18664 const unsigned int mask
;
18665 const enum insn_code icode
;
18666 const char * const name
;
18667 const enum arm_builtins code
;
18668 const enum rtx_code comparison
;
18669 const unsigned int flag
;
18672 static const struct builtin_description bdesc_2arg
[] =
18674 #define IWMMXT_BUILTIN(code, string, builtin) \
18675 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
18676 ARM_BUILTIN_##builtin, UNKNOWN, 0 },
18678 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
18679 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
18680 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
18681 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
18682 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
18683 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
18684 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
18685 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
18686 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
18687 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
18688 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
18689 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
18690 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
18691 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
18692 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
18693 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
18694 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
18695 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
18696 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
18697 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsm", WMULSM
)
18698 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmulum", WMULUM
)
18699 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
18700 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
18701 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
18702 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
18703 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
18704 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
18705 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
18706 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
18707 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
18708 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
18709 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
18710 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
18711 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
18712 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
18713 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
18714 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
18715 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
18716 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
18717 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
18718 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
18719 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
18720 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
18721 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
18722 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
18723 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
18724 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
18725 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
18726 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
18727 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
18728 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
18729 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
18730 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
18731 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
18732 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
18733 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
18734 IWMMXT_BUILTIN (iwmmxt_wmadds
, "wmadds", WMADDS
)
18735 IWMMXT_BUILTIN (iwmmxt_wmaddu
, "wmaddu", WMADDU
)
18737 #define IWMMXT_BUILTIN2(code, builtin) \
18738 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 },
18740 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
18741 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
18742 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
18743 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
18744 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
18745 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
18746 IWMMXT_BUILTIN2 (ashlv4hi3_di
, WSLLH
)
18747 IWMMXT_BUILTIN2 (ashlv4hi3_iwmmxt
, WSLLHI
)
18748 IWMMXT_BUILTIN2 (ashlv2si3_di
, WSLLW
)
18749 IWMMXT_BUILTIN2 (ashlv2si3_iwmmxt
, WSLLWI
)
18750 IWMMXT_BUILTIN2 (ashldi3_di
, WSLLD
)
18751 IWMMXT_BUILTIN2 (ashldi3_iwmmxt
, WSLLDI
)
18752 IWMMXT_BUILTIN2 (lshrv4hi3_di
, WSRLH
)
18753 IWMMXT_BUILTIN2 (lshrv4hi3_iwmmxt
, WSRLHI
)
18754 IWMMXT_BUILTIN2 (lshrv2si3_di
, WSRLW
)
18755 IWMMXT_BUILTIN2 (lshrv2si3_iwmmxt
, WSRLWI
)
18756 IWMMXT_BUILTIN2 (lshrdi3_di
, WSRLD
)
18757 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt
, WSRLDI
)
18758 IWMMXT_BUILTIN2 (ashrv4hi3_di
, WSRAH
)
18759 IWMMXT_BUILTIN2 (ashrv4hi3_iwmmxt
, WSRAHI
)
18760 IWMMXT_BUILTIN2 (ashrv2si3_di
, WSRAW
)
18761 IWMMXT_BUILTIN2 (ashrv2si3_iwmmxt
, WSRAWI
)
18762 IWMMXT_BUILTIN2 (ashrdi3_di
, WSRAD
)
18763 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt
, WSRADI
)
18764 IWMMXT_BUILTIN2 (rorv4hi3_di
, WRORH
)
18765 IWMMXT_BUILTIN2 (rorv4hi3
, WRORHI
)
18766 IWMMXT_BUILTIN2 (rorv2si3_di
, WRORW
)
18767 IWMMXT_BUILTIN2 (rorv2si3
, WRORWI
)
18768 IWMMXT_BUILTIN2 (rordi3_di
, WRORD
)
18769 IWMMXT_BUILTIN2 (rordi3
, WRORDI
)
18770 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
18771 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
18774 static const struct builtin_description bdesc_1arg
[] =
18776 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
18777 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
18778 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
18779 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
18780 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
18781 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
18782 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
18783 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
18784 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
18785 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
18786 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
18787 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
18788 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
18789 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
18790 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
18791 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
18792 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
18793 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
18796 /* Set up all the iWMMXt builtins. This is not called if
18797 TARGET_IWMMXT is zero. */
18800 arm_init_iwmmxt_builtins (void)
18802 const struct builtin_description
* d
;
18805 tree V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
18806 tree V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
18807 tree V8QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V8QImode
);
18810 = build_function_type_list (integer_type_node
,
18811 integer_type_node
, NULL_TREE
);
18812 tree v8qi_ftype_v8qi_v8qi_int
18813 = build_function_type_list (V8QI_type_node
,
18814 V8QI_type_node
, V8QI_type_node
,
18815 integer_type_node
, NULL_TREE
);
18816 tree v4hi_ftype_v4hi_int
18817 = build_function_type_list (V4HI_type_node
,
18818 V4HI_type_node
, integer_type_node
, NULL_TREE
);
18819 tree v2si_ftype_v2si_int
18820 = build_function_type_list (V2SI_type_node
,
18821 V2SI_type_node
, integer_type_node
, NULL_TREE
);
18822 tree v2si_ftype_di_di
18823 = build_function_type_list (V2SI_type_node
,
18824 long_long_integer_type_node
,
18825 long_long_integer_type_node
,
18827 tree di_ftype_di_int
18828 = build_function_type_list (long_long_integer_type_node
,
18829 long_long_integer_type_node
,
18830 integer_type_node
, NULL_TREE
);
18831 tree di_ftype_di_int_int
18832 = build_function_type_list (long_long_integer_type_node
,
18833 long_long_integer_type_node
,
18835 integer_type_node
, NULL_TREE
);
18836 tree int_ftype_v8qi
18837 = build_function_type_list (integer_type_node
,
18838 V8QI_type_node
, NULL_TREE
);
18839 tree int_ftype_v4hi
18840 = build_function_type_list (integer_type_node
,
18841 V4HI_type_node
, NULL_TREE
);
18842 tree int_ftype_v2si
18843 = build_function_type_list (integer_type_node
,
18844 V2SI_type_node
, NULL_TREE
);
18845 tree int_ftype_v8qi_int
18846 = build_function_type_list (integer_type_node
,
18847 V8QI_type_node
, integer_type_node
, NULL_TREE
);
18848 tree int_ftype_v4hi_int
18849 = build_function_type_list (integer_type_node
,
18850 V4HI_type_node
, integer_type_node
, NULL_TREE
);
18851 tree int_ftype_v2si_int
18852 = build_function_type_list (integer_type_node
,
18853 V2SI_type_node
, integer_type_node
, NULL_TREE
);
18854 tree v8qi_ftype_v8qi_int_int
18855 = build_function_type_list (V8QI_type_node
,
18856 V8QI_type_node
, integer_type_node
,
18857 integer_type_node
, NULL_TREE
);
18858 tree v4hi_ftype_v4hi_int_int
18859 = build_function_type_list (V4HI_type_node
,
18860 V4HI_type_node
, integer_type_node
,
18861 integer_type_node
, NULL_TREE
);
18862 tree v2si_ftype_v2si_int_int
18863 = build_function_type_list (V2SI_type_node
,
18864 V2SI_type_node
, integer_type_node
,
18865 integer_type_node
, NULL_TREE
);
18866 /* Miscellaneous. */
18867 tree v8qi_ftype_v4hi_v4hi
18868 = build_function_type_list (V8QI_type_node
,
18869 V4HI_type_node
, V4HI_type_node
, NULL_TREE
);
18870 tree v4hi_ftype_v2si_v2si
18871 = build_function_type_list (V4HI_type_node
,
18872 V2SI_type_node
, V2SI_type_node
, NULL_TREE
);
18873 tree v2si_ftype_v4hi_v4hi
18874 = build_function_type_list (V2SI_type_node
,
18875 V4HI_type_node
, V4HI_type_node
, NULL_TREE
);
18876 tree v2si_ftype_v8qi_v8qi
18877 = build_function_type_list (V2SI_type_node
,
18878 V8QI_type_node
, V8QI_type_node
, NULL_TREE
);
18879 tree v4hi_ftype_v4hi_di
18880 = build_function_type_list (V4HI_type_node
,
18881 V4HI_type_node
, long_long_integer_type_node
,
18883 tree v2si_ftype_v2si_di
18884 = build_function_type_list (V2SI_type_node
,
18885 V2SI_type_node
, long_long_integer_type_node
,
18887 tree void_ftype_int_int
18888 = build_function_type_list (void_type_node
,
18889 integer_type_node
, integer_type_node
,
18892 = build_function_type_list (long_long_unsigned_type_node
, NULL_TREE
);
18894 = build_function_type_list (long_long_integer_type_node
,
18895 V8QI_type_node
, NULL_TREE
);
18897 = build_function_type_list (long_long_integer_type_node
,
18898 V4HI_type_node
, NULL_TREE
);
18900 = build_function_type_list (long_long_integer_type_node
,
18901 V2SI_type_node
, NULL_TREE
);
18902 tree v2si_ftype_v4hi
18903 = build_function_type_list (V2SI_type_node
,
18904 V4HI_type_node
, NULL_TREE
);
18905 tree v4hi_ftype_v8qi
18906 = build_function_type_list (V4HI_type_node
,
18907 V8QI_type_node
, NULL_TREE
);
18909 tree di_ftype_di_v4hi_v4hi
18910 = build_function_type_list (long_long_unsigned_type_node
,
18911 long_long_unsigned_type_node
,
18912 V4HI_type_node
, V4HI_type_node
,
18915 tree di_ftype_v4hi_v4hi
18916 = build_function_type_list (long_long_unsigned_type_node
,
18917 V4HI_type_node
,V4HI_type_node
,
18920 /* Normal vector binops. */
18921 tree v8qi_ftype_v8qi_v8qi
18922 = build_function_type_list (V8QI_type_node
,
18923 V8QI_type_node
, V8QI_type_node
, NULL_TREE
);
18924 tree v4hi_ftype_v4hi_v4hi
18925 = build_function_type_list (V4HI_type_node
,
18926 V4HI_type_node
,V4HI_type_node
, NULL_TREE
);
18927 tree v2si_ftype_v2si_v2si
18928 = build_function_type_list (V2SI_type_node
,
18929 V2SI_type_node
, V2SI_type_node
, NULL_TREE
);
18930 tree di_ftype_di_di
18931 = build_function_type_list (long_long_unsigned_type_node
,
18932 long_long_unsigned_type_node
,
18933 long_long_unsigned_type_node
,
18936 /* Add all builtins that are more or less simple operations on two
18938 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
18940 /* Use one of the operands; the target can have a different mode for
18941 mask-generating compares. */
18942 enum machine_mode mode
;
18948 mode
= insn_data
[d
->icode
].operand
[1].mode
;
18953 type
= v8qi_ftype_v8qi_v8qi
;
18956 type
= v4hi_ftype_v4hi_v4hi
;
18959 type
= v2si_ftype_v2si_v2si
;
18962 type
= di_ftype_di_di
;
18966 gcc_unreachable ();
18969 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
18972 /* Add the remaining MMX insns with somewhat more complicated types. */
18973 #define iwmmx_mbuiltin(NAME, TYPE, CODE) \
18974 def_mbuiltin (FL_IWMMXT, "__builtin_arm_" NAME, (TYPE), \
18975 ARM_BUILTIN_ ## CODE)
18977 iwmmx_mbuiltin ("wzero", di_ftype_void
, WZERO
);
18978 iwmmx_mbuiltin ("setwcx", void_ftype_int_int
, SETWCX
);
18979 iwmmx_mbuiltin ("getwcx", int_ftype_int
, GETWCX
);
18981 iwmmx_mbuiltin ("wsllh", v4hi_ftype_v4hi_di
, WSLLH
);
18982 iwmmx_mbuiltin ("wsllw", v2si_ftype_v2si_di
, WSLLW
);
18983 iwmmx_mbuiltin ("wslld", di_ftype_di_di
, WSLLD
);
18984 iwmmx_mbuiltin ("wsllhi", v4hi_ftype_v4hi_int
, WSLLHI
);
18985 iwmmx_mbuiltin ("wsllwi", v2si_ftype_v2si_int
, WSLLWI
);
18986 iwmmx_mbuiltin ("wslldi", di_ftype_di_int
, WSLLDI
);
18988 iwmmx_mbuiltin ("wsrlh", v4hi_ftype_v4hi_di
, WSRLH
);
18989 iwmmx_mbuiltin ("wsrlw", v2si_ftype_v2si_di
, WSRLW
);
18990 iwmmx_mbuiltin ("wsrld", di_ftype_di_di
, WSRLD
);
18991 iwmmx_mbuiltin ("wsrlhi", v4hi_ftype_v4hi_int
, WSRLHI
);
18992 iwmmx_mbuiltin ("wsrlwi", v2si_ftype_v2si_int
, WSRLWI
);
18993 iwmmx_mbuiltin ("wsrldi", di_ftype_di_int
, WSRLDI
);
18995 iwmmx_mbuiltin ("wsrah", v4hi_ftype_v4hi_di
, WSRAH
);
18996 iwmmx_mbuiltin ("wsraw", v2si_ftype_v2si_di
, WSRAW
);
18997 iwmmx_mbuiltin ("wsrad", di_ftype_di_di
, WSRAD
);
18998 iwmmx_mbuiltin ("wsrahi", v4hi_ftype_v4hi_int
, WSRAHI
);
18999 iwmmx_mbuiltin ("wsrawi", v2si_ftype_v2si_int
, WSRAWI
);
19000 iwmmx_mbuiltin ("wsradi", di_ftype_di_int
, WSRADI
);
19002 iwmmx_mbuiltin ("wrorh", v4hi_ftype_v4hi_di
, WRORH
);
19003 iwmmx_mbuiltin ("wrorw", v2si_ftype_v2si_di
, WRORW
);
19004 iwmmx_mbuiltin ("wrord", di_ftype_di_di
, WRORD
);
19005 iwmmx_mbuiltin ("wrorhi", v4hi_ftype_v4hi_int
, WRORHI
);
19006 iwmmx_mbuiltin ("wrorwi", v2si_ftype_v2si_int
, WRORWI
);
19007 iwmmx_mbuiltin ("wrordi", di_ftype_di_int
, WRORDI
);
19009 iwmmx_mbuiltin ("wshufh", v4hi_ftype_v4hi_int
, WSHUFH
);
19011 iwmmx_mbuiltin ("wsadb", v2si_ftype_v8qi_v8qi
, WSADB
);
19012 iwmmx_mbuiltin ("wsadh", v2si_ftype_v4hi_v4hi
, WSADH
);
19013 iwmmx_mbuiltin ("wsadbz", v2si_ftype_v8qi_v8qi
, WSADBZ
);
19014 iwmmx_mbuiltin ("wsadhz", v2si_ftype_v4hi_v4hi
, WSADHZ
);
19016 iwmmx_mbuiltin ("textrmsb", int_ftype_v8qi_int
, TEXTRMSB
);
19017 iwmmx_mbuiltin ("textrmsh", int_ftype_v4hi_int
, TEXTRMSH
);
19018 iwmmx_mbuiltin ("textrmsw", int_ftype_v2si_int
, TEXTRMSW
);
19019 iwmmx_mbuiltin ("textrmub", int_ftype_v8qi_int
, TEXTRMUB
);
19020 iwmmx_mbuiltin ("textrmuh", int_ftype_v4hi_int
, TEXTRMUH
);
19021 iwmmx_mbuiltin ("textrmuw", int_ftype_v2si_int
, TEXTRMUW
);
19022 iwmmx_mbuiltin ("tinsrb", v8qi_ftype_v8qi_int_int
, TINSRB
);
19023 iwmmx_mbuiltin ("tinsrh", v4hi_ftype_v4hi_int_int
, TINSRH
);
19024 iwmmx_mbuiltin ("tinsrw", v2si_ftype_v2si_int_int
, TINSRW
);
19026 iwmmx_mbuiltin ("waccb", di_ftype_v8qi
, WACCB
);
19027 iwmmx_mbuiltin ("wacch", di_ftype_v4hi
, WACCH
);
19028 iwmmx_mbuiltin ("waccw", di_ftype_v2si
, WACCW
);
19030 iwmmx_mbuiltin ("tmovmskb", int_ftype_v8qi
, TMOVMSKB
);
19031 iwmmx_mbuiltin ("tmovmskh", int_ftype_v4hi
, TMOVMSKH
);
19032 iwmmx_mbuiltin ("tmovmskw", int_ftype_v2si
, TMOVMSKW
);
19034 iwmmx_mbuiltin ("wpackhss", v8qi_ftype_v4hi_v4hi
, WPACKHSS
);
19035 iwmmx_mbuiltin ("wpackhus", v8qi_ftype_v4hi_v4hi
, WPACKHUS
);
19036 iwmmx_mbuiltin ("wpackwus", v4hi_ftype_v2si_v2si
, WPACKWUS
);
19037 iwmmx_mbuiltin ("wpackwss", v4hi_ftype_v2si_v2si
, WPACKWSS
);
19038 iwmmx_mbuiltin ("wpackdus", v2si_ftype_di_di
, WPACKDUS
);
19039 iwmmx_mbuiltin ("wpackdss", v2si_ftype_di_di
, WPACKDSS
);
19041 iwmmx_mbuiltin ("wunpckehub", v4hi_ftype_v8qi
, WUNPCKEHUB
);
19042 iwmmx_mbuiltin ("wunpckehuh", v2si_ftype_v4hi
, WUNPCKEHUH
);
19043 iwmmx_mbuiltin ("wunpckehuw", di_ftype_v2si
, WUNPCKEHUW
);
19044 iwmmx_mbuiltin ("wunpckehsb", v4hi_ftype_v8qi
, WUNPCKEHSB
);
19045 iwmmx_mbuiltin ("wunpckehsh", v2si_ftype_v4hi
, WUNPCKEHSH
);
19046 iwmmx_mbuiltin ("wunpckehsw", di_ftype_v2si
, WUNPCKEHSW
);
19047 iwmmx_mbuiltin ("wunpckelub", v4hi_ftype_v8qi
, WUNPCKELUB
);
19048 iwmmx_mbuiltin ("wunpckeluh", v2si_ftype_v4hi
, WUNPCKELUH
);
19049 iwmmx_mbuiltin ("wunpckeluw", di_ftype_v2si
, WUNPCKELUW
);
19050 iwmmx_mbuiltin ("wunpckelsb", v4hi_ftype_v8qi
, WUNPCKELSB
);
19051 iwmmx_mbuiltin ("wunpckelsh", v2si_ftype_v4hi
, WUNPCKELSH
);
19052 iwmmx_mbuiltin ("wunpckelsw", di_ftype_v2si
, WUNPCKELSW
);
19054 iwmmx_mbuiltin ("wmacs", di_ftype_di_v4hi_v4hi
, WMACS
);
19055 iwmmx_mbuiltin ("wmacsz", di_ftype_v4hi_v4hi
, WMACSZ
);
19056 iwmmx_mbuiltin ("wmacu", di_ftype_di_v4hi_v4hi
, WMACU
);
19057 iwmmx_mbuiltin ("wmacuz", di_ftype_v4hi_v4hi
, WMACUZ
);
19059 iwmmx_mbuiltin ("walign", v8qi_ftype_v8qi_v8qi_int
, WALIGN
);
19060 iwmmx_mbuiltin ("tmia", di_ftype_di_int_int
, TMIA
);
19061 iwmmx_mbuiltin ("tmiaph", di_ftype_di_int_int
, TMIAPH
);
19062 iwmmx_mbuiltin ("tmiabb", di_ftype_di_int_int
, TMIABB
);
19063 iwmmx_mbuiltin ("tmiabt", di_ftype_di_int_int
, TMIABT
);
19064 iwmmx_mbuiltin ("tmiatb", di_ftype_di_int_int
, TMIATB
);
19065 iwmmx_mbuiltin ("tmiatt", di_ftype_di_int_int
, TMIATT
);
19067 #undef iwmmx_mbuiltin
19071 arm_init_tls_builtins (void)
19075 ftype
= build_function_type (ptr_type_node
, void_list_node
);
19076 decl
= add_builtin_function ("__builtin_thread_pointer", ftype
,
19077 ARM_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
19079 TREE_NOTHROW (decl
) = 1;
19080 TREE_READONLY (decl
) = 1;
19081 arm_builtin_decls
[ARM_BUILTIN_THREAD_POINTER
] = decl
;
19085 arm_init_fp16_builtins (void)
19087 tree fp16_type
= make_node (REAL_TYPE
);
19088 TYPE_PRECISION (fp16_type
) = 16;
19089 layout_type (fp16_type
);
19090 (*lang_hooks
.types
.register_builtin_type
) (fp16_type
, "__fp16");
19094 arm_init_builtins (void)
19096 arm_init_tls_builtins ();
19098 if (TARGET_REALLY_IWMMXT
)
19099 arm_init_iwmmxt_builtins ();
19102 arm_init_neon_builtins ();
19104 if (arm_fp16_format
)
19105 arm_init_fp16_builtins ();
19108 /* Return the ARM builtin for CODE. */
19111 arm_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
19113 if (code
>= ARM_BUILTIN_MAX
)
19114 return error_mark_node
;
19116 return arm_builtin_decls
[code
];
19119 /* Implement TARGET_INVALID_PARAMETER_TYPE. */
19121 static const char *
19122 arm_invalid_parameter_type (const_tree t
)
19124 if (SCALAR_FLOAT_TYPE_P (t
) && TYPE_PRECISION (t
) == 16)
19125 return N_("function parameters cannot have __fp16 type");
19129 /* Implement TARGET_INVALID_PARAMETER_TYPE. */
19131 static const char *
19132 arm_invalid_return_type (const_tree t
)
19134 if (SCALAR_FLOAT_TYPE_P (t
) && TYPE_PRECISION (t
) == 16)
19135 return N_("functions cannot return __fp16 type");
19139 /* Implement TARGET_PROMOTED_TYPE. */
19142 arm_promoted_type (const_tree t
)
19144 if (SCALAR_FLOAT_TYPE_P (t
) && TYPE_PRECISION (t
) == 16)
19145 return float_type_node
;
19149 /* Implement TARGET_CONVERT_TO_TYPE.
19150 Specifically, this hook implements the peculiarity of the ARM
19151 half-precision floating-point C semantics that requires conversions between
19152 __fp16 to or from double to do an intermediate conversion to float. */
19155 arm_convert_to_type (tree type
, tree expr
)
19157 tree fromtype
= TREE_TYPE (expr
);
19158 if (!SCALAR_FLOAT_TYPE_P (fromtype
) || !SCALAR_FLOAT_TYPE_P (type
))
19160 if ((TYPE_PRECISION (fromtype
) == 16 && TYPE_PRECISION (type
) > 32)
19161 || (TYPE_PRECISION (type
) == 16 && TYPE_PRECISION (fromtype
) > 32))
19162 return convert (type
, convert (float_type_node
, expr
));
19166 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P.
19167 This simply adds HFmode as a supported mode; even though we don't
19168 implement arithmetic on this type directly, it's supported by
19169 optabs conversions, much the way the double-word arithmetic is
19170 special-cased in the default hook. */
19173 arm_scalar_mode_supported_p (enum machine_mode mode
)
19175 if (mode
== HFmode
)
19176 return (arm_fp16_format
!= ARM_FP16_FORMAT_NONE
);
19178 return default_scalar_mode_supported_p (mode
);
19181 /* Errors in the source file can cause expand_expr to return const0_rtx
19182 where we expect a vector. To avoid crashing, use one of the vector
19183 clear instructions. */
19186 safe_vector_operand (rtx x
, enum machine_mode mode
)
19188 if (x
!= const0_rtx
)
19190 x
= gen_reg_rtx (mode
);
19192 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
19193 : gen_rtx_SUBREG (DImode
, x
, 0)));
19197 /* Subroutine of arm_expand_builtin to take care of binop insns. */
19200 arm_expand_binop_builtin (enum insn_code icode
,
19201 tree exp
, rtx target
)
19204 tree arg0
= CALL_EXPR_ARG (exp
, 0);
19205 tree arg1
= CALL_EXPR_ARG (exp
, 1);
19206 rtx op0
= expand_normal (arg0
);
19207 rtx op1
= expand_normal (arg1
);
19208 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
19209 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
19210 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
19212 if (VECTOR_MODE_P (mode0
))
19213 op0
= safe_vector_operand (op0
, mode0
);
19214 if (VECTOR_MODE_P (mode1
))
19215 op1
= safe_vector_operand (op1
, mode1
);
19218 || GET_MODE (target
) != tmode
19219 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
19220 target
= gen_reg_rtx (tmode
);
19222 gcc_assert (GET_MODE (op0
) == mode0
&& GET_MODE (op1
) == mode1
);
19224 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
19225 op0
= copy_to_mode_reg (mode0
, op0
);
19226 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
19227 op1
= copy_to_mode_reg (mode1
, op1
);
19229 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
19236 /* Subroutine of arm_expand_builtin to take care of unop insns. */
19239 arm_expand_unop_builtin (enum insn_code icode
,
19240 tree exp
, rtx target
, int do_load
)
19243 tree arg0
= CALL_EXPR_ARG (exp
, 0);
19244 rtx op0
= expand_normal (arg0
);
19245 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
19246 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
19249 || GET_MODE (target
) != tmode
19250 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
19251 target
= gen_reg_rtx (tmode
);
19253 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
19256 if (VECTOR_MODE_P (mode0
))
19257 op0
= safe_vector_operand (op0
, mode0
);
19259 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
19260 op0
= copy_to_mode_reg (mode0
, op0
);
19263 pat
= GEN_FCN (icode
) (target
, op0
);
19271 NEON_ARG_COPY_TO_REG
,
19277 #define NEON_MAX_BUILTIN_ARGS 5
19279 /* EXP is a pointer argument to a Neon load or store intrinsic. Derive
19280 and return an expression for the accessed memory.
19282 The intrinsic function operates on a block of registers that has
19283 mode REG_MODE. This block contains vectors of type TYPE_MODE.
19284 The function references the memory at EXP in mode MEM_MODE;
19285 this mode may be BLKmode if no more suitable mode is available. */
19288 neon_dereference_pointer (tree exp
, enum machine_mode mem_mode
,
19289 enum machine_mode reg_mode
,
19290 neon_builtin_type_mode type_mode
)
19292 HOST_WIDE_INT reg_size
, vector_size
, nvectors
, nelems
;
19293 tree elem_type
, upper_bound
, array_type
;
19295 /* Work out the size of the register block in bytes. */
19296 reg_size
= GET_MODE_SIZE (reg_mode
);
19298 /* Work out the size of each vector in bytes. */
19299 gcc_assert (TYPE_MODE_BIT (type_mode
) & (TB_DREG
| TB_QREG
));
19300 vector_size
= (TYPE_MODE_BIT (type_mode
) & TB_QREG
? 16 : 8);
19302 /* Work out how many vectors there are. */
19303 gcc_assert (reg_size
% vector_size
== 0);
19304 nvectors
= reg_size
/ vector_size
;
19306 /* Work out how many elements are being loaded or stored.
19307 MEM_MODE == REG_MODE implies a one-to-one mapping between register
19308 and memory elements; anything else implies a lane load or store. */
19309 if (mem_mode
== reg_mode
)
19310 nelems
= vector_size
* nvectors
;
19314 /* Work out the type of each element. */
19315 gcc_assert (POINTER_TYPE_P (TREE_TYPE (exp
)));
19316 elem_type
= TREE_TYPE (TREE_TYPE (exp
));
19318 /* Create a type that describes the full access. */
19319 upper_bound
= build_int_cst (size_type_node
, nelems
- 1);
19320 array_type
= build_array_type (elem_type
, build_index_type (upper_bound
));
19322 /* Dereference EXP using that type. */
19323 exp
= convert (build_pointer_type (array_type
), exp
);
19324 return fold_build2 (MEM_REF
, array_type
, exp
,
19325 build_int_cst (TREE_TYPE (exp
), 0));
19328 /* Expand a Neon builtin. */
19330 arm_expand_neon_args (rtx target
, int icode
, int have_retval
,
19331 neon_builtin_type_mode type_mode
,
19336 tree arg
[NEON_MAX_BUILTIN_ARGS
];
19337 rtx op
[NEON_MAX_BUILTIN_ARGS
];
19338 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
19339 enum machine_mode mode
[NEON_MAX_BUILTIN_ARGS
];
19340 enum machine_mode other_mode
;
19346 || GET_MODE (target
) != tmode
19347 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
)))
19348 target
= gen_reg_rtx (tmode
);
19350 va_start (ap
, exp
);
19354 builtin_arg thisarg
= (builtin_arg
) va_arg (ap
, int);
19356 if (thisarg
== NEON_ARG_STOP
)
19360 opno
= argc
+ have_retval
;
19361 mode
[argc
] = insn_data
[icode
].operand
[opno
].mode
;
19362 arg
[argc
] = CALL_EXPR_ARG (exp
, argc
);
19363 if (thisarg
== NEON_ARG_MEMORY
)
19365 other_mode
= insn_data
[icode
].operand
[1 - opno
].mode
;
19366 arg
[argc
] = neon_dereference_pointer (arg
[argc
], mode
[argc
],
19367 other_mode
, type_mode
);
19369 op
[argc
] = expand_normal (arg
[argc
]);
19373 case NEON_ARG_COPY_TO_REG
:
19374 /*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/
19375 if (!(*insn_data
[icode
].operand
[opno
].predicate
)
19376 (op
[argc
], mode
[argc
]))
19377 op
[argc
] = copy_to_mode_reg (mode
[argc
], op
[argc
]);
19380 case NEON_ARG_CONSTANT
:
19381 /* FIXME: This error message is somewhat unhelpful. */
19382 if (!(*insn_data
[icode
].operand
[opno
].predicate
)
19383 (op
[argc
], mode
[argc
]))
19384 error ("argument must be a constant");
19387 case NEON_ARG_MEMORY
:
19388 gcc_assert (MEM_P (op
[argc
]));
19389 PUT_MODE (op
[argc
], mode
[argc
]);
19390 /* ??? arm_neon.h uses the same built-in functions for signed
19391 and unsigned accesses, casting where necessary. This isn't
19393 set_mem_alias_set (op
[argc
], 0);
19394 if (!(*insn_data
[icode
].operand
[opno
].predicate
)
19395 (op
[argc
], mode
[argc
]))
19396 op
[argc
] = (replace_equiv_address
19397 (op
[argc
], force_reg (Pmode
, XEXP (op
[argc
], 0))));
19400 case NEON_ARG_STOP
:
19401 gcc_unreachable ();
19414 pat
= GEN_FCN (icode
) (target
, op
[0]);
19418 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
19422 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2]);
19426 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2], op
[3]);
19430 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2], op
[3], op
[4]);
19434 gcc_unreachable ();
19440 pat
= GEN_FCN (icode
) (op
[0]);
19444 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
19448 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
19452 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
19456 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3], op
[4]);
19460 gcc_unreachable ();
19471 /* Expand a Neon builtin. These are "special" because they don't have symbolic
19472 constants defined per-instruction or per instruction-variant. Instead, the
19473 required info is looked up in the table neon_builtin_data. */
19475 arm_expand_neon_builtin (int fcode
, tree exp
, rtx target
)
19477 neon_builtin_datum
*d
= &neon_builtin_data
[fcode
- ARM_BUILTIN_NEON_BASE
];
19478 neon_itype itype
= d
->itype
;
19479 enum insn_code icode
= d
->code
;
19480 neon_builtin_type_mode type_mode
= d
->mode
;
19487 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
,
19488 NEON_ARG_COPY_TO_REG
, NEON_ARG_CONSTANT
, NEON_ARG_STOP
);
19492 case NEON_SCALARMUL
:
19493 case NEON_SCALARMULL
:
19494 case NEON_SCALARMULH
:
19495 case NEON_SHIFTINSERT
:
19496 case NEON_LOGICBINOP
:
19497 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
,
19498 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_CONSTANT
,
19502 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
,
19503 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
,
19504 NEON_ARG_CONSTANT
, NEON_ARG_STOP
);
19508 case NEON_SHIFTIMM
:
19509 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
,
19510 NEON_ARG_COPY_TO_REG
, NEON_ARG_CONSTANT
, NEON_ARG_CONSTANT
,
19514 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
,
19515 NEON_ARG_COPY_TO_REG
, NEON_ARG_STOP
);
19519 case NEON_REINTERP
:
19520 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
,
19521 NEON_ARG_COPY_TO_REG
, NEON_ARG_STOP
);
19525 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
,
19526 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_STOP
);
19528 case NEON_RESULTPAIR
:
19529 return arm_expand_neon_args (target
, icode
, 0, type_mode
, exp
,
19530 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
,
19534 case NEON_LANEMULL
:
19535 case NEON_LANEMULH
:
19536 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
,
19537 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_CONSTANT
,
19538 NEON_ARG_CONSTANT
, NEON_ARG_STOP
);
19541 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
,
19542 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
,
19543 NEON_ARG_CONSTANT
, NEON_ARG_CONSTANT
, NEON_ARG_STOP
);
19545 case NEON_SHIFTACC
:
19546 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
,
19547 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_CONSTANT
,
19548 NEON_ARG_CONSTANT
, NEON_ARG_STOP
);
19550 case NEON_SCALARMAC
:
19551 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
,
19552 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
,
19553 NEON_ARG_CONSTANT
, NEON_ARG_STOP
);
19557 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
,
19558 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
,
19562 case NEON_LOADSTRUCT
:
19563 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
,
19564 NEON_ARG_MEMORY
, NEON_ARG_STOP
);
19566 case NEON_LOAD1LANE
:
19567 case NEON_LOADSTRUCTLANE
:
19568 return arm_expand_neon_args (target
, icode
, 1, type_mode
, exp
,
19569 NEON_ARG_MEMORY
, NEON_ARG_COPY_TO_REG
, NEON_ARG_CONSTANT
,
19573 case NEON_STORESTRUCT
:
19574 return arm_expand_neon_args (target
, icode
, 0, type_mode
, exp
,
19575 NEON_ARG_MEMORY
, NEON_ARG_COPY_TO_REG
, NEON_ARG_STOP
);
19577 case NEON_STORE1LANE
:
19578 case NEON_STORESTRUCTLANE
:
19579 return arm_expand_neon_args (target
, icode
, 0, type_mode
, exp
,
19580 NEON_ARG_MEMORY
, NEON_ARG_COPY_TO_REG
, NEON_ARG_CONSTANT
,
19584 gcc_unreachable ();
19587 /* Emit code to reinterpret one Neon type as another, without altering bits. */
19589 neon_reinterpret (rtx dest
, rtx src
)
19591 emit_move_insn (dest
, gen_lowpart (GET_MODE (dest
), src
));
19594 /* Emit code to place a Neon pair result in memory locations (with equal
19597 neon_emit_pair_result_insn (enum machine_mode mode
,
19598 rtx (*intfn
) (rtx
, rtx
, rtx
, rtx
), rtx destaddr
,
19601 rtx mem
= gen_rtx_MEM (mode
, destaddr
);
19602 rtx tmp1
= gen_reg_rtx (mode
);
19603 rtx tmp2
= gen_reg_rtx (mode
);
19605 emit_insn (intfn (tmp1
, op1
, op2
, tmp2
));
19607 emit_move_insn (mem
, tmp1
);
19608 mem
= adjust_address (mem
, mode
, GET_MODE_SIZE (mode
));
19609 emit_move_insn (mem
, tmp2
);
19612 /* Set up operands for a register copy from src to dest, taking care not to
19613 clobber registers in the process.
19614 FIXME: This has rather high polynomial complexity (O(n^3)?) but shouldn't
19615 be called with a large N, so that should be OK. */
19618 neon_disambiguate_copy (rtx
*operands
, rtx
*dest
, rtx
*src
, unsigned int count
)
19620 unsigned int copied
= 0, opctr
= 0;
19621 unsigned int done
= (1 << count
) - 1;
19624 while (copied
!= done
)
19626 for (i
= 0; i
< count
; i
++)
19630 for (j
= 0; good
&& j
< count
; j
++)
19631 if (i
!= j
&& (copied
& (1 << j
)) == 0
19632 && reg_overlap_mentioned_p (src
[j
], dest
[i
]))
19637 operands
[opctr
++] = dest
[i
];
19638 operands
[opctr
++] = src
[i
];
19644 gcc_assert (opctr
== count
* 2);
19647 /* Expand an expression EXP that calls a built-in function,
19648 with result going to TARGET if that's convenient
19649 (and in mode MODE if that's convenient).
19650 SUBTARGET may be used as the target for computing one of EXP's operands.
19651 IGNORE is nonzero if the value is to be ignored. */
19654 arm_expand_builtin (tree exp
,
19656 rtx subtarget ATTRIBUTE_UNUSED
,
19657 enum machine_mode mode ATTRIBUTE_UNUSED
,
19658 int ignore ATTRIBUTE_UNUSED
)
19660 const struct builtin_description
* d
;
19661 enum insn_code icode
;
19662 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
19670 int fcode
= DECL_FUNCTION_CODE (fndecl
);
19672 enum machine_mode tmode
;
19673 enum machine_mode mode0
;
19674 enum machine_mode mode1
;
19675 enum machine_mode mode2
;
19677 if (fcode
>= ARM_BUILTIN_NEON_BASE
)
19678 return arm_expand_neon_builtin (fcode
, exp
, target
);
19682 case ARM_BUILTIN_TEXTRMSB
:
19683 case ARM_BUILTIN_TEXTRMUB
:
19684 case ARM_BUILTIN_TEXTRMSH
:
19685 case ARM_BUILTIN_TEXTRMUH
:
19686 case ARM_BUILTIN_TEXTRMSW
:
19687 case ARM_BUILTIN_TEXTRMUW
:
19688 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
19689 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
19690 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
19691 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
19692 : CODE_FOR_iwmmxt_textrmw
);
19694 arg0
= CALL_EXPR_ARG (exp
, 0);
19695 arg1
= CALL_EXPR_ARG (exp
, 1);
19696 op0
= expand_normal (arg0
);
19697 op1
= expand_normal (arg1
);
19698 tmode
= insn_data
[icode
].operand
[0].mode
;
19699 mode0
= insn_data
[icode
].operand
[1].mode
;
19700 mode1
= insn_data
[icode
].operand
[2].mode
;
19702 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
19703 op0
= copy_to_mode_reg (mode0
, op0
);
19704 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
19706 /* @@@ better error message */
19707 error ("selector must be an immediate");
19708 return gen_reg_rtx (tmode
);
19711 || GET_MODE (target
) != tmode
19712 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
19713 target
= gen_reg_rtx (tmode
);
19714 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
19720 case ARM_BUILTIN_TINSRB
:
19721 case ARM_BUILTIN_TINSRH
:
19722 case ARM_BUILTIN_TINSRW
:
19723 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
19724 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
19725 : CODE_FOR_iwmmxt_tinsrw
);
19726 arg0
= CALL_EXPR_ARG (exp
, 0);
19727 arg1
= CALL_EXPR_ARG (exp
, 1);
19728 arg2
= CALL_EXPR_ARG (exp
, 2);
19729 op0
= expand_normal (arg0
);
19730 op1
= expand_normal (arg1
);
19731 op2
= expand_normal (arg2
);
19732 tmode
= insn_data
[icode
].operand
[0].mode
;
19733 mode0
= insn_data
[icode
].operand
[1].mode
;
19734 mode1
= insn_data
[icode
].operand
[2].mode
;
19735 mode2
= insn_data
[icode
].operand
[3].mode
;
19737 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
19738 op0
= copy_to_mode_reg (mode0
, op0
);
19739 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
19740 op1
= copy_to_mode_reg (mode1
, op1
);
19741 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
19743 /* @@@ better error message */
19744 error ("selector must be an immediate");
19748 || GET_MODE (target
) != tmode
19749 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
19750 target
= gen_reg_rtx (tmode
);
19751 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
19757 case ARM_BUILTIN_SETWCX
:
19758 arg0
= CALL_EXPR_ARG (exp
, 0);
19759 arg1
= CALL_EXPR_ARG (exp
, 1);
19760 op0
= force_reg (SImode
, expand_normal (arg0
));
19761 op1
= expand_normal (arg1
);
19762 emit_insn (gen_iwmmxt_tmcr (op1
, op0
));
19765 case ARM_BUILTIN_GETWCX
:
19766 arg0
= CALL_EXPR_ARG (exp
, 0);
19767 op0
= expand_normal (arg0
);
19768 target
= gen_reg_rtx (SImode
);
19769 emit_insn (gen_iwmmxt_tmrc (target
, op0
));
19772 case ARM_BUILTIN_WSHUFH
:
19773 icode
= CODE_FOR_iwmmxt_wshufh
;
19774 arg0
= CALL_EXPR_ARG (exp
, 0);
19775 arg1
= CALL_EXPR_ARG (exp
, 1);
19776 op0
= expand_normal (arg0
);
19777 op1
= expand_normal (arg1
);
19778 tmode
= insn_data
[icode
].operand
[0].mode
;
19779 mode1
= insn_data
[icode
].operand
[1].mode
;
19780 mode2
= insn_data
[icode
].operand
[2].mode
;
19782 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
19783 op0
= copy_to_mode_reg (mode1
, op0
);
19784 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
19786 /* @@@ better error message */
19787 error ("mask must be an immediate");
19791 || GET_MODE (target
) != tmode
19792 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
19793 target
= gen_reg_rtx (tmode
);
19794 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
19800 case ARM_BUILTIN_WSADB
:
19801 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb
, exp
, target
);
19802 case ARM_BUILTIN_WSADH
:
19803 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh
, exp
, target
);
19804 case ARM_BUILTIN_WSADBZ
:
19805 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, exp
, target
);
19806 case ARM_BUILTIN_WSADHZ
:
19807 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, exp
, target
);
19809 /* Several three-argument builtins. */
19810 case ARM_BUILTIN_WMACS
:
19811 case ARM_BUILTIN_WMACU
:
19812 case ARM_BUILTIN_WALIGN
:
19813 case ARM_BUILTIN_TMIA
:
19814 case ARM_BUILTIN_TMIAPH
:
19815 case ARM_BUILTIN_TMIATT
:
19816 case ARM_BUILTIN_TMIATB
:
19817 case ARM_BUILTIN_TMIABT
:
19818 case ARM_BUILTIN_TMIABB
:
19819 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
19820 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
19821 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
19822 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
19823 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
19824 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
19825 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
19826 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
19827 : CODE_FOR_iwmmxt_walign
);
19828 arg0
= CALL_EXPR_ARG (exp
, 0);
19829 arg1
= CALL_EXPR_ARG (exp
, 1);
19830 arg2
= CALL_EXPR_ARG (exp
, 2);
19831 op0
= expand_normal (arg0
);
19832 op1
= expand_normal (arg1
);
19833 op2
= expand_normal (arg2
);
19834 tmode
= insn_data
[icode
].operand
[0].mode
;
19835 mode0
= insn_data
[icode
].operand
[1].mode
;
19836 mode1
= insn_data
[icode
].operand
[2].mode
;
19837 mode2
= insn_data
[icode
].operand
[3].mode
;
19839 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
19840 op0
= copy_to_mode_reg (mode0
, op0
);
19841 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
19842 op1
= copy_to_mode_reg (mode1
, op1
);
19843 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
19844 op2
= copy_to_mode_reg (mode2
, op2
);
19846 || GET_MODE (target
) != tmode
19847 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
19848 target
= gen_reg_rtx (tmode
);
19849 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
19855 case ARM_BUILTIN_WZERO
:
19856 target
= gen_reg_rtx (DImode
);
19857 emit_insn (gen_iwmmxt_clrdi (target
));
19860 case ARM_BUILTIN_THREAD_POINTER
:
19861 return arm_load_tp (target
);
19867 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
19868 if (d
->code
== (const enum arm_builtins
) fcode
)
19869 return arm_expand_binop_builtin (d
->icode
, exp
, target
);
19871 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
19872 if (d
->code
== (const enum arm_builtins
) fcode
)
19873 return arm_expand_unop_builtin (d
->icode
, exp
, target
, 0);
19875 /* @@@ Should really do something sensible here. */
19879 /* Return the number (counting from 0) of
19880 the least significant set bit in MASK. */
19883 number_of_first_bit_set (unsigned mask
)
19888 (mask
& (1 << bit
)) == 0;
19895 /* Emit code to push or pop registers to or from the stack. F is the
19896 assembly file. MASK is the registers to push or pop. PUSH is
19897 nonzero if we should push, and zero if we should pop. For debugging
19898 output, if pushing, adjust CFA_OFFSET by the amount of space added
19899 to the stack. REAL_REGS should have the same number of bits set as
19900 MASK, and will be used instead (in the same order) to describe which
19901 registers were saved - this is used to mark the save slots when we
19902 push high registers after moving them to low registers. */
19904 thumb_pushpop (FILE *f
, unsigned long mask
, int push
, int *cfa_offset
,
19905 unsigned long real_regs
)
19908 int lo_mask
= mask
& 0xFF;
19909 int pushed_words
= 0;
19913 if (lo_mask
== 0 && !push
&& (mask
& (1 << PC_REGNUM
)))
19915 /* Special case. Do not generate a POP PC statement here, do it in
19917 thumb_exit (f
, -1);
19921 if (push
&& arm_except_unwind_info (&global_options
) == UI_TARGET
)
19923 fprintf (f
, "\t.save\t{");
19924 for (regno
= 0; regno
< 15; regno
++)
19926 if (real_regs
& (1 << regno
))
19928 if (real_regs
& ((1 << regno
) -1))
19930 asm_fprintf (f
, "%r", regno
);
19933 fprintf (f
, "}\n");
19936 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
19938 /* Look at the low registers first. */
19939 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
19943 asm_fprintf (f
, "%r", regno
);
19945 if ((lo_mask
& ~1) != 0)
19952 if (push
&& (mask
& (1 << LR_REGNUM
)))
19954 /* Catch pushing the LR. */
19958 asm_fprintf (f
, "%r", LR_REGNUM
);
19962 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
19964 /* Catch popping the PC. */
19965 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
19966 || crtl
->calls_eh_return
)
19968 /* The PC is never poped directly, instead
19969 it is popped into r3 and then BX is used. */
19970 fprintf (f
, "}\n");
19972 thumb_exit (f
, -1);
19981 asm_fprintf (f
, "%r", PC_REGNUM
);
19985 fprintf (f
, "}\n");
19987 if (push
&& pushed_words
&& dwarf2out_do_frame ())
19989 char *l
= dwarf2out_cfi_label (false);
19990 int pushed_mask
= real_regs
;
19992 *cfa_offset
+= pushed_words
* 4;
19993 dwarf2out_def_cfa (l
, SP_REGNUM
, *cfa_offset
);
19996 pushed_mask
= real_regs
;
19997 for (regno
= 0; regno
<= 14; regno
++, pushed_mask
>>= 1)
19999 if (pushed_mask
& 1)
20000 dwarf2out_reg_save (l
, regno
, 4 * pushed_words
++ - *cfa_offset
);
20005 /* Generate code to return from a thumb function.
20006 If 'reg_containing_return_addr' is -1, then the return address is
20007 actually on the stack, at the stack pointer. */
20009 thumb_exit (FILE *f
, int reg_containing_return_addr
)
20011 unsigned regs_available_for_popping
;
20012 unsigned regs_to_pop
;
20014 unsigned available
;
20018 int restore_a4
= FALSE
;
20020 /* Compute the registers we need to pop. */
20024 if (reg_containing_return_addr
== -1)
20026 regs_to_pop
|= 1 << LR_REGNUM
;
20030 if (TARGET_BACKTRACE
)
20032 /* Restore the (ARM) frame pointer and stack pointer. */
20033 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
20037 /* If there is nothing to pop then just emit the BX instruction and
20039 if (pops_needed
== 0)
20041 if (crtl
->calls_eh_return
)
20042 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
20044 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
20047 /* Otherwise if we are not supporting interworking and we have not created
20048 a backtrace structure and the function was not entered in ARM mode then
20049 just pop the return address straight into the PC. */
20050 else if (!TARGET_INTERWORK
20051 && !TARGET_BACKTRACE
20052 && !is_called_in_ARM_mode (current_function_decl
)
20053 && !crtl
->calls_eh_return
)
20055 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
20059 /* Find out how many of the (return) argument registers we can corrupt. */
20060 regs_available_for_popping
= 0;
20062 /* If returning via __builtin_eh_return, the bottom three registers
20063 all contain information needed for the return. */
20064 if (crtl
->calls_eh_return
)
20068 /* If we can deduce the registers used from the function's
20069 return value. This is more reliable that examining
20070 df_regs_ever_live_p () because that will be set if the register is
20071 ever used in the function, not just if the register is used
20072 to hold a return value. */
20074 if (crtl
->return_rtx
!= 0)
20075 mode
= GET_MODE (crtl
->return_rtx
);
20077 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
20079 size
= GET_MODE_SIZE (mode
);
20083 /* In a void function we can use any argument register.
20084 In a function that returns a structure on the stack
20085 we can use the second and third argument registers. */
20086 if (mode
== VOIDmode
)
20087 regs_available_for_popping
=
20088 (1 << ARG_REGISTER (1))
20089 | (1 << ARG_REGISTER (2))
20090 | (1 << ARG_REGISTER (3));
20092 regs_available_for_popping
=
20093 (1 << ARG_REGISTER (2))
20094 | (1 << ARG_REGISTER (3));
20096 else if (size
<= 4)
20097 regs_available_for_popping
=
20098 (1 << ARG_REGISTER (2))
20099 | (1 << ARG_REGISTER (3));
20100 else if (size
<= 8)
20101 regs_available_for_popping
=
20102 (1 << ARG_REGISTER (3));
20105 /* Match registers to be popped with registers into which we pop them. */
20106 for (available
= regs_available_for_popping
,
20107 required
= regs_to_pop
;
20108 required
!= 0 && available
!= 0;
20109 available
&= ~(available
& - available
),
20110 required
&= ~(required
& - required
))
20113 /* If we have any popping registers left over, remove them. */
20115 regs_available_for_popping
&= ~available
;
20117 /* Otherwise if we need another popping register we can use
20118 the fourth argument register. */
20119 else if (pops_needed
)
20121 /* If we have not found any free argument registers and
20122 reg a4 contains the return address, we must move it. */
20123 if (regs_available_for_popping
== 0
20124 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
20126 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
20127 reg_containing_return_addr
= LR_REGNUM
;
20129 else if (size
> 12)
20131 /* Register a4 is being used to hold part of the return value,
20132 but we have dire need of a free, low register. */
20135 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
20138 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
20140 /* The fourth argument register is available. */
20141 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
20147 /* Pop as many registers as we can. */
20148 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
20149 regs_available_for_popping
);
20151 /* Process the registers we popped. */
20152 if (reg_containing_return_addr
== -1)
20154 /* The return address was popped into the lowest numbered register. */
20155 regs_to_pop
&= ~(1 << LR_REGNUM
);
20157 reg_containing_return_addr
=
20158 number_of_first_bit_set (regs_available_for_popping
);
20160 /* Remove this register for the mask of available registers, so that
20161 the return address will not be corrupted by further pops. */
20162 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
20165 /* If we popped other registers then handle them here. */
20166 if (regs_available_for_popping
)
20170 /* Work out which register currently contains the frame pointer. */
20171 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
20173 /* Move it into the correct place. */
20174 asm_fprintf (f
, "\tmov\t%r, %r\n",
20175 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
20177 /* (Temporarily) remove it from the mask of popped registers. */
20178 regs_available_for_popping
&= ~(1 << frame_pointer
);
20179 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
20181 if (regs_available_for_popping
)
20185 /* We popped the stack pointer as well,
20186 find the register that contains it. */
20187 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
20189 /* Move it into the stack register. */
20190 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
20192 /* At this point we have popped all necessary registers, so
20193 do not worry about restoring regs_available_for_popping
20194 to its correct value:
20196 assert (pops_needed == 0)
20197 assert (regs_available_for_popping == (1 << frame_pointer))
20198 assert (regs_to_pop == (1 << STACK_POINTER)) */
20202 /* Since we have just move the popped value into the frame
20203 pointer, the popping register is available for reuse, and
20204 we know that we still have the stack pointer left to pop. */
20205 regs_available_for_popping
|= (1 << frame_pointer
);
20209 /* If we still have registers left on the stack, but we no longer have
20210 any registers into which we can pop them, then we must move the return
20211 address into the link register and make available the register that
20213 if (regs_available_for_popping
== 0 && pops_needed
> 0)
20215 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
20217 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
20218 reg_containing_return_addr
);
20220 reg_containing_return_addr
= LR_REGNUM
;
20223 /* If we have registers left on the stack then pop some more.
20224 We know that at most we will want to pop FP and SP. */
20225 if (pops_needed
> 0)
20230 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
20231 regs_available_for_popping
);
20233 /* We have popped either FP or SP.
20234 Move whichever one it is into the correct register. */
20235 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
20236 move_to
= number_of_first_bit_set (regs_to_pop
);
20238 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
20240 regs_to_pop
&= ~(1 << move_to
);
20245 /* If we still have not popped everything then we must have only
20246 had one register available to us and we are now popping the SP. */
20247 if (pops_needed
> 0)
20251 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
20252 regs_available_for_popping
);
20254 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
20256 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
20258 assert (regs_to_pop == (1 << STACK_POINTER))
20259 assert (pops_needed == 1)
20263 /* If necessary restore the a4 register. */
20266 if (reg_containing_return_addr
!= LR_REGNUM
)
20268 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
20269 reg_containing_return_addr
= LR_REGNUM
;
20272 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
20275 if (crtl
->calls_eh_return
)
20276 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
20278 /* Return to caller. */
20279 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
20282 /* Scan INSN just before assembler is output for it.
20283 For Thumb-1, we track the status of the condition codes; this
20284 information is used in the cbranchsi4_insn pattern. */
20286 thumb1_final_prescan_insn (rtx insn
)
20288 if (flag_print_asm_name
)
20289 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
20290 INSN_ADDRESSES (INSN_UID (insn
)));
20291 /* Don't overwrite the previous setter when we get to a cbranch. */
20292 if (INSN_CODE (insn
) != CODE_FOR_cbranchsi4_insn
)
20294 enum attr_conds conds
;
20296 if (cfun
->machine
->thumb1_cc_insn
)
20298 if (modified_in_p (cfun
->machine
->thumb1_cc_op0
, insn
)
20299 || modified_in_p (cfun
->machine
->thumb1_cc_op1
, insn
))
20302 conds
= get_attr_conds (insn
);
20303 if (conds
== CONDS_SET
)
20305 rtx set
= single_set (insn
);
20306 cfun
->machine
->thumb1_cc_insn
= insn
;
20307 cfun
->machine
->thumb1_cc_op0
= SET_DEST (set
);
20308 cfun
->machine
->thumb1_cc_op1
= const0_rtx
;
20309 cfun
->machine
->thumb1_cc_mode
= CC_NOOVmode
;
20310 if (INSN_CODE (insn
) == CODE_FOR_thumb1_subsi3_insn
)
20312 rtx src1
= XEXP (SET_SRC (set
), 1);
20313 if (src1
== const0_rtx
)
20314 cfun
->machine
->thumb1_cc_mode
= CCmode
;
20317 else if (conds
!= CONDS_NOCOND
)
20318 cfun
->machine
->thumb1_cc_insn
= NULL_RTX
;
20323 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
20325 unsigned HOST_WIDE_INT mask
= 0xff;
20328 val
= val
& (unsigned HOST_WIDE_INT
)0xffffffffu
;
20329 if (val
== 0) /* XXX */
20332 for (i
= 0; i
< 25; i
++)
20333 if ((val
& (mask
<< i
)) == val
)
20339 /* Returns nonzero if the current function contains,
20340 or might contain a far jump. */
20342 thumb_far_jump_used_p (void)
20346 /* This test is only important for leaf functions. */
20347 /* assert (!leaf_function_p ()); */
20349 /* If we have already decided that far jumps may be used,
20350 do not bother checking again, and always return true even if
20351 it turns out that they are not being used. Once we have made
20352 the decision that far jumps are present (and that hence the link
20353 register will be pushed onto the stack) we cannot go back on it. */
20354 if (cfun
->machine
->far_jump_used
)
20357 /* If this function is not being called from the prologue/epilogue
20358 generation code then it must be being called from the
20359 INITIAL_ELIMINATION_OFFSET macro. */
20360 if (!(ARM_DOUBLEWORD_ALIGN
|| reload_completed
))
20362 /* In this case we know that we are being asked about the elimination
20363 of the arg pointer register. If that register is not being used,
20364 then there are no arguments on the stack, and we do not have to
20365 worry that a far jump might force the prologue to push the link
20366 register, changing the stack offsets. In this case we can just
20367 return false, since the presence of far jumps in the function will
20368 not affect stack offsets.
20370 If the arg pointer is live (or if it was live, but has now been
20371 eliminated and so set to dead) then we do have to test to see if
20372 the function might contain a far jump. This test can lead to some
20373 false negatives, since before reload is completed, then length of
20374 branch instructions is not known, so gcc defaults to returning their
20375 longest length, which in turn sets the far jump attribute to true.
20377 A false negative will not result in bad code being generated, but it
20378 will result in a needless push and pop of the link register. We
20379 hope that this does not occur too often.
20381 If we need doubleword stack alignment this could affect the other
20382 elimination offsets so we can't risk getting it wrong. */
20383 if (df_regs_ever_live_p (ARG_POINTER_REGNUM
))
20384 cfun
->machine
->arg_pointer_live
= 1;
20385 else if (!cfun
->machine
->arg_pointer_live
)
20389 /* Check to see if the function contains a branch
20390 insn with the far jump attribute set. */
20391 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
20393 if (GET_CODE (insn
) == JUMP_INSN
20394 /* Ignore tablejump patterns. */
20395 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
20396 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
20397 && get_attr_far_jump (insn
) == FAR_JUMP_YES
20400 /* Record the fact that we have decided that
20401 the function does use far jumps. */
20402 cfun
->machine
->far_jump_used
= 1;
20410 /* Return nonzero if FUNC must be entered in ARM mode. */
20412 is_called_in_ARM_mode (tree func
)
20414 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
20416 /* Ignore the problem about functions whose address is taken. */
20417 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
20421 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
20427 /* Given the stack offsets and register mask in OFFSETS, decide how
20428 many additional registers to push instead of subtracting a constant
20429 from SP. For epilogues the principle is the same except we use pop.
20430 FOR_PROLOGUE indicates which we're generating. */
20432 thumb1_extra_regs_pushed (arm_stack_offsets
*offsets
, bool for_prologue
)
20434 HOST_WIDE_INT amount
;
20435 unsigned long live_regs_mask
= offsets
->saved_regs_mask
;
20436 /* Extract a mask of the ones we can give to the Thumb's push/pop
20438 unsigned long l_mask
= live_regs_mask
& (for_prologue
? 0x40ff : 0xff);
20439 /* Then count how many other high registers will need to be pushed. */
20440 unsigned long high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
20441 int n_free
, reg_base
;
20443 if (!for_prologue
&& frame_pointer_needed
)
20444 amount
= offsets
->locals_base
- offsets
->saved_regs
;
20446 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
20448 /* If the stack frame size is 512 exactly, we can save one load
20449 instruction, which should make this a win even when optimizing
20451 if (!optimize_size
&& amount
!= 512)
20454 /* Can't do this if there are high registers to push. */
20455 if (high_regs_pushed
!= 0)
20458 /* Shouldn't do it in the prologue if no registers would normally
20459 be pushed at all. In the epilogue, also allow it if we'll have
20460 a pop insn for the PC. */
20463 || TARGET_BACKTRACE
20464 || (live_regs_mask
& 1 << LR_REGNUM
) == 0
20465 || TARGET_INTERWORK
20466 || crtl
->args
.pretend_args_size
!= 0))
20469 /* Don't do this if thumb_expand_prologue wants to emit instructions
20470 between the push and the stack frame allocation. */
20472 && ((flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
20473 || (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)))
20480 reg_base
= arm_size_return_regs () / UNITS_PER_WORD
;
20481 live_regs_mask
>>= reg_base
;
20484 while (reg_base
+ n_free
< 8 && !(live_regs_mask
& 1)
20485 && (for_prologue
|| call_used_regs
[reg_base
+ n_free
]))
20487 live_regs_mask
>>= 1;
20493 gcc_assert (amount
/ 4 * 4 == amount
);
20495 if (amount
>= 512 && (amount
- n_free
* 4) < 512)
20496 return (amount
- 508) / 4;
20497 if (amount
<= n_free
* 4)
20502 /* The bits which aren't usefully expanded as rtl. */
20504 thumb_unexpanded_epilogue (void)
20506 arm_stack_offsets
*offsets
;
20508 unsigned long live_regs_mask
= 0;
20509 int high_regs_pushed
= 0;
20511 int had_to_push_lr
;
20514 if (cfun
->machine
->return_used_this_function
!= 0)
20517 if (IS_NAKED (arm_current_func_type ()))
20520 offsets
= arm_get_frame_offsets ();
20521 live_regs_mask
= offsets
->saved_regs_mask
;
20522 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
20524 /* If we can deduce the registers used from the function's return value.
20525 This is more reliable that examining df_regs_ever_live_p () because that
20526 will be set if the register is ever used in the function, not just if
20527 the register is used to hold a return value. */
20528 size
= arm_size_return_regs ();
20530 extra_pop
= thumb1_extra_regs_pushed (offsets
, false);
20533 unsigned long extra_mask
= (1 << extra_pop
) - 1;
20534 live_regs_mask
|= extra_mask
<< (size
/ UNITS_PER_WORD
);
20537 /* The prolog may have pushed some high registers to use as
20538 work registers. e.g. the testsuite file:
20539 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
20540 compiles to produce:
20541 push {r4, r5, r6, r7, lr}
20545 as part of the prolog. We have to undo that pushing here. */
20547 if (high_regs_pushed
)
20549 unsigned long mask
= live_regs_mask
& 0xff;
20552 /* The available low registers depend on the size of the value we are
20560 /* Oh dear! We have no low registers into which we can pop
20563 ("no low registers available for popping high registers");
20565 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
20566 if (live_regs_mask
& (1 << next_hi_reg
))
20569 while (high_regs_pushed
)
20571 /* Find lo register(s) into which the high register(s) can
20573 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
20575 if (mask
& (1 << regno
))
20576 high_regs_pushed
--;
20577 if (high_regs_pushed
== 0)
20581 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
20583 /* Pop the values into the low register(s). */
20584 thumb_pushpop (asm_out_file
, mask
, 0, NULL
, mask
);
20586 /* Move the value(s) into the high registers. */
20587 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
20589 if (mask
& (1 << regno
))
20591 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
20594 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
20595 if (live_regs_mask
& (1 << next_hi_reg
))
20600 live_regs_mask
&= ~0x0f00;
20603 had_to_push_lr
= (live_regs_mask
& (1 << LR_REGNUM
)) != 0;
20604 live_regs_mask
&= 0xff;
20606 if (crtl
->args
.pretend_args_size
== 0 || TARGET_BACKTRACE
)
20608 /* Pop the return address into the PC. */
20609 if (had_to_push_lr
)
20610 live_regs_mask
|= 1 << PC_REGNUM
;
20612 /* Either no argument registers were pushed or a backtrace
20613 structure was created which includes an adjusted stack
20614 pointer, so just pop everything. */
20615 if (live_regs_mask
)
20616 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
20619 /* We have either just popped the return address into the
20620 PC or it is was kept in LR for the entire function.
20621 Note that thumb_pushpop has already called thumb_exit if the
20622 PC was in the list. */
20623 if (!had_to_push_lr
)
20624 thumb_exit (asm_out_file
, LR_REGNUM
);
20628 /* Pop everything but the return address. */
20629 if (live_regs_mask
)
20630 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
20633 if (had_to_push_lr
)
20637 /* We have no free low regs, so save one. */
20638 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", IP_REGNUM
,
20642 /* Get the return address into a temporary register. */
20643 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0, NULL
,
20644 1 << LAST_ARG_REGNUM
);
20648 /* Move the return address to lr. */
20649 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LR_REGNUM
,
20651 /* Restore the low register. */
20652 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
,
20657 regno
= LAST_ARG_REGNUM
;
20662 /* Remove the argument registers that were pushed onto the stack. */
20663 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
20664 SP_REGNUM
, SP_REGNUM
,
20665 crtl
->args
.pretend_args_size
);
20667 thumb_exit (asm_out_file
, regno
);
20673 /* Functions to save and restore machine-specific function data. */
20674 static struct machine_function
*
20675 arm_init_machine_status (void)
20677 struct machine_function
*machine
;
20678 machine
= ggc_alloc_cleared_machine_function ();
20680 #if ARM_FT_UNKNOWN != 0
20681 machine
->func_type
= ARM_FT_UNKNOWN
;
20686 /* Return an RTX indicating where the return address to the
20687 calling function can be found. */
20689 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
20694 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
20697 /* Do anything needed before RTL is emitted for each function. */
20699 arm_init_expanders (void)
20701 /* Arrange to initialize and mark the machine per-function status. */
20702 init_machine_status
= arm_init_machine_status
;
20704 /* This is to stop the combine pass optimizing away the alignment
20705 adjustment of va_arg. */
20706 /* ??? It is claimed that this should not be necessary. */
20708 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
20712 /* Like arm_compute_initial_elimination offset. Simpler because there
20713 isn't an ABI specified frame pointer for Thumb. Instead, we set it
20714 to point at the base of the local variables after static stack
20715 space for a function has been allocated. */
20718 thumb_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
20720 arm_stack_offsets
*offsets
;
20722 offsets
= arm_get_frame_offsets ();
20726 case ARG_POINTER_REGNUM
:
20729 case STACK_POINTER_REGNUM
:
20730 return offsets
->outgoing_args
- offsets
->saved_args
;
20732 case FRAME_POINTER_REGNUM
:
20733 return offsets
->soft_frame
- offsets
->saved_args
;
20735 case ARM_HARD_FRAME_POINTER_REGNUM
:
20736 return offsets
->saved_regs
- offsets
->saved_args
;
20738 case THUMB_HARD_FRAME_POINTER_REGNUM
:
20739 return offsets
->locals_base
- offsets
->saved_args
;
20742 gcc_unreachable ();
20746 case FRAME_POINTER_REGNUM
:
20749 case STACK_POINTER_REGNUM
:
20750 return offsets
->outgoing_args
- offsets
->soft_frame
;
20752 case ARM_HARD_FRAME_POINTER_REGNUM
:
20753 return offsets
->saved_regs
- offsets
->soft_frame
;
20755 case THUMB_HARD_FRAME_POINTER_REGNUM
:
20756 return offsets
->locals_base
- offsets
->soft_frame
;
20759 gcc_unreachable ();
20764 gcc_unreachable ();
20768 /* Generate the rest of a function's prologue. */
20770 thumb1_expand_prologue (void)
20774 HOST_WIDE_INT amount
;
20775 arm_stack_offsets
*offsets
;
20776 unsigned long func_type
;
20778 unsigned long live_regs_mask
;
20780 func_type
= arm_current_func_type ();
20782 /* Naked functions don't have prologues. */
20783 if (IS_NAKED (func_type
))
20786 if (IS_INTERRUPT (func_type
))
20788 error ("interrupt Service Routines cannot be coded in Thumb mode");
20792 offsets
= arm_get_frame_offsets ();
20793 live_regs_mask
= offsets
->saved_regs_mask
;
20794 /* Load the pic register before setting the frame pointer,
20795 so we can use r7 as a temporary work register. */
20796 if (flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
20797 arm_load_pic_register (live_regs_mask
);
20799 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
20800 emit_move_insn (gen_rtx_REG (Pmode
, ARM_HARD_FRAME_POINTER_REGNUM
),
20801 stack_pointer_rtx
);
20803 if (flag_stack_usage_info
)
20804 current_function_static_stack_size
20805 = offsets
->outgoing_args
- offsets
->saved_args
;
20807 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
20808 amount
-= 4 * thumb1_extra_regs_pushed (offsets
, true);
20813 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
20814 GEN_INT (- amount
)));
20815 RTX_FRAME_RELATED_P (insn
) = 1;
20821 /* The stack decrement is too big for an immediate value in a single
20822 insn. In theory we could issue multiple subtracts, but after
20823 three of them it becomes more space efficient to place the full
20824 value in the constant pool and load into a register. (Also the
20825 ARM debugger really likes to see only one stack decrement per
20826 function). So instead we look for a scratch register into which
20827 we can load the decrement, and then we subtract this from the
20828 stack pointer. Unfortunately on the thumb the only available
20829 scratch registers are the argument registers, and we cannot use
20830 these as they may hold arguments to the function. Instead we
20831 attempt to locate a call preserved register which is used by this
20832 function. If we can find one, then we know that it will have
20833 been pushed at the start of the prologue and so we can corrupt
20835 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
20836 if (live_regs_mask
& (1 << regno
))
20839 gcc_assert(regno
<= LAST_LO_REGNUM
);
20841 reg
= gen_rtx_REG (SImode
, regno
);
20843 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
20845 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
20846 stack_pointer_rtx
, reg
));
20847 RTX_FRAME_RELATED_P (insn
) = 1;
20848 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
20849 plus_constant (stack_pointer_rtx
,
20851 RTX_FRAME_RELATED_P (dwarf
) = 1;
20852 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
20856 if (frame_pointer_needed
)
20857 thumb_set_frame_pointer (offsets
);
20859 /* If we are profiling, make sure no instructions are scheduled before
20860 the call to mcount. Similarly if the user has requested no
20861 scheduling in the prolog. Similarly if we want non-call exceptions
20862 using the EABI unwinder, to prevent faulting instructions from being
20863 swapped with a stack adjustment. */
20864 if (crtl
->profile
|| !TARGET_SCHED_PROLOG
20865 || (arm_except_unwind_info (&global_options
) == UI_TARGET
20866 && cfun
->can_throw_non_call_exceptions
))
20867 emit_insn (gen_blockage ());
20869 cfun
->machine
->lr_save_eliminated
= !thumb_force_lr_save ();
20870 if (live_regs_mask
& 0xff)
20871 cfun
->machine
->lr_save_eliminated
= 0;
20876 thumb1_expand_epilogue (void)
20878 HOST_WIDE_INT amount
;
20879 arm_stack_offsets
*offsets
;
20882 /* Naked functions don't have prologues. */
20883 if (IS_NAKED (arm_current_func_type ()))
20886 offsets
= arm_get_frame_offsets ();
20887 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
20889 if (frame_pointer_needed
)
20891 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
20892 amount
= offsets
->locals_base
- offsets
->saved_regs
;
20894 amount
-= 4 * thumb1_extra_regs_pushed (offsets
, false);
20896 gcc_assert (amount
>= 0);
20900 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
20901 GEN_INT (amount
)));
20904 /* r3 is always free in the epilogue. */
20905 rtx reg
= gen_rtx_REG (SImode
, LAST_ARG_REGNUM
);
20907 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
20908 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
20912 /* Emit a USE (stack_pointer_rtx), so that
20913 the stack adjustment will not be deleted. */
20914 emit_insn (gen_prologue_use (stack_pointer_rtx
));
20916 if (crtl
->profile
|| !TARGET_SCHED_PROLOG
)
20917 emit_insn (gen_blockage ());
20919 /* Emit a clobber for each insn that will be restored in the epilogue,
20920 so that flow2 will get register lifetimes correct. */
20921 for (regno
= 0; regno
< 13; regno
++)
20922 if (df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
20923 emit_clobber (gen_rtx_REG (SImode
, regno
));
20925 if (! df_regs_ever_live_p (LR_REGNUM
))
20926 emit_use (gen_rtx_REG (SImode
, LR_REGNUM
));
20930 thumb1_output_function_prologue (FILE *f
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
20932 arm_stack_offsets
*offsets
;
20933 unsigned long live_regs_mask
= 0;
20934 unsigned long l_mask
;
20935 unsigned high_regs_pushed
= 0;
20936 int cfa_offset
= 0;
20939 if (IS_NAKED (arm_current_func_type ()))
20942 if (is_called_in_ARM_mode (current_function_decl
))
20946 gcc_assert (GET_CODE (DECL_RTL (current_function_decl
)) == MEM
);
20947 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0))
20949 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
20951 /* Generate code sequence to switch us into Thumb mode. */
20952 /* The .code 32 directive has already been emitted by
20953 ASM_DECLARE_FUNCTION_NAME. */
20954 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
20955 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
20957 /* Generate a label, so that the debugger will notice the
20958 change in instruction sets. This label is also used by
20959 the assembler to bypass the ARM code when this function
20960 is called from a Thumb encoded function elsewhere in the
20961 same file. Hence the definition of STUB_NAME here must
20962 agree with the definition in gas/config/tc-arm.c. */
20964 #define STUB_NAME ".real_start_of"
20966 fprintf (f
, "\t.code\t16\n");
20968 if (arm_dllexport_name_p (name
))
20969 name
= arm_strip_name_encoding (name
);
20971 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
20972 fprintf (f
, "\t.thumb_func\n");
20973 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
20976 if (crtl
->args
.pretend_args_size
)
20978 /* Output unwind directive for the stack adjustment. */
20979 if (arm_except_unwind_info (&global_options
) == UI_TARGET
)
20980 fprintf (f
, "\t.pad #%d\n",
20981 crtl
->args
.pretend_args_size
);
20983 if (cfun
->machine
->uses_anonymous_args
)
20987 fprintf (f
, "\tpush\t{");
20989 num_pushes
= ARM_NUM_INTS (crtl
->args
.pretend_args_size
);
20991 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
20992 regno
<= LAST_ARG_REGNUM
;
20994 asm_fprintf (f
, "%r%s", regno
,
20995 regno
== LAST_ARG_REGNUM
? "" : ", ");
20997 fprintf (f
, "}\n");
21000 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
21001 SP_REGNUM
, SP_REGNUM
,
21002 crtl
->args
.pretend_args_size
);
21004 /* We don't need to record the stores for unwinding (would it
21005 help the debugger any if we did?), but record the change in
21006 the stack pointer. */
21007 if (dwarf2out_do_frame ())
21009 char *l
= dwarf2out_cfi_label (false);
21011 cfa_offset
= cfa_offset
+ crtl
->args
.pretend_args_size
;
21012 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
21016 /* Get the registers we are going to push. */
21017 offsets
= arm_get_frame_offsets ();
21018 live_regs_mask
= offsets
->saved_regs_mask
;
21019 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
21020 l_mask
= live_regs_mask
& 0x40ff;
21021 /* Then count how many other high registers will need to be pushed. */
21022 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
21024 if (TARGET_BACKTRACE
)
21027 unsigned work_register
;
21029 /* We have been asked to create a stack backtrace structure.
21030 The code looks like this:
21034 0 sub SP, #16 Reserve space for 4 registers.
21035 2 push {R7} Push low registers.
21036 4 add R7, SP, #20 Get the stack pointer before the push.
21037 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
21038 8 mov R7, PC Get hold of the start of this code plus 12.
21039 10 str R7, [SP, #16] Store it.
21040 12 mov R7, FP Get hold of the current frame pointer.
21041 14 str R7, [SP, #4] Store it.
21042 16 mov R7, LR Get hold of the current return address.
21043 18 str R7, [SP, #12] Store it.
21044 20 add R7, SP, #16 Point at the start of the backtrace structure.
21045 22 mov FP, R7 Put this value into the frame pointer. */
21047 work_register
= thumb_find_work_register (live_regs_mask
);
21049 if (arm_except_unwind_info (&global_options
) == UI_TARGET
)
21050 asm_fprintf (f
, "\t.pad #16\n");
21053 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
21054 SP_REGNUM
, SP_REGNUM
);
21056 if (dwarf2out_do_frame ())
21058 char *l
= dwarf2out_cfi_label (false);
21060 cfa_offset
= cfa_offset
+ 16;
21061 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
21066 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
21067 offset
= bit_count (l_mask
) * UNITS_PER_WORD
;
21072 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
21073 offset
+ 16 + crtl
->args
.pretend_args_size
);
21075 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
21078 /* Make sure that the instruction fetching the PC is in the right place
21079 to calculate "start of backtrace creation code + 12". */
21082 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
21083 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
21085 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
21086 ARM_HARD_FRAME_POINTER_REGNUM
);
21087 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
21092 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
21093 ARM_HARD_FRAME_POINTER_REGNUM
);
21094 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
21096 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
21097 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
21101 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
21102 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
21104 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
21106 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
21107 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
21109 /* Optimization: If we are not pushing any low registers but we are going
21110 to push some high registers then delay our first push. This will just
21111 be a push of LR and we can combine it with the push of the first high
21113 else if ((l_mask
& 0xff) != 0
21114 || (high_regs_pushed
== 0 && l_mask
))
21116 unsigned long mask
= l_mask
;
21117 mask
|= (1 << thumb1_extra_regs_pushed (offsets
, true)) - 1;
21118 thumb_pushpop (f
, mask
, 1, &cfa_offset
, mask
);
21121 if (high_regs_pushed
)
21123 unsigned pushable_regs
;
21124 unsigned next_hi_reg
;
21126 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
21127 if (live_regs_mask
& (1 << next_hi_reg
))
21130 pushable_regs
= l_mask
& 0xff;
21132 if (pushable_regs
== 0)
21133 pushable_regs
= 1 << thumb_find_work_register (live_regs_mask
);
21135 while (high_regs_pushed
> 0)
21137 unsigned long real_regs_mask
= 0;
21139 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
21141 if (pushable_regs
& (1 << regno
))
21143 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
21145 high_regs_pushed
--;
21146 real_regs_mask
|= (1 << next_hi_reg
);
21148 if (high_regs_pushed
)
21150 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
21152 if (live_regs_mask
& (1 << next_hi_reg
))
21157 pushable_regs
&= ~((1 << regno
) - 1);
21163 /* If we had to find a work register and we have not yet
21164 saved the LR then add it to the list of regs to push. */
21165 if (l_mask
== (1 << LR_REGNUM
))
21167 thumb_pushpop (f
, pushable_regs
| (1 << LR_REGNUM
),
21169 real_regs_mask
| (1 << LR_REGNUM
));
21173 thumb_pushpop (f
, pushable_regs
, 1, &cfa_offset
, real_regs_mask
);
21178 /* Handle the case of a double word load into a low register from
21179 a computed memory address. The computed address may involve a
21180 register which is overwritten by the load. */
21182 thumb_load_double_from_address (rtx
*operands
)
21190 gcc_assert (GET_CODE (operands
[0]) == REG
);
21191 gcc_assert (GET_CODE (operands
[1]) == MEM
);
21193 /* Get the memory address. */
21194 addr
= XEXP (operands
[1], 0);
21196 /* Work out how the memory address is computed. */
21197 switch (GET_CODE (addr
))
21200 operands
[2] = adjust_address (operands
[1], SImode
, 4);
21202 if (REGNO (operands
[0]) == REGNO (addr
))
21204 output_asm_insn ("ldr\t%H0, %2", operands
);
21205 output_asm_insn ("ldr\t%0, %1", operands
);
21209 output_asm_insn ("ldr\t%0, %1", operands
);
21210 output_asm_insn ("ldr\t%H0, %2", operands
);
21215 /* Compute <address> + 4 for the high order load. */
21216 operands
[2] = adjust_address (operands
[1], SImode
, 4);
21218 output_asm_insn ("ldr\t%0, %1", operands
);
21219 output_asm_insn ("ldr\t%H0, %2", operands
);
21223 arg1
= XEXP (addr
, 0);
21224 arg2
= XEXP (addr
, 1);
21226 if (CONSTANT_P (arg1
))
21227 base
= arg2
, offset
= arg1
;
21229 base
= arg1
, offset
= arg2
;
21231 gcc_assert (GET_CODE (base
) == REG
);
21233 /* Catch the case of <address> = <reg> + <reg> */
21234 if (GET_CODE (offset
) == REG
)
21236 int reg_offset
= REGNO (offset
);
21237 int reg_base
= REGNO (base
);
21238 int reg_dest
= REGNO (operands
[0]);
21240 /* Add the base and offset registers together into the
21241 higher destination register. */
21242 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
21243 reg_dest
+ 1, reg_base
, reg_offset
);
21245 /* Load the lower destination register from the address in
21246 the higher destination register. */
21247 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
21248 reg_dest
, reg_dest
+ 1);
21250 /* Load the higher destination register from its own address
21252 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
21253 reg_dest
+ 1, reg_dest
+ 1);
21257 /* Compute <address> + 4 for the high order load. */
21258 operands
[2] = adjust_address (operands
[1], SImode
, 4);
21260 /* If the computed address is held in the low order register
21261 then load the high order register first, otherwise always
21262 load the low order register first. */
21263 if (REGNO (operands
[0]) == REGNO (base
))
21265 output_asm_insn ("ldr\t%H0, %2", operands
);
21266 output_asm_insn ("ldr\t%0, %1", operands
);
21270 output_asm_insn ("ldr\t%0, %1", operands
);
21271 output_asm_insn ("ldr\t%H0, %2", operands
);
21277 /* With no registers to worry about we can just load the value
21279 operands
[2] = adjust_address (operands
[1], SImode
, 4);
21281 output_asm_insn ("ldr\t%H0, %2", operands
);
21282 output_asm_insn ("ldr\t%0, %1", operands
);
21286 gcc_unreachable ();
21293 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
21300 if (REGNO (operands
[4]) > REGNO (operands
[5]))
21303 operands
[4] = operands
[5];
21306 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
21307 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
21311 if (REGNO (operands
[4]) > REGNO (operands
[5]))
21314 operands
[4] = operands
[5];
21317 if (REGNO (operands
[5]) > REGNO (operands
[6]))
21320 operands
[5] = operands
[6];
21323 if (REGNO (operands
[4]) > REGNO (operands
[5]))
21326 operands
[4] = operands
[5];
21330 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
21331 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
21335 gcc_unreachable ();
21341 /* Output a call-via instruction for thumb state. */
21343 thumb_call_via_reg (rtx reg
)
21345 int regno
= REGNO (reg
);
21348 gcc_assert (regno
< LR_REGNUM
);
21350 /* If we are in the normal text section we can use a single instance
21351 per compilation unit. If we are doing function sections, then we need
21352 an entry per section, since we can't rely on reachability. */
21353 if (in_section
== text_section
)
21355 thumb_call_reg_needed
= 1;
21357 if (thumb_call_via_label
[regno
] == NULL
)
21358 thumb_call_via_label
[regno
] = gen_label_rtx ();
21359 labelp
= thumb_call_via_label
+ regno
;
21363 if (cfun
->machine
->call_via
[regno
] == NULL
)
21364 cfun
->machine
->call_via
[regno
] = gen_label_rtx ();
21365 labelp
= cfun
->machine
->call_via
+ regno
;
21368 output_asm_insn ("bl\t%a0", labelp
);
21372 /* Routines for generating rtl. */
21374 thumb_expand_movmemqi (rtx
*operands
)
21376 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
21377 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
21378 HOST_WIDE_INT len
= INTVAL (operands
[2]);
21379 HOST_WIDE_INT offset
= 0;
21383 emit_insn (gen_movmem12b (out
, in
, out
, in
));
21389 emit_insn (gen_movmem8b (out
, in
, out
, in
));
21395 rtx reg
= gen_reg_rtx (SImode
);
21396 emit_insn (gen_movsi (reg
, gen_rtx_MEM (SImode
, in
)));
21397 emit_insn (gen_movsi (gen_rtx_MEM (SImode
, out
), reg
));
21404 rtx reg
= gen_reg_rtx (HImode
);
21405 emit_insn (gen_movhi (reg
, gen_rtx_MEM (HImode
,
21406 plus_constant (in
, offset
))));
21407 emit_insn (gen_movhi (gen_rtx_MEM (HImode
, plus_constant (out
, offset
)),
21415 rtx reg
= gen_reg_rtx (QImode
);
21416 emit_insn (gen_movqi (reg
, gen_rtx_MEM (QImode
,
21417 plus_constant (in
, offset
))));
21418 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (out
, offset
)),
21424 thumb_reload_out_hi (rtx
*operands
)
21426 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
21429 /* Handle reading a half-word from memory during reload. */
21431 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
21433 gcc_unreachable ();
21436 /* Return the length of a function name prefix
21437 that starts with the character 'c'. */
21439 arm_get_strip_length (int c
)
21443 ARM_NAME_ENCODING_LENGTHS
21448 /* Return a pointer to a function's name with any
21449 and all prefix encodings stripped from it. */
21451 arm_strip_name_encoding (const char *name
)
21455 while ((skip
= arm_get_strip_length (* name
)))
21461 /* If there is a '*' anywhere in the name's prefix, then
21462 emit the stripped name verbatim, otherwise prepend an
21463 underscore if leading underscores are being used. */
21465 arm_asm_output_labelref (FILE *stream
, const char *name
)
21470 while ((skip
= arm_get_strip_length (* name
)))
21472 verbatim
|= (*name
== '*');
21477 fputs (name
, stream
);
21479 asm_fprintf (stream
, "%U%s", name
);
21483 arm_file_start (void)
21487 if (TARGET_UNIFIED_ASM
)
21488 asm_fprintf (asm_out_file
, "\t.syntax unified\n");
21492 const char *fpu_name
;
21493 if (arm_selected_arch
)
21494 asm_fprintf (asm_out_file
, "\t.arch %s\n", arm_selected_arch
->name
);
21496 asm_fprintf (asm_out_file
, "\t.cpu %s\n", arm_selected_cpu
->name
);
21498 if (TARGET_SOFT_FLOAT
)
21501 fpu_name
= "softvfp";
21503 fpu_name
= "softfpa";
21507 fpu_name
= arm_fpu_desc
->name
;
21508 if (arm_fpu_desc
->model
== ARM_FP_MODEL_VFP
)
21510 if (TARGET_HARD_FLOAT
)
21511 asm_fprintf (asm_out_file
, "\t.eabi_attribute 27, 3\n");
21512 if (TARGET_HARD_FLOAT_ABI
)
21513 asm_fprintf (asm_out_file
, "\t.eabi_attribute 28, 1\n");
21516 asm_fprintf (asm_out_file
, "\t.fpu %s\n", fpu_name
);
21518 /* Some of these attributes only apply when the corresponding features
21519 are used. However we don't have any easy way of figuring this out.
21520 Conservatively record the setting that would have been used. */
21522 /* Tag_ABI_FP_rounding. */
21523 if (flag_rounding_math
)
21524 asm_fprintf (asm_out_file
, "\t.eabi_attribute 19, 1\n");
21525 if (!flag_unsafe_math_optimizations
)
21527 /* Tag_ABI_FP_denomal. */
21528 asm_fprintf (asm_out_file
, "\t.eabi_attribute 20, 1\n");
21529 /* Tag_ABI_FP_exceptions. */
21530 asm_fprintf (asm_out_file
, "\t.eabi_attribute 21, 1\n");
21532 /* Tag_ABI_FP_user_exceptions. */
21533 if (flag_signaling_nans
)
21534 asm_fprintf (asm_out_file
, "\t.eabi_attribute 22, 1\n");
21535 /* Tag_ABI_FP_number_model. */
21536 asm_fprintf (asm_out_file
, "\t.eabi_attribute 23, %d\n",
21537 flag_finite_math_only
? 1 : 3);
21539 /* Tag_ABI_align8_needed. */
21540 asm_fprintf (asm_out_file
, "\t.eabi_attribute 24, 1\n");
21541 /* Tag_ABI_align8_preserved. */
21542 asm_fprintf (asm_out_file
, "\t.eabi_attribute 25, 1\n");
21543 /* Tag_ABI_enum_size. */
21544 asm_fprintf (asm_out_file
, "\t.eabi_attribute 26, %d\n",
21545 flag_short_enums
? 1 : 2);
21547 /* Tag_ABI_optimization_goals. */
21550 else if (optimize
>= 2)
21556 asm_fprintf (asm_out_file
, "\t.eabi_attribute 30, %d\n", val
);
21558 /* Tag_ABI_FP_16bit_format. */
21559 if (arm_fp16_format
)
21560 asm_fprintf (asm_out_file
, "\t.eabi_attribute 38, %d\n",
21561 (int)arm_fp16_format
);
21563 if (arm_lang_output_object_attributes_hook
)
21564 arm_lang_output_object_attributes_hook();
21566 default_file_start();
21570 arm_file_end (void)
21574 if (NEED_INDICATE_EXEC_STACK
)
21575 /* Add .note.GNU-stack. */
21576 file_end_indicate_exec_stack ();
21578 if (! thumb_call_reg_needed
)
21581 switch_to_section (text_section
);
21582 asm_fprintf (asm_out_file
, "\t.code 16\n");
21583 ASM_OUTPUT_ALIGN (asm_out_file
, 1);
21585 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
21587 rtx label
= thumb_call_via_label
[regno
];
21591 targetm
.asm_out
.internal_label (asm_out_file
, "L",
21592 CODE_LABEL_NUMBER (label
));
21593 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
21599 /* Symbols in the text segment can be accessed without indirecting via the
21600 constant pool; it may take an extra binary operation, but this is still
21601 faster than indirecting via memory. Don't do this when not optimizing,
21602 since we won't be calculating al of the offsets necessary to do this
21606 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
21608 if (optimize
> 0 && TREE_CONSTANT (decl
))
21609 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
21611 default_encode_section_info (decl
, rtl
, first
);
21613 #endif /* !ARM_PE */
21616 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
21618 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
21619 && !strcmp (prefix
, "L"))
21621 arm_ccfsm_state
= 0;
21622 arm_target_insn
= NULL
;
21624 default_internal_label (stream
, prefix
, labelno
);
21627 /* Output code to add DELTA to the first argument, and then jump
21628 to FUNCTION. Used for C++ multiple inheritance. */
21630 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
21631 HOST_WIDE_INT delta
,
21632 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
21635 static int thunk_label
= 0;
21638 int mi_delta
= delta
;
21639 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
21641 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
21644 mi_delta
= - mi_delta
;
21648 int labelno
= thunk_label
++;
21649 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHUMBFUNC", labelno
);
21650 /* Thunks are entered in arm mode when avaiable. */
21651 if (TARGET_THUMB1_ONLY
)
21653 /* push r3 so we can use it as a temporary. */
21654 /* TODO: Omit this save if r3 is not used. */
21655 fputs ("\tpush {r3}\n", file
);
21656 fputs ("\tldr\tr3, ", file
);
21660 fputs ("\tldr\tr12, ", file
);
21662 assemble_name (file
, label
);
21663 fputc ('\n', file
);
21666 /* If we are generating PIC, the ldr instruction below loads
21667 "(target - 7) - .LTHUNKPCn" into r12. The pc reads as
21668 the address of the add + 8, so we have:
21670 r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8)
21673 Note that we have "+ 1" because some versions of GNU ld
21674 don't set the low bit of the result for R_ARM_REL32
21675 relocations against thumb function symbols.
21676 On ARMv6M this is +4, not +8. */
21677 ASM_GENERATE_INTERNAL_LABEL (labelpc
, "LTHUNKPC", labelno
);
21678 assemble_name (file
, labelpc
);
21679 fputs (":\n", file
);
21680 if (TARGET_THUMB1_ONLY
)
21682 /* This is 2 insns after the start of the thunk, so we know it
21683 is 4-byte aligned. */
21684 fputs ("\tadd\tr3, pc, r3\n", file
);
21685 fputs ("\tmov r12, r3\n", file
);
21688 fputs ("\tadd\tr12, pc, r12\n", file
);
21690 else if (TARGET_THUMB1_ONLY
)
21691 fputs ("\tmov r12, r3\n", file
);
21693 if (TARGET_THUMB1_ONLY
)
21695 if (mi_delta
> 255)
21697 fputs ("\tldr\tr3, ", file
);
21698 assemble_name (file
, label
);
21699 fputs ("+4\n", file
);
21700 asm_fprintf (file
, "\t%s\t%r, %r, r3\n",
21701 mi_op
, this_regno
, this_regno
);
21703 else if (mi_delta
!= 0)
21705 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
21706 mi_op
, this_regno
, this_regno
,
21712 /* TODO: Use movw/movt for large constants when available. */
21713 while (mi_delta
!= 0)
21715 if ((mi_delta
& (3 << shift
)) == 0)
21719 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
21720 mi_op
, this_regno
, this_regno
,
21721 mi_delta
& (0xff << shift
));
21722 mi_delta
&= ~(0xff << shift
);
21729 if (TARGET_THUMB1_ONLY
)
21730 fputs ("\tpop\t{r3}\n", file
);
21732 fprintf (file
, "\tbx\tr12\n");
21733 ASM_OUTPUT_ALIGN (file
, 2);
21734 assemble_name (file
, label
);
21735 fputs (":\n", file
);
21738 /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */
21739 rtx tem
= XEXP (DECL_RTL (function
), 0);
21740 tem
= gen_rtx_PLUS (GET_MODE (tem
), tem
, GEN_INT (-7));
21741 tem
= gen_rtx_MINUS (GET_MODE (tem
),
21743 gen_rtx_SYMBOL_REF (Pmode
,
21744 ggc_strdup (labelpc
)));
21745 assemble_integer (tem
, 4, BITS_PER_WORD
, 1);
21748 /* Output ".word .LTHUNKn". */
21749 assemble_integer (XEXP (DECL_RTL (function
), 0), 4, BITS_PER_WORD
, 1);
21751 if (TARGET_THUMB1_ONLY
&& mi_delta
> 255)
21752 assemble_integer (GEN_INT(mi_delta
), 4, BITS_PER_WORD
, 1);
21756 fputs ("\tb\t", file
);
21757 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
21758 if (NEED_PLT_RELOC
)
21759 fputs ("(PLT)", file
);
21760 fputc ('\n', file
);
21765 arm_emit_vector_const (FILE *file
, rtx x
)
21768 const char * pattern
;
21770 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
21772 switch (GET_MODE (x
))
21774 case V2SImode
: pattern
= "%08x"; break;
21775 case V4HImode
: pattern
= "%04x"; break;
21776 case V8QImode
: pattern
= "%02x"; break;
21777 default: gcc_unreachable ();
21780 fprintf (file
, "0x");
21781 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
21785 element
= CONST_VECTOR_ELT (x
, i
);
21786 fprintf (file
, pattern
, INTVAL (element
));
21792 /* Emit a fp16 constant appropriately padded to occupy a 4-byte word.
21793 HFmode constant pool entries are actually loaded with ldr. */
21795 arm_emit_fp16_const (rtx c
)
21800 REAL_VALUE_FROM_CONST_DOUBLE (r
, c
);
21801 bits
= real_to_target (NULL
, &r
, HFmode
);
21802 if (WORDS_BIG_ENDIAN
)
21803 assemble_zeros (2);
21804 assemble_integer (GEN_INT (bits
), 2, BITS_PER_WORD
, 1);
21805 if (!WORDS_BIG_ENDIAN
)
21806 assemble_zeros (2);
21810 arm_output_load_gr (rtx
*operands
)
21817 if (GET_CODE (operands
[1]) != MEM
21818 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
21819 || GET_CODE (reg
= XEXP (sum
, 0)) != REG
21820 || GET_CODE (offset
= XEXP (sum
, 1)) != CONST_INT
21821 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
21822 return "wldrw%?\t%0, %1";
21824 /* Fix up an out-of-range load of a GR register. */
21825 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
21826 wcgr
= operands
[0];
21828 output_asm_insn ("ldr%?\t%0, %1", operands
);
21830 operands
[0] = wcgr
;
21832 output_asm_insn ("tmcr%?\t%0, %1", operands
);
21833 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);
21838 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
21840 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
21841 named arg and all anonymous args onto the stack.
21842 XXX I know the prologue shouldn't be pushing registers, but it is faster
21846 arm_setup_incoming_varargs (CUMULATIVE_ARGS
*pcum
,
21847 enum machine_mode mode
,
21850 int second_time ATTRIBUTE_UNUSED
)
21854 cfun
->machine
->uses_anonymous_args
= 1;
21855 if (pcum
->pcs_variant
<= ARM_PCS_AAPCS_LOCAL
)
21857 nregs
= pcum
->aapcs_ncrn
;
21858 if ((nregs
& 1) && arm_needs_doubleword_align (mode
, type
))
21862 nregs
= pcum
->nregs
;
21864 if (nregs
< NUM_ARG_REGS
)
21865 *pretend_size
= (NUM_ARG_REGS
- nregs
) * UNITS_PER_WORD
;
21868 /* Return nonzero if the CONSUMER instruction (a store) does not need
21869 PRODUCER's value to calculate the address. */
21872 arm_no_early_store_addr_dep (rtx producer
, rtx consumer
)
21874 rtx value
= PATTERN (producer
);
21875 rtx addr
= PATTERN (consumer
);
21877 if (GET_CODE (value
) == COND_EXEC
)
21878 value
= COND_EXEC_CODE (value
);
21879 if (GET_CODE (value
) == PARALLEL
)
21880 value
= XVECEXP (value
, 0, 0);
21881 value
= XEXP (value
, 0);
21882 if (GET_CODE (addr
) == COND_EXEC
)
21883 addr
= COND_EXEC_CODE (addr
);
21884 if (GET_CODE (addr
) == PARALLEL
)
21885 addr
= XVECEXP (addr
, 0, 0);
21886 addr
= XEXP (addr
, 0);
21888 return !reg_overlap_mentioned_p (value
, addr
);
21891 /* Return nonzero if the CONSUMER instruction (a store) does need
21892 PRODUCER's value to calculate the address. */
21895 arm_early_store_addr_dep (rtx producer
, rtx consumer
)
21897 return !arm_no_early_store_addr_dep (producer
, consumer
);
21900 /* Return nonzero if the CONSUMER instruction (a load) does need
21901 PRODUCER's value to calculate the address. */
21904 arm_early_load_addr_dep (rtx producer
, rtx consumer
)
21906 rtx value
= PATTERN (producer
);
21907 rtx addr
= PATTERN (consumer
);
21909 if (GET_CODE (value
) == COND_EXEC
)
21910 value
= COND_EXEC_CODE (value
);
21911 if (GET_CODE (value
) == PARALLEL
)
21912 value
= XVECEXP (value
, 0, 0);
21913 value
= XEXP (value
, 0);
21914 if (GET_CODE (addr
) == COND_EXEC
)
21915 addr
= COND_EXEC_CODE (addr
);
21916 if (GET_CODE (addr
) == PARALLEL
)
21917 addr
= XVECEXP (addr
, 0, 0);
21918 addr
= XEXP (addr
, 1);
21920 return reg_overlap_mentioned_p (value
, addr
);
21923 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
21924 have an early register shift value or amount dependency on the
21925 result of PRODUCER. */
21928 arm_no_early_alu_shift_dep (rtx producer
, rtx consumer
)
21930 rtx value
= PATTERN (producer
);
21931 rtx op
= PATTERN (consumer
);
21934 if (GET_CODE (value
) == COND_EXEC
)
21935 value
= COND_EXEC_CODE (value
);
21936 if (GET_CODE (value
) == PARALLEL
)
21937 value
= XVECEXP (value
, 0, 0);
21938 value
= XEXP (value
, 0);
21939 if (GET_CODE (op
) == COND_EXEC
)
21940 op
= COND_EXEC_CODE (op
);
21941 if (GET_CODE (op
) == PARALLEL
)
21942 op
= XVECEXP (op
, 0, 0);
21945 early_op
= XEXP (op
, 0);
21946 /* This is either an actual independent shift, or a shift applied to
21947 the first operand of another operation. We want the whole shift
21949 if (GET_CODE (early_op
) == REG
)
21952 return !reg_overlap_mentioned_p (value
, early_op
);
21955 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
21956 have an early register shift value dependency on the result of
21960 arm_no_early_alu_shift_value_dep (rtx producer
, rtx consumer
)
21962 rtx value
= PATTERN (producer
);
21963 rtx op
= PATTERN (consumer
);
21966 if (GET_CODE (value
) == COND_EXEC
)
21967 value
= COND_EXEC_CODE (value
);
21968 if (GET_CODE (value
) == PARALLEL
)
21969 value
= XVECEXP (value
, 0, 0);
21970 value
= XEXP (value
, 0);
21971 if (GET_CODE (op
) == COND_EXEC
)
21972 op
= COND_EXEC_CODE (op
);
21973 if (GET_CODE (op
) == PARALLEL
)
21974 op
= XVECEXP (op
, 0, 0);
21977 early_op
= XEXP (op
, 0);
21979 /* This is either an actual independent shift, or a shift applied to
21980 the first operand of another operation. We want the value being
21981 shifted, in either case. */
21982 if (GET_CODE (early_op
) != REG
)
21983 early_op
= XEXP (early_op
, 0);
21985 return !reg_overlap_mentioned_p (value
, early_op
);
21988 /* Return nonzero if the CONSUMER (a mul or mac op) does not
21989 have an early register mult dependency on the result of
21993 arm_no_early_mul_dep (rtx producer
, rtx consumer
)
21995 rtx value
= PATTERN (producer
);
21996 rtx op
= PATTERN (consumer
);
21998 if (GET_CODE (value
) == COND_EXEC
)
21999 value
= COND_EXEC_CODE (value
);
22000 if (GET_CODE (value
) == PARALLEL
)
22001 value
= XVECEXP (value
, 0, 0);
22002 value
= XEXP (value
, 0);
22003 if (GET_CODE (op
) == COND_EXEC
)
22004 op
= COND_EXEC_CODE (op
);
22005 if (GET_CODE (op
) == PARALLEL
)
22006 op
= XVECEXP (op
, 0, 0);
22009 if (GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
22011 if (GET_CODE (XEXP (op
, 0)) == MULT
)
22012 return !reg_overlap_mentioned_p (value
, XEXP (op
, 0));
22014 return !reg_overlap_mentioned_p (value
, XEXP (op
, 1));
22020 /* We can't rely on the caller doing the proper promotion when
22021 using APCS or ATPCS. */
22024 arm_promote_prototypes (const_tree t ATTRIBUTE_UNUSED
)
22026 return !TARGET_AAPCS_BASED
;
22029 static enum machine_mode
22030 arm_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
22031 enum machine_mode mode
,
22032 int *punsignedp ATTRIBUTE_UNUSED
,
22033 const_tree fntype ATTRIBUTE_UNUSED
,
22034 int for_return ATTRIBUTE_UNUSED
)
22036 if (GET_MODE_CLASS (mode
) == MODE_INT
22037 && GET_MODE_SIZE (mode
) < 4)
22043 /* AAPCS based ABIs use short enums by default. */
22046 arm_default_short_enums (void)
22048 return TARGET_AAPCS_BASED
&& arm_abi
!= ARM_ABI_AAPCS_LINUX
;
22052 /* AAPCS requires that anonymous bitfields affect structure alignment. */
22055 arm_align_anon_bitfield (void)
22057 return TARGET_AAPCS_BASED
;
22061 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
22064 arm_cxx_guard_type (void)
22066 return TARGET_AAPCS_BASED
? integer_type_node
: long_long_integer_type_node
;
22069 /* Return non-zero if the consumer (a multiply-accumulate instruction)
22070 has an accumulator dependency on the result of the producer (a
22071 multiplication instruction) and no other dependency on that result. */
22073 arm_mac_accumulator_is_mul_result (rtx producer
, rtx consumer
)
22075 rtx mul
= PATTERN (producer
);
22076 rtx mac
= PATTERN (consumer
);
22078 rtx mac_op0
, mac_op1
, mac_acc
;
22080 if (GET_CODE (mul
) == COND_EXEC
)
22081 mul
= COND_EXEC_CODE (mul
);
22082 if (GET_CODE (mac
) == COND_EXEC
)
22083 mac
= COND_EXEC_CODE (mac
);
22085 /* Check that mul is of the form (set (...) (mult ...))
22086 and mla is of the form (set (...) (plus (mult ...) (...))). */
22087 if ((GET_CODE (mul
) != SET
|| GET_CODE (XEXP (mul
, 1)) != MULT
)
22088 || (GET_CODE (mac
) != SET
|| GET_CODE (XEXP (mac
, 1)) != PLUS
22089 || GET_CODE (XEXP (XEXP (mac
, 1), 0)) != MULT
))
22092 mul_result
= XEXP (mul
, 0);
22093 mac_op0
= XEXP (XEXP (XEXP (mac
, 1), 0), 0);
22094 mac_op1
= XEXP (XEXP (XEXP (mac
, 1), 0), 1);
22095 mac_acc
= XEXP (XEXP (mac
, 1), 1);
22097 return (reg_overlap_mentioned_p (mul_result
, mac_acc
)
22098 && !reg_overlap_mentioned_p (mul_result
, mac_op0
)
22099 && !reg_overlap_mentioned_p (mul_result
, mac_op1
));
22103 /* The EABI says test the least significant bit of a guard variable. */
22106 arm_cxx_guard_mask_bit (void)
22108 return TARGET_AAPCS_BASED
;
22112 /* The EABI specifies that all array cookies are 8 bytes long. */
22115 arm_get_cookie_size (tree type
)
22119 if (!TARGET_AAPCS_BASED
)
22120 return default_cxx_get_cookie_size (type
);
22122 size
= build_int_cst (sizetype
, 8);
22127 /* The EABI says that array cookies should also contain the element size. */
22130 arm_cookie_has_size (void)
22132 return TARGET_AAPCS_BASED
;
22136 /* The EABI says constructors and destructors should return a pointer to
22137 the object constructed/destroyed. */
22140 arm_cxx_cdtor_returns_this (void)
22142 return TARGET_AAPCS_BASED
;
22145 /* The EABI says that an inline function may never be the key
22149 arm_cxx_key_method_may_be_inline (void)
22151 return !TARGET_AAPCS_BASED
;
22155 arm_cxx_determine_class_data_visibility (tree decl
)
22157 if (!TARGET_AAPCS_BASED
22158 || !TARGET_DLLIMPORT_DECL_ATTRIBUTES
)
22161 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
22162 is exported. However, on systems without dynamic vague linkage,
22163 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
22164 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
&& DECL_COMDAT (decl
))
22165 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
22167 DECL_VISIBILITY (decl
) = VISIBILITY_DEFAULT
;
22168 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
22172 arm_cxx_class_data_always_comdat (void)
22174 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
22175 vague linkage if the class has no key function. */
22176 return !TARGET_AAPCS_BASED
;
22180 /* The EABI says __aeabi_atexit should be used to register static
22184 arm_cxx_use_aeabi_atexit (void)
22186 return TARGET_AAPCS_BASED
;
22191 arm_set_return_address (rtx source
, rtx scratch
)
22193 arm_stack_offsets
*offsets
;
22194 HOST_WIDE_INT delta
;
22196 unsigned long saved_regs
;
22198 offsets
= arm_get_frame_offsets ();
22199 saved_regs
= offsets
->saved_regs_mask
;
22201 if ((saved_regs
& (1 << LR_REGNUM
)) == 0)
22202 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
22205 if (frame_pointer_needed
)
22206 addr
= plus_constant(hard_frame_pointer_rtx
, -4);
22209 /* LR will be the first saved register. */
22210 delta
= offsets
->outgoing_args
- (offsets
->frame
+ 4);
22215 emit_insn (gen_addsi3 (scratch
, stack_pointer_rtx
,
22216 GEN_INT (delta
& ~4095)));
22221 addr
= stack_pointer_rtx
;
22223 addr
= plus_constant (addr
, delta
);
22225 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
22231 thumb_set_return_address (rtx source
, rtx scratch
)
22233 arm_stack_offsets
*offsets
;
22234 HOST_WIDE_INT delta
;
22235 HOST_WIDE_INT limit
;
22238 unsigned long mask
;
22242 offsets
= arm_get_frame_offsets ();
22243 mask
= offsets
->saved_regs_mask
;
22244 if (mask
& (1 << LR_REGNUM
))
22247 /* Find the saved regs. */
22248 if (frame_pointer_needed
)
22250 delta
= offsets
->soft_frame
- offsets
->saved_args
;
22251 reg
= THUMB_HARD_FRAME_POINTER_REGNUM
;
22257 delta
= offsets
->outgoing_args
- offsets
->saved_args
;
22260 /* Allow for the stack frame. */
22261 if (TARGET_THUMB1
&& TARGET_BACKTRACE
)
22263 /* The link register is always the first saved register. */
22266 /* Construct the address. */
22267 addr
= gen_rtx_REG (SImode
, reg
);
22270 emit_insn (gen_movsi (scratch
, GEN_INT (delta
)));
22271 emit_insn (gen_addsi3 (scratch
, scratch
, stack_pointer_rtx
));
22275 addr
= plus_constant (addr
, delta
);
22277 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
22280 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
22283 /* Implements target hook vector_mode_supported_p. */
22285 arm_vector_mode_supported_p (enum machine_mode mode
)
22287 /* Neon also supports V2SImode, etc. listed in the clause below. */
22288 if (TARGET_NEON
&& (mode
== V2SFmode
|| mode
== V4SImode
|| mode
== V8HImode
22289 || mode
== V16QImode
|| mode
== V4SFmode
|| mode
== V2DImode
))
22292 if ((TARGET_NEON
|| TARGET_IWMMXT
)
22293 && ((mode
== V2SImode
)
22294 || (mode
== V4HImode
)
22295 || (mode
== V8QImode
)))
22301 /* Implements target hook array_mode_supported_p. */
22304 arm_array_mode_supported_p (enum machine_mode mode
,
22305 unsigned HOST_WIDE_INT nelems
)
22308 && (VALID_NEON_DREG_MODE (mode
) || VALID_NEON_QREG_MODE (mode
))
22309 && (nelems
>= 2 && nelems
<= 4))
22315 /* Use the option -mvectorize-with-neon-quad to override the use of doubleword
22316 registers when autovectorizing for Neon, at least until multiple vector
22317 widths are supported properly by the middle-end. */
22319 static enum machine_mode
22320 arm_preferred_simd_mode (enum machine_mode mode
)
22326 return TARGET_NEON_VECTORIZE_QUAD
? V4SFmode
: V2SFmode
;
22328 return TARGET_NEON_VECTORIZE_QUAD
? V4SImode
: V2SImode
;
22330 return TARGET_NEON_VECTORIZE_QUAD
? V8HImode
: V4HImode
;
22332 return TARGET_NEON_VECTORIZE_QUAD
? V16QImode
: V8QImode
;
22334 if (TARGET_NEON_VECTORIZE_QUAD
)
22341 if (TARGET_REALLY_IWMMXT
)
22357 /* Implement TARGET_CLASS_LIKELY_SPILLED_P.
22359 We need to define this for LO_REGS on Thumb-1. Otherwise we can end up
22360 using r0-r4 for function arguments, r7 for the stack frame and don't have
22361 enough left over to do doubleword arithmetic. For Thumb-2 all the
22362 potentially problematic instructions accept high registers so this is not
22363 necessary. Care needs to be taken to avoid adding new Thumb-2 patterns
22364 that require many low registers. */
22366 arm_class_likely_spilled_p (reg_class_t rclass
)
22368 if ((TARGET_THUMB1
&& rclass
== LO_REGS
)
22369 || rclass
== CC_REG
)
22375 /* Implements target hook small_register_classes_for_mode_p. */
22377 arm_small_register_classes_for_mode_p (enum machine_mode mode ATTRIBUTE_UNUSED
)
22379 return TARGET_THUMB1
;
22382 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
22383 ARM insns and therefore guarantee that the shift count is modulo 256.
22384 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
22385 guarantee no particular behavior for out-of-range counts. */
22387 static unsigned HOST_WIDE_INT
22388 arm_shift_truncation_mask (enum machine_mode mode
)
22390 return mode
== SImode
? 255 : 0;
22394 /* Map internal gcc register numbers to DWARF2 register numbers. */
22397 arm_dbx_register_number (unsigned int regno
)
22402 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
22403 compatibility. The EABI defines them as registers 96-103. */
22404 if (IS_FPA_REGNUM (regno
))
22405 return (TARGET_AAPCS_BASED
? 96 : 16) + regno
- FIRST_FPA_REGNUM
;
22407 if (IS_VFP_REGNUM (regno
))
22409 /* See comment in arm_dwarf_register_span. */
22410 if (VFP_REGNO_OK_FOR_SINGLE (regno
))
22411 return 64 + regno
- FIRST_VFP_REGNUM
;
22413 return 256 + (regno
- FIRST_VFP_REGNUM
) / 2;
22416 if (IS_IWMMXT_GR_REGNUM (regno
))
22417 return 104 + regno
- FIRST_IWMMXT_GR_REGNUM
;
22419 if (IS_IWMMXT_REGNUM (regno
))
22420 return 112 + regno
- FIRST_IWMMXT_REGNUM
;
22422 gcc_unreachable ();
22425 /* Dwarf models VFPv3 registers as 32 64-bit registers.
22426 GCC models tham as 64 32-bit registers, so we need to describe this to
22427 the DWARF generation code. Other registers can use the default. */
22429 arm_dwarf_register_span (rtx rtl
)
22436 regno
= REGNO (rtl
);
22437 if (!IS_VFP_REGNUM (regno
))
22440 /* XXX FIXME: The EABI defines two VFP register ranges:
22441 64-95: Legacy VFPv2 numbering for S0-S31 (obsolescent)
22443 The recommended encoding for S0-S31 is a DW_OP_bit_piece of the
22444 corresponding D register. Until GDB supports this, we shall use the
22445 legacy encodings. We also use these encodings for D0-D15 for
22446 compatibility with older debuggers. */
22447 if (VFP_REGNO_OK_FOR_SINGLE (regno
))
22450 nregs
= GET_MODE_SIZE (GET_MODE (rtl
)) / 8;
22451 p
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nregs
));
22452 regno
= (regno
- FIRST_VFP_REGNUM
) / 2;
22453 for (i
= 0; i
< nregs
; i
++)
22454 XVECEXP (p
, 0, i
) = gen_rtx_REG (DImode
, 256 + regno
+ i
);
22459 #if ARM_UNWIND_INFO
22460 /* Emit unwind directives for a store-multiple instruction or stack pointer
22461 push during alignment.
22462 These should only ever be generated by the function prologue code, so
22463 expect them to have a particular form. */
22466 arm_unwind_emit_sequence (FILE * asm_out_file
, rtx p
)
22469 HOST_WIDE_INT offset
;
22470 HOST_WIDE_INT nregs
;
22476 e
= XVECEXP (p
, 0, 0);
22477 if (GET_CODE (e
) != SET
)
22480 /* First insn will adjust the stack pointer. */
22481 if (GET_CODE (e
) != SET
22482 || GET_CODE (XEXP (e
, 0)) != REG
22483 || REGNO (XEXP (e
, 0)) != SP_REGNUM
22484 || GET_CODE (XEXP (e
, 1)) != PLUS
)
22487 offset
= -INTVAL (XEXP (XEXP (e
, 1), 1));
22488 nregs
= XVECLEN (p
, 0) - 1;
22490 reg
= REGNO (XEXP (XVECEXP (p
, 0, 1), 1));
22493 /* The function prologue may also push pc, but not annotate it as it is
22494 never restored. We turn this into a stack pointer adjustment. */
22495 if (nregs
* 4 == offset
- 4)
22497 fprintf (asm_out_file
, "\t.pad #4\n");
22501 fprintf (asm_out_file
, "\t.save {");
22503 else if (IS_VFP_REGNUM (reg
))
22506 fprintf (asm_out_file
, "\t.vsave {");
22508 else if (reg
>= FIRST_FPA_REGNUM
&& reg
<= LAST_FPA_REGNUM
)
22510 /* FPA registers are done differently. */
22511 asm_fprintf (asm_out_file
, "\t.save %r, %wd\n", reg
, nregs
);
22515 /* Unknown register type. */
22518 /* If the stack increment doesn't match the size of the saved registers,
22519 something has gone horribly wrong. */
22520 if (offset
!= nregs
* reg_size
)
22525 /* The remaining insns will describe the stores. */
22526 for (i
= 1; i
<= nregs
; i
++)
22528 /* Expect (set (mem <addr>) (reg)).
22529 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
22530 e
= XVECEXP (p
, 0, i
);
22531 if (GET_CODE (e
) != SET
22532 || GET_CODE (XEXP (e
, 0)) != MEM
22533 || GET_CODE (XEXP (e
, 1)) != REG
)
22536 reg
= REGNO (XEXP (e
, 1));
22541 fprintf (asm_out_file
, ", ");
22542 /* We can't use %r for vfp because we need to use the
22543 double precision register names. */
22544 if (IS_VFP_REGNUM (reg
))
22545 asm_fprintf (asm_out_file
, "d%d", (reg
- FIRST_VFP_REGNUM
) / 2);
22547 asm_fprintf (asm_out_file
, "%r", reg
);
22549 #ifdef ENABLE_CHECKING
22550 /* Check that the addresses are consecutive. */
22551 e
= XEXP (XEXP (e
, 0), 0);
22552 if (GET_CODE (e
) == PLUS
)
22554 offset
+= reg_size
;
22555 if (GET_CODE (XEXP (e
, 0)) != REG
22556 || REGNO (XEXP (e
, 0)) != SP_REGNUM
22557 || GET_CODE (XEXP (e
, 1)) != CONST_INT
22558 || offset
!= INTVAL (XEXP (e
, 1)))
22562 || GET_CODE (e
) != REG
22563 || REGNO (e
) != SP_REGNUM
)
22567 fprintf (asm_out_file
, "}\n");
22570 /* Emit unwind directives for a SET. */
22573 arm_unwind_emit_set (FILE * asm_out_file
, rtx p
)
22581 switch (GET_CODE (e0
))
22584 /* Pushing a single register. */
22585 if (GET_CODE (XEXP (e0
, 0)) != PRE_DEC
22586 || GET_CODE (XEXP (XEXP (e0
, 0), 0)) != REG
22587 || REGNO (XEXP (XEXP (e0
, 0), 0)) != SP_REGNUM
)
22590 asm_fprintf (asm_out_file
, "\t.save ");
22591 if (IS_VFP_REGNUM (REGNO (e1
)))
22592 asm_fprintf(asm_out_file
, "{d%d}\n",
22593 (REGNO (e1
) - FIRST_VFP_REGNUM
) / 2);
22595 asm_fprintf(asm_out_file
, "{%r}\n", REGNO (e1
));
22599 if (REGNO (e0
) == SP_REGNUM
)
22601 /* A stack increment. */
22602 if (GET_CODE (e1
) != PLUS
22603 || GET_CODE (XEXP (e1
, 0)) != REG
22604 || REGNO (XEXP (e1
, 0)) != SP_REGNUM
22605 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
22608 asm_fprintf (asm_out_file
, "\t.pad #%wd\n",
22609 -INTVAL (XEXP (e1
, 1)));
22611 else if (REGNO (e0
) == HARD_FRAME_POINTER_REGNUM
)
22613 HOST_WIDE_INT offset
;
22615 if (GET_CODE (e1
) == PLUS
)
22617 if (GET_CODE (XEXP (e1
, 0)) != REG
22618 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
22620 reg
= REGNO (XEXP (e1
, 0));
22621 offset
= INTVAL (XEXP (e1
, 1));
22622 asm_fprintf (asm_out_file
, "\t.setfp %r, %r, #%wd\n",
22623 HARD_FRAME_POINTER_REGNUM
, reg
,
22626 else if (GET_CODE (e1
) == REG
)
22629 asm_fprintf (asm_out_file
, "\t.setfp %r, %r\n",
22630 HARD_FRAME_POINTER_REGNUM
, reg
);
22635 else if (GET_CODE (e1
) == REG
&& REGNO (e1
) == SP_REGNUM
)
22637 /* Move from sp to reg. */
22638 asm_fprintf (asm_out_file
, "\t.movsp %r\n", REGNO (e0
));
22640 else if (GET_CODE (e1
) == PLUS
22641 && GET_CODE (XEXP (e1
, 0)) == REG
22642 && REGNO (XEXP (e1
, 0)) == SP_REGNUM
22643 && GET_CODE (XEXP (e1
, 1)) == CONST_INT
)
22645 /* Set reg to offset from sp. */
22646 asm_fprintf (asm_out_file
, "\t.movsp %r, #%d\n",
22647 REGNO (e0
), (int)INTVAL(XEXP (e1
, 1)));
22649 else if (GET_CODE (e1
) == UNSPEC
&& XINT (e1
, 1) == UNSPEC_STACK_ALIGN
)
22651 /* Stack pointer save before alignment. */
22653 asm_fprintf (asm_out_file
, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n",
22666 /* Emit unwind directives for the given insn. */
22669 arm_unwind_emit (FILE * asm_out_file
, rtx insn
)
22673 if (arm_except_unwind_info (&global_options
) != UI_TARGET
)
22676 if (!(flag_unwind_tables
|| crtl
->uses_eh_lsda
)
22677 && (TREE_NOTHROW (current_function_decl
)
22678 || crtl
->all_throwers_are_sibcalls
))
22681 if (GET_CODE (insn
) == NOTE
|| !RTX_FRAME_RELATED_P (insn
))
22684 pat
= find_reg_note (insn
, REG_FRAME_RELATED_EXPR
, NULL_RTX
);
22686 pat
= XEXP (pat
, 0);
22688 pat
= PATTERN (insn
);
22690 switch (GET_CODE (pat
))
22693 arm_unwind_emit_set (asm_out_file
, pat
);
22697 /* Store multiple. */
22698 arm_unwind_emit_sequence (asm_out_file
, pat
);
22707 /* Output a reference from a function exception table to the type_info
22708 object X. The EABI specifies that the symbol should be relocated by
22709 an R_ARM_TARGET2 relocation. */
22712 arm_output_ttype (rtx x
)
22714 fputs ("\t.word\t", asm_out_file
);
22715 output_addr_const (asm_out_file
, x
);
22716 /* Use special relocations for symbol references. */
22717 if (GET_CODE (x
) != CONST_INT
)
22718 fputs ("(TARGET2)", asm_out_file
);
22719 fputc ('\n', asm_out_file
);
22724 /* Implement TARGET_ASM_EMIT_EXCEPT_PERSONALITY. */
22727 arm_asm_emit_except_personality (rtx personality
)
22729 fputs ("\t.personality\t", asm_out_file
);
22730 output_addr_const (asm_out_file
, personality
);
22731 fputc ('\n', asm_out_file
);
22734 /* Implement TARGET_ASM_INITIALIZE_SECTIONS. */
22737 arm_asm_init_sections (void)
22739 exception_section
= get_unnamed_section (0, output_section_asm_op
,
22742 #endif /* ARM_UNWIND_INFO */
22744 /* Implement TARGET_EXCEPT_UNWIND_INFO. */
22746 static enum unwind_info_type
22747 arm_except_unwind_info (struct gcc_options
*opts
)
22749 /* Honor the --enable-sjlj-exceptions configure switch. */
22750 #ifdef CONFIG_SJLJ_EXCEPTIONS
22751 if (CONFIG_SJLJ_EXCEPTIONS
)
22755 /* If not using ARM EABI unwind tables... */
22756 if (ARM_UNWIND_INFO
)
22758 /* For simplicity elsewhere in this file, indicate that all unwind
22759 info is disabled if we're not emitting unwind tables. */
22760 if (!opts
->x_flag_exceptions
&& !opts
->x_flag_unwind_tables
)
22766 /* ... we use sjlj exceptions for backwards compatibility. */
22771 /* Handle UNSPEC DWARF call frame instructions. These are needed for dynamic
22772 stack alignment. */
22775 arm_dwarf_handle_frame_unspec (const char *label
, rtx pattern
, int index
)
22777 rtx unspec
= SET_SRC (pattern
);
22778 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
22782 case UNSPEC_STACK_ALIGN
:
22783 /* ??? We should set the CFA = (SP & ~7). At this point we haven't
22784 put anything on the stack, so hopefully it won't matter.
22785 CFA = SP will be correct after alignment. */
22786 dwarf2out_reg_save_reg (label
, stack_pointer_rtx
,
22787 SET_DEST (pattern
));
22790 gcc_unreachable ();
22795 /* Output unwind directives for the start/end of a function. */
22798 arm_output_fn_unwind (FILE * f
, bool prologue
)
22800 if (arm_except_unwind_info (&global_options
) != UI_TARGET
)
22804 fputs ("\t.fnstart\n", f
);
22807 /* If this function will never be unwound, then mark it as such.
22808 The came condition is used in arm_unwind_emit to suppress
22809 the frame annotations. */
22810 if (!(flag_unwind_tables
|| crtl
->uses_eh_lsda
)
22811 && (TREE_NOTHROW (current_function_decl
)
22812 || crtl
->all_throwers_are_sibcalls
))
22813 fputs("\t.cantunwind\n", f
);
22815 fputs ("\t.fnend\n", f
);
22820 arm_emit_tls_decoration (FILE *fp
, rtx x
)
22822 enum tls_reloc reloc
;
22825 val
= XVECEXP (x
, 0, 0);
22826 reloc
= (enum tls_reloc
) INTVAL (XVECEXP (x
, 0, 1));
22828 output_addr_const (fp
, val
);
22833 fputs ("(tlsgd)", fp
);
22836 fputs ("(tlsldm)", fp
);
22839 fputs ("(tlsldo)", fp
);
22842 fputs ("(gottpoff)", fp
);
22845 fputs ("(tpoff)", fp
);
22848 gcc_unreachable ();
22856 fputs (" + (. - ", fp
);
22857 output_addr_const (fp
, XVECEXP (x
, 0, 2));
22859 output_addr_const (fp
, XVECEXP (x
, 0, 3));
22869 /* ARM implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
22872 arm_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
22874 gcc_assert (size
== 4);
22875 fputs ("\t.word\t", file
);
22876 output_addr_const (file
, x
);
22877 fputs ("(tlsldo)", file
);
22880 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
22883 arm_output_addr_const_extra (FILE *fp
, rtx x
)
22885 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
22886 return arm_emit_tls_decoration (fp
, x
);
22887 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_PIC_LABEL
)
22890 int labelno
= INTVAL (XVECEXP (x
, 0, 0));
22892 ASM_GENERATE_INTERNAL_LABEL (label
, "LPIC", labelno
);
22893 assemble_name_raw (fp
, label
);
22897 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_GOTSYM_OFF
)
22899 assemble_name (fp
, "_GLOBAL_OFFSET_TABLE_");
22903 output_addr_const (fp
, XVECEXP (x
, 0, 0));
22907 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_SYMBOL_OFFSET
)
22909 output_addr_const (fp
, XVECEXP (x
, 0, 0));
22913 output_addr_const (fp
, XVECEXP (x
, 0, 1));
22917 else if (GET_CODE (x
) == CONST_VECTOR
)
22918 return arm_emit_vector_const (fp
, x
);
22923 /* Output assembly for a shift instruction.
22924 SET_FLAGS determines how the instruction modifies the condition codes.
22925 0 - Do not set condition codes.
22926 1 - Set condition codes.
22927 2 - Use smallest instruction. */
22929 arm_output_shift(rtx
* operands
, int set_flags
)
22932 static const char flag_chars
[3] = {'?', '.', '!'};
22937 c
= flag_chars
[set_flags
];
22938 if (TARGET_UNIFIED_ASM
)
22940 shift
= shift_op(operands
[3], &val
);
22944 operands
[2] = GEN_INT(val
);
22945 sprintf (pattern
, "%s%%%c\t%%0, %%1, %%2", shift
, c
);
22948 sprintf (pattern
, "mov%%%c\t%%0, %%1", c
);
22951 sprintf (pattern
, "mov%%%c\t%%0, %%1%%S3", c
);
22952 output_asm_insn (pattern
, operands
);
22956 /* Output a Thumb-1 casesi dispatch sequence. */
22958 thumb1_output_casesi (rtx
*operands
)
22960 rtx diff_vec
= PATTERN (next_real_insn (operands
[0]));
22962 gcc_assert (GET_CODE (diff_vec
) == ADDR_DIFF_VEC
);
22964 switch (GET_MODE(diff_vec
))
22967 return (ADDR_DIFF_VEC_FLAGS (diff_vec
).offset_unsigned
?
22968 "bl\t%___gnu_thumb1_case_uqi" : "bl\t%___gnu_thumb1_case_sqi");
22970 return (ADDR_DIFF_VEC_FLAGS (diff_vec
).offset_unsigned
?
22971 "bl\t%___gnu_thumb1_case_uhi" : "bl\t%___gnu_thumb1_case_shi");
22973 return "bl\t%___gnu_thumb1_case_si";
22975 gcc_unreachable ();
22979 /* Output a Thumb-2 casesi instruction. */
22981 thumb2_output_casesi (rtx
*operands
)
22983 rtx diff_vec
= PATTERN (next_real_insn (operands
[2]));
22985 gcc_assert (GET_CODE (diff_vec
) == ADDR_DIFF_VEC
);
22987 output_asm_insn ("cmp\t%0, %1", operands
);
22988 output_asm_insn ("bhi\t%l3", operands
);
22989 switch (GET_MODE(diff_vec
))
22992 return "tbb\t[%|pc, %0]";
22994 return "tbh\t[%|pc, %0, lsl #1]";
22998 output_asm_insn ("adr\t%4, %l2", operands
);
22999 output_asm_insn ("ldr\t%5, [%4, %0, lsl #2]", operands
);
23000 output_asm_insn ("add\t%4, %4, %5", operands
);
23005 output_asm_insn ("adr\t%4, %l2", operands
);
23006 return "ldr\t%|pc, [%4, %0, lsl #2]";
23009 gcc_unreachable ();
23013 /* Most ARM cores are single issue, but some newer ones can dual issue.
23014 The scheduler descriptions rely on this being correct. */
23016 arm_issue_rate (void)
23033 /* A table and a function to perform ARM-specific name mangling for
23034 NEON vector types in order to conform to the AAPCS (see "Procedure
23035 Call Standard for the ARM Architecture", Appendix A). To qualify
23036 for emission with the mangled names defined in that document, a
23037 vector type must not only be of the correct mode but also be
23038 composed of NEON vector element types (e.g. __builtin_neon_qi). */
23041 enum machine_mode mode
;
23042 const char *element_type_name
;
23043 const char *aapcs_name
;
23044 } arm_mangle_map_entry
;
23046 static arm_mangle_map_entry arm_mangle_map
[] = {
23047 /* 64-bit containerized types. */
23048 { V8QImode
, "__builtin_neon_qi", "15__simd64_int8_t" },
23049 { V8QImode
, "__builtin_neon_uqi", "16__simd64_uint8_t" },
23050 { V4HImode
, "__builtin_neon_hi", "16__simd64_int16_t" },
23051 { V4HImode
, "__builtin_neon_uhi", "17__simd64_uint16_t" },
23052 { V2SImode
, "__builtin_neon_si", "16__simd64_int32_t" },
23053 { V2SImode
, "__builtin_neon_usi", "17__simd64_uint32_t" },
23054 { V2SFmode
, "__builtin_neon_sf", "18__simd64_float32_t" },
23055 { V8QImode
, "__builtin_neon_poly8", "16__simd64_poly8_t" },
23056 { V4HImode
, "__builtin_neon_poly16", "17__simd64_poly16_t" },
23057 /* 128-bit containerized types. */
23058 { V16QImode
, "__builtin_neon_qi", "16__simd128_int8_t" },
23059 { V16QImode
, "__builtin_neon_uqi", "17__simd128_uint8_t" },
23060 { V8HImode
, "__builtin_neon_hi", "17__simd128_int16_t" },
23061 { V8HImode
, "__builtin_neon_uhi", "18__simd128_uint16_t" },
23062 { V4SImode
, "__builtin_neon_si", "17__simd128_int32_t" },
23063 { V4SImode
, "__builtin_neon_usi", "18__simd128_uint32_t" },
23064 { V4SFmode
, "__builtin_neon_sf", "19__simd128_float32_t" },
23065 { V16QImode
, "__builtin_neon_poly8", "17__simd128_poly8_t" },
23066 { V8HImode
, "__builtin_neon_poly16", "18__simd128_poly16_t" },
23067 { VOIDmode
, NULL
, NULL
}
23071 arm_mangle_type (const_tree type
)
23073 arm_mangle_map_entry
*pos
= arm_mangle_map
;
23075 /* The ARM ABI documents (10th October 2008) say that "__va_list"
23076 has to be managled as if it is in the "std" namespace. */
23077 if (TARGET_AAPCS_BASED
23078 && lang_hooks
.types_compatible_p (CONST_CAST_TREE (type
), va_list_type
))
23080 static bool warned
;
23081 if (!warned
&& warn_psabi
&& !in_system_header
)
23084 inform (input_location
,
23085 "the mangling of %<va_list%> has changed in GCC 4.4");
23087 return "St9__va_list";
23090 /* Half-precision float. */
23091 if (TREE_CODE (type
) == REAL_TYPE
&& TYPE_PRECISION (type
) == 16)
23094 if (TREE_CODE (type
) != VECTOR_TYPE
)
23097 /* Check the mode of the vector type, and the name of the vector
23098 element type, against the table. */
23099 while (pos
->mode
!= VOIDmode
)
23101 tree elt_type
= TREE_TYPE (type
);
23103 if (pos
->mode
== TYPE_MODE (type
)
23104 && TREE_CODE (TYPE_NAME (elt_type
)) == TYPE_DECL
23105 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (elt_type
))),
23106 pos
->element_type_name
))
23107 return pos
->aapcs_name
;
23112 /* Use the default mangling for unrecognized (possibly user-defined)
23117 /* Order of allocation of core registers for Thumb: this allocation is
23118 written over the corresponding initial entries of the array
23119 initialized with REG_ALLOC_ORDER. We allocate all low registers
23120 first. Saving and restoring a low register is usually cheaper than
23121 using a call-clobbered high register. */
23123 static const int thumb_core_reg_alloc_order
[] =
23125 3, 2, 1, 0, 4, 5, 6, 7,
23126 14, 12, 8, 9, 10, 11, 13, 15
23129 /* Adjust register allocation order when compiling for Thumb. */
23132 arm_order_regs_for_local_alloc (void)
23134 const int arm_reg_alloc_order
[] = REG_ALLOC_ORDER
;
23135 memcpy(reg_alloc_order
, arm_reg_alloc_order
, sizeof (reg_alloc_order
));
23137 memcpy (reg_alloc_order
, thumb_core_reg_alloc_order
,
23138 sizeof (thumb_core_reg_alloc_order
));
23141 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
23144 arm_frame_pointer_required (void)
23146 return (cfun
->has_nonlocal_label
23147 || SUBTARGET_FRAME_POINTER_REQUIRED
23148 || (TARGET_ARM
&& TARGET_APCS_FRAME
&& ! leaf_function_p ()));
23151 /* Only thumb1 can't support conditional execution, so return true if
23152 the target is not thumb1. */
23154 arm_have_conditional_execution (void)
23156 return !TARGET_THUMB1
;
23159 /* Legitimize a memory reference for sync primitive implemented using
23160 ldrex / strex. We currently force the form of the reference to be
23161 indirect without offset. We do not yet support the indirect offset
23162 addressing supported by some ARM targets for these
23165 arm_legitimize_sync_memory (rtx memory
)
23167 rtx addr
= force_reg (Pmode
, XEXP (memory
, 0));
23168 rtx legitimate_memory
= gen_rtx_MEM (GET_MODE (memory
), addr
);
23170 set_mem_alias_set (legitimate_memory
, ALIAS_SET_MEMORY_BARRIER
);
23171 MEM_VOLATILE_P (legitimate_memory
) = MEM_VOLATILE_P (memory
);
23172 return legitimate_memory
;
23175 /* An instruction emitter. */
23176 typedef void (* emit_f
) (int label
, const char *, rtx
*);
23178 /* An instruction emitter that emits via the conventional
23179 output_asm_insn. */
23181 arm_emit (int label ATTRIBUTE_UNUSED
, const char *pattern
, rtx
*operands
)
23183 output_asm_insn (pattern
, operands
);
23186 /* Count the number of emitted synchronization instructions. */
23187 static unsigned arm_insn_count
;
23189 /* An emitter that counts emitted instructions but does not actually
23190 emit instruction into the instruction stream. */
23192 arm_count (int label
,
23193 const char *pattern ATTRIBUTE_UNUSED
,
23194 rtx
*operands ATTRIBUTE_UNUSED
)
23200 /* Construct a pattern using conventional output formatting and feed
23201 it to output_asm_insn. Provides a mechanism to construct the
23202 output pattern on the fly. Note the hard limit on the pattern
23204 static void ATTRIBUTE_PRINTF_4
23205 arm_output_asm_insn (emit_f emit
, int label
, rtx
*operands
,
23206 const char *pattern
, ...)
23211 va_start (ap
, pattern
);
23212 vsprintf (buffer
, pattern
, ap
);
23214 emit (label
, buffer
, operands
);
23217 /* Emit the memory barrier instruction, if any, provided by this
23218 target to a specified emitter. */
23220 arm_process_output_memory_barrier (emit_f emit
, rtx
*operands
)
23222 if (TARGET_HAVE_DMB
)
23224 /* Note we issue a system level barrier. We should consider
23225 issuing a inner shareabilty zone barrier here instead, ie.
23227 emit (0, "dmb\tsy", operands
);
23231 if (TARGET_HAVE_DMB_MCR
)
23233 emit (0, "mcr\tp15, 0, r0, c7, c10, 5", operands
);
23237 gcc_unreachable ();
23240 /* Emit the memory barrier instruction, if any, provided by this
23243 arm_output_memory_barrier (rtx
*operands
)
23245 arm_process_output_memory_barrier (arm_emit
, operands
);
23249 /* Helper to figure out the instruction suffix required on ldrex/strex
23250 for operations on an object of the specified mode. */
23251 static const char *
23252 arm_ldrex_suffix (enum machine_mode mode
)
23256 case QImode
: return "b";
23257 case HImode
: return "h";
23258 case SImode
: return "";
23259 case DImode
: return "d";
23261 gcc_unreachable ();
23266 /* Emit an ldrex{b,h,d, } instruction appropriate for the specified
23269 arm_output_ldrex (emit_f emit
,
23270 enum machine_mode mode
,
23274 const char *suffix
= arm_ldrex_suffix (mode
);
23277 operands
[0] = target
;
23278 operands
[1] = memory
;
23279 arm_output_asm_insn (emit
, 0, operands
, "ldrex%s\t%%0, %%C1", suffix
);
23282 /* Emit a strex{b,h,d, } instruction appropriate for the specified
23285 arm_output_strex (emit_f emit
,
23286 enum machine_mode mode
,
23292 const char *suffix
= arm_ldrex_suffix (mode
);
23295 operands
[0] = result
;
23296 operands
[1] = value
;
23297 operands
[2] = memory
;
23298 arm_output_asm_insn (emit
, 0, operands
, "strex%s%s\t%%0, %%1, %%C2", suffix
,
23302 /* Helper to emit a two operand instruction. */
23304 arm_output_op2 (emit_f emit
, const char *mnemonic
, rtx d
, rtx s
)
23310 arm_output_asm_insn (emit
, 0, operands
, "%s\t%%0, %%1", mnemonic
);
23313 /* Helper to emit a three operand instruction. */
23315 arm_output_op3 (emit_f emit
, const char *mnemonic
, rtx d
, rtx a
, rtx b
)
23322 arm_output_asm_insn (emit
, 0, operands
, "%s\t%%0, %%1, %%2", mnemonic
);
23325 /* Emit a load store exclusive synchronization loop.
23329 if old_value != required_value
23331 t1 = sync_op (old_value, new_value)
23332 [mem] = t1, t2 = [0|1]
23336 t1 == t2 is not permitted
23337 t1 == old_value is permitted
23341 RTX register or const_int representing the required old_value for
23342 the modify to continue, if NULL no comparsion is performed. */
23344 arm_output_sync_loop (emit_f emit
,
23345 enum machine_mode mode
,
23348 rtx required_value
,
23352 enum attr_sync_op sync_op
,
23353 int early_barrier_required
)
23357 gcc_assert (t1
!= t2
);
23359 if (early_barrier_required
)
23360 arm_process_output_memory_barrier (emit
, NULL
);
23362 arm_output_asm_insn (emit
, 1, operands
, "%sLSYT%%=:", LOCAL_LABEL_PREFIX
);
23364 arm_output_ldrex (emit
, mode
, old_value
, memory
);
23366 if (required_value
)
23370 operands
[0] = old_value
;
23371 operands
[1] = required_value
;
23372 arm_output_asm_insn (emit
, 0, operands
, "cmp\t%%0, %%1");
23373 arm_output_asm_insn (emit
, 0, operands
, "bne\t%sLSYB%%=", LOCAL_LABEL_PREFIX
);
23379 arm_output_op3 (emit
, "add", t1
, old_value
, new_value
);
23383 arm_output_op3 (emit
, "sub", t1
, old_value
, new_value
);
23387 arm_output_op3 (emit
, "orr", t1
, old_value
, new_value
);
23391 arm_output_op3 (emit
, "eor", t1
, old_value
, new_value
);
23395 arm_output_op3 (emit
,"and", t1
, old_value
, new_value
);
23399 arm_output_op3 (emit
, "and", t1
, old_value
, new_value
);
23400 arm_output_op2 (emit
, "mvn", t1
, t1
);
23410 arm_output_strex (emit
, mode
, "", t2
, t1
, memory
);
23412 arm_output_asm_insn (emit
, 0, operands
, "teq\t%%0, #0");
23413 arm_output_asm_insn (emit
, 0, operands
, "bne\t%sLSYT%%=",
23414 LOCAL_LABEL_PREFIX
);
23418 /* Use old_value for the return value because for some operations
23419 the old_value can easily be restored. This saves one register. */
23420 arm_output_strex (emit
, mode
, "", old_value
, t1
, memory
);
23421 operands
[0] = old_value
;
23422 arm_output_asm_insn (emit
, 0, operands
, "teq\t%%0, #0");
23423 arm_output_asm_insn (emit
, 0, operands
, "bne\t%sLSYT%%=",
23424 LOCAL_LABEL_PREFIX
);
23429 arm_output_op3 (emit
, "sub", old_value
, t1
, new_value
);
23433 arm_output_op3 (emit
, "add", old_value
, t1
, new_value
);
23437 arm_output_op3 (emit
, "eor", old_value
, t1
, new_value
);
23441 arm_output_op2 (emit
, "mov", old_value
, required_value
);
23445 gcc_unreachable ();
23449 arm_process_output_memory_barrier (emit
, NULL
);
23450 arm_output_asm_insn (emit
, 1, operands
, "%sLSYB%%=:", LOCAL_LABEL_PREFIX
);
23454 arm_get_sync_operand (rtx
*operands
, int index
, rtx default_value
)
23457 default_value
= operands
[index
- 1];
23459 return default_value
;
23462 #define FETCH_SYNC_OPERAND(NAME, DEFAULT) \
23463 arm_get_sync_operand (operands, (int) get_attr_sync_##NAME (insn), DEFAULT);
23465 /* Extract the operands for a synchroniztion instruction from the
23466 instructions attributes and emit the instruction. */
23468 arm_process_output_sync_insn (emit_f emit
, rtx insn
, rtx
*operands
)
23470 rtx result
, memory
, required_value
, new_value
, t1
, t2
;
23472 enum machine_mode mode
;
23473 enum attr_sync_op sync_op
;
23475 result
= FETCH_SYNC_OPERAND(result
, 0);
23476 memory
= FETCH_SYNC_OPERAND(memory
, 0);
23477 required_value
= FETCH_SYNC_OPERAND(required_value
, 0);
23478 new_value
= FETCH_SYNC_OPERAND(new_value
, 0);
23479 t1
= FETCH_SYNC_OPERAND(t1
, 0);
23480 t2
= FETCH_SYNC_OPERAND(t2
, 0);
23482 get_attr_sync_release_barrier (insn
) == SYNC_RELEASE_BARRIER_YES
;
23483 sync_op
= get_attr_sync_op (insn
);
23484 mode
= GET_MODE (memory
);
23486 arm_output_sync_loop (emit
, mode
, result
, memory
, required_value
,
23487 new_value
, t1
, t2
, sync_op
, early_barrier
);
23490 /* Emit a synchronization instruction loop. */
23492 arm_output_sync_insn (rtx insn
, rtx
*operands
)
23494 arm_process_output_sync_insn (arm_emit
, insn
, operands
);
23498 /* Count the number of machine instruction that will be emitted for a
23499 synchronization instruction. Note that the emitter used does not
23500 emit instructions, it just counts instructions being carefull not
23501 to count labels. */
23503 arm_sync_loop_insns (rtx insn
, rtx
*operands
)
23505 arm_insn_count
= 0;
23506 arm_process_output_sync_insn (arm_count
, insn
, operands
);
23507 return arm_insn_count
;
23510 /* Helper to call a target sync instruction generator, dealing with
23511 the variation in operands required by the different generators. */
23513 arm_call_generator (struct arm_sync_generator
*generator
, rtx old_value
,
23514 rtx memory
, rtx required_value
, rtx new_value
)
23516 switch (generator
->op
)
23518 case arm_sync_generator_omn
:
23519 gcc_assert (! required_value
);
23520 return generator
->u
.omn (old_value
, memory
, new_value
);
23522 case arm_sync_generator_omrn
:
23523 gcc_assert (required_value
);
23524 return generator
->u
.omrn (old_value
, memory
, required_value
, new_value
);
23530 /* Expand a synchronization loop. The synchronization loop is expanded
23531 as an opaque block of instructions in order to ensure that we do
23532 not subsequently get extraneous memory accesses inserted within the
23533 critical region. The exclusive access property of ldrex/strex is
23534 only guaranteed in there are no intervening memory accesses. */
23536 arm_expand_sync (enum machine_mode mode
,
23537 struct arm_sync_generator
*generator
,
23538 rtx target
, rtx memory
, rtx required_value
, rtx new_value
)
23540 if (target
== NULL
)
23541 target
= gen_reg_rtx (mode
);
23543 memory
= arm_legitimize_sync_memory (memory
);
23544 if (mode
!= SImode
)
23546 rtx load_temp
= gen_reg_rtx (SImode
);
23548 if (required_value
)
23549 required_value
= convert_modes (SImode
, mode
, required_value
, true);
23551 new_value
= convert_modes (SImode
, mode
, new_value
, true);
23552 emit_insn (arm_call_generator (generator
, load_temp
, memory
,
23553 required_value
, new_value
));
23554 emit_move_insn (target
, gen_lowpart (mode
, load_temp
));
23558 emit_insn (arm_call_generator (generator
, target
, memory
, required_value
,
23563 static unsigned int
23564 arm_autovectorize_vector_sizes (void)
23566 return TARGET_NEON_VECTORIZE_QUAD
? 16 | 8 : 0;
23570 arm_vector_alignment_reachable (const_tree type
, bool is_packed
)
23572 /* Vectors which aren't in packed structures will not be less aligned than
23573 the natural alignment of their element type, so this is safe. */
23574 if (TARGET_NEON
&& !BYTES_BIG_ENDIAN
)
23577 return default_builtin_vector_alignment_reachable (type
, is_packed
);
23581 arm_builtin_support_vector_misalignment (enum machine_mode mode
,
23582 const_tree type
, int misalignment
,
23585 if (TARGET_NEON
&& !BYTES_BIG_ENDIAN
)
23587 HOST_WIDE_INT align
= TYPE_ALIGN_UNIT (type
);
23592 /* If the misalignment is unknown, we should be able to handle the access
23593 so long as it is not to a member of a packed data structure. */
23594 if (misalignment
== -1)
23597 /* Return true if the misalignment is a multiple of the natural alignment
23598 of the vector's element type. This is probably always going to be
23599 true in practice, since we've already established that this isn't a
23601 return ((misalignment
% align
) == 0);
23604 return default_builtin_support_vector_misalignment (mode
, type
, misalignment
,
23609 arm_conditional_register_usage (void)
23613 if (TARGET_SOFT_FLOAT
|| TARGET_THUMB1
|| !TARGET_FPA
)
23615 for (regno
= FIRST_FPA_REGNUM
;
23616 regno
<= LAST_FPA_REGNUM
; ++regno
)
23617 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
23620 if (TARGET_THUMB1
&& optimize_size
)
23622 /* When optimizing for size on Thumb-1, it's better not
23623 to use the HI regs, because of the overhead of
23625 for (regno
= FIRST_HI_REGNUM
;
23626 regno
<= LAST_HI_REGNUM
; ++regno
)
23627 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
23630 /* The link register can be clobbered by any branch insn,
23631 but we have no way to track that at present, so mark
23632 it as unavailable. */
23634 fixed_regs
[LR_REGNUM
] = call_used_regs
[LR_REGNUM
] = 1;
23636 if (TARGET_32BIT
&& TARGET_HARD_FLOAT
)
23638 if (TARGET_MAVERICK
)
23640 for (regno
= FIRST_FPA_REGNUM
;
23641 regno
<= LAST_FPA_REGNUM
; ++ regno
)
23642 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
23643 for (regno
= FIRST_CIRRUS_FP_REGNUM
;
23644 regno
<= LAST_CIRRUS_FP_REGNUM
; ++ regno
)
23646 fixed_regs
[regno
] = 0;
23647 call_used_regs
[regno
] = regno
< FIRST_CIRRUS_FP_REGNUM
+ 4;
23652 /* VFPv3 registers are disabled when earlier VFP
23653 versions are selected due to the definition of
23654 LAST_VFP_REGNUM. */
23655 for (regno
= FIRST_VFP_REGNUM
;
23656 regno
<= LAST_VFP_REGNUM
; ++ regno
)
23658 fixed_regs
[regno
] = 0;
23659 call_used_regs
[regno
] = regno
< FIRST_VFP_REGNUM
+ 16
23660 || regno
>= FIRST_VFP_REGNUM
+ 32;
23665 if (TARGET_REALLY_IWMMXT
)
23667 regno
= FIRST_IWMMXT_GR_REGNUM
;
23668 /* The 2002/10/09 revision of the XScale ABI has wCG0
23669 and wCG1 as call-preserved registers. The 2002/11/21
23670 revision changed this so that all wCG registers are
23671 scratch registers. */
23672 for (regno
= FIRST_IWMMXT_GR_REGNUM
;
23673 regno
<= LAST_IWMMXT_GR_REGNUM
; ++ regno
)
23674 fixed_regs
[regno
] = 0;
23675 /* The XScale ABI has wR0 - wR9 as scratch registers,
23676 the rest as call-preserved registers. */
23677 for (regno
= FIRST_IWMMXT_REGNUM
;
23678 regno
<= LAST_IWMMXT_REGNUM
; ++ regno
)
23680 fixed_regs
[regno
] = 0;
23681 call_used_regs
[regno
] = regno
< FIRST_IWMMXT_REGNUM
+ 10;
23685 if ((unsigned) PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
23687 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
23688 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
23690 else if (TARGET_APCS_STACK
)
23692 fixed_regs
[10] = 1;
23693 call_used_regs
[10] = 1;
23695 /* -mcaller-super-interworking reserves r11 for calls to
23696 _interwork_r11_call_via_rN(). Making the register global
23697 is an easy way of ensuring that it remains valid for all
23699 if (TARGET_APCS_FRAME
|| TARGET_CALLER_INTERWORKING
23700 || TARGET_TPCS_FRAME
|| TARGET_TPCS_LEAF_FRAME
)
23702 fixed_regs
[ARM_HARD_FRAME_POINTER_REGNUM
] = 1;
23703 call_used_regs
[ARM_HARD_FRAME_POINTER_REGNUM
] = 1;
23704 if (TARGET_CALLER_INTERWORKING
)
23705 global_regs
[ARM_HARD_FRAME_POINTER_REGNUM
] = 1;
23707 SUBTARGET_CONDITIONAL_REGISTER_USAGE
23711 arm_preferred_rename_class (reg_class_t rclass
)
23713 /* Thumb-2 instructions using LO_REGS may be smaller than instructions
23714 using GENERIC_REGS. During register rename pass, we prefer LO_REGS,
23715 and code size can be reduced. */
23716 if (TARGET_THUMB2
&& rclass
== GENERAL_REGS
)
23722 /* Compute the atrribute "length" of insn "*push_multi".
23723 So this function MUST be kept in sync with that insn pattern. */
23725 arm_attr_length_push_multi(rtx parallel_op
, rtx first_op
)
23727 int i
, regno
, hi_reg
;
23728 int num_saves
= XVECLEN (parallel_op
, 0);
23735 regno
= REGNO (first_op
);
23736 hi_reg
= (REGNO_REG_CLASS (regno
) == HI_REGS
) && (regno
!= LR_REGNUM
);
23737 for (i
= 1; i
< num_saves
&& !hi_reg
; i
++)
23739 regno
= REGNO (XEXP (XVECEXP (parallel_op
, 0, i
), 0));
23740 hi_reg
|= (REGNO_REG_CLASS (regno
) == HI_REGS
) && (regno
!= LR_REGNUM
);
23748 #include "gt-arm.h"