1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 /* Forward definitions of types. */
55 typedef struct minipool_node Mnode
;
56 typedef struct minipool_fixup Mfix
;
58 const struct attribute_spec arm_attribute_table
[];
60 /* Forward function declarations. */
61 static void arm_add_gc_roots (void);
62 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, HOST_WIDE_INT
,
64 static unsigned bit_count (unsigned long);
65 static int arm_address_register_rtx_p (rtx
, int);
66 static int arm_legitimate_index_p (enum machine_mode
, rtx
, int);
67 static int thumb_base_register_rtx_p (rtx
, enum machine_mode
, int);
68 inline static int thumb_index_register_rtx_p (rtx
, int);
69 static int const_ok_for_op (HOST_WIDE_INT
, enum rtx_code
);
70 static rtx
emit_multi_reg_push (int);
71 static rtx
emit_sfm (int, int);
73 static bool arm_assemble_integer (rtx
, unsigned int, int);
75 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
76 static arm_cc
get_arm_condition_code (rtx
);
77 static void init_fpa_table (void);
78 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
79 static rtx
is_jump_table (rtx
);
80 static const char *output_multi_immediate (rtx
*, const char *, const char *,
82 static void print_multi_reg (FILE *, const char *, int, int);
83 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
84 static struct machine_function
*arm_init_machine_status (void);
85 static int number_of_first_bit_set (int);
86 static void replace_symbols_in_block (tree
, rtx
, rtx
);
87 static void thumb_exit (FILE *, int, rtx
);
88 static void thumb_pushpop (FILE *, int, int);
89 static const char *thumb_condition_code (rtx
, int);
90 static rtx
is_jump_table (rtx
);
91 static HOST_WIDE_INT
get_jump_table_size (rtx
);
92 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
93 static Mnode
*add_minipool_forward_ref (Mfix
*);
94 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
95 static Mnode
*add_minipool_backward_ref (Mfix
*);
96 static void assign_minipool_offsets (Mfix
*);
97 static void arm_print_value (FILE *, rtx
);
98 static void dump_minipool (rtx
);
99 static int arm_barrier_cost (rtx
);
100 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
101 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
102 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
104 static void arm_reorg (void);
105 static bool note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
106 static int current_file_function_operand (rtx
);
107 static unsigned long arm_compute_save_reg0_reg12_mask (void);
108 static unsigned long arm_compute_save_reg_mask (void);
109 static unsigned long arm_isr_value (tree
);
110 static unsigned long arm_compute_func_type (void);
111 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
112 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
113 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
114 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
115 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT
);
116 static int arm_comp_type_attributes (tree
, tree
);
117 static void arm_set_default_type_attributes (tree
);
118 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
119 static int arm_use_dfa_pipeline_interface (void);
120 static int count_insns_for_constant (HOST_WIDE_INT
, int);
121 static int arm_get_strip_length (int);
122 static bool arm_function_ok_for_sibcall (tree
, tree
);
123 static void arm_internal_label (FILE *, const char *, unsigned long);
124 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
126 static int arm_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
127 static bool arm_rtx_costs (rtx
, int, int, int *);
128 static int arm_address_cost (rtx
);
129 static bool arm_memory_load_p (rtx
);
130 static bool arm_cirrus_insn_p (rtx
);
131 static void cirrus_reorg (rtx
);
132 static void arm_init_builtins (void);
133 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
134 static void arm_init_iwmmxt_builtins (void);
135 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
136 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
137 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
138 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
140 #ifdef OBJECT_FORMAT_ELF
141 static void arm_elf_asm_named_section (const char *, unsigned int);
144 static void arm_encode_section_info (tree
, rtx
, int);
147 static void aof_globalize_label (FILE *, const char *);
148 static void aof_dump_imports (FILE *);
149 static void aof_dump_pic_table (FILE *);
150 static void aof_file_start (void);
151 static void aof_file_end (void);
155 /* Initialize the GCC target structure. */
156 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
157 #undef TARGET_MERGE_DECL_ATTRIBUTES
158 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
161 #undef TARGET_ATTRIBUTE_TABLE
162 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
165 #undef TARGET_ASM_BYTE_OP
166 #define TARGET_ASM_BYTE_OP "\tDCB\t"
167 #undef TARGET_ASM_ALIGNED_HI_OP
168 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
169 #undef TARGET_ASM_ALIGNED_SI_OP
170 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
171 #undef TARGET_ASM_GLOBALIZE_LABEL
172 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
173 #undef TARGET_ASM_FILE_START
174 #define TARGET_ASM_FILE_START aof_file_start
175 #undef TARGET_ASM_FILE_END
176 #define TARGET_ASM_FILE_END aof_file_end
178 #undef TARGET_ASM_ALIGNED_SI_OP
179 #define TARGET_ASM_ALIGNED_SI_OP NULL
180 #undef TARGET_ASM_INTEGER
181 #define TARGET_ASM_INTEGER arm_assemble_integer
184 #undef TARGET_ASM_FUNCTION_PROLOGUE
185 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
187 #undef TARGET_ASM_FUNCTION_EPILOGUE
188 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
190 #undef TARGET_COMP_TYPE_ATTRIBUTES
191 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
193 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
194 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
196 #undef TARGET_SCHED_ADJUST_COST
197 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
199 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
200 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE arm_use_dfa_pipeline_interface
202 #undef TARGET_ENCODE_SECTION_INFO
204 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
206 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
209 #undef TARGET_STRIP_NAME_ENCODING
210 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
212 #undef TARGET_ASM_INTERNAL_LABEL
213 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
215 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
216 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
218 #undef TARGET_ASM_OUTPUT_MI_THUNK
219 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
220 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
221 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
223 #undef TARGET_RTX_COSTS
224 #define TARGET_RTX_COSTS arm_rtx_costs
225 #undef TARGET_ADDRESS_COST
226 #define TARGET_ADDRESS_COST arm_address_cost
228 #undef TARGET_MACHINE_DEPENDENT_REORG
229 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
231 #undef TARGET_INIT_BUILTINS
232 #define TARGET_INIT_BUILTINS arm_init_builtins
233 #undef TARGET_EXPAND_BUILTIN
234 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
236 struct gcc_target targetm
= TARGET_INITIALIZER
;
238 /* Obstack for minipool constant handling. */
239 static struct obstack minipool_obstack
;
240 static char * minipool_startobj
;
242 /* The maximum number of insns skipped which
243 will be conditionalised if possible. */
244 static int max_insns_skipped
= 5;
246 extern FILE * asm_out_file
;
248 /* True if we are currently building a constant table. */
249 int making_const_table
;
251 /* Define the information needed to generate branch insns. This is
252 stored from the compare operation. */
253 rtx arm_compare_op0
, arm_compare_op1
;
255 /* What type of floating point are we tuning for? */
256 enum fputype arm_fpu_tune
;
258 /* What type of floating point instructions are available? */
259 enum fputype arm_fpu_arch
;
261 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
262 enum prog_mode_type arm_prgmode
;
264 /* Set by the -mfp=... option. */
265 const char * target_fp_name
= NULL
;
267 /* Used to parse -mstructure_size_boundary command line option. */
268 const char * structure_size_string
= NULL
;
269 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
271 /* Bit values used to identify processor capabilities. */
272 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
273 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
274 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
275 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
276 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
277 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
278 #define FL_THUMB (1 << 6) /* Thumb aware */
279 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
280 #define FL_STRONG (1 << 8) /* StrongARM */
281 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
282 #define FL_XSCALE (1 << 10) /* XScale */
283 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
284 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
286 /* The bits in this mask specify which
287 instructions we are allowed to generate. */
288 static unsigned long insn_flags
= 0;
290 /* The bits in this mask specify which instruction scheduling options should
291 be used. Note - there is an overlap with the FL_FAST_MULT. For some
292 hardware we want to be able to generate the multiply instructions, but to
293 tune as if they were not present in the architecture. */
294 static unsigned long tune_flags
= 0;
296 /* The following are used in the arm.md file as equivalents to bits
297 in the above two flag variables. */
299 /* Nonzero if this is an "M" variant of the processor. */
300 int arm_fast_multiply
= 0;
302 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
305 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
308 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
311 /* Nonzero if this chip can benefit from load scheduling. */
312 int arm_ld_sched
= 0;
314 /* Nonzero if this chip is a StrongARM. */
315 int arm_is_strong
= 0;
317 /* Nonzero if this chip supports Intel Wireless MMX technology. */
318 int arm_arch_iwmmxt
= 0;
320 /* Nonzero if this chip is an XScale. */
321 int arm_arch_xscale
= 0;
323 /* Nonzero if tuning for XScale */
324 int arm_tune_xscale
= 0;
326 /* Nonzero if this chip is an ARM6 or an ARM7. */
327 int arm_is_6_or_7
= 0;
329 /* Nonzero if this chip is a Cirrus/DSP. */
330 int arm_is_cirrus
= 0;
332 /* Nonzero if generating Thumb instructions. */
335 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
336 must report the mode of the memory reference from PRINT_OPERAND to
337 PRINT_OPERAND_ADDRESS. */
338 enum machine_mode output_memory_reference_mode
;
340 /* The register number to be used for the PIC offset register. */
341 const char * arm_pic_register_string
= NULL
;
342 int arm_pic_register
= INVALID_REGNUM
;
344 /* Set to 1 when a return insn is output, this means that the epilogue
346 int return_used_this_function
;
348 /* Set to 1 after arm_reorg has started. Reset to start at the start of
349 the next function. */
350 static int after_arm_reorg
= 0;
352 /* The maximum number of insns to be used when loading a constant. */
353 static int arm_constant_limit
= 3;
355 /* For an explanation of these variables, see final_prescan_insn below. */
357 enum arm_cond_code arm_current_cc
;
359 int arm_target_label
;
361 /* The condition codes of the ARM, and the inverse function. */
362 static const char * const arm_condition_codes
[] =
364 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
365 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
368 #define streq(string1, string2) (strcmp (string1, string2) == 0)
370 /* Initialization code. */
374 const char *const name
;
375 const unsigned long flags
;
378 /* Not all of these give usefully different compilation alternatives,
379 but there is no simple way of generalizing them. */
380 static const struct processors all_cores
[] =
384 {"arm2", FL_CO_PROC
| FL_MODE26
},
385 {"arm250", FL_CO_PROC
| FL_MODE26
},
386 {"arm3", FL_CO_PROC
| FL_MODE26
},
387 {"arm6", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
388 {"arm60", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
389 {"arm600", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
390 {"arm610", FL_MODE26
| FL_MODE32
},
391 {"arm620", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
392 {"arm7", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
393 /* arm7m doesn't exist on its own, but only with D, (and I), but
394 those don't alter the code, so arm7m is sometimes used. */
395 {"arm7m", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
396 {"arm7d", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
397 {"arm7dm", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
398 {"arm7di", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
399 {"arm7dmi", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
400 {"arm70", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
401 {"arm700", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
402 {"arm700i", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
403 {"arm710", FL_MODE26
| FL_MODE32
},
404 {"arm720", FL_MODE26
| FL_MODE32
},
405 {"arm710c", FL_MODE26
| FL_MODE32
},
406 {"arm7100", FL_MODE26
| FL_MODE32
},
407 {"arm7500", FL_MODE26
| FL_MODE32
},
408 /* Doesn't have an external co-proc, but does have embedded fpa. */
409 {"arm7500fe", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
410 {"arm7tdmi", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
411 {"arm710t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
412 {"arm720t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
413 {"arm740t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
414 {"arm8", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
415 {"arm810", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
416 {"arm9", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
417 {"arm920", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
418 {"arm920t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
419 {"arm940t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
420 {"arm9tdmi", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
421 {"arm9e", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
422 {"ep9312", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_CIRRUS
},
423 {"strongarm", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
424 {"strongarm110", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
425 {"strongarm1100", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
426 {"strongarm1110", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
427 {"arm10tdmi", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_ARCH5
},
428 {"arm1020t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_ARCH5
},
429 {"xscale", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_STRONG
| FL_ARCH5
| FL_ARCH5E
| FL_XSCALE
},
430 {"iwmmxt", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_STRONG
| FL_ARCH5
| FL_ARCH5E
| FL_XSCALE
| FL_IWMMXT
},
435 static const struct processors all_architectures
[] =
437 /* ARM Architectures */
439 { "armv2", FL_CO_PROC
| FL_MODE26
},
440 { "armv2a", FL_CO_PROC
| FL_MODE26
},
441 { "armv3", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
442 { "armv3m", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
443 { "armv4", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
},
444 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
445 implementations that support it, so we will leave it out for now. */
446 { "armv4t", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
447 { "armv5", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
},
448 { "armv5t", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
},
449 { "armv5te", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
| FL_ARCH5E
},
450 { "ep9312", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_CIRRUS
},
451 {"iwmmxt", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_STRONG
| FL_ARCH5
| FL_ARCH5E
| FL_XSCALE
| FL_IWMMXT
},
455 /* This is a magic structure. The 'string' field is magically filled in
456 with a pointer to the value specified by the user on the command line
457 assuming that the user has specified such a value. */
459 struct arm_cpu_select arm_select
[] =
461 /* string name processors */
462 { NULL
, "-mcpu=", all_cores
},
463 { NULL
, "-march=", all_architectures
},
464 { NULL
, "-mtune=", all_cores
}
467 /* Return the number of bits set in VALUE. */
469 bit_count (unsigned long value
)
471 unsigned long count
= 0;
476 value
&= value
- 1; /* Clear the least-significant set bit. */
482 /* Fix up any incompatible options that the user has specified.
483 This has now turned into a maze. */
485 arm_override_options (void)
489 /* Set up the flags based on the cpu/architecture selected by the user. */
490 for (i
= ARRAY_SIZE (arm_select
); i
--;)
492 struct arm_cpu_select
* ptr
= arm_select
+ i
;
494 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
496 const struct processors
* sel
;
498 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
499 if (streq (ptr
->string
, sel
->name
))
502 tune_flags
= sel
->flags
;
505 /* If we have been given an architecture and a processor
506 make sure that they are compatible. We only generate
507 a warning though, and we prefer the CPU over the
509 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
510 warning ("switch -mcpu=%s conflicts with -march= switch",
513 insn_flags
= sel
->flags
;
519 if (sel
->name
== NULL
)
520 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
524 /* If the user did not specify a processor, choose one for them. */
527 const struct processors
* sel
;
529 static const struct cpu_default
532 const char *const name
;
536 { TARGET_CPU_arm2
, "arm2" },
537 { TARGET_CPU_arm6
, "arm6" },
538 { TARGET_CPU_arm610
, "arm610" },
539 { TARGET_CPU_arm710
, "arm710" },
540 { TARGET_CPU_arm7m
, "arm7m" },
541 { TARGET_CPU_arm7500fe
, "arm7500fe" },
542 { TARGET_CPU_arm7tdmi
, "arm7tdmi" },
543 { TARGET_CPU_arm8
, "arm8" },
544 { TARGET_CPU_arm810
, "arm810" },
545 { TARGET_CPU_arm9
, "arm9" },
546 { TARGET_CPU_strongarm
, "strongarm" },
547 { TARGET_CPU_xscale
, "xscale" },
548 { TARGET_CPU_ep9312
, "ep9312" },
549 { TARGET_CPU_iwmmxt
, "iwmmxt" },
550 { TARGET_CPU_generic
, "arm" },
553 const struct cpu_default
* def
;
555 /* Find the default. */
556 for (def
= cpu_defaults
; def
->name
; def
++)
557 if (def
->cpu
== TARGET_CPU_DEFAULT
)
560 /* Make sure we found the default CPU. */
561 if (def
->name
== NULL
)
564 /* Find the default CPU's flags. */
565 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
566 if (streq (def
->name
, sel
->name
))
569 if (sel
->name
== NULL
)
572 insn_flags
= sel
->flags
;
574 /* Now check to see if the user has specified some command line
575 switch that require certain abilities from the cpu. */
578 if (TARGET_INTERWORK
|| TARGET_THUMB
)
580 sought
|= (FL_THUMB
| FL_MODE32
);
582 /* Force apcs-32 to be used for interworking. */
583 target_flags
|= ARM_FLAG_APCS_32
;
585 /* There are no ARM processors that support both APCS-26 and
586 interworking. Therefore we force FL_MODE26 to be removed
587 from insn_flags here (if it was set), so that the search
588 below will always be able to find a compatible processor. */
589 insn_flags
&= ~FL_MODE26
;
591 else if (!TARGET_APCS_32
)
594 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
596 /* Try to locate a CPU type that supports all of the abilities
597 of the default CPU, plus the extra abilities requested by
599 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
600 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
603 if (sel
->name
== NULL
)
605 unsigned current_bit_count
= 0;
606 const struct processors
* best_fit
= NULL
;
608 /* Ideally we would like to issue an error message here
609 saying that it was not possible to find a CPU compatible
610 with the default CPU, but which also supports the command
611 line options specified by the programmer, and so they
612 ought to use the -mcpu=<name> command line option to
613 override the default CPU type.
615 Unfortunately this does not work with multilibing. We
616 need to be able to support multilibs for -mapcs-26 and for
617 -mthumb-interwork and there is no CPU that can support both
618 options. Instead if we cannot find a cpu that has both the
619 characteristics of the default cpu and the given command line
620 options we scan the array again looking for a best match. */
621 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
622 if ((sel
->flags
& sought
) == sought
)
626 count
= bit_count (sel
->flags
& insn_flags
);
628 if (count
>= current_bit_count
)
631 current_bit_count
= count
;
635 if (best_fit
== NULL
)
641 insn_flags
= sel
->flags
;
645 /* If tuning has not been specified, tune for whichever processor or
646 architecture has been selected. */
648 tune_flags
= insn_flags
;
650 /* Make sure that the processor choice does not conflict with any of the
651 other command line choices. */
652 if (TARGET_APCS_32
&& !(insn_flags
& FL_MODE32
))
654 /* If APCS-32 was not the default then it must have been set by the
655 user, so issue a warning message. If the user has specified
656 "-mapcs-32 -mcpu=arm2" then we loose here. */
657 if ((TARGET_DEFAULT
& ARM_FLAG_APCS_32
) == 0)
658 warning ("target CPU does not support APCS-32" );
659 target_flags
&= ~ARM_FLAG_APCS_32
;
661 else if (!TARGET_APCS_32
&& !(insn_flags
& FL_MODE26
))
663 warning ("target CPU does not support APCS-26" );
664 target_flags
|= ARM_FLAG_APCS_32
;
667 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
669 warning ("target CPU does not support interworking" );
670 target_flags
&= ~ARM_FLAG_INTERWORK
;
673 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
675 warning ("target CPU does not support THUMB instructions");
676 target_flags
&= ~ARM_FLAG_THUMB
;
679 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
681 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
682 target_flags
&= ~ARM_FLAG_APCS_FRAME
;
685 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
686 from here where no function is being compiled currently. */
687 if ((target_flags
& (THUMB_FLAG_LEAF_BACKTRACE
| THUMB_FLAG_BACKTRACE
))
689 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
691 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
692 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
694 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
695 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
697 /* If interworking is enabled then APCS-32 must be selected as well. */
698 if (TARGET_INTERWORK
)
701 warning ("interworking forces APCS-32 to be used" );
702 target_flags
|= ARM_FLAG_APCS_32
;
705 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
707 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
708 target_flags
|= ARM_FLAG_APCS_FRAME
;
711 if (TARGET_POKE_FUNCTION_NAME
)
712 target_flags
|= ARM_FLAG_APCS_FRAME
;
714 if (TARGET_APCS_REENT
&& flag_pic
)
715 error ("-fpic and -mapcs-reent are incompatible");
717 if (TARGET_APCS_REENT
)
718 warning ("APCS reentrant code not supported. Ignored");
720 /* If this target is normally configured to use APCS frames, warn if they
721 are turned off and debugging is turned on. */
723 && write_symbols
!= NO_DEBUG
724 && !TARGET_APCS_FRAME
725 && (TARGET_DEFAULT
& ARM_FLAG_APCS_FRAME
))
726 warning ("-g with -mno-apcs-frame may not give sensible debugging");
728 /* If stack checking is disabled, we can use r10 as the PIC register,
729 which keeps r9 available. */
731 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
733 if (TARGET_APCS_FLOAT
)
734 warning ("passing floating point arguments in fp regs not yet supported");
736 /* Initialize boolean versions of the flags, for use in the arm.md file. */
737 arm_fast_multiply
= (insn_flags
& FL_FAST_MULT
) != 0;
738 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
739 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
740 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
741 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
743 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
744 arm_is_strong
= (tune_flags
& FL_STRONG
) != 0;
745 thumb_code
= (TARGET_ARM
== 0);
746 arm_is_6_or_7
= (((tune_flags
& (FL_MODE26
| FL_MODE32
))
747 && !(tune_flags
& FL_ARCH4
))) != 0;
748 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
749 arm_is_cirrus
= (tune_flags
& FL_CIRRUS
) != 0;
750 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
752 if (TARGET_IWMMXT
&& (! TARGET_ATPCS
))
753 target_flags
|= ARM_FLAG_ATPCS
;
757 arm_fpu_tune
= FPUTYPE_MAVERICK
;
759 /* Ignore -mhard-float if -mcpu=ep9312. */
760 if (TARGET_HARD_FLOAT
)
761 target_flags
^= ARM_FLAG_SOFT_FLOAT
;
764 /* Default value for floating point code... if no co-processor
765 bus, then schedule for emulated floating point. Otherwise,
766 assume the user has an FPA.
767 Note: this does not prevent use of floating point instructions,
768 -msoft-float does that. */
769 arm_fpu_tune
= (tune_flags
& FL_CO_PROC
) ? FPUTYPE_FPA
: FPUTYPE_FPA_EMU3
;
773 if (streq (target_fp_name
, "2"))
774 arm_fpu_arch
= FPUTYPE_FPA_EMU2
;
775 else if (streq (target_fp_name
, "3"))
776 arm_fpu_arch
= FPUTYPE_FPA_EMU3
;
778 error ("invalid floating point emulation option: -mfpe-%s",
782 arm_fpu_arch
= FPUTYPE_DEFAULT
;
786 if (arm_fpu_tune
== FPUTYPE_FPA_EMU3
)
787 arm_fpu_tune
= FPUTYPE_FPA_EMU2
;
788 else if (arm_fpu_tune
== FPUTYPE_MAVERICK
)
789 warning ("-mfpe switch not supported by ep9312 target cpu - ignored.");
790 else if (arm_fpu_tune
!= FPUTYPE_FPA
)
791 arm_fpu_tune
= FPUTYPE_FPA_EMU2
;
794 /* For arm2/3 there is no need to do any scheduling if there is only
795 a floating point emulator, or we are doing software floating-point. */
796 if ((TARGET_SOFT_FLOAT
|| arm_fpu_tune
!= FPUTYPE_FPA
)
797 && (tune_flags
& FL_MODE32
) == 0)
798 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
800 arm_prgmode
= TARGET_APCS_32
? PROG_MODE_PROG32
: PROG_MODE_PROG26
;
802 if (structure_size_string
!= NULL
)
804 int size
= strtol (structure_size_string
, NULL
, 0);
806 if (size
== 8 || size
== 32)
807 arm_structure_size_boundary
= size
;
809 warning ("structure size boundary can only be set to 8 or 32");
812 if (arm_pic_register_string
!= NULL
)
814 int pic_register
= decode_reg_name (arm_pic_register_string
);
817 warning ("-mpic-register= is useless without -fpic");
819 /* Prevent the user from choosing an obviously stupid PIC register. */
820 else if (pic_register
< 0 || call_used_regs
[pic_register
]
821 || pic_register
== HARD_FRAME_POINTER_REGNUM
822 || pic_register
== STACK_POINTER_REGNUM
823 || pic_register
>= PC_REGNUM
)
824 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
826 arm_pic_register
= pic_register
;
829 if (TARGET_THUMB
&& flag_schedule_insns
)
831 /* Don't warn since it's on by default in -O2. */
832 flag_schedule_insns
= 0;
835 /* If optimizing for space, don't synthesize constants.
836 For processors with load scheduling, it never costs more than 2 cycles
837 to load a constant, and the load scheduler may well reduce that to 1. */
838 if (optimize_size
|| (tune_flags
& FL_LDSCHED
))
839 arm_constant_limit
= 1;
842 arm_constant_limit
= 2;
844 /* If optimizing for size, bump the number of instructions that we
845 are prepared to conditionally execute (even on a StrongARM).
846 Otherwise for the StrongARM, which has early execution of branches,
847 a sequence that is worth skipping is shorter. */
849 max_insns_skipped
= 6;
850 else if (arm_is_strong
)
851 max_insns_skipped
= 3;
853 /* Register global variables with the garbage collector. */
858 arm_add_gc_roots (void)
860 gcc_obstack_init(&minipool_obstack
);
861 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
864 /* A table of known ARM exception types.
865 For use with the interrupt function attribute. */
869 const char *const arg
;
870 const unsigned long return_value
;
874 static const isr_attribute_arg isr_attribute_args
[] =
876 { "IRQ", ARM_FT_ISR
},
877 { "irq", ARM_FT_ISR
},
878 { "FIQ", ARM_FT_FIQ
},
879 { "fiq", ARM_FT_FIQ
},
880 { "ABORT", ARM_FT_ISR
},
881 { "abort", ARM_FT_ISR
},
882 { "ABORT", ARM_FT_ISR
},
883 { "abort", ARM_FT_ISR
},
884 { "UNDEF", ARM_FT_EXCEPTION
},
885 { "undef", ARM_FT_EXCEPTION
},
886 { "SWI", ARM_FT_EXCEPTION
},
887 { "swi", ARM_FT_EXCEPTION
},
888 { NULL
, ARM_FT_NORMAL
}
891 /* Returns the (interrupt) function type of the current
892 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
895 arm_isr_value (tree argument
)
897 const isr_attribute_arg
* ptr
;
900 /* No argument - default to IRQ. */
901 if (argument
== NULL_TREE
)
904 /* Get the value of the argument. */
905 if (TREE_VALUE (argument
) == NULL_TREE
906 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
907 return ARM_FT_UNKNOWN
;
909 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
911 /* Check it against the list of known arguments. */
912 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
913 if (streq (arg
, ptr
->arg
))
914 return ptr
->return_value
;
916 /* An unrecognized interrupt type. */
917 return ARM_FT_UNKNOWN
;
920 /* Computes the type of the current function. */
923 arm_compute_func_type (void)
925 unsigned long type
= ARM_FT_UNKNOWN
;
929 if (TREE_CODE (current_function_decl
) != FUNCTION_DECL
)
932 /* Decide if the current function is volatile. Such functions
933 never return, and many memory cycles can be saved by not storing
934 register values that will never be needed again. This optimization
935 was added to speed up context switching in a kernel application. */
937 && current_function_nothrow
938 && TREE_THIS_VOLATILE (current_function_decl
))
939 type
|= ARM_FT_VOLATILE
;
941 if (current_function_needs_context
)
942 type
|= ARM_FT_NESTED
;
944 attr
= DECL_ATTRIBUTES (current_function_decl
);
946 a
= lookup_attribute ("naked", attr
);
948 type
|= ARM_FT_NAKED
;
950 if (cfun
->machine
->eh_epilogue_sp_ofs
!= NULL_RTX
)
951 type
|= ARM_FT_EXCEPTION_HANDLER
;
954 a
= lookup_attribute ("isr", attr
);
956 a
= lookup_attribute ("interrupt", attr
);
959 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
961 type
|= arm_isr_value (TREE_VALUE (a
));
967 /* Returns the type of the current function. */
970 arm_current_func_type (void)
972 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
973 cfun
->machine
->func_type
= arm_compute_func_type ();
975 return cfun
->machine
->func_type
;
978 /* Return 1 if it is possible to return using a single instruction. */
981 use_return_insn (int iscond
)
984 unsigned int func_type
;
985 unsigned long saved_int_regs
;
987 /* Never use a return instruction before reload has run. */
988 if (!reload_completed
)
991 func_type
= arm_current_func_type ();
993 /* Naked functions and volatile functions need special
995 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
))
998 /* So do interrupt functions that use the frame pointer. */
999 if (IS_INTERRUPT (func_type
) && frame_pointer_needed
)
1002 /* As do variadic functions. */
1003 if (current_function_pretend_args_size
1004 || cfun
->machine
->uses_anonymous_args
1005 /* Of if the function calls __builtin_eh_return () */
1006 || ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
1007 /* Or if there is no frame pointer and there is a stack adjustment. */
1008 || ((arm_get_frame_size () + current_function_outgoing_args_size
!= 0)
1009 && !frame_pointer_needed
))
1012 saved_int_regs
= arm_compute_save_reg_mask ();
1014 /* Can't be done if interworking with Thumb, and any registers have been
1016 if (TARGET_INTERWORK
&& saved_int_regs
!= 0)
1019 /* On StrongARM, conditional returns are expensive if they aren't
1020 taken and multiple registers have been stacked. */
1021 if (iscond
&& arm_is_strong
)
1023 /* Conditional return when just the LR is stored is a simple
1024 conditional-load instruction, that's not expensive. */
1025 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
1028 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
1032 /* If there are saved registers but the LR isn't saved, then we need
1033 two instructions for the return. */
1034 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
1037 /* Can't be done if any of the FPA regs are pushed,
1038 since this also requires an insn. */
1039 if (TARGET_HARD_FLOAT
)
1040 for (regno
= FIRST_ARM_FP_REGNUM
; regno
<= LAST_ARM_FP_REGNUM
; regno
++)
1041 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1044 if (TARGET_REALLY_IWMMXT
)
1045 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
1046 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1052 /* Return TRUE if int I is a valid immediate ARM constant. */
1055 const_ok_for_arm (HOST_WIDE_INT i
)
1057 unsigned HOST_WIDE_INT mask
= ~(unsigned HOST_WIDE_INT
)0xFF;
1059 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1060 be all zero, or all one. */
1061 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
1062 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
1063 != ((~(unsigned HOST_WIDE_INT
) 0)
1064 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
1067 /* Fast return for 0 and powers of 2 */
1068 if ((i
& (i
- 1)) == 0)
1073 if ((i
& mask
& (unsigned HOST_WIDE_INT
) 0xffffffff) == 0)
1076 (mask
<< 2) | ((mask
& (unsigned HOST_WIDE_INT
) 0xffffffff)
1077 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT
) 0xffffffff;
1079 while (mask
!= ~(unsigned HOST_WIDE_INT
) 0xFF);
1084 /* Return true if I is a valid constant for the operation CODE. */
1086 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
1088 if (const_ok_for_arm (i
))
1094 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1096 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1102 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1109 /* Emit a sequence of insns to handle a large constant.
1110 CODE is the code of the operation required, it can be any of SET, PLUS,
1111 IOR, AND, XOR, MINUS;
1112 MODE is the mode in which the operation is being performed;
1113 VAL is the integer to operate on;
1114 SOURCE is the other operand (a register, or a null-pointer for SET);
1115 SUBTARGETS means it is safe to create scratch registers if that will
1116 either produce a simpler sequence, or we will want to cse the values.
1117 Return value is the number of insns emitted. */
1120 arm_split_constant (enum rtx_code code
, enum machine_mode mode
,
1121 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
1123 if (subtargets
|| code
== SET
1124 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1125 && REGNO (target
) != REGNO (source
)))
1127 /* After arm_reorg has been called, we can't fix up expensive
1128 constants by pushing them into memory so we must synthesize
1129 them in-line, regardless of the cost. This is only likely to
1130 be more costly on chips that have load delay slots and we are
1131 compiling without running the scheduler (so no splitting
1132 occurred before the final instruction emission).
1134 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1136 if (!after_arm_reorg
1137 && (arm_gen_constant (code
, mode
, val
, target
, source
, 1, 0)
1138 > arm_constant_limit
+ (code
!= SET
)))
1142 /* Currently SET is the only monadic value for CODE, all
1143 the rest are diadic. */
1144 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (val
)));
1149 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1151 emit_insn (gen_rtx_SET (VOIDmode
, temp
, GEN_INT (val
)));
1152 /* For MINUS, the value is subtracted from, since we never
1153 have subtraction of a constant. */
1155 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1156 gen_rtx_MINUS (mode
, temp
, source
)));
1158 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1159 gen_rtx (code
, mode
, source
, temp
)));
1165 return arm_gen_constant (code
, mode
, val
, target
, source
, subtargets
, 1);
1169 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
1171 HOST_WIDE_INT temp1
;
1179 if (remainder
& (3 << (i
- 2)))
1184 temp1
= remainder
& ((0x0ff << end
)
1185 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1186 remainder
&= ~temp1
;
1191 } while (remainder
);
1195 /* As above, but extra parameter GENERATE which, if clear, suppresses
1199 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
,
1200 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
1205 int can_negate_initial
= 0;
1208 int num_bits_set
= 0;
1209 int set_sign_bit_copies
= 0;
1210 int clear_sign_bit_copies
= 0;
1211 int clear_zero_bit_copies
= 0;
1212 int set_zero_bit_copies
= 0;
1214 unsigned HOST_WIDE_INT temp1
, temp2
;
1215 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1217 /* Find out which operations are safe for a given CODE. Also do a quick
1218 check for degenerate cases; these can occur when DImode operations
1230 can_negate_initial
= 1;
1234 if (remainder
== 0xffffffff)
1237 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1238 GEN_INT (ARM_SIGN_EXTEND (val
))));
1243 if (reload_completed
&& rtx_equal_p (target
, source
))
1246 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1255 emit_insn (gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1258 if (remainder
== 0xffffffff)
1260 if (reload_completed
&& rtx_equal_p (target
, source
))
1263 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1272 if (reload_completed
&& rtx_equal_p (target
, source
))
1275 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1278 if (remainder
== 0xffffffff)
1281 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1282 gen_rtx_NOT (mode
, source
)));
1286 /* We don't know how to handle this yet below. */
1290 /* We treat MINUS as (val - source), since (source - val) is always
1291 passed as (source + (-val)). */
1295 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1296 gen_rtx_NEG (mode
, source
)));
1299 if (const_ok_for_arm (val
))
1302 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1303 gen_rtx_MINUS (mode
, GEN_INT (val
),
1315 /* If we can do it in one insn get out quickly. */
1316 if (const_ok_for_arm (val
)
1317 || (can_negate_initial
&& const_ok_for_arm (-val
))
1318 || (can_invert
&& const_ok_for_arm (~val
)))
1321 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1322 (source
? gen_rtx (code
, mode
, source
,
1328 /* Calculate a few attributes that may be useful for specific
1330 for (i
= 31; i
>= 0; i
--)
1332 if ((remainder
& (1 << i
)) == 0)
1333 clear_sign_bit_copies
++;
1338 for (i
= 31; i
>= 0; i
--)
1340 if ((remainder
& (1 << i
)) != 0)
1341 set_sign_bit_copies
++;
1346 for (i
= 0; i
<= 31; i
++)
1348 if ((remainder
& (1 << i
)) == 0)
1349 clear_zero_bit_copies
++;
1354 for (i
= 0; i
<= 31; i
++)
1356 if ((remainder
& (1 << i
)) != 0)
1357 set_zero_bit_copies
++;
1365 /* See if we can do this by sign_extending a constant that is known
1366 to be negative. This is a good, way of doing it, since the shift
1367 may well merge into a subsequent insn. */
1368 if (set_sign_bit_copies
> 1)
1370 if (const_ok_for_arm
1371 (temp1
= ARM_SIGN_EXTEND (remainder
1372 << (set_sign_bit_copies
- 1))))
1376 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1377 emit_insn (gen_rtx_SET (VOIDmode
, new_src
,
1379 emit_insn (gen_ashrsi3 (target
, new_src
,
1380 GEN_INT (set_sign_bit_copies
- 1)));
1384 /* For an inverted constant, we will need to set the low bits,
1385 these will be shifted out of harm's way. */
1386 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1387 if (const_ok_for_arm (~temp1
))
1391 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1392 emit_insn (gen_rtx_SET (VOIDmode
, new_src
,
1394 emit_insn (gen_ashrsi3 (target
, new_src
,
1395 GEN_INT (set_sign_bit_copies
- 1)));
1401 /* See if we can generate this by setting the bottom (or the top)
1402 16 bits, and then shifting these into the other half of the
1403 word. We only look for the simplest cases, to do more would cost
1404 too much. Be careful, however, not to generate this when the
1405 alternative would take fewer insns. */
1406 if (val
& 0xffff0000)
1408 temp1
= remainder
& 0xffff0000;
1409 temp2
= remainder
& 0x0000ffff;
1411 /* Overlaps outside this range are best done using other methods. */
1412 for (i
= 9; i
< 24; i
++)
1414 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
1415 && !const_ok_for_arm (temp2
))
1417 rtx new_src
= (subtargets
1418 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1420 insns
= arm_gen_constant (code
, mode
, temp2
, new_src
,
1421 source
, subtargets
, generate
);
1424 emit_insn (gen_rtx_SET
1427 gen_rtx_ASHIFT (mode
, source
,
1434 /* Don't duplicate cases already considered. */
1435 for (i
= 17; i
< 24; i
++)
1437 if (((temp1
| (temp1
>> i
)) == remainder
)
1438 && !const_ok_for_arm (temp1
))
1440 rtx new_src
= (subtargets
1441 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1443 insns
= arm_gen_constant (code
, mode
, temp1
, new_src
,
1444 source
, subtargets
, generate
);
1448 (gen_rtx_SET (VOIDmode
, target
,
1451 gen_rtx_LSHIFTRT (mode
, source
,
1462 /* If we have IOR or XOR, and the constant can be loaded in a
1463 single instruction, and we can find a temporary to put it in,
1464 then this can be done in two instructions instead of 3-4. */
1466 /* TARGET can't be NULL if SUBTARGETS is 0 */
1467 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
1469 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
1473 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1475 emit_insn (gen_rtx_SET (VOIDmode
, sub
, GEN_INT (val
)));
1476 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1477 gen_rtx (code
, mode
, source
, sub
)));
1486 if (set_sign_bit_copies
> 8
1487 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
1491 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1492 rtx shift
= GEN_INT (set_sign_bit_copies
);
1494 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1496 gen_rtx_ASHIFT (mode
,
1499 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1501 gen_rtx_LSHIFTRT (mode
, sub
,
1507 if (set_zero_bit_copies
> 8
1508 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
1512 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1513 rtx shift
= GEN_INT (set_zero_bit_copies
);
1515 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1517 gen_rtx_LSHIFTRT (mode
,
1520 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1522 gen_rtx_ASHIFT (mode
, sub
,
1528 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
1532 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1533 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1534 gen_rtx_NOT (mode
, source
)));
1537 sub
= gen_reg_rtx (mode
);
1538 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1539 gen_rtx_AND (mode
, source
,
1541 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1542 gen_rtx_NOT (mode
, sub
)));
1549 /* See if two shifts will do 2 or more insn's worth of work. */
1550 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
1552 HOST_WIDE_INT shift_mask
= ((0xffffffff
1553 << (32 - clear_sign_bit_copies
))
1556 if ((remainder
| shift_mask
) != 0xffffffff)
1560 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1561 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1562 new_src
, source
, subtargets
, 1);
1567 rtx targ
= subtargets
? NULL_RTX
: target
;
1568 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1569 targ
, source
, subtargets
, 0);
1575 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1576 rtx shift
= GEN_INT (clear_sign_bit_copies
);
1578 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
1579 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
1585 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
1587 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
1589 if ((remainder
| shift_mask
) != 0xffffffff)
1593 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1595 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1596 new_src
, source
, subtargets
, 1);
1601 rtx targ
= subtargets
? NULL_RTX
: target
;
1603 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1604 targ
, source
, subtargets
, 0);
1610 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1611 rtx shift
= GEN_INT (clear_zero_bit_copies
);
1613 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
1614 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
1626 for (i
= 0; i
< 32; i
++)
1627 if (remainder
& (1 << i
))
1630 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
1631 remainder
= (~remainder
) & 0xffffffff;
1632 else if (code
== PLUS
&& num_bits_set
> 16)
1633 remainder
= (-remainder
) & 0xffffffff;
1640 /* Now try and find a way of doing the job in either two or three
1642 We start by looking for the largest block of zeros that are aligned on
1643 a 2-bit boundary, we then fill up the temps, wrapping around to the
1644 top of the word when we drop off the bottom.
1645 In the worst case this code should produce no more than four insns. */
1648 int best_consecutive_zeros
= 0;
1650 for (i
= 0; i
< 32; i
+= 2)
1652 int consecutive_zeros
= 0;
1654 if (!(remainder
& (3 << i
)))
1656 while ((i
< 32) && !(remainder
& (3 << i
)))
1658 consecutive_zeros
+= 2;
1661 if (consecutive_zeros
> best_consecutive_zeros
)
1663 best_consecutive_zeros
= consecutive_zeros
;
1664 best_start
= i
- consecutive_zeros
;
1670 /* So long as it won't require any more insns to do so, it's
1671 desirable to emit a small constant (in bits 0...9) in the last
1672 insn. This way there is more chance that it can be combined with
1673 a later addressing insn to form a pre-indexed load or store
1674 operation. Consider:
1676 *((volatile int *)0xe0000100) = 1;
1677 *((volatile int *)0xe0000110) = 2;
1679 We want this to wind up as:
1683 str rB, [rA, #0x100]
1685 str rB, [rA, #0x110]
1687 rather than having to synthesize both large constants from scratch.
1689 Therefore, we calculate how many insns would be required to emit
1690 the constant starting from `best_start', and also starting from
1691 zero (ie with bit 31 first to be output). If `best_start' doesn't
1692 yield a shorter sequence, we may as well use zero. */
1694 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
1695 && (count_insns_for_constant (remainder
, 0) <=
1696 count_insns_for_constant (remainder
, best_start
)))
1699 /* Now start emitting the insns. */
1707 if (remainder
& (3 << (i
- 2)))
1712 temp1
= remainder
& ((0x0ff << end
)
1713 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1714 remainder
&= ~temp1
;
1718 rtx new_src
, temp1_rtx
;
1720 if (code
== SET
|| code
== MINUS
)
1722 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
1723 if (can_invert
&& code
!= MINUS
)
1728 if (remainder
&& subtargets
)
1729 new_src
= gen_reg_rtx (mode
);
1734 else if (can_negate
)
1738 temp1
= trunc_int_for_mode (temp1
, mode
);
1739 temp1_rtx
= GEN_INT (temp1
);
1743 else if (code
== MINUS
)
1744 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
1746 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
1748 emit_insn (gen_rtx_SET (VOIDmode
, new_src
, temp1_rtx
));
1757 else if (code
== MINUS
)
1771 /* Canonicalize a comparison so that we are more likely to recognize it.
1772 This can be done for a few constant compares, where we can make the
1773 immediate value easier to load. */
1776 arm_canonicalize_comparison (enum rtx_code code
, rtx
* op1
)
1778 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
1788 if (i
!= ((((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1)) - 1)
1789 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
1791 *op1
= GEN_INT (i
+ 1);
1792 return code
== GT
? GE
: LT
;
1798 if (i
!= (((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1))
1799 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
1801 *op1
= GEN_INT (i
- 1);
1802 return code
== GE
? GT
: LE
;
1808 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
1809 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
1811 *op1
= GEN_INT (i
+ 1);
1812 return code
== GTU
? GEU
: LTU
;
1819 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
1821 *op1
= GEN_INT (i
- 1);
1822 return code
== GEU
? GTU
: LEU
;
1833 /* Decide whether a type should be returned in memory (true)
1834 or in a register (false). This is called by the macro
1835 RETURN_IN_MEMORY. */
1837 arm_return_in_memory (tree type
)
1841 if (!AGGREGATE_TYPE_P (type
))
1842 /* All simple types are returned in registers. */
1845 size
= int_size_in_bytes (type
);
1849 /* ATPCS returns aggregate types in memory only if they are
1850 larger than a word (or are variable size). */
1851 return (size
< 0 || size
> UNITS_PER_WORD
);
1854 /* For the arm-wince targets we choose to be compatible with Microsoft's
1855 ARM and Thumb compilers, which always return aggregates in memory. */
1857 /* All structures/unions bigger than one word are returned in memory.
1858 Also catch the case where int_size_in_bytes returns -1. In this case
1859 the aggregate is either huge or of variable size, and in either case
1860 we will want to return it via memory and not in a register. */
1861 if (size
< 0 || size
> UNITS_PER_WORD
)
1864 if (TREE_CODE (type
) == RECORD_TYPE
)
1868 /* For a struct the APCS says that we only return in a register
1869 if the type is 'integer like' and every addressable element
1870 has an offset of zero. For practical purposes this means
1871 that the structure can have at most one non bit-field element
1872 and that this element must be the first one in the structure. */
1874 /* Find the first field, ignoring non FIELD_DECL things which will
1875 have been created by C++. */
1876 for (field
= TYPE_FIELDS (type
);
1877 field
&& TREE_CODE (field
) != FIELD_DECL
;
1878 field
= TREE_CHAIN (field
))
1882 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1884 /* Check that the first field is valid for returning in a register. */
1886 /* ... Floats are not allowed */
1887 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
1890 /* ... Aggregates that are not themselves valid for returning in
1891 a register are not allowed. */
1892 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
1895 /* Now check the remaining fields, if any. Only bitfields are allowed,
1896 since they are not addressable. */
1897 for (field
= TREE_CHAIN (field
);
1899 field
= TREE_CHAIN (field
))
1901 if (TREE_CODE (field
) != FIELD_DECL
)
1904 if (!DECL_BIT_FIELD_TYPE (field
))
1911 if (TREE_CODE (type
) == UNION_TYPE
)
1915 /* Unions can be returned in registers if every element is
1916 integral, or can be returned in an integer register. */
1917 for (field
= TYPE_FIELDS (type
);
1919 field
= TREE_CHAIN (field
))
1921 if (TREE_CODE (field
) != FIELD_DECL
)
1924 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
1927 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
1933 #endif /* not ARM_WINCE */
1935 /* Return all other types in memory. */
1939 /* Indicate whether or not words of a double are in big-endian order. */
1942 arm_float_words_big_endian (void)
1947 /* For FPA, float words are always big-endian. For VFP, floats words
1948 follow the memory system mode. */
1950 if (TARGET_HARD_FLOAT
)
1952 /* FIXME: TARGET_HARD_FLOAT currently implies FPA. */
1957 return (TARGET_BIG_END
? 1 : 0);
1962 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1963 for a call to a function whose data type is FNTYPE.
1964 For a library call, FNTYPE is NULL. */
1966 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
1967 rtx libname ATTRIBUTE_UNUSED
,
1968 tree fndecl ATTRIBUTE_UNUSED
)
1970 /* On the ARM, the offset starts at 0. */
1971 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
), fntype
)) ? 1 : 0);
1972 pcum
->iwmmxt_nregs
= 0;
1974 pcum
->call_cookie
= CALL_NORMAL
;
1976 if (TARGET_LONG_CALLS
)
1977 pcum
->call_cookie
= CALL_LONG
;
1979 /* Check for long call/short call attributes. The attributes
1980 override any command line option. */
1983 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
1984 pcum
->call_cookie
= CALL_SHORT
;
1985 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
1986 pcum
->call_cookie
= CALL_LONG
;
1989 /* Varargs vectors are treated the same as long long.
1990 named_count avoids having to change the way arm handles 'named' */
1991 pcum
->named_count
= 0;
1994 if (TARGET_REALLY_IWMMXT
&& fntype
)
1998 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
2000 fn_arg
= TREE_CHAIN (fn_arg
))
2001 pcum
->named_count
+= 1;
2003 if (! pcum
->named_count
)
2004 pcum
->named_count
= INT_MAX
;
2008 /* Determine where to put an argument to a function.
2009 Value is zero to push the argument on the stack,
2010 or a hard register in which to store the argument.
2012 MODE is the argument's machine mode.
2013 TYPE is the data type of the argument (as a tree).
2014 This is null for libcalls where that information may
2016 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2017 the preceding args and about the function being called.
2018 NAMED is nonzero if this argument is a named parameter
2019 (otherwise it is an extra parameter matching an ellipsis). */
2022 arm_function_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2023 tree type ATTRIBUTE_UNUSED
, int named
)
2025 if (TARGET_REALLY_IWMMXT
)
2027 if (VECTOR_MODE_SUPPORTED_P (mode
))
2029 /* varargs vectors are treated the same as long long.
2030 named_count avoids having to change the way arm handles 'named' */
2031 if (pcum
->named_count
<= pcum
->nargs
+ 1)
2033 if (pcum
->nregs
== 1)
2035 if (pcum
->nregs
<= 2)
2036 return gen_rtx_REG (mode
, pcum
->nregs
);
2040 else if (pcum
->iwmmxt_nregs
<= 9)
2041 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
2045 else if ((mode
== DImode
|| mode
== DFmode
) && pcum
->nregs
& 1)
2049 if (mode
== VOIDmode
)
2050 /* Compute operand 2 of the call insn. */
2051 return GEN_INT (pcum
->call_cookie
);
2053 if (!named
|| pcum
->nregs
>= NUM_ARG_REGS
)
2056 return gen_rtx_REG (mode
, pcum
->nregs
);
2059 /* Variable sized types are passed by reference. This is a GCC
2060 extension to the ARM ABI. */
2063 arm_function_arg_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
2064 enum machine_mode mode ATTRIBUTE_UNUSED
,
2065 tree type
, int named ATTRIBUTE_UNUSED
)
2067 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
2070 /* Implement va_arg. */
2073 arm_va_arg (tree valist
, tree type
)
2075 /* Variable sized types are passed by reference. */
2076 if (TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
2078 rtx addr
= std_expand_builtin_va_arg (valist
, build_pointer_type (type
));
2079 return gen_rtx_MEM (ptr_mode
, force_reg (Pmode
, addr
));
2082 if (FUNCTION_ARG_BOUNDARY (TYPE_MODE (type
), NULL
) == IWMMXT_ALIGNMENT
)
2087 /* Maintain 64-bit alignment of the valist pointer by
2088 constructing: valist = ((valist + (8 - 1)) & -8). */
2089 minus_eight
= build_int_2 (- (IWMMXT_ALIGNMENT
/ BITS_PER_UNIT
), -1);
2090 t
= build_int_2 ((IWMMXT_ALIGNMENT
/ BITS_PER_UNIT
) - 1, 0);
2091 t
= build (PLUS_EXPR
, TREE_TYPE (valist
), valist
, t
);
2092 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
, minus_eight
);
2093 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
2094 TREE_SIDE_EFFECTS (t
) = 1;
2095 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2097 /* This is to stop the combine pass optimizing
2098 away the alignment adjustment. */
2099 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
2102 return std_expand_builtin_va_arg (valist
, type
);
2105 /* Encode the current state of the #pragma [no_]long_calls. */
2108 OFF
, /* No #pramgma [no_]long_calls is in effect. */
2109 LONG
, /* #pragma long_calls is in effect. */
2110 SHORT
/* #pragma no_long_calls is in effect. */
2113 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
2116 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2118 arm_pragma_long_calls
= LONG
;
2122 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2124 arm_pragma_long_calls
= SHORT
;
2128 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2130 arm_pragma_long_calls
= OFF
;
2133 /* Table of machine attributes. */
2134 const struct attribute_spec arm_attribute_table
[] =
2136 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2137 /* Function calls made to this symbol must be done indirectly, because
2138 it may lie outside of the 26 bit addressing range of a normal function
2140 { "long_call", 0, 0, false, true, true, NULL
},
2141 /* Whereas these functions are always known to reside within the 26 bit
2142 addressing range. */
2143 { "short_call", 0, 0, false, true, true, NULL
},
2144 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2145 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
2146 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
2147 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2149 /* ARM/PE has three new attributes:
2151 dllexport - for exporting a function/variable that will live in a dll
2152 dllimport - for importing a function/variable from a dll
2154 Microsoft allows multiple declspecs in one __declspec, separating
2155 them with spaces. We do NOT support this. Instead, use __declspec
2158 { "dllimport", 0, 0, true, false, false, NULL
},
2159 { "dllexport", 0, 0, true, false, false, NULL
},
2160 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2162 { NULL
, 0, 0, false, false, false, NULL
}
2165 /* Handle an attribute requiring a FUNCTION_DECL;
2166 arguments as in struct attribute_spec.handler. */
2168 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
2169 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2171 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2173 warning ("`%s' attribute only applies to functions",
2174 IDENTIFIER_POINTER (name
));
2175 *no_add_attrs
= true;
2181 /* Handle an "interrupt" or "isr" attribute;
2182 arguments as in struct attribute_spec.handler. */
2184 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
2189 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2191 warning ("`%s' attribute only applies to functions",
2192 IDENTIFIER_POINTER (name
));
2193 *no_add_attrs
= true;
2195 /* FIXME: the argument if any is checked for type attributes;
2196 should it be checked for decl ones? */
2200 if (TREE_CODE (*node
) == FUNCTION_TYPE
2201 || TREE_CODE (*node
) == METHOD_TYPE
)
2203 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
2205 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2206 *no_add_attrs
= true;
2209 else if (TREE_CODE (*node
) == POINTER_TYPE
2210 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
2211 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
2212 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
2214 *node
= build_type_copy (*node
);
2215 TREE_TYPE (*node
) = build_type_attribute_variant
2217 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
2218 *no_add_attrs
= true;
2222 /* Possibly pass this attribute on from the type to a decl. */
2223 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2224 | (int) ATTR_FLAG_FUNCTION_NEXT
2225 | (int) ATTR_FLAG_ARRAY_NEXT
))
2227 *no_add_attrs
= true;
2228 return tree_cons (name
, args
, NULL_TREE
);
2232 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2240 /* Return 0 if the attributes for two types are incompatible, 1 if they
2241 are compatible, and 2 if they are nearly compatible (which causes a
2242 warning to be generated). */
2244 arm_comp_type_attributes (tree type1
, tree type2
)
2248 /* Check for mismatch of non-default calling convention. */
2249 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2252 /* Check for mismatched call attributes. */
2253 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2254 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2255 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2256 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2258 /* Only bother to check if an attribute is defined. */
2259 if (l1
| l2
| s1
| s2
)
2261 /* If one type has an attribute, the other must have the same attribute. */
2262 if ((l1
!= l2
) || (s1
!= s2
))
2265 /* Disallow mixed attributes. */
2266 if ((l1
& s2
) || (l2
& s1
))
2270 /* Check for mismatched ISR attribute. */
2271 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
2273 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
2274 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
2276 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
2283 /* Encode long_call or short_call attribute by prefixing
2284 symbol name in DECL with a special character FLAG. */
2286 arm_encode_call_attribute (tree decl
, int flag
)
2288 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2289 int len
= strlen (str
);
2292 /* Do not allow weak functions to be treated as short call. */
2293 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
2296 newstr
= alloca (len
+ 2);
2298 strcpy (newstr
+ 1, str
);
2300 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
2301 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
2304 /* Assigns default attributes to newly defined type. This is used to
2305 set short_call/long_call attributes for function types of
2306 functions defined inside corresponding #pragma scopes. */
2308 arm_set_default_type_attributes (tree type
)
2310 /* Add __attribute__ ((long_call)) to all functions, when
2311 inside #pragma long_calls or __attribute__ ((short_call)),
2312 when inside #pragma no_long_calls. */
2313 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
2315 tree type_attr_list
, attr_name
;
2316 type_attr_list
= TYPE_ATTRIBUTES (type
);
2318 if (arm_pragma_long_calls
== LONG
)
2319 attr_name
= get_identifier ("long_call");
2320 else if (arm_pragma_long_calls
== SHORT
)
2321 attr_name
= get_identifier ("short_call");
2325 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
2326 TYPE_ATTRIBUTES (type
) = type_attr_list
;
2330 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2331 defined within the current compilation unit. If this cannot be
2332 determined, then 0 is returned. */
2334 current_file_function_operand (rtx sym_ref
)
2336 /* This is a bit of a fib. A function will have a short call flag
2337 applied to its name if it has the short call attribute, or it has
2338 already been defined within the current compilation unit. */
2339 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
2342 /* The current function is always defined within the current compilation
2343 unit. if it s a weak definition however, then this may not be the real
2344 definition of the function, and so we have to say no. */
2345 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
2346 && !DECL_WEAK (current_function_decl
))
2349 /* We cannot make the determination - default to returning 0. */
2353 /* Return nonzero if a 32 bit "long_call" should be generated for
2354 this call. We generate a long_call if the function:
2356 a. has an __attribute__((long call))
2357 or b. is within the scope of a #pragma long_calls
2358 or c. the -mlong-calls command line switch has been specified
2360 However we do not generate a long call if the function:
2362 d. has an __attribute__ ((short_call))
2363 or e. is inside the scope of a #pragma no_long_calls
2364 or f. has an __attribute__ ((section))
2365 or g. is defined within the current compilation unit.
2367 This function will be called by C fragments contained in the machine
2368 description file. CALL_REF and CALL_COOKIE correspond to the matched
2369 rtl operands. CALL_SYMBOL is used to distinguish between
2370 two different callers of the function. It is set to 1 in the
2371 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2372 and "call_value" patterns. This is because of the difference in the
2373 SYM_REFs passed by these patterns. */
2375 arm_is_longcall_p (rtx sym_ref
, int call_cookie
, int call_symbol
)
2379 if (GET_CODE (sym_ref
) != MEM
)
2382 sym_ref
= XEXP (sym_ref
, 0);
2385 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
2388 if (call_cookie
& CALL_SHORT
)
2391 if (TARGET_LONG_CALLS
&& flag_function_sections
)
2394 if (current_file_function_operand (sym_ref
))
2397 return (call_cookie
& CALL_LONG
)
2398 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
2399 || TARGET_LONG_CALLS
;
2402 /* Return nonzero if it is ok to make a tail-call to DECL. */
2404 arm_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
2406 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
2408 if (cfun
->machine
->sibcall_blocked
)
2411 /* Never tailcall something for which we have no decl, or if we
2412 are in Thumb mode. */
2413 if (decl
== NULL
|| TARGET_THUMB
)
2416 /* Get the calling method. */
2417 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2418 call_type
= CALL_SHORT
;
2419 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2420 call_type
= CALL_LONG
;
2422 /* Cannot tail-call to long calls, since these are out of range of
2423 a branch instruction. However, if not compiling PIC, we know
2424 we can reach the symbol if it is in this compilation unit. */
2425 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
2428 /* If we are interworking and the function is not declared static
2429 then we can't tail-call it unless we know that it exists in this
2430 compilation unit (since it might be a Thumb routine). */
2431 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
2434 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2435 if (IS_INTERRUPT (arm_current_func_type ()))
2438 /* Everything else is ok. */
2443 /* Addressing mode support functions. */
2445 /* Return nonzero if X is a legitimate immediate operand when compiling
2448 legitimate_pic_operand_p (rtx x
)
2452 && (GET_CODE (x
) == SYMBOL_REF
2453 || (GET_CODE (x
) == CONST
2454 && GET_CODE (XEXP (x
, 0)) == PLUS
2455 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)))
2462 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
2464 if (GET_CODE (orig
) == SYMBOL_REF
2465 || GET_CODE (orig
) == LABEL_REF
)
2467 #ifndef AOF_ASSEMBLER
2468 rtx pic_ref
, address
;
2478 reg
= gen_reg_rtx (Pmode
);
2483 #ifdef AOF_ASSEMBLER
2484 /* The AOF assembler can generate relocations for these directly, and
2485 understands that the PIC register has to be added into the offset. */
2486 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
2489 address
= gen_reg_rtx (Pmode
);
2494 emit_insn (gen_pic_load_addr_arm (address
, orig
));
2496 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
2498 if ((GET_CODE (orig
) == LABEL_REF
2499 || (GET_CODE (orig
) == SYMBOL_REF
&&
2500 SYMBOL_REF_LOCAL_P (orig
)))
2502 pic_ref
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, address
);
2505 pic_ref
= gen_rtx_MEM (Pmode
,
2506 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
2508 RTX_UNCHANGING_P (pic_ref
) = 1;
2511 insn
= emit_move_insn (reg
, pic_ref
);
2513 current_function_uses_pic_offset_table
= 1;
2514 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2516 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
2520 else if (GET_CODE (orig
) == CONST
)
2524 if (GET_CODE (XEXP (orig
, 0)) == PLUS
2525 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
2533 reg
= gen_reg_rtx (Pmode
);
2536 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
2538 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2539 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2540 base
== reg
? 0 : reg
);
2545 if (GET_CODE (offset
) == CONST_INT
)
2547 /* The base register doesn't really matter, we only want to
2548 test the index for the appropriate mode. */
2549 if (!arm_legitimate_index_p (mode
, offset
, 0))
2551 if (!no_new_pseudos
)
2552 offset
= force_reg (Pmode
, offset
);
2557 if (GET_CODE (offset
) == CONST_INT
)
2558 return plus_constant (base
, INTVAL (offset
));
2561 if (GET_MODE_SIZE (mode
) > 4
2562 && (GET_MODE_CLASS (mode
) == MODE_INT
2563 || TARGET_SOFT_FLOAT
))
2565 emit_insn (gen_addsi3 (reg
, base
, offset
));
2569 return gen_rtx_PLUS (Pmode
, base
, offset
);
2575 /* Generate code to load the PIC register. PROLOGUE is true if
2576 called from arm_expand_prologue (in which case we want the
2577 generated insns at the start of the function); false if called
2578 by an exception receiver that needs the PIC register reloaded
2579 (in which case the insns are just dumped at the current location). */
2581 arm_finalize_pic (int prologue ATTRIBUTE_UNUSED
)
2583 #ifndef AOF_ASSEMBLER
2584 rtx l1
, pic_tmp
, pic_tmp2
, seq
, pic_rtx
;
2585 rtx global_offset_table
;
2587 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
2594 l1
= gen_label_rtx ();
2596 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
2597 /* On the ARM the PC register contains 'dot + 8' at the time of the
2598 addition, on the Thumb it is 'dot + 4'. */
2599 pic_tmp
= plus_constant (gen_rtx_LABEL_REF (Pmode
, l1
), TARGET_ARM
? 8 : 4);
2601 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
2602 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
2604 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
2606 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
2610 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx
, pic_rtx
));
2611 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx
, l1
));
2615 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx
, pic_rtx
));
2616 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx
, l1
));
2622 emit_insn_after (seq
, get_insns ());
2626 /* Need to emit this whether or not we obey regdecls,
2627 since setjmp/longjmp can cause life info to screw up. */
2628 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
2629 #endif /* AOF_ASSEMBLER */
2632 /* Return nonzero if X is valid as an ARM state addressing register. */
2634 arm_address_register_rtx_p (rtx x
, int strict_p
)
2638 if (GET_CODE (x
) != REG
)
2644 return ARM_REGNO_OK_FOR_BASE_P (regno
);
2646 return (regno
<= LAST_ARM_REGNUM
2647 || regno
>= FIRST_PSEUDO_REGISTER
2648 || regno
== FRAME_POINTER_REGNUM
2649 || regno
== ARG_POINTER_REGNUM
);
2652 /* Return nonzero if X is a valid ARM state address operand. */
2654 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
2656 if (arm_address_register_rtx_p (x
, strict_p
))
2659 else if (GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == PRE_DEC
)
2660 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
2662 else if ((GET_CODE (x
) == POST_MODIFY
|| GET_CODE (x
) == PRE_MODIFY
)
2663 && GET_MODE_SIZE (mode
) <= 4
2664 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
2665 && GET_CODE (XEXP (x
, 1)) == PLUS
2666 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2667 return arm_legitimate_index_p (mode
, XEXP (XEXP (x
, 1), 1), strict_p
);
2669 /* After reload constants split into minipools will have addresses
2670 from a LABEL_REF. */
2671 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
2672 && (GET_CODE (x
) == LABEL_REF
2673 || (GET_CODE (x
) == CONST
2674 && GET_CODE (XEXP (x
, 0)) == PLUS
2675 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
2676 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
2679 else if (mode
== TImode
)
2682 else if (mode
== DImode
|| (TARGET_SOFT_FLOAT
&& mode
== DFmode
))
2684 if (GET_CODE (x
) == PLUS
2685 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
2686 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2688 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
2690 if (val
== 4 || val
== -4 || val
== -8)
2695 else if (GET_CODE (x
) == PLUS
)
2697 rtx xop0
= XEXP (x
, 0);
2698 rtx xop1
= XEXP (x
, 1);
2700 return ((arm_address_register_rtx_p (xop0
, strict_p
)
2701 && arm_legitimate_index_p (mode
, xop1
, strict_p
))
2702 || (arm_address_register_rtx_p (xop1
, strict_p
)
2703 && arm_legitimate_index_p (mode
, xop0
, strict_p
)));
2707 /* Reload currently can't handle MINUS, so disable this for now */
2708 else if (GET_CODE (x
) == MINUS
)
2710 rtx xop0
= XEXP (x
, 0);
2711 rtx xop1
= XEXP (x
, 1);
2713 return (arm_address_register_rtx_p (xop0
, strict_p
)
2714 && arm_legitimate_index_p (mode
, xop1
, strict_p
));
2718 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
2719 && GET_CODE (x
) == SYMBOL_REF
2720 && CONSTANT_POOL_ADDRESS_P (x
)
2722 && symbol_mentioned_p (get_pool_constant (x
))))
2725 else if ((GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == POST_DEC
)
2726 && (GET_MODE_SIZE (mode
) <= 4)
2727 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
))
2733 /* Return nonzero if INDEX is valid for an address index operand in
2736 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, int strict_p
)
2738 HOST_WIDE_INT range
;
2739 enum rtx_code code
= GET_CODE (index
);
2741 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2742 return (code
== CONST_INT
&& INTVAL (index
) < 1024
2743 && INTVAL (index
) > -1024
2744 && (INTVAL (index
) & 3) == 0);
2747 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
|| mode
== DImode
))
2748 return (code
== CONST_INT
2749 && INTVAL (index
) < 255
2750 && INTVAL (index
) > -255);
2752 if (arm_address_register_rtx_p (index
, strict_p
)
2753 && GET_MODE_SIZE (mode
) <= 4)
2756 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
2757 return (code
== CONST_INT
2758 && INTVAL (index
) < 256
2759 && INTVAL (index
) > -256);
2761 /* XXX What about ldrsb? */
2762 if (GET_MODE_SIZE (mode
) <= 4 && code
== MULT
2763 && (!arm_arch4
|| (mode
) != HImode
))
2765 rtx xiop0
= XEXP (index
, 0);
2766 rtx xiop1
= XEXP (index
, 1);
2768 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
2769 && power_of_two_operand (xiop1
, SImode
))
2770 || (arm_address_register_rtx_p (xiop1
, strict_p
)
2771 && power_of_two_operand (xiop0
, SImode
)));
2774 if (GET_MODE_SIZE (mode
) <= 4
2775 && (code
== LSHIFTRT
|| code
== ASHIFTRT
2776 || code
== ASHIFT
|| code
== ROTATERT
)
2777 && (!arm_arch4
|| (mode
) != HImode
))
2779 rtx op
= XEXP (index
, 1);
2781 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
2782 && GET_CODE (op
) == CONST_INT
2784 && INTVAL (op
) <= 31);
2787 /* XXX For ARM v4 we may be doing a sign-extend operation during the
2788 load, but that has a restricted addressing range and we are unable
2789 to tell here whether that is the case. To be safe we restrict all
2790 loads to that range. */
2791 range
= ((mode
) == HImode
|| (mode
) == QImode
)
2792 ? (arm_arch4
? 256 : 4095) : 4096;
2794 return (code
== CONST_INT
2795 && INTVAL (index
) < range
2796 && INTVAL (index
) > -range
);
2799 /* Return nonzero if X is valid as an ARM state addressing register. */
2801 thumb_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
2805 if (GET_CODE (x
) != REG
)
2811 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
2813 return (regno
<= LAST_LO_REGNUM
2814 || regno
>= FIRST_PSEUDO_REGISTER
2815 || regno
== FRAME_POINTER_REGNUM
2816 || (GET_MODE_SIZE (mode
) >= 4
2817 && (regno
== STACK_POINTER_REGNUM
2818 || x
== hard_frame_pointer_rtx
2819 || x
== arg_pointer_rtx
)));
2822 /* Return nonzero if x is a legitimate index register. This is the case
2823 for any base register that can access a QImode object. */
2825 thumb_index_register_rtx_p (rtx x
, int strict_p
)
2827 return thumb_base_register_rtx_p (x
, QImode
, strict_p
);
2830 /* Return nonzero if x is a legitimate Thumb-state address.
2832 The AP may be eliminated to either the SP or the FP, so we use the
2833 least common denominator, e.g. SImode, and offsets from 0 to 64.
2835 ??? Verify whether the above is the right approach.
2837 ??? Also, the FP may be eliminated to the SP, so perhaps that
2838 needs special handling also.
2840 ??? Look at how the mips16 port solves this problem. It probably uses
2841 better ways to solve some of these problems.
2843 Although it is not incorrect, we don't accept QImode and HImode
2844 addresses based on the frame pointer or arg pointer until the
2845 reload pass starts. This is so that eliminating such addresses
2846 into stack based ones won't produce impossible code. */
2848 thumb_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
2850 /* ??? Not clear if this is right. Experiment. */
2851 if (GET_MODE_SIZE (mode
) < 4
2852 && !(reload_in_progress
|| reload_completed
)
2853 && (reg_mentioned_p (frame_pointer_rtx
, x
)
2854 || reg_mentioned_p (arg_pointer_rtx
, x
)
2855 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
2856 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
2857 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
2858 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
2861 /* Accept any base register. SP only in SImode or larger. */
2862 else if (thumb_base_register_rtx_p (x
, mode
, strict_p
))
2865 /* This is PC relative data before arm_reorg runs. */
2866 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
2867 && GET_CODE (x
) == SYMBOL_REF
2868 && CONSTANT_POOL_ADDRESS_P (x
) && ! flag_pic
)
2871 /* This is PC relative data after arm_reorg runs. */
2872 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
2873 && (GET_CODE (x
) == LABEL_REF
2874 || (GET_CODE (x
) == CONST
2875 && GET_CODE (XEXP (x
, 0)) == PLUS
2876 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
2877 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
2880 /* Post-inc indexing only supported for SImode and larger. */
2881 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
2882 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
))
2885 else if (GET_CODE (x
) == PLUS
)
2887 /* REG+REG address can be any two index registers. */
2888 /* We disallow FRAME+REG addressing since we know that FRAME
2889 will be replaced with STACK, and SP relative addressing only
2890 permits SP+OFFSET. */
2891 if (GET_MODE_SIZE (mode
) <= 4
2892 && XEXP (x
, 0) != frame_pointer_rtx
2893 && XEXP (x
, 1) != frame_pointer_rtx
2894 && XEXP (x
, 0) != virtual_stack_vars_rtx
2895 && XEXP (x
, 1) != virtual_stack_vars_rtx
2896 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
2897 && thumb_index_register_rtx_p (XEXP (x
, 1), strict_p
))
2900 /* REG+const has 5-7 bit offset for non-SP registers. */
2901 else if ((thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
2902 || XEXP (x
, 0) == arg_pointer_rtx
)
2903 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2904 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
2907 /* REG+const has 10 bit offset for SP, but only SImode and
2908 larger is supported. */
2909 /* ??? Should probably check for DI/DFmode overflow here
2910 just like GO_IF_LEGITIMATE_OFFSET does. */
2911 else if (GET_CODE (XEXP (x
, 0)) == REG
2912 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
2913 && GET_MODE_SIZE (mode
) >= 4
2914 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2915 && INTVAL (XEXP (x
, 1)) >= 0
2916 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
2917 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
2920 else if (GET_CODE (XEXP (x
, 0)) == REG
2921 && REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
2922 && GET_MODE_SIZE (mode
) >= 4
2923 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2924 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
2928 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
2929 && GET_CODE (x
) == SYMBOL_REF
2930 && CONSTANT_POOL_ADDRESS_P (x
)
2932 && symbol_mentioned_p (get_pool_constant (x
))))
2938 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
2939 instruction of mode MODE. */
2941 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
2943 switch (GET_MODE_SIZE (mode
))
2946 return val
>= 0 && val
< 32;
2949 return val
>= 0 && val
< 64 && (val
& 1) == 0;
2953 && (val
+ GET_MODE_SIZE (mode
)) <= 128
2958 /* Try machine-dependent ways of modifying an illegitimate address
2959 to be legitimate. If we find one, return the new, valid address. */
2961 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
2963 if (GET_CODE (x
) == PLUS
)
2965 rtx xop0
= XEXP (x
, 0);
2966 rtx xop1
= XEXP (x
, 1);
2968 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
2969 xop0
= force_reg (SImode
, xop0
);
2971 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
2972 xop1
= force_reg (SImode
, xop1
);
2974 if (ARM_BASE_REGISTER_RTX_P (xop0
)
2975 && GET_CODE (xop1
) == CONST_INT
)
2977 HOST_WIDE_INT n
, low_n
;
2981 if (mode
== DImode
|| (TARGET_SOFT_FLOAT
&& mode
== DFmode
))
2993 low_n
= ((mode
) == TImode
? 0
2994 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
2998 base_reg
= gen_reg_rtx (SImode
);
2999 val
= force_operand (gen_rtx_PLUS (SImode
, xop0
,
3000 GEN_INT (n
)), NULL_RTX
);
3001 emit_move_insn (base_reg
, val
);
3002 x
= (low_n
== 0 ? base_reg
3003 : gen_rtx_PLUS (SImode
, base_reg
, GEN_INT (low_n
)));
3005 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3006 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
3009 /* XXX We don't allow MINUS any more -- see comment in
3010 arm_legitimate_address_p (). */
3011 else if (GET_CODE (x
) == MINUS
)
3013 rtx xop0
= XEXP (x
, 0);
3014 rtx xop1
= XEXP (x
, 1);
3016 if (CONSTANT_P (xop0
))
3017 xop0
= force_reg (SImode
, xop0
);
3019 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
3020 xop1
= force_reg (SImode
, xop1
);
3022 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3023 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
3028 /* We need to find and carefully transform any SYMBOL and LABEL
3029 references; so go back to the original address expression. */
3030 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
3032 if (new_x
!= orig_x
)
3041 #define REG_OR_SUBREG_REG(X) \
3042 (GET_CODE (X) == REG \
3043 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3045 #define REG_OR_SUBREG_RTX(X) \
3046 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3048 #ifndef COSTS_N_INSNS
3049 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3051 /* Worker routine for arm_rtx_costs. */
3053 arm_rtx_costs_1 (rtx x
, enum rtx_code code
, enum rtx_code outer
)
3055 enum machine_mode mode
= GET_MODE (x
);
3056 enum rtx_code subcode
;
3072 return COSTS_N_INSNS (1);
3075 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3078 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
3085 return COSTS_N_INSNS (2) + cycles
;
3087 return COSTS_N_INSNS (1) + 16;
3090 return (COSTS_N_INSNS (1)
3091 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
3092 + GET_CODE (SET_DEST (x
)) == MEM
));
3097 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
3099 if (thumb_shiftable_const (INTVAL (x
)))
3100 return COSTS_N_INSNS (2);
3101 return COSTS_N_INSNS (3);
3103 else if (outer
== PLUS
3104 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
3106 else if (outer
== COMPARE
3107 && (unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
3109 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
3110 || outer
== LSHIFTRT
)
3112 return COSTS_N_INSNS (2);
3118 return COSTS_N_INSNS (3);
3137 /* XXX another guess. */
3138 /* Memory costs quite a lot for the first word, but subsequent words
3139 load at the equivalent of a single insn each. */
3140 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
3141 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
3146 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
3151 /* XXX still guessing. */
3152 switch (GET_MODE (XEXP (x
, 0)))
3155 return (1 + (mode
== DImode
? 4 : 0)
3156 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3159 return (4 + (mode
== DImode
? 4 : 0)
3160 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3163 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3177 /* Memory costs quite a lot for the first word, but subsequent words
3178 load at the equivalent of a single insn each. */
3179 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
3180 + (GET_CODE (x
) == SYMBOL_REF
3181 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
3188 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
3195 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
3197 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
3198 + ((GET_CODE (XEXP (x
, 0)) == REG
3199 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3200 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
3202 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
3203 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3204 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
3206 + ((GET_CODE (XEXP (x
, 1)) == REG
3207 || (GET_CODE (XEXP (x
, 1)) == SUBREG
3208 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
3209 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
3214 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
3215 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3216 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
3217 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
3220 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3221 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3222 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
3223 && const_double_rtx_ok_for_fpa (XEXP (x
, 1))))
3225 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3226 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
3227 && const_double_rtx_ok_for_fpa (XEXP (x
, 0))))
3230 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
3231 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
3232 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
3233 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
3234 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
3235 || subcode
== ROTATE
|| subcode
== ROTATERT
3237 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
3238 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
3239 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
3240 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
3241 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
3242 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
3243 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
3248 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3249 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
3250 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3251 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
3252 && const_double_rtx_ok_for_fpa (XEXP (x
, 1))))
3256 case AND
: case XOR
: case IOR
:
3259 /* Normally the frame registers will be spilt into reg+const during
3260 reload, so it is a bad idea to combine them with other instructions,
3261 since then they might not be moved outside of loops. As a compromise
3262 we allow integration with ops that have a constant as their second
3264 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3265 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
3266 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3267 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
3268 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
3272 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
3273 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3274 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
3275 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
3278 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
3279 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
3280 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3281 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
3282 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
3285 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
3286 return (1 + extra_cost
3287 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
3288 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
3289 || subcode
== ROTATE
|| subcode
== ROTATERT
3291 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3292 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
3293 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
3294 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
3295 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
3296 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
3302 /* There is no point basing this on the tuning, since it is always the
3303 fast variant if it exists at all. */
3304 if (arm_fast_multiply
&& mode
== DImode
3305 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
3306 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
3307 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
3310 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
3314 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3316 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
3317 & (unsigned HOST_WIDE_INT
) 0xffffffff);
3318 int add_cost
= const_ok_for_arm (i
) ? 4 : 8;
3321 /* Tune as appropriate. */
3322 int booth_unit_size
= ((tune_flags
& FL_FAST_MULT
) ? 8 : 2);
3324 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
3326 i
>>= booth_unit_size
;
3333 return (((tune_flags
& FL_FAST_MULT
) ? 8 : 30)
3334 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
3335 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4));
3338 if (arm_fast_multiply
&& mode
== SImode
3339 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3340 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
3341 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
3342 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
3343 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
3344 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
3349 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3350 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
3354 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
3356 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
3359 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
3367 return 4 + (mode
== DImode
? 4 : 0);
3370 if (GET_MODE (XEXP (x
, 0)) == QImode
)
3371 return (4 + (mode
== DImode
? 4 : 0)
3372 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3375 switch (GET_MODE (XEXP (x
, 0)))
3378 return (1 + (mode
== DImode
? 4 : 0)
3379 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3382 return (4 + (mode
== DImode
? 4 : 0)
3383 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3386 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3401 if (const_ok_for_arm (INTVAL (x
)))
3402 return outer
== SET
? 2 : -1;
3403 else if (outer
== AND
3404 && const_ok_for_arm (~INTVAL (x
)))
3406 else if ((outer
== COMPARE
3407 || outer
== PLUS
|| outer
== MINUS
)
3408 && const_ok_for_arm (-INTVAL (x
)))
3419 if (const_double_rtx_ok_for_fpa (x
))
3420 return outer
== SET
? 2 : -1;
3421 else if ((outer
== COMPARE
|| outer
== PLUS
)
3422 && neg_const_double_rtx_ok_for_fpa (x
))
3432 arm_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
3434 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
3438 /* All address computations that can be done are free, but rtx cost returns
3439 the same for practically all of them. So we weight the different types
3440 of address here in the order (most pref first):
3441 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
3443 arm_address_cost (rtx x
)
3445 #define ARM_ADDRESS_COST(X) \
3446 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
3447 || GET_CODE (X) == SYMBOL_REF) \
3449 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
3450 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
3452 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
3453 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
3454 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
3455 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
3456 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
3457 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
3461 #define THUMB_ADDRESS_COST(X) \
3462 ((GET_CODE (X) == REG \
3463 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
3464 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \
3467 return (TARGET_ARM
? ARM_ADDRESS_COST (x
) : THUMB_ADDRESS_COST (x
));
3471 arm_use_dfa_pipeline_interface (void)
3477 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
3481 /* Some true dependencies can have a higher cost depending
3482 on precisely how certain input operands are used. */
3484 && REG_NOTE_KIND (link
) == 0
3485 && recog_memoized (insn
) >= 0
3486 && recog_memoized (dep
) >= 0)
3488 int shift_opnum
= get_attr_shift (insn
);
3489 enum attr_type attr_type
= get_attr_type (dep
);
3491 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
3492 operand for INSN. If we have a shifted input operand and the
3493 instruction we depend on is another ALU instruction, then we may
3494 have to account for an additional stall. */
3495 if (shift_opnum
!= 0 && attr_type
== TYPE_NORMAL
)
3497 rtx shifted_operand
;
3500 /* Get the shifted operand. */
3501 extract_insn (insn
);
3502 shifted_operand
= recog_data
.operand
[shift_opnum
];
3504 /* Iterate over all the operands in DEP. If we write an operand
3505 that overlaps with SHIFTED_OPERAND, then we have increase the
3506 cost of this dependency. */
3508 preprocess_constraints ();
3509 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
3511 /* We can ignore strict inputs. */
3512 if (recog_data
.operand_type
[opno
] == OP_IN
)
3515 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
3522 /* XXX This is not strictly true for the FPA. */
3523 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
3524 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
3527 /* Call insns don't incur a stall, even if they follow a load. */
3528 if (REG_NOTE_KIND (link
) == 0
3529 && GET_CODE (insn
) == CALL_INSN
)
3532 if ((i_pat
= single_set (insn
)) != NULL
3533 && GET_CODE (SET_SRC (i_pat
)) == MEM
3534 && (d_pat
= single_set (dep
)) != NULL
3535 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
3537 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
3538 /* This is a load after a store, there is no conflict if the load reads
3539 from a cached area. Assume that loads from the stack, and from the
3540 constant pool are cached, and that others will miss. This is a
3543 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
3544 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
3545 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
3546 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
3553 static int fpa_consts_inited
= 0;
3555 static const char * const strings_fpa
[8] =
3558 "4", "5", "0.5", "10"
3561 static REAL_VALUE_TYPE values_fpa
[8];
3564 init_fpa_table (void)
3569 for (i
= 0; i
< 8; i
++)
3571 r
= REAL_VALUE_ATOF (strings_fpa
[i
], DFmode
);
3575 fpa_consts_inited
= 1;
3578 /* Return TRUE if rtx X is a valid immediate FPA constant. */
3580 const_double_rtx_ok_for_fpa (rtx x
)
3585 if (!fpa_consts_inited
)
3588 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3589 if (REAL_VALUE_MINUS_ZERO (r
))
3592 for (i
= 0; i
< 8; i
++)
3593 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
3599 /* Return TRUE if rtx X is a valid immediate FPA constant. */
3601 neg_const_double_rtx_ok_for_fpa (rtx x
)
3606 if (!fpa_consts_inited
)
3609 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3610 r
= REAL_VALUE_NEGATE (r
);
3611 if (REAL_VALUE_MINUS_ZERO (r
))
3614 for (i
= 0; i
< 8; i
++)
3615 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
3621 /* Predicates for `match_operand' and `match_operator'. */
3623 /* s_register_operand is the same as register_operand, but it doesn't accept
3626 This function exists because at the time it was put in it led to better
3627 code. SUBREG(MEM) always needs a reload in the places where
3628 s_register_operand is used, and this seemed to lead to excessive
3631 s_register_operand (rtx op
, enum machine_mode mode
)
3633 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3636 if (GET_CODE (op
) == SUBREG
)
3637 op
= SUBREG_REG (op
);
3639 /* We don't consider registers whose class is NO_REGS
3640 to be a register operand. */
3641 /* XXX might have to check for lo regs only for thumb ??? */
3642 return (GET_CODE (op
) == REG
3643 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3644 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
3647 /* A hard register operand (even before reload. */
3649 arm_hard_register_operand (rtx op
, enum machine_mode mode
)
3651 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3654 return (GET_CODE (op
) == REG
3655 && REGNO (op
) < FIRST_PSEUDO_REGISTER
);
3658 /* Only accept reg, subreg(reg), const_int. */
3660 reg_or_int_operand (rtx op
, enum machine_mode mode
)
3662 if (GET_CODE (op
) == CONST_INT
)
3665 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3668 if (GET_CODE (op
) == SUBREG
)
3669 op
= SUBREG_REG (op
);
3671 /* We don't consider registers whose class is NO_REGS
3672 to be a register operand. */
3673 return (GET_CODE (op
) == REG
3674 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3675 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
3678 /* Return 1 if OP is an item in memory, given that we are in reload. */
3680 arm_reload_memory_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3682 int regno
= true_regnum (op
);
3684 return (!CONSTANT_P (op
)
3686 || (GET_CODE (op
) == REG
3687 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)));
3690 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
3691 memory access (architecture V4).
3692 MODE is QImode if called when computing constraints, or VOIDmode when
3693 emitting patterns. In this latter case we cannot use memory_operand()
3694 because it will fail on badly formed MEMs, which is precisely what we are
3697 bad_signed_byte_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3699 if (GET_CODE (op
) != MEM
)
3704 /* A sum of anything more complex than reg + reg or reg + const is bad. */
3705 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3706 && (!s_register_operand (XEXP (op
, 0), VOIDmode
)
3707 || (!s_register_operand (XEXP (op
, 1), VOIDmode
)
3708 && GET_CODE (XEXP (op
, 1)) != CONST_INT
)))
3711 /* Big constants are also bad. */
3712 if (GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
3713 && (INTVAL (XEXP (op
, 1)) > 0xff
3714 || -INTVAL (XEXP (op
, 1)) > 0xff))
3717 /* Everything else is good, or can will automatically be made so. */
3721 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
3723 arm_rhs_operand (rtx op
, enum machine_mode mode
)
3725 return (s_register_operand (op
, mode
)
3726 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
))));
3729 /* Return TRUE for valid operands for the
3730 rhs of an ARM instruction, or a load. */
3732 arm_rhsm_operand (rtx op
, enum machine_mode mode
)
3734 return (s_register_operand (op
, mode
)
3735 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
)))
3736 || memory_operand (op
, mode
));
3739 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
3740 constant that is valid when negated. */
3742 arm_add_operand (rtx op
, enum machine_mode mode
)
3745 return thumb_cmp_operand (op
, mode
);
3747 return (s_register_operand (op
, mode
)
3748 || (GET_CODE (op
) == CONST_INT
3749 && (const_ok_for_arm (INTVAL (op
))
3750 || const_ok_for_arm (-INTVAL (op
)))));
3753 /* Return TRUE for valid ARM constants (or when valid if negated). */
3755 arm_addimm_operand (rtx op
, enum machine_mode mode
)
3757 return (GET_CODE (op
) == CONST_INT
3758 && (const_ok_for_arm (INTVAL (op
))
3759 || const_ok_for_arm (-INTVAL (op
))));
3763 arm_not_operand (rtx op
, enum machine_mode mode
)
3765 return (s_register_operand (op
, mode
)
3766 || (GET_CODE (op
) == CONST_INT
3767 && (const_ok_for_arm (INTVAL (op
))
3768 || const_ok_for_arm (~INTVAL (op
)))));
3771 /* Return TRUE if the operand is a memory reference which contains an
3772 offsettable address. */
3774 offsettable_memory_operand (rtx op
, enum machine_mode mode
)
3776 if (mode
== VOIDmode
)
3777 mode
= GET_MODE (op
);
3779 return (mode
== GET_MODE (op
)
3780 && GET_CODE (op
) == MEM
3781 && offsettable_address_p (reload_completed
| reload_in_progress
,
3782 mode
, XEXP (op
, 0)));
3785 /* Return TRUE if the operand is a memory reference which is, or can be
3786 made word aligned by adjusting the offset. */
3788 alignable_memory_operand (rtx op
, enum machine_mode mode
)
3792 if (mode
== VOIDmode
)
3793 mode
= GET_MODE (op
);
3795 if (mode
!= GET_MODE (op
) || GET_CODE (op
) != MEM
)
3800 return ((GET_CODE (reg
= op
) == REG
3801 || (GET_CODE (op
) == SUBREG
3802 && GET_CODE (reg
= SUBREG_REG (op
)) == REG
)
3803 || (GET_CODE (op
) == PLUS
3804 && GET_CODE (XEXP (op
, 1)) == CONST_INT
3805 && (GET_CODE (reg
= XEXP (op
, 0)) == REG
3806 || (GET_CODE (XEXP (op
, 0)) == SUBREG
3807 && GET_CODE (reg
= SUBREG_REG (XEXP (op
, 0))) == REG
))))
3808 && REGNO_POINTER_ALIGN (REGNO (reg
)) >= 32);
3811 /* Similar to s_register_operand, but does not allow hard integer
3814 f_register_operand (rtx op
, enum machine_mode mode
)
3816 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3819 if (GET_CODE (op
) == SUBREG
)
3820 op
= SUBREG_REG (op
);
3822 /* We don't consider registers whose class is NO_REGS
3823 to be a register operand. */
3824 return (GET_CODE (op
) == REG
3825 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3826 || REGNO_REG_CLASS (REGNO (op
)) == FPA_REGS
));
3829 /* Return TRUE for valid operands for the rhs of an FPA instruction. */
3831 fpa_rhs_operand (rtx op
, enum machine_mode mode
)
3833 if (s_register_operand (op
, mode
))
3836 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3839 if (GET_CODE (op
) == CONST_DOUBLE
)
3840 return const_double_rtx_ok_for_fpa (op
);
3846 fpa_add_operand (rtx op
, enum machine_mode mode
)
3848 if (s_register_operand (op
, mode
))
3851 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3854 if (GET_CODE (op
) == CONST_DOUBLE
)
3855 return (const_double_rtx_ok_for_fpa (op
)
3856 || neg_const_double_rtx_ok_for_fpa (op
));
3861 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
3863 cirrus_memory_offset (rtx op
)
3865 /* Reject eliminable registers. */
3866 if (! (reload_in_progress
|| reload_completed
)
3867 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
3868 || reg_mentioned_p (arg_pointer_rtx
, op
)
3869 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
3870 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
3871 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
3872 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
3875 if (GET_CODE (op
) == MEM
)
3881 /* Match: (mem (reg)). */
3882 if (GET_CODE (ind
) == REG
)
3888 if (GET_CODE (ind
) == PLUS
3889 && GET_CODE (XEXP (ind
, 0)) == REG
3890 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
3891 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
3898 /* Return nonzero if OP is a Cirrus or general register. */
3900 cirrus_register_operand (rtx op
, enum machine_mode mode
)
3902 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3905 if (GET_CODE (op
) == SUBREG
)
3906 op
= SUBREG_REG (op
);
3908 return (GET_CODE (op
) == REG
3909 && (REGNO_REG_CLASS (REGNO (op
)) == CIRRUS_REGS
3910 || REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
));
3913 /* Return nonzero if OP is a cirrus FP register. */
3915 cirrus_fp_register (rtx op
, enum machine_mode mode
)
3917 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3920 if (GET_CODE (op
) == SUBREG
)
3921 op
= SUBREG_REG (op
);
3923 return (GET_CODE (op
) == REG
3924 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3925 || REGNO_REG_CLASS (REGNO (op
)) == CIRRUS_REGS
));
3928 /* Return nonzero if OP is a 6bit constant (0..63). */
3930 cirrus_shift_const (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3932 return (GET_CODE (op
) == CONST_INT
3934 && INTVAL (op
) < 64);
3937 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
3938 Use by the Cirrus Maverick code which has to workaround
3939 a hardware bug triggered by such instructions. */
3941 arm_memory_load_p (rtx insn
)
3943 rtx body
, lhs
, rhs
;;
3945 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
3948 body
= PATTERN (insn
);
3950 if (GET_CODE (body
) != SET
)
3953 lhs
= XEXP (body
, 0);
3954 rhs
= XEXP (body
, 1);
3956 lhs
= REG_OR_SUBREG_RTX (lhs
);
3958 /* If the destination is not a general purpose
3959 register we do not have to worry. */
3960 if (GET_CODE (lhs
) != REG
3961 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
3964 /* As well as loads from memory we also have to react
3965 to loads of invalid constants which will be turned
3966 into loads from the minipool. */
3967 return (GET_CODE (rhs
) == MEM
3968 || GET_CODE (rhs
) == SYMBOL_REF
3969 || note_invalid_constants (insn
, -1, false));
3972 /* Return TRUE if INSN is a Cirrus instruction. */
3974 arm_cirrus_insn_p (rtx insn
)
3976 enum attr_cirrus attr
;
3978 /* get_attr aborts on USE and CLOBBER. */
3980 || GET_CODE (insn
) != INSN
3981 || GET_CODE (PATTERN (insn
)) == USE
3982 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
3985 attr
= get_attr_cirrus (insn
);
3987 return attr
!= CIRRUS_NOT
;
3990 /* Cirrus reorg for invalid instruction combinations. */
3992 cirrus_reorg (rtx first
)
3994 enum attr_cirrus attr
;
3995 rtx body
= PATTERN (first
);
3999 /* Any branch must be followed by 2 non Cirrus instructions. */
4000 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
4003 t
= next_nonnote_insn (first
);
4005 if (arm_cirrus_insn_p (t
))
4008 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
4012 emit_insn_after (gen_nop (), first
);
4017 /* (float (blah)) is in parallel with a clobber. */
4018 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
4019 body
= XVECEXP (body
, 0, 0);
4021 if (GET_CODE (body
) == SET
)
4023 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
4025 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4026 be followed by a non Cirrus insn. */
4027 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
4029 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
4030 emit_insn_after (gen_nop (), first
);
4034 else if (arm_memory_load_p (first
))
4036 unsigned int arm_regno
;
4038 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4039 ldr/cfmv64hr combination where the Rd field is the same
4040 in both instructions must be split with a non Cirrus
4047 /* Get Arm register number for ldr insn. */
4048 if (GET_CODE (lhs
) == REG
)
4049 arm_regno
= REGNO (lhs
);
4050 else if (GET_CODE (rhs
) == REG
)
4051 arm_regno
= REGNO (rhs
);
4056 first
= next_nonnote_insn (first
);
4058 if (! arm_cirrus_insn_p (first
))
4061 body
= PATTERN (first
);
4063 /* (float (blah)) is in parallel with a clobber. */
4064 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
4065 body
= XVECEXP (body
, 0, 0);
4067 if (GET_CODE (body
) == FLOAT
)
4068 body
= XEXP (body
, 0);
4070 if (get_attr_cirrus (first
) == CIRRUS_MOVE
4071 && GET_CODE (XEXP (body
, 1)) == REG
4072 && arm_regno
== REGNO (XEXP (body
, 1)))
4073 emit_insn_after (gen_nop (), first
);
4079 /* get_attr aborts on USE and CLOBBER. */
4081 || GET_CODE (first
) != INSN
4082 || GET_CODE (PATTERN (first
)) == USE
4083 || GET_CODE (PATTERN (first
)) == CLOBBER
)
4086 attr
= get_attr_cirrus (first
);
4088 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4089 must be followed by a non-coprocessor instruction. */
4090 if (attr
== CIRRUS_COMPARE
)
4094 t
= next_nonnote_insn (first
);
4096 if (arm_cirrus_insn_p (t
))
4099 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
4103 emit_insn_after (gen_nop (), first
);
4109 /* Return nonzero if OP is a constant power of two. */
4111 power_of_two_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4113 if (GET_CODE (op
) == CONST_INT
)
4115 HOST_WIDE_INT value
= INTVAL (op
);
4117 return value
!= 0 && (value
& (value
- 1)) == 0;
4123 /* Return TRUE for a valid operand of a DImode operation.
4124 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4125 Note that this disallows MEM(REG+REG), but allows
4126 MEM(PRE/POST_INC/DEC(REG)). */
4128 di_operand (rtx op
, enum machine_mode mode
)
4130 if (s_register_operand (op
, mode
))
4133 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
4136 if (GET_CODE (op
) == SUBREG
)
4137 op
= SUBREG_REG (op
);
4139 switch (GET_CODE (op
))
4146 return memory_address_p (DImode
, XEXP (op
, 0));
4153 /* Like di_operand, but don't accept constants. */
4155 nonimmediate_di_operand (rtx op
, enum machine_mode mode
)
4157 if (s_register_operand (op
, mode
))
4160 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
4163 if (GET_CODE (op
) == SUBREG
)
4164 op
= SUBREG_REG (op
);
4166 if (GET_CODE (op
) == MEM
)
4167 return memory_address_p (DImode
, XEXP (op
, 0));
4172 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
4173 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4174 Note that this disallows MEM(REG+REG), but allows
4175 MEM(PRE/POST_INC/DEC(REG)). */
4177 soft_df_operand (rtx op
, enum machine_mode mode
)
4179 if (s_register_operand (op
, mode
))
4182 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
4185 if (GET_CODE (op
) == SUBREG
&& CONSTANT_P (SUBREG_REG (op
)))
4188 if (GET_CODE (op
) == SUBREG
)
4189 op
= SUBREG_REG (op
);
4191 switch (GET_CODE (op
))
4197 return memory_address_p (DFmode
, XEXP (op
, 0));
4204 /* Like soft_df_operand, but don't accept constants. */
4206 nonimmediate_soft_df_operand (rtx op
, enum machine_mode mode
)
4208 if (s_register_operand (op
, mode
))
4211 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
4214 if (GET_CODE (op
) == SUBREG
)
4215 op
= SUBREG_REG (op
);
4217 if (GET_CODE (op
) == MEM
)
4218 return memory_address_p (DFmode
, XEXP (op
, 0));
4222 /* Return TRUE for valid index operands. */
4224 index_operand (rtx op
, enum machine_mode mode
)
4226 return (s_register_operand (op
, mode
)
4227 || (immediate_operand (op
, mode
)
4228 && (GET_CODE (op
) != CONST_INT
4229 || (INTVAL (op
) < 4096 && INTVAL (op
) > -4096))));
4232 /* Return TRUE for valid shifts by a constant. This also accepts any
4233 power of two on the (somewhat overly relaxed) assumption that the
4234 shift operator in this case was a mult. */
4236 const_shift_operand (rtx op
, enum machine_mode mode
)
4238 return (power_of_two_operand (op
, mode
)
4239 || (immediate_operand (op
, mode
)
4240 && (GET_CODE (op
) != CONST_INT
4241 || (INTVAL (op
) < 32 && INTVAL (op
) > 0))));
4244 /* Return TRUE for arithmetic operators which can be combined with a multiply
4247 shiftable_operator (rtx x
, enum machine_mode mode
)
4251 if (GET_MODE (x
) != mode
)
4254 code
= GET_CODE (x
);
4256 return (code
== PLUS
|| code
== MINUS
4257 || code
== IOR
|| code
== XOR
|| code
== AND
);
4260 /* Return TRUE for binary logical operators. */
4262 logical_binary_operator (rtx x
, enum machine_mode mode
)
4266 if (GET_MODE (x
) != mode
)
4269 code
= GET_CODE (x
);
4271 return (code
== IOR
|| code
== XOR
|| code
== AND
);
4274 /* Return TRUE for shift operators. */
4276 shift_operator (rtx x
,enum machine_mode mode
)
4280 if (GET_MODE (x
) != mode
)
4283 code
= GET_CODE (x
);
4286 return power_of_two_operand (XEXP (x
, 1), mode
);
4288 return (code
== ASHIFT
|| code
== ASHIFTRT
|| code
== LSHIFTRT
4289 || code
== ROTATERT
);
4292 /* Return TRUE if x is EQ or NE. */
4294 equality_operator (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4296 return GET_CODE (x
) == EQ
|| GET_CODE (x
) == NE
;
4299 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
4301 arm_comparison_operator (rtx x
, enum machine_mode mode
)
4303 return (comparison_operator (x
, mode
)
4304 && GET_CODE (x
) != LTGT
4305 && GET_CODE (x
) != UNEQ
);
4308 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
4310 minmax_operator (rtx x
, enum machine_mode mode
)
4312 enum rtx_code code
= GET_CODE (x
);
4314 if (GET_MODE (x
) != mode
)
4317 return code
== SMIN
|| code
== SMAX
|| code
== UMIN
|| code
== UMAX
;
4320 /* Return TRUE if this is the condition code register, if we aren't given
4321 a mode, accept any class CCmode register. */
4323 cc_register (rtx x
, enum machine_mode mode
)
4325 if (mode
== VOIDmode
)
4327 mode
= GET_MODE (x
);
4329 if (GET_MODE_CLASS (mode
) != MODE_CC
)
4333 if ( GET_MODE (x
) == mode
4334 && GET_CODE (x
) == REG
4335 && REGNO (x
) == CC_REGNUM
)
4341 /* Return TRUE if this is the condition code register, if we aren't given
4342 a mode, accept any class CCmode register which indicates a dominance
4345 dominant_cc_register (rtx x
, enum machine_mode mode
)
4347 if (mode
== VOIDmode
)
4349 mode
= GET_MODE (x
);
4351 if (GET_MODE_CLASS (mode
) != MODE_CC
)
4355 if (mode
!= CC_DNEmode
&& mode
!= CC_DEQmode
4356 && mode
!= CC_DLEmode
&& mode
!= CC_DLTmode
4357 && mode
!= CC_DGEmode
&& mode
!= CC_DGTmode
4358 && mode
!= CC_DLEUmode
&& mode
!= CC_DLTUmode
4359 && mode
!= CC_DGEUmode
&& mode
!= CC_DGTUmode
)
4362 return cc_register (x
, mode
);
4365 /* Return TRUE if X references a SYMBOL_REF. */
4367 symbol_mentioned_p (rtx x
)
4372 if (GET_CODE (x
) == SYMBOL_REF
)
4375 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
4377 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
4383 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4384 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
4387 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
4394 /* Return TRUE if X references a LABEL_REF. */
4396 label_mentioned_p (rtx x
)
4401 if (GET_CODE (x
) == LABEL_REF
)
4404 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
4405 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
4411 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4412 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
4415 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
4425 enum rtx_code code
= GET_CODE (x
);
4429 else if (code
== SMIN
)
4431 else if (code
== UMIN
)
4433 else if (code
== UMAX
)
4439 /* Return 1 if memory locations are adjacent. */
4441 adjacent_mem_locations (rtx a
, rtx b
)
4443 if ((GET_CODE (XEXP (a
, 0)) == REG
4444 || (GET_CODE (XEXP (a
, 0)) == PLUS
4445 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
4446 && (GET_CODE (XEXP (b
, 0)) == REG
4447 || (GET_CODE (XEXP (b
, 0)) == PLUS
4448 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
4450 int val0
= 0, val1
= 0;
4453 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
4455 reg0
= REGNO (XEXP (XEXP (a
, 0), 0));
4456 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
4459 reg0
= REGNO (XEXP (a
, 0));
4461 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
4463 reg1
= REGNO (XEXP (XEXP (b
, 0), 0));
4464 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
4467 reg1
= REGNO (XEXP (b
, 0));
4469 /* Don't accept any offset that will require multiple
4470 instructions to handle, since this would cause the
4471 arith_adjacentmem pattern to output an overlong sequence. */
4472 if (!const_ok_for_op (PLUS
, val0
) || !const_ok_for_op (PLUS
, val1
))
4475 return (reg0
== reg1
) && ((val1
- val0
) == 4 || (val0
- val1
) == 4);
4480 /* Return 1 if OP is a load multiple operation. It is known to be
4481 parallel and the first section will be tested. */
4483 load_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4485 HOST_WIDE_INT count
= XVECLEN (op
, 0);
4488 HOST_WIDE_INT i
= 1, base
= 0;
4492 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
4495 /* Check to see if this might be a write-back. */
4496 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
4501 /* Now check it more carefully. */
4502 if (GET_CODE (SET_DEST (elt
)) != REG
4503 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
4504 || REGNO (XEXP (SET_SRC (elt
), 0)) != REGNO (SET_DEST (elt
))
4505 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
4506 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
4510 /* Perform a quick check so we don't blow up below. */
4512 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
4513 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != REG
4514 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != MEM
)
4517 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, i
- 1)));
4518 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, i
- 1)), 0);
4520 for (; i
< count
; i
++)
4522 elt
= XVECEXP (op
, 0, i
);
4524 if (GET_CODE (elt
) != SET
4525 || GET_CODE (SET_DEST (elt
)) != REG
4526 || GET_MODE (SET_DEST (elt
)) != SImode
4527 || REGNO (SET_DEST (elt
)) != (unsigned int)(dest_regno
+ i
- base
)
4528 || GET_CODE (SET_SRC (elt
)) != MEM
4529 || GET_MODE (SET_SRC (elt
)) != SImode
4530 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
4531 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
4532 || GET_CODE (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != CONST_INT
4533 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != (i
- base
) * 4)
4540 /* Return 1 if OP is a store multiple operation. It is known to be
4541 parallel and the first section will be tested. */
4543 store_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4545 HOST_WIDE_INT count
= XVECLEN (op
, 0);
4548 HOST_WIDE_INT i
= 1, base
= 0;
4552 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
4555 /* Check to see if this might be a write-back. */
4556 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
4561 /* Now check it more carefully. */
4562 if (GET_CODE (SET_DEST (elt
)) != REG
4563 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
4564 || REGNO (XEXP (SET_SRC (elt
), 0)) != REGNO (SET_DEST (elt
))
4565 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
4566 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
4570 /* Perform a quick check so we don't blow up below. */
4572 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
4573 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != MEM
4574 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != REG
)
4577 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, i
- 1)));
4578 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, i
- 1)), 0);
4580 for (; i
< count
; i
++)
4582 elt
= XVECEXP (op
, 0, i
);
4584 if (GET_CODE (elt
) != SET
4585 || GET_CODE (SET_SRC (elt
)) != REG
4586 || GET_MODE (SET_SRC (elt
)) != SImode
4587 || REGNO (SET_SRC (elt
)) != (unsigned int)(src_regno
+ i
- base
)
4588 || GET_CODE (SET_DEST (elt
)) != MEM
4589 || GET_MODE (SET_DEST (elt
)) != SImode
4590 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
4591 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_addr
)
4592 || GET_CODE (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != CONST_INT
4593 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != (i
- base
) * 4)
4601 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
4602 HOST_WIDE_INT
*load_offset
)
4604 int unsorted_regs
[4];
4605 HOST_WIDE_INT unsorted_offsets
[4];
4610 /* Can only handle 2, 3, or 4 insns at present,
4611 though could be easily extended if required. */
4612 if (nops
< 2 || nops
> 4)
4615 /* Loop over the operands and check that the memory references are
4616 suitable (ie immediate offsets from the same base register). At
4617 the same time, extract the target register, and the memory
4619 for (i
= 0; i
< nops
; i
++)
4624 /* Convert a subreg of a mem into the mem itself. */
4625 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
4626 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
4628 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
4631 /* Don't reorder volatile memory references; it doesn't seem worth
4632 looking for the case where the order is ok anyway. */
4633 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
4636 offset
= const0_rtx
;
4638 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
4639 || (GET_CODE (reg
) == SUBREG
4640 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4641 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
4642 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
4644 || (GET_CODE (reg
) == SUBREG
4645 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4646 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
4651 base_reg
= REGNO (reg
);
4652 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
4653 ? REGNO (operands
[i
])
4654 : REGNO (SUBREG_REG (operands
[i
])));
4659 if (base_reg
!= (int) REGNO (reg
))
4660 /* Not addressed from the same base register. */
4663 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
4664 ? REGNO (operands
[i
])
4665 : REGNO (SUBREG_REG (operands
[i
])));
4666 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
4670 /* If it isn't an integer register, or if it overwrites the
4671 base register but isn't the last insn in the list, then
4672 we can't do this. */
4673 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
4674 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
4677 unsorted_offsets
[i
] = INTVAL (offset
);
4680 /* Not a suitable memory address. */
4684 /* All the useful information has now been extracted from the
4685 operands into unsorted_regs and unsorted_offsets; additionally,
4686 order[0] has been set to the lowest numbered register in the
4687 list. Sort the registers into order, and check that the memory
4688 offsets are ascending and adjacent. */
4690 for (i
= 1; i
< nops
; i
++)
4694 order
[i
] = order
[i
- 1];
4695 for (j
= 0; j
< nops
; j
++)
4696 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
4697 && (order
[i
] == order
[i
- 1]
4698 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
4701 /* Have we found a suitable register? if not, one must be used more
4703 if (order
[i
] == order
[i
- 1])
4706 /* Is the memory address adjacent and ascending? */
4707 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
4715 for (i
= 0; i
< nops
; i
++)
4716 regs
[i
] = unsorted_regs
[order
[i
]];
4718 *load_offset
= unsorted_offsets
[order
[0]];
4721 if (unsorted_offsets
[order
[0]] == 0)
4722 return 1; /* ldmia */
4724 if (unsorted_offsets
[order
[0]] == 4)
4725 return 2; /* ldmib */
4727 if (unsorted_offsets
[order
[nops
- 1]] == 0)
4728 return 3; /* ldmda */
4730 if (unsorted_offsets
[order
[nops
- 1]] == -4)
4731 return 4; /* ldmdb */
4733 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
4734 if the offset isn't small enough. The reason 2 ldrs are faster
4735 is because these ARMs are able to do more than one cache access
4736 in a single cycle. The ARM9 and StrongARM have Harvard caches,
4737 whilst the ARM8 has a double bandwidth cache. This means that
4738 these cores can do both an instruction fetch and a data fetch in
4739 a single cycle, so the trick of calculating the address into a
4740 scratch register (one of the result regs) and then doing a load
4741 multiple actually becomes slower (and no smaller in code size).
4742 That is the transformation
4744 ldr rd1, [rbase + offset]
4745 ldr rd2, [rbase + offset + 4]
4749 add rd1, rbase, offset
4750 ldmia rd1, {rd1, rd2}
4752 produces worse code -- '3 cycles + any stalls on rd2' instead of
4753 '2 cycles + any stalls on rd2'. On ARMs with only one cache
4754 access per cycle, the first sequence could never complete in less
4755 than 6 cycles, whereas the ldm sequence would only take 5 and
4756 would make better use of sequential accesses if not hitting the
4759 We cheat here and test 'arm_ld_sched' which we currently know to
4760 only be true for the ARM8, ARM9 and StrongARM. If this ever
4761 changes, then the test below needs to be reworked. */
4762 if (nops
== 2 && arm_ld_sched
)
4765 /* Can't do it without setting up the offset, only do this if it takes
4766 no more than one insn. */
4767 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
4768 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
4772 emit_ldm_seq (rtx
*operands
, int nops
)
4776 HOST_WIDE_INT offset
;
4780 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
4783 strcpy (buf
, "ldm%?ia\t");
4787 strcpy (buf
, "ldm%?ib\t");
4791 strcpy (buf
, "ldm%?da\t");
4795 strcpy (buf
, "ldm%?db\t");
4800 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
4801 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
4804 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
4805 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
4807 output_asm_insn (buf
, operands
);
4809 strcpy (buf
, "ldm%?ia\t");
4816 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
4817 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
4819 for (i
= 1; i
< nops
; i
++)
4820 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
4821 reg_names
[regs
[i
]]);
4823 strcat (buf
, "}\t%@ phole ldm");
4825 output_asm_insn (buf
, operands
);
4830 store_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
4831 HOST_WIDE_INT
* load_offset
)
4833 int unsorted_regs
[4];
4834 HOST_WIDE_INT unsorted_offsets
[4];
4839 /* Can only handle 2, 3, or 4 insns at present, though could be easily
4840 extended if required. */
4841 if (nops
< 2 || nops
> 4)
4844 /* Loop over the operands and check that the memory references are
4845 suitable (ie immediate offsets from the same base register). At
4846 the same time, extract the target register, and the memory
4848 for (i
= 0; i
< nops
; i
++)
4853 /* Convert a subreg of a mem into the mem itself. */
4854 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
4855 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
4857 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
4860 /* Don't reorder volatile memory references; it doesn't seem worth
4861 looking for the case where the order is ok anyway. */
4862 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
4865 offset
= const0_rtx
;
4867 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
4868 || (GET_CODE (reg
) == SUBREG
4869 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4870 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
4871 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
4873 || (GET_CODE (reg
) == SUBREG
4874 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4875 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
4880 base_reg
= REGNO (reg
);
4881 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
4882 ? REGNO (operands
[i
])
4883 : REGNO (SUBREG_REG (operands
[i
])));
4888 if (base_reg
!= (int) REGNO (reg
))
4889 /* Not addressed from the same base register. */
4892 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
4893 ? REGNO (operands
[i
])
4894 : REGNO (SUBREG_REG (operands
[i
])));
4895 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
4899 /* If it isn't an integer register, then we can't do this. */
4900 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
4903 unsorted_offsets
[i
] = INTVAL (offset
);
4906 /* Not a suitable memory address. */
4910 /* All the useful information has now been extracted from the
4911 operands into unsorted_regs and unsorted_offsets; additionally,
4912 order[0] has been set to the lowest numbered register in the
4913 list. Sort the registers into order, and check that the memory
4914 offsets are ascending and adjacent. */
4916 for (i
= 1; i
< nops
; i
++)
4920 order
[i
] = order
[i
- 1];
4921 for (j
= 0; j
< nops
; j
++)
4922 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
4923 && (order
[i
] == order
[i
- 1]
4924 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
4927 /* Have we found a suitable register? if not, one must be used more
4929 if (order
[i
] == order
[i
- 1])
4932 /* Is the memory address adjacent and ascending? */
4933 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
4941 for (i
= 0; i
< nops
; i
++)
4942 regs
[i
] = unsorted_regs
[order
[i
]];
4944 *load_offset
= unsorted_offsets
[order
[0]];
4947 if (unsorted_offsets
[order
[0]] == 0)
4948 return 1; /* stmia */
4950 if (unsorted_offsets
[order
[0]] == 4)
4951 return 2; /* stmib */
4953 if (unsorted_offsets
[order
[nops
- 1]] == 0)
4954 return 3; /* stmda */
4956 if (unsorted_offsets
[order
[nops
- 1]] == -4)
4957 return 4; /* stmdb */
4963 emit_stm_seq (rtx
*operands
, int nops
)
4967 HOST_WIDE_INT offset
;
4971 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
4974 strcpy (buf
, "stm%?ia\t");
4978 strcpy (buf
, "stm%?ib\t");
4982 strcpy (buf
, "stm%?da\t");
4986 strcpy (buf
, "stm%?db\t");
4993 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
4994 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
4996 for (i
= 1; i
< nops
; i
++)
4997 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
4998 reg_names
[regs
[i
]]);
5000 strcat (buf
, "}\t%@ phole stm");
5002 output_asm_insn (buf
, operands
);
5007 multi_register_push (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
5009 if (GET_CODE (op
) != PARALLEL
5010 || (GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
5011 || (GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC
)
5012 || (XINT (SET_SRC (XVECEXP (op
, 0, 0)), 1) != UNSPEC_PUSH_MULT
))
5018 /* Routines for use in generating RTL. */
5021 arm_gen_load_multiple (int base_regno
, int count
, rtx from
, int up
,
5022 int write_back
, int unchanging_p
, int in_struct_p
,
5027 int sign
= up
? 1 : -1;
5030 /* XScale has load-store double instructions, but they have stricter
5031 alignment requirements than load-store multiple, so we can not
5034 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5035 the pipeline until completion.
5043 An ldr instruction takes 1-3 cycles, but does not block the
5052 Best case ldr will always win. However, the more ldr instructions
5053 we issue, the less likely we are to be able to schedule them well.
5054 Using ldr instructions also increases code size.
5056 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5057 for counts of 3 or 4 regs. */
5058 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
5064 for (i
= 0; i
< count
; i
++)
5066 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, i
* 4 * sign
));
5067 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5068 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5069 MEM_SCALAR_P (mem
) = scalar_p
;
5070 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
5074 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
5082 result
= gen_rtx_PARALLEL (VOIDmode
,
5083 rtvec_alloc (count
+ (write_back
? 1 : 0)));
5086 XVECEXP (result
, 0, 0)
5087 = gen_rtx_SET (GET_MODE (from
), from
,
5088 plus_constant (from
, count
* 4 * sign
));
5093 for (j
= 0; i
< count
; i
++, j
++)
5095 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, j
* 4 * sign
));
5096 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5097 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5098 MEM_SCALAR_P (mem
) = scalar_p
;
5099 XVECEXP (result
, 0, i
)
5100 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
5107 arm_gen_store_multiple (int base_regno
, int count
, rtx to
, int up
,
5108 int write_back
, int unchanging_p
, int in_struct_p
,
5113 int sign
= up
? 1 : -1;
5116 /* See arm_gen_load_multiple for discussion of
5117 the pros/cons of ldm/stm usage for XScale. */
5118 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
5124 for (i
= 0; i
< count
; i
++)
5126 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, i
* 4 * sign
));
5127 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5128 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5129 MEM_SCALAR_P (mem
) = scalar_p
;
5130 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
5134 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
5142 result
= gen_rtx_PARALLEL (VOIDmode
,
5143 rtvec_alloc (count
+ (write_back
? 1 : 0)));
5146 XVECEXP (result
, 0, 0)
5147 = gen_rtx_SET (GET_MODE (to
), to
,
5148 plus_constant (to
, count
* 4 * sign
));
5153 for (j
= 0; i
< count
; i
++, j
++)
5155 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, j
* 4 * sign
));
5156 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5157 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5158 MEM_SCALAR_P (mem
) = scalar_p
;
5160 XVECEXP (result
, 0, i
)
5161 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
5168 arm_gen_movstrqi (rtx
*operands
)
5170 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
5173 rtx st_src
, st_dst
, fin_src
, fin_dst
;
5174 rtx part_bytes_reg
= NULL
;
5176 int dst_unchanging_p
, dst_in_struct_p
, src_unchanging_p
, src_in_struct_p
;
5177 int dst_scalar_p
, src_scalar_p
;
5179 if (GET_CODE (operands
[2]) != CONST_INT
5180 || GET_CODE (operands
[3]) != CONST_INT
5181 || INTVAL (operands
[2]) > 64
5182 || INTVAL (operands
[3]) & 3)
5185 st_dst
= XEXP (operands
[0], 0);
5186 st_src
= XEXP (operands
[1], 0);
5188 dst_unchanging_p
= RTX_UNCHANGING_P (operands
[0]);
5189 dst_in_struct_p
= MEM_IN_STRUCT_P (operands
[0]);
5190 dst_scalar_p
= MEM_SCALAR_P (operands
[0]);
5191 src_unchanging_p
= RTX_UNCHANGING_P (operands
[1]);
5192 src_in_struct_p
= MEM_IN_STRUCT_P (operands
[1]);
5193 src_scalar_p
= MEM_SCALAR_P (operands
[1]);
5195 fin_dst
= dst
= copy_to_mode_reg (SImode
, st_dst
);
5196 fin_src
= src
= copy_to_mode_reg (SImode
, st_src
);
5198 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
5199 out_words_to_go
= INTVAL (operands
[2]) / 4;
5200 last_bytes
= INTVAL (operands
[2]) & 3;
5202 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
5203 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
5205 for (i
= 0; in_words_to_go
>= 2; i
+=4)
5207 if (in_words_to_go
> 4)
5208 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
5213 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
5214 FALSE
, src_unchanging_p
,
5215 src_in_struct_p
, src_scalar_p
));
5217 if (out_words_to_go
)
5219 if (out_words_to_go
> 4)
5220 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
5224 else if (out_words_to_go
!= 1)
5225 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
5234 mem
= gen_rtx_MEM (SImode
, dst
);
5235 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
5236 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
5237 MEM_SCALAR_P (mem
) = dst_scalar_p
;
5238 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
5239 if (last_bytes
!= 0)
5240 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
5244 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
5245 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
5248 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
5249 if (out_words_to_go
)
5253 mem
= gen_rtx_MEM (SImode
, src
);
5254 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
5255 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
5256 MEM_SCALAR_P (mem
) = src_scalar_p
;
5257 emit_move_insn (sreg
= gen_reg_rtx (SImode
), mem
);
5258 emit_move_insn (fin_src
= gen_reg_rtx (SImode
), plus_constant (src
, 4));
5260 mem
= gen_rtx_MEM (SImode
, dst
);
5261 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
5262 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
5263 MEM_SCALAR_P (mem
) = dst_scalar_p
;
5264 emit_move_insn (mem
, sreg
);
5265 emit_move_insn (fin_dst
= gen_reg_rtx (SImode
), plus_constant (dst
, 4));
5268 if (in_words_to_go
) /* Sanity check */
5274 if (in_words_to_go
< 0)
5277 mem
= gen_rtx_MEM (SImode
, src
);
5278 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
5279 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
5280 MEM_SCALAR_P (mem
) = src_scalar_p
;
5281 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
5284 if (last_bytes
&& part_bytes_reg
== NULL
)
5287 if (BYTES_BIG_ENDIAN
&& last_bytes
)
5289 rtx tmp
= gen_reg_rtx (SImode
);
5291 /* The bytes we want are in the top end of the word. */
5292 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
5293 GEN_INT (8 * (4 - last_bytes
))));
5294 part_bytes_reg
= tmp
;
5298 mem
= gen_rtx_MEM (QImode
, plus_constant (dst
, last_bytes
- 1));
5299 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
5300 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
5301 MEM_SCALAR_P (mem
) = dst_scalar_p
;
5302 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
5306 tmp
= gen_reg_rtx (SImode
);
5307 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
5308 part_bytes_reg
= tmp
;
5317 mem
= gen_rtx_MEM (HImode
, dst
);
5318 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
5319 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
5320 MEM_SCALAR_P (mem
) = dst_scalar_p
;
5321 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
5325 rtx tmp
= gen_reg_rtx (SImode
);
5327 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (2)));
5328 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
5329 part_bytes_reg
= tmp
;
5335 mem
= gen_rtx_MEM (QImode
, dst
);
5336 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
5337 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
5338 MEM_SCALAR_P (mem
) = dst_scalar_p
;
5339 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
5346 /* Generate a memory reference for a half word, such that it will be loaded
5347 into the top 16 bits of the word. We can assume that the address is
5348 known to be alignable and of the form reg, or plus (reg, const). */
5351 arm_gen_rotated_half_load (rtx memref
)
5353 HOST_WIDE_INT offset
= 0;
5354 rtx base
= XEXP (memref
, 0);
5356 if (GET_CODE (base
) == PLUS
)
5358 offset
= INTVAL (XEXP (base
, 1));
5359 base
= XEXP (base
, 0);
5362 /* If we aren't allowed to generate unaligned addresses, then fail. */
5363 if (TARGET_MMU_TRAPS
5364 && ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 0)))
5367 base
= gen_rtx_MEM (SImode
, plus_constant (base
, offset
& ~2));
5369 if ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 2))
5372 return gen_rtx_ROTATE (SImode
, base
, GEN_INT (16));
5375 /* Select a dominance comparison mode if possible for a test of the general
5376 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
5377 COND_OR == DOM_CC_X_AND_Y => (X && Y)
5378 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
5379 COND_OR == DOM_CC_X_OR_Y => (X || Y)
5380 In all cases OP will be either EQ or NE, but we don't need to know which
5381 here. If we are unable to support a dominance comparison we return
5382 CC mode. This will then fail to match for the RTL expressions that
5383 generate this call. */
5385 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
5387 enum rtx_code cond1
, cond2
;
5390 /* Currently we will probably get the wrong result if the individual
5391 comparisons are not simple. This also ensures that it is safe to
5392 reverse a comparison if necessary. */
5393 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
5395 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
5399 /* The if_then_else variant of this tests the second condition if the
5400 first passes, but is true if the first fails. Reverse the first
5401 condition to get a true "inclusive-or" expression. */
5402 if (cond_or
== DOM_CC_NX_OR_Y
)
5403 cond1
= reverse_condition (cond1
);
5405 /* If the comparisons are not equal, and one doesn't dominate the other,
5406 then we can't do this. */
5408 && !comparison_dominates_p (cond1
, cond2
)
5409 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
5414 enum rtx_code temp
= cond1
;
5422 if (cond2
== EQ
|| cond_or
== DOM_CC_X_AND_Y
)
5427 case LE
: return CC_DLEmode
;
5428 case LEU
: return CC_DLEUmode
;
5429 case GE
: return CC_DGEmode
;
5430 case GEU
: return CC_DGEUmode
;
5437 if (cond2
== LT
|| cond_or
== DOM_CC_X_AND_Y
)
5446 if (cond2
== GT
|| cond_or
== DOM_CC_X_AND_Y
)
5455 if (cond2
== LTU
|| cond_or
== DOM_CC_X_AND_Y
)
5464 if (cond2
== GTU
|| cond_or
== DOM_CC_X_AND_Y
)
5472 /* The remaining cases only occur when both comparisons are the
5497 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
5499 /* All floating point compares return CCFP if it is an equality
5500 comparison, and CCFPE otherwise. */
5501 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5530 /* A compare with a shifted operand. Because of canonicalization, the
5531 comparison will have to be swapped when we emit the assembler. */
5532 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
5533 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
5534 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
5535 || GET_CODE (x
) == ROTATERT
))
5538 /* This is a special case that is used by combine to allow a
5539 comparison of a shifted byte load to be split into a zero-extend
5540 followed by a comparison of the shifted integer (only valid for
5541 equalities and unsigned inequalities). */
5542 if (GET_MODE (x
) == SImode
5543 && GET_CODE (x
) == ASHIFT
5544 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
5545 && GET_CODE (XEXP (x
, 0)) == SUBREG
5546 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
5547 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
5548 && (op
== EQ
|| op
== NE
5549 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
5550 && GET_CODE (y
) == CONST_INT
)
5553 /* A construct for a conditional compare, if the false arm contains
5554 0, then both conditions must be true, otherwise either condition
5555 must be true. Not all conditions are possible, so CCmode is
5556 returned if it can't be done. */
5557 if (GET_CODE (x
) == IF_THEN_ELSE
5558 && (XEXP (x
, 2) == const0_rtx
5559 || XEXP (x
, 2) == const1_rtx
)
5560 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
5561 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
5562 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
5563 INTVAL (XEXP (x
, 2)));
5565 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
5566 if (GET_CODE (x
) == AND
5567 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
5568 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
5569 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
5572 if (GET_CODE (x
) == IOR
5573 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
5574 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
5575 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
5578 /* An operation that sets the condition codes as a side-effect, the
5579 V flag is not set correctly, so we can only use comparisons where
5580 this doesn't matter. (For LT and GE we can use "mi" and "pl"
5582 if (GET_MODE (x
) == SImode
5584 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
5585 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
5586 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
5587 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
5588 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
5589 || GET_CODE (x
) == LSHIFTRT
5590 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
5591 || GET_CODE (x
) == ROTATERT
|| GET_CODE (x
) == ZERO_EXTRACT
))
5594 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
5597 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
5598 && GET_CODE (x
) == PLUS
5599 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
5605 /* X and Y are two things to compare using CODE. Emit the compare insn and
5606 return the rtx for register 0 in the proper mode. FP means this is a
5607 floating point compare: I don't think that it is needed on the arm. */
5609 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
5611 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
5612 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
5614 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
5615 gen_rtx_COMPARE (mode
, x
, y
)));
5620 /* Generate a sequence of insns that will generate the correct return
5621 address mask depending on the physical architecture that the program
5624 arm_gen_return_addr_mask (void)
5626 rtx reg
= gen_reg_rtx (Pmode
);
5628 emit_insn (gen_return_addr_mask (reg
));
5633 arm_reload_in_hi (rtx
*operands
)
5635 rtx ref
= operands
[1];
5637 HOST_WIDE_INT offset
= 0;
5639 if (GET_CODE (ref
) == SUBREG
)
5641 offset
= SUBREG_BYTE (ref
);
5642 ref
= SUBREG_REG (ref
);
5645 if (GET_CODE (ref
) == REG
)
5647 /* We have a pseudo which has been spilt onto the stack; there
5648 are two cases here: the first where there is a simple
5649 stack-slot replacement and a second where the stack-slot is
5650 out of range, or is used as a subreg. */
5651 if (reg_equiv_mem
[REGNO (ref
)])
5653 ref
= reg_equiv_mem
[REGNO (ref
)];
5654 base
= find_replacement (&XEXP (ref
, 0));
5657 /* The slot is out of range, or was dressed up in a SUBREG. */
5658 base
= reg_equiv_address
[REGNO (ref
)];
5661 base
= find_replacement (&XEXP (ref
, 0));
5663 /* Handle the case where the address is too complex to be offset by 1. */
5664 if (GET_CODE (base
) == MINUS
5665 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
5667 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5669 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
5672 else if (GET_CODE (base
) == PLUS
)
5674 /* The addend must be CONST_INT, or we would have dealt with it above. */
5675 HOST_WIDE_INT hi
, lo
;
5677 offset
+= INTVAL (XEXP (base
, 1));
5678 base
= XEXP (base
, 0);
5680 /* Rework the address into a legal sequence of insns. */
5681 /* Valid range for lo is -4095 -> 4095 */
5684 : -((-offset
) & 0xfff));
5686 /* Corner case, if lo is the max offset then we would be out of range
5687 once we have added the additional 1 below, so bump the msb into the
5688 pre-loading insn(s). */
5692 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
5693 ^ (HOST_WIDE_INT
) 0x80000000)
5694 - (HOST_WIDE_INT
) 0x80000000);
5696 if (hi
+ lo
!= offset
)
5701 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5703 /* Get the base address; addsi3 knows how to handle constants
5704 that require more than one insn. */
5705 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
5711 /* Operands[2] may overlap operands[0] (though it won't overlap
5712 operands[1]), that's why we asked for a DImode reg -- so we can
5713 use the bit that does not overlap. */
5714 if (REGNO (operands
[2]) == REGNO (operands
[0]))
5715 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5717 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
5719 emit_insn (gen_zero_extendqisi2 (scratch
,
5720 gen_rtx_MEM (QImode
,
5721 plus_constant (base
,
5723 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
5724 gen_rtx_MEM (QImode
,
5725 plus_constant (base
,
5727 if (!BYTES_BIG_ENDIAN
)
5728 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
5729 gen_rtx_IOR (SImode
,
5732 gen_rtx_SUBREG (SImode
, operands
[0], 0),
5736 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
5737 gen_rtx_IOR (SImode
,
5738 gen_rtx_ASHIFT (SImode
, scratch
,
5740 gen_rtx_SUBREG (SImode
, operands
[0],
5744 /* Handle storing a half-word to memory during reload by synthesizing as two
5745 byte stores. Take care not to clobber the input values until after we
5746 have moved them somewhere safe. This code assumes that if the DImode
5747 scratch in operands[2] overlaps either the input value or output address
5748 in some way, then that value must die in this insn (we absolutely need
5749 two scratch registers for some corner cases). */
5751 arm_reload_out_hi (rtx
*operands
)
5753 rtx ref
= operands
[0];
5754 rtx outval
= operands
[1];
5756 HOST_WIDE_INT offset
= 0;
5758 if (GET_CODE (ref
) == SUBREG
)
5760 offset
= SUBREG_BYTE (ref
);
5761 ref
= SUBREG_REG (ref
);
5764 if (GET_CODE (ref
) == REG
)
5766 /* We have a pseudo which has been spilt onto the stack; there
5767 are two cases here: the first where there is a simple
5768 stack-slot replacement and a second where the stack-slot is
5769 out of range, or is used as a subreg. */
5770 if (reg_equiv_mem
[REGNO (ref
)])
5772 ref
= reg_equiv_mem
[REGNO (ref
)];
5773 base
= find_replacement (&XEXP (ref
, 0));
5776 /* The slot is out of range, or was dressed up in a SUBREG. */
5777 base
= reg_equiv_address
[REGNO (ref
)];
5780 base
= find_replacement (&XEXP (ref
, 0));
5782 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
5784 /* Handle the case where the address is too complex to be offset by 1. */
5785 if (GET_CODE (base
) == MINUS
5786 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
5788 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5790 /* Be careful not to destroy OUTVAL. */
5791 if (reg_overlap_mentioned_p (base_plus
, outval
))
5793 /* Updating base_plus might destroy outval, see if we can
5794 swap the scratch and base_plus. */
5795 if (!reg_overlap_mentioned_p (scratch
, outval
))
5798 scratch
= base_plus
;
5803 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
5805 /* Be conservative and copy OUTVAL into the scratch now,
5806 this should only be necessary if outval is a subreg
5807 of something larger than a word. */
5808 /* XXX Might this clobber base? I can't see how it can,
5809 since scratch is known to overlap with OUTVAL, and
5810 must be wider than a word. */
5811 emit_insn (gen_movhi (scratch_hi
, outval
));
5812 outval
= scratch_hi
;
5816 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
5819 else if (GET_CODE (base
) == PLUS
)
5821 /* The addend must be CONST_INT, or we would have dealt with it above. */
5822 HOST_WIDE_INT hi
, lo
;
5824 offset
+= INTVAL (XEXP (base
, 1));
5825 base
= XEXP (base
, 0);
5827 /* Rework the address into a legal sequence of insns. */
5828 /* Valid range for lo is -4095 -> 4095 */
5831 : -((-offset
) & 0xfff));
5833 /* Corner case, if lo is the max offset then we would be out of range
5834 once we have added the additional 1 below, so bump the msb into the
5835 pre-loading insn(s). */
5839 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
5840 ^ (HOST_WIDE_INT
) 0x80000000)
5841 - (HOST_WIDE_INT
) 0x80000000);
5843 if (hi
+ lo
!= offset
)
5848 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5850 /* Be careful not to destroy OUTVAL. */
5851 if (reg_overlap_mentioned_p (base_plus
, outval
))
5853 /* Updating base_plus might destroy outval, see if we
5854 can swap the scratch and base_plus. */
5855 if (!reg_overlap_mentioned_p (scratch
, outval
))
5858 scratch
= base_plus
;
5863 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
5865 /* Be conservative and copy outval into scratch now,
5866 this should only be necessary if outval is a
5867 subreg of something larger than a word. */
5868 /* XXX Might this clobber base? I can't see how it
5869 can, since scratch is known to overlap with
5871 emit_insn (gen_movhi (scratch_hi
, outval
));
5872 outval
= scratch_hi
;
5876 /* Get the base address; addsi3 knows how to handle constants
5877 that require more than one insn. */
5878 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
5884 if (BYTES_BIG_ENDIAN
)
5886 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
5887 plus_constant (base
, offset
+ 1)),
5888 gen_lowpart (QImode
, outval
)));
5889 emit_insn (gen_lshrsi3 (scratch
,
5890 gen_rtx_SUBREG (SImode
, outval
, 0),
5892 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
5893 gen_lowpart (QImode
, scratch
)));
5897 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
5898 gen_lowpart (QImode
, outval
)));
5899 emit_insn (gen_lshrsi3 (scratch
,
5900 gen_rtx_SUBREG (SImode
, outval
, 0),
5902 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
5903 plus_constant (base
, offset
+ 1)),
5904 gen_lowpart (QImode
, scratch
)));
5908 /* Print a symbolic form of X to the debug file, F. */
5910 arm_print_value (FILE *f
, rtx x
)
5912 switch (GET_CODE (x
))
5915 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
5919 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
5927 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
5929 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
5930 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
5938 fprintf (f
, "\"%s\"", XSTR (x
, 0));
5942 fprintf (f
, "`%s'", XSTR (x
, 0));
5946 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
5950 arm_print_value (f
, XEXP (x
, 0));
5954 arm_print_value (f
, XEXP (x
, 0));
5956 arm_print_value (f
, XEXP (x
, 1));
5964 fprintf (f
, "????");
5969 /* Routines for manipulation of the constant pool. */
5971 /* Arm instructions cannot load a large constant directly into a
5972 register; they have to come from a pc relative load. The constant
5973 must therefore be placed in the addressable range of the pc
5974 relative load. Depending on the precise pc relative load
5975 instruction the range is somewhere between 256 bytes and 4k. This
5976 means that we often have to dump a constant inside a function, and
5977 generate code to branch around it.
5979 It is important to minimize this, since the branches will slow
5980 things down and make the code larger.
5982 Normally we can hide the table after an existing unconditional
5983 branch so that there is no interruption of the flow, but in the
5984 worst case the code looks like this:
6002 We fix this by performing a scan after scheduling, which notices
6003 which instructions need to have their operands fetched from the
6004 constant table and builds the table.
6006 The algorithm starts by building a table of all the constants that
6007 need fixing up and all the natural barriers in the function (places
6008 where a constant table can be dropped without breaking the flow).
6009 For each fixup we note how far the pc-relative replacement will be
6010 able to reach and the offset of the instruction into the function.
6012 Having built the table we then group the fixes together to form
6013 tables that are as large as possible (subject to addressing
6014 constraints) and emit each table of constants after the last
6015 barrier that is within range of all the instructions in the group.
6016 If a group does not contain a barrier, then we forcibly create one
6017 by inserting a jump instruction into the flow. Once the table has
6018 been inserted, the insns are then modified to reference the
6019 relevant entry in the pool.
6021 Possible enhancements to the algorithm (not implemented) are:
6023 1) For some processors and object formats, there may be benefit in
6024 aligning the pools to the start of cache lines; this alignment
6025 would need to be taken into account when calculating addressability
6028 /* These typedefs are located at the start of this file, so that
6029 they can be used in the prototypes there. This comment is to
6030 remind readers of that fact so that the following structures
6031 can be understood more easily.
6033 typedef struct minipool_node Mnode;
6034 typedef struct minipool_fixup Mfix; */
6036 struct minipool_node
6038 /* Doubly linked chain of entries. */
6041 /* The maximum offset into the code that this entry can be placed. While
6042 pushing fixes for forward references, all entries are sorted in order
6043 of increasing max_address. */
6044 HOST_WIDE_INT max_address
;
6045 /* Similarly for an entry inserted for a backwards ref. */
6046 HOST_WIDE_INT min_address
;
6047 /* The number of fixes referencing this entry. This can become zero
6048 if we "unpush" an entry. In this case we ignore the entry when we
6049 come to emit the code. */
6051 /* The offset from the start of the minipool. */
6052 HOST_WIDE_INT offset
;
6053 /* The value in table. */
6055 /* The mode of value. */
6056 enum machine_mode mode
;
6057 /* The size of the value. With iWMMXt enabled
6058 sizes > 4 also imply an alignment of 8-bytes. */
6062 struct minipool_fixup
6066 HOST_WIDE_INT address
;
6068 enum machine_mode mode
;
6072 HOST_WIDE_INT forwards
;
6073 HOST_WIDE_INT backwards
;
6076 /* Fixes less than a word need padding out to a word boundary. */
6077 #define MINIPOOL_FIX_SIZE(mode) \
6078 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6080 static Mnode
* minipool_vector_head
;
6081 static Mnode
* minipool_vector_tail
;
6082 static rtx minipool_vector_label
;
6084 /* The linked list of all minipool fixes required for this function. */
6085 Mfix
* minipool_fix_head
;
6086 Mfix
* minipool_fix_tail
;
6087 /* The fix entry for the current minipool, once it has been placed. */
6088 Mfix
* minipool_barrier
;
6090 /* Determines if INSN is the start of a jump table. Returns the end
6091 of the TABLE or NULL_RTX. */
6093 is_jump_table (rtx insn
)
6097 if (GET_CODE (insn
) == JUMP_INSN
6098 && JUMP_LABEL (insn
) != NULL
6099 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
6100 == next_real_insn (insn
))
6102 && GET_CODE (table
) == JUMP_INSN
6103 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
6104 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
6110 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6111 #define JUMP_TABLES_IN_TEXT_SECTION 0
6114 static HOST_WIDE_INT
6115 get_jump_table_size (rtx insn
)
6117 /* ADDR_VECs only take room if read-only data does into the text
6119 if (JUMP_TABLES_IN_TEXT_SECTION
6120 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6125 rtx body
= PATTERN (insn
);
6126 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
6128 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
6134 /* Move a minipool fix MP from its current location to before MAX_MP.
6135 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6136 constraints may need updating. */
6138 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
6139 HOST_WIDE_INT max_address
)
6141 /* This should never be true and the code below assumes these are
6148 if (max_address
< mp
->max_address
)
6149 mp
->max_address
= max_address
;
6153 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
6154 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
6156 mp
->max_address
= max_address
;
6158 /* Unlink MP from its current position. Since max_mp is non-null,
6159 mp->prev must be non-null. */
6160 mp
->prev
->next
= mp
->next
;
6161 if (mp
->next
!= NULL
)
6162 mp
->next
->prev
= mp
->prev
;
6164 minipool_vector_tail
= mp
->prev
;
6166 /* Re-insert it before MAX_MP. */
6168 mp
->prev
= max_mp
->prev
;
6171 if (mp
->prev
!= NULL
)
6172 mp
->prev
->next
= mp
;
6174 minipool_vector_head
= mp
;
6177 /* Save the new entry. */
6180 /* Scan over the preceding entries and adjust their addresses as
6182 while (mp
->prev
!= NULL
6183 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
6185 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
6192 /* Add a constant to the minipool for a forward reference. Returns the
6193 node added or NULL if the constant will not fit in this pool. */
6195 add_minipool_forward_ref (Mfix
*fix
)
6197 /* If set, max_mp is the first pool_entry that has a lower
6198 constraint than the one we are trying to add. */
6199 Mnode
* max_mp
= NULL
;
6200 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
;
6203 /* If this fix's address is greater than the address of the first
6204 entry, then we can't put the fix in this pool. We subtract the
6205 size of the current fix to ensure that if the table is fully
6206 packed we still have enough room to insert this value by suffling
6207 the other fixes forwards. */
6208 if (minipool_vector_head
&&
6209 fix
->address
>= minipool_vector_head
->max_address
- fix
->fix_size
)
6212 /* Scan the pool to see if a constant with the same value has
6213 already been added. While we are doing this, also note the
6214 location where we must insert the constant if it doesn't already
6216 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
6218 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
6219 && fix
->mode
== mp
->mode
6220 && (GET_CODE (fix
->value
) != CODE_LABEL
6221 || (CODE_LABEL_NUMBER (fix
->value
)
6222 == CODE_LABEL_NUMBER (mp
->value
)))
6223 && rtx_equal_p (fix
->value
, mp
->value
))
6225 /* More than one fix references this entry. */
6227 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
6230 /* Note the insertion point if necessary. */
6232 && mp
->max_address
> max_address
)
6235 /* If we are inserting an 8-bytes aligned quantity and
6236 we have not already found an insertion point, then
6237 make sure that all such 8-byte aligned quantities are
6238 placed at the start of the pool. */
6239 if (TARGET_REALLY_IWMMXT
6241 && fix
->fix_size
== 8
6242 && mp
->fix_size
!= 8)
6245 max_address
= mp
->max_address
;
6249 /* The value is not currently in the minipool, so we need to create
6250 a new entry for it. If MAX_MP is NULL, the entry will be put on
6251 the end of the list since the placement is less constrained than
6252 any existing entry. Otherwise, we insert the new fix before
6253 MAX_MP and, if necessary, adjust the constraints on the other
6255 mp
= xmalloc (sizeof (* mp
));
6256 mp
->fix_size
= fix
->fix_size
;
6257 mp
->mode
= fix
->mode
;
6258 mp
->value
= fix
->value
;
6260 /* Not yet required for a backwards ref. */
6261 mp
->min_address
= -65536;
6265 mp
->max_address
= max_address
;
6267 mp
->prev
= minipool_vector_tail
;
6269 if (mp
->prev
== NULL
)
6271 minipool_vector_head
= mp
;
6272 minipool_vector_label
= gen_label_rtx ();
6275 mp
->prev
->next
= mp
;
6277 minipool_vector_tail
= mp
;
6281 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
6282 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
6284 mp
->max_address
= max_address
;
6287 mp
->prev
= max_mp
->prev
;
6289 if (mp
->prev
!= NULL
)
6290 mp
->prev
->next
= mp
;
6292 minipool_vector_head
= mp
;
6295 /* Save the new entry. */
6298 /* Scan over the preceding entries and adjust their addresses as
6300 while (mp
->prev
!= NULL
6301 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
6303 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
6311 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
6312 HOST_WIDE_INT min_address
)
6314 HOST_WIDE_INT offset
;
6316 /* This should never be true, and the code below assumes these are
6323 if (min_address
> mp
->min_address
)
6324 mp
->min_address
= min_address
;
6328 /* We will adjust this below if it is too loose. */
6329 mp
->min_address
= min_address
;
6331 /* Unlink MP from its current position. Since min_mp is non-null,
6332 mp->next must be non-null. */
6333 mp
->next
->prev
= mp
->prev
;
6334 if (mp
->prev
!= NULL
)
6335 mp
->prev
->next
= mp
->next
;
6337 minipool_vector_head
= mp
->next
;
6339 /* Reinsert it after MIN_MP. */
6341 mp
->next
= min_mp
->next
;
6343 if (mp
->next
!= NULL
)
6344 mp
->next
->prev
= mp
;
6346 minipool_vector_tail
= mp
;
6352 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
6354 mp
->offset
= offset
;
6355 if (mp
->refcount
> 0)
6356 offset
+= mp
->fix_size
;
6358 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
6359 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
6365 /* Add a constant to the minipool for a backward reference. Returns the
6366 node added or NULL if the constant will not fit in this pool.
6368 Note that the code for insertion for a backwards reference can be
6369 somewhat confusing because the calculated offsets for each fix do
6370 not take into account the size of the pool (which is still under
6373 add_minipool_backward_ref (Mfix
*fix
)
6375 /* If set, min_mp is the last pool_entry that has a lower constraint
6376 than the one we are trying to add. */
6377 Mnode
*min_mp
= NULL
;
6378 /* This can be negative, since it is only a constraint. */
6379 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
6382 /* If we can't reach the current pool from this insn, or if we can't
6383 insert this entry at the end of the pool without pushing other
6384 fixes out of range, then we don't try. This ensures that we
6385 can't fail later on. */
6386 if (min_address
>= minipool_barrier
->address
6387 || (minipool_vector_tail
->min_address
+ fix
->fix_size
6388 >= minipool_barrier
->address
))
6391 /* Scan the pool to see if a constant with the same value has
6392 already been added. While we are doing this, also note the
6393 location where we must insert the constant if it doesn't already
6395 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
6397 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
6398 && fix
->mode
== mp
->mode
6399 && (GET_CODE (fix
->value
) != CODE_LABEL
6400 || (CODE_LABEL_NUMBER (fix
->value
)
6401 == CODE_LABEL_NUMBER (mp
->value
)))
6402 && rtx_equal_p (fix
->value
, mp
->value
)
6403 /* Check that there is enough slack to move this entry to the
6404 end of the table (this is conservative). */
6406 > (minipool_barrier
->address
6407 + minipool_vector_tail
->offset
6408 + minipool_vector_tail
->fix_size
)))
6411 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
6415 mp
->min_address
+= fix
->fix_size
;
6418 /* Note the insertion point if necessary. */
6419 if (mp
->min_address
< min_address
)
6421 /* For now, we do not allow the insertion of 8-byte alignment
6422 requiring nodes anywhere but at the start of the pool. */
6423 if (TARGET_REALLY_IWMMXT
&& fix
->fix_size
== 8 && mp
->fix_size
!= 8)
6428 else if (mp
->max_address
6429 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
6431 /* Inserting before this entry would push the fix beyond
6432 its maximum address (which can happen if we have
6433 re-located a forwards fix); force the new fix to come
6436 min_address
= mp
->min_address
+ fix
->fix_size
;
6438 /* If we are inserting an 8-bytes aligned quantity and
6439 we have not already found an insertion point, then
6440 make sure that all such 8-byte aligned quantities are
6441 placed at the start of the pool. */
6442 else if (TARGET_REALLY_IWMMXT
6444 && fix
->fix_size
== 8
6445 && mp
->fix_size
< 8)
6448 min_address
= mp
->min_address
+ fix
->fix_size
;
6453 /* We need to create a new entry. */
6454 mp
= xmalloc (sizeof (* mp
));
6455 mp
->fix_size
= fix
->fix_size
;
6456 mp
->mode
= fix
->mode
;
6457 mp
->value
= fix
->value
;
6459 mp
->max_address
= minipool_barrier
->address
+ 65536;
6461 mp
->min_address
= min_address
;
6466 mp
->next
= minipool_vector_head
;
6468 if (mp
->next
== NULL
)
6470 minipool_vector_tail
= mp
;
6471 minipool_vector_label
= gen_label_rtx ();
6474 mp
->next
->prev
= mp
;
6476 minipool_vector_head
= mp
;
6480 mp
->next
= min_mp
->next
;
6484 if (mp
->next
!= NULL
)
6485 mp
->next
->prev
= mp
;
6487 minipool_vector_tail
= mp
;
6490 /* Save the new entry. */
6498 /* Scan over the following entries and adjust their offsets. */
6499 while (mp
->next
!= NULL
)
6501 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
6502 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
6505 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
6507 mp
->next
->offset
= mp
->offset
;
6516 assign_minipool_offsets (Mfix
*barrier
)
6518 HOST_WIDE_INT offset
= 0;
6521 minipool_barrier
= barrier
;
6523 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
6525 mp
->offset
= offset
;
6527 if (mp
->refcount
> 0)
6528 offset
+= mp
->fix_size
;
6532 /* Output the literal table */
6534 dump_minipool (rtx scan
)
6540 if (TARGET_REALLY_IWMMXT
)
6541 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
6542 if (mp
->refcount
> 0 && mp
->fix_size
== 8)
6549 fprintf (rtl_dump_file
,
6550 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
6551 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
6553 scan
= emit_label_after (gen_label_rtx (), scan
);
6554 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
6555 scan
= emit_label_after (minipool_vector_label
, scan
);
6557 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
6559 if (mp
->refcount
> 0)
6563 fprintf (rtl_dump_file
,
6564 ";; Offset %u, min %ld, max %ld ",
6565 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
6566 (unsigned long) mp
->max_address
);
6567 arm_print_value (rtl_dump_file
, mp
->value
);
6568 fputc ('\n', rtl_dump_file
);
6571 switch (mp
->fix_size
)
6573 #ifdef HAVE_consttable_1
6575 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
6579 #ifdef HAVE_consttable_2
6581 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
6585 #ifdef HAVE_consttable_4
6587 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
6591 #ifdef HAVE_consttable_8
6593 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
6607 minipool_vector_head
= minipool_vector_tail
= NULL
;
6608 scan
= emit_insn_after (gen_consttable_end (), scan
);
6609 scan
= emit_barrier_after (scan
);
6612 /* Return the cost of forcibly inserting a barrier after INSN. */
6614 arm_barrier_cost (rtx insn
)
6616 /* Basing the location of the pool on the loop depth is preferable,
6617 but at the moment, the basic block information seems to be
6618 corrupt by this stage of the compilation. */
6620 rtx next
= next_nonnote_insn (insn
);
6622 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
6625 switch (GET_CODE (insn
))
6628 /* It will always be better to place the table before the label, rather
6637 return base_cost
- 10;
6640 return base_cost
+ 10;
6644 /* Find the best place in the insn stream in the range
6645 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
6646 Create the barrier by inserting a jump and add a new fix entry for
6649 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
6651 HOST_WIDE_INT count
= 0;
6653 rtx from
= fix
->insn
;
6654 rtx selected
= from
;
6656 HOST_WIDE_INT selected_address
;
6658 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
6659 rtx label
= gen_label_rtx ();
6661 selected_cost
= arm_barrier_cost (from
);
6662 selected_address
= fix
->address
;
6664 while (from
&& count
< max_count
)
6669 /* This code shouldn't have been called if there was a natural barrier
6671 if (GET_CODE (from
) == BARRIER
)
6674 /* Count the length of this insn. */
6675 count
+= get_attr_length (from
);
6677 /* If there is a jump table, add its length. */
6678 tmp
= is_jump_table (from
);
6681 count
+= get_jump_table_size (tmp
);
6683 /* Jump tables aren't in a basic block, so base the cost on
6684 the dispatch insn. If we select this location, we will
6685 still put the pool after the table. */
6686 new_cost
= arm_barrier_cost (from
);
6688 if (count
< max_count
&& new_cost
<= selected_cost
)
6691 selected_cost
= new_cost
;
6692 selected_address
= fix
->address
+ count
;
6695 /* Continue after the dispatch table. */
6696 from
= NEXT_INSN (tmp
);
6700 new_cost
= arm_barrier_cost (from
);
6702 if (count
< max_count
&& new_cost
<= selected_cost
)
6705 selected_cost
= new_cost
;
6706 selected_address
= fix
->address
+ count
;
6709 from
= NEXT_INSN (from
);
6712 /* Create a new JUMP_INSN that branches around a barrier. */
6713 from
= emit_jump_insn_after (gen_jump (label
), selected
);
6714 JUMP_LABEL (from
) = label
;
6715 barrier
= emit_barrier_after (from
);
6716 emit_label_after (label
, barrier
);
6718 /* Create a minipool barrier entry for the new barrier. */
6719 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
6720 new_fix
->insn
= barrier
;
6721 new_fix
->address
= selected_address
;
6722 new_fix
->next
= fix
->next
;
6723 fix
->next
= new_fix
;
6728 /* Record that there is a natural barrier in the insn stream at
6731 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
6733 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
6736 fix
->address
= address
;
6739 if (minipool_fix_head
!= NULL
)
6740 minipool_fix_tail
->next
= fix
;
6742 minipool_fix_head
= fix
;
6744 minipool_fix_tail
= fix
;
6747 /* Record INSN, which will need fixing up to load a value from the
6748 minipool. ADDRESS is the offset of the insn since the start of the
6749 function; LOC is a pointer to the part of the insn which requires
6750 fixing; VALUE is the constant that must be loaded, which is of type
6753 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
6754 enum machine_mode mode
, rtx value
)
6756 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
6758 #ifdef AOF_ASSEMBLER
6759 /* PIC symbol references need to be converted into offsets into the
6761 /* XXX This shouldn't be done here. */
6762 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
6763 value
= aof_pic_entry (value
);
6764 #endif /* AOF_ASSEMBLER */
6767 fix
->address
= address
;
6770 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
6772 fix
->forwards
= get_attr_pool_range (insn
);
6773 fix
->backwards
= get_attr_neg_pool_range (insn
);
6774 fix
->minipool
= NULL
;
6776 /* If an insn doesn't have a range defined for it, then it isn't
6777 expecting to be reworked by this code. Better to abort now than
6778 to generate duff assembly code. */
6779 if (fix
->forwards
== 0 && fix
->backwards
== 0)
6782 /* With iWMMXt enabled, the pool is aligned to an 8-byte boundary.
6783 So there might be an empty word before the start of the pool.
6784 Hence we reduce the forward range by 4 to allow for this
6786 if (TARGET_REALLY_IWMMXT
&& fix
->fix_size
== 8)
6791 fprintf (rtl_dump_file
,
6792 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
6793 GET_MODE_NAME (mode
),
6794 INSN_UID (insn
), (unsigned long) address
,
6795 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
6796 arm_print_value (rtl_dump_file
, fix
->value
);
6797 fprintf (rtl_dump_file
, "\n");
6800 /* Add it to the chain of fixes. */
6803 if (minipool_fix_head
!= NULL
)
6804 minipool_fix_tail
->next
= fix
;
6806 minipool_fix_head
= fix
;
6808 minipool_fix_tail
= fix
;
6811 /* Scan INSN and note any of its operands that need fixing.
6812 If DO_PUSHES is false we do not actually push any of the fixups
6813 needed. The function returns TRUE is any fixups were needed/pushed.
6814 This is used by arm_memory_load_p() which needs to know about loads
6815 of constants that will be converted into minipool loads. */
6817 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
6819 bool result
= false;
6822 extract_insn (insn
);
6824 if (!constrain_operands (1))
6825 fatal_insn_not_found (insn
);
6827 /* Fill in recog_op_alt with information about the constraints of this insn. */
6828 preprocess_constraints ();
6830 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
6832 /* Things we need to fix can only occur in inputs. */
6833 if (recog_data
.operand_type
[opno
] != OP_IN
)
6836 /* If this alternative is a memory reference, then any mention
6837 of constants in this alternative is really to fool reload
6838 into allowing us to accept one there. We need to fix them up
6839 now so that we output the right code. */
6840 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
6842 rtx op
= recog_data
.operand
[opno
];
6844 if (CONSTANT_P (op
))
6847 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
6848 recog_data
.operand_mode
[opno
], op
);
6851 else if (GET_CODE (op
) == MEM
6852 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
6853 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
6856 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
6857 recog_data
.operand_mode
[opno
],
6858 get_pool_constant (XEXP (op
, 0)));
6868 /* Gcc puts the pool in the wrong place for ARM, since we can only
6869 load addresses a limited distance around the pc. We do some
6870 special munging to move the constant pool values to the correct
6871 point in the code. */
6876 HOST_WIDE_INT address
= 0;
6879 minipool_fix_head
= minipool_fix_tail
= NULL
;
6881 /* The first insn must always be a note, or the code below won't
6882 scan it properly. */
6883 insn
= get_insns ();
6884 if (GET_CODE (insn
) != NOTE
)
6887 /* Scan all the insns and record the operands that will need fixing. */
6888 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
6890 if (TARGET_CIRRUS_FIX_INVALID_INSNS
6891 && (arm_cirrus_insn_p (insn
)
6892 || GET_CODE (insn
) == JUMP_INSN
6893 || arm_memory_load_p (insn
)))
6894 cirrus_reorg (insn
);
6896 if (GET_CODE (insn
) == BARRIER
)
6897 push_minipool_barrier (insn
, address
);
6898 else if (INSN_P (insn
))
6902 note_invalid_constants (insn
, address
, true);
6903 address
+= get_attr_length (insn
);
6905 /* If the insn is a vector jump, add the size of the table
6906 and skip the table. */
6907 if ((table
= is_jump_table (insn
)) != NULL
)
6909 address
+= get_jump_table_size (table
);
6915 fix
= minipool_fix_head
;
6917 /* Now scan the fixups and perform the required changes. */
6922 Mfix
* last_added_fix
;
6923 Mfix
* last_barrier
= NULL
;
6926 /* Skip any further barriers before the next fix. */
6927 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
6930 /* No more fixes. */
6934 last_added_fix
= NULL
;
6936 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
6938 if (GET_CODE (ftmp
->insn
) == BARRIER
)
6940 if (ftmp
->address
>= minipool_vector_head
->max_address
)
6943 last_barrier
= ftmp
;
6945 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
6948 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
6951 /* If we found a barrier, drop back to that; any fixes that we
6952 could have reached but come after the barrier will now go in
6953 the next mini-pool. */
6954 if (last_barrier
!= NULL
)
6956 /* Reduce the refcount for those fixes that won't go into this
6958 for (fdel
= last_barrier
->next
;
6959 fdel
&& fdel
!= ftmp
;
6962 fdel
->minipool
->refcount
--;
6963 fdel
->minipool
= NULL
;
6966 ftmp
= last_barrier
;
6970 /* ftmp is first fix that we can't fit into this pool and
6971 there no natural barriers that we could use. Insert a
6972 new barrier in the code somewhere between the previous
6973 fix and this one, and arrange to jump around it. */
6974 HOST_WIDE_INT max_address
;
6976 /* The last item on the list of fixes must be a barrier, so
6977 we can never run off the end of the list of fixes without
6978 last_barrier being set. */
6982 max_address
= minipool_vector_head
->max_address
;
6983 /* Check that there isn't another fix that is in range that
6984 we couldn't fit into this pool because the pool was
6985 already too large: we need to put the pool before such an
6987 if (ftmp
->address
< max_address
)
6988 max_address
= ftmp
->address
;
6990 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
6993 assign_minipool_offsets (last_barrier
);
6997 if (GET_CODE (ftmp
->insn
) != BARRIER
6998 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
7005 /* Scan over the fixes we have identified for this pool, fixing them
7006 up and adding the constants to the pool itself. */
7007 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
7008 this_fix
= this_fix
->next
)
7009 if (GET_CODE (this_fix
->insn
) != BARRIER
)
7012 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
7013 minipool_vector_label
),
7014 this_fix
->minipool
->offset
);
7015 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
7018 dump_minipool (last_barrier
->insn
);
7022 /* From now on we must synthesize any constants that we can't handle
7023 directly. This can happen if the RTL gets split during final
7024 instruction generation. */
7025 after_arm_reorg
= 1;
7027 /* Free the minipool memory. */
7028 obstack_free (&minipool_obstack
, minipool_startobj
);
7031 /* Routines to output assembly language. */
7033 /* If the rtx is the correct value then return the string of the number.
7034 In this way we can ensure that valid double constants are generated even
7035 when cross compiling. */
7037 fp_immediate_constant (rtx x
)
7042 if (!fpa_consts_inited
)
7045 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
7046 for (i
= 0; i
< 8; i
++)
7047 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
7048 return strings_fpa
[i
];
7053 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7055 fp_const_from_val (REAL_VALUE_TYPE
*r
)
7059 if (!fpa_consts_inited
)
7062 for (i
= 0; i
< 8; i
++)
7063 if (REAL_VALUES_EQUAL (*r
, values_fpa
[i
]))
7064 return strings_fpa
[i
];
7069 /* Output the operands of a LDM/STM instruction to STREAM.
7070 MASK is the ARM register set mask of which only bits 0-15 are important.
7071 REG is the base register, either the frame pointer or the stack pointer,
7072 INSTR is the possibly suffixed load or store instruction. */
7074 print_multi_reg (FILE *stream
, const char *instr
, int reg
, int mask
)
7077 int not_first
= FALSE
;
7079 fputc ('\t', stream
);
7080 asm_fprintf (stream
, instr
, reg
);
7081 fputs (", {", stream
);
7083 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
7084 if (mask
& (1 << i
))
7087 fprintf (stream
, ", ");
7089 asm_fprintf (stream
, "%r", i
);
7093 fprintf (stream
, "}");
7095 /* Add a ^ character for the 26-bit ABI, but only if we were loading
7096 the PC. Otherwise we would generate an UNPREDICTABLE instruction.
7097 Strictly speaking the instruction would be unpredicatble only if
7098 we were writing back the base register as well, but since we never
7099 want to generate an LDM type 2 instruction (register bank switching)
7100 which is what you get if the PC is not being loaded, we do not need
7101 to check for writeback. */
7102 if (! TARGET_APCS_32
7103 && ((mask
& (1 << PC_REGNUM
)) != 0))
7104 fprintf (stream
, "^");
7106 fprintf (stream
, "\n");
7109 /* Output a 'call' insn. */
7111 output_call (rtx
*operands
)
7113 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
7115 if (REGNO (operands
[0]) == LR_REGNUM
)
7117 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
7118 output_asm_insn ("mov%?\t%0, %|lr", operands
);
7121 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
7123 if (TARGET_INTERWORK
)
7124 output_asm_insn ("bx%?\t%0", operands
);
7126 output_asm_insn ("mov%?\t%|pc, %0", operands
);
7131 /* Output a 'call' insn that is a reference in memory. */
7133 output_call_mem (rtx
*operands
)
7135 if (TARGET_INTERWORK
)
7137 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
7138 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
7139 output_asm_insn ("bx%?\t%|ip", operands
);
7141 else if (regno_use_in (LR_REGNUM
, operands
[0]))
7143 /* LR is used in the memory address. We load the address in the
7144 first instruction. It's safe to use IP as the target of the
7145 load since the call will kill it anyway. */
7146 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
7147 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
7148 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
7152 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
7153 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
7160 /* Output a move from arm registers to an fpa registers.
7161 OPERANDS[0] is an fpa register.
7162 OPERANDS[1] is the first registers of an arm register pair. */
7164 output_mov_long_double_fpa_from_arm (rtx
*operands
)
7166 int arm_reg0
= REGNO (operands
[1]);
7169 if (arm_reg0
== IP_REGNUM
)
7172 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
7173 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
7174 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
7176 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
7177 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
7182 /* Output a move from an fpa register to arm registers.
7183 OPERANDS[0] is the first registers of an arm register pair.
7184 OPERANDS[1] is an fpa register. */
7186 output_mov_long_double_arm_from_fpa (rtx
*operands
)
7188 int arm_reg0
= REGNO (operands
[0]);
7191 if (arm_reg0
== IP_REGNUM
)
7194 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
7195 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
7196 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
7198 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
7199 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
7203 /* Output a move from arm registers to arm registers of a long double
7204 OPERANDS[0] is the destination.
7205 OPERANDS[1] is the source. */
7207 output_mov_long_double_arm_from_arm (rtx
*operands
)
7209 /* We have to be careful here because the two might overlap. */
7210 int dest_start
= REGNO (operands
[0]);
7211 int src_start
= REGNO (operands
[1]);
7215 if (dest_start
< src_start
)
7217 for (i
= 0; i
< 3; i
++)
7219 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
7220 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
7221 output_asm_insn ("mov%?\t%0, %1", ops
);
7226 for (i
= 2; i
>= 0; i
--)
7228 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
7229 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
7230 output_asm_insn ("mov%?\t%0, %1", ops
);
7238 /* Output a move from arm registers to an fpa registers.
7239 OPERANDS[0] is an fpa register.
7240 OPERANDS[1] is the first registers of an arm register pair. */
7242 output_mov_double_fpa_from_arm (rtx
*operands
)
7244 int arm_reg0
= REGNO (operands
[1]);
7247 if (arm_reg0
== IP_REGNUM
)
7250 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
7251 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
7252 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
7253 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
7257 /* Output a move from an fpa register to arm registers.
7258 OPERANDS[0] is the first registers of an arm register pair.
7259 OPERANDS[1] is an fpa register. */
7261 output_mov_double_arm_from_fpa (rtx
*operands
)
7263 int arm_reg0
= REGNO (operands
[0]);
7266 if (arm_reg0
== IP_REGNUM
)
7269 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
7270 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
7271 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
7272 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
7276 /* Output a move between double words.
7277 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
7278 or MEM<-REG and all MEMs must be offsettable addresses. */
7280 output_move_double (rtx
*operands
)
7282 enum rtx_code code0
= GET_CODE (operands
[0]);
7283 enum rtx_code code1
= GET_CODE (operands
[1]);
7288 int reg0
= REGNO (operands
[0]);
7290 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
7294 int reg1
= REGNO (operands
[1]);
7295 if (reg1
== IP_REGNUM
)
7298 /* Ensure the second source is not overwritten. */
7299 if (reg1
== reg0
+ (WORDS_BIG_ENDIAN
? -1 : 1))
7300 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands
);
7302 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands
);
7304 else if (code1
== CONST_VECTOR
)
7306 HOST_WIDE_INT hint
= 0;
7308 switch (GET_MODE (operands
[1]))
7311 otherops
[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands
[1], 1)));
7312 operands
[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands
[1], 0)));
7316 if (BYTES_BIG_ENDIAN
)
7318 hint
= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
7320 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
7324 hint
= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
7326 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
7329 otherops
[1] = GEN_INT (hint
);
7332 if (BYTES_BIG_ENDIAN
)
7334 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
7336 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
7340 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
7342 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
7345 operands
[1] = GEN_INT (hint
);
7349 if (BYTES_BIG_ENDIAN
)
7351 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 4));
7353 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 5));
7355 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 6));
7357 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 7));
7361 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 7));
7363 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 6));
7365 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 5));
7367 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 4));
7370 otherops
[1] = GEN_INT (hint
);
7373 if (BYTES_BIG_ENDIAN
)
7375 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
7377 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
7379 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
7381 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
7385 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
7387 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
7389 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
7391 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
7394 operands
[1] = GEN_INT (hint
);
7400 output_mov_immediate (operands
);
7401 output_mov_immediate (otherops
);
7403 else if (code1
== CONST_DOUBLE
)
7405 if (GET_MODE (operands
[1]) == DFmode
)
7410 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
7411 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
7412 otherops
[1] = GEN_INT (l
[1]);
7413 operands
[1] = GEN_INT (l
[0]);
7415 else if (GET_MODE (operands
[1]) != VOIDmode
)
7417 else if (WORDS_BIG_ENDIAN
)
7419 otherops
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
7420 operands
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
7424 otherops
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
7425 operands
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
7428 output_mov_immediate (operands
);
7429 output_mov_immediate (otherops
);
7431 else if (code1
== CONST_INT
)
7433 #if HOST_BITS_PER_WIDE_INT > 32
7434 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
7435 what the upper word is. */
7436 if (WORDS_BIG_ENDIAN
)
7438 otherops
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
7439 operands
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
7443 otherops
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
7444 operands
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
7447 /* Sign extend the intval into the high-order word. */
7448 if (WORDS_BIG_ENDIAN
)
7450 otherops
[1] = operands
[1];
7451 operands
[1] = (INTVAL (operands
[1]) < 0
7452 ? constm1_rtx
: const0_rtx
);
7455 otherops
[1] = INTVAL (operands
[1]) < 0 ? constm1_rtx
: const0_rtx
;
7457 output_mov_immediate (otherops
);
7458 output_mov_immediate (operands
);
7460 else if (code1
== MEM
)
7462 switch (GET_CODE (XEXP (operands
[1], 0)))
7465 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
7469 abort (); /* Should never happen now. */
7473 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
7477 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
7481 abort (); /* Should never happen now. */
7486 output_asm_insn ("adr%?\t%0, %1", operands
);
7487 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
7491 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
7492 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
7494 otherops
[0] = operands
[0];
7495 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
7496 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
7498 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
7500 if (GET_CODE (otherops
[2]) == CONST_INT
)
7502 switch ((int) INTVAL (otherops
[2]))
7505 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
7508 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
7511 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
7515 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
7516 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
7518 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
7521 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
7524 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
7526 return "ldm%?ia\t%0, %M0";
7530 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
7531 /* Take care of overlapping base/data reg. */
7532 if (reg_mentioned_p (operands
[0], operands
[1]))
7534 output_asm_insn ("ldr%?\t%0, %1", otherops
);
7535 output_asm_insn ("ldr%?\t%0, %1", operands
);
7539 output_asm_insn ("ldr%?\t%0, %1", operands
);
7540 output_asm_insn ("ldr%?\t%0, %1", otherops
);
7546 abort (); /* Constraints should prevent this. */
7548 else if (code0
== MEM
&& code1
== REG
)
7550 if (REGNO (operands
[1]) == IP_REGNUM
)
7553 switch (GET_CODE (XEXP (operands
[0], 0)))
7556 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
7560 abort (); /* Should never happen now. */
7564 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
7568 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
7572 abort (); /* Should never happen now. */
7576 if (GET_CODE (XEXP (XEXP (operands
[0], 0), 1)) == CONST_INT
)
7578 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
7581 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
7585 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
7589 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
7596 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
7597 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
7598 output_asm_insn ("str%?\t%1, %0", operands
);
7599 output_asm_insn ("str%?\t%1, %0", otherops
);
7603 /* Constraints should prevent this. */
7610 /* Output an arbitrary MOV reg, #n.
7611 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
7613 output_mov_immediate (rtx
*operands
)
7615 HOST_WIDE_INT n
= INTVAL (operands
[1]);
7617 /* Try to use one MOV. */
7618 if (const_ok_for_arm (n
))
7619 output_asm_insn ("mov%?\t%0, %1", operands
);
7621 /* Try to use one MVN. */
7622 else if (const_ok_for_arm (~n
))
7624 operands
[1] = GEN_INT (~n
);
7625 output_asm_insn ("mvn%?\t%0, %1", operands
);
7632 /* If all else fails, make it out of ORRs or BICs as appropriate. */
7633 for (i
= 0; i
< 32; i
++)
7637 if (n_ones
> 16) /* Shorter to use MVN with BIC in this case. */
7638 output_multi_immediate (operands
, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n
);
7640 output_multi_immediate (operands
, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n
);
7646 /* Output an ADD r, s, #n where n may be too big for one instruction.
7647 If adding zero to one register, output nothing. */
7649 output_add_immediate (rtx
*operands
)
7651 HOST_WIDE_INT n
= INTVAL (operands
[2]);
7653 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
7656 output_multi_immediate (operands
,
7657 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
7660 output_multi_immediate (operands
,
7661 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
7668 /* Output a multiple immediate operation.
7669 OPERANDS is the vector of operands referred to in the output patterns.
7670 INSTR1 is the output pattern to use for the first constant.
7671 INSTR2 is the output pattern to use for subsequent constants.
7672 IMMED_OP is the index of the constant slot in OPERANDS.
7673 N is the constant value. */
7675 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
7676 int immed_op
, HOST_WIDE_INT n
)
7678 #if HOST_BITS_PER_WIDE_INT > 32
7684 /* Quick and easy output. */
7685 operands
[immed_op
] = const0_rtx
;
7686 output_asm_insn (instr1
, operands
);
7691 const char * instr
= instr1
;
7693 /* Note that n is never zero here (which would give no output). */
7694 for (i
= 0; i
< 32; i
+= 2)
7698 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
7699 output_asm_insn (instr
, operands
);
7709 /* Return the appropriate ARM instruction for the operation code.
7710 The returned result should not be overwritten. OP is the rtx of the
7711 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
7714 arithmetic_instr (rtx op
, int shift_first_arg
)
7716 switch (GET_CODE (op
))
7722 return shift_first_arg
? "rsb" : "sub";
7738 /* Ensure valid constant shifts and return the appropriate shift mnemonic
7739 for the operation code. The returned result should not be overwritten.
7740 OP is the rtx code of the shift.
7741 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
7744 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
7747 enum rtx_code code
= GET_CODE (op
);
7749 if (GET_CODE (XEXP (op
, 1)) == REG
|| GET_CODE (XEXP (op
, 1)) == SUBREG
)
7751 else if (GET_CODE (XEXP (op
, 1)) == CONST_INT
)
7752 *amountp
= INTVAL (XEXP (op
, 1));
7775 /* We never have to worry about the amount being other than a
7776 power of 2, since this case can never be reloaded from a reg. */
7778 *amountp
= int_log2 (*amountp
);
7789 /* This is not 100% correct, but follows from the desire to merge
7790 multiplication by a power of 2 with the recognizer for a
7791 shift. >=32 is not a valid shift for "asl", so we must try and
7792 output a shift that produces the correct arithmetical result.
7793 Using lsr #32 is identical except for the fact that the carry bit
7794 is not set correctly if we set the flags; but we never use the
7795 carry bit from such an operation, so we can ignore that. */
7796 if (code
== ROTATERT
)
7797 /* Rotate is just modulo 32. */
7799 else if (*amountp
!= (*amountp
& 31))
7806 /* Shifts of 0 are no-ops. */
7814 /* Obtain the shift from the POWER of two. */
7816 static HOST_WIDE_INT
7817 int_log2 (HOST_WIDE_INT power
)
7819 HOST_WIDE_INT shift
= 0;
7821 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
7831 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
7832 /bin/as is horribly restrictive. */
7833 #define MAX_ASCII_LEN 51
7836 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
7841 fputs ("\t.ascii\t\"", stream
);
7843 for (i
= 0; i
< len
; i
++)
7847 if (len_so_far
>= MAX_ASCII_LEN
)
7849 fputs ("\"\n\t.ascii\t\"", stream
);
7856 fputs ("\\t", stream
);
7861 fputs ("\\f", stream
);
7866 fputs ("\\b", stream
);
7871 fputs ("\\r", stream
);
7875 case TARGET_NEWLINE
:
7876 fputs ("\\n", stream
);
7878 if ((c
>= ' ' && c
<= '~')
7880 /* This is a good place for a line break. */
7881 len_so_far
= MAX_ASCII_LEN
;
7888 putc ('\\', stream
);
7893 if (c
>= ' ' && c
<= '~')
7900 fprintf (stream
, "\\%03o", c
);
7907 fputs ("\"\n", stream
);
7910 /* Compute the register sabe mask for registers 0 through 12
7911 inclusive. This code is used by both arm_compute_save_reg_mask
7912 and arm_compute_initial_elimination_offset. */
7913 static unsigned long
7914 arm_compute_save_reg0_reg12_mask (void)
7916 unsigned long func_type
= arm_current_func_type ();
7917 unsigned int save_reg_mask
= 0;
7920 if (IS_INTERRUPT (func_type
))
7922 unsigned int max_reg
;
7923 /* Interrupt functions must not corrupt any registers,
7924 even call clobbered ones. If this is a leaf function
7925 we can just examine the registers used by the RTL, but
7926 otherwise we have to assume that whatever function is
7927 called might clobber anything, and so we have to save
7928 all the call-clobbered registers as well. */
7929 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
7930 /* FIQ handlers have registers r8 - r12 banked, so
7931 we only need to check r0 - r7, Normal ISRs only
7932 bank r14 and r15, so we must check up to r12.
7933 r13 is the stack pointer which is always preserved,
7934 so we do not need to consider it here. */
7939 for (reg
= 0; reg
<= max_reg
; reg
++)
7940 if (regs_ever_live
[reg
]
7941 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
7942 save_reg_mask
|= (1 << reg
);
7946 /* In the normal case we only need to save those registers
7947 which are call saved and which are used by this function. */
7948 for (reg
= 0; reg
<= 10; reg
++)
7949 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
7950 save_reg_mask
|= (1 << reg
);
7952 /* Handle the frame pointer as a special case. */
7953 if (! TARGET_APCS_FRAME
7954 && ! frame_pointer_needed
7955 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
7956 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
7957 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
7959 /* If we aren't loading the PIC register,
7960 don't stack it even though it may be live. */
7962 && ! TARGET_SINGLE_PIC_BASE
7963 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
7964 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
7967 return save_reg_mask
;
7970 /* Compute a bit mask of which registers need to be
7971 saved on the stack for the current function. */
7973 static unsigned long
7974 arm_compute_save_reg_mask (void)
7976 unsigned int save_reg_mask
= 0;
7977 unsigned long func_type
= arm_current_func_type ();
7979 if (IS_NAKED (func_type
))
7980 /* This should never really happen. */
7983 /* If we are creating a stack frame, then we must save the frame pointer,
7984 IP (which will hold the old stack pointer), LR and the PC. */
7985 if (frame_pointer_needed
)
7987 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
7992 /* Volatile functions do not return, so there
7993 is no need to save any other registers. */
7994 if (IS_VOLATILE (func_type
))
7995 return save_reg_mask
;
7997 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
7999 /* Decide if we need to save the link register.
8000 Interrupt routines have their own banked link register,
8001 so they never need to save it.
8002 Otherwise if we do not use the link register we do not need to save
8003 it. If we are pushing other registers onto the stack however, we
8004 can save an instruction in the epilogue by pushing the link register
8005 now and then popping it back into the PC. This incurs extra memory
8006 accesses though, so we only do it when optimizing for size, and only
8007 if we know that we will not need a fancy return sequence. */
8008 if (regs_ever_live
[LR_REGNUM
]
8011 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
))
8012 save_reg_mask
|= 1 << LR_REGNUM
;
8014 if (cfun
->machine
->lr_save_eliminated
)
8015 save_reg_mask
&= ~ (1 << LR_REGNUM
);
8017 if (TARGET_REALLY_IWMMXT
8018 && ((bit_count (save_reg_mask
)
8019 + ARM_NUM_INTS (current_function_pretend_args_size
)) % 2) != 0)
8023 /* The total number of registers that are going to be pushed
8024 onto the stack is odd. We need to ensure that the stack
8025 is 64-bit aligned before we start to save iWMMXt registers,
8026 and also before we start to create locals. (A local variable
8027 might be a double or long long which we will load/store using
8028 an iWMMXt instruction). Therefore we need to push another
8029 ARM register, so that the stack will be 64-bit aligned. We
8030 try to avoid using the arg registers (r0 -r3) as they might be
8031 used to pass values in a tail call. */
8032 for (reg
= 4; reg
<= 12; reg
++)
8033 if ((save_reg_mask
& (1 << reg
)) == 0)
8037 save_reg_mask
|= (1 << reg
);
8040 cfun
->machine
->sibcall_blocked
= 1;
8041 save_reg_mask
|= (1 << 3);
8045 return save_reg_mask
;
8048 /* Generate a function exit sequence. If REALLY_RETURN is true, then do
8049 everything bar the final return instruction. */
8051 output_return_instruction (rtx operand
, int really_return
, int reverse
)
8053 char conditional
[10];
8056 unsigned long live_regs_mask
;
8057 unsigned long func_type
;
8059 func_type
= arm_current_func_type ();
8061 if (IS_NAKED (func_type
))
8064 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
8066 /* If this function was declared non-returning, and we have found a tail
8067 call, then we have to trust that the called function won't return. */
8072 /* Otherwise, trap an attempted return by aborting. */
8074 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
8076 assemble_external_libcall (ops
[1]);
8077 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
8083 if (current_function_calls_alloca
&& !really_return
)
8086 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
8088 return_used_this_function
= 1;
8090 live_regs_mask
= arm_compute_save_reg_mask ();
8094 const char * return_reg
;
8096 /* If we do not have any special requirements for function exit
8097 (eg interworking, or ISR) then we can load the return address
8098 directly into the PC. Otherwise we must load it into LR. */
8100 && ! TARGET_INTERWORK
)
8101 return_reg
= reg_names
[PC_REGNUM
];
8103 return_reg
= reg_names
[LR_REGNUM
];
8105 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
8106 /* There are two possible reasons for the IP register being saved.
8107 Either a stack frame was created, in which case IP contains the
8108 old stack pointer, or an ISR routine corrupted it. If this in an
8109 ISR routine then just restore IP, otherwise restore IP into SP. */
8110 if (! IS_INTERRUPT (func_type
))
8112 live_regs_mask
&= ~ (1 << IP_REGNUM
);
8113 live_regs_mask
|= (1 << SP_REGNUM
);
8116 /* On some ARM architectures it is faster to use LDR rather than
8117 LDM to load a single register. On other architectures, the
8118 cost is the same. In 26 bit mode, or for exception handlers,
8119 we have to use LDM to load the PC so that the CPSR is also
8121 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
8123 if (live_regs_mask
== (unsigned int)(1 << reg
))
8126 if (reg
<= LAST_ARM_REGNUM
8127 && (reg
!= LR_REGNUM
8129 || (TARGET_APCS_32
&& ! IS_INTERRUPT (func_type
))))
8131 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
8132 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
8139 /* Generate the load multiple instruction to restore the registers. */
8140 if (frame_pointer_needed
)
8141 sprintf (instr
, "ldm%sea\t%%|fp, {", conditional
);
8142 else if (live_regs_mask
& (1 << SP_REGNUM
))
8143 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
8145 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
8147 p
= instr
+ strlen (instr
);
8149 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
8150 if (live_regs_mask
& (1 << reg
))
8152 int l
= strlen (reg_names
[reg
]);
8158 memcpy (p
, ", ", 2);
8162 memcpy (p
, "%|", 2);
8163 memcpy (p
+ 2, reg_names
[reg
], l
);
8167 if (live_regs_mask
& (1 << LR_REGNUM
))
8169 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
8170 /* Decide if we need to add the ^ symbol to the end of the
8171 register list. This causes the saved condition codes
8172 register to be copied into the current condition codes
8173 register. We do the copy if we are conforming to the 32-bit
8174 ABI and this is an interrupt function, or if we are
8175 conforming to the 26-bit ABI. There is a special case for
8176 the 26-bit ABI however, which is if we are writing back the
8177 stack pointer but not loading the PC. In this case adding
8178 the ^ symbol would create a type 2 LDM instruction, where
8179 writeback is UNPREDICTABLE. We are safe in leaving the ^
8180 character off in this case however, since the actual return
8181 instruction will be a MOVS which will restore the CPSR. */
8182 if ((TARGET_APCS_32
&& IS_INTERRUPT (func_type
))
8183 || (! TARGET_APCS_32
&& really_return
))
8190 output_asm_insn (instr
, & operand
);
8192 /* See if we need to generate an extra instruction to
8193 perform the actual function return. */
8195 && func_type
!= ARM_FT_INTERWORKED
8196 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
8198 /* The return has already been handled
8199 by loading the LR into the PC. */
8206 switch ((int) ARM_FUNC_TYPE (func_type
))
8210 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
8213 case ARM_FT_INTERWORKED
:
8214 sprintf (instr
, "bx%s\t%%|lr", conditional
);
8217 case ARM_FT_EXCEPTION
:
8218 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
8222 /* ARMv5 implementations always provide BX, so interworking
8223 is the default unless APCS-26 is in use. */
8224 if ((insn_flags
& FL_ARCH5
) != 0 && TARGET_APCS_32
)
8225 sprintf (instr
, "bx%s\t%%|lr", conditional
);
8227 sprintf (instr
, "mov%s%s\t%%|pc, %%|lr",
8228 conditional
, TARGET_APCS_32
? "" : "s");
8232 output_asm_insn (instr
, & operand
);
8238 /* Write the function name into the code section, directly preceding
8239 the function prologue.
8241 Code will be output similar to this:
8243 .ascii "arm_poke_function_name", 0
8246 .word 0xff000000 + (t1 - t0)
8247 arm_poke_function_name
8249 stmfd sp!, {fp, ip, lr, pc}
8252 When performing a stack backtrace, code can inspect the value
8253 of 'pc' stored at 'fp' + 0. If the trace function then looks
8254 at location pc - 12 and the top 8 bits are set, then we know
8255 that there is a function name embedded immediately preceding this
8256 location and has length ((pc[-3]) & 0xff000000).
8258 We assume that pc is declared as a pointer to an unsigned long.
8260 It is of no benefit to output the function name if we are assembling
8261 a leaf function. These function types will not contain a stack
8262 backtrace structure, therefore it is not possible to determine the
8265 arm_poke_function_name (FILE *stream
, const char *name
)
8267 unsigned long alignlength
;
8268 unsigned long length
;
8271 length
= strlen (name
) + 1;
8272 alignlength
= ROUND_UP_WORD (length
);
8274 ASM_OUTPUT_ASCII (stream
, name
, length
);
8275 ASM_OUTPUT_ALIGN (stream
, 2);
8276 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
8277 assemble_aligned_integer (UNITS_PER_WORD
, x
);
8280 /* Place some comments into the assembler stream
8281 describing the current function. */
8283 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
8285 unsigned long func_type
;
8289 thumb_output_function_prologue (f
, frame_size
);
8294 if (arm_ccfsm_state
|| arm_target_insn
)
8297 func_type
= arm_current_func_type ();
8299 switch ((int) ARM_FUNC_TYPE (func_type
))
8304 case ARM_FT_INTERWORKED
:
8305 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
8307 case ARM_FT_EXCEPTION_HANDLER
:
8308 asm_fprintf (f
, "\t%@ C++ Exception Handler.\n");
8311 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
8314 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
8316 case ARM_FT_EXCEPTION
:
8317 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
8321 if (IS_NAKED (func_type
))
8322 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
8324 if (IS_VOLATILE (func_type
))
8325 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
8327 if (IS_NESTED (func_type
))
8328 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
8330 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
8331 current_function_args_size
,
8332 current_function_pretend_args_size
, frame_size
);
8334 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
8335 frame_pointer_needed
,
8336 cfun
->machine
->uses_anonymous_args
);
8338 if (cfun
->machine
->lr_save_eliminated
)
8339 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
8341 #ifdef AOF_ASSEMBLER
8343 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
8346 return_used_this_function
= 0;
8350 arm_output_epilogue (int really_return
)
8353 unsigned long saved_regs_mask
;
8354 unsigned long func_type
;
8355 /* Floats_offset is the offset from the "virtual" frame. In an APCS
8356 frame that is $fp + 4 for a non-variadic function. */
8357 int floats_offset
= 0;
8359 int frame_size
= arm_get_frame_size ();
8360 FILE * f
= asm_out_file
;
8361 rtx eh_ofs
= cfun
->machine
->eh_epilogue_sp_ofs
;
8362 unsigned int lrm_count
= 0;
8364 /* If we have already generated the return instruction
8365 then it is futile to generate anything else. */
8366 if (use_return_insn (FALSE
) && return_used_this_function
)
8369 func_type
= arm_current_func_type ();
8371 if (IS_NAKED (func_type
))
8372 /* Naked functions don't have epilogues. */
8375 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
8379 /* A volatile function should never return. Call abort. */
8380 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
8381 assemble_external_libcall (op
);
8382 output_asm_insn ("bl\t%a0", &op
);
8387 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
8389 /* If we are throwing an exception, then we really must
8390 be doing a return, so we can't tail-call. */
8393 saved_regs_mask
= arm_compute_save_reg_mask ();
8396 lrm_count
= bit_count (saved_regs_mask
);
8398 /* XXX We should adjust floats_offset for any anonymous args, and then
8399 re-adjust vfp_offset below to compensate. */
8401 /* Compute how far away the floats will be. */
8402 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
8403 if (saved_regs_mask
& (1 << reg
))
8406 if (frame_pointer_needed
)
8410 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
8412 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
8413 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8415 floats_offset
+= 12;
8416 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
8417 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
8422 int start_reg
= LAST_ARM_FP_REGNUM
;
8424 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
8426 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8428 floats_offset
+= 12;
8430 /* We can't unstack more than four registers at once. */
8431 if (start_reg
- reg
== 3)
8433 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
8434 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
8435 start_reg
= reg
- 1;
8440 if (reg
!= start_reg
)
8441 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
8442 reg
+ 1, start_reg
- reg
,
8443 FP_REGNUM
, floats_offset
- vfp_offset
);
8444 start_reg
= reg
- 1;
8448 /* Just in case the last register checked also needs unstacking. */
8449 if (reg
!= start_reg
)
8450 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
8451 reg
+ 1, start_reg
- reg
,
8452 FP_REGNUM
, floats_offset
- vfp_offset
);
8457 /* The frame pointer is guaranteed to be non-double-word aligned.
8458 This is because it is set to (old_stack_pointer - 4) and the
8459 old_stack_pointer was double word aligned. Thus the offset to
8460 the iWMMXt registers to be loaded must also be non-double-word
8461 sized, so that the resultant address *is* double-word aligned.
8462 We can ignore floats_offset since that was already included in
8463 the live_regs_mask. */
8464 lrm_count
+= (lrm_count
% 2 ? 2 : 1);
8466 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
8467 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8469 asm_fprintf (f
, "\twldrd\t%r, [%r, #-%d]\n",
8470 reg
, FP_REGNUM
, lrm_count
* 4);
8475 /* saved_regs_mask should contain the IP, which at the time of stack
8476 frame generation actually contains the old stack pointer. So a
8477 quick way to unwind the stack is just pop the IP register directly
8478 into the stack pointer. */
8479 if ((saved_regs_mask
& (1 << IP_REGNUM
)) == 0)
8481 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
8482 saved_regs_mask
|= (1 << SP_REGNUM
);
8484 /* There are two registers left in saved_regs_mask - LR and PC. We
8485 only need to restore the LR register (the return address), but to
8486 save time we can load it directly into the PC, unless we need a
8487 special function exit sequence, or we are not really returning. */
8488 if (really_return
&& ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
)
8489 /* Delete the LR from the register mask, so that the LR on
8490 the stack is loaded into the PC in the register mask. */
8491 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
8493 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
8495 print_multi_reg (f
, "ldmea\t%r", FP_REGNUM
, saved_regs_mask
);
8497 if (IS_INTERRUPT (func_type
))
8498 /* Interrupt handlers will have pushed the
8499 IP onto the stack, so restore it now. */
8500 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, 1 << IP_REGNUM
);
8504 /* Restore stack pointer if necessary. */
8505 if (frame_size
+ current_function_outgoing_args_size
!= 0)
8507 operands
[0] = operands
[1] = stack_pointer_rtx
;
8508 operands
[2] = GEN_INT (frame_size
8509 + current_function_outgoing_args_size
);
8510 output_add_immediate (operands
);
8513 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
8515 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
8516 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8517 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
8522 int start_reg
= FIRST_ARM_FP_REGNUM
;
8524 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
8526 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8528 if (reg
- start_reg
== 3)
8530 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
8531 start_reg
, SP_REGNUM
);
8532 start_reg
= reg
+ 1;
8537 if (reg
!= start_reg
)
8538 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
8539 start_reg
, reg
- start_reg
,
8542 start_reg
= reg
+ 1;
8546 /* Just in case the last register checked also needs unstacking. */
8547 if (reg
!= start_reg
)
8548 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
8549 start_reg
, reg
- start_reg
, SP_REGNUM
);
8553 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
8554 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8555 asm_fprintf (f
, "\twldrd\t%r, [%r, #+8]!\n", reg
, SP_REGNUM
);
8557 /* If we can, restore the LR into the PC. */
8558 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
8560 && current_function_pretend_args_size
== 0
8561 && saved_regs_mask
& (1 << LR_REGNUM
))
8563 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
8564 saved_regs_mask
|= (1 << PC_REGNUM
);
8567 /* Load the registers off the stack. If we only have one register
8568 to load use the LDR instruction - it is faster. */
8569 if (saved_regs_mask
== (1 << LR_REGNUM
))
8571 /* The exception handler ignores the LR, so we do
8572 not really need to load it off the stack. */
8574 asm_fprintf (f
, "\tadd\t%r, %r, #4\n", SP_REGNUM
, SP_REGNUM
);
8576 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
8578 else if (saved_regs_mask
)
8580 if (saved_regs_mask
& (1 << SP_REGNUM
))
8581 /* Note - write back to the stack register is not enabled
8582 (ie "ldmfd sp!..."). We know that the stack pointer is
8583 in the list of registers and if we add writeback the
8584 instruction becomes UNPREDICTABLE. */
8585 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
8587 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
8590 if (current_function_pretend_args_size
)
8592 /* Unwind the pre-pushed regs. */
8593 operands
[0] = operands
[1] = stack_pointer_rtx
;
8594 operands
[2] = GEN_INT (current_function_pretend_args_size
);
8595 output_add_immediate (operands
);
8600 || (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
8601 && current_function_pretend_args_size
== 0
8602 && saved_regs_mask
& (1 << PC_REGNUM
)))
8605 /* Generate the return instruction. */
8606 switch ((int) ARM_FUNC_TYPE (func_type
))
8608 case ARM_FT_EXCEPTION_HANDLER
:
8609 /* Even in 26-bit mode we do a mov (rather than a movs)
8610 because we don't have the PSR bits set in the address. */
8611 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, EXCEPTION_LR_REGNUM
);
8616 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
8619 case ARM_FT_EXCEPTION
:
8620 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
8623 case ARM_FT_INTERWORKED
:
8624 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
8628 if (frame_pointer_needed
)
8629 /* If we used the frame pointer then the return address
8630 will have been loaded off the stack directly into the
8631 PC, so there is no need to issue a MOV instruction
8634 else if (current_function_pretend_args_size
== 0
8635 && (saved_regs_mask
& (1 << LR_REGNUM
)))
8636 /* Similarly we may have been able to load LR into the PC
8637 even if we did not create a stack frame. */
8639 else if (TARGET_APCS_32
)
8640 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
8642 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
8650 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
8651 HOST_WIDE_INT frame_size
)
8655 /* ??? Probably not safe to set this here, since it assumes that a
8656 function will be emitted as assembly immediately after we generate
8657 RTL for it. This does not happen for inline functions. */
8658 return_used_this_function
= 0;
8662 /* We need to take into account any stack-frame rounding. */
8663 frame_size
= arm_get_frame_size ();
8665 if (use_return_insn (FALSE
)
8666 && return_used_this_function
8667 && (frame_size
+ current_function_outgoing_args_size
) != 0
8668 && !frame_pointer_needed
)
8671 /* Reset the ARM-specific per-function variables. */
8672 after_arm_reorg
= 0;
8676 /* Generate and emit an insn that we will recognize as a push_multi.
8677 Unfortunately, since this insn does not reflect very well the actual
8678 semantics of the operation, we need to annotate the insn for the benefit
8679 of DWARF2 frame unwind information. */
8681 emit_multi_reg_push (int mask
)
8688 int dwarf_par_index
;
8691 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
8692 if (mask
& (1 << i
))
8695 if (num_regs
== 0 || num_regs
> 16)
8698 /* We don't record the PC in the dwarf frame information. */
8699 num_dwarf_regs
= num_regs
;
8700 if (mask
& (1 << PC_REGNUM
))
8703 /* For the body of the insn we are going to generate an UNSPEC in
8704 parallel with several USEs. This allows the insn to be recognized
8705 by the push_multi pattern in the arm.md file. The insn looks
8706 something like this:
8709 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
8710 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
8711 (use (reg:SI 11 fp))
8712 (use (reg:SI 12 ip))
8713 (use (reg:SI 14 lr))
8714 (use (reg:SI 15 pc))
8717 For the frame note however, we try to be more explicit and actually
8718 show each register being stored into the stack frame, plus a (single)
8719 decrement of the stack pointer. We do it this way in order to be
8720 friendly to the stack unwinding code, which only wants to see a single
8721 stack decrement per instruction. The RTL we generate for the note looks
8722 something like this:
8725 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
8726 (set (mem:SI (reg:SI sp)) (reg:SI r4))
8727 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
8728 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
8729 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
8732 This sequence is used both by the code to support stack unwinding for
8733 exceptions handlers and the code to generate dwarf2 frame debugging. */
8735 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
8736 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
8737 dwarf_par_index
= 1;
8739 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
8741 if (mask
& (1 << i
))
8743 reg
= gen_rtx_REG (SImode
, i
);
8746 = gen_rtx_SET (VOIDmode
,
8747 gen_rtx_MEM (BLKmode
,
8748 gen_rtx_PRE_DEC (BLKmode
,
8749 stack_pointer_rtx
)),
8750 gen_rtx_UNSPEC (BLKmode
,
8756 tmp
= gen_rtx_SET (VOIDmode
,
8757 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
8759 RTX_FRAME_RELATED_P (tmp
) = 1;
8760 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
8768 for (j
= 1, i
++; j
< num_regs
; i
++)
8770 if (mask
& (1 << i
))
8772 reg
= gen_rtx_REG (SImode
, i
);
8774 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
8778 tmp
= gen_rtx_SET (VOIDmode
,
8779 gen_rtx_MEM (SImode
,
8780 plus_constant (stack_pointer_rtx
,
8783 RTX_FRAME_RELATED_P (tmp
) = 1;
8784 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
8791 par
= emit_insn (par
);
8793 tmp
= gen_rtx_SET (SImode
,
8795 gen_rtx_PLUS (SImode
,
8797 GEN_INT (-4 * num_regs
)));
8798 RTX_FRAME_RELATED_P (tmp
) = 1;
8799 XVECEXP (dwarf
, 0, 0) = tmp
;
8801 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8807 emit_sfm (int base_reg
, int count
)
8814 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8815 dwarf
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8817 reg
= gen_rtx_REG (XFmode
, base_reg
++);
8820 = gen_rtx_SET (VOIDmode
,
8821 gen_rtx_MEM (BLKmode
,
8822 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
8823 gen_rtx_UNSPEC (BLKmode
,
8827 = gen_rtx_SET (VOIDmode
,
8828 gen_rtx_MEM (XFmode
,
8829 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
8831 RTX_FRAME_RELATED_P (tmp
) = 1;
8832 XVECEXP (dwarf
, 0, count
- 1) = tmp
;
8834 for (i
= 1; i
< count
; i
++)
8836 reg
= gen_rtx_REG (XFmode
, base_reg
++);
8837 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
8839 tmp
= gen_rtx_SET (VOIDmode
,
8840 gen_rtx_MEM (XFmode
,
8841 gen_rtx_PRE_DEC (BLKmode
,
8842 stack_pointer_rtx
)),
8844 RTX_FRAME_RELATED_P (tmp
) = 1;
8845 XVECEXP (dwarf
, 0, count
- i
- 1) = tmp
;
8848 par
= emit_insn (par
);
8849 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8854 /* Compute the distance from register FROM to register TO.
8855 These can be the arg pointer (26), the soft frame pointer (25),
8856 the stack pointer (13) or the hard frame pointer (11).
8857 Typical stack layout looks like this:
8859 old stack pointer -> | |
8862 | | saved arguments for
8863 | | vararg functions
8866 hard FP & arg pointer -> | | \
8874 soft frame pointer -> | | /
8884 current stack pointer -> | | /
8887 For a given function some or all of these stack components
8888 may not be needed, giving rise to the possibility of
8889 eliminating some of the registers.
8891 The values returned by this function must reflect the behavior
8892 of arm_expand_prologue() and arm_compute_save_reg_mask().
8894 The sign of the number returned reflects the direction of stack
8895 growth, so the values are positive for all eliminations except
8896 from the soft frame pointer to the hard frame pointer. */
8898 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
8900 unsigned int local_vars
= arm_get_frame_size ();
8901 unsigned int outgoing_args
= current_function_outgoing_args_size
;
8902 unsigned int stack_frame
;
8903 unsigned int call_saved_registers
;
8904 unsigned long func_type
;
8906 func_type
= arm_current_func_type ();
8908 /* Volatile functions never return, so there is
8909 no need to save call saved registers. */
8910 call_saved_registers
= 0;
8911 if (! IS_VOLATILE (func_type
))
8913 unsigned int reg_mask
;
8916 /* Make sure that we compute which registers will be saved
8917 on the stack using the same algorithm that is used by
8918 the prologue creation code. */
8919 reg_mask
= arm_compute_save_reg_mask ();
8921 /* Now count the number of bits set in save_reg_mask.
8922 If we have already counted the registers in the stack
8923 frame, do not count them again. Non call-saved registers
8924 might be saved in the call-save area of the stack, if
8925 doing so will preserve the stack's alignment. Hence we
8926 must count them here. For each set bit we need 4 bytes
8928 if (frame_pointer_needed
)
8930 call_saved_registers
+= 4 * bit_count (reg_mask
);
8932 /* If the hard floating point registers are going to be
8933 used then they must be saved on the stack as well.
8934 Each register occupies 12 bytes of stack space. */
8935 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
8936 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
8937 call_saved_registers
+= 12;
8939 if (TARGET_REALLY_IWMMXT
)
8940 /* Check for the call-saved iWMMXt registers. */
8941 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
8942 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
8943 call_saved_registers
+= 8;
8946 /* The stack frame contains 4 registers - the old frame pointer,
8947 the old stack pointer, the return address and PC of the start
8949 stack_frame
= frame_pointer_needed
? 16 : 0;
8951 /* OK, now we have enough information to compute the distances.
8952 There must be an entry in these switch tables for each pair
8953 of registers in ELIMINABLE_REGS, even if some of the entries
8954 seem to be redundant or useless. */
8957 case ARG_POINTER_REGNUM
:
8960 case THUMB_HARD_FRAME_POINTER_REGNUM
:
8963 case FRAME_POINTER_REGNUM
:
8964 /* This is the reverse of the soft frame pointer
8965 to hard frame pointer elimination below. */
8966 if (call_saved_registers
== 0 && stack_frame
== 0)
8968 return (call_saved_registers
+ stack_frame
- 4);
8970 case ARM_HARD_FRAME_POINTER_REGNUM
:
8971 /* If there is no stack frame then the hard
8972 frame pointer and the arg pointer coincide. */
8973 if (stack_frame
== 0 && call_saved_registers
!= 0)
8975 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
8976 return (frame_pointer_needed
8977 && current_function_needs_context
8978 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
8980 case STACK_POINTER_REGNUM
:
8981 /* If nothing has been pushed on the stack at all
8982 then this will return -4. This *is* correct! */
8983 return call_saved_registers
+ stack_frame
+ local_vars
+ outgoing_args
- 4;
8990 case FRAME_POINTER_REGNUM
:
8993 case THUMB_HARD_FRAME_POINTER_REGNUM
:
8996 case ARM_HARD_FRAME_POINTER_REGNUM
:
8997 /* The hard frame pointer points to the top entry in the
8998 stack frame. The soft frame pointer to the bottom entry
8999 in the stack frame. If there is no stack frame at all,
9000 then they are identical. */
9001 if (call_saved_registers
== 0 && stack_frame
== 0)
9003 return - (call_saved_registers
+ stack_frame
- 4);
9005 case STACK_POINTER_REGNUM
:
9006 return local_vars
+ outgoing_args
;
9014 /* You cannot eliminate from the stack pointer.
9015 In theory you could eliminate from the hard frame
9016 pointer to the stack pointer, but this will never
9017 happen, since if a stack frame is not needed the
9018 hard frame pointer will never be used. */
9023 /* Calculate the size of the stack frame, taking into account any
9024 padding that is required to ensure stack-alignment. */
9026 arm_get_frame_size (void)
9030 int base_size
= ROUND_UP_WORD (get_frame_size ());
9032 unsigned long func_type
= arm_current_func_type ();
9041 /* We need to know if we are a leaf function. Unfortunately, it
9042 is possible to be called after start_sequence has been called,
9043 which causes get_insns to return the insns for the sequence,
9044 not the function, which will cause leaf_function_p to return
9045 the incorrect result.
9047 To work around this, we cache the computed frame size. This
9048 works because we will only be calling RTL expanders that need
9049 to know about leaf functions once reload has completed, and the
9050 frame size cannot be changed after that time, so we can safely
9051 use the cached value. */
9053 if (reload_completed
)
9054 return cfun
->machine
->frame_size
;
9056 leaf
= leaf_function_p ();
9058 /* A leaf function does not need any stack alignment if it has nothing
9060 if (leaf
&& base_size
== 0)
9062 cfun
->machine
->frame_size
= 0;
9066 /* We know that SP will be word aligned on entry, and we must
9067 preserve that condition at any subroutine call. But those are
9068 the only constraints. */
9070 /* Space for variadic functions. */
9071 if (current_function_pretend_args_size
)
9072 entry_size
+= current_function_pretend_args_size
;
9074 /* Space for saved registers. */
9075 entry_size
+= bit_count (arm_compute_save_reg_mask ()) * 4;
9077 /* Space for saved FPA registers. */
9078 if (! IS_VOLATILE (func_type
))
9080 for (regno
= FIRST_ARM_FP_REGNUM
; regno
<= LAST_ARM_FP_REGNUM
; regno
++)
9081 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
9085 if (TARGET_REALLY_IWMMXT
)
9087 /* Check for the call-saved iWMMXt registers. */
9088 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
9089 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
9093 if ((entry_size
+ base_size
+ current_function_outgoing_args_size
) & 7)
9095 if ((entry_size
+ base_size
+ current_function_outgoing_args_size
) & 7)
9098 cfun
->machine
->frame_size
= base_size
;
9103 /* Generate the prologue instructions for entry into an ARM function. */
9105 arm_expand_prologue (void)
9111 unsigned long live_regs_mask
;
9112 unsigned long func_type
;
9114 int saved_pretend_args
= 0;
9115 unsigned int args_to_push
;
9117 func_type
= arm_current_func_type ();
9119 /* Naked functions don't have prologues. */
9120 if (IS_NAKED (func_type
))
9123 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
9124 args_to_push
= current_function_pretend_args_size
;
9126 /* Compute which register we will have to save onto the stack. */
9127 live_regs_mask
= arm_compute_save_reg_mask ();
9129 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
9131 if (frame_pointer_needed
)
9133 if (IS_INTERRUPT (func_type
))
9135 /* Interrupt functions must not corrupt any registers.
9136 Creating a frame pointer however, corrupts the IP
9137 register, so we must push it first. */
9138 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
9140 /* Do not set RTX_FRAME_RELATED_P on this insn.
9141 The dwarf stack unwinding code only wants to see one
9142 stack decrement per function, and this is not it. If
9143 this instruction is labeled as being part of the frame
9144 creation sequence then dwarf2out_frame_debug_expr will
9145 abort when it encounters the assignment of IP to FP
9146 later on, since the use of SP here establishes SP as
9147 the CFA register and not IP.
9149 Anyway this instruction is not really part of the stack
9150 frame creation although it is part of the prologue. */
9152 else if (IS_NESTED (func_type
))
9154 /* The Static chain register is the same as the IP register
9155 used as a scratch register during stack frame creation.
9156 To get around this need to find somewhere to store IP
9157 whilst the frame is being created. We try the following
9160 1. The last argument register.
9161 2. A slot on the stack above the frame. (This only
9162 works if the function is not a varargs function).
9163 3. Register r3, after pushing the argument registers
9166 Note - we only need to tell the dwarf2 backend about the SP
9167 adjustment in the second variant; the static chain register
9168 doesn't need to be unwound, as it doesn't contain a value
9169 inherited from the caller. */
9171 if (regs_ever_live
[3] == 0)
9173 insn
= gen_rtx_REG (SImode
, 3);
9174 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
9175 insn
= emit_insn (insn
);
9177 else if (args_to_push
== 0)
9180 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
9181 insn
= gen_rtx_MEM (SImode
, insn
);
9182 insn
= gen_rtx_SET (VOIDmode
, insn
, ip_rtx
);
9183 insn
= emit_insn (insn
);
9187 /* Just tell the dwarf backend that we adjusted SP. */
9188 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
9189 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
9190 GEN_INT (-fp_offset
)));
9191 RTX_FRAME_RELATED_P (insn
) = 1;
9192 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
9193 dwarf
, REG_NOTES (insn
));
9197 /* Store the args on the stack. */
9198 if (cfun
->machine
->uses_anonymous_args
)
9199 insn
= emit_multi_reg_push
9200 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
9203 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9204 GEN_INT (- args_to_push
)));
9206 RTX_FRAME_RELATED_P (insn
) = 1;
9208 saved_pretend_args
= 1;
9209 fp_offset
= args_to_push
;
9212 /* Now reuse r3 to preserve IP. */
9213 insn
= gen_rtx_REG (SImode
, 3);
9214 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
9215 (void) emit_insn (insn
);
9221 insn
= gen_rtx_PLUS (SImode
, stack_pointer_rtx
, GEN_INT (fp_offset
));
9222 insn
= gen_rtx_SET (SImode
, ip_rtx
, insn
);
9225 insn
= gen_movsi (ip_rtx
, stack_pointer_rtx
);
9227 insn
= emit_insn (insn
);
9228 RTX_FRAME_RELATED_P (insn
) = 1;
9233 /* Push the argument registers, or reserve space for them. */
9234 if (cfun
->machine
->uses_anonymous_args
)
9235 insn
= emit_multi_reg_push
9236 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
9239 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9240 GEN_INT (- args_to_push
)));
9241 RTX_FRAME_RELATED_P (insn
) = 1;
9244 /* If this is an interrupt service routine, and the link register
9245 is going to be pushed, and we are not creating a stack frame,
9246 (which would involve an extra push of IP and a pop in the epilogue)
9247 subtracting four from LR now will mean that the function return
9248 can be done with a single instruction. */
9249 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
9250 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
9251 && ! frame_pointer_needed
)
9252 emit_insn (gen_rtx_SET (SImode
,
9253 gen_rtx_REG (SImode
, LR_REGNUM
),
9254 gen_rtx_PLUS (SImode
,
9255 gen_rtx_REG (SImode
, LR_REGNUM
),
9260 insn
= emit_multi_reg_push (live_regs_mask
);
9261 RTX_FRAME_RELATED_P (insn
) = 1;
9265 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
9266 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
9268 insn
= gen_rtx_PRE_DEC (V2SImode
, stack_pointer_rtx
);
9269 insn
= gen_rtx_MEM (V2SImode
, insn
);
9270 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
9271 gen_rtx_REG (V2SImode
, reg
)));
9272 RTX_FRAME_RELATED_P (insn
) = 1;
9275 if (! IS_VOLATILE (func_type
))
9277 /* Save any floating point call-saved registers used by this
9279 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9281 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
9282 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9284 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
9285 insn
= gen_rtx_MEM (XFmode
, insn
);
9286 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
9287 gen_rtx_REG (XFmode
, reg
)));
9288 RTX_FRAME_RELATED_P (insn
) = 1;
9293 int start_reg
= LAST_ARM_FP_REGNUM
;
9295 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
9297 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9299 if (start_reg
- reg
== 3)
9301 insn
= emit_sfm (reg
, 4);
9302 RTX_FRAME_RELATED_P (insn
) = 1;
9303 start_reg
= reg
- 1;
9308 if (start_reg
!= reg
)
9310 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
9311 RTX_FRAME_RELATED_P (insn
) = 1;
9313 start_reg
= reg
- 1;
9317 if (start_reg
!= reg
)
9319 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
9320 RTX_FRAME_RELATED_P (insn
) = 1;
9325 if (frame_pointer_needed
)
9327 /* Create the new frame pointer. */
9328 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
9329 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
9330 RTX_FRAME_RELATED_P (insn
) = 1;
9332 if (IS_NESTED (func_type
))
9334 /* Recover the static chain register. */
9335 if (regs_ever_live
[3] == 0
9336 || saved_pretend_args
)
9337 insn
= gen_rtx_REG (SImode
, 3);
9338 else /* if (current_function_pretend_args_size == 0) */
9340 insn
= gen_rtx_PLUS (SImode
, hard_frame_pointer_rtx
,
9342 insn
= gen_rtx_MEM (SImode
, insn
);
9345 emit_insn (gen_rtx_SET (SImode
, ip_rtx
, insn
));
9346 /* Add a USE to stop propagate_one_insn() from barfing. */
9347 emit_insn (gen_prologue_use (ip_rtx
));
9351 amount
= GEN_INT (-(arm_get_frame_size ()
9352 + current_function_outgoing_args_size
));
9354 if (amount
!= const0_rtx
)
9356 /* This add can produce multiple insns for a large constant, so we
9357 need to get tricky. */
9358 rtx last
= get_last_insn ();
9359 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9363 last
= last
? NEXT_INSN (last
) : get_insns ();
9364 RTX_FRAME_RELATED_P (last
) = 1;
9366 while (last
!= insn
);
9368 /* If the frame pointer is needed, emit a special barrier that
9369 will prevent the scheduler from moving stores to the frame
9370 before the stack adjustment. */
9371 if (frame_pointer_needed
)
9372 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
9373 hard_frame_pointer_rtx
));
9376 /* If we are profiling, make sure no instructions are scheduled before
9377 the call to mcount. Similarly if the user has requested no
9378 scheduling in the prolog. */
9379 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
9380 emit_insn (gen_blockage ());
9382 /* If the link register is being kept alive, with the return address in it,
9383 then make sure that it does not get reused by the ce2 pass. */
9384 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
9386 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
9387 cfun
->machine
->lr_save_eliminated
= 1;
9391 /* If CODE is 'd', then the X is a condition operand and the instruction
9392 should only be executed if the condition is true.
9393 if CODE is 'D', then the X is a condition operand and the instruction
9394 should only be executed if the condition is false: however, if the mode
9395 of the comparison is CCFPEmode, then always execute the instruction -- we
9396 do this because in these circumstances !GE does not necessarily imply LT;
9397 in these cases the instruction pattern will take care to make sure that
9398 an instruction containing %d will follow, thereby undoing the effects of
9399 doing this instruction unconditionally.
9400 If CODE is 'N' then X is a floating point operand that must be negated
9402 If CODE is 'B' then output a bitwise inverted value of X (a const int).
9403 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
9405 arm_print_operand (FILE *stream
, rtx x
, int code
)
9410 fputs (ASM_COMMENT_START
, stream
);
9414 fputs (user_label_prefix
, stream
);
9418 fputs (REGISTER_PREFIX
, stream
);
9422 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
9424 if (TARGET_THUMB
|| current_insn_predicate
!= NULL
)
9427 fputs (arm_condition_codes
[arm_current_cc
], stream
);
9429 else if (current_insn_predicate
)
9431 enum arm_cond_code code
;
9436 code
= get_arm_condition_code (current_insn_predicate
);
9437 fputs (arm_condition_codes
[code
], stream
);
9444 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
9445 r
= REAL_VALUE_NEGATE (r
);
9446 fprintf (stream
, "%s", fp_const_from_val (&r
));
9451 if (GET_CODE (x
) == CONST_INT
)
9454 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
9455 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
9460 output_addr_const (stream
, x
);
9465 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
9468 /* Truncate Cirrus shift counts. */
9470 if (GET_CODE (x
) == CONST_INT
)
9472 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
9475 arm_print_operand (stream
, x
, 0);
9479 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
9485 const char * shift
= shift_op (x
, &val
);
9489 fprintf (stream
, ", %s ", shift_op (x
, &val
));
9491 arm_print_operand (stream
, XEXP (x
, 1), 0);
9493 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
9498 /* An explanation of the 'Q', 'R' and 'H' register operands:
9500 In a pair of registers containing a DI or DF value the 'Q'
9501 operand returns the register number of the register containing
9502 the least significant part of the value. The 'R' operand returns
9503 the register number of the register containing the most
9504 significant part of the value.
9506 The 'H' operand returns the higher of the two register numbers.
9507 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
9508 same as the 'Q' operand, since the most significant part of the
9509 value is held in the lower number register. The reverse is true
9510 on systems where WORDS_BIG_ENDIAN is false.
9512 The purpose of these operands is to distinguish between cases
9513 where the endian-ness of the values is important (for example
9514 when they are added together), and cases where the endian-ness
9515 is irrelevant, but the order of register operations is important.
9516 For example when loading a value from memory into a register
9517 pair, the endian-ness does not matter. Provided that the value
9518 from the lower memory address is put into the lower numbered
9519 register, and the value from the higher address is put into the
9520 higher numbered register, the load will work regardless of whether
9521 the value being loaded is big-wordian or little-wordian. The
9522 order of the two register loads can matter however, if the address
9523 of the memory location is actually held in one of the registers
9524 being overwritten by the load. */
9526 if (REGNO (x
) > LAST_ARM_REGNUM
)
9528 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
9532 if (REGNO (x
) > LAST_ARM_REGNUM
)
9534 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
9538 if (REGNO (x
) > LAST_ARM_REGNUM
)
9540 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
9544 asm_fprintf (stream
, "%r",
9545 GET_CODE (XEXP (x
, 0)) == REG
9546 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
9550 asm_fprintf (stream
, "{%r-%r}",
9552 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
9556 /* CONST_TRUE_RTX means always -- that's the default. */
9557 if (x
== const_true_rtx
)
9561 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
9564 fputs (thumb_condition_code (x
, 0), stream
);
9568 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
9570 if (x
== const_true_rtx
)
9574 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
9575 (get_arm_condition_code (x
))],
9578 fputs (thumb_condition_code (x
, 1), stream
);
9581 /* Cirrus registers can be accessed in a variety of ways:
9582 single floating point (f)
9583 double floating point (d)
9585 64bit integer (dx). */
9586 case 'W': /* Cirrus register in F mode. */
9587 case 'X': /* Cirrus register in D mode. */
9588 case 'Y': /* Cirrus register in FX mode. */
9589 case 'Z': /* Cirrus register in DX mode. */
9590 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
9593 fprintf (stream
, "mv%s%s",
9596 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
9600 /* Print cirrus register in the mode specified by the register's mode. */
9603 int mode
= GET_MODE (x
);
9605 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
9608 fprintf (stream
, "mv%s%s",
9609 mode
== DFmode
? "d"
9610 : mode
== SImode
? "fx"
9611 : mode
== DImode
? "dx"
9612 : "f", reg_names
[REGNO (x
)] + 2);
9618 if (GET_CODE (x
) != REG
9619 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
9620 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
9621 /* Bad value for wCG register number. */
9624 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
9627 /* Print an iWMMXt control register name. */
9629 if (GET_CODE (x
) != CONST_INT
9631 || INTVAL (x
) >= 16)
9632 /* Bad value for wC register number. */
9636 static const char * wc_reg_names
[16] =
9638 "wCID", "wCon", "wCSSF", "wCASF",
9639 "wC4", "wC5", "wC6", "wC7",
9640 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
9641 "wC12", "wC13", "wC14", "wC15"
9644 fprintf (stream
, wc_reg_names
[INTVAL (x
)]);
9652 if (GET_CODE (x
) == REG
)
9653 asm_fprintf (stream
, "%r", REGNO (x
));
9654 else if (GET_CODE (x
) == MEM
)
9656 output_memory_reference_mode
= GET_MODE (x
);
9657 output_address (XEXP (x
, 0));
9659 else if (GET_CODE (x
) == CONST_DOUBLE
)
9660 fprintf (stream
, "#%s", fp_immediate_constant (x
));
9661 else if (GET_CODE (x
) == NEG
)
9662 abort (); /* This should never happen now. */
9665 fputc ('#', stream
);
9666 output_addr_const (stream
, x
);
9671 #ifndef AOF_ASSEMBLER
9672 /* Target hook for assembling integer objects. The ARM version needs to
9673 handle word-sized values specially. */
9675 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
9677 if (size
== UNITS_PER_WORD
&& aligned_p
)
9679 fputs ("\t.word\t", asm_out_file
);
9680 output_addr_const (asm_out_file
, x
);
9682 /* Mark symbols as position independent. We only do this in the
9683 .text segment, not in the .data segment. */
9684 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
9685 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
9687 if (GET_CODE (x
) == SYMBOL_REF
9688 && (CONSTANT_POOL_ADDRESS_P (x
)
9689 || SYMBOL_REF_LOCAL_P (x
)))
9690 fputs ("(GOTOFF)", asm_out_file
);
9691 else if (GET_CODE (x
) == LABEL_REF
)
9692 fputs ("(GOTOFF)", asm_out_file
);
9694 fputs ("(GOT)", asm_out_file
);
9696 fputc ('\n', asm_out_file
);
9700 if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x
)))
9704 if (GET_CODE (x
) != CONST_VECTOR
)
9707 units
= CONST_VECTOR_NUNITS (x
);
9709 switch (GET_MODE (x
))
9711 case V2SImode
: size
= 4; break;
9712 case V4HImode
: size
= 2; break;
9713 case V8QImode
: size
= 1; break;
9718 for (i
= 0; i
< units
; i
++)
9722 elt
= CONST_VECTOR_ELT (x
, i
);
9724 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
9730 return default_assemble_integer (x
, size
, aligned_p
);
9734 /* A finite state machine takes care of noticing whether or not instructions
9735 can be conditionally executed, and thus decrease execution time and code
9736 size by deleting branch instructions. The fsm is controlled by
9737 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
9739 /* The state of the fsm controlling condition codes are:
9740 0: normal, do nothing special
9741 1: make ASM_OUTPUT_OPCODE not output this instruction
9742 2: make ASM_OUTPUT_OPCODE not output this instruction
9743 3: make instructions conditional
9744 4: make instructions conditional
9746 State transitions (state->state by whom under condition):
9747 0 -> 1 final_prescan_insn if the `target' is a label
9748 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
9749 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
9750 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
9751 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
9752 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
9753 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
9754 (the target insn is arm_target_insn).
9756 If the jump clobbers the conditions then we use states 2 and 4.
9758 A similar thing can be done with conditional return insns.
9760 XXX In case the `target' is an unconditional branch, this conditionalising
9761 of the instructions always reduces code size, but not always execution
9762 time. But then, I want to reduce the code size to somewhere near what
9763 /bin/cc produces. */
9765 /* Returns the index of the ARM condition code string in
9766 `arm_condition_codes'. COMPARISON should be an rtx like
9767 `(eq (...) (...))'. */
9768 static enum arm_cond_code
9769 get_arm_condition_code (rtx comparison
)
9771 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
9773 enum rtx_code comp_code
= GET_CODE (comparison
);
9775 if (GET_MODE_CLASS (mode
) != MODE_CC
)
9776 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
9777 XEXP (comparison
, 1));
9781 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
9782 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
9783 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
9784 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
9785 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
9786 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
9787 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
9788 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
9789 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
9790 case CC_DLTUmode
: code
= ARM_CC
;
9793 if (comp_code
!= EQ
&& comp_code
!= NE
)
9796 if (comp_code
== EQ
)
9797 return ARM_INVERSE_CONDITION_CODE (code
);
9803 case NE
: return ARM_NE
;
9804 case EQ
: return ARM_EQ
;
9805 case GE
: return ARM_PL
;
9806 case LT
: return ARM_MI
;
9813 case NE
: return ARM_NE
;
9814 case EQ
: return ARM_EQ
;
9820 /* These encodings assume that AC=1 in the FPA system control
9821 byte. This allows us to handle all cases except UNEQ and
9825 case GE
: return ARM_GE
;
9826 case GT
: return ARM_GT
;
9827 case LE
: return ARM_LS
;
9828 case LT
: return ARM_MI
;
9829 case NE
: return ARM_NE
;
9830 case EQ
: return ARM_EQ
;
9831 case ORDERED
: return ARM_VC
;
9832 case UNORDERED
: return ARM_VS
;
9833 case UNLT
: return ARM_LT
;
9834 case UNLE
: return ARM_LE
;
9835 case UNGT
: return ARM_HI
;
9836 case UNGE
: return ARM_PL
;
9837 /* UNEQ and LTGT do not have a representation. */
9838 case UNEQ
: /* Fall through. */
9839 case LTGT
: /* Fall through. */
9846 case NE
: return ARM_NE
;
9847 case EQ
: return ARM_EQ
;
9848 case GE
: return ARM_LE
;
9849 case GT
: return ARM_LT
;
9850 case LE
: return ARM_GE
;
9851 case LT
: return ARM_GT
;
9852 case GEU
: return ARM_LS
;
9853 case GTU
: return ARM_CC
;
9854 case LEU
: return ARM_CS
;
9855 case LTU
: return ARM_HI
;
9862 case LTU
: return ARM_CS
;
9863 case GEU
: return ARM_CC
;
9870 case NE
: return ARM_NE
;
9871 case EQ
: return ARM_EQ
;
9872 case GE
: return ARM_GE
;
9873 case GT
: return ARM_GT
;
9874 case LE
: return ARM_LE
;
9875 case LT
: return ARM_LT
;
9876 case GEU
: return ARM_CS
;
9877 case GTU
: return ARM_HI
;
9878 case LEU
: return ARM_LS
;
9879 case LTU
: return ARM_CC
;
9890 arm_final_prescan_insn (rtx insn
)
9892 /* BODY will hold the body of INSN. */
9893 rtx body
= PATTERN (insn
);
9895 /* This will be 1 if trying to repeat the trick, and things need to be
9896 reversed if it appears to fail. */
9899 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
9900 taken are clobbered, even if the rtl suggests otherwise. It also
9901 means that we have to grub around within the jump expression to find
9902 out what the conditions are when the jump isn't taken. */
9903 int jump_clobbers
= 0;
9905 /* If we start with a return insn, we only succeed if we find another one. */
9906 int seeking_return
= 0;
9908 /* START_INSN will hold the insn from where we start looking. This is the
9909 first insn after the following code_label if REVERSE is true. */
9910 rtx start_insn
= insn
;
9912 /* If in state 4, check if the target branch is reached, in order to
9913 change back to state 0. */
9914 if (arm_ccfsm_state
== 4)
9916 if (insn
== arm_target_insn
)
9918 arm_target_insn
= NULL
;
9919 arm_ccfsm_state
= 0;
9924 /* If in state 3, it is possible to repeat the trick, if this insn is an
9925 unconditional branch to a label, and immediately following this branch
9926 is the previous target label which is only used once, and the label this
9927 branch jumps to is not too far off. */
9928 if (arm_ccfsm_state
== 3)
9930 if (simplejump_p (insn
))
9932 start_insn
= next_nonnote_insn (start_insn
);
9933 if (GET_CODE (start_insn
) == BARRIER
)
9935 /* XXX Isn't this always a barrier? */
9936 start_insn
= next_nonnote_insn (start_insn
);
9938 if (GET_CODE (start_insn
) == CODE_LABEL
9939 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
9940 && LABEL_NUSES (start_insn
) == 1)
9945 else if (GET_CODE (body
) == RETURN
)
9947 start_insn
= next_nonnote_insn (start_insn
);
9948 if (GET_CODE (start_insn
) == BARRIER
)
9949 start_insn
= next_nonnote_insn (start_insn
);
9950 if (GET_CODE (start_insn
) == CODE_LABEL
9951 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
9952 && LABEL_NUSES (start_insn
) == 1)
9964 if (arm_ccfsm_state
!= 0 && !reverse
)
9966 if (GET_CODE (insn
) != JUMP_INSN
)
9969 /* This jump might be paralleled with a clobber of the condition codes
9970 the jump should always come first */
9971 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
9972 body
= XVECEXP (body
, 0, 0);
9975 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
9976 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
9979 int fail
= FALSE
, succeed
= FALSE
;
9980 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
9981 int then_not_else
= TRUE
;
9982 rtx this_insn
= start_insn
, label
= 0;
9984 /* If the jump cannot be done with one instruction, we cannot
9985 conditionally execute the instruction in the inverse case. */
9986 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
9992 /* Register the insn jumped to. */
9995 if (!seeking_return
)
9996 label
= XEXP (SET_SRC (body
), 0);
9998 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
9999 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
10000 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
10002 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
10003 then_not_else
= FALSE
;
10005 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
10006 seeking_return
= 1;
10007 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
10009 seeking_return
= 1;
10010 then_not_else
= FALSE
;
10015 /* See how many insns this branch skips, and what kind of insns. If all
10016 insns are okay, and the label or unconditional branch to the same
10017 label is not too far away, succeed. */
10018 for (insns_skipped
= 0;
10019 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
10023 this_insn
= next_nonnote_insn (this_insn
);
10027 switch (GET_CODE (this_insn
))
10030 /* Succeed if it is the target label, otherwise fail since
10031 control falls in from somewhere else. */
10032 if (this_insn
== label
)
10036 arm_ccfsm_state
= 2;
10037 this_insn
= next_nonnote_insn (this_insn
);
10040 arm_ccfsm_state
= 1;
10048 /* Succeed if the following insn is the target label.
10050 If return insns are used then the last insn in a function
10051 will be a barrier. */
10052 this_insn
= next_nonnote_insn (this_insn
);
10053 if (this_insn
&& this_insn
== label
)
10057 arm_ccfsm_state
= 2;
10058 this_insn
= next_nonnote_insn (this_insn
);
10061 arm_ccfsm_state
= 1;
10069 /* If using 32-bit addresses the cc is not preserved over
10071 if (TARGET_APCS_32
)
10073 /* Succeed if the following insn is the target label,
10074 or if the following two insns are a barrier and
10075 the target label. */
10076 this_insn
= next_nonnote_insn (this_insn
);
10077 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
10078 this_insn
= next_nonnote_insn (this_insn
);
10080 if (this_insn
&& this_insn
== label
10081 && insns_skipped
< max_insns_skipped
)
10085 arm_ccfsm_state
= 2;
10086 this_insn
= next_nonnote_insn (this_insn
);
10089 arm_ccfsm_state
= 1;
10098 /* If this is an unconditional branch to the same label, succeed.
10099 If it is to another label, do nothing. If it is conditional,
10101 /* XXX Probably, the tests for SET and the PC are
10104 scanbody
= PATTERN (this_insn
);
10105 if (GET_CODE (scanbody
) == SET
10106 && GET_CODE (SET_DEST (scanbody
)) == PC
)
10108 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
10109 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
10111 arm_ccfsm_state
= 2;
10114 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
10117 /* Fail if a conditional return is undesirable (eg on a
10118 StrongARM), but still allow this if optimizing for size. */
10119 else if (GET_CODE (scanbody
) == RETURN
10120 && !use_return_insn (TRUE
)
10123 else if (GET_CODE (scanbody
) == RETURN
10126 arm_ccfsm_state
= 2;
10129 else if (GET_CODE (scanbody
) == PARALLEL
)
10131 switch (get_attr_conds (this_insn
))
10141 fail
= TRUE
; /* Unrecognized jump (eg epilogue). */
10146 /* Instructions using or affecting the condition codes make it
10148 scanbody
= PATTERN (this_insn
);
10149 if (!(GET_CODE (scanbody
) == SET
10150 || GET_CODE (scanbody
) == PARALLEL
)
10151 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
10154 /* A conditional cirrus instruction must be followed by
10155 a non Cirrus instruction. However, since we
10156 conditionalize instructions in this function and by
10157 the time we get here we can't add instructions
10158 (nops), because shorten_branches() has already been
10159 called, we will disable conditionalizing Cirrus
10160 instructions to be safe. */
10161 if (GET_CODE (scanbody
) != USE
10162 && GET_CODE (scanbody
) != CLOBBER
10163 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
10173 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
10174 arm_target_label
= CODE_LABEL_NUMBER (label
);
10175 else if (seeking_return
|| arm_ccfsm_state
== 2)
10177 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
10179 this_insn
= next_nonnote_insn (this_insn
);
10180 if (this_insn
&& (GET_CODE (this_insn
) == BARRIER
10181 || GET_CODE (this_insn
) == CODE_LABEL
))
10186 /* Oh, dear! we ran off the end.. give up */
10187 recog (PATTERN (insn
), insn
, NULL
);
10188 arm_ccfsm_state
= 0;
10189 arm_target_insn
= NULL
;
10192 arm_target_insn
= this_insn
;
10201 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
10203 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
10204 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
10205 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
10206 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
10210 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
10213 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
10217 if (reverse
|| then_not_else
)
10218 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
10221 /* Restore recog_data (getting the attributes of other insns can
10222 destroy this array, but final.c assumes that it remains intact
10223 across this call; since the insn has been recognized already we
10224 call recog direct). */
10225 recog (PATTERN (insn
), insn
, NULL
);
10229 /* Returns true if REGNO is a valid register
10230 for holding a quantity of tyoe MODE. */
10232 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
10234 if (GET_MODE_CLASS (mode
) == MODE_CC
)
10235 return regno
== CC_REGNUM
;
10238 /* For the Thumb we only allow values bigger than SImode in
10239 registers 0 - 6, so that there is always a second low
10240 register available to hold the upper part of the value.
10241 We probably we ought to ensure that the register is the
10242 start of an even numbered register pair. */
10243 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
10245 if (IS_CIRRUS_REGNUM (regno
))
10246 /* We have outlawed SI values in Cirrus registers because they
10247 reside in the lower 32 bits, but SF values reside in the
10248 upper 32 bits. This causes gcc all sorts of grief. We can't
10249 even split the registers into pairs because Cirrus SI values
10250 get sign extended to 64bits-- aldyh. */
10251 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
10253 if (IS_IWMMXT_GR_REGNUM (regno
))
10254 return mode
== SImode
;
10256 if (IS_IWMMXT_REGNUM (regno
))
10257 return VALID_IWMMXT_REG_MODE (mode
);
10259 if (regno
<= LAST_ARM_REGNUM
)
10260 /* We allow any value to be stored in the general registers. */
10263 if ( regno
== FRAME_POINTER_REGNUM
10264 || regno
== ARG_POINTER_REGNUM
)
10265 /* We only allow integers in the fake hard registers. */
10266 return GET_MODE_CLASS (mode
) == MODE_INT
;
10268 /* The only registers left are the FPA registers
10269 which we only allow to hold FP values. */
10270 return GET_MODE_CLASS (mode
) == MODE_FLOAT
10271 && regno
>= FIRST_ARM_FP_REGNUM
10272 && regno
<= LAST_ARM_FP_REGNUM
;
10276 arm_regno_class (int regno
)
10280 if (regno
== STACK_POINTER_REGNUM
)
10282 if (regno
== CC_REGNUM
)
10289 if ( regno
<= LAST_ARM_REGNUM
10290 || regno
== FRAME_POINTER_REGNUM
10291 || regno
== ARG_POINTER_REGNUM
)
10292 return GENERAL_REGS
;
10294 if (regno
== CC_REGNUM
)
10297 if (IS_CIRRUS_REGNUM (regno
))
10298 return CIRRUS_REGS
;
10300 if (IS_IWMMXT_REGNUM (regno
))
10301 return IWMMXT_REGS
;
10306 /* Handle a special case when computing the offset
10307 of an argument from the frame pointer. */
10309 arm_debugger_arg_offset (int value
, rtx addr
)
10313 /* We are only interested if dbxout_parms() failed to compute the offset. */
10317 /* We can only cope with the case where the address is held in a register. */
10318 if (GET_CODE (addr
) != REG
)
10321 /* If we are using the frame pointer to point at the argument, then
10322 an offset of 0 is correct. */
10323 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
10326 /* If we are using the stack pointer to point at the
10327 argument, then an offset of 0 is correct. */
10328 if ((TARGET_THUMB
|| !frame_pointer_needed
)
10329 && REGNO (addr
) == SP_REGNUM
)
10332 /* Oh dear. The argument is pointed to by a register rather
10333 than being held in a register, or being stored at a known
10334 offset from the frame pointer. Since GDB only understands
10335 those two kinds of argument we must translate the address
10336 held in the register into an offset from the frame pointer.
10337 We do this by searching through the insns for the function
10338 looking to see where this register gets its value. If the
10339 register is initialized from the frame pointer plus an offset
10340 then we are in luck and we can continue, otherwise we give up.
10342 This code is exercised by producing debugging information
10343 for a function with arguments like this:
10345 double func (double a, double b, int c, double d) {return d;}
10347 Without this code the stab for parameter 'd' will be set to
10348 an offset of 0 from the frame pointer, rather than 8. */
10350 /* The if() statement says:
10352 If the insn is a normal instruction
10353 and if the insn is setting the value in a register
10354 and if the register being set is the register holding the address of the argument
10355 and if the address is computing by an addition
10356 that involves adding to a register
10357 which is the frame pointer
10362 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10364 if ( GET_CODE (insn
) == INSN
10365 && GET_CODE (PATTERN (insn
)) == SET
10366 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
10367 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
10368 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
10369 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
10370 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
10373 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
10382 warning ("unable to compute real location of stacked parameter");
10383 value
= 8; /* XXX magic hack */
10389 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
10392 if ((MASK) & insn_flags) \
10393 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \
10397 struct builtin_description
10399 const unsigned int mask
;
10400 const enum insn_code icode
;
10401 const char * const name
;
10402 const enum arm_builtins code
;
10403 const enum rtx_code comparison
;
10404 const unsigned int flag
;
10407 static const struct builtin_description bdesc_2arg
[] =
10409 #define IWMMXT_BUILTIN(code, string, builtin) \
10410 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
10411 ARM_BUILTIN_##builtin, 0, 0 },
10413 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
10414 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
10415 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
10416 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
10417 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
10418 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
10419 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
10420 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
10421 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
10422 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
10423 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
10424 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
10425 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
10426 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
10427 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
10428 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
10429 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
10430 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
10431 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
10432 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsh", WMULSH
)
10433 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmuluh", WMULUH
)
10434 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
10435 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
10436 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
10437 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
10438 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
10439 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
10440 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
10441 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
10442 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
10443 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
10444 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
10445 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
10446 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
10447 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
10448 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
10449 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
10450 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
10451 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
10452 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
10453 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
10454 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
10455 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
10456 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
10457 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
10458 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
10459 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
10460 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
10461 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
10462 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
10463 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
10464 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
10465 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
10466 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
10467 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
10468 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
10469 IWMMXT_BUILTIN (iwmmxt_wmadds
, "wmadds", WMADDS
)
10470 IWMMXT_BUILTIN (iwmmxt_wmaddu
, "wmaddu", WMADDU
)
10472 #define IWMMXT_BUILTIN2(code, builtin) \
10473 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
10475 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
10476 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
10477 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
10478 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
10479 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
10480 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
10481 IWMMXT_BUILTIN2 (ashlv4hi3_di
, WSLLH
)
10482 IWMMXT_BUILTIN2 (ashlv4hi3
, WSLLHI
)
10483 IWMMXT_BUILTIN2 (ashlv2si3_di
, WSLLW
)
10484 IWMMXT_BUILTIN2 (ashlv2si3
, WSLLWI
)
10485 IWMMXT_BUILTIN2 (ashldi3_di
, WSLLD
)
10486 IWMMXT_BUILTIN2 (ashldi3_iwmmxt
, WSLLDI
)
10487 IWMMXT_BUILTIN2 (lshrv4hi3_di
, WSRLH
)
10488 IWMMXT_BUILTIN2 (lshrv4hi3
, WSRLHI
)
10489 IWMMXT_BUILTIN2 (lshrv2si3_di
, WSRLW
)
10490 IWMMXT_BUILTIN2 (lshrv2si3
, WSRLWI
)
10491 IWMMXT_BUILTIN2 (lshrdi3_di
, WSRLD
)
10492 IWMMXT_BUILTIN2 (lshrdi3
, WSRLDI
)
10493 IWMMXT_BUILTIN2 (ashrv4hi3_di
, WSRAH
)
10494 IWMMXT_BUILTIN2 (ashrv4hi3
, WSRAHI
)
10495 IWMMXT_BUILTIN2 (ashrv2si3_di
, WSRAW
)
10496 IWMMXT_BUILTIN2 (ashrv2si3
, WSRAWI
)
10497 IWMMXT_BUILTIN2 (ashrdi3_di
, WSRAD
)
10498 IWMMXT_BUILTIN2 (ashrdi3
, WSRADI
)
10499 IWMMXT_BUILTIN2 (rorv4hi3_di
, WRORH
)
10500 IWMMXT_BUILTIN2 (rorv4hi3
, WRORHI
)
10501 IWMMXT_BUILTIN2 (rorv2si3_di
, WRORW
)
10502 IWMMXT_BUILTIN2 (rorv2si3
, WRORWI
)
10503 IWMMXT_BUILTIN2 (rordi3_di
, WRORD
)
10504 IWMMXT_BUILTIN2 (rordi3
, WRORDI
)
10505 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
10506 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
10509 static const struct builtin_description bdesc_1arg
[] =
10511 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
10512 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
10513 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
10514 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
10515 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
10516 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
10517 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
10518 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
10519 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
10520 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
10521 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
10522 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
10523 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
10524 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
10525 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
10526 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
10527 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
10528 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
10531 /* Set up all the iWMMXt builtins. This is
10532 not called if TARGET_IWMMXT is zero. */
10535 arm_init_iwmmxt_builtins (void)
10537 const struct builtin_description
* d
;
10539 tree endlink
= void_list_node
;
10542 = build_function_type (integer_type_node
,
10543 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
10544 tree v8qi_ftype_v8qi_v8qi_int
10545 = build_function_type (V8QI_type_node
,
10546 tree_cons (NULL_TREE
, V8QI_type_node
,
10547 tree_cons (NULL_TREE
, V8QI_type_node
,
10548 tree_cons (NULL_TREE
,
10551 tree v4hi_ftype_v4hi_int
10552 = build_function_type (V4HI_type_node
,
10553 tree_cons (NULL_TREE
, V4HI_type_node
,
10554 tree_cons (NULL_TREE
, integer_type_node
,
10556 tree v2si_ftype_v2si_int
10557 = build_function_type (V2SI_type_node
,
10558 tree_cons (NULL_TREE
, V2SI_type_node
,
10559 tree_cons (NULL_TREE
, integer_type_node
,
10561 tree v2si_ftype_di_di
10562 = build_function_type (V2SI_type_node
,
10563 tree_cons (NULL_TREE
, long_long_integer_type_node
,
10564 tree_cons (NULL_TREE
, long_long_integer_type_node
,
10566 tree di_ftype_di_int
10567 = build_function_type (long_long_integer_type_node
,
10568 tree_cons (NULL_TREE
, long_long_integer_type_node
,
10569 tree_cons (NULL_TREE
, integer_type_node
,
10571 tree di_ftype_di_int_int
10572 = build_function_type (long_long_integer_type_node
,
10573 tree_cons (NULL_TREE
, long_long_integer_type_node
,
10574 tree_cons (NULL_TREE
, integer_type_node
,
10575 tree_cons (NULL_TREE
,
10578 tree int_ftype_v8qi
10579 = build_function_type (integer_type_node
,
10580 tree_cons (NULL_TREE
, V8QI_type_node
,
10582 tree int_ftype_v4hi
10583 = build_function_type (integer_type_node
,
10584 tree_cons (NULL_TREE
, V4HI_type_node
,
10586 tree int_ftype_v2si
10587 = build_function_type (integer_type_node
,
10588 tree_cons (NULL_TREE
, V2SI_type_node
,
10590 tree int_ftype_v8qi_int
10591 = build_function_type (integer_type_node
,
10592 tree_cons (NULL_TREE
, V8QI_type_node
,
10593 tree_cons (NULL_TREE
, integer_type_node
,
10595 tree int_ftype_v4hi_int
10596 = build_function_type (integer_type_node
,
10597 tree_cons (NULL_TREE
, V4HI_type_node
,
10598 tree_cons (NULL_TREE
, integer_type_node
,
10600 tree int_ftype_v2si_int
10601 = build_function_type (integer_type_node
,
10602 tree_cons (NULL_TREE
, V2SI_type_node
,
10603 tree_cons (NULL_TREE
, integer_type_node
,
10605 tree v8qi_ftype_v8qi_int_int
10606 = build_function_type (V8QI_type_node
,
10607 tree_cons (NULL_TREE
, V8QI_type_node
,
10608 tree_cons (NULL_TREE
, integer_type_node
,
10609 tree_cons (NULL_TREE
,
10612 tree v4hi_ftype_v4hi_int_int
10613 = build_function_type (V4HI_type_node
,
10614 tree_cons (NULL_TREE
, V4HI_type_node
,
10615 tree_cons (NULL_TREE
, integer_type_node
,
10616 tree_cons (NULL_TREE
,
10619 tree v2si_ftype_v2si_int_int
10620 = build_function_type (V2SI_type_node
,
10621 tree_cons (NULL_TREE
, V2SI_type_node
,
10622 tree_cons (NULL_TREE
, integer_type_node
,
10623 tree_cons (NULL_TREE
,
10626 /* Miscellaneous. */
10627 tree v8qi_ftype_v4hi_v4hi
10628 = build_function_type (V8QI_type_node
,
10629 tree_cons (NULL_TREE
, V4HI_type_node
,
10630 tree_cons (NULL_TREE
, V4HI_type_node
,
10632 tree v4hi_ftype_v2si_v2si
10633 = build_function_type (V4HI_type_node
,
10634 tree_cons (NULL_TREE
, V2SI_type_node
,
10635 tree_cons (NULL_TREE
, V2SI_type_node
,
10637 tree v2si_ftype_v4hi_v4hi
10638 = build_function_type (V2SI_type_node
,
10639 tree_cons (NULL_TREE
, V4HI_type_node
,
10640 tree_cons (NULL_TREE
, V4HI_type_node
,
10642 tree v2si_ftype_v8qi_v8qi
10643 = build_function_type (V2SI_type_node
,
10644 tree_cons (NULL_TREE
, V8QI_type_node
,
10645 tree_cons (NULL_TREE
, V8QI_type_node
,
10647 tree v4hi_ftype_v4hi_di
10648 = build_function_type (V4HI_type_node
,
10649 tree_cons (NULL_TREE
, V4HI_type_node
,
10650 tree_cons (NULL_TREE
,
10651 long_long_integer_type_node
,
10653 tree v2si_ftype_v2si_di
10654 = build_function_type (V2SI_type_node
,
10655 tree_cons (NULL_TREE
, V2SI_type_node
,
10656 tree_cons (NULL_TREE
,
10657 long_long_integer_type_node
,
10659 tree void_ftype_int_int
10660 = build_function_type (void_type_node
,
10661 tree_cons (NULL_TREE
, integer_type_node
,
10662 tree_cons (NULL_TREE
, integer_type_node
,
10665 = build_function_type (long_long_unsigned_type_node
, endlink
);
10667 = build_function_type (long_long_integer_type_node
,
10668 tree_cons (NULL_TREE
, V8QI_type_node
,
10671 = build_function_type (long_long_integer_type_node
,
10672 tree_cons (NULL_TREE
, V4HI_type_node
,
10675 = build_function_type (long_long_integer_type_node
,
10676 tree_cons (NULL_TREE
, V2SI_type_node
,
10678 tree v2si_ftype_v4hi
10679 = build_function_type (V2SI_type_node
,
10680 tree_cons (NULL_TREE
, V4HI_type_node
,
10682 tree v4hi_ftype_v8qi
10683 = build_function_type (V4HI_type_node
,
10684 tree_cons (NULL_TREE
, V8QI_type_node
,
10687 tree di_ftype_di_v4hi_v4hi
10688 = build_function_type (long_long_unsigned_type_node
,
10689 tree_cons (NULL_TREE
,
10690 long_long_unsigned_type_node
,
10691 tree_cons (NULL_TREE
, V4HI_type_node
,
10692 tree_cons (NULL_TREE
,
10696 tree di_ftype_v4hi_v4hi
10697 = build_function_type (long_long_unsigned_type_node
,
10698 tree_cons (NULL_TREE
, V4HI_type_node
,
10699 tree_cons (NULL_TREE
, V4HI_type_node
,
10702 /* Normal vector binops. */
10703 tree v8qi_ftype_v8qi_v8qi
10704 = build_function_type (V8QI_type_node
,
10705 tree_cons (NULL_TREE
, V8QI_type_node
,
10706 tree_cons (NULL_TREE
, V8QI_type_node
,
10708 tree v4hi_ftype_v4hi_v4hi
10709 = build_function_type (V4HI_type_node
,
10710 tree_cons (NULL_TREE
, V4HI_type_node
,
10711 tree_cons (NULL_TREE
, V4HI_type_node
,
10713 tree v2si_ftype_v2si_v2si
10714 = build_function_type (V2SI_type_node
,
10715 tree_cons (NULL_TREE
, V2SI_type_node
,
10716 tree_cons (NULL_TREE
, V2SI_type_node
,
10718 tree di_ftype_di_di
10719 = build_function_type (long_long_unsigned_type_node
,
10720 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
10721 tree_cons (NULL_TREE
,
10722 long_long_unsigned_type_node
,
10725 /* Add all builtins that are more or less simple operations on two
10727 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
10729 /* Use one of the operands; the target can have a different mode for
10730 mask-generating compares. */
10731 enum machine_mode mode
;
10737 mode
= insn_data
[d
->icode
].operand
[1].mode
;
10742 type
= v8qi_ftype_v8qi_v8qi
;
10745 type
= v4hi_ftype_v4hi_v4hi
;
10748 type
= v2si_ftype_v2si_v2si
;
10751 type
= di_ftype_di_di
;
10758 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
10761 /* Add the remaining MMX insns with somewhat more complicated types. */
10762 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wzero", di_ftype_void
, ARM_BUILTIN_WZERO
);
10763 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_setwcx", void_ftype_int_int
, ARM_BUILTIN_SETWCX
);
10764 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_getwcx", int_ftype_int
, ARM_BUILTIN_GETWCX
);
10766 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSLLH
);
10767 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSLLW
);
10768 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslld", di_ftype_di_di
, ARM_BUILTIN_WSLLD
);
10769 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSLLHI
);
10770 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSLLWI
);
10771 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslldi", di_ftype_di_int
, ARM_BUILTIN_WSLLDI
);
10773 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRLH
);
10774 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRLW
);
10775 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrld", di_ftype_di_di
, ARM_BUILTIN_WSRLD
);
10776 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRLHI
);
10777 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRLWI
);
10778 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrldi", di_ftype_di_int
, ARM_BUILTIN_WSRLDI
);
10780 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRAH
);
10781 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsraw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRAW
);
10782 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrad", di_ftype_di_di
, ARM_BUILTIN_WSRAD
);
10783 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRAHI
);
10784 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrawi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRAWI
);
10785 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsradi", di_ftype_di_int
, ARM_BUILTIN_WSRADI
);
10787 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WRORH
);
10788 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorw", v2si_ftype_v2si_di
, ARM_BUILTIN_WRORW
);
10789 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrord", di_ftype_di_di
, ARM_BUILTIN_WRORD
);
10790 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WRORHI
);
10791 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WRORWI
);
10792 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrordi", di_ftype_di_int
, ARM_BUILTIN_WRORDI
);
10794 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSHUFH
);
10796 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADB
);
10797 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADH
);
10798 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADBZ
);
10799 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADHZ
);
10801 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsb", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMSB
);
10802 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMSH
);
10803 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMSW
);
10804 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmub", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMUB
);
10805 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMUH
);
10806 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMUW
);
10807 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int
, ARM_BUILTIN_TINSRB
);
10808 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int
, ARM_BUILTIN_TINSRH
);
10809 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int
, ARM_BUILTIN_TINSRW
);
10811 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccb", di_ftype_v8qi
, ARM_BUILTIN_WACCB
);
10812 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wacch", di_ftype_v4hi
, ARM_BUILTIN_WACCH
);
10813 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccw", di_ftype_v2si
, ARM_BUILTIN_WACCW
);
10815 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskb", int_ftype_v8qi
, ARM_BUILTIN_TMOVMSKB
);
10816 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskh", int_ftype_v4hi
, ARM_BUILTIN_TMOVMSKH
);
10817 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskw", int_ftype_v2si
, ARM_BUILTIN_TMOVMSKW
);
10819 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHSS
);
10820 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHUS
);
10821 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWUS
);
10822 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWSS
);
10823 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdus", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDUS
);
10824 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdss", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDSS
);
10826 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHUB
);
10827 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHUH
);
10828 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHUW
);
10829 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHSB
);
10830 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHSH
);
10831 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHSW
);
10832 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELUB
);
10833 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELUH
);
10834 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELUW
);
10835 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELSB
);
10836 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELSH
);
10837 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELSW
);
10839 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACS
);
10840 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACSZ
);
10841 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACU
);
10842 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACUZ
);
10844 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int
, ARM_BUILTIN_WALIGN
);
10845 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmia", di_ftype_di_int_int
, ARM_BUILTIN_TMIA
);
10846 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiaph", di_ftype_di_int_int
, ARM_BUILTIN_TMIAPH
);
10847 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabb", di_ftype_di_int_int
, ARM_BUILTIN_TMIABB
);
10848 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabt", di_ftype_di_int_int
, ARM_BUILTIN_TMIABT
);
10849 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatb", di_ftype_di_int_int
, ARM_BUILTIN_TMIATB
);
10850 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatt", di_ftype_di_int_int
, ARM_BUILTIN_TMIATT
);
10854 arm_init_builtins (void)
10856 if (TARGET_REALLY_IWMMXT
)
10857 arm_init_iwmmxt_builtins ();
10860 /* Errors in the source file can cause expand_expr to return const0_rtx
10861 where we expect a vector. To avoid crashing, use one of the vector
10862 clear instructions. */
10865 safe_vector_operand (rtx x
, enum machine_mode mode
)
10867 if (x
!= const0_rtx
)
10869 x
= gen_reg_rtx (mode
);
10871 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
10872 : gen_rtx_SUBREG (DImode
, x
, 0)));
10876 /* Subroutine of arm_expand_builtin to take care of binop insns. */
10879 arm_expand_binop_builtin (enum insn_code icode
,
10880 tree arglist
, rtx target
)
10883 tree arg0
= TREE_VALUE (arglist
);
10884 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
10885 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
10886 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
10887 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10888 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
10889 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
10891 if (VECTOR_MODE_P (mode0
))
10892 op0
= safe_vector_operand (op0
, mode0
);
10893 if (VECTOR_MODE_P (mode1
))
10894 op1
= safe_vector_operand (op1
, mode1
);
10897 || GET_MODE (target
) != tmode
10898 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10899 target
= gen_reg_rtx (tmode
);
10901 /* In case the insn wants input operands in modes different from
10902 the result, abort. */
10903 if (GET_MODE (op0
) != mode0
|| GET_MODE (op1
) != mode1
)
10906 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10907 op0
= copy_to_mode_reg (mode0
, op0
);
10908 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
10909 op1
= copy_to_mode_reg (mode1
, op1
);
10911 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
10918 /* Subroutine of arm_expand_builtin to take care of unop insns. */
10921 arm_expand_unop_builtin (enum insn_code icode
,
10922 tree arglist
, rtx target
, int do_load
)
10925 tree arg0
= TREE_VALUE (arglist
);
10926 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
10927 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10928 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
10931 || GET_MODE (target
) != tmode
10932 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10933 target
= gen_reg_rtx (tmode
);
10935 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
10938 if (VECTOR_MODE_P (mode0
))
10939 op0
= safe_vector_operand (op0
, mode0
);
10941 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10942 op0
= copy_to_mode_reg (mode0
, op0
);
10945 pat
= GEN_FCN (icode
) (target
, op0
);
10952 /* Expand an expression EXP that calls a built-in function,
10953 with result going to TARGET if that's convenient
10954 (and in mode MODE if that's convenient).
10955 SUBTARGET may be used as the target for computing one of EXP's operands.
10956 IGNORE is nonzero if the value is to be ignored. */
10959 arm_expand_builtin (tree exp
,
10961 rtx subtarget ATTRIBUTE_UNUSED
,
10962 enum machine_mode mode ATTRIBUTE_UNUSED
,
10963 int ignore ATTRIBUTE_UNUSED
)
10965 const struct builtin_description
* d
;
10966 enum insn_code icode
;
10967 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
10968 tree arglist
= TREE_OPERAND (exp
, 1);
10976 int fcode
= DECL_FUNCTION_CODE (fndecl
);
10978 enum machine_mode tmode
;
10979 enum machine_mode mode0
;
10980 enum machine_mode mode1
;
10981 enum machine_mode mode2
;
10985 case ARM_BUILTIN_TEXTRMSB
:
10986 case ARM_BUILTIN_TEXTRMUB
:
10987 case ARM_BUILTIN_TEXTRMSH
:
10988 case ARM_BUILTIN_TEXTRMUH
:
10989 case ARM_BUILTIN_TEXTRMSW
:
10990 case ARM_BUILTIN_TEXTRMUW
:
10991 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
10992 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
10993 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
10994 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
10995 : CODE_FOR_iwmmxt_textrmw
);
10997 arg0
= TREE_VALUE (arglist
);
10998 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
10999 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11000 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11001 tmode
= insn_data
[icode
].operand
[0].mode
;
11002 mode0
= insn_data
[icode
].operand
[1].mode
;
11003 mode1
= insn_data
[icode
].operand
[2].mode
;
11005 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11006 op0
= copy_to_mode_reg (mode0
, op0
);
11007 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11009 /* @@@ better error message */
11010 error ("selector must be an immediate");
11011 return gen_reg_rtx (tmode
);
11014 || GET_MODE (target
) != tmode
11015 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11016 target
= gen_reg_rtx (tmode
);
11017 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
11023 case ARM_BUILTIN_TINSRB
:
11024 case ARM_BUILTIN_TINSRH
:
11025 case ARM_BUILTIN_TINSRW
:
11026 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
11027 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
11028 : CODE_FOR_iwmmxt_tinsrw
);
11029 arg0
= TREE_VALUE (arglist
);
11030 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11031 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
11032 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11033 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11034 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
11035 tmode
= insn_data
[icode
].operand
[0].mode
;
11036 mode0
= insn_data
[icode
].operand
[1].mode
;
11037 mode1
= insn_data
[icode
].operand
[2].mode
;
11038 mode2
= insn_data
[icode
].operand
[3].mode
;
11040 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11041 op0
= copy_to_mode_reg (mode0
, op0
);
11042 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11043 op1
= copy_to_mode_reg (mode1
, op1
);
11044 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
11046 /* @@@ better error message */
11047 error ("selector must be an immediate");
11051 || GET_MODE (target
) != tmode
11052 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11053 target
= gen_reg_rtx (tmode
);
11054 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
11060 case ARM_BUILTIN_SETWCX
:
11061 arg0
= TREE_VALUE (arglist
);
11062 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11063 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11064 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11065 emit_insn (gen_iwmmxt_tmcr (op0
, op1
));
11068 case ARM_BUILTIN_GETWCX
:
11069 arg0
= TREE_VALUE (arglist
);
11070 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11071 target
= gen_reg_rtx (SImode
);
11072 emit_insn (gen_iwmmxt_tmrc (target
, op0
));
11075 case ARM_BUILTIN_WSHUFH
:
11076 icode
= CODE_FOR_iwmmxt_wshufh
;
11077 arg0
= TREE_VALUE (arglist
);
11078 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11079 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11080 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11081 tmode
= insn_data
[icode
].operand
[0].mode
;
11082 mode1
= insn_data
[icode
].operand
[1].mode
;
11083 mode2
= insn_data
[icode
].operand
[2].mode
;
11085 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
11086 op0
= copy_to_mode_reg (mode1
, op0
);
11087 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
11089 /* @@@ better error message */
11090 error ("mask must be an immediate");
11094 || GET_MODE (target
) != tmode
11095 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11096 target
= gen_reg_rtx (tmode
);
11097 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
11103 case ARM_BUILTIN_WSADB
:
11104 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb
, arglist
, target
);
11105 case ARM_BUILTIN_WSADH
:
11106 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh
, arglist
, target
);
11107 case ARM_BUILTIN_WSADBZ
:
11108 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, arglist
, target
);
11109 case ARM_BUILTIN_WSADHZ
:
11110 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, arglist
, target
);
11112 /* Several three-argument builtins. */
11113 case ARM_BUILTIN_WMACS
:
11114 case ARM_BUILTIN_WMACU
:
11115 case ARM_BUILTIN_WALIGN
:
11116 case ARM_BUILTIN_TMIA
:
11117 case ARM_BUILTIN_TMIAPH
:
11118 case ARM_BUILTIN_TMIATT
:
11119 case ARM_BUILTIN_TMIATB
:
11120 case ARM_BUILTIN_TMIABT
:
11121 case ARM_BUILTIN_TMIABB
:
11122 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
11123 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
11124 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
11125 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
11126 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
11127 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
11128 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
11129 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
11130 : CODE_FOR_iwmmxt_walign
);
11131 arg0
= TREE_VALUE (arglist
);
11132 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11133 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
11134 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11135 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11136 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
11137 tmode
= insn_data
[icode
].operand
[0].mode
;
11138 mode0
= insn_data
[icode
].operand
[1].mode
;
11139 mode1
= insn_data
[icode
].operand
[2].mode
;
11140 mode2
= insn_data
[icode
].operand
[3].mode
;
11142 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11143 op0
= copy_to_mode_reg (mode0
, op0
);
11144 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11145 op1
= copy_to_mode_reg (mode1
, op1
);
11146 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
11147 op2
= copy_to_mode_reg (mode2
, op2
);
11149 || GET_MODE (target
) != tmode
11150 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11151 target
= gen_reg_rtx (tmode
);
11152 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
11158 case ARM_BUILTIN_WZERO
:
11159 target
= gen_reg_rtx (DImode
);
11160 emit_insn (gen_iwmmxt_clrdi (target
));
11167 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
11168 if (d
->code
== (const enum arm_builtins
) fcode
)
11169 return arm_expand_binop_builtin (d
->icode
, arglist
, target
);
11171 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
11172 if (d
->code
== (const enum arm_builtins
) fcode
)
11173 return arm_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
11175 /* @@@ Should really do something sensible here. */
11179 /* Recursively search through all of the blocks in a function
11180 checking to see if any of the variables created in that
11181 function match the RTX called 'orig'. If they do then
11182 replace them with the RTX called 'new'. */
11184 replace_symbols_in_block (tree block
, rtx orig
, rtx
new)
11186 for (; block
; block
= BLOCK_CHAIN (block
))
11190 if (!TREE_USED (block
))
11193 for (sym
= BLOCK_VARS (block
); sym
; sym
= TREE_CHAIN (sym
))
11195 if ( (DECL_NAME (sym
) == 0 && TREE_CODE (sym
) != TYPE_DECL
)
11196 || DECL_IGNORED_P (sym
)
11197 || TREE_CODE (sym
) != VAR_DECL
11198 || DECL_EXTERNAL (sym
)
11199 || !rtx_equal_p (DECL_RTL (sym
), orig
)
11203 SET_DECL_RTL (sym
, new);
11206 replace_symbols_in_block (BLOCK_SUBBLOCKS (block
), orig
, new);
11210 /* Return the number (counting from 0) of
11211 the least significant set bit in MASK. */
11214 number_of_first_bit_set (int mask
)
11219 (mask
& (1 << bit
)) == 0;
11226 /* Generate code to return from a thumb function.
11227 If 'reg_containing_return_addr' is -1, then the return address is
11228 actually on the stack, at the stack pointer. */
11230 thumb_exit (FILE *f
, int reg_containing_return_addr
, rtx eh_ofs
)
11232 unsigned regs_available_for_popping
;
11233 unsigned regs_to_pop
;
11235 unsigned available
;
11239 int restore_a4
= FALSE
;
11241 /* Compute the registers we need to pop. */
11245 /* There is an assumption here, that if eh_ofs is not NULL, the
11246 normal return address will have been pushed. */
11247 if (reg_containing_return_addr
== -1 || eh_ofs
)
11249 /* When we are generating a return for __builtin_eh_return,
11250 reg_containing_return_addr must specify the return regno. */
11251 if (eh_ofs
&& reg_containing_return_addr
== -1)
11254 regs_to_pop
|= 1 << LR_REGNUM
;
11258 if (TARGET_BACKTRACE
)
11260 /* Restore the (ARM) frame pointer and stack pointer. */
11261 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
11265 /* If there is nothing to pop then just emit the BX instruction and
11267 if (pops_needed
== 0)
11270 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
11272 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
11275 /* Otherwise if we are not supporting interworking and we have not created
11276 a backtrace structure and the function was not entered in ARM mode then
11277 just pop the return address straight into the PC. */
11278 else if (!TARGET_INTERWORK
11279 && !TARGET_BACKTRACE
11280 && !is_called_in_ARM_mode (current_function_decl
))
11284 asm_fprintf (f
, "\tadd\t%r, #4\n", SP_REGNUM
);
11285 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
11286 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
11289 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
11294 /* Find out how many of the (return) argument registers we can corrupt. */
11295 regs_available_for_popping
= 0;
11297 /* If returning via __builtin_eh_return, the bottom three registers
11298 all contain information needed for the return. */
11304 /* If we can deduce the registers used from the function's
11305 return value. This is more reliable that examining
11306 regs_ever_live[] because that will be set if the register is
11307 ever used in the function, not just if the register is used
11308 to hold a return value. */
11310 if (current_function_return_rtx
!= 0)
11311 mode
= GET_MODE (current_function_return_rtx
);
11314 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
11316 size
= GET_MODE_SIZE (mode
);
11320 /* In a void function we can use any argument register.
11321 In a function that returns a structure on the stack
11322 we can use the second and third argument registers. */
11323 if (mode
== VOIDmode
)
11324 regs_available_for_popping
=
11325 (1 << ARG_REGISTER (1))
11326 | (1 << ARG_REGISTER (2))
11327 | (1 << ARG_REGISTER (3));
11329 regs_available_for_popping
=
11330 (1 << ARG_REGISTER (2))
11331 | (1 << ARG_REGISTER (3));
11333 else if (size
<= 4)
11334 regs_available_for_popping
=
11335 (1 << ARG_REGISTER (2))
11336 | (1 << ARG_REGISTER (3));
11337 else if (size
<= 8)
11338 regs_available_for_popping
=
11339 (1 << ARG_REGISTER (3));
11342 /* Match registers to be popped with registers into which we pop them. */
11343 for (available
= regs_available_for_popping
,
11344 required
= regs_to_pop
;
11345 required
!= 0 && available
!= 0;
11346 available
&= ~(available
& - available
),
11347 required
&= ~(required
& - required
))
11350 /* If we have any popping registers left over, remove them. */
11352 regs_available_for_popping
&= ~available
;
11354 /* Otherwise if we need another popping register we can use
11355 the fourth argument register. */
11356 else if (pops_needed
)
11358 /* If we have not found any free argument registers and
11359 reg a4 contains the return address, we must move it. */
11360 if (regs_available_for_popping
== 0
11361 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
11363 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
11364 reg_containing_return_addr
= LR_REGNUM
;
11366 else if (size
> 12)
11368 /* Register a4 is being used to hold part of the return value,
11369 but we have dire need of a free, low register. */
11372 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
11375 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
11377 /* The fourth argument register is available. */
11378 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
11384 /* Pop as many registers as we can. */
11385 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
11387 /* Process the registers we popped. */
11388 if (reg_containing_return_addr
== -1)
11390 /* The return address was popped into the lowest numbered register. */
11391 regs_to_pop
&= ~(1 << LR_REGNUM
);
11393 reg_containing_return_addr
=
11394 number_of_first_bit_set (regs_available_for_popping
);
11396 /* Remove this register for the mask of available registers, so that
11397 the return address will not be corrupted by further pops. */
11398 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
11401 /* If we popped other registers then handle them here. */
11402 if (regs_available_for_popping
)
11406 /* Work out which register currently contains the frame pointer. */
11407 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
11409 /* Move it into the correct place. */
11410 asm_fprintf (f
, "\tmov\t%r, %r\n",
11411 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
11413 /* (Temporarily) remove it from the mask of popped registers. */
11414 regs_available_for_popping
&= ~(1 << frame_pointer
);
11415 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
11417 if (regs_available_for_popping
)
11421 /* We popped the stack pointer as well,
11422 find the register that contains it. */
11423 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
11425 /* Move it into the stack register. */
11426 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
11428 /* At this point we have popped all necessary registers, so
11429 do not worry about restoring regs_available_for_popping
11430 to its correct value:
11432 assert (pops_needed == 0)
11433 assert (regs_available_for_popping == (1 << frame_pointer))
11434 assert (regs_to_pop == (1 << STACK_POINTER)) */
11438 /* Since we have just move the popped value into the frame
11439 pointer, the popping register is available for reuse, and
11440 we know that we still have the stack pointer left to pop. */
11441 regs_available_for_popping
|= (1 << frame_pointer
);
11445 /* If we still have registers left on the stack, but we no longer have
11446 any registers into which we can pop them, then we must move the return
11447 address into the link register and make available the register that
11449 if (regs_available_for_popping
== 0 && pops_needed
> 0)
11451 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
11453 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
11454 reg_containing_return_addr
);
11456 reg_containing_return_addr
= LR_REGNUM
;
11459 /* If we have registers left on the stack then pop some more.
11460 We know that at most we will want to pop FP and SP. */
11461 if (pops_needed
> 0)
11466 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
11468 /* We have popped either FP or SP.
11469 Move whichever one it is into the correct register. */
11470 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
11471 move_to
= number_of_first_bit_set (regs_to_pop
);
11473 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
11475 regs_to_pop
&= ~(1 << move_to
);
11480 /* If we still have not popped everything then we must have only
11481 had one register available to us and we are now popping the SP. */
11482 if (pops_needed
> 0)
11486 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
11488 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
11490 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
11492 assert (regs_to_pop == (1 << STACK_POINTER))
11493 assert (pops_needed == 1)
11497 /* If necessary restore the a4 register. */
11500 if (reg_containing_return_addr
!= LR_REGNUM
)
11502 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
11503 reg_containing_return_addr
= LR_REGNUM
;
11506 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
11510 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
11512 /* Return to caller. */
11513 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
11516 /* Emit code to push or pop registers to or from the stack. */
11518 thumb_pushpop (FILE *f
, int mask
, int push
)
11521 int lo_mask
= mask
& 0xFF;
11523 if (lo_mask
== 0 && !push
&& (mask
& (1 << 15)))
11525 /* Special case. Do not generate a POP PC statement here, do it in
11527 thumb_exit (f
, -1, NULL_RTX
);
11531 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
11533 /* Look at the low registers first. */
11534 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
11538 asm_fprintf (f
, "%r", regno
);
11540 if ((lo_mask
& ~1) != 0)
11545 if (push
&& (mask
& (1 << LR_REGNUM
)))
11547 /* Catch pushing the LR. */
11551 asm_fprintf (f
, "%r", LR_REGNUM
);
11553 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
11555 /* Catch popping the PC. */
11556 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
)
11558 /* The PC is never poped directly, instead
11559 it is popped into r3 and then BX is used. */
11560 fprintf (f
, "}\n");
11562 thumb_exit (f
, -1, NULL_RTX
);
11571 asm_fprintf (f
, "%r", PC_REGNUM
);
11575 fprintf (f
, "}\n");
11579 thumb_final_prescan_insn (rtx insn
)
11581 if (flag_print_asm_name
)
11582 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
11583 INSN_ADDRESSES (INSN_UID (insn
)));
11587 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
11589 unsigned HOST_WIDE_INT mask
= 0xff;
11592 if (val
== 0) /* XXX */
11595 for (i
= 0; i
< 25; i
++)
11596 if ((val
& (mask
<< i
)) == val
)
11602 /* Returns nonzero if the current function contains,
11603 or might contain a far jump. */
11605 thumb_far_jump_used_p (int in_prologue
)
11609 /* This test is only important for leaf functions. */
11610 /* assert (!leaf_function_p ()); */
11612 /* If we have already decided that far jumps may be used,
11613 do not bother checking again, and always return true even if
11614 it turns out that they are not being used. Once we have made
11615 the decision that far jumps are present (and that hence the link
11616 register will be pushed onto the stack) we cannot go back on it. */
11617 if (cfun
->machine
->far_jump_used
)
11620 /* If this function is not being called from the prologue/epilogue
11621 generation code then it must be being called from the
11622 INITIAL_ELIMINATION_OFFSET macro. */
11625 /* In this case we know that we are being asked about the elimination
11626 of the arg pointer register. If that register is not being used,
11627 then there are no arguments on the stack, and we do not have to
11628 worry that a far jump might force the prologue to push the link
11629 register, changing the stack offsets. In this case we can just
11630 return false, since the presence of far jumps in the function will
11631 not affect stack offsets.
11633 If the arg pointer is live (or if it was live, but has now been
11634 eliminated and so set to dead) then we do have to test to see if
11635 the function might contain a far jump. This test can lead to some
11636 false negatives, since before reload is completed, then length of
11637 branch instructions is not known, so gcc defaults to returning their
11638 longest length, which in turn sets the far jump attribute to true.
11640 A false negative will not result in bad code being generated, but it
11641 will result in a needless push and pop of the link register. We
11642 hope that this does not occur too often. */
11643 if (regs_ever_live
[ARG_POINTER_REGNUM
])
11644 cfun
->machine
->arg_pointer_live
= 1;
11645 else if (!cfun
->machine
->arg_pointer_live
)
11649 /* Check to see if the function contains a branch
11650 insn with the far jump attribute set. */
11651 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11653 if (GET_CODE (insn
) == JUMP_INSN
11654 /* Ignore tablejump patterns. */
11655 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
11656 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
11657 && get_attr_far_jump (insn
) == FAR_JUMP_YES
11660 /* Record the fact that we have decided that
11661 the function does use far jumps. */
11662 cfun
->machine
->far_jump_used
= 1;
11670 /* Return nonzero if FUNC must be entered in ARM mode. */
11672 is_called_in_ARM_mode (tree func
)
11674 if (TREE_CODE (func
) != FUNCTION_DECL
)
11677 /* Ignore the problem about functions whoes address is taken. */
11678 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
11682 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
11688 /* The bits which aren't usefully expanded as rtl. */
11690 thumb_unexpanded_epilogue (void)
11693 int live_regs_mask
= 0;
11694 int high_regs_pushed
= 0;
11695 int leaf_function
= leaf_function_p ();
11696 int had_to_push_lr
;
11697 rtx eh_ofs
= cfun
->machine
->eh_epilogue_sp_ofs
;
11699 if (return_used_this_function
)
11702 if (IS_NAKED (arm_current_func_type ()))
11705 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
11706 if (THUMB_REG_PUSHED_P (regno
))
11707 live_regs_mask
|= 1 << regno
;
11709 for (regno
= 8; regno
< 13; regno
++)
11710 if (THUMB_REG_PUSHED_P (regno
))
11711 high_regs_pushed
++;
11713 /* The prolog may have pushed some high registers to use as
11714 work registers. eg the testsuite file:
11715 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
11716 compiles to produce:
11717 push {r4, r5, r6, r7, lr}
11721 as part of the prolog. We have to undo that pushing here. */
11723 if (high_regs_pushed
)
11725 int mask
= live_regs_mask
;
11731 /* If we can deduce the registers used from the function's return value.
11732 This is more reliable that examining regs_ever_live[] because that
11733 will be set if the register is ever used in the function, not just if
11734 the register is used to hold a return value. */
11736 if (current_function_return_rtx
!= 0)
11737 mode
= GET_MODE (current_function_return_rtx
);
11740 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
11742 size
= GET_MODE_SIZE (mode
);
11744 /* Unless we are returning a type of size > 12 register r3 is
11750 /* Oh dear! We have no low registers into which we can pop
11753 ("no low registers available for popping high registers");
11755 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
11756 if (THUMB_REG_PUSHED_P (next_hi_reg
))
11759 while (high_regs_pushed
)
11761 /* Find lo register(s) into which the high register(s) can
11763 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
11765 if (mask
& (1 << regno
))
11766 high_regs_pushed
--;
11767 if (high_regs_pushed
== 0)
11771 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
11773 /* Pop the values into the low register(s). */
11774 thumb_pushpop (asm_out_file
, mask
, 0);
11776 /* Move the value(s) into the high registers. */
11777 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
11779 if (mask
& (1 << regno
))
11781 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
11784 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
11785 if (THUMB_REG_PUSHED_P (next_hi_reg
))
11792 had_to_push_lr
= (live_regs_mask
|| !leaf_function
11793 || thumb_far_jump_used_p (1));
11795 if (TARGET_BACKTRACE
11796 && ((live_regs_mask
& 0xFF) == 0)
11797 && regs_ever_live
[LAST_ARG_REGNUM
] != 0)
11799 /* The stack backtrace structure creation code had to
11800 push R7 in order to get a work register, so we pop
11802 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
11805 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
11808 && !is_called_in_ARM_mode (current_function_decl
)
11810 live_regs_mask
|= 1 << PC_REGNUM
;
11812 /* Either no argument registers were pushed or a backtrace
11813 structure was created which includes an adjusted stack
11814 pointer, so just pop everything. */
11815 if (live_regs_mask
)
11816 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
);
11819 thumb_exit (asm_out_file
, 2, eh_ofs
);
11820 /* We have either just popped the return address into the
11821 PC or it is was kept in LR for the entire function or
11822 it is still on the stack because we do not want to
11823 return by doing a pop {pc}. */
11824 else if ((live_regs_mask
& (1 << PC_REGNUM
)) == 0)
11825 thumb_exit (asm_out_file
,
11827 && is_called_in_ARM_mode (current_function_decl
)) ?
11828 -1 : LR_REGNUM
, NULL_RTX
);
11832 /* Pop everything but the return address. */
11833 live_regs_mask
&= ~(1 << PC_REGNUM
);
11835 if (live_regs_mask
)
11836 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
);
11838 if (had_to_push_lr
)
11839 /* Get the return address into a temporary register. */
11840 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0);
11842 /* Remove the argument registers that were pushed onto the stack. */
11843 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
11844 SP_REGNUM
, SP_REGNUM
,
11845 current_function_pretend_args_size
);
11848 thumb_exit (asm_out_file
, 2, eh_ofs
);
11850 thumb_exit (asm_out_file
,
11851 had_to_push_lr
? LAST_ARG_REGNUM
: LR_REGNUM
, NULL_RTX
);
11857 /* Functions to save and restore machine-specific function data. */
11858 static struct machine_function
*
11859 arm_init_machine_status (void)
11861 struct machine_function
*machine
;
11862 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
11864 #if ARM_FT_UNKNOWN != 0
11865 machine
->func_type
= ARM_FT_UNKNOWN
;
11870 /* Return an RTX indicating where the return address to the
11871 calling function can be found. */
11873 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
11878 if (TARGET_APCS_32
)
11879 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
11882 rtx lr
= gen_rtx_AND (Pmode
, gen_rtx_REG (Pmode
, LR_REGNUM
),
11883 GEN_INT (RETURN_ADDR_MASK26
));
11884 return get_func_hard_reg_initial_val (cfun
, lr
);
11888 /* Do anything needed before RTL is emitted for each function. */
11890 arm_init_expanders (void)
11892 /* Arrange to initialize and mark the machine per-function status. */
11893 init_machine_status
= arm_init_machine_status
;
11897 thumb_get_frame_size (void)
11901 int base_size
= ROUND_UP_WORD (get_frame_size ());
11902 int count_regs
= 0;
11903 int entry_size
= 0;
11906 if (! TARGET_THUMB
)
11909 if (! TARGET_ATPCS
)
11912 /* We need to know if we are a leaf function. Unfortunately, it
11913 is possible to be called after start_sequence has been called,
11914 which causes get_insns to return the insns for the sequence,
11915 not the function, which will cause leaf_function_p to return
11916 the incorrect result.
11918 To work around this, we cache the computed frame size. This
11919 works because we will only be calling RTL expanders that need
11920 to know about leaf functions once reload has completed, and the
11921 frame size cannot be changed after that time, so we can safely
11922 use the cached value. */
11924 if (reload_completed
)
11925 return cfun
->machine
->frame_size
;
11927 leaf
= leaf_function_p ();
11929 /* A leaf function does not need any stack alignment if it has nothing
11931 if (leaf
&& base_size
== 0)
11933 cfun
->machine
->frame_size
= 0;
11937 /* We know that SP will be word aligned on entry, and we must
11938 preserve that condition at any subroutine call. But those are
11939 the only constraints. */
11941 /* Space for variadic functions. */
11942 if (current_function_pretend_args_size
)
11943 entry_size
+= current_function_pretend_args_size
;
11945 /* Space for pushed lo registers. */
11946 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
11947 if (THUMB_REG_PUSHED_P (regno
))
11950 /* Space for backtrace structure. */
11951 if (TARGET_BACKTRACE
)
11953 if (count_regs
== 0 && regs_ever_live
[LAST_ARG_REGNUM
] != 0)
11959 if (count_regs
|| !leaf
|| thumb_far_jump_used_p (1))
11960 count_regs
++; /* LR */
11962 entry_size
+= count_regs
* 4;
11965 /* Space for pushed hi regs. */
11966 for (regno
= 8; regno
< 13; regno
++)
11967 if (THUMB_REG_PUSHED_P (regno
))
11970 entry_size
+= count_regs
* 4;
11972 if ((entry_size
+ base_size
+ current_function_outgoing_args_size
) & 7)
11974 if ((entry_size
+ base_size
+ current_function_outgoing_args_size
) & 7)
11977 cfun
->machine
->frame_size
= base_size
;
11982 /* Generate the rest of a function's prologue. */
11984 thumb_expand_prologue (void)
11986 HOST_WIDE_INT amount
= (thumb_get_frame_size ()
11987 + current_function_outgoing_args_size
);
11988 unsigned long func_type
;
11990 func_type
= arm_current_func_type ();
11992 /* Naked functions don't have prologues. */
11993 if (IS_NAKED (func_type
))
11996 if (IS_INTERRUPT (func_type
))
11998 error ("interrupt Service Routines cannot be coded in Thumb mode");
12002 if (frame_pointer_needed
)
12003 emit_insn (gen_movsi (hard_frame_pointer_rtx
, stack_pointer_rtx
));
12007 amount
= ROUND_UP_WORD (amount
);
12010 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
12011 GEN_INT (- amount
)));
12017 /* The stack decrement is too big for an immediate value in a single
12018 insn. In theory we could issue multiple subtracts, but after
12019 three of them it becomes more space efficient to place the full
12020 value in the constant pool and load into a register. (Also the
12021 ARM debugger really likes to see only one stack decrement per
12022 function). So instead we look for a scratch register into which
12023 we can load the decrement, and then we subtract this from the
12024 stack pointer. Unfortunately on the thumb the only available
12025 scratch registers are the argument registers, and we cannot use
12026 these as they may hold arguments to the function. Instead we
12027 attempt to locate a call preserved register which is used by this
12028 function. If we can find one, then we know that it will have
12029 been pushed at the start of the prologue and so we can corrupt
12031 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
12032 if (THUMB_REG_PUSHED_P (regno
)
12033 && !(frame_pointer_needed
12034 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
12037 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
12039 rtx spare
= gen_rtx (REG
, SImode
, IP_REGNUM
);
12041 /* Choose an arbitrary, non-argument low register. */
12042 reg
= gen_rtx (REG
, SImode
, LAST_LO_REGNUM
);
12044 /* Save it by copying it into a high, scratch register. */
12045 emit_insn (gen_movsi (spare
, reg
));
12046 /* Add a USE to stop propagate_one_insn() from barfing. */
12047 emit_insn (gen_prologue_use (spare
));
12049 /* Decrement the stack. */
12050 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
12051 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
12054 /* Restore the low register's original value. */
12055 emit_insn (gen_movsi (reg
, spare
));
12057 /* Emit a USE of the restored scratch register, so that flow
12058 analysis will not consider the restore redundant. The
12059 register won't be used again in this function and isn't
12060 restored by the epilogue. */
12061 emit_insn (gen_prologue_use (reg
));
12065 reg
= gen_rtx (REG
, SImode
, regno
);
12067 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
12068 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
12074 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
12075 emit_insn (gen_blockage ());
12079 thumb_expand_epilogue (void)
12081 HOST_WIDE_INT amount
= (thumb_get_frame_size ()
12082 + current_function_outgoing_args_size
);
12084 /* Naked functions don't have prologues. */
12085 if (IS_NAKED (arm_current_func_type ()))
12088 if (frame_pointer_needed
)
12089 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
12092 amount
= ROUND_UP_WORD (amount
);
12095 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
12096 GEN_INT (amount
)));
12099 /* r3 is always free in the epilogue. */
12100 rtx reg
= gen_rtx (REG
, SImode
, LAST_ARG_REGNUM
);
12102 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
12103 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
12107 /* Emit a USE (stack_pointer_rtx), so that
12108 the stack adjustment will not be deleted. */
12109 emit_insn (gen_prologue_use (stack_pointer_rtx
));
12111 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
12112 emit_insn (gen_blockage ());
12116 thumb_output_function_prologue (FILE *f
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
12118 int live_regs_mask
= 0;
12119 int high_regs_pushed
= 0;
12122 if (IS_NAKED (arm_current_func_type ()))
12125 if (is_called_in_ARM_mode (current_function_decl
))
12129 if (GET_CODE (DECL_RTL (current_function_decl
)) != MEM
)
12131 if (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0)) != SYMBOL_REF
)
12133 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
12135 /* Generate code sequence to switch us into Thumb mode. */
12136 /* The .code 32 directive has already been emitted by
12137 ASM_DECLARE_FUNCTION_NAME. */
12138 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
12139 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
12141 /* Generate a label, so that the debugger will notice the
12142 change in instruction sets. This label is also used by
12143 the assembler to bypass the ARM code when this function
12144 is called from a Thumb encoded function elsewhere in the
12145 same file. Hence the definition of STUB_NAME here must
12146 agree with the definition in gas/config/tc-arm.c */
12148 #define STUB_NAME ".real_start_of"
12150 fprintf (f
, "\t.code\t16\n");
12152 if (arm_dllexport_name_p (name
))
12153 name
= arm_strip_name_encoding (name
);
12155 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
12156 fprintf (f
, "\t.thumb_func\n");
12157 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
12160 if (current_function_pretend_args_size
)
12162 if (cfun
->machine
->uses_anonymous_args
)
12166 fprintf (f
, "\tpush\t{");
12168 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
12170 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
12171 regno
<= LAST_ARG_REGNUM
;
12173 asm_fprintf (f
, "%r%s", regno
,
12174 regno
== LAST_ARG_REGNUM
? "" : ", ");
12176 fprintf (f
, "}\n");
12179 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
12180 SP_REGNUM
, SP_REGNUM
,
12181 current_function_pretend_args_size
);
12184 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
12185 if (THUMB_REG_PUSHED_P (regno
))
12186 live_regs_mask
|= 1 << regno
;
12188 if (live_regs_mask
|| !leaf_function_p () || thumb_far_jump_used_p (1))
12189 live_regs_mask
|= 1 << LR_REGNUM
;
12191 if (TARGET_BACKTRACE
)
12194 int work_register
= 0;
12197 /* We have been asked to create a stack backtrace structure.
12198 The code looks like this:
12202 0 sub SP, #16 Reserve space for 4 registers.
12203 2 push {R7} Get a work register.
12204 4 add R7, SP, #20 Get the stack pointer before the push.
12205 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
12206 8 mov R7, PC Get hold of the start of this code plus 12.
12207 10 str R7, [SP, #16] Store it.
12208 12 mov R7, FP Get hold of the current frame pointer.
12209 14 str R7, [SP, #4] Store it.
12210 16 mov R7, LR Get hold of the current return address.
12211 18 str R7, [SP, #12] Store it.
12212 20 add R7, SP, #16 Point at the start of the backtrace structure.
12213 22 mov FP, R7 Put this value into the frame pointer. */
12215 if ((live_regs_mask
& 0xFF) == 0)
12217 /* See if the a4 register is free. */
12219 if (regs_ever_live
[LAST_ARG_REGNUM
] == 0)
12220 work_register
= LAST_ARG_REGNUM
;
12221 else /* We must push a register of our own */
12222 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
12225 if (work_register
== 0)
12227 /* Select a register from the list that will be pushed to
12228 use as our work register. */
12229 for (work_register
= (LAST_LO_REGNUM
+ 1); work_register
--;)
12230 if ((1 << work_register
) & live_regs_mask
)
12235 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
12236 SP_REGNUM
, SP_REGNUM
);
12238 if (live_regs_mask
)
12239 thumb_pushpop (f
, live_regs_mask
, 1);
12241 for (offset
= 0, wr
= 1 << 15; wr
!= 0; wr
>>= 1)
12242 if (wr
& live_regs_mask
)
12245 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
12246 offset
+ 16 + current_function_pretend_args_size
);
12248 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
12251 /* Make sure that the instruction fetching the PC is in the right place
12252 to calculate "start of backtrace creation code + 12". */
12253 if (live_regs_mask
)
12255 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
12256 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
12258 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
12259 ARM_HARD_FRAME_POINTER_REGNUM
);
12260 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
12265 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
12266 ARM_HARD_FRAME_POINTER_REGNUM
);
12267 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
12269 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
12270 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
12274 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
12275 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
12277 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
12279 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
12280 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
12282 else if (live_regs_mask
)
12283 thumb_pushpop (f
, live_regs_mask
, 1);
12285 for (regno
= 8; regno
< 13; regno
++)
12286 if (THUMB_REG_PUSHED_P (regno
))
12287 high_regs_pushed
++;
12289 if (high_regs_pushed
)
12291 int pushable_regs
= 0;
12292 int mask
= live_regs_mask
& 0xff;
12295 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
12296 if (THUMB_REG_PUSHED_P (next_hi_reg
))
12299 pushable_regs
= mask
;
12301 if (pushable_regs
== 0)
12303 /* Desperation time -- this probably will never happen. */
12304 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM
))
12305 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, LAST_ARG_REGNUM
);
12306 mask
= 1 << LAST_ARG_REGNUM
;
12309 while (high_regs_pushed
> 0)
12311 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
12313 if (mask
& (1 << regno
))
12315 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
12317 high_regs_pushed
--;
12319 if (high_regs_pushed
)
12321 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
12323 if (THUMB_REG_PUSHED_P (next_hi_reg
))
12328 mask
&= ~((1 << regno
) - 1);
12334 thumb_pushpop (f
, mask
, 1);
12337 if (pushable_regs
== 0
12338 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM
)))
12339 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
12343 /* Handle the case of a double word load into a low register from
12344 a computed memory address. The computed address may involve a
12345 register which is overwritten by the load. */
12347 thumb_load_double_from_address (rtx
*operands
)
12355 if (GET_CODE (operands
[0]) != REG
)
12358 if (GET_CODE (operands
[1]) != MEM
)
12361 /* Get the memory address. */
12362 addr
= XEXP (operands
[1], 0);
12364 /* Work out how the memory address is computed. */
12365 switch (GET_CODE (addr
))
12368 operands
[2] = gen_rtx (MEM
, SImode
,
12369 plus_constant (XEXP (operands
[1], 0), 4));
12371 if (REGNO (operands
[0]) == REGNO (addr
))
12373 output_asm_insn ("ldr\t%H0, %2", operands
);
12374 output_asm_insn ("ldr\t%0, %1", operands
);
12378 output_asm_insn ("ldr\t%0, %1", operands
);
12379 output_asm_insn ("ldr\t%H0, %2", operands
);
12384 /* Compute <address> + 4 for the high order load. */
12385 operands
[2] = gen_rtx (MEM
, SImode
,
12386 plus_constant (XEXP (operands
[1], 0), 4));
12388 output_asm_insn ("ldr\t%0, %1", operands
);
12389 output_asm_insn ("ldr\t%H0, %2", operands
);
12393 arg1
= XEXP (addr
, 0);
12394 arg2
= XEXP (addr
, 1);
12396 if (CONSTANT_P (arg1
))
12397 base
= arg2
, offset
= arg1
;
12399 base
= arg1
, offset
= arg2
;
12401 if (GET_CODE (base
) != REG
)
12404 /* Catch the case of <address> = <reg> + <reg> */
12405 if (GET_CODE (offset
) == REG
)
12407 int reg_offset
= REGNO (offset
);
12408 int reg_base
= REGNO (base
);
12409 int reg_dest
= REGNO (operands
[0]);
12411 /* Add the base and offset registers together into the
12412 higher destination register. */
12413 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
12414 reg_dest
+ 1, reg_base
, reg_offset
);
12416 /* Load the lower destination register from the address in
12417 the higher destination register. */
12418 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
12419 reg_dest
, reg_dest
+ 1);
12421 /* Load the higher destination register from its own address
12423 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
12424 reg_dest
+ 1, reg_dest
+ 1);
12428 /* Compute <address> + 4 for the high order load. */
12429 operands
[2] = gen_rtx (MEM
, SImode
,
12430 plus_constant (XEXP (operands
[1], 0), 4));
12432 /* If the computed address is held in the low order register
12433 then load the high order register first, otherwise always
12434 load the low order register first. */
12435 if (REGNO (operands
[0]) == REGNO (base
))
12437 output_asm_insn ("ldr\t%H0, %2", operands
);
12438 output_asm_insn ("ldr\t%0, %1", operands
);
12442 output_asm_insn ("ldr\t%0, %1", operands
);
12443 output_asm_insn ("ldr\t%H0, %2", operands
);
12449 /* With no registers to worry about we can just load the value
12451 operands
[2] = gen_rtx (MEM
, SImode
,
12452 plus_constant (XEXP (operands
[1], 0), 4));
12454 output_asm_insn ("ldr\t%H0, %2", operands
);
12455 output_asm_insn ("ldr\t%0, %1", operands
);
12467 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
12474 if (REGNO (operands
[4]) > REGNO (operands
[5]))
12477 operands
[4] = operands
[5];
12480 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
12481 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
12485 if (REGNO (operands
[4]) > REGNO (operands
[5]))
12488 operands
[4] = operands
[5];
12491 if (REGNO (operands
[5]) > REGNO (operands
[6]))
12494 operands
[5] = operands
[6];
12497 if (REGNO (operands
[4]) > REGNO (operands
[5]))
12500 operands
[4] = operands
[5];
12504 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
12505 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
12515 /* Routines for generating rtl. */
12517 thumb_expand_movstrqi (rtx
*operands
)
12519 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
12520 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
12521 HOST_WIDE_INT len
= INTVAL (operands
[2]);
12522 HOST_WIDE_INT offset
= 0;
12526 emit_insn (gen_movmem12b (out
, in
, out
, in
));
12532 emit_insn (gen_movmem8b (out
, in
, out
, in
));
12538 rtx reg
= gen_reg_rtx (SImode
);
12539 emit_insn (gen_movsi (reg
, gen_rtx (MEM
, SImode
, in
)));
12540 emit_insn (gen_movsi (gen_rtx (MEM
, SImode
, out
), reg
));
12547 rtx reg
= gen_reg_rtx (HImode
);
12548 emit_insn (gen_movhi (reg
, gen_rtx (MEM
, HImode
,
12549 plus_constant (in
, offset
))));
12550 emit_insn (gen_movhi (gen_rtx (MEM
, HImode
, plus_constant (out
, offset
)),
12558 rtx reg
= gen_reg_rtx (QImode
);
12559 emit_insn (gen_movqi (reg
, gen_rtx (MEM
, QImode
,
12560 plus_constant (in
, offset
))));
12561 emit_insn (gen_movqi (gen_rtx (MEM
, QImode
, plus_constant (out
, offset
)),
12567 thumb_cmp_operand (rtx op
, enum machine_mode mode
)
12569 return ((GET_CODE (op
) == CONST_INT
12570 && (unsigned HOST_WIDE_INT
) (INTVAL (op
)) < 256)
12571 || register_operand (op
, mode
));
12574 static const char *
12575 thumb_condition_code (rtx x
, int invert
)
12577 static const char * const conds
[] =
12579 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
12580 "hi", "ls", "ge", "lt", "gt", "le"
12584 switch (GET_CODE (x
))
12586 case EQ
: val
= 0; break;
12587 case NE
: val
= 1; break;
12588 case GEU
: val
= 2; break;
12589 case LTU
: val
= 3; break;
12590 case GTU
: val
= 8; break;
12591 case LEU
: val
= 9; break;
12592 case GE
: val
= 10; break;
12593 case LT
: val
= 11; break;
12594 case GT
: val
= 12; break;
12595 case LE
: val
= 13; break;
12600 return conds
[val
^ invert
];
12603 /* Handle storing a half-word to memory during reload. */
12605 thumb_reload_out_hi (rtx
*operands
)
12607 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
12610 /* Handle reading a half-word from memory during reload. */
12612 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
12617 /* Return the length of a function name prefix
12618 that starts with the character 'c'. */
12620 arm_get_strip_length (int c
)
12624 ARM_NAME_ENCODING_LENGTHS
12629 /* Return a pointer to a function's name with any
12630 and all prefix encodings stripped from it. */
12632 arm_strip_name_encoding (const char *name
)
12636 while ((skip
= arm_get_strip_length (* name
)))
12642 /* If there is a '*' anywhere in the name's prefix, then
12643 emit the stripped name verbatim, otherwise prepend an
12644 underscore if leading underscores are being used. */
12646 arm_asm_output_labelref (FILE *stream
, const char *name
)
12651 while ((skip
= arm_get_strip_length (* name
)))
12653 verbatim
|= (*name
== '*');
12658 fputs (name
, stream
);
12660 asm_fprintf (stream
, "%U%s", name
);
12665 #ifdef AOF_ASSEMBLER
12666 /* Special functions only needed when producing AOF syntax assembler. */
12670 struct pic_chain
* next
;
12671 const char * symname
;
12674 static struct pic_chain
* aof_pic_chain
= NULL
;
12677 aof_pic_entry (rtx x
)
12679 struct pic_chain
** chainp
;
12682 if (aof_pic_label
== NULL_RTX
)
12684 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
12687 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
12688 offset
+= 4, chainp
= &(*chainp
)->next
)
12689 if ((*chainp
)->symname
== XSTR (x
, 0))
12690 return plus_constant (aof_pic_label
, offset
);
12692 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
12693 (*chainp
)->next
= NULL
;
12694 (*chainp
)->symname
= XSTR (x
, 0);
12695 return plus_constant (aof_pic_label
, offset
);
12699 aof_dump_pic_table (FILE *f
)
12701 struct pic_chain
* chain
;
12703 if (aof_pic_chain
== NULL
)
12706 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
12707 PIC_OFFSET_TABLE_REGNUM
,
12708 PIC_OFFSET_TABLE_REGNUM
);
12709 fputs ("|x$adcons|\n", f
);
12711 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
12713 fputs ("\tDCD\t", f
);
12714 assemble_name (f
, chain
->symname
);
12719 int arm_text_section_count
= 1;
12722 aof_text_section (void )
12724 static char buf
[100];
12725 sprintf (buf
, "\tAREA |C$$code%d|, CODE, READONLY",
12726 arm_text_section_count
++);
12728 strcat (buf
, ", PIC, REENTRANT");
12732 static int arm_data_section_count
= 1;
12735 aof_data_section (void)
12737 static char buf
[100];
12738 sprintf (buf
, "\tAREA |C$$data%d|, DATA", arm_data_section_count
++);
12742 /* The AOF assembler is religiously strict about declarations of
12743 imported and exported symbols, so that it is impossible to declare
12744 a function as imported near the beginning of the file, and then to
12745 export it later on. It is, however, possible to delay the decision
12746 until all the functions in the file have been compiled. To get
12747 around this, we maintain a list of the imports and exports, and
12748 delete from it any that are subsequently defined. At the end of
12749 compilation we spit the remainder of the list out before the END
12754 struct import
* next
;
12758 static struct import
* imports_list
= NULL
;
12761 aof_add_import (const char *name
)
12763 struct import
* new;
12765 for (new = imports_list
; new; new = new->next
)
12766 if (new->name
== name
)
12769 new = (struct import
*) xmalloc (sizeof (struct import
));
12770 new->next
= imports_list
;
12771 imports_list
= new;
12776 aof_delete_import (const char *name
)
12778 struct import
** old
;
12780 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
12782 if ((*old
)->name
== name
)
12784 *old
= (*old
)->next
;
12790 int arm_main_function
= 0;
12793 aof_dump_imports (FILE *f
)
12795 /* The AOF assembler needs this to cause the startup code to be extracted
12796 from the library. Brining in __main causes the whole thing to work
12798 if (arm_main_function
)
12801 fputs ("\tIMPORT __main\n", f
);
12802 fputs ("\tDCD __main\n", f
);
12805 /* Now dump the remaining imports. */
12806 while (imports_list
)
12808 fprintf (f
, "\tIMPORT\t");
12809 assemble_name (f
, imports_list
->name
);
12811 imports_list
= imports_list
->next
;
12816 aof_globalize_label (FILE *stream
, const char *name
)
12818 default_globalize_label (stream
, name
);
12819 if (! strcmp (name
, "main"))
12820 arm_main_function
= 1;
12826 fputs ("__r0\tRN\t0\n", asm_out_file
);
12827 fputs ("__a1\tRN\t0\n", asm_out_file
);
12828 fputs ("__a2\tRN\t1\n", asm_out_file
);
12829 fputs ("__a3\tRN\t2\n", asm_out_file
);
12830 fputs ("__a4\tRN\t3\n", asm_out_file
);
12831 fputs ("__v1\tRN\t4\n", asm_out_file
);
12832 fputs ("__v2\tRN\t5\n", asm_out_file
);
12833 fputs ("__v3\tRN\t6\n", asm_out_file
);
12834 fputs ("__v4\tRN\t7\n", asm_out_file
);
12835 fputs ("__v5\tRN\t8\n", asm_out_file
);
12836 fputs ("__v6\tRN\t9\n", asm_out_file
);
12837 fputs ("__sl\tRN\t10\n", asm_out_file
);
12838 fputs ("__fp\tRN\t11\n", asm_out_file
);
12839 fputs ("__ip\tRN\t12\n", asm_out_file
);
12840 fputs ("__sp\tRN\t13\n", asm_out_file
);
12841 fputs ("__lr\tRN\t14\n", asm_out_file
);
12842 fputs ("__pc\tRN\t15\n", asm_out_file
);
12843 fputs ("__f0\tFN\t0\n", asm_out_file
);
12844 fputs ("__f1\tFN\t1\n", asm_out_file
);
12845 fputs ("__f2\tFN\t2\n", asm_out_file
);
12846 fputs ("__f3\tFN\t3\n", asm_out_file
);
12847 fputs ("__f4\tFN\t4\n", asm_out_file
);
12848 fputs ("__f5\tFN\t5\n", asm_out_file
);
12849 fputs ("__f6\tFN\t6\n", asm_out_file
);
12850 fputs ("__f7\tFN\t7\n", asm_out_file
);
12855 aof_file_end (void)
12858 aof_dump_pic_table (asm_out_file
);
12859 aof_dump_imports (asm_out_file
);
12860 fputs ("\tEND\n", asm_out_file
);
12862 #endif /* AOF_ASSEMBLER */
12864 #ifdef OBJECT_FORMAT_ELF
12865 /* Switch to an arbitrary section NAME with attributes as specified
12866 by FLAGS. ALIGN specifies any known alignment requirements for
12867 the section; 0 if the default should be used.
12869 Differs from the default elf version only in the prefix character
12870 used before the section type. */
12873 arm_elf_asm_named_section (const char *name
, unsigned int flags
)
12875 char flagchars
[10], *f
= flagchars
;
12877 if (! named_section_first_declaration (name
))
12879 fprintf (asm_out_file
, "\t.section\t%s\n", name
);
12883 if (!(flags
& SECTION_DEBUG
))
12885 if (flags
& SECTION_WRITE
)
12887 if (flags
& SECTION_CODE
)
12889 if (flags
& SECTION_SMALL
)
12891 if (flags
& SECTION_MERGE
)
12893 if (flags
& SECTION_STRINGS
)
12895 if (flags
& SECTION_TLS
)
12899 fprintf (asm_out_file
, "\t.section\t%s,\"%s\"", name
, flagchars
);
12901 if (!(flags
& SECTION_NOTYPE
))
12905 if (flags
& SECTION_BSS
)
12910 fprintf (asm_out_file
, ",%%%s", type
);
12912 if (flags
& SECTION_ENTSIZE
)
12913 fprintf (asm_out_file
, ",%d", flags
& SECTION_ENTSIZE
);
12916 putc ('\n', asm_out_file
);
12921 /* Symbols in the text segment can be accessed without indirecting via the
12922 constant pool; it may take an extra binary operation, but this is still
12923 faster than indirecting via memory. Don't do this when not optimizing,
12924 since we won't be calculating al of the offsets necessary to do this
12928 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
12930 /* This doesn't work with AOF syntax, since the string table may be in
12931 a different AREA. */
12932 #ifndef AOF_ASSEMBLER
12933 if (optimize
> 0 && TREE_CONSTANT (decl
)
12934 && (!flag_writable_strings
|| TREE_CODE (decl
) != STRING_CST
))
12935 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
12938 /* If we are referencing a function that is weak then encode a long call
12939 flag in the function name, otherwise if the function is static or
12940 or known to be defined in this file then encode a short call flag. */
12941 if (first
&& TREE_CODE_CLASS (TREE_CODE (decl
)) == 'd')
12943 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
12944 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
12945 else if (! TREE_PUBLIC (decl
))
12946 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
12949 #endif /* !ARM_PE */
12952 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
12954 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
12955 && !strcmp (prefix
, "L"))
12957 arm_ccfsm_state
= 0;
12958 arm_target_insn
= NULL
;
12960 default_internal_label (stream
, prefix
, labelno
);
12963 /* Output code to add DELTA to the first argument, and then jump
12964 to FUNCTION. Used for C++ multiple inheritance. */
12966 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
12967 HOST_WIDE_INT delta
,
12968 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
12971 int mi_delta
= delta
;
12972 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
12974 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
12977 mi_delta
= - mi_delta
;
12978 while (mi_delta
!= 0)
12980 if ((mi_delta
& (3 << shift
)) == 0)
12984 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
12985 mi_op
, this_regno
, this_regno
,
12986 mi_delta
& (0xff << shift
));
12987 mi_delta
&= ~(0xff << shift
);
12991 fputs ("\tb\t", file
);
12992 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
12993 if (NEED_PLT_RELOC
)
12994 fputs ("(PLT)", file
);
12995 fputc ('\n', file
);
12999 arm_emit_vector_const (file
, x
)
13004 const char * pattern
;
13006 if (GET_CODE (x
) != CONST_VECTOR
)
13009 switch (GET_MODE (x
))
13011 case V2SImode
: pattern
= "%08x"; break;
13012 case V4HImode
: pattern
= "%04x"; break;
13013 case V8QImode
: pattern
= "%02x"; break;
13017 fprintf (file
, "0x");
13018 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
13022 element
= CONST_VECTOR_ELT (x
, i
);
13023 fprintf (file
, pattern
, INTVAL (element
));
13030 arm_output_load_gr (operands
)
13038 if (GET_CODE (operands
[1]) != MEM
13039 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
13040 || GET_CODE (reg
= XEXP (sum
, 0)) != REG
13041 || GET_CODE (offset
= XEXP (sum
, 1)) != CONST_INT
13042 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
13043 return "wldrw%?\t%0, %1";
13045 /* Fix up an out-of-range load of a GR register. */
13046 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
13047 wcgr
= operands
[0];
13049 output_asm_insn ("ldr%?\t%0, %1", operands
);
13051 operands
[0] = wcgr
;
13053 output_asm_insn ("tmcr%?\t%0, %1", operands
);
13054 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);