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[gcc.git] / gcc / config / arm / arm.h
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
6
7 This file is part of GNU CC.
8
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
23
24 /* Configuration triples for ARM ports work as follows:
25 (This is a bit of a mess and needs some thought)
26 arm-*-*: little endian
27 armel-*-*: little endian
28 armeb-*-*: big endian
29 If a non-embedded environment (ie: "real" OS) is specified, `arm'
30 should default to that used by the OS.
31 */
32
33 #ifndef __ARM_H__
34 #define __ARM_H__
35
36 #define TARGET_CPU_arm2 0x0000
37 #define TARGET_CPU_arm250 0x0000
38 #define TARGET_CPU_arm3 0x0000
39 #define TARGET_CPU_arm6 0x0001
40 #define TARGET_CPU_arm600 0x0001
41 #define TARGET_CPU_arm610 0x0002
42 #define TARGET_CPU_arm7 0x0001
43 #define TARGET_CPU_arm7m 0x0004
44 #define TARGET_CPU_arm7dm 0x0004
45 #define TARGET_CPU_arm7dmi 0x0004
46 #define TARGET_CPU_arm700 0x0001
47 #define TARGET_CPU_arm710 0x0002
48 #define TARGET_CPU_arm7100 0x0002
49 #define TARGET_CPU_arm7500 0x0002
50 #define TARGET_CPU_arm7500fe 0x1001
51 #define TARGET_CPU_arm7tdmi 0x0008
52 #define TARGET_CPU_arm8 0x0010
53 #define TARGET_CPU_arm810 0x0020
54 #define TARGET_CPU_strongarm 0x0040
55 #define TARGET_CPU_strongarm110 0x0040
56 #define TARGET_CPU_strongarm1100 0x0040
57 #define TARGET_CPU_arm9 0x0080
58 #define TARGET_CPU_arm9tdmi 0x0080
59 /* Configure didn't specify */
60 #define TARGET_CPU_generic 0x8000
61
62 enum arm_cond_code
63 {
64 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
65 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
66 };
67 extern enum arm_cond_code arm_current_cc;
68 extern char *arm_condition_codes[];
69
70 #define ARM_INVERSE_CONDITION_CODE(X) ((enum arm_cond_code) (((int)X) ^ 1))
71
72 /* This is needed by the tail-calling peepholes */
73 extern int frame_pointer_needed;
74
75 \f
76 /* Just in case configure has failed to define anything. */
77 #ifndef TARGET_CPU_DEFAULT
78 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
79 #endif
80
81 /* If the configuration file doesn't specify the cpu, the subtarget may
82 override it. If it doesn't, then default to an ARM6. */
83 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
84 #undef TARGET_CPU_DEFAULT
85 #ifdef SUBTARGET_CPU_DEFAULT
86 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
87 #else
88 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
89 #endif
90 #endif
91
92 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
93 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
94 #else
95 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
96 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
97 #else
98 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
99 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
100 #else
101 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_ARM9
102 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
103 #else
104 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm
105 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
106 #else
107 Unrecognized value in TARGET_CPU_DEFAULT.
108 #endif
109 #endif
110 #endif
111 #endif
112 #endif
113
114 #ifndef CPP_PREDEFINES
115 #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
116 #endif
117
118 #define CPP_SPEC "\
119 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
120 %(cpp_endian) %(subtarget_cpp_spec)"
121
122 /* Set the architecture define -- if -march= is set, then it overrides
123 the -mcpu= setting. */
124 #define CPP_CPU_ARCH_SPEC "\
125 %{m2:-D__arm2__ -D__ARM_ARCH_2__} \
126 %{m3:-D__arm2__ -D__ARM_ARCH_2__} \
127 %{m6:-D__arm6__ -D__ARM_ARCH_3__} \
128 %{march=arm2:-D__ARM_ARCH_2__} \
129 %{march=arm250:-D__ARM_ARCH_2__} \
130 %{march=arm3:-D__ARM_ARCH_2__} \
131 %{march=arm6:-D__ARM_ARCH_3__} \
132 %{march=arm600:-D__ARM_ARCH_3__} \
133 %{march=arm610:-D__ARM_ARCH_3__} \
134 %{march=arm7:-D__ARM_ARCH_3__} \
135 %{march=arm700:-D__ARM_ARCH_3__} \
136 %{march=arm710:-D__ARM_ARCH_3__} \
137 %{march=arm7100:-D__ARM_ARCH_3__} \
138 %{march=arm7500:-D__ARM_ARCH_3__} \
139 %{march=arm7500fe:-D__ARM_ARCH_3__} \
140 %{march=arm7m:-D__ARM_ARCH_3M__} \
141 %{march=arm7dm:-D__ARM_ARCH_3M__} \
142 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
143 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
144 %{march=arm8:-D__ARM_ARCH_4__} \
145 %{march=arm810:-D__ARM_ARCH_4__} \
146 %{march=arm9:-D__ARM_ARCH_4T__} \
147 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
148 %{march=strongarm:-D__ARM_ARCH_4__} \
149 %{march=strongarm110:-D__ARM_ARCH_4__} \
150 %{march=strongarm1100:-D__ARM_ARCH_4__} \
151 %{march=armv2:-D__ARM_ARCH_2__} \
152 %{march=armv2a:-D__ARM_ARCH_2__} \
153 %{march=armv3:-D__ARM_ARCH_3__} \
154 %{march=armv3m:-D__ARM_ARCH_3M__} \
155 %{march=armv4:-D__ARM_ARCH_4__} \
156 %{march=armv4t:-D__ARM_ARCH_4T__} \
157 %{!march=*: \
158 %{mcpu=arm2:-D__ARM_ARCH_2__} \
159 %{mcpu=arm250:-D__ARM_ARCH_2__} \
160 %{mcpu=arm3:-D__ARM_ARCH_2__} \
161 %{mcpu=arm6:-D__ARM_ARCH_3__} \
162 %{mcpu=arm600:-D__ARM_ARCH_3__} \
163 %{mcpu=arm610:-D__ARM_ARCH_3__} \
164 %{mcpu=arm7:-D__ARM_ARCH_3__} \
165 %{mcpu=arm700:-D__ARM_ARCH_3__} \
166 %{mcpu=arm710:-D__ARM_ARCH_3__} \
167 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
168 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
169 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
170 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
171 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
172 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
173 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
174 %{mcpu=arm8:-D__ARM_ARCH_4__} \
175 %{mcpu=arm810:-D__ARM_ARCH_4__} \
176 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
177 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
178 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
179 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
180 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
181 %{!mcpu*:%{!m6:%{!m2:%{!m3:%(cpp_cpu_arch_default)}}}}} \
182 "
183
184 /* Define __APCS_26__ if the PC also contains the PSR */
185 /* This also examines deprecated -m[236] if neither of -mapcs-{26,32} is set,
186 ??? Delete this for 2.9. */
187 #define CPP_APCS_PC_SPEC "\
188 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
189 -D__APCS_32__} \
190 %{mapcs-26:-D__APCS_26__} \
191 %{!mapcs-32: %{!mapcs-26:%{m6:-D__APCS_32__} %{m2:-D__APCS_26__} \
192 %{m3:-D__APCS_26__} %{!m6:%{!m3:%{!m2:%(cpp_apcs_pc_default)}}}}} \
193 "
194
195 #ifndef CPP_APCS_PC_DEFAULT_SPEC
196 #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"
197 #endif
198
199 #define CPP_FLOAT_SPEC "\
200 %{msoft-float:\
201 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
202 -D__SOFTFP__} \
203 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
204 "
205
206 /* Default is hard float, which doesn't define anything */
207 #define CPP_FLOAT_DEFAULT_SPEC ""
208
209 #define CPP_ENDIAN_SPEC "\
210 %{mbig-endian: \
211 %{mlittle-endian: \
212 %e-mbig-endian and -mlittle-endian may not be used together} \
213 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \
214 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
215 "
216
217 /* Default is little endian, which doesn't define anything. */
218 #define CPP_ENDIAN_DEFAULT_SPEC ""
219
220 /* Translate (for now) the old -m[236] option into the appropriate -mcpu=...
221 and -mapcs-xx equivalents.
222 ??? Remove support for this style in 2.9.*/
223 #define CC1_SPEC "\
224 %{m2:-mcpu=arm2 -mapcs-26} \
225 %{m3:-mcpu=arm3 -mapcs-26} \
226 %{m6:-mcpu=arm6 -mapcs-32} \
227 "
228
229 /* This macro defines names of additional specifications to put in the specs
230 that can be used in various specifications like CC1_SPEC. Its definition
231 is an initializer with a subgrouping for each command option.
232
233 Each subgrouping contains a string constant, that defines the
234 specification name, and a string constant that used by the GNU CC driver
235 program.
236
237 Do not define this macro if it does not need to do anything. */
238 #define EXTRA_SPECS \
239 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
240 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
241 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \
242 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \
243 { "cpp_float", CPP_FLOAT_SPEC }, \
244 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \
245 { "cpp_endian", CPP_ENDIAN_SPEC }, \
246 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \
247 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
248 SUBTARGET_EXTRA_SPECS
249
250 #define SUBTARGET_EXTRA_SPECS
251 #define SUBTARGET_CPP_SPEC ""
252
253 \f
254 /* Run-time Target Specification. */
255 #ifndef TARGET_VERSION
256 #define TARGET_VERSION \
257 fputs (" (ARM/generic)", stderr);
258 #endif
259
260 /* Run-time compilation parameters selecting different hardware subsets. */
261 extern int target_flags;
262
263 /* The floating point instruction architecture, can be 2 or 3 */
264 extern char * target_fp_name;
265
266 /* Nonzero if the function prologue (and epilogue) should obey
267 the ARM Procedure Call Standard. */
268 #define ARM_FLAG_APCS_FRAME (0x0001)
269
270 /* Nonzero if the function prologue should output the function name to enable
271 the post mortem debugger to print a backtrace (very useful on RISCOS,
272 unused on RISCiX). Specifying this flag also enables
273 -fno-omit-frame-pointer.
274 XXX Must still be implemented in the prologue. */
275 #define ARM_FLAG_POKE (0x0002)
276
277 /* Nonzero if floating point instructions are emulated by the FPE, in which
278 case instruction scheduling becomes very uninteresting. */
279 #define ARM_FLAG_FPE (0x0004)
280
281 /* Nonzero if destined for an ARM6xx. Takes out bits that assume restoration
282 of condition flags when returning from a branch & link (ie. a function) */
283 /* ********* DEPRECATED ******** */
284 #define ARM_FLAG_ARM6 (0x0008)
285
286 /* ********* DEPRECATED ******** */
287 #define ARM_FLAG_ARM3 (0x0010)
288
289 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
290 that assume restoration of the condition flags when returning from a
291 branch and link (ie a function). */
292 #define ARM_FLAG_APCS_32 (0x0020)
293
294 /* Nonzero if stack checking should be performed on entry to each function
295 which allocates temporary variables on the stack. */
296 #define ARM_FLAG_APCS_STACK (0x0040)
297
298 /* Nonzero if floating point parameters should be passed to functions in
299 floating point registers. */
300 #define ARM_FLAG_APCS_FLOAT (0x0080)
301
302 /* Nonzero if re-entrant, position independent code should be generated.
303 This is equivalent to -fpic. */
304 #define ARM_FLAG_APCS_REENT (0x0100)
305
306 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must be
307 loaded byte-at-a-time. */
308 #define ARM_FLAG_SHORT_BYTE (0x0200)
309
310 /* Nonzero if all floating point instructions are missing (and there is no
311 emulator either). Generate function calls for all ops in this case. */
312 #define ARM_FLAG_SOFT_FLOAT (0x0400)
313
314 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
315 #define ARM_FLAG_BIG_END (0x0800)
316
317 /* Nonzero if we should compile for Thumb interworking. */
318 #define ARM_FLAG_THUMB (0x1000)
319
320 /* Nonzero if we should have little-endian words even when compiling for
321 big-endian (for backwards compatibility with older versions of GCC). */
322 #define ARM_FLAG_LITTLE_WORDS (0x2000)
323
324 /* Nonzero if we need to protect the prolog from scheduling */
325 #define ARM_FLAG_NO_SCHED_PRO (0x4000)
326
327 /* Nonzero if a call to abort should be generated if a noreturn
328 function tries to return. */
329 #define ARM_FLAG_ABORT_NORETURN (0x8000)
330
331 #define TARGET_APCS (target_flags & ARM_FLAG_APCS_FRAME)
332 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
333 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
334 #define TARGET_6 (target_flags & ARM_FLAG_ARM6)
335 #define TARGET_3 (target_flags & ARM_FLAG_ARM3)
336 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
337 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
338 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
339 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
340 #define TARGET_SHORT_BY_BYTES (target_flags & ARM_FLAG_SHORT_BYTE)
341 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
342 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
343 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
344 #define TARGET_THUMB_INTERWORK (target_flags & ARM_FLAG_THUMB)
345 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
346 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
347 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
348
349 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
350 Bit 31 is reserved. See riscix.h. */
351 #ifndef SUBTARGET_SWITCHES
352 #define SUBTARGET_SWITCHES
353 #endif
354
355 #define TARGET_SWITCHES \
356 { \
357 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
358 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
359 "Generate APCS conformant stack frames" }, \
360 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
361 {"poke-function-name", ARM_FLAG_POKE, \
362 "Store function names in object code" }, \
363 {"fpe", ARM_FLAG_FPE, "" }, \
364 {"6", ARM_FLAG_ARM6, "" }, \
365 {"2", ARM_FLAG_ARM3, "" }, \
366 {"3", ARM_FLAG_ARM3, "" }, \
367 {"apcs-32", ARM_FLAG_APCS_32, \
368 "Use the 32bit version of the APCS" }, \
369 {"apcs-26", -ARM_FLAG_APCS_32, \
370 "Use the 26bit version of the APCS" }, \
371 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
372 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
373 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
374 "Pass FP arguments in FP registers" }, \
375 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
376 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
377 "Generate re-entrant, PIC code" }, \
378 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
379 {"short-load-bytes", ARM_FLAG_SHORT_BYTE, \
380 "Load shorts a byte at a time" }, \
381 {"no-short-load-bytes", -ARM_FLAG_SHORT_BYTE, "" }, \
382 {"short-load-words", -ARM_FLAG_SHORT_BYTE, \
383 "Load words a byte at a time" }, \
384 {"no-short-load-words", ARM_FLAG_SHORT_BYTE, "" }, \
385 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
386 "Use library calls to perform FP operations" }, \
387 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
388 "Use hardware floating point instructions" }, \
389 {"big-endian", ARM_FLAG_BIG_END, \
390 "Assume target CPU is configured as big endian" }, \
391 {"little-endian", -ARM_FLAG_BIG_END, \
392 "Assume target CPU is configured as little endian" }, \
393 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
394 "Assume big endian bytes, little endian words" }, \
395 {"thumb-interwork", ARM_FLAG_THUMB, \
396 "Support calls between THUMB and ARM instructions sets" }, \
397 {"no-thumb-interwork", -ARM_FLAG_THUMB, "" }, \
398 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
399 "Generate a call to abort if a noreturn function returns"}, \
400 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, ""}, \
401 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \
402 "Do not move instructions into a function's prologue" }, \
403 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \
404 SUBTARGET_SWITCHES \
405 {"", TARGET_DEFAULT } \
406 }
407
408 #define TARGET_OPTIONS \
409 { \
410 {"cpu=", & arm_select[0].string, \
411 "Specify the name of the target CPU" }, \
412 {"arch=", & arm_select[1].string, \
413 "Specify the name of the target architecture" }, \
414 {"tune=", & arm_select[2].string, "" }, \
415 {"fpe=", & target_fp_name, "" }, \
416 {"fp=", & target_fp_name, \
417 "Specify the version of the floating point emulator" }, \
418 { "structure-size-boundary=", & structure_size_string, \
419 "Specify the minumum bit alignment of structures" } \
420 }
421
422 struct arm_cpu_select
423 {
424 char * string;
425 char * name;
426 struct processors * processors;
427 };
428
429 /* This is a magic array. If the user specifies a command line switch
430 which matches one of the entries in TARGET_OPTIONS then the corresponding
431 string pointer will be set to the value specified by the user. */
432 extern struct arm_cpu_select arm_select[];
433
434 enum prog_mode_type
435 {
436 prog_mode26,
437 prog_mode32
438 };
439
440 /* Recast the program mode class to be the prog_mode attribute */
441 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
442
443 extern enum prog_mode_type arm_prgmode;
444
445 /* What sort of floating point unit do we have? Hardware or software.
446 If software, is it issue 2 or issue 3? */
447 enum floating_point_type
448 {
449 FP_HARD,
450 FP_SOFT2,
451 FP_SOFT3
452 };
453
454 /* Recast the floating point class to be the floating point attribute. */
455 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
456
457 /* What type of floating point to tune for */
458 extern enum floating_point_type arm_fpu;
459
460 /* What type of floating point instructions are available */
461 extern enum floating_point_type arm_fpu_arch;
462
463 /* Default floating point architecture. Override in sub-target if
464 necessary. */
465 #define FP_DEFAULT FP_SOFT2
466
467 /* Nonzero if the processor has a fast multiply insn, and one that does
468 a 64-bit multiply of two 32-bit values. */
469 extern int arm_fast_multiply;
470
471 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
472 extern int arm_arch4;
473
474 /* Nonzero if this chip can benefit from load scheduling. */
475 extern int arm_ld_sched;
476
477 /* Nonzero if this chip is a StrongARM. */
478 extern int arm_is_strong;
479
480 /* Nonzero if this chip is a an ARM6 or an ARM7. */
481 extern int arm_is_6_or_7;
482
483 #ifndef TARGET_DEFAULT
484 #define TARGET_DEFAULT 0
485 #endif
486
487 /* The frame pointer register used in gcc has nothing to do with debugging;
488 that is controlled by the APCS-FRAME option. */
489 /* Not fully implemented yet */
490 /* #define CAN_DEBUG_WITHOUT_FP 1 */
491
492 #define TARGET_MEM_FUNCTIONS 1
493
494 #define OVERRIDE_OPTIONS arm_override_options ()
495 \f
496 /* Target machine storage Layout. */
497
498
499 /* Define this macro if it is advisable to hold scalars in registers
500 in a wider mode than that declared by the program. In such cases,
501 the value is constrained to be within the bounds of the declared
502 type, but kept valid in the wider mode. The signedness of the
503 extension may differ from that of the type. */
504
505 /* It is far faster to zero extend chars than to sign extend them */
506
507 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
508 if (GET_MODE_CLASS (MODE) == MODE_INT \
509 && GET_MODE_SIZE (MODE) < 4) \
510 { \
511 if (MODE == QImode) \
512 UNSIGNEDP = 1; \
513 else if (MODE == HImode) \
514 UNSIGNEDP = TARGET_SHORT_BY_BYTES != 0; \
515 (MODE) = SImode; \
516 }
517
518 /* Define this macro if the promotion described by `PROMOTE_MODE'
519 should also be done for outgoing function arguments. */
520 /* This is required to ensure that push insns always push a word. */
521 #define PROMOTE_FUNCTION_ARGS
522
523 /* Define for XFmode extended real floating point support.
524 This will automatically cause REAL_ARITHMETIC to be defined. */
525 /* For the ARM:
526 I think I have added all the code to make this work. Unfortunately,
527 early releases of the floating point emulation code on RISCiX used a
528 different format for extended precision numbers. On my RISCiX box there
529 is a bug somewhere which causes the machine to lock up when running enquire
530 with long doubles. There is the additional aspect that Norcroft C
531 treats long doubles as doubles and we ought to remain compatible.
532 Perhaps someone with an FPA coprocessor and not running RISCiX would like
533 to try this someday. */
534 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
535
536 /* Disable XFmode patterns in md file */
537 #define ENABLE_XF_PATTERNS 0
538
539 /* Define if you don't want extended real, but do want to use the
540 software floating point emulator for REAL_ARITHMETIC and
541 decimal <-> binary conversion. */
542 /* See comment above */
543 #define REAL_ARITHMETIC
544
545 /* Define this if most significant bit is lowest numbered
546 in instructions that operate on numbered bit-fields. */
547 #define BITS_BIG_ENDIAN 0
548
549 /* Define this if most significant byte of a word is the lowest numbered.
550 Most ARM processors are run in little endian mode, so that is the default.
551 If you want to have it run-time selectable, change the definition in a
552 cover file to be TARGET_BIG_ENDIAN. */
553 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
554
555 /* Define this if most significant word of a multiword number is the lowest
556 numbered.
557 This is always false, even when in big-endian mode. */
558 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
559
560 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
561 on processor pre-defineds when compiling libgcc2.c. */
562 #if defined(__ARMEB__) && !defined(__ARMWEL__)
563 #define LIBGCC2_WORDS_BIG_ENDIAN 1
564 #else
565 #define LIBGCC2_WORDS_BIG_ENDIAN 0
566 #endif
567
568 /* Define this if most significant word of doubles is the lowest numbered.
569 This is always true, even when in little-endian mode. */
570 #define FLOAT_WORDS_BIG_ENDIAN 1
571
572 /* Number of bits in an addressable storage unit */
573 #define BITS_PER_UNIT 8
574
575 #define BITS_PER_WORD 32
576
577 #define UNITS_PER_WORD 4
578
579 #define POINTER_SIZE 32
580
581 #define PARM_BOUNDARY 32
582
583 #define STACK_BOUNDARY 32
584
585 #define FUNCTION_BOUNDARY 32
586
587 #define EMPTY_FIELD_BOUNDARY 32
588
589 #define BIGGEST_ALIGNMENT 32
590
591 /* Make strings word-aligned so strcpy from constants will be faster. */
592 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
593 (TREE_CODE (EXP) == STRING_CST \
594 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
595
596 /* Every structures size must be a multiple of 32 bits. */
597 /* This is for compatibility with ARMCC. ARM SDT Reference Manual
598 (ARM DUI 0020D) page 2-20 says "Structures are aligned on word
599 boundaries". */
600 #ifndef STRUCTURE_SIZE_BOUNDARY
601 #define STRUCTURE_SIZE_BOUNDARY 32
602 #endif
603
604 /* Used when parsing command line option -mstructure_size_boundary. */
605 extern char * structure_size_string;
606
607 /* Non-zero if move instructions will actually fail to work
608 when given unaligned data. */
609 #define STRICT_ALIGNMENT 1
610
611 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
612
613 \f
614 /* Standard register usage. */
615
616 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
617 (S - saved over call).
618
619 r0 * argument word/integer result
620 r1-r3 argument word
621
622 r4-r8 S register variable
623 r9 S (rfp) register variable (real frame pointer)
624
625 r10 F S (sl) stack limit (used by -mapcs-stack-check)
626 r11 F S (fp) argument pointer
627 r12 (ip) temp workspace
628 r13 F S (sp) lower end of current stack frame
629 r14 (lr) link address/workspace
630 r15 F (pc) program counter
631
632 f0 floating point result
633 f1-f3 floating point scratch
634
635 f4-f7 S floating point variable
636
637 cc This is NOT a real register, but is used internally
638 to represent things that use or set the condition
639 codes.
640 sfp This isn't either. It is used during rtl generation
641 since the offset between the frame pointer and the
642 auto's isn't known until after register allocation.
643 afp Nor this, we only need this because of non-local
644 goto. Without it fp appears to be used and the
645 elimination code won't get rid of sfp. It tracks
646 fp exactly at all times.
647
648 *: See CONDITIONAL_REGISTER_USAGE */
649
650 /* The stack backtrace structure is as follows:
651 fp points to here: | save code pointer | [fp]
652 | return link value | [fp, #-4]
653 | return sp value | [fp, #-8]
654 | return fp value | [fp, #-12]
655 [| saved r10 value |]
656 [| saved r9 value |]
657 [| saved r8 value |]
658 [| saved r7 value |]
659 [| saved r6 value |]
660 [| saved r5 value |]
661 [| saved r4 value |]
662 [| saved r3 value |]
663 [| saved r2 value |]
664 [| saved r1 value |]
665 [| saved r0 value |]
666 [| saved f7 value |] three words
667 [| saved f6 value |] three words
668 [| saved f5 value |] three words
669 [| saved f4 value |] three words
670 r0-r3 are not normally saved in a C function. */
671
672 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
673 #define FIRST_PSEUDO_REGISTER 27
674
675 /* 1 for registers that have pervasive standard uses
676 and are not available for the register allocator. */
677 #define FIXED_REGISTERS \
678 { \
679 0,0,0,0,0,0,0,0, \
680 0,0,1,1,0,1,0,1, \
681 0,0,0,0,0,0,0,0, \
682 1,1,1 \
683 }
684
685 /* 1 for registers not available across function calls.
686 These must include the FIXED_REGISTERS and also any
687 registers that can be used without being saved.
688 The latter must include the registers where values are returned
689 and the register where structure-value addresses are passed.
690 Aside from that, you can include as many other registers as you like.
691 The CC is not preserved over function calls on the ARM 6, so it is
692 easier to assume this for all. SFP is preserved, since FP is. */
693 #define CALL_USED_REGISTERS \
694 { \
695 1,1,1,1,0,0,0,0, \
696 0,0,1,1,1,1,1,1, \
697 1,1,1,1,0,0,0,0, \
698 1,1,1 \
699 }
700
701 /* If doing stupid life analysis, avoid a bug causing a return value r0 to be
702 trampled. This effectively reduces the number of available registers by 1.
703 XXX It is a hack, I know.
704 XXX Is this still needed? */
705 #define CONDITIONAL_REGISTER_USAGE \
706 { \
707 if (obey_regdecls) \
708 fixed_regs[0] = 1; \
709 if (TARGET_SOFT_FLOAT) \
710 { \
711 int regno; \
712 for (regno = 16; regno < 24; ++regno) \
713 fixed_regs[regno] = call_used_regs[regno] = 1; \
714 } \
715 if (flag_pic) \
716 { \
717 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
718 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 0; \
719 } \
720 else if (! TARGET_APCS_STACK) \
721 { \
722 fixed_regs[10] = 0; \
723 call_used_regs[10] = 0; \
724 } \
725 }
726
727 /* Return number of consecutive hard regs needed starting at reg REGNO
728 to hold something of mode MODE.
729 This is ordinarily the length in words of a value of mode MODE
730 but can be less for certain modes in special long registers.
731
732 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
733 mode. */
734 #define HARD_REGNO_NREGS(REGNO, MODE) \
735 (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \
736 && (REGNO) != ARG_POINTER_REGNUM) ? 1 \
737 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
738
739 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
740 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
741 regs holding FP. */
742 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
743 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
744 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
745 || REGNO == ARG_POINTER_REGNUM \
746 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
747
748 /* Value is 1 if it is a good idea to tie two pseudo registers
749 when one has mode MODE1 and one has mode MODE2.
750 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
751 for any hard reg, then this must be 0 for correct output. */
752 #define MODES_TIEABLE_P(MODE1, MODE2) \
753 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
754
755 /* Specify the registers used for certain standard purposes.
756 The values of these macros are register numbers. */
757
758 /* Define this if the program counter is overloaded on a register. */
759 #define PC_REGNUM 15
760
761 /* Register to use for pushing function arguments. */
762 #define STACK_POINTER_REGNUM 13
763
764 /* Base register for access to local variables of the function. */
765 #define FRAME_POINTER_REGNUM 25
766
767 /* Define this to be where the real frame pointer is if it is not possible to
768 work out the offset between the frame pointer and the automatic variables
769 until after register allocation has taken place. FRAME_POINTER_REGNUM
770 should point to a special register that we will make sure is eliminated. */
771 #define HARD_FRAME_POINTER_REGNUM 11
772
773 /* Value should be nonzero if functions must have frame pointers.
774 Zero means the frame pointer need not be set up (and parms may be accessed
775 via the stack pointer) in functions that seem suitable.
776 If we have to have a frame pointer we might as well make use of it.
777 APCS says that the frame pointer does not need to be pushed in leaf
778 functions, or simple tail call functions. */
779 #define FRAME_POINTER_REQUIRED \
780 (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ()))
781
782 /* Base register for access to arguments of the function. */
783 #define ARG_POINTER_REGNUM 26
784
785 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
786 as an invisible last argument (possible since varargs don't exist in
787 Pascal), so the following is not true. */
788 #define STATIC_CHAIN_REGNUM 8
789
790 /* Register in which address to store a structure value
791 is passed to a function. */
792 #define STRUCT_VALUE_REGNUM 0
793
794 /* Internal, so that we don't need to refer to a raw number */
795 #define CC_REGNUM 24
796
797 /* The order in which register should be allocated. It is good to use ip
798 since no saving is required (though calls clobber it) and it never contains
799 function parameters. It is quite good to use lr since other calls may
800 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
801 least likely to contain a function parameter; in addition results are
802 returned in r0.
803 */
804 #define REG_ALLOC_ORDER \
805 { \
806 3, 2, 1, 0, 12, 14, 4, 5, \
807 6, 7, 8, 10, 9, 11, 13, 15, \
808 16, 17, 18, 19, 20, 21, 22, 23, \
809 24, 25, 26 \
810 }
811 \f
812 /* Register and constant classes. */
813
814 /* Register classes: all ARM regs or all FPU regs---simple! */
815 enum reg_class
816 {
817 NO_REGS,
818 FPU_REGS,
819 GENERAL_REGS,
820 ALL_REGS,
821 LIM_REG_CLASSES
822 };
823
824 #define N_REG_CLASSES (int) LIM_REG_CLASSES
825
826 /* Give names of register classes as strings for dump file. */
827 #define REG_CLASS_NAMES \
828 { \
829 "NO_REGS", \
830 "FPU_REGS", \
831 "GENERAL_REGS", \
832 "ALL_REGS", \
833 }
834
835 /* Define which registers fit in which classes.
836 This is an initializer for a vector of HARD_REG_SET
837 of length N_REG_CLASSES. */
838 #define REG_CLASS_CONTENTS \
839 { \
840 0x0000000, /* NO_REGS */ \
841 0x0FF0000, /* FPU_REGS */ \
842 0x200FFFF, /* GENERAL_REGS */ \
843 0x2FFFFFF /* ALL_REGS */ \
844 }
845
846 /* The same information, inverted:
847 Return the class number of the smallest class containing
848 reg number REGNO. This could be a conditional expression
849 or could index an array. */
850 #define REGNO_REG_CLASS(REGNO) \
851 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
852 || REGNO == ARG_POINTER_REGNUM) \
853 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
854 ? NO_REGS : FPU_REGS)
855
856 /* The class value for index registers, and the one for base regs. */
857 #define INDEX_REG_CLASS GENERAL_REGS
858 #define BASE_REG_CLASS GENERAL_REGS
859
860 /* Get reg_class from a letter such as appears in the machine description.
861 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
862 #define REG_CLASS_FROM_LETTER(C) \
863 ((C)=='f' ? FPU_REGS : NO_REGS)
864
865 /* The letters I, J, K, L and M in a register constraint string
866 can be used to stand for particular ranges of immediate operands.
867 This macro defines what the ranges are.
868 C is the letter, and VALUE is a constant value.
869 Return 1 if VALUE is in the range specified by C.
870 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
871 J: valid indexing constants.
872 K: ~value ok in rhs argument of data operand.
873 L: -value ok in rhs argument of data operand.
874 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
875 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
876 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
877 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
878 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
879 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
880 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
881 || (((VALUE) & ((VALUE) - 1)) == 0)) \
882 : 0)
883
884 /* For the ARM, `Q' means that this is a memory operand that is just
885 an offset from a register.
886 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
887 address. This means that the symbol is in the text segment and can be
888 accessed without using a load. */
889
890 #define EXTRA_CONSTRAINT(OP, C) \
891 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
892 : (C) == 'R' ? (GET_CODE (OP) == MEM \
893 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
894 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
895 : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
896 : 0)
897
898 /* Constant letter 'G' for the FPU immediate constants.
899 'H' means the same constant negated. */
900 #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
901 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
902 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
903
904 /* Given an rtx X being reloaded into a reg required to be
905 in class CLASS, return the class of reg to actually use.
906 In general this is just CLASS; but on some machines
907 in some cases it is preferable to use a more restrictive class. */
908 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
909
910 /* Return the register class of a scratch register needed to copy IN into
911 or out of a register in CLASS in MODE. If it can be done directly,
912 NO_REGS is returned. */
913 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
914 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
915 ? GENERAL_REGS : NO_REGS)
916
917 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
918 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
919 (((MODE) == HImode && ! arm_arch4 && TARGET_SHORT_BY_BYTES \
920 && (GET_CODE (X) == MEM \
921 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
922 && true_regnum (X) == -1))) \
923 ? GENERAL_REGS : NO_REGS)
924
925 /* Try a machine-dependent way of reloading an illegitimate address
926 operand. If we find one, push the reload and jump to WIN. This
927 macro is used in only one place: `find_reloads_address' in reload.c.
928
929 For the ARM, we wish to handle large displacements off a base
930 register by splitting the addend across a MOV and the mem insn.
931 This can cut the number of reloads needed. */
932 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
933 do { \
934 if (GET_CODE (X) == PLUS \
935 && GET_CODE (XEXP (X, 0)) == REG \
936 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
937 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
938 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
939 { \
940 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
941 HOST_WIDE_INT low, high; \
942 \
943 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
944 low = ((val & 0xf) ^ 0x8) - 0x8; \
945 else if (MODE == SImode || MODE == QImode \
946 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
947 || (MODE == HImode && ! arm_arch4)) \
948 /* Need to be careful, -4096 is not a valid offset */ \
949 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
950 else if (MODE == HImode && arm_arch4) \
951 /* Need to be careful, -256 is not a valid offset */ \
952 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
953 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
954 && TARGET_HARD_FLOAT) \
955 /* Need to be careful, -1024 is not a valid offset */ \
956 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
957 else \
958 break; \
959 \
960 high = ((((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000); \
961 /* Check for overflow or zero */ \
962 if (low == 0 || high == 0 || (high + low != val)) \
963 break; \
964 \
965 /* Reload the high part into a base reg; leave the low part \
966 in the mem. */ \
967 X = gen_rtx_PLUS (GET_MODE (X), \
968 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
969 GEN_INT (high)), \
970 GEN_INT (low)); \
971 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
972 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
973 OPNUM, TYPE); \
974 goto WIN; \
975 } \
976 } while (0)
977
978 /* Return the maximum number of consecutive registers
979 needed to represent mode MODE in a register of class CLASS.
980 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
981 #define CLASS_MAX_NREGS(CLASS, MODE) \
982 ((CLASS) == FPU_REGS ? 1 \
983 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
984
985 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
986 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
987 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
988 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
989 ? 20 : 2)
990 \f
991 /* Stack layout; function entry, exit and calling. */
992
993 /* Define this if pushing a word on the stack
994 makes the stack pointer a smaller address. */
995 #define STACK_GROWS_DOWNWARD 1
996
997 /* Define this if the nominal address of the stack frame
998 is at the high-address end of the local variables;
999 that is, each additional local variable allocated
1000 goes at a more negative offset in the frame. */
1001 #define FRAME_GROWS_DOWNWARD 1
1002
1003 /* Offset within stack frame to start allocating local variables at.
1004 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1005 first local allocated. Otherwise, it is the offset to the BEGINNING
1006 of the first local allocated. */
1007 #define STARTING_FRAME_OFFSET 0
1008
1009 /* If we generate an insn to push BYTES bytes,
1010 this says how many the stack pointer really advances by. */
1011 /* The push insns do not do this rounding implicitly. So don't define this. */
1012 /* #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) */
1013
1014 /* Define this if the maximum size of all the outgoing args is to be
1015 accumulated and pushed during the prologue. The amount can be
1016 found in the variable current_function_outgoing_args_size. */
1017 #define ACCUMULATE_OUTGOING_ARGS
1018
1019 /* Offset of first parameter from the argument pointer register value. */
1020 #define FIRST_PARM_OFFSET(FNDECL) 4
1021
1022 /* Value is the number of byte of arguments automatically
1023 popped when returning from a subroutine call.
1024 FUNDECL is the declaration node of the function (as a tree),
1025 FUNTYPE is the data type of the function (as a tree),
1026 or for a library call it is an identifier node for the subroutine name.
1027 SIZE is the number of bytes of arguments passed on the stack.
1028
1029 On the ARM, the caller does not pop any of its arguments that were passed
1030 on the stack. */
1031 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1032
1033 /* Define how to find the value returned by a function.
1034 VALTYPE is the data type of the value (as a tree).
1035 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1036 otherwise, FUNC is 0. */
1037 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1038 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT && TARGET_HARD_FLOAT \
1039 ? gen_rtx_REG (TYPE_MODE (VALTYPE), 16) \
1040 : gen_rtx_REG (TYPE_MODE (VALTYPE), 0))
1041
1042 /* Define how to find the value returned by a library function
1043 assuming the value has mode MODE. */
1044 #define LIBCALL_VALUE(MODE) \
1045 (GET_MODE_CLASS (MODE) == MODE_FLOAT && TARGET_HARD_FLOAT \
1046 ? gen_rtx_REG (MODE, 16) \
1047 : gen_rtx_REG (MODE, 0))
1048
1049 /* 1 if N is a possible register number for a function value.
1050 On the ARM, only r0 and f0 can return results. */
1051 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1052 ((REGNO) == 0 || ((REGNO) == 16) && TARGET_HARD_FLOAT)
1053
1054 /* How large values are returned */
1055 /* A C expression which can inhibit the returning of certain function values
1056 in registers, based on the type of value. */
1057 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1058
1059 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1060 values must be in memory. On the ARM, they need only do so if larger
1061 than a word, or if they contain elements offset from zero in the struct. */
1062 #define DEFAULT_PCC_STRUCT_RETURN 0
1063
1064 /* Define where to put the arguments to a function.
1065 Value is zero to push the argument on the stack,
1066 or a hard register in which to store the argument.
1067
1068 MODE is the argument's machine mode.
1069 TYPE is the data type of the argument (as a tree).
1070 This is null for libcalls where that information may
1071 not be available.
1072 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1073 the preceding args and about the function being called.
1074 NAMED is nonzero if this argument is a named parameter
1075 (otherwise it is an extra parameter matching an ellipsis).
1076
1077 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1078 other arguments are passed on the stack. If (NAMED == 0) (which happens
1079 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1080 passed in the stack (function_prologue will indeed make it pass in the
1081 stack if necessary). */
1082 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1083 ((NAMED) \
1084 ? ((CUM) >= 16 ? 0 : gen_rtx_REG (MODE, (CUM) / 4)) \
1085 : 0)
1086
1087 /* For an arg passed partly in registers and partly in memory,
1088 this is the number of registers used.
1089 For args passed entirely in registers or entirely in memory, zero. */
1090 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1091 ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \
1092 ? GET_MODE_SIZE (MODE) \
1093 : int_size_in_bytes (TYPE)) \
1094 ? 4 - (CUM) / 4 : 0)
1095
1096 /* A C type for declaring a variable that is used as the first argument of
1097 `FUNCTION_ARG' and other related values. For some target machines, the
1098 type `int' suffices and can hold the number of bytes of argument so far.
1099
1100 On the ARM, this is the number of bytes of arguments scanned so far. */
1101 #define CUMULATIVE_ARGS int
1102
1103 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1104 for a call to a function whose data type is FNTYPE.
1105 For a library call, FNTYPE is 0.
1106 On the ARM, the offset starts at 0. */
1107 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1108 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0))
1109
1110 /* Update the data in CUM to advance over an argument
1111 of mode MODE and data type TYPE.
1112 (TYPE is null for libcalls where that information may not be available.) */
1113 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1114 (CUM) += ((MODE) != BLKmode \
1115 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
1116 : (int_size_in_bytes (TYPE) + 3) & ~3) \
1117
1118 /* 1 if N is a possible register number for function argument passing.
1119 On the ARM, r0-r3 are used to pass args. */
1120 #define FUNCTION_ARG_REGNO_P(REGNO) \
1121 ((REGNO) >= 0 && (REGNO) <= 3)
1122
1123 /* Perform any actions needed for a function that is receiving a variable
1124 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1125 of the current parameter. PRETEND_SIZE is a variable that should be set to
1126 the amount of stack that must be pushed by the prolog to pretend that our
1127 caller pushed it.
1128
1129 Normally, this macro will push all remaining incoming registers on the
1130 stack and set PRETEND_SIZE to the length of the registers pushed.
1131
1132 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1133 named arg and all anonymous args onto the stack.
1134 XXX I know the prologue shouldn't be pushing registers, but it is faster
1135 that way. */
1136 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1137 { \
1138 extern int current_function_anonymous_args; \
1139 current_function_anonymous_args = 1; \
1140 if ((CUM) < 16) \
1141 (PRETEND_SIZE) = 16 - (CUM); \
1142 }
1143
1144 /* Generate assembly output for the start of a function. */
1145 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
1146 output_func_prologue ((STREAM), (SIZE))
1147
1148 /* Call the function profiler with a given profile label. The Acorn compiler
1149 puts this BEFORE the prolog but gcc puts it afterwards. The ``mov ip,lr''
1150 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
1151 to mind about this! */
1152 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1153 { \
1154 fprintf(STREAM, "\tmov\t%sip, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX); \
1155 fprintf(STREAM, "\tbl\tmcount\n"); \
1156 fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \
1157 }
1158
1159 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1160 the stack pointer does not matter. The value is tested only in
1161 functions that have frame pointers.
1162 No definition is equivalent to always zero.
1163
1164 On the ARM, the function epilogue recovers the stack pointer from the
1165 frame. */
1166 #define EXIT_IGNORE_STACK 1
1167
1168 /* Generate the assembly code for function exit. */
1169 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
1170 output_func_epilogue ((STREAM), (SIZE))
1171
1172 /* Determine if the epilogue should be output as RTL.
1173 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1174 #define USE_RETURN_INSN(ISCOND) use_return_insn (ISCOND)
1175
1176 /* Definitions for register eliminations.
1177
1178 This is an array of structures. Each structure initializes one pair
1179 of eliminable registers. The "from" register number is given first,
1180 followed by "to". Eliminations of the same "from" register are listed
1181 in order of preference.
1182
1183 We have two registers that can be eliminated on the ARM. First, the
1184 arg pointer register can often be eliminated in favor of the stack
1185 pointer register. Secondly, the pseudo frame pointer register can always
1186 be eliminated; it is replaced with either the stack or the real frame
1187 pointer. */
1188
1189 #define ELIMINABLE_REGS \
1190 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1191 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1192 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1193 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
1194
1195 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1196 Frame pointer elimination is automatically handled.
1197
1198 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1199 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1200 pointer, we must eliminate FRAME_POINTER_REGNUM into
1201 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
1202 #define CAN_ELIMINATE(FROM, TO) \
1203 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
1204
1205 /* Define the offset between two registers, one to be eliminated, and the other
1206 its replacement, at the start of a routine. */
1207 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1208 { \
1209 int volatile_func = arm_volatile_func (); \
1210 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
1211 (OFFSET) = 0; \
1212 else if ((FROM) == FRAME_POINTER_REGNUM \
1213 && (TO) == STACK_POINTER_REGNUM) \
1214 (OFFSET) = (current_function_outgoing_args_size \
1215 + (get_frame_size () + 3 & ~3)); \
1216 else \
1217 { \
1218 int regno; \
1219 int offset = 12; \
1220 int saved_hard_reg = 0; \
1221 \
1222 if (! volatile_func) \
1223 { \
1224 for (regno = 0; regno <= 10; regno++) \
1225 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1226 saved_hard_reg = 1, offset += 4; \
1227 for (regno = 16; regno <=23; regno++) \
1228 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1229 offset += 12; \
1230 } \
1231 if ((FROM) == FRAME_POINTER_REGNUM) \
1232 (OFFSET) = -offset; \
1233 else \
1234 { \
1235 if (! frame_pointer_needed) \
1236 offset -= 16; \
1237 if (! volatile_func \
1238 && (regs_ever_live[14] || saved_hard_reg)) \
1239 offset += 4; \
1240 offset += current_function_outgoing_args_size; \
1241 (OFFSET) = (get_frame_size () + 3 & ~3) + offset; \
1242 } \
1243 } \
1244 }
1245
1246 /* Output assembler code for a block containing the constant parts
1247 of a trampoline, leaving space for the variable parts.
1248
1249 On the ARM, (if r8 is the static chain regnum, and remembering that
1250 referencing pc adds an offset of 8) the trampoline looks like:
1251 ldr r8, [pc, #0]
1252 ldr pc, [pc]
1253 .word static chain value
1254 .word function's address
1255 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1256 #define TRAMPOLINE_TEMPLATE(FILE) \
1257 { \
1258 fprintf ((FILE), "\tldr\t%sr8, [%spc, #0]\n", \
1259 REGISTER_PREFIX, REGISTER_PREFIX); \
1260 fprintf ((FILE), "\tldr\t%spc, [%spc, #0]\n", \
1261 REGISTER_PREFIX, REGISTER_PREFIX); \
1262 fprintf ((FILE), "\t.word\t0\n"); \
1263 fprintf ((FILE), "\t.word\t0\n"); \
1264 }
1265
1266 /* Length in units of the trampoline for entering a nested function. */
1267 #define TRAMPOLINE_SIZE 16
1268
1269 /* Alignment required for a trampoline in units. */
1270 #define TRAMPOLINE_ALIGN 4
1271
1272 /* Emit RTL insns to initialize the variable parts of a trampoline.
1273 FNADDR is an RTX for the address of the function's pure code.
1274 CXT is an RTX for the static chain value for the function. */
1275 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1276 { \
1277 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
1278 (CXT)); \
1279 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
1280 (FNADDR)); \
1281 }
1282
1283 \f
1284 /* Addressing modes, and classification of registers for them. */
1285
1286 #define HAVE_POST_INCREMENT 1
1287 #define HAVE_PRE_INCREMENT 1
1288 #define HAVE_POST_DECREMENT 1
1289 #define HAVE_PRE_DECREMENT 1
1290
1291 /* Macros to check register numbers against specific register classes. */
1292
1293 /* These assume that REGNO is a hard or pseudo reg number.
1294 They give nonzero only if REGNO is a hard reg of the suitable class
1295 or a pseudo reg currently allocated to a suitable hard reg.
1296 Since they use reg_renumber, they are safe only once reg_renumber
1297 has been allocated, which happens in local-alloc.c.
1298
1299 On the ARM, don't allow the pc to be used. */
1300 #define REGNO_OK_FOR_BASE_P(REGNO) \
1301 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
1302 || (REGNO) == ARG_POINTER_REGNUM \
1303 || (unsigned) reg_renumber[(REGNO)] < 15 \
1304 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
1305 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
1306 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1307 REGNO_OK_FOR_BASE_P(REGNO)
1308
1309 /* Maximum number of registers that can appear in a valid memory address.
1310 Shifts in addresses can't be by a register. */
1311
1312 #define MAX_REGS_PER_ADDRESS 2
1313
1314 /* Recognize any constant value that is a valid address. */
1315 /* XXX We can address any constant, eventually... */
1316
1317 #ifdef AOF_ASSEMBLER
1318
1319 #define CONSTANT_ADDRESS_P(X) \
1320 (GET_CODE (X) == SYMBOL_REF \
1321 && CONSTANT_POOL_ADDRESS_P (X))
1322
1323 #else
1324
1325 #define CONSTANT_ADDRESS_P(X) \
1326 (GET_CODE (X) == SYMBOL_REF \
1327 && (CONSTANT_POOL_ADDRESS_P (X) \
1328 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
1329
1330 #endif /* AOF_ASSEMBLER */
1331
1332 /* Nonzero if the constant value X is a legitimate general operand.
1333 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1334
1335 On the ARM, allow any integer (invalid ones are removed later by insn
1336 patterns), nice doubles and symbol_refs which refer to the function's
1337 constant pool XXX. */
1338 #define LEGITIMATE_CONSTANT_P(X) (! label_mentioned_p (X))
1339
1340 /* Symbols in the text segment can be accessed without indirecting via the
1341 constant pool; it may take an extra binary operation, but this is still
1342 faster than indirecting via memory. Don't do this when not optimizing,
1343 since we won't be calculating al of the offsets necessary to do this
1344 simplification. */
1345 /* This doesn't work with AOF syntax, since the string table may be in
1346 a different AREA. */
1347 #ifndef AOF_ASSEMBLER
1348 #define ENCODE_SECTION_INFO(decl) \
1349 { \
1350 if (optimize > 0 && TREE_CONSTANT (decl) \
1351 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1352 { \
1353 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1354 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1355 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1356 } \
1357 }
1358 #endif
1359
1360 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1361 and check its validity for a certain class.
1362 We have two alternate definitions for each of them.
1363 The usual definition accepts all pseudo regs; the other rejects
1364 them unless they have been allocated suitable hard regs.
1365 The symbol REG_OK_STRICT causes the latter definition to be used. */
1366 #ifndef REG_OK_STRICT
1367
1368 /* Nonzero if X is a hard reg that can be used as a base reg
1369 or if it is a pseudo reg. */
1370 #define REG_OK_FOR_BASE_P(X) \
1371 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1372 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1373
1374 /* Nonzero if X is a hard reg that can be used as an index
1375 or if it is a pseudo reg. */
1376 #define REG_OK_FOR_INDEX_P(X) \
1377 REG_OK_FOR_BASE_P(X)
1378
1379 #define REG_OK_FOR_PRE_POST_P(X) \
1380 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1381 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1382
1383 #else
1384
1385 /* Nonzero if X is a hard reg that can be used as a base reg. */
1386 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1387
1388 /* Nonzero if X is a hard reg that can be used as an index. */
1389 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1390
1391 #define REG_OK_FOR_PRE_POST_P(X) \
1392 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
1393 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
1394 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
1395 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
1396
1397 #endif
1398 \f
1399 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1400 that is a valid memory address for an instruction.
1401 The MODE argument is the machine mode for the MEM expression
1402 that wants to use this address.
1403
1404 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1405 #define BASE_REGISTER_RTX_P(X) \
1406 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
1407
1408 #define INDEX_REGISTER_RTX_P(X) \
1409 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
1410
1411 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
1412 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
1413 only be small constants. */
1414 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
1415 do \
1416 { \
1417 HOST_WIDE_INT range; \
1418 enum rtx_code code = GET_CODE (INDEX); \
1419 \
1420 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1421 { \
1422 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
1423 && INTVAL (INDEX) > -1024 \
1424 && (INTVAL (INDEX) & 3) == 0) \
1425 goto LABEL; \
1426 } \
1427 else \
1428 { \
1429 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
1430 goto LABEL; \
1431 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
1432 && (! arm_arch4 || (MODE) != HImode)) \
1433 { \
1434 rtx xiop0 = XEXP (INDEX, 0); \
1435 rtx xiop1 = XEXP (INDEX, 1); \
1436 if (INDEX_REGISTER_RTX_P (xiop0) \
1437 && power_of_two_operand (xiop1, SImode)) \
1438 goto LABEL; \
1439 if (INDEX_REGISTER_RTX_P (xiop1) \
1440 && power_of_two_operand (xiop0, SImode)) \
1441 goto LABEL; \
1442 } \
1443 if (GET_MODE_SIZE (MODE) <= 4 \
1444 && (code == LSHIFTRT || code == ASHIFTRT \
1445 || code == ASHIFT || code == ROTATERT) \
1446 && (! arm_arch4 || (MODE) != HImode)) \
1447 { \
1448 rtx op = XEXP (INDEX, 1); \
1449 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
1450 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
1451 && INTVAL (op) <= 31) \
1452 goto LABEL; \
1453 } \
1454 /* NASTY: Since this limits the addressing of unsigned byte loads */ \
1455 range = ((MODE) == HImode || (MODE) == QImode) \
1456 ? (arm_arch4 ? 256 : 4095) : 4096; \
1457 if (code == CONST_INT && INTVAL (INDEX) < range \
1458 && INTVAL (INDEX) > -range) \
1459 goto LABEL; \
1460 } \
1461 } while (0)
1462
1463 /* Jump to LABEL if X is a valid address RTX. This must also take
1464 REG_OK_STRICT into account when deciding about valid registers, but it uses
1465 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
1466 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
1467 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
1468 refs must be forced though a static cell to ensure addressability. */
1469 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1470 { \
1471 if (BASE_REGISTER_RTX_P (X)) \
1472 goto LABEL; \
1473 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1474 && GET_CODE (XEXP (X, 0)) == REG \
1475 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1476 goto LABEL; \
1477 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
1478 && (GET_CODE (X) == LABEL_REF \
1479 || (GET_CODE (X) == CONST \
1480 && GET_CODE (XEXP ((X), 0)) == PLUS \
1481 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
1482 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
1483 goto LABEL; \
1484 else if ((MODE) == TImode) \
1485 ; \
1486 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
1487 { \
1488 if (GET_CODE (X) == PLUS && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
1489 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1490 { \
1491 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1492 if (val == 4 || val == -4 || val == -8) \
1493 goto LABEL; \
1494 } \
1495 } \
1496 else if (GET_CODE (X) == PLUS) \
1497 { \
1498 rtx xop0 = XEXP(X,0); \
1499 rtx xop1 = XEXP(X,1); \
1500 \
1501 if (BASE_REGISTER_RTX_P (xop0)) \
1502 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1503 else if (BASE_REGISTER_RTX_P (xop1)) \
1504 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1505 } \
1506 /* Reload currently can't handle MINUS, so disable this for now */ \
1507 /* else if (GET_CODE (X) == MINUS) \
1508 { \
1509 rtx xop0 = XEXP (X,0); \
1510 rtx xop1 = XEXP (X,1); \
1511 \
1512 if (BASE_REGISTER_RTX_P (xop0)) \
1513 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1514 } */ \
1515 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1516 && GET_CODE (X) == SYMBOL_REF \
1517 && CONSTANT_POOL_ADDRESS_P (X) \
1518 && ! (flag_pic \
1519 && symbol_mentioned_p (get_pool_constant (X)))) \
1520 goto LABEL; \
1521 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1522 && (GET_MODE_SIZE (MODE) <= 4) \
1523 && GET_CODE (XEXP (X, 0)) == REG \
1524 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1525 goto LABEL; \
1526 }
1527 \f
1528 /* Try machine-dependent ways of modifying an illegitimate address
1529 to be legitimate. If we find one, return the new, valid address.
1530 This macro is used in only one place: `memory_address' in explow.c.
1531
1532 OLDX is the address as it was before break_out_memory_refs was called.
1533 In some cases it is useful to look at this to decide what needs to be done.
1534
1535 MODE and WIN are passed so that this macro can use
1536 GO_IF_LEGITIMATE_ADDRESS.
1537
1538 It is always safe for this macro to do nothing. It exists to recognize
1539 opportunities to optimize the output.
1540
1541 On the ARM, try to convert [REG, #BIGCONST]
1542 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1543 where VALIDCONST == 0 in case of TImode. */
1544 extern struct rtx_def *legitimize_pic_address ();
1545 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1546 { \
1547 if (GET_CODE (X) == PLUS) \
1548 { \
1549 rtx xop0 = XEXP (X, 0); \
1550 rtx xop1 = XEXP (X, 1); \
1551 \
1552 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
1553 xop0 = force_reg (SImode, xop0); \
1554 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1555 xop1 = force_reg (SImode, xop1); \
1556 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1557 { \
1558 HOST_WIDE_INT n, low_n; \
1559 rtx base_reg, val; \
1560 n = INTVAL (xop1); \
1561 \
1562 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1563 { \
1564 low_n = n & 0x0f; \
1565 n &= ~0x0f; \
1566 if (low_n > 4) \
1567 { \
1568 n += 16; \
1569 low_n -= 16; \
1570 } \
1571 } \
1572 else \
1573 { \
1574 low_n = ((MODE) == TImode ? 0 \
1575 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
1576 n -= low_n; \
1577 } \
1578 base_reg = gen_reg_rtx (SImode); \
1579 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
1580 GEN_INT (n)), NULL_RTX); \
1581 emit_move_insn (base_reg, val); \
1582 (X) = (low_n == 0 ? base_reg \
1583 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
1584 } \
1585 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
1586 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
1587 } \
1588 else if (GET_CODE (X) == MINUS) \
1589 { \
1590 rtx xop0 = XEXP (X, 0); \
1591 rtx xop1 = XEXP (X, 1); \
1592 \
1593 if (CONSTANT_P (xop0)) \
1594 xop0 = force_reg (SImode, xop0); \
1595 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1596 xop1 = force_reg (SImode, xop1); \
1597 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
1598 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
1599 } \
1600 if (flag_pic) \
1601 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
1602 if (memory_address_p (MODE, X)) \
1603 goto WIN; \
1604 }
1605
1606 /* Go to LABEL if ADDR (a legitimate address expression)
1607 has an effect that depends on the machine mode it is used for. */
1608 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1609 { \
1610 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1611 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1612 goto LABEL; \
1613 }
1614 \f
1615 /* Specify the machine mode that this machine uses
1616 for the index in the tablejump instruction. */
1617 #define CASE_VECTOR_MODE SImode
1618
1619 /* Define as C expression which evaluates to nonzero if the tablejump
1620 instruction expects the table to contain offsets from the address of the
1621 table.
1622 Do not define this if the table should contain absolute addresses. */
1623 /* #define CASE_VECTOR_PC_RELATIVE 1 */
1624
1625 /* Specify the tree operation to be used to convert reals to integers. */
1626 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1627
1628 /* This is the kind of divide that is easiest to do in the general case. */
1629 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1630
1631 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1632 unsigned is probably best, but may break some code. */
1633 #ifndef DEFAULT_SIGNED_CHAR
1634 #define DEFAULT_SIGNED_CHAR 0
1635 #endif
1636
1637 /* Don't cse the address of the function being compiled. */
1638 #define NO_RECURSIVE_FUNCTION_CSE 1
1639
1640 /* Max number of bytes we can move from memory to memory
1641 in one reasonably fast instruction. */
1642 #define MOVE_MAX 4
1643
1644 /* Define if operations between registers always perform the operation
1645 on the full register even if a narrower mode is specified. */
1646 #define WORD_REGISTER_OPERATIONS
1647
1648 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1649 will either zero-extend or sign-extend. The value of this macro should
1650 be the code that says which one of the two operations is implicitly
1651 done, NIL if none. */
1652 #define LOAD_EXTEND_OP(MODE) \
1653 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
1654 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))
1655
1656 /* Define this if zero-extension is slow (more than one real instruction).
1657 On the ARM, it is more than one instruction only if not fetching from
1658 memory. */
1659 /* #define SLOW_ZERO_EXTEND */
1660
1661 /* Nonzero if access to memory by bytes is slow and undesirable. */
1662 #define SLOW_BYTE_ACCESS 0
1663
1664 /* Immediate shift counts are truncated by the output routines (or was it
1665 the assembler?). Shift counts in a register are truncated by ARM. Note
1666 that the native compiler puts too large (> 32) immediate shift counts
1667 into a register and shifts by the register, letting the ARM decide what
1668 to do instead of doing that itself. */
1669 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1670 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1671 On the arm, Y in a register is used modulo 256 for the shift. Only for
1672 rotates is modulo 32 used. */
1673 /* #define SHIFT_COUNT_TRUNCATED 1 */
1674
1675 /* All integers have the same format so truncation is easy. */
1676 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1677
1678 /* Calling from registers is a massive pain. */
1679 #define NO_FUNCTION_CSE 1
1680
1681 /* Chars and shorts should be passed as ints. */
1682 #define PROMOTE_PROTOTYPES 1
1683
1684 /* The machine modes of pointers and functions */
1685 #define Pmode SImode
1686 #define FUNCTION_MODE Pmode
1687
1688 /* The structure type of the machine dependent info field of insns
1689 No uses for this yet. */
1690 /* #define INSN_MACHINE_INFO struct machine_info */
1691
1692 /* The relative costs of various types of constants. Note that cse.c defines
1693 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1694 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1695 case CONST_INT: \
1696 if (const_ok_for_arm (INTVAL (RTX))) \
1697 return (OUTER_CODE) == SET ? 2 : -1; \
1698 else if (OUTER_CODE == AND \
1699 && const_ok_for_arm (~INTVAL (RTX))) \
1700 return -1; \
1701 else if ((OUTER_CODE == COMPARE \
1702 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1703 && const_ok_for_arm (-INTVAL (RTX))) \
1704 return -1; \
1705 else \
1706 return 5; \
1707 case CONST: \
1708 case LABEL_REF: \
1709 case SYMBOL_REF: \
1710 return 6; \
1711 case CONST_DOUBLE: \
1712 if (const_double_rtx_ok_for_fpu (RTX)) \
1713 return (OUTER_CODE) == SET ? 2 : -1; \
1714 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1715 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1716 return -1; \
1717 return(7);
1718
1719 #define ARM_FRAME_RTX(X) \
1720 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1721 || (X) == arg_pointer_rtx)
1722
1723 #define DEFAULT_RTX_COSTS(X,CODE,OUTER_CODE) \
1724 return arm_rtx_costs (X, CODE, OUTER_CODE);
1725
1726 /* Moves to and from memory are quite expensive */
1727 #define MEMORY_MOVE_COST(MODE,CLASS,IN) 10
1728
1729 /* All address computations that can be done are free, but rtx cost returns
1730 the same for practically all of them. So we weight the different types
1731 of address here in the order (most pref first):
1732 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
1733 #define ADDRESS_COST(X) \
1734 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
1735 || GET_CODE (X) == SYMBOL_REF) \
1736 ? 0 \
1737 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
1738 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1739 ? 10 \
1740 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
1741 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
1742 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
1743 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
1744 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
1745 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
1746 ? 1 : 0)) \
1747 : 4)))))
1748
1749
1750
1751 /* Try to generate sequences that don't involve branches, we can then use
1752 conditional instructions */
1753 #define BRANCH_COST 4
1754
1755 /* A C statement to update the variable COST based on the relationship
1756 between INSN that is dependent on DEP through dependence LINK. */
1757 #define ADJUST_COST(INSN,LINK,DEP,COST) \
1758 (COST) = arm_adjust_cost ((INSN), (LINK), (DEP), (COST))
1759 \f
1760 /* Position Independent Code. */
1761 /* We decide which register to use based on the compilation options and
1762 the assembler in use; this is more general than the APCS restriction of
1763 using sb (r9) all the time. */
1764 extern int arm_pic_register;
1765
1766 /* The register number of the register used to address a table of static
1767 data addresses in memory. */
1768 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
1769
1770 #define FINALIZE_PIC arm_finalize_pic ()
1771
1772 /* We can't directly access anything that contains a symbol,
1773 nor can we indirect via the constant pool. */
1774 #define LEGITIMATE_PIC_OPERAND_P(X) \
1775 (! symbol_mentioned_p (X) \
1776 && (! CONSTANT_POOL_ADDRESS_P (X) \
1777 || ! symbol_mentioned_p (get_pool_constant (X))))
1778
1779
1780 \f
1781 /* Condition code information. */
1782 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1783 return the mode to be used for the comparison.
1784 CCFPEmode should be used with floating inequalities,
1785 CCFPmode should be used with floating equalities.
1786 CC_NOOVmode should be used with SImode integer equalities.
1787 CC_Zmode should be used if only the Z flag is set correctly
1788 CCmode should be used otherwise. */
1789
1790 #define EXTRA_CC_MODES CC_NOOVmode, CC_Zmode, CC_SWPmode, \
1791 CCFPmode, CCFPEmode, CC_DNEmode, CC_DEQmode, CC_DLEmode, \
1792 CC_DLTmode, CC_DGEmode, CC_DGTmode, CC_DLEUmode, CC_DLTUmode, \
1793 CC_DGEUmode, CC_DGTUmode, CC_Cmode
1794
1795 #define EXTRA_CC_NAMES "CC_NOOV", "CC_Z", "CC_SWP", "CCFP", "CCFPE", \
1796 "CC_DNE", "CC_DEQ", "CC_DLE", "CC_DLT", "CC_DGE", "CC_DGT", "CC_DLEU", \
1797 "CC_DLTU", "CC_DGEU", "CC_DGTU", "CC_C"
1798
1799 enum machine_mode arm_select_cc_mode ();
1800 #define SELECT_CC_MODE(OP,X,Y) arm_select_cc_mode ((OP), (X), (Y))
1801
1802 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1803
1804 enum rtx_code arm_canonicalize_comparison ();
1805 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
1806 do \
1807 { \
1808 if (GET_CODE (OP1) == CONST_INT \
1809 && ! (const_ok_for_arm (INTVAL (OP1)) \
1810 || (const_ok_for_arm (- INTVAL (OP1))))) \
1811 { \
1812 rtx const_op = OP1; \
1813 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
1814 OP1 = const_op; \
1815 } \
1816 } while (0)
1817
1818 #define STORE_FLAG_VALUE 1
1819
1820 /* Define the information needed to generate branch insns. This is
1821 stored from the compare operation. Note that we can't use "rtx" here
1822 since it hasn't been defined! */
1823
1824 extern struct rtx_def *arm_compare_op0, *arm_compare_op1;
1825 extern int arm_compare_fp;
1826
1827 /* Define the codes that are matched by predicates in arm.c */
1828 #define PREDICATE_CODES \
1829 {"s_register_operand", {SUBREG, REG}}, \
1830 {"f_register_operand", {SUBREG, REG}}, \
1831 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
1832 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1833 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
1834 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1835 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
1836 {"offsettable_memory_operand", {MEM}}, \
1837 {"bad_signed_byte_operand", {MEM}}, \
1838 {"alignable_memory_operand", {MEM}}, \
1839 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
1840 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
1841 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
1842 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
1843 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
1844 {"load_multiple_operation", {PARALLEL}}, \
1845 {"store_multiple_operation", {PARALLEL}}, \
1846 {"equality_operator", {EQ, NE}}, \
1847 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1848 {"const_shift_operand", {CONST_INT}}, \
1849 {"index_operand", {SUBREG, REG, CONST_INT}}, \
1850 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
1851 {"multi_register_push", {PARALLEL}}, \
1852 {"cc_register", {REG}}, \
1853 {"dominant_cc_register", {REG}},
1854
1855 \f
1856
1857 /* Gcc puts the pool in the wrong place for ARM, since we can only
1858 load addresses a limited distance around the pc. We do some
1859 special munging to move the constant pool values to the correct
1860 point in the code. */
1861 #define MACHINE_DEPENDENT_REORG(INSN) arm_reorg ((INSN))
1862
1863 /* The pool is empty, since we have moved everything into the code. */
1864 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE,X,MODE,ALIGN,LABELNO,JUMPTO) \
1865 goto JUMPTO
1866
1867 /* Output an internal label definition. */
1868 #ifndef ASM_OUTPUT_INTERNAL_LABEL
1869 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1870 do \
1871 { \
1872 char * s = (char *) alloca (40 + strlen (PREFIX)); \
1873 extern int arm_target_label, arm_ccfsm_state; \
1874 extern rtx arm_target_insn; \
1875 \
1876 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1877 && !strcmp (PREFIX, "L")) \
1878 { \
1879 arm_ccfsm_state = 0; \
1880 arm_target_insn = NULL; \
1881 } \
1882 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
1883 ASM_OUTPUT_LABEL (STREAM, s); \
1884 } while (0)
1885 #endif
1886
1887 /* Output a push or a pop instruction (only used when profiling). */
1888 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1889 fprintf (STREAM,"\tstmfd\t%ssp!,{%s%s}\n", \
1890 REGISTER_PREFIX, REGISTER_PREFIX, reg_names [REGNO])
1891
1892 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1893 fprintf (STREAM,"\tldmfd\t%ssp!,{%s%s}\n", \
1894 REGISTER_PREFIX, REGISTER_PREFIX, reg_names [REGNO])
1895
1896 /* Target characters. */
1897 #define TARGET_BELL 007
1898 #define TARGET_BS 010
1899 #define TARGET_TAB 011
1900 #define TARGET_NEWLINE 012
1901 #define TARGET_VT 013
1902 #define TARGET_FF 014
1903 #define TARGET_CR 015
1904 \f
1905 /* Only perform branch elimination (by making instructions conditional) if
1906 we're optimising. Otherwise it's of no use anyway. */
1907 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1908 if (optimize) \
1909 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1910
1911 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1912 ((CODE) == '?' || (CODE) == '|' || (CODE) == '@')
1913 /* Output an operand of an instruction. */
1914 #define PRINT_OPERAND(STREAM, X, CODE) \
1915 arm_print_operand (STREAM, X, CODE)
1916
1917 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
1918 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
1919 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \
1920 (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \
1921 ? ((~ (HOST_WIDE_INT) 0) \
1922 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
1923 : 0))))
1924
1925 /* Output the address of an operand. */
1926 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
1927 { \
1928 int is_minus = GET_CODE (X) == MINUS; \
1929 \
1930 if (GET_CODE (X) == REG) \
1931 fprintf (STREAM, "[%s%s, #0]", REGISTER_PREFIX, \
1932 reg_names[REGNO (X)]); \
1933 else if (GET_CODE (X) == PLUS || is_minus) \
1934 { \
1935 rtx base = XEXP (X, 0); \
1936 rtx index = XEXP (X, 1); \
1937 char * base_reg_name; \
1938 HOST_WIDE_INT offset = 0; \
1939 if (GET_CODE (base) != REG) \
1940 { \
1941 /* Ensure that BASE is a register (one of them must be). */ \
1942 rtx temp = base; \
1943 base = index; \
1944 index = temp; \
1945 } \
1946 base_reg_name = reg_names[REGNO (base)]; \
1947 switch (GET_CODE (index)) \
1948 { \
1949 case CONST_INT: \
1950 offset = INTVAL (index); \
1951 if (is_minus) \
1952 offset = -offset; \
1953 fprintf (STREAM, "[%s%s, #%d]", REGISTER_PREFIX, \
1954 base_reg_name, offset); \
1955 break; \
1956 \
1957 case REG: \
1958 fprintf (STREAM, "[%s%s, %s%s%s]", REGISTER_PREFIX, \
1959 base_reg_name, is_minus ? "-" : "", \
1960 REGISTER_PREFIX, reg_names[REGNO (index)] ); \
1961 break; \
1962 \
1963 case MULT: \
1964 case ASHIFTRT: \
1965 case LSHIFTRT: \
1966 case ASHIFT: \
1967 case ROTATERT: \
1968 { \
1969 fprintf (STREAM, "[%s%s, %s%s%s", REGISTER_PREFIX, \
1970 base_reg_name, is_minus ? "-" : "", REGISTER_PREFIX,\
1971 reg_names[REGNO (XEXP (index, 0))]); \
1972 arm_print_operand (STREAM, index, 'S'); \
1973 fputs ("]", STREAM); \
1974 break; \
1975 } \
1976 \
1977 default: \
1978 abort(); \
1979 } \
1980 } \
1981 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
1982 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
1983 { \
1984 extern int output_memory_reference_mode; \
1985 \
1986 if (GET_CODE (XEXP (X, 0)) != REG) \
1987 abort (); \
1988 \
1989 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
1990 fprintf (STREAM, "[%s%s, #%s%d]!", REGISTER_PREFIX, \
1991 reg_names[REGNO (XEXP (X, 0))], \
1992 GET_CODE (X) == PRE_DEC ? "-" : "", \
1993 GET_MODE_SIZE (output_memory_reference_mode)); \
1994 else \
1995 fprintf (STREAM, "[%s%s], #%s%d", REGISTER_PREFIX, \
1996 reg_names[REGNO (XEXP (X, 0))], \
1997 GET_CODE (X) == POST_DEC ? "-" : "", \
1998 GET_MODE_SIZE (output_memory_reference_mode)); \
1999 } \
2000 else output_addr_const(STREAM, X); \
2001 }
2002
2003 /* Handles PIC addr specially */
2004 #define OUTPUT_INT_ADDR_CONST(STREAM,X) \
2005 { \
2006 if (flag_pic && GET_CODE(X) == CONST && is_pic(X)) \
2007 { \
2008 output_addr_const(STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \
2009 fputs(" - (", STREAM); \
2010 output_addr_const(STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \
2011 fputs(")", STREAM); \
2012 } \
2013 else output_addr_const(STREAM, X); \
2014 }
2015
2016 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2017 Used for C++ multiple inheritance. */
2018 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2019 do { \
2020 int mi_delta = (DELTA); \
2021 char *mi_op = mi_delta < 0 ? "sub" : "add"; \
2022 int shift = 0; \
2023 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
2024 ? 1 : 0); \
2025 if (mi_delta < 0) mi_delta = -mi_delta; \
2026 while (mi_delta != 0) \
2027 { \
2028 if (mi_delta & (3 << shift) == 0) \
2029 shift += 2; \
2030 else \
2031 { \
2032 fprintf (FILE, "\t%s\t%s%s, %s%s, #%d\n", \
2033 mi_op, REGISTER_PREFIX, reg_names[this_regno], \
2034 REGISTER_PREFIX, reg_names[this_regno], \
2035 mi_delta & (0xff << shift)); \
2036 mi_delta &= ~(0xff << shift); \
2037 shift += 8; \
2038 } \
2039 } \
2040 fputs ("\tb\t", FILE); \
2041 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2042 fputc ('\n', FILE); \
2043 } while (0)
2044
2045 /* A C expression whose value is RTL representing the value of the return
2046 address for the frame COUNT steps up from the current frame. */
2047
2048 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2049 ((COUNT == 0) \
2050 ? gen_rtx_MEM (Pmode, plus_constant (FRAME, -4)) \
2051 : NULL_RTX)
2052
2053 /* Used to mask out junk bits from the return address, such as
2054 processor state, interrupt status, condition codes and the like. */
2055 #define MASK_RETURN_ADDR \
2056 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2057 in 26 bit mode, the condition codes must be masked out of the \
2058 return address. This does not apply to ARM6 and later processors \
2059 when running in 32 bit mode. */ \
2060 ((!TARGET_APCS_32) ? (GEN_INT (0x03fffffc)) : (GEN_INT (0xffffffff)))
2061
2062 /* Prototypes for arm.c -- actually, they aren't since the types aren't
2063 fully defined yet. */
2064
2065 void arm_override_options (/* void */);
2066 int use_return_insn (/* int */);
2067 int const_ok_for_arm (/* HOST_WIDE_INT */);
2068 int const_ok_for_op (/* HOST_WIDE_INT, enum rtx_code,
2069 enum machine_mode */);
2070 int arm_split_constant (/* enum rtx_code, enum machine_mode,
2071 HOST_WIDE_INT, struct rtx_def *,
2072 struct rtx_def *, int */);
2073 enum rtx_code arm_canonicalize_comparison (/* enum rtx_code,
2074 struct rtx_def ** */);
2075 int arm_return_in_memory (/* union tree_node * */);
2076 int legitimate_pic_operand_p (/* struct rtx_def * */);
2077 struct rtx_def *legitimize_pic_address (/* struct rtx_def *,
2078 enum machine_mode,
2079 struct rtx_def * */);
2080 int is_pic (/* struct rtx_def * */);
2081 void arm_finalize_pic (/* void */);
2082 int arm_rtx_costs (/* struct rtx_def *, enum rtx_code, enum rtx_code */);
2083 int arm_adjust_cost (/* struct rtx_def *, struct rtx_def *,
2084 struct rtx_def *, int */);
2085 int const_double_rtx_ok_for_fpu (/* struct rtx_def * */);
2086 int neg_const_double_rtx_ok_for_fpu (/* struct rtx_def * */);
2087 int s_register_operand (/* struct rtx_def *, enum machine_mode */);
2088 int f_register_operand (/* struct rtx_def *, enum machine_mode */);
2089 int reg_or_int_operand (/* struct rtx_def *, enum machine_mode */);
2090 int reload_memory_operand (/* struct rtx_def *, enum machine_mode */);
2091 int arm_rhs_operand (/* struct rtx_def *, enum machine_mode */);
2092 int arm_rhsm_operand (/* struct rtx_def *, enum machine_mode */);
2093 int arm_add_operand (/* struct rtx_def *, enum machine_mode */);
2094 int arm_not_operand (/* struct rtx_def *, enum machine_mode */);
2095 int offsettable_memory_operand (/* struct rtx_def *, enum machine_mode */);
2096 int alignable_memory_operand (/* struct rtx_def *, enum machine_mode */);
2097 int bad_signed_byte_operand (/* struct rtx_def *, enum machine_mode */);
2098 int fpu_rhs_operand (/* struct rtx_def *, enum machine_mode */);
2099 int fpu_add_operand (/* struct rtx_def *, enum machine_mode */);
2100 int power_of_two_operand (/* struct rtx_def *, enum machine_mode */);
2101 int di_operand (/* struct rtx_def *, enum machine_mode */);
2102 int soft_df_operand (/* struct rtx_def *, enum machine_mode */);
2103 int index_operand (/* struct rtx_def *, enum machine_mode */);
2104 int const_shift_operand (/* struct rtx_def *, enum machine_mode */);
2105 int shiftable_operator (/* struct rtx_def *, enum machine_mode */);
2106 int shift_operator (/* struct rtx_def *, enum machine_mode */);
2107 int equality_operator (/* struct rtx_def *, enum machine_mode */);
2108 int minmax_operator (/* struct rtx_def *, enum machine_mode */);
2109 int cc_register (/* struct rtx_def *, enum machine_mode */);
2110 int dominant_cc_register (/* struct rtx_def *, enum machine_mode */);
2111 int symbol_mentioned_p (/* struct rtx_def * */);
2112 int label_mentioned_p (/* struct rtx_def * */);
2113 enum rtx_code minmax_code (/* struct rtx_def * */);
2114 int adjacent_mem_locations (/* struct rtx_def *, struct rtx_def * */);
2115 int load_multiple_operation (/* struct rtx_def *, enum machine_mode */);
2116 int store_multiple_operation (/* struct rtx_def *, enum machine_mode */);
2117 int load_multiple_sequence (/* struct rtx_def **, int, int *, int *,
2118 HOST_WIDE_INT * */);
2119 char *emit_ldm_seq (/* struct rtx_def **, int */);
2120 int store_multiple_sequence (/* struct rtx_def **, int, int *, int *,
2121 HOST_WIDE_INT * */);
2122 char *emit_stm_seq (/* struct rtx_def **, int */);
2123 int multi_register_push (/* struct rtx_def *, enum machine_mode */);
2124 int arm_valid_machine_decl_attribute (/* union tree_node *, union tree_node *,
2125 union tree_node *,
2126 union tree_node * */);
2127 struct rtx_def *arm_gen_load_multiple (/* int, int, struct rtx_def *,
2128 int, int, int, int, int */);
2129 struct rtx_def *arm_gen_store_multiple (/* int, int, struct rtx_def *,
2130 int, int, int, int, int */);
2131 int arm_gen_movstrqi (/* struct rtx_def ** */);
2132 struct rtx_def *gen_rotated_half_load (/* struct rtx_def * */);
2133 enum machine_mode arm_select_cc_mode (/* enum rtx_code, struct rtx_def *,
2134 struct rtx_def * */);
2135 struct rtx_def *gen_compare_reg (/* enum rtx_code, struct rtx_def *,
2136 struct rtx_def * */);
2137 void arm_reload_in_hi (/* struct rtx_def ** */);
2138 void arm_reload_out_hi (/* struct rtx_def ** */);
2139 void arm_reorg (/* struct rtx_def * */);
2140 char *fp_immediate_constant (/* struct rtx_def * */);
2141 void print_multi_reg (/* FILE *, char *, int, int */);
2142 char *output_call (/* struct rtx_def ** */);
2143 char *output_call_mem (/* struct rtx_def ** */);
2144 char *output_mov_long_double_fpu_from_arm (/* struct rtx_def ** */);
2145 char *output_mov_long_double_arm_from_fpu (/* struct rtx_def ** */);
2146 char *output_mov_long_double_arm_from_arm (/* struct rtx_def ** */);
2147 char *output_mov_double_fpu_from_arm (/* struct rtx_def ** */);
2148 char *output_mov_double_arm_from_fpu (/* struct rtx_def ** */);
2149 char *output_move_double (/* struct rtx_def ** */);
2150 char *output_mov_immediate (/* struct rtx_def ** */);
2151 char *output_add_immediate (/* struct rtx_def ** */);
2152 char *arithmetic_instr (/* struct rtx_def *, int */);
2153 void output_ascii_pseudo_op (/* FILE *, unsigned char *, int */);
2154 char *output_return_instruction (/* struct rtx_def *, int, int */);
2155 int arm_volatile_func (/* void */);
2156 void output_func_prologue (/* FILE *, int */);
2157 void output_func_epilogue (/* FILE *, int */);
2158 void arm_expand_prologue (/* void */);
2159 void arm_print_operand (/* FILE *, struct rtx_def *, int */);
2160 void final_prescan_insn (/* struct rtx_def *, struct rtx_def **, int */);
2161 #ifdef AOF_ASSEMBLER
2162 struct rtx_def *aof_pic_entry (/* struct rtx_def * */);
2163 void aof_dump_pic_table (/* FILE * */);
2164 char *aof_text_section (/* void */);
2165 char *aof_data_section (/* void */);
2166 void aof_add_import (/* char * */);
2167 void aof_delete_import (/* char * */);
2168 void aof_dump_imports (/* FILE * */);
2169 #endif
2170
2171 #endif /* __ARM_H__ */