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* config/arm/arm-cores.def (cortex-m1, cortex-m0)
[gcc.git] / gcc / config / arm / arm.h
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
6 and Martin Simmons (@harleqn.co.uk).
7 More major hacks by Richard Earnshaw (rearnsha@arm.com)
8 Minor hacks by Nick Clifton (nickc@cygnus.com)
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published
14 by the Free Software Foundation; either version 3, or (at your
15 option) any later version.
16
17 GCC is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 /* We can't use enum machine_mode inside a generator file because it
30 hasn't been created yet; we shouldn't be using any code that
31 needs the real definition though, so this ought to be safe. */
32 #ifdef GENERATOR_FILE
33 #define MACHMODE int
34 #else
35 #include "insn-modes.h"
36 #define MACHMODE enum machine_mode
37 #endif
38
39 #include "config/vxworks-dummy.h"
40
41 /* The architecture define. */
42 extern char arm_arch_name[];
43
44 /* Target CPU builtins. */
45 #define TARGET_CPU_CPP_BUILTINS() \
46 do \
47 { \
48 if (TARGET_DSP_MULTIPLY) \
49 builtin_define ("__ARM_FEATURE_DSP"); \
50 if (TARGET_ARM_QBIT) \
51 builtin_define ("__ARM_FEATURE_QBIT"); \
52 if (TARGET_ARM_SAT) \
53 builtin_define ("__ARM_FEATURE_SAT"); \
54 if (unaligned_access) \
55 builtin_define ("__ARM_FEATURE_UNALIGNED"); \
56 if (TARGET_ARM_FEATURE_LDREX) \
57 builtin_define_with_int_value ( \
58 "__ARM_FEATURE_LDREX", TARGET_ARM_FEATURE_LDREX); \
59 if ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB) \
60 || TARGET_ARM_ARCH_ISA_THUMB >=2) \
61 builtin_define ("__ARM_FEATURE_CLZ"); \
62 if (TARGET_INT_SIMD) \
63 builtin_define ("__ARM_FEATURE_SIMD32"); \
64 \
65 builtin_define_with_int_value ( \
66 "__ARM_SIZEOF_MINIMAL_ENUM", \
67 flag_short_enums ? 1 : 4); \
68 builtin_define_with_int_value ( \
69 "__ARM_SIZEOF_WCHAR_T", WCHAR_TYPE_SIZE); \
70 if (TARGET_ARM_ARCH_PROFILE) \
71 builtin_define_with_int_value ( \
72 "__ARM_ARCH_PROFILE", TARGET_ARM_ARCH_PROFILE); \
73 \
74 /* Define __arm__ even when in thumb mode, for \
75 consistency with armcc. */ \
76 builtin_define ("__arm__"); \
77 if (TARGET_ARM_ARCH) \
78 builtin_define_with_int_value ( \
79 "__ARM_ARCH", TARGET_ARM_ARCH); \
80 if (arm_arch_notm) \
81 builtin_define ("__ARM_ARCH_ISA_ARM"); \
82 builtin_define ("__APCS_32__"); \
83 if (TARGET_THUMB) \
84 builtin_define ("__thumb__"); \
85 if (TARGET_THUMB2) \
86 builtin_define ("__thumb2__"); \
87 if (TARGET_ARM_ARCH_ISA_THUMB) \
88 builtin_define_with_int_value ( \
89 "__ARM_ARCH_ISA_THUMB", \
90 TARGET_ARM_ARCH_ISA_THUMB); \
91 \
92 if (TARGET_BIG_END) \
93 { \
94 builtin_define ("__ARMEB__"); \
95 builtin_define ("__ARM_BIG_ENDIAN"); \
96 if (TARGET_THUMB) \
97 builtin_define ("__THUMBEB__"); \
98 if (TARGET_LITTLE_WORDS) \
99 builtin_define ("__ARMWEL__"); \
100 } \
101 else \
102 { \
103 builtin_define ("__ARMEL__"); \
104 if (TARGET_THUMB) \
105 builtin_define ("__THUMBEL__"); \
106 } \
107 \
108 if (TARGET_SOFT_FLOAT) \
109 builtin_define ("__SOFTFP__"); \
110 \
111 if (TARGET_VFP) \
112 builtin_define ("__VFP_FP__"); \
113 \
114 if (TARGET_ARM_FP) \
115 builtin_define_with_int_value ( \
116 "__ARM_FP", TARGET_ARM_FP); \
117 if (arm_fp16_format == ARM_FP16_FORMAT_IEEE) \
118 builtin_define ("__ARM_FP16_FORMAT_IEEE"); \
119 if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) \
120 builtin_define ("__ARM_FP16_FORMAT_ALTERNATIVE"); \
121 if (TARGET_FMA) \
122 builtin_define ("__ARM_FEATURE_FMA"); \
123 \
124 if (TARGET_NEON) \
125 { \
126 builtin_define ("__ARM_NEON__"); \
127 builtin_define ("__ARM_NEON"); \
128 } \
129 if (TARGET_NEON_FP) \
130 builtin_define_with_int_value ( \
131 "__ARM_NEON_FP", TARGET_NEON_FP); \
132 \
133 /* Add a define for interworking. \
134 Needed when building libgcc.a. */ \
135 if (arm_cpp_interwork) \
136 builtin_define ("__THUMB_INTERWORK__"); \
137 \
138 builtin_assert ("cpu=arm"); \
139 builtin_assert ("machine=arm"); \
140 \
141 builtin_define (arm_arch_name); \
142 if (arm_arch_xscale) \
143 builtin_define ("__XSCALE__"); \
144 if (arm_arch_iwmmxt) \
145 { \
146 builtin_define ("__IWMMXT__"); \
147 builtin_define ("__ARM_WMMX"); \
148 } \
149 if (arm_arch_iwmmxt2) \
150 builtin_define ("__IWMMXT2__"); \
151 if (TARGET_AAPCS_BASED) \
152 { \
153 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \
154 builtin_define ("__ARM_PCS_VFP"); \
155 else if (arm_pcs_default == ARM_PCS_AAPCS) \
156 builtin_define ("__ARM_PCS"); \
157 builtin_define ("__ARM_EABI__"); \
158 } \
159 if (TARGET_IDIV) \
160 builtin_define ("__ARM_ARCH_EXT_IDIV__"); \
161 } while (0)
162
163 #include "config/arm/arm-opts.h"
164
165 enum target_cpus
166 {
167 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
168 TARGET_CPU_##IDENT,
169 #include "arm-cores.def"
170 #undef ARM_CORE
171 TARGET_CPU_generic
172 };
173
174 /* The processor for which instructions should be scheduled. */
175 extern enum processor_type arm_tune;
176
177 typedef enum arm_cond_code
178 {
179 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
180 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
181 }
182 arm_cc;
183
184 extern arm_cc arm_current_cc;
185
186 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
187
188 extern int arm_target_label;
189 extern int arm_ccfsm_state;
190 extern GTY(()) rtx arm_target_insn;
191 /* The label of the current constant pool. */
192 extern rtx pool_vector_label;
193 /* Set to 1 when a return insn is output, this means that the epilogue
194 is not needed. */
195 extern int return_used_this_function;
196 /* Callback to output language specific object attributes. */
197 extern void (*arm_lang_output_object_attributes_hook)(void);
198 \f
199 /* Just in case configure has failed to define anything. */
200 #ifndef TARGET_CPU_DEFAULT
201 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
202 #endif
203
204
205 #undef CPP_SPEC
206 #define CPP_SPEC "%(subtarget_cpp_spec) \
207 %{mfloat-abi=soft:%{mfloat-abi=hard: \
208 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \
209 %{mbig-endian:%{mlittle-endian: \
210 %e-mbig-endian and -mlittle-endian may not be used together}}"
211
212 #ifndef CC1_SPEC
213 #define CC1_SPEC ""
214 #endif
215
216 /* This macro defines names of additional specifications to put in the specs
217 that can be used in various specifications like CC1_SPEC. Its definition
218 is an initializer with a subgrouping for each command option.
219
220 Each subgrouping contains a string constant, that defines the
221 specification name, and a string constant that used by the GCC driver
222 program.
223
224 Do not define this macro if it does not need to do anything. */
225 #define EXTRA_SPECS \
226 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
227 { "asm_cpu_spec", ASM_CPU_SPEC }, \
228 SUBTARGET_EXTRA_SPECS
229
230 #ifndef SUBTARGET_EXTRA_SPECS
231 #define SUBTARGET_EXTRA_SPECS
232 #endif
233
234 #ifndef SUBTARGET_CPP_SPEC
235 #define SUBTARGET_CPP_SPEC ""
236 #endif
237 \f
238 /* Run-time Target Specification. */
239 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
240 /* Use hardware floating point instructions. */
241 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
242 /* Use hardware floating point calling convention. */
243 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
244 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
245 #define TARGET_IWMMXT (arm_arch_iwmmxt)
246 #define TARGET_IWMMXT2 (arm_arch_iwmmxt2)
247 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
248 #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT)
249 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
250 #define TARGET_ARM (! TARGET_THUMB)
251 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
252 #define TARGET_BACKTRACE (leaf_function_p () \
253 ? TARGET_TPCS_LEAF_FRAME \
254 : TARGET_TPCS_FRAME)
255 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
256 #define TARGET_AAPCS_BASED \
257 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
258
259 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
260 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
261 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2)
262
263 /* Only 16-bit thumb code. */
264 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
265 /* Arm or Thumb-2 32-bit code. */
266 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
267 /* 32-bit Thumb-2 code. */
268 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
269 /* Thumb-1 only. */
270 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
271
272 /* The following two macros concern the ability to execute coprocessor
273 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
274 only ever tested when we know we are generating for VFP hardware; we need
275 to be more careful with TARGET_NEON as noted below. */
276
277 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */
278 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32)
279
280 /* FPU supports VFPv3 instructions. */
281 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
282
283 /* FPU only supports VFP single-precision instructions. */
284 #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE)
285
286 /* FPU supports VFP double-precision instructions. */
287 #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE)
288
289 /* FPU supports half-precision floating-point with NEON element load/store. */
290 #define TARGET_NEON_FP16 \
291 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16)
292
293 /* FPU supports VFP half-precision floating-point. */
294 #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16)
295
296 /* FPU supports fused-multiply-add operations. */
297 #define TARGET_FMA (TARGET_VFP && arm_fpu_desc->rev >= 4)
298
299 /* FPU supports Crypto extensions. */
300 #define TARGET_CRYPTO (TARGET_VFP && arm_fpu_desc->crypto)
301
302 /* FPU supports Neon instructions. The setting of this macro gets
303 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
304 and TARGET_HARD_FLOAT to ensure that NEON instructions are
305 available. */
306 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
307 && TARGET_VFP && arm_fpu_desc->neon)
308
309 /* Q-bit is present. */
310 #define TARGET_ARM_QBIT \
311 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7))
312 /* Saturation operation, e.g. SSAT. */
313 #define TARGET_ARM_SAT \
314 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7))
315 /* "DSP" multiply instructions, eg. SMULxy. */
316 #define TARGET_DSP_MULTIPLY \
317 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em))
318 /* Integer SIMD instructions, and extend-accumulate instructions. */
319 #define TARGET_INT_SIMD \
320 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
321
322 /* Should MOVW/MOVT be used in preference to a constant pool. */
323 #define TARGET_USE_MOVT \
324 (arm_arch_thumb2 && !optimize_size && !current_tune->prefer_constant_pool)
325
326 /* We could use unified syntax for arm mode, but for now we just use it
327 for Thumb-2. */
328 #define TARGET_UNIFIED_ASM TARGET_THUMB2
329
330 /* Nonzero if this chip provides the DMB instruction. */
331 #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7)
332
333 /* Nonzero if this chip implements a memory barrier via CP15. */
334 #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \
335 && ! TARGET_THUMB1)
336
337 /* Nonzero if this chip implements a memory barrier instruction. */
338 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
339
340 /* Nonzero if this chip supports ldrex and strex */
341 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7)
342
343 /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */
344 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7)
345
346 /* Nonzero if this chip supports ldrexd and strexd. */
347 #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) || arm_arch7) \
348 && arm_arch_notm)
349
350 /* Nonzero if integer division instructions supported. */
351 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \
352 || (TARGET_THUMB2 && arm_arch_thumb_hwdiv))
353
354 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
355 then TARGET_AAPCS_BASED must be true -- but the converse does not
356 hold. TARGET_BPABI implies the use of the BPABI runtime library,
357 etc., in addition to just the AAPCS calling conventions. */
358 #ifndef TARGET_BPABI
359 #define TARGET_BPABI false
360 #endif
361
362 /* Support for a compile-time default CPU, et cetera. The rules are:
363 --with-arch is ignored if -march or -mcpu are specified.
364 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
365 by --with-arch.
366 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
367 by -march).
368 --with-float is ignored if -mfloat-abi is specified.
369 --with-fpu is ignored if -mfpu is specified.
370 --with-abi is ignored if -mabi is specified.
371 --with-tls is ignored if -mtls-dialect is specified. */
372 #define OPTION_DEFAULT_SPECS \
373 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
374 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
375 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
376 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \
377 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
378 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
379 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \
380 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"},
381
382 /* Which floating point model to use. */
383 enum arm_fp_model
384 {
385 ARM_FP_MODEL_UNKNOWN,
386 /* VFP floating point model. */
387 ARM_FP_MODEL_VFP
388 };
389
390 enum vfp_reg_type
391 {
392 VFP_NONE = 0,
393 VFP_REG_D16,
394 VFP_REG_D32,
395 VFP_REG_SINGLE
396 };
397
398 extern const struct arm_fpu_desc
399 {
400 const char *name;
401 enum arm_fp_model model;
402 int rev;
403 enum vfp_reg_type regs;
404 int neon;
405 int fp16;
406 int crypto;
407 } *arm_fpu_desc;
408
409 /* Which floating point hardware to schedule for. */
410 extern int arm_fpu_attr;
411
412 #ifndef TARGET_DEFAULT_FLOAT_ABI
413 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
414 #endif
415
416 #define LARGEST_EXPONENT_IS_NORMAL(bits) \
417 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
418
419 #ifndef ARM_DEFAULT_ABI
420 #define ARM_DEFAULT_ABI ARM_ABI_APCS
421 #endif
422
423 /* Map each of the micro-architecture variants to their corresponding
424 major architecture revision. */
425
426 enum base_architecture
427 {
428 BASE_ARCH_0 = 0,
429 BASE_ARCH_2 = 2,
430 BASE_ARCH_3 = 3,
431 BASE_ARCH_3M = 3,
432 BASE_ARCH_4 = 4,
433 BASE_ARCH_4T = 4,
434 BASE_ARCH_5 = 5,
435 BASE_ARCH_5E = 5,
436 BASE_ARCH_5T = 5,
437 BASE_ARCH_5TE = 5,
438 BASE_ARCH_5TEJ = 5,
439 BASE_ARCH_6 = 6,
440 BASE_ARCH_6J = 6,
441 BASE_ARCH_6ZK = 6,
442 BASE_ARCH_6K = 6,
443 BASE_ARCH_6T2 = 6,
444 BASE_ARCH_6M = 6,
445 BASE_ARCH_6Z = 6,
446 BASE_ARCH_7 = 7,
447 BASE_ARCH_7A = 7,
448 BASE_ARCH_7R = 7,
449 BASE_ARCH_7M = 7,
450 BASE_ARCH_7EM = 7,
451 BASE_ARCH_8A = 8
452 };
453
454 /* The major revision number of the ARM Architecture implemented by the target. */
455 extern enum base_architecture arm_base_arch;
456
457 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
458 extern int arm_arch3m;
459
460 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
461 extern int arm_arch4;
462
463 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
464 extern int arm_arch4t;
465
466 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
467 extern int arm_arch5;
468
469 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
470 extern int arm_arch5e;
471
472 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
473 extern int arm_arch6;
474
475 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */
476 extern int arm_arch6k;
477
478 /* Nonzero if instructions present in ARMv6-M can be used. */
479 extern int arm_arch6m;
480
481 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */
482 extern int arm_arch7;
483
484 /* Nonzero if instructions not present in the 'M' profile can be used. */
485 extern int arm_arch_notm;
486
487 /* Nonzero if instructions present in ARMv7E-M can be used. */
488 extern int arm_arch7em;
489
490 /* Nonzero if this chip supports the ARM Architecture 8 extensions. */
491 extern int arm_arch8;
492
493 /* Nonzero if this chip can benefit from load scheduling. */
494 extern int arm_ld_sched;
495
496 /* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */
497 extern int thumb_code;
498
499 /* Nonzero if generating Thumb-1 code. */
500 extern int thumb1_code;
501
502 /* Nonzero if this chip is a StrongARM. */
503 extern int arm_tune_strongarm;
504
505 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
506 extern int arm_arch_iwmmxt;
507
508 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */
509 extern int arm_arch_iwmmxt2;
510
511 /* Nonzero if this chip is an XScale. */
512 extern int arm_arch_xscale;
513
514 /* Nonzero if tuning for XScale. */
515 extern int arm_tune_xscale;
516
517 /* Nonzero if tuning for stores via the write buffer. */
518 extern int arm_tune_wbuf;
519
520 /* Nonzero if tuning for Cortex-A9. */
521 extern int arm_tune_cortex_a9;
522
523 /* Nonzero if we should define __THUMB_INTERWORK__ in the
524 preprocessor.
525 XXX This is a bit of a hack, it's intended to help work around
526 problems in GLD which doesn't understand that armv5t code is
527 interworking clean. */
528 extern int arm_cpp_interwork;
529
530 /* Nonzero if chip supports Thumb 2. */
531 extern int arm_arch_thumb2;
532
533 /* Nonzero if chip supports integer division instruction in ARM mode. */
534 extern int arm_arch_arm_hwdiv;
535
536 /* Nonzero if chip supports integer division instruction in Thumb mode. */
537 extern int arm_arch_thumb_hwdiv;
538
539 #ifndef TARGET_DEFAULT
540 #define TARGET_DEFAULT (MASK_APCS_FRAME)
541 #endif
542
543 /* Nonzero if PIC code requires explicit qualifiers to generate
544 PLT and GOT relocs rather than the assembler doing so implicitly.
545 Subtargets can override these if required. */
546 #ifndef NEED_GOT_RELOC
547 #define NEED_GOT_RELOC 0
548 #endif
549 #ifndef NEED_PLT_RELOC
550 #define NEED_PLT_RELOC 0
551 #endif
552
553 /* Nonzero if we need to refer to the GOT with a PC-relative
554 offset. In other words, generate
555
556 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
557
558 rather than
559
560 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
561
562 The default is true, which matches NetBSD. Subtargets can
563 override this if required. */
564 #ifndef GOT_PCREL
565 #define GOT_PCREL 1
566 #endif
567 \f
568 /* Target machine storage Layout. */
569
570
571 /* Define this macro if it is advisable to hold scalars in registers
572 in a wider mode than that declared by the program. In such cases,
573 the value is constrained to be within the bounds of the declared
574 type, but kept valid in the wider mode. The signedness of the
575 extension may differ from that of the type. */
576
577 /* It is far faster to zero extend chars than to sign extend them */
578
579 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
580 if (GET_MODE_CLASS (MODE) == MODE_INT \
581 && GET_MODE_SIZE (MODE) < 4) \
582 { \
583 if (MODE == QImode) \
584 UNSIGNEDP = 1; \
585 else if (MODE == HImode) \
586 UNSIGNEDP = 1; \
587 (MODE) = SImode; \
588 }
589
590 /* Define this if most significant bit is lowest numbered
591 in instructions that operate on numbered bit-fields. */
592 #define BITS_BIG_ENDIAN 0
593
594 /* Define this if most significant byte of a word is the lowest numbered.
595 Most ARM processors are run in little endian mode, so that is the default.
596 If you want to have it run-time selectable, change the definition in a
597 cover file to be TARGET_BIG_ENDIAN. */
598 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
599
600 /* Define this if most significant word of a multiword number is the lowest
601 numbered.
602 This is always false, even when in big-endian mode. */
603 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
604
605 #define UNITS_PER_WORD 4
606
607 /* True if natural alignment is used for doubleword types. */
608 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
609
610 #define DOUBLEWORD_ALIGNMENT 64
611
612 #define PARM_BOUNDARY 32
613
614 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
615
616 #define PREFERRED_STACK_BOUNDARY \
617 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
618
619 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32)
620
621 /* The lowest bit is used to indicate Thumb-mode functions, so the
622 vbit must go into the delta field of pointers to member
623 functions. */
624 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
625
626 #define EMPTY_FIELD_BOUNDARY 32
627
628 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
629
630 /* XXX Blah -- this macro is used directly by libobjc. Since it
631 supports no vector modes, cut out the complexity and fall back
632 on BIGGEST_FIELD_ALIGNMENT. */
633 #ifdef IN_TARGET_LIBS
634 #define BIGGEST_FIELD_ALIGNMENT 64
635 #endif
636
637 /* Make strings word-aligned so strcpy from constants will be faster. */
638 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
639
640 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
641 ((TREE_CODE (EXP) == STRING_CST \
642 && !optimize_size \
643 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
644 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
645
646 /* Align definitions of arrays, unions and structures so that
647 initializations and copies can be made more efficient. This is not
648 ABI-changing, so it only affects places where we can see the
649 definition. Increasing the alignment tends to introduce padding,
650 so don't do this when optimizing for size/conserving stack space. */
651 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \
652 (((COND) && ((ALIGN) < BITS_PER_WORD) \
653 && (TREE_CODE (EXP) == ARRAY_TYPE \
654 || TREE_CODE (EXP) == UNION_TYPE \
655 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
656
657 /* Align global data. */
658 #define DATA_ALIGNMENT(EXP, ALIGN) \
659 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN)
660
661 /* Similarly, make sure that objects on the stack are sensibly aligned. */
662 #define LOCAL_ALIGNMENT(EXP, ALIGN) \
663 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN)
664
665 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
666 value set in previous versions of this toolchain was 8, which produces more
667 compact structures. The command line option -mstructure_size_boundary=<n>
668 can be used to change this value. For compatibility with the ARM SDK
669 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
670 0020D) page 2-20 says "Structures are aligned on word boundaries".
671 The AAPCS specifies a value of 8. */
672 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
673
674 /* This is the value used to initialize arm_structure_size_boundary. If a
675 particular arm target wants to change the default value it should change
676 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
677 for an example of this. */
678 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
679 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
680 #endif
681
682 /* Nonzero if move instructions will actually fail to work
683 when given unaligned data. */
684 #define STRICT_ALIGNMENT 1
685
686 /* wchar_t is unsigned under the AAPCS. */
687 #ifndef WCHAR_TYPE
688 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
689
690 #define WCHAR_TYPE_SIZE BITS_PER_WORD
691 #endif
692
693 /* Sized for fixed-point types. */
694
695 #define SHORT_FRACT_TYPE_SIZE 8
696 #define FRACT_TYPE_SIZE 16
697 #define LONG_FRACT_TYPE_SIZE 32
698 #define LONG_LONG_FRACT_TYPE_SIZE 64
699
700 #define SHORT_ACCUM_TYPE_SIZE 16
701 #define ACCUM_TYPE_SIZE 32
702 #define LONG_ACCUM_TYPE_SIZE 64
703 #define LONG_LONG_ACCUM_TYPE_SIZE 64
704
705 #define MAX_FIXED_MODE_SIZE 64
706
707 #ifndef SIZE_TYPE
708 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
709 #endif
710
711 #ifndef PTRDIFF_TYPE
712 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
713 #endif
714
715 /* AAPCS requires that structure alignment is affected by bitfields. */
716 #ifndef PCC_BITFIELD_TYPE_MATTERS
717 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
718 #endif
719
720 \f
721 /* Standard register usage. */
722
723 /* Register allocation in ARM Procedure Call Standard
724 (S - saved over call).
725
726 r0 * argument word/integer result
727 r1-r3 argument word
728
729 r4-r8 S register variable
730 r9 S (rfp) register variable (real frame pointer)
731
732 r10 F S (sl) stack limit (used by -mapcs-stack-check)
733 r11 F S (fp) argument pointer
734 r12 (ip) temp workspace
735 r13 F S (sp) lower end of current stack frame
736 r14 (lr) link address/workspace
737 r15 F (pc) program counter
738
739 cc This is NOT a real register, but is used internally
740 to represent things that use or set the condition
741 codes.
742 sfp This isn't either. It is used during rtl generation
743 since the offset between the frame pointer and the
744 auto's isn't known until after register allocation.
745 afp Nor this, we only need this because of non-local
746 goto. Without it fp appears to be used and the
747 elimination code won't get rid of sfp. It tracks
748 fp exactly at all times.
749
750 *: See TARGET_CONDITIONAL_REGISTER_USAGE */
751
752 /* s0-s15 VFP scratch (aka d0-d7).
753 s16-s31 S VFP variable (aka d8-d15).
754 vfpcc Not a real register. Represents the VFP condition
755 code flags. */
756
757 /* The stack backtrace structure is as follows:
758 fp points to here: | save code pointer | [fp]
759 | return link value | [fp, #-4]
760 | return sp value | [fp, #-8]
761 | return fp value | [fp, #-12]
762 [| saved r10 value |]
763 [| saved r9 value |]
764 [| saved r8 value |]
765 [| saved r7 value |]
766 [| saved r6 value |]
767 [| saved r5 value |]
768 [| saved r4 value |]
769 [| saved r3 value |]
770 [| saved r2 value |]
771 [| saved r1 value |]
772 [| saved r0 value |]
773 r0-r3 are not normally saved in a C function. */
774
775 /* 1 for registers that have pervasive standard uses
776 and are not available for the register allocator. */
777 #define FIXED_REGISTERS \
778 { \
779 /* Core regs. */ \
780 0,0,0,0,0,0,0,0, \
781 0,0,0,0,0,1,0,1, \
782 /* VFP regs. */ \
783 1,1,1,1,1,1,1,1, \
784 1,1,1,1,1,1,1,1, \
785 1,1,1,1,1,1,1,1, \
786 1,1,1,1,1,1,1,1, \
787 1,1,1,1,1,1,1,1, \
788 1,1,1,1,1,1,1,1, \
789 1,1,1,1,1,1,1,1, \
790 1,1,1,1,1,1,1,1, \
791 /* IWMMXT regs. */ \
792 1,1,1,1,1,1,1,1, \
793 1,1,1,1,1,1,1,1, \
794 1,1,1,1, \
795 /* Specials. */ \
796 1,1,1,1 \
797 }
798
799 /* 1 for registers not available across function calls.
800 These must include the FIXED_REGISTERS and also any
801 registers that can be used without being saved.
802 The latter must include the registers where values are returned
803 and the register where structure-value addresses are passed.
804 Aside from that, you can include as many other registers as you like.
805 The CC is not preserved over function calls on the ARM 6, so it is
806 easier to assume this for all. SFP is preserved, since FP is. */
807 #define CALL_USED_REGISTERS \
808 { \
809 /* Core regs. */ \
810 1,1,1,1,0,0,0,0, \
811 0,0,0,0,1,1,1,1, \
812 /* VFP Regs. */ \
813 1,1,1,1,1,1,1,1, \
814 1,1,1,1,1,1,1,1, \
815 1,1,1,1,1,1,1,1, \
816 1,1,1,1,1,1,1,1, \
817 1,1,1,1,1,1,1,1, \
818 1,1,1,1,1,1,1,1, \
819 1,1,1,1,1,1,1,1, \
820 1,1,1,1,1,1,1,1, \
821 /* IWMMXT regs. */ \
822 1,1,1,1,1,1,1,1, \
823 1,1,1,1,1,1,1,1, \
824 1,1,1,1, \
825 /* Specials. */ \
826 1,1,1,1 \
827 }
828
829 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
830 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
831 #endif
832
833 /* These are a couple of extensions to the formats accepted
834 by asm_fprintf:
835 %@ prints out ASM_COMMENT_START
836 %r prints out REGISTER_PREFIX reg_names[arg] */
837 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
838 case '@': \
839 fputs (ASM_COMMENT_START, FILE); \
840 break; \
841 \
842 case 'r': \
843 fputs (REGISTER_PREFIX, FILE); \
844 fputs (reg_names [va_arg (ARGS, int)], FILE); \
845 break;
846
847 /* Round X up to the nearest word. */
848 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
849
850 /* Convert fron bytes to ints. */
851 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
852
853 /* The number of (integer) registers required to hold a quantity of type MODE.
854 Also used for VFP registers. */
855 #define ARM_NUM_REGS(MODE) \
856 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
857
858 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
859 #define ARM_NUM_REGS2(MODE, TYPE) \
860 ARM_NUM_INTS ((MODE) == BLKmode ? \
861 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
862
863 /* The number of (integer) argument register available. */
864 #define NUM_ARG_REGS 4
865
866 /* And similarly for the VFP. */
867 #define NUM_VFP_ARG_REGS 16
868
869 /* Return the register number of the N'th (integer) argument. */
870 #define ARG_REGISTER(N) (N - 1)
871
872 /* Specify the registers used for certain standard purposes.
873 The values of these macros are register numbers. */
874
875 /* The number of the last argument register. */
876 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
877
878 /* The numbers of the Thumb register ranges. */
879 #define FIRST_LO_REGNUM 0
880 #define LAST_LO_REGNUM 7
881 #define FIRST_HI_REGNUM 8
882 #define LAST_HI_REGNUM 11
883
884 /* Overridden by config/arm/bpabi.h. */
885 #ifndef ARM_UNWIND_INFO
886 #define ARM_UNWIND_INFO 0
887 #endif
888
889 /* Use r0 and r1 to pass exception handling information. */
890 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
891
892 /* The register that holds the return address in exception handlers. */
893 #define ARM_EH_STACKADJ_REGNUM 2
894 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
895
896 #ifndef ARM_TARGET2_DWARF_FORMAT
897 #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel
898
899 /* ttype entries (the only interesting data references used)
900 use TARGET2 relocations. */
901 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \
902 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \
903 : DW_EH_PE_absptr)
904 #endif
905
906 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
907 as an invisible last argument (possible since varargs don't exist in
908 Pascal), so the following is not true. */
909 #define STATIC_CHAIN_REGNUM 12
910
911 /* Define this to be where the real frame pointer is if it is not possible to
912 work out the offset between the frame pointer and the automatic variables
913 until after register allocation has taken place. FRAME_POINTER_REGNUM
914 should point to a special register that we will make sure is eliminated.
915
916 For the Thumb we have another problem. The TPCS defines the frame pointer
917 as r11, and GCC believes that it is always possible to use the frame pointer
918 as base register for addressing purposes. (See comments in
919 find_reloads_address()). But - the Thumb does not allow high registers,
920 including r11, to be used as base address registers. Hence our problem.
921
922 The solution used here, and in the old thumb port is to use r7 instead of
923 r11 as the hard frame pointer and to have special code to generate
924 backtrace structures on the stack (if required to do so via a command line
925 option) using r11. This is the only 'user visible' use of r11 as a frame
926 pointer. */
927 #define ARM_HARD_FRAME_POINTER_REGNUM 11
928 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
929
930 #define HARD_FRAME_POINTER_REGNUM \
931 (TARGET_ARM \
932 ? ARM_HARD_FRAME_POINTER_REGNUM \
933 : THUMB_HARD_FRAME_POINTER_REGNUM)
934
935 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
936 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
937
938 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
939
940 /* Register to use for pushing function arguments. */
941 #define STACK_POINTER_REGNUM SP_REGNUM
942
943 #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1)
944 #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15)
945 #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1)
946 #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3)
947
948 #define IS_IWMMXT_REGNUM(REGNUM) \
949 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
950 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
951 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
952
953 /* Base register for access to local variables of the function. */
954 #define FRAME_POINTER_REGNUM 102
955
956 /* Base register for access to arguments of the function. */
957 #define ARG_POINTER_REGNUM 103
958
959 #define FIRST_VFP_REGNUM 16
960 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15)
961 #define LAST_VFP_REGNUM \
962 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
963
964 #define IS_VFP_REGNUM(REGNUM) \
965 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
966
967 /* VFP registers are split into two types: those defined by VFP versions < 3
968 have D registers overlaid on consecutive pairs of S registers. VFP version 3
969 defines 16 new D registers (d16-d31) which, for simplicity and correctness
970 in various parts of the backend, we implement as "fake" single-precision
971 registers (which would be S32-S63, but cannot be used in that way). The
972 following macros define these ranges of registers. */
973 #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31)
974 #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1)
975 #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31)
976
977 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
978 ((REGNUM) <= LAST_LO_VFP_REGNUM)
979
980 /* DFmode values are only valid in even register pairs. */
981 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
982 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
983
984 /* Neon Quad values must start at a multiple of four registers. */
985 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
986 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
987
988 /* Neon structures of vectors must be in even register pairs and there
989 must be enough registers available. Because of various patterns
990 requiring quad registers, we require them to start at a multiple of
991 four. */
992 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
993 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
994 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
995
996 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP. */
997 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
998 /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */
999 #define FIRST_PSEUDO_REGISTER 104
1000
1001 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1002
1003 /* Value should be nonzero if functions must have frame pointers.
1004 Zero means the frame pointer need not be set up (and parms may be accessed
1005 via the stack pointer) in functions that seem suitable.
1006 If we have to have a frame pointer we might as well make use of it.
1007 APCS says that the frame pointer does not need to be pushed in leaf
1008 functions, or simple tail call functions. */
1009
1010 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1011 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1012 #endif
1013
1014 /* Return number of consecutive hard regs needed starting at reg REGNO
1015 to hold something of mode MODE.
1016 This is ordinarily the length in words of a value of mode MODE
1017 but can be less for certain modes in special long registers.
1018
1019 On the ARM core regs are UNITS_PER_WORD bits wide. */
1020 #define HARD_REGNO_NREGS(REGNO, MODE) \
1021 ((TARGET_32BIT \
1022 && REGNO > PC_REGNUM \
1023 && REGNO != FRAME_POINTER_REGNUM \
1024 && REGNO != ARG_POINTER_REGNUM) \
1025 && !IS_VFP_REGNUM (REGNO) \
1026 ? 1 : ARM_NUM_REGS (MODE))
1027
1028 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1029 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1030 arm_hard_regno_mode_ok ((REGNO), (MODE))
1031
1032 #define MODES_TIEABLE_P(MODE1, MODE2) arm_modes_tieable_p (MODE1, MODE2)
1033
1034 #define VALID_IWMMXT_REG_MODE(MODE) \
1035 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1036
1037 /* Modes valid for Neon D registers. */
1038 #define VALID_NEON_DREG_MODE(MODE) \
1039 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1040 || (MODE) == V2SFmode || (MODE) == DImode)
1041
1042 /* Modes valid for Neon Q registers. */
1043 #define VALID_NEON_QREG_MODE(MODE) \
1044 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1045 || (MODE) == V4SFmode || (MODE) == V2DImode)
1046
1047 /* Structure modes valid for Neon registers. */
1048 #define VALID_NEON_STRUCT_MODE(MODE) \
1049 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1050 || (MODE) == CImode || (MODE) == XImode)
1051
1052 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */
1053 extern int arm_regs_in_sequence[];
1054
1055 /* The order in which register should be allocated. It is good to use ip
1056 since no saving is required (though calls clobber it) and it never contains
1057 function parameters. It is quite good to use lr since other calls may
1058 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1059 least likely to contain a function parameter; in addition results are
1060 returned in r0.
1061 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1062 then D8-D15. The reason for doing this is to attempt to reduce register
1063 pressure when both single- and double-precision registers are used in a
1064 function. */
1065
1066 #define VREG(X) (FIRST_VFP_REGNUM + (X))
1067 #define WREG(X) (FIRST_IWMMXT_REGNUM + (X))
1068 #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X))
1069
1070 #define REG_ALLOC_ORDER \
1071 { \
1072 /* General registers. */ \
1073 3, 2, 1, 0, 12, 14, 4, 5, \
1074 6, 7, 8, 9, 10, 11, \
1075 /* High VFP registers. */ \
1076 VREG(32), VREG(33), VREG(34), VREG(35), \
1077 VREG(36), VREG(37), VREG(38), VREG(39), \
1078 VREG(40), VREG(41), VREG(42), VREG(43), \
1079 VREG(44), VREG(45), VREG(46), VREG(47), \
1080 VREG(48), VREG(49), VREG(50), VREG(51), \
1081 VREG(52), VREG(53), VREG(54), VREG(55), \
1082 VREG(56), VREG(57), VREG(58), VREG(59), \
1083 VREG(60), VREG(61), VREG(62), VREG(63), \
1084 /* VFP argument registers. */ \
1085 VREG(15), VREG(14), VREG(13), VREG(12), \
1086 VREG(11), VREG(10), VREG(9), VREG(8), \
1087 VREG(7), VREG(6), VREG(5), VREG(4), \
1088 VREG(3), VREG(2), VREG(1), VREG(0), \
1089 /* VFP call-saved registers. */ \
1090 VREG(16), VREG(17), VREG(18), VREG(19), \
1091 VREG(20), VREG(21), VREG(22), VREG(23), \
1092 VREG(24), VREG(25), VREG(26), VREG(27), \
1093 VREG(28), VREG(29), VREG(30), VREG(31), \
1094 /* IWMMX registers. */ \
1095 WREG(0), WREG(1), WREG(2), WREG(3), \
1096 WREG(4), WREG(5), WREG(6), WREG(7), \
1097 WREG(8), WREG(9), WREG(10), WREG(11), \
1098 WREG(12), WREG(13), WREG(14), WREG(15), \
1099 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \
1100 /* Registers not for general use. */ \
1101 CC_REGNUM, VFPCC_REGNUM, \
1102 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \
1103 SP_REGNUM, PC_REGNUM \
1104 }
1105
1106 /* Use different register alloc ordering for Thumb. */
1107 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
1108
1109 /* Tell IRA to use the order we define rather than messing it up with its
1110 own cost calculations. */
1111 #define HONOR_REG_ALLOC_ORDER
1112
1113 /* Interrupt functions can only use registers that have already been
1114 saved by the prologue, even if they would normally be
1115 call-clobbered. */
1116 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1117 (! IS_INTERRUPT (cfun->machine->func_type) || \
1118 df_regs_ever_live_p (DST))
1119 \f
1120 /* Register and constant classes. */
1121
1122 /* Register classes. */
1123 enum reg_class
1124 {
1125 NO_REGS,
1126 LO_REGS,
1127 STACK_REG,
1128 BASE_REGS,
1129 HI_REGS,
1130 GENERAL_REGS,
1131 CORE_REGS,
1132 VFP_D0_D7_REGS,
1133 VFP_LO_REGS,
1134 VFP_HI_REGS,
1135 VFP_REGS,
1136 IWMMXT_REGS,
1137 IWMMXT_GR_REGS,
1138 CC_REG,
1139 VFPCC_REG,
1140 SFP_REG,
1141 AFP_REG,
1142 ALL_REGS,
1143 LIM_REG_CLASSES
1144 };
1145
1146 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1147
1148 /* Give names of register classes as strings for dump file. */
1149 #define REG_CLASS_NAMES \
1150 { \
1151 "NO_REGS", \
1152 "LO_REGS", \
1153 "STACK_REG", \
1154 "BASE_REGS", \
1155 "HI_REGS", \
1156 "GENERAL_REGS", \
1157 "CORE_REGS", \
1158 "VFP_D0_D7_REGS", \
1159 "VFP_LO_REGS", \
1160 "VFP_HI_REGS", \
1161 "VFP_REGS", \
1162 "IWMMXT_REGS", \
1163 "IWMMXT_GR_REGS", \
1164 "CC_REG", \
1165 "VFPCC_REG", \
1166 "ALL_REGS", \
1167 }
1168
1169 /* Define which registers fit in which classes.
1170 This is an initializer for a vector of HARD_REG_SET
1171 of length N_REG_CLASSES. */
1172 #define REG_CLASS_CONTENTS \
1173 { \
1174 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1175 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1176 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1177 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1178 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1179 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1180 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
1181 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1182 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \
1183 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \
1184 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \
1185 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \
1186 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \
1187 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \
1188 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \
1189 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \
1190 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \
1191 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000 } /* ALL_REGS */ \
1192 }
1193
1194 /* Any of the VFP register classes. */
1195 #define IS_VFP_CLASS(X) \
1196 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1197 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1198
1199 /* The same information, inverted:
1200 Return the class number of the smallest class containing
1201 reg number REGNO. This could be a conditional expression
1202 or could index an array. */
1203 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1204
1205 /* In VFPv1, VFP registers could only be accessed in the mode they
1206 were set, so subregs would be invalid there. However, we don't
1207 support VFPv1 at the moment, and the restriction was lifted in
1208 VFPv2.
1209 In big-endian mode, modes greater than word size (i.e. DFmode) are stored in
1210 VFP registers in little-endian order. We can't describe that accurately to
1211 GCC, so avoid taking subregs of such values. */
1212 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1213 (TARGET_VFP && TARGET_BIG_END \
1214 && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \
1215 || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \
1216 && reg_classes_intersect_p (VFP_REGS, (CLASS)))
1217
1218 /* The class value for index registers, and the one for base regs. */
1219 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1220 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1221
1222 /* For the Thumb the high registers cannot be used as base registers
1223 when addressing quantities in QI or HI mode; if we don't know the
1224 mode, then we must be conservative. */
1225 #define MODE_BASE_REG_CLASS(MODE) \
1226 (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS : \
1227 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1228
1229 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1230 instead of BASE_REGS. */
1231 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1232
1233 /* When this hook returns true for MODE, the compiler allows
1234 registers explicitly used in the rtl to be used as spill registers
1235 but prevents the compiler from extending the lifetime of these
1236 registers. */
1237 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1238 arm_small_register_classes_for_mode_p
1239
1240 /* Must leave BASE_REGS reloads alone */
1241 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1242 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1243 ? ((true_regnum (X) == -1 ? LO_REGS \
1244 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1245 : NO_REGS)) \
1246 : NO_REGS)
1247
1248 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1249 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1250 ? ((true_regnum (X) == -1 ? LO_REGS \
1251 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1252 : NO_REGS)) \
1253 : NO_REGS)
1254
1255 /* Return the register class of a scratch register needed to copy IN into
1256 or out of a register in CLASS in MODE. If it can be done directly,
1257 NO_REGS is returned. */
1258 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1259 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1260 ((TARGET_VFP && TARGET_HARD_FLOAT \
1261 && IS_VFP_CLASS (CLASS)) \
1262 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1263 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1264 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1265 : TARGET_32BIT \
1266 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1267 ? GENERAL_REGS : NO_REGS) \
1268 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1269
1270 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1271 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1272 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1273 ((TARGET_VFP && TARGET_HARD_FLOAT \
1274 && IS_VFP_CLASS (CLASS)) \
1275 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1276 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1277 coproc_secondary_reload_class (MODE, X, TRUE) : \
1278 (TARGET_32BIT ? \
1279 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1280 && CONSTANT_P (X)) \
1281 ? GENERAL_REGS : \
1282 (((MODE) == HImode && ! arm_arch4 \
1283 && (MEM_P (X) \
1284 || ((REG_P (X) || GET_CODE (X) == SUBREG) \
1285 && true_regnum (X) == -1))) \
1286 ? GENERAL_REGS : NO_REGS) \
1287 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1288
1289 /* Try a machine-dependent way of reloading an illegitimate address
1290 operand. If we find one, push the reload and jump to WIN. This
1291 macro is used in only one place: `find_reloads_address' in reload.c.
1292
1293 For the ARM, we wish to handle large displacements off a base
1294 register by splitting the addend across a MOV and the mem insn.
1295 This can cut the number of reloads needed. */
1296 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1297 do \
1298 { \
1299 if (arm_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND)) \
1300 goto WIN; \
1301 } \
1302 while (0)
1303
1304 /* XXX If an HImode FP+large_offset address is converted to an HImode
1305 SP+large_offset address, then reload won't know how to fix it. It sees
1306 only that SP isn't valid for HImode, and so reloads the SP into an index
1307 register, but the resulting address is still invalid because the offset
1308 is too big. We fix it here instead by reloading the entire address. */
1309 /* We could probably achieve better results by defining PROMOTE_MODE to help
1310 cope with the variances between the Thumb's signed and unsigned byte and
1311 halfword load instructions. */
1312 /* ??? This should be safe for thumb2, but we may be able to do better. */
1313 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1314 do { \
1315 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1316 if (new_x) \
1317 { \
1318 X = new_x; \
1319 goto WIN; \
1320 } \
1321 } while (0)
1322
1323 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1324 if (TARGET_ARM) \
1325 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1326 else \
1327 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1328
1329 /* Return the maximum number of consecutive registers
1330 needed to represent mode MODE in a register of class CLASS.
1331 ARM regs are UNITS_PER_WORD bits.
1332 FIXME: Is this true for iWMMX? */
1333 #define CLASS_MAX_NREGS(CLASS, MODE) \
1334 (ARM_NUM_REGS (MODE))
1335
1336 /* If defined, gives a class of registers that cannot be used as the
1337 operand of a SUBREG that changes the mode of the object illegally. */
1338 \f
1339 /* Stack layout; function entry, exit and calling. */
1340
1341 /* Define this if pushing a word on the stack
1342 makes the stack pointer a smaller address. */
1343 #define STACK_GROWS_DOWNWARD 1
1344
1345 /* Define this to nonzero if the nominal address of the stack frame
1346 is at the high-address end of the local variables;
1347 that is, each additional local variable allocated
1348 goes at a more negative offset in the frame. */
1349 #define FRAME_GROWS_DOWNWARD 1
1350
1351 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1352 When present, it is one word in size, and sits at the top of the frame,
1353 between the soft frame pointer and either r7 or r11.
1354
1355 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1356 and only then if some outgoing arguments are passed on the stack. It would
1357 be tempting to also check whether the stack arguments are passed by indirect
1358 calls, but there seems to be no reason in principle why a post-reload pass
1359 couldn't convert a direct call into an indirect one. */
1360 #define CALLER_INTERWORKING_SLOT_SIZE \
1361 (TARGET_CALLER_INTERWORKING \
1362 && crtl->outgoing_args_size != 0 \
1363 ? UNITS_PER_WORD : 0)
1364
1365 /* Offset within stack frame to start allocating local variables at.
1366 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1367 first local allocated. Otherwise, it is the offset to the BEGINNING
1368 of the first local allocated. */
1369 #define STARTING_FRAME_OFFSET 0
1370
1371 /* If we generate an insn to push BYTES bytes,
1372 this says how many the stack pointer really advances by. */
1373 /* The push insns do not do this rounding implicitly.
1374 So don't define this. */
1375 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1376
1377 /* Define this if the maximum size of all the outgoing args is to be
1378 accumulated and pushed during the prologue. The amount can be
1379 found in the variable crtl->outgoing_args_size. */
1380 #define ACCUMULATE_OUTGOING_ARGS 1
1381
1382 /* Offset of first parameter from the argument pointer register value. */
1383 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1384
1385 /* Amount of memory needed for an untyped call to save all possible return
1386 registers. */
1387 #define APPLY_RESULT_SIZE arm_apply_result_size()
1388
1389 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1390 values must be in memory. On the ARM, they need only do so if larger
1391 than a word, or if they contain elements offset from zero in the struct. */
1392 #define DEFAULT_PCC_STRUCT_RETURN 0
1393
1394 /* These bits describe the different types of function supported
1395 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1396 normal function and an interworked function, for example. Knowing the
1397 type of a function is important for determining its prologue and
1398 epilogue sequences.
1399 Note value 7 is currently unassigned. Also note that the interrupt
1400 function types all have bit 2 set, so that they can be tested for easily.
1401 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1402 machine_function structure is initialized (to zero) func_type will
1403 default to unknown. This will force the first use of arm_current_func_type
1404 to call arm_compute_func_type. */
1405 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1406 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1407 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1408 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1409 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1410 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1411
1412 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1413
1414 /* In addition functions can have several type modifiers,
1415 outlined by these bit masks: */
1416 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1417 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1418 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1419 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1420 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1421
1422 /* Some macros to test these flags. */
1423 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1424 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1425 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1426 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1427 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1428 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1429
1430
1431 /* Structure used to hold the function stack frame layout. Offsets are
1432 relative to the stack pointer on function entry. Positive offsets are
1433 in the direction of stack growth.
1434 Only soft_frame is used in thumb mode. */
1435
1436 typedef struct GTY(()) arm_stack_offsets
1437 {
1438 int saved_args; /* ARG_POINTER_REGNUM. */
1439 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1440 int saved_regs;
1441 int soft_frame; /* FRAME_POINTER_REGNUM. */
1442 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1443 int outgoing_args; /* STACK_POINTER_REGNUM. */
1444 unsigned int saved_regs_mask;
1445 }
1446 arm_stack_offsets;
1447
1448 #ifndef GENERATOR_FILE
1449 /* A C structure for machine-specific, per-function data.
1450 This is added to the cfun structure. */
1451 typedef struct GTY(()) machine_function
1452 {
1453 /* Additional stack adjustment in __builtin_eh_throw. */
1454 rtx eh_epilogue_sp_ofs;
1455 /* Records if LR has to be saved for far jumps. */
1456 int far_jump_used;
1457 /* Records if ARG_POINTER was ever live. */
1458 int arg_pointer_live;
1459 /* Records if the save of LR has been eliminated. */
1460 int lr_save_eliminated;
1461 /* The size of the stack frame. Only valid after reload. */
1462 arm_stack_offsets stack_offsets;
1463 /* Records the type of the current function. */
1464 unsigned long func_type;
1465 /* Record if the function has a variable argument list. */
1466 int uses_anonymous_args;
1467 /* Records if sibcalls are blocked because an argument
1468 register is needed to preserve stack alignment. */
1469 int sibcall_blocked;
1470 /* The PIC register for this function. This might be a pseudo. */
1471 rtx pic_reg;
1472 /* Labels for per-function Thumb call-via stubs. One per potential calling
1473 register. We can never call via LR or PC. We can call via SP if a
1474 trampoline happens to be on the top of the stack. */
1475 rtx call_via[14];
1476 /* Set to 1 when a return insn is output, this means that the epilogue
1477 is not needed. */
1478 int return_used_this_function;
1479 /* When outputting Thumb-1 code, record the last insn that provides
1480 information about condition codes, and the comparison operands. */
1481 rtx thumb1_cc_insn;
1482 rtx thumb1_cc_op0;
1483 rtx thumb1_cc_op1;
1484 /* Also record the CC mode that is supported. */
1485 enum machine_mode thumb1_cc_mode;
1486 }
1487 machine_function;
1488 #endif
1489
1490 /* As in the machine_function, a global set of call-via labels, for code
1491 that is in text_section. */
1492 extern GTY(()) rtx thumb_call_via_label[14];
1493
1494 /* The number of potential ways of assigning to a co-processor. */
1495 #define ARM_NUM_COPROC_SLOTS 1
1496
1497 /* Enumeration of procedure calling standard variants. We don't really
1498 support all of these yet. */
1499 enum arm_pcs
1500 {
1501 ARM_PCS_AAPCS, /* Base standard AAPCS. */
1502 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */
1503 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */
1504 /* This must be the last AAPCS variant. */
1505 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */
1506 ARM_PCS_ATPCS, /* ATPCS. */
1507 ARM_PCS_APCS, /* APCS (legacy Linux etc). */
1508 ARM_PCS_UNKNOWN
1509 };
1510
1511 /* Default procedure calling standard of current compilation unit. */
1512 extern enum arm_pcs arm_pcs_default;
1513
1514 /* A C type for declaring a variable that is used as the first argument of
1515 `FUNCTION_ARG' and other related values. */
1516 typedef struct
1517 {
1518 /* This is the number of registers of arguments scanned so far. */
1519 int nregs;
1520 /* This is the number of iWMMXt register arguments scanned so far. */
1521 int iwmmxt_nregs;
1522 int named_count;
1523 int nargs;
1524 /* Which procedure call variant to use for this call. */
1525 enum arm_pcs pcs_variant;
1526
1527 /* AAPCS related state tracking. */
1528 int aapcs_arg_processed; /* No need to lay out this argument again. */
1529 int aapcs_cprc_slot; /* Index of co-processor rules to handle
1530 this argument, or -1 if using core
1531 registers. */
1532 int aapcs_ncrn;
1533 int aapcs_next_ncrn;
1534 rtx aapcs_reg; /* Register assigned to this argument. */
1535 int aapcs_partial; /* How many bytes are passed in regs (if
1536 split between core regs and stack.
1537 Zero otherwise. */
1538 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS];
1539 int can_split; /* Argument can be split between core regs
1540 and the stack. */
1541 /* Private data for tracking VFP register allocation */
1542 unsigned aapcs_vfp_regs_free;
1543 unsigned aapcs_vfp_reg_alloc;
1544 int aapcs_vfp_rcount;
1545 MACHMODE aapcs_vfp_rmode;
1546 } CUMULATIVE_ARGS;
1547
1548 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1549 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1550
1551 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1552 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1553
1554 /* For AAPCS, padding should never be below the argument. For other ABIs,
1555 * mimic the default. */
1556 #define PAD_VARARGS_DOWN \
1557 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1558
1559 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1560 for a call to a function whose data type is FNTYPE.
1561 For a library call, FNTYPE is 0.
1562 On the ARM, the offset starts at 0. */
1563 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1564 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1565
1566 /* 1 if N is a possible register number for function argument passing.
1567 On the ARM, r0-r3 are used to pass args. */
1568 #define FUNCTION_ARG_REGNO_P(REGNO) \
1569 (IN_RANGE ((REGNO), 0, 3) \
1570 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \
1571 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
1572 || (TARGET_IWMMXT_ABI \
1573 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1574
1575 \f
1576 /* If your target environment doesn't prefix user functions with an
1577 underscore, you may wish to re-define this to prevent any conflicts. */
1578 #ifndef ARM_MCOUNT_NAME
1579 #define ARM_MCOUNT_NAME "*mcount"
1580 #endif
1581
1582 /* Call the function profiler with a given profile label. The Acorn
1583 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1584 On the ARM the full profile code will look like:
1585 .data
1586 LP1
1587 .word 0
1588 .text
1589 mov ip, lr
1590 bl mcount
1591 .word LP1
1592
1593 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1594 will output the .text section.
1595
1596 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1597 ``prof'' doesn't seem to mind about this!
1598
1599 Note - this version of the code is designed to work in both ARM and
1600 Thumb modes. */
1601 #ifndef ARM_FUNCTION_PROFILER
1602 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1603 { \
1604 char temp[20]; \
1605 rtx sym; \
1606 \
1607 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1608 IP_REGNUM, LR_REGNUM); \
1609 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1610 fputc ('\n', STREAM); \
1611 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1612 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1613 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1614 }
1615 #endif
1616
1617 #ifdef THUMB_FUNCTION_PROFILER
1618 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1619 if (TARGET_ARM) \
1620 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1621 else \
1622 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1623 #else
1624 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1625 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1626 #endif
1627
1628 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1629 the stack pointer does not matter. The value is tested only in
1630 functions that have frame pointers.
1631 No definition is equivalent to always zero.
1632
1633 On the ARM, the function epilogue recovers the stack pointer from the
1634 frame. */
1635 #define EXIT_IGNORE_STACK 1
1636
1637 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1638
1639 /* Determine if the epilogue should be output as RTL.
1640 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1641 #define USE_RETURN_INSN(ISCOND) \
1642 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0)
1643
1644 /* Definitions for register eliminations.
1645
1646 This is an array of structures. Each structure initializes one pair
1647 of eliminable registers. The "from" register number is given first,
1648 followed by "to". Eliminations of the same "from" register are listed
1649 in order of preference.
1650
1651 We have two registers that can be eliminated on the ARM. First, the
1652 arg pointer register can often be eliminated in favor of the stack
1653 pointer register. Secondly, the pseudo frame pointer register can always
1654 be eliminated; it is replaced with either the stack or the real frame
1655 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1656 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1657
1658 #define ELIMINABLE_REGS \
1659 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1660 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1661 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1662 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1663 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1664 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1665 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1666
1667 /* Define the offset between two registers, one to be eliminated, and the
1668 other its replacement, at the start of a routine. */
1669 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1670 if (TARGET_ARM) \
1671 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1672 else \
1673 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1674
1675 /* Special case handling of the location of arguments passed on the stack. */
1676 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1677
1678 /* Initialize data used by insn expanders. This is called from insn_emit,
1679 once for every function before code is generated. */
1680 #define INIT_EXPANDERS arm_init_expanders ()
1681
1682 /* Length in units of the trampoline for entering a nested function. */
1683 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1684
1685 /* Alignment required for a trampoline in bits. */
1686 #define TRAMPOLINE_ALIGNMENT 32
1687 \f
1688 /* Addressing modes, and classification of registers for them. */
1689 #define HAVE_POST_INCREMENT 1
1690 #define HAVE_PRE_INCREMENT TARGET_32BIT
1691 #define HAVE_POST_DECREMENT TARGET_32BIT
1692 #define HAVE_PRE_DECREMENT TARGET_32BIT
1693 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1694 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1695 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1696 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1697
1698 enum arm_auto_incmodes
1699 {
1700 ARM_POST_INC,
1701 ARM_PRE_INC,
1702 ARM_POST_DEC,
1703 ARM_PRE_DEC
1704 };
1705
1706 #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \
1707 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code))
1708 #define USE_LOAD_POST_INCREMENT(mode) \
1709 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC)
1710 #define USE_LOAD_PRE_INCREMENT(mode) \
1711 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC)
1712 #define USE_LOAD_POST_DECREMENT(mode) \
1713 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC)
1714 #define USE_LOAD_PRE_DECREMENT(mode) \
1715 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC)
1716
1717 #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode)
1718 #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode)
1719 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode)
1720 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode)
1721
1722 /* Macros to check register numbers against specific register classes. */
1723
1724 /* These assume that REGNO is a hard or pseudo reg number.
1725 They give nonzero only if REGNO is a hard reg of the suitable class
1726 or a pseudo reg currently allocated to a suitable hard reg.
1727 Since they use reg_renumber, they are safe only once reg_renumber
1728 has been allocated, which happens in local-alloc.c. */
1729 #define TEST_REGNO(R, TEST, VALUE) \
1730 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1731
1732 /* Don't allow the pc to be used. */
1733 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1734 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1735 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1736 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1737
1738 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1739 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1740 || (GET_MODE_SIZE (MODE) >= 4 \
1741 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1742
1743 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1744 (TARGET_THUMB1 \
1745 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1746 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1747
1748 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1749 For Thumb, we can not use SP + reg, so reject SP. */
1750 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1751 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1752
1753 /* For ARM code, we don't care about the mode, but for Thumb, the index
1754 must be suitable for use in a QImode load. */
1755 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1756 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1757 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1758
1759 /* Maximum number of registers that can appear in a valid memory address.
1760 Shifts in addresses can't be by a register. */
1761 #define MAX_REGS_PER_ADDRESS 2
1762
1763 /* Recognize any constant value that is a valid address. */
1764 /* XXX We can address any constant, eventually... */
1765 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1766 #define CONSTANT_ADDRESS_P(X) \
1767 (GET_CODE (X) == SYMBOL_REF \
1768 && (CONSTANT_POOL_ADDRESS_P (X) \
1769 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1770
1771 /* True if SYMBOL + OFFSET constants must refer to something within
1772 SYMBOL's section. */
1773 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1774
1775 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1776 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1777 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
1778 #endif
1779
1780 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1781 #define SUBTARGET_NAME_ENCODING_LENGTHS
1782 #endif
1783
1784 /* This is a C fragment for the inside of a switch statement.
1785 Each case label should return the number of characters to
1786 be stripped from the start of a function's name, if that
1787 name starts with the indicated character. */
1788 #define ARM_NAME_ENCODING_LENGTHS \
1789 case '*': return 1; \
1790 SUBTARGET_NAME_ENCODING_LENGTHS
1791
1792 /* This is how to output a reference to a user-level label named NAME.
1793 `assemble_name' uses this. */
1794 #undef ASM_OUTPUT_LABELREF
1795 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1796 arm_asm_output_labelref (FILE, NAME)
1797
1798 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1799 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1800 if (TARGET_THUMB2) \
1801 thumb2_asm_output_opcode (STREAM);
1802
1803 /* The EABI specifies that constructors should go in .init_array.
1804 Other targets use .ctors for compatibility. */
1805 #ifndef ARM_EABI_CTORS_SECTION_OP
1806 #define ARM_EABI_CTORS_SECTION_OP \
1807 "\t.section\t.init_array,\"aw\",%init_array"
1808 #endif
1809 #ifndef ARM_EABI_DTORS_SECTION_OP
1810 #define ARM_EABI_DTORS_SECTION_OP \
1811 "\t.section\t.fini_array,\"aw\",%fini_array"
1812 #endif
1813 #define ARM_CTORS_SECTION_OP \
1814 "\t.section\t.ctors,\"aw\",%progbits"
1815 #define ARM_DTORS_SECTION_OP \
1816 "\t.section\t.dtors,\"aw\",%progbits"
1817
1818 /* Define CTORS_SECTION_ASM_OP. */
1819 #undef CTORS_SECTION_ASM_OP
1820 #undef DTORS_SECTION_ASM_OP
1821 #ifndef IN_LIBGCC2
1822 # define CTORS_SECTION_ASM_OP \
1823 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1824 # define DTORS_SECTION_ASM_OP \
1825 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1826 #else /* !defined (IN_LIBGCC2) */
1827 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1828 so we cannot use the definition above. */
1829 # ifdef __ARM_EABI__
1830 /* The .ctors section is not part of the EABI, so we do not define
1831 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1832 from trying to use it. We do define it when doing normal
1833 compilation, as .init_array can be used instead of .ctors. */
1834 /* There is no need to emit begin or end markers when using
1835 init_array; the dynamic linker will compute the size of the
1836 array itself based on special symbols created by the static
1837 linker. However, we do need to arrange to set up
1838 exception-handling here. */
1839 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1840 # define CTOR_LIST_END /* empty */
1841 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1842 # define DTOR_LIST_END /* empty */
1843 # else /* !defined (__ARM_EABI__) */
1844 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1845 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1846 # endif /* !defined (__ARM_EABI__) */
1847 #endif /* !defined (IN_LIBCC2) */
1848
1849 /* True if the operating system can merge entities with vague linkage
1850 (e.g., symbols in COMDAT group) during dynamic linking. */
1851 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1852 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1853 #endif
1854
1855 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
1856
1857 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1858 and check its validity for a certain class.
1859 We have two alternate definitions for each of them.
1860 The usual definition accepts all pseudo regs; the other rejects
1861 them unless they have been allocated suitable hard regs.
1862 The symbol REG_OK_STRICT causes the latter definition to be used.
1863 Thumb-2 has the same restrictions as arm. */
1864 #ifndef REG_OK_STRICT
1865
1866 #define ARM_REG_OK_FOR_BASE_P(X) \
1867 (REGNO (X) <= LAST_ARM_REGNUM \
1868 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1869 || REGNO (X) == FRAME_POINTER_REGNUM \
1870 || REGNO (X) == ARG_POINTER_REGNUM)
1871
1872 #define ARM_REG_OK_FOR_INDEX_P(X) \
1873 ((REGNO (X) <= LAST_ARM_REGNUM \
1874 && REGNO (X) != STACK_POINTER_REGNUM) \
1875 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1876 || REGNO (X) == FRAME_POINTER_REGNUM \
1877 || REGNO (X) == ARG_POINTER_REGNUM)
1878
1879 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1880 (REGNO (X) <= LAST_LO_REGNUM \
1881 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1882 || (GET_MODE_SIZE (MODE) >= 4 \
1883 && (REGNO (X) == STACK_POINTER_REGNUM \
1884 || (X) == hard_frame_pointer_rtx \
1885 || (X) == arg_pointer_rtx)))
1886
1887 #define REG_STRICT_P 0
1888
1889 #else /* REG_OK_STRICT */
1890
1891 #define ARM_REG_OK_FOR_BASE_P(X) \
1892 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
1893
1894 #define ARM_REG_OK_FOR_INDEX_P(X) \
1895 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
1896
1897 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1898 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
1899
1900 #define REG_STRICT_P 1
1901
1902 #endif /* REG_OK_STRICT */
1903
1904 /* Now define some helpers in terms of the above. */
1905
1906 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1907 (TARGET_THUMB1 \
1908 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
1909 : ARM_REG_OK_FOR_BASE_P (X))
1910
1911 /* For 16-bit Thumb, a valid index register is anything that can be used in
1912 a byte load instruction. */
1913 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
1914 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
1915
1916 /* Nonzero if X is a hard reg that can be used as an index
1917 or if it is a pseudo reg. On the Thumb, the stack pointer
1918 is not suitable. */
1919 #define REG_OK_FOR_INDEX_P(X) \
1920 (TARGET_THUMB1 \
1921 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
1922 : ARM_REG_OK_FOR_INDEX_P (X))
1923
1924 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1925 For Thumb, we can not use SP + reg, so reject SP. */
1926 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1927 REG_OK_FOR_INDEX_P (X)
1928 \f
1929 #define ARM_BASE_REGISTER_RTX_P(X) \
1930 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X))
1931
1932 #define ARM_INDEX_REGISTER_RTX_P(X) \
1933 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X))
1934 \f
1935 /* Specify the machine mode that this machine uses
1936 for the index in the tablejump instruction. */
1937 #define CASE_VECTOR_MODE Pmode
1938
1939 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \
1940 || (TARGET_THUMB1 \
1941 && (optimize_size || flag_pic)))
1942
1943 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
1944 (TARGET_THUMB1 \
1945 ? (min >= 0 && max < 512 \
1946 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
1947 : min >= -256 && max < 256 \
1948 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \
1949 : min >= 0 && max < 8192 \
1950 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \
1951 : min >= -4096 && max < 4096 \
1952 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
1953 : SImode) \
1954 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \
1955 : (max >= 0x200) ? HImode \
1956 : QImode))
1957
1958 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1959 unsigned is probably best, but may break some code. */
1960 #ifndef DEFAULT_SIGNED_CHAR
1961 #define DEFAULT_SIGNED_CHAR 0
1962 #endif
1963
1964 /* Max number of bytes we can move from memory to memory
1965 in one reasonably fast instruction. */
1966 #define MOVE_MAX 4
1967
1968 #undef MOVE_RATIO
1969 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
1970
1971 /* Define if operations between registers always perform the operation
1972 on the full register even if a narrower mode is specified. */
1973 #define WORD_REGISTER_OPERATIONS
1974
1975 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1976 will either zero-extend or sign-extend. The value of this macro should
1977 be the code that says which one of the two operations is implicitly
1978 done, UNKNOWN if none. */
1979 #define LOAD_EXTEND_OP(MODE) \
1980 (TARGET_THUMB ? ZERO_EXTEND : \
1981 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
1982 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
1983
1984 /* Nonzero if access to memory by bytes is slow and undesirable. */
1985 #define SLOW_BYTE_ACCESS 0
1986
1987 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
1988
1989 /* Immediate shift counts are truncated by the output routines (or was it
1990 the assembler?). Shift counts in a register are truncated by ARM. Note
1991 that the native compiler puts too large (> 32) immediate shift counts
1992 into a register and shifts by the register, letting the ARM decide what
1993 to do instead of doing that itself. */
1994 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1995 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1996 On the arm, Y in a register is used modulo 256 for the shift. Only for
1997 rotates is modulo 32 used. */
1998 /* #define SHIFT_COUNT_TRUNCATED 1 */
1999
2000 /* All integers have the same format so truncation is easy. */
2001 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2002
2003 /* Calling from registers is a massive pain. */
2004 #define NO_FUNCTION_CSE 1
2005
2006 /* The machine modes of pointers and functions */
2007 #define Pmode SImode
2008 #define FUNCTION_MODE Pmode
2009
2010 #define ARM_FRAME_RTX(X) \
2011 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2012 || (X) == arg_pointer_rtx)
2013
2014 /* Try to generate sequences that don't involve branches, we can then use
2015 conditional instructions. */
2016 #define BRANCH_COST(speed_p, predictable_p) \
2017 (current_tune->branch_cost (speed_p, predictable_p))
2018
2019 /* False if short circuit operation is preferred. */
2020 #define LOGICAL_OP_NON_SHORT_CIRCUIT \
2021 ((optimize_size) \
2022 ? (TARGET_THUMB ? false : true) \
2023 : (current_tune->logical_op_non_short_circuit[TARGET_ARM]))
2024
2025 \f
2026 /* Position Independent Code. */
2027 /* We decide which register to use based on the compilation options and
2028 the assembler in use; this is more general than the APCS restriction of
2029 using sb (r9) all the time. */
2030 extern unsigned arm_pic_register;
2031
2032 /* The register number of the register used to address a table of static
2033 data addresses in memory. */
2034 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2035
2036 /* We can't directly access anything that contains a symbol,
2037 nor can we indirect via the constant pool. One exception is
2038 UNSPEC_TLS, which is always PIC. */
2039 #define LEGITIMATE_PIC_OPERAND_P(X) \
2040 (!(symbol_mentioned_p (X) \
2041 || label_mentioned_p (X) \
2042 || (GET_CODE (X) == SYMBOL_REF \
2043 && CONSTANT_POOL_ADDRESS_P (X) \
2044 && (symbol_mentioned_p (get_pool_constant (X)) \
2045 || label_mentioned_p (get_pool_constant (X))))) \
2046 || tls_mentioned_p (X))
2047
2048 /* We need to know when we are making a constant pool; this determines
2049 whether data needs to be in the GOT or can be referenced via a GOT
2050 offset. */
2051 extern int making_const_table;
2052 \f
2053 /* Handle pragmas for compatibility with Intel's compilers. */
2054 /* Also abuse this to register additional C specific EABI attributes. */
2055 #define REGISTER_TARGET_PRAGMAS() do { \
2056 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2057 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2058 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2059 arm_lang_object_attributes_init(); \
2060 } while (0)
2061
2062 /* Condition code information. */
2063 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2064 return the mode to be used for the comparison. */
2065
2066 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2067
2068 #define REVERSIBLE_CC_MODE(MODE) 1
2069
2070 #define REVERSE_CONDITION(CODE,MODE) \
2071 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2072 ? reverse_condition_maybe_unordered (code) \
2073 : reverse_condition (code))
2074
2075 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2076 (CODE) = arm_canonicalize_comparison (CODE, &(OP0), &(OP1))
2077
2078 /* The arm5 clz instruction returns 32. */
2079 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2080 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2081 \f
2082 #define CC_STATUS_INIT \
2083 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0)
2084
2085 #undef ASM_APP_OFF
2086 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2087 TARGET_THUMB2 ? "\t.thumb\n" : "")
2088
2089 /* Output a push or a pop instruction (only used when profiling).
2090 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know
2091 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and
2092 that r7 isn't used by the function profiler, so we can use it as a
2093 scratch reg. WARNING: This isn't safe in the general case! It may be
2094 sensitive to future changes in final.c:profile_function. */
2095 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2096 do \
2097 { \
2098 if (TARGET_ARM) \
2099 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2100 STACK_POINTER_REGNUM, REGNO); \
2101 else if (TARGET_THUMB1 \
2102 && (REGNO) == STATIC_CHAIN_REGNUM) \
2103 { \
2104 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2105 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\
2106 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2107 } \
2108 else \
2109 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2110 } while (0)
2111
2112
2113 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */
2114 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2115 do \
2116 { \
2117 if (TARGET_ARM) \
2118 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2119 STACK_POINTER_REGNUM, REGNO); \
2120 else if (TARGET_THUMB1 \
2121 && (REGNO) == STATIC_CHAIN_REGNUM) \
2122 { \
2123 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2124 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\
2125 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2126 } \
2127 else \
2128 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2129 } while (0)
2130
2131 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2132 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2133
2134 /* This is how to output a label which precedes a jumptable. Since
2135 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2136 #undef ASM_OUTPUT_CASE_LABEL
2137 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2138 do \
2139 { \
2140 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2141 ASM_OUTPUT_ALIGN (FILE, 2); \
2142 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2143 } \
2144 while (0)
2145
2146 /* Make sure subsequent insns are aligned after a TBB. */
2147 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2148 do \
2149 { \
2150 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2151 ASM_OUTPUT_ALIGN (FILE, 1); \
2152 } \
2153 while (0)
2154
2155 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2156 do \
2157 { \
2158 if (TARGET_THUMB) \
2159 { \
2160 if (is_called_in_ARM_mode (DECL) \
2161 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
2162 && cfun->is_thunk)) \
2163 fprintf (STREAM, "\t.code 32\n") ; \
2164 else if (TARGET_THUMB1) \
2165 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2166 else \
2167 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2168 } \
2169 if (TARGET_POKE_FUNCTION_NAME) \
2170 arm_poke_function_name (STREAM, (const char *) NAME); \
2171 } \
2172 while (0)
2173
2174 /* For aliases of functions we use .thumb_set instead. */
2175 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2176 do \
2177 { \
2178 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2179 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2180 \
2181 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2182 { \
2183 fprintf (FILE, "\t.thumb_set "); \
2184 assemble_name (FILE, LABEL1); \
2185 fprintf (FILE, ","); \
2186 assemble_name (FILE, LABEL2); \
2187 fprintf (FILE, "\n"); \
2188 } \
2189 else \
2190 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2191 } \
2192 while (0)
2193
2194 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2195 /* To support -falign-* switches we need to use .p2align so
2196 that alignment directives in code sections will be padded
2197 with no-op instructions, rather than zeroes. */
2198 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2199 if ((LOG) != 0) \
2200 { \
2201 if ((MAX_SKIP) == 0) \
2202 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2203 else \
2204 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2205 (int) (LOG), (int) (MAX_SKIP)); \
2206 }
2207 #endif
2208 \f
2209 /* Add two bytes to the length of conditionally executed Thumb-2
2210 instructions for the IT instruction. */
2211 #define ADJUST_INSN_LENGTH(insn, length) \
2212 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2213 length += 2;
2214
2215 /* Only perform branch elimination (by making instructions conditional) if
2216 we're optimizing. For Thumb-2 check if any IT instructions need
2217 outputting. */
2218 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2219 if (TARGET_ARM && optimize) \
2220 arm_final_prescan_insn (INSN); \
2221 else if (TARGET_THUMB2) \
2222 thumb2_final_prescan_insn (INSN); \
2223 else if (TARGET_THUMB1) \
2224 thumb1_final_prescan_insn (INSN)
2225
2226 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2227 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2228 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2229 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2230 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2231 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2232 : 0))))
2233
2234 /* A C expression whose value is RTL representing the value of the return
2235 address for the frame COUNT steps up from the current frame. */
2236
2237 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2238 arm_return_addr (COUNT, FRAME)
2239
2240 /* Mask of the bits in the PC that contain the real return address
2241 when running in 26-bit mode. */
2242 #define RETURN_ADDR_MASK26 (0x03fffffc)
2243
2244 /* Pick up the return address upon entry to a procedure. Used for
2245 dwarf2 unwind information. This also enables the table driven
2246 mechanism. */
2247 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2248 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2249
2250 /* Used to mask out junk bits from the return address, such as
2251 processor state, interrupt status, condition codes and the like. */
2252 #define MASK_RETURN_ADDR \
2253 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2254 in 26 bit mode, the condition codes must be masked out of the \
2255 return address. This does not apply to ARM6 and later processors \
2256 when running in 32 bit mode. */ \
2257 ((arm_arch4 || TARGET_THUMB) \
2258 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2259 : arm_gen_return_addr_mask ())
2260
2261 \f
2262 /* Do not emit .note.GNU-stack by default. */
2263 #ifndef NEED_INDICATE_EXEC_STACK
2264 #define NEED_INDICATE_EXEC_STACK 0
2265 #endif
2266
2267 #define TARGET_ARM_ARCH \
2268 (arm_base_arch) \
2269
2270 #define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2)
2271 #define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2)
2272
2273 /* The highest Thumb instruction set version supported by the chip. */
2274 #define TARGET_ARM_ARCH_ISA_THUMB \
2275 (arm_arch_thumb2 ? 2 \
2276 : ((TARGET_ARM_ARCH >= 5 || arm_arch4t) ? 1 : 0))
2277
2278 /* Expands to an upper-case char of the target's architectural
2279 profile. */
2280 #define TARGET_ARM_ARCH_PROFILE \
2281 (!arm_arch_notm \
2282 ? 'M' \
2283 : (arm_arch7 \
2284 ? (strlen (arm_arch_name) >=3 \
2285 ? (arm_arch_name[strlen (arm_arch_name) - 3]) \
2286 : 0) \
2287 : 0))
2288
2289 /* Bit-field indicating what size LDREX/STREX loads/stores are available.
2290 Bit 0 for bytes, up to bit 3 for double-words. */
2291 #define TARGET_ARM_FEATURE_LDREX \
2292 ((TARGET_HAVE_LDREX ? 4 : 0) \
2293 | (TARGET_HAVE_LDREXBH ? 3 : 0) \
2294 | (TARGET_HAVE_LDREXD ? 8 : 0))
2295
2296 /* Set as a bit mask indicating the available widths of hardware floating
2297 point types. Where bit 1 indicates 16-bit support, bit 2 indicates
2298 32-bit support, bit 3 indicates 64-bit support. */
2299 #define TARGET_ARM_FP \
2300 (TARGET_VFP_SINGLE ? 4 \
2301 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0))
2302
2303
2304 /* Set as a bit mask indicating the available widths of floating point
2305 types for hardware NEON floating point. This is the same as
2306 TARGET_ARM_FP without the 64-bit bit set. */
2307 #ifdef TARGET_NEON
2308 #define TARGET_NEON_FP \
2309 (TARGET_ARM_FP & (0xff ^ 0x08))
2310 #endif
2311
2312 /* The maximum number of parallel loads or stores we support in an ldm/stm
2313 instruction. */
2314 #define MAX_LDM_STM_OPS 4
2315
2316 #define ASM_CPU_SPEC \
2317 " %{mcpu=generic-*:-march=%*;" \
2318 " :%{mcpu=*:-mcpu=%*} %{march=*:-march=%*}}"
2319
2320 /* -mcpu=native handling only makes sense with compiler running on
2321 an ARM chip. */
2322 #if defined(__arm__)
2323 extern const char *host_detect_local_cpu (int argc, const char **argv);
2324 # define EXTRA_SPEC_FUNCTIONS \
2325 { "local_cpu_detect", host_detect_local_cpu },
2326
2327 # define MCPU_MTUNE_NATIVE_SPECS \
2328 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \
2329 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \
2330 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
2331 #else
2332 # define MCPU_MTUNE_NATIVE_SPECS ""
2333 #endif
2334
2335 #define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS
2336
2337 #endif /* ! GCC_ARM_H */