alpha-modes.def: Fix comment formatting.
[gcc.git] / gcc / config / arm / arm.h
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
15
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
24 MA 02111-1307, USA. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 /* Target CPU builtins. */
30 #define TARGET_CPU_CPP_BUILTINS() \
31 do \
32 { \
33 if (TARGET_ARM) \
34 builtin_define ("__arm__"); \
35 else \
36 builtin_define ("__thumb__"); \
37 \
38 if (TARGET_BIG_END) \
39 { \
40 builtin_define ("__ARMEB__"); \
41 if (TARGET_THUMB) \
42 builtin_define ("__THUMBEB__"); \
43 if (TARGET_LITTLE_WORDS) \
44 builtin_define ("__ARMWEL__"); \
45 } \
46 else \
47 { \
48 builtin_define ("__ARMEL__"); \
49 if (TARGET_THUMB) \
50 builtin_define ("__THUMBEL__"); \
51 } \
52 \
53 if (TARGET_APCS_32) \
54 builtin_define ("__APCS_32__"); \
55 else \
56 builtin_define ("__APCS_26__"); \
57 \
58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
60 \
61 /* FIXME: TARGET_HARD_FLOAT currently implies \
62 FPA. */ \
63 if (TARGET_VFP && !TARGET_HARD_FLOAT) \
64 builtin_define ("__VFP_FP__"); \
65 \
66 /* Add a define for interworking. \
67 Needed when building libgcc.a. */ \
68 if (TARGET_INTERWORK) \
69 builtin_define ("__THUMB_INTERWORK__"); \
70 \
71 builtin_assert ("cpu=arm"); \
72 builtin_assert ("machine=arm"); \
73 } while (0)
74
75 #define TARGET_CPU_arm2 0x0000
76 #define TARGET_CPU_arm250 0x0000
77 #define TARGET_CPU_arm3 0x0000
78 #define TARGET_CPU_arm6 0x0001
79 #define TARGET_CPU_arm600 0x0001
80 #define TARGET_CPU_arm610 0x0002
81 #define TARGET_CPU_arm7 0x0001
82 #define TARGET_CPU_arm7m 0x0004
83 #define TARGET_CPU_arm7dm 0x0004
84 #define TARGET_CPU_arm7dmi 0x0004
85 #define TARGET_CPU_arm700 0x0001
86 #define TARGET_CPU_arm710 0x0002
87 #define TARGET_CPU_arm7100 0x0002
88 #define TARGET_CPU_arm7500 0x0002
89 #define TARGET_CPU_arm7500fe 0x1001
90 #define TARGET_CPU_arm7tdmi 0x0008
91 #define TARGET_CPU_arm8 0x0010
92 #define TARGET_CPU_arm810 0x0020
93 #define TARGET_CPU_strongarm 0x0040
94 #define TARGET_CPU_strongarm110 0x0040
95 #define TARGET_CPU_strongarm1100 0x0040
96 #define TARGET_CPU_arm9 0x0080
97 #define TARGET_CPU_arm9tdmi 0x0080
98 #define TARGET_CPU_xscale 0x0100
99 #define TARGET_CPU_ep9312 0x0200
100 #define TARGET_CPU_iwmmxt 0x0400
101 #define TARGET_CPU_arm926ej_s 0x0800
102 #define TARGET_CPU_arm1026ej_s 0x1000
103 #define TARGET_CPU_arm1136j_s 0x2000
104 #define TARGET_CPU_arm1136jf_s 0x4000
105 /* Configure didn't specify. */
106 #define TARGET_CPU_generic 0x8000
107
108 typedef enum arm_cond_code
109 {
110 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
111 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
112 }
113 arm_cc;
114
115 extern arm_cc arm_current_cc;
116
117 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
118
119 extern int arm_target_label;
120 extern int arm_ccfsm_state;
121 extern GTY(()) rtx arm_target_insn;
122 /* Run-time compilation parameters selecting different hardware subsets. */
123 extern int target_flags;
124 /* The floating point instruction architecture, can be 2 or 3 */
125 extern const char * target_fp_name;
126 /* Define the information needed to generate branch insns. This is
127 stored from the compare operation. */
128 extern GTY(()) rtx arm_compare_op0;
129 extern GTY(()) rtx arm_compare_op1;
130 /* The label of the current constant pool. */
131 extern rtx pool_vector_label;
132 /* Set to 1 when a return insn is output, this means that the epilogue
133 is not needed. */
134 extern int return_used_this_function;
135 /* Used to produce AOF syntax assembler. */
136 extern GTY(()) rtx aof_pic_label;
137 \f
138 /* Just in case configure has failed to define anything. */
139 #ifndef TARGET_CPU_DEFAULT
140 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
141 #endif
142
143 /* If the configuration file doesn't specify the cpu, the subtarget may
144 override it. If it doesn't, then default to an ARM6. */
145 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
146 #undef TARGET_CPU_DEFAULT
147
148 #ifdef SUBTARGET_CPU_DEFAULT
149 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
150 #else
151 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
152 #endif
153 #endif
154
155 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
156 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
157 #else
158 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
159 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
160 #else
161 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
162 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
163 #else
164 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi
165 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
166 #else
167 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
168 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
169 #else
170 #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale
171 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__"
172 #else
173 #if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312
174 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__ -D__MAVERICK__"
175 /* Set TARGET_DEFAULT to the default, but without soft-float. */
176 #ifdef TARGET_DEFAULT
177 #undef TARGET_DEFAULT
178 #define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME)
179 #endif
180 #else
181 #if TARGET_CPU_DEFAULT == TARGET_CPU_iwmmxt
182 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__ -D__IWMMXT__"
183 #else
184 #error Unrecognized value in TARGET_CPU_DEFAULT.
185 #endif
186 #endif
187 #endif
188 #endif
189 #endif
190 #endif
191 #endif
192 #endif
193
194 #undef CPP_SPEC
195 #define CPP_SPEC "%(cpp_cpu_arch) %(subtarget_cpp_spec) \
196 %{mapcs-32:%{mapcs-26: \
197 %e-mapcs-26 and -mapcs-32 may not be used together}} \
198 %{msoft-float:%{mhard-float: \
199 %e-msoft-float and -mhard_float may not be used together}} \
200 %{mbig-endian:%{mlittle-endian: \
201 %e-mbig-endian and -mlittle-endian may not be used together}}"
202
203 /* Set the architecture define -- if -march= is set, then it overrides
204 the -mcpu= setting. */
205 #define CPP_CPU_ARCH_SPEC "\
206 %{march=arm2:-D__ARM_ARCH_2__} \
207 %{march=arm250:-D__ARM_ARCH_2__} \
208 %{march=arm3:-D__ARM_ARCH_2__} \
209 %{march=arm6:-D__ARM_ARCH_3__} \
210 %{march=arm600:-D__ARM_ARCH_3__} \
211 %{march=arm610:-D__ARM_ARCH_3__} \
212 %{march=arm7:-D__ARM_ARCH_3__} \
213 %{march=arm700:-D__ARM_ARCH_3__} \
214 %{march=arm710:-D__ARM_ARCH_3__} \
215 %{march=arm720:-D__ARM_ARCH_3__} \
216 %{march=arm7100:-D__ARM_ARCH_3__} \
217 %{march=arm7500:-D__ARM_ARCH_3__} \
218 %{march=arm7500fe:-D__ARM_ARCH_3__} \
219 %{march=arm7m:-D__ARM_ARCH_3M__} \
220 %{march=arm7dm:-D__ARM_ARCH_3M__} \
221 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
222 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
223 %{march=arm8:-D__ARM_ARCH_4__} \
224 %{march=arm810:-D__ARM_ARCH_4__} \
225 %{march=arm9:-D__ARM_ARCH_4T__} \
226 %{march=arm920:-D__ARM_ARCH_4__} \
227 %{march=arm920t:-D__ARM_ARCH_4T__} \
228 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
229 %{march=strongarm:-D__ARM_ARCH_4__} \
230 %{march=strongarm110:-D__ARM_ARCH_4__} \
231 %{march=strongarm1100:-D__ARM_ARCH_4__} \
232 %{march=xscale:-D__ARM_ARCH_5TE__} \
233 %{march=xscale:-D__XSCALE__} \
234 %{march=ep9312:-D__ARM_ARCH_4T__} \
235 %{march=ep9312:-D__MAVERICK__} \
236 %{march=armv2:-D__ARM_ARCH_2__} \
237 %{march=armv2a:-D__ARM_ARCH_2__} \
238 %{march=armv3:-D__ARM_ARCH_3__} \
239 %{march=armv3m:-D__ARM_ARCH_3M__} \
240 %{march=armv4:-D__ARM_ARCH_4__} \
241 %{march=armv4t:-D__ARM_ARCH_4T__} \
242 %{march=armv5:-D__ARM_ARCH_5__} \
243 %{march=armv5t:-D__ARM_ARCH_5T__} \
244 %{march=armv5e:-D__ARM_ARCH_5E__} \
245 %{march=armv5te:-D__ARM_ARCH_5TE__} \
246 %{!march=*: \
247 %{mcpu=arm2:-D__ARM_ARCH_2__} \
248 %{mcpu=arm250:-D__ARM_ARCH_2__} \
249 %{mcpu=arm3:-D__ARM_ARCH_2__} \
250 %{mcpu=arm6:-D__ARM_ARCH_3__} \
251 %{mcpu=arm600:-D__ARM_ARCH_3__} \
252 %{mcpu=arm610:-D__ARM_ARCH_3__} \
253 %{mcpu=arm7:-D__ARM_ARCH_3__} \
254 %{mcpu=arm700:-D__ARM_ARCH_3__} \
255 %{mcpu=arm710:-D__ARM_ARCH_3__} \
256 %{mcpu=arm720:-D__ARM_ARCH_3__} \
257 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
258 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
259 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
260 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
261 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
262 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
263 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
264 %{mcpu=arm8:-D__ARM_ARCH_4__} \
265 %{mcpu=arm810:-D__ARM_ARCH_4__} \
266 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
267 %{mcpu=arm920:-D__ARM_ARCH_4__} \
268 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
269 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
270 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
271 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
272 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
273 %{mcpu=xscale:-D__ARM_ARCH_5TE__} \
274 %{mcpu=xscale:-D__XSCALE__} \
275 %{mcpu=ep9312:-D__ARM_ARCH_4T__} \
276 %{mcpu=ep9312:-D__MAVERICK__} \
277 %{mcpu=iwmmxt:-D__ARM_ARCH_5TE__} \
278 %{mcpu=iwmmxt:-D__XSCALE__} \
279 %{mcpu=iwmmxt:-D__IWMMXT__} \
280 %{!mcpu*:%(cpp_cpu_arch_default)}} \
281 "
282
283 #ifndef CC1_SPEC
284 #define CC1_SPEC ""
285 #endif
286
287 /* This macro defines names of additional specifications to put in the specs
288 that can be used in various specifications like CC1_SPEC. Its definition
289 is an initializer with a subgrouping for each command option.
290
291 Each subgrouping contains a string constant, that defines the
292 specification name, and a string constant that used by the GCC driver
293 program.
294
295 Do not define this macro if it does not need to do anything. */
296 #define EXTRA_SPECS \
297 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
298 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
299 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
300 SUBTARGET_EXTRA_SPECS
301
302 #ifndef SUBTARGET_EXTRA_SPECS
303 #define SUBTARGET_EXTRA_SPECS
304 #endif
305
306 #ifndef SUBTARGET_CPP_SPEC
307 #define SUBTARGET_CPP_SPEC ""
308 #endif
309 \f
310 /* Run-time Target Specification. */
311 #ifndef TARGET_VERSION
312 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
313 #endif
314
315 /* Nonzero if the function prologue (and epilogue) should obey
316 the ARM Procedure Call Standard. */
317 #define ARM_FLAG_APCS_FRAME (1 << 0)
318
319 /* Nonzero if the function prologue should output the function name to enable
320 the post mortem debugger to print a backtrace (very useful on RISCOS,
321 unused on RISCiX). Specifying this flag also enables
322 -fno-omit-frame-pointer.
323 XXX Must still be implemented in the prologue. */
324 #define ARM_FLAG_POKE (1 << 1)
325
326 /* Nonzero if floating point instructions are emulated by the FPE, in which
327 case instruction scheduling becomes very uninteresting. */
328 #define ARM_FLAG_FPE (1 << 2)
329
330 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
331 that assume restoration of the condition flags when returning from a
332 branch and link (ie a function). */
333 #define ARM_FLAG_APCS_32 (1 << 3)
334
335 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
336
337 /* Nonzero if stack checking should be performed on entry to each function
338 which allocates temporary variables on the stack. */
339 #define ARM_FLAG_APCS_STACK (1 << 4)
340
341 /* Nonzero if floating point parameters should be passed to functions in
342 floating point registers. */
343 #define ARM_FLAG_APCS_FLOAT (1 << 5)
344
345 /* Nonzero if re-entrant, position independent code should be generated.
346 This is equivalent to -fpic. */
347 #define ARM_FLAG_APCS_REENT (1 << 6)
348
349 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
350 be loaded using either LDRH or LDRB instructions. */
351 #define ARM_FLAG_MMU_TRAPS (1 << 7)
352
353 /* Nonzero if all floating point instructions are missing (and there is no
354 emulator either). Generate function calls for all ops in this case. */
355 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
356
357 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
358 #define ARM_FLAG_BIG_END (1 << 9)
359
360 /* Nonzero if we should compile for Thumb interworking. */
361 #define ARM_FLAG_INTERWORK (1 << 10)
362
363 /* Nonzero if we should have little-endian words even when compiling for
364 big-endian (for backwards compatibility with older versions of GCC). */
365 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
366
367 /* Nonzero if we need to protect the prolog from scheduling */
368 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
369
370 /* Nonzero if a call to abort should be generated if a noreturn
371 function tries to return. */
372 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
373
374 /* Nonzero if function prologues should not load the PIC register. */
375 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
376
377 /* Nonzero if all call instructions should be indirect. */
378 #define ARM_FLAG_LONG_CALLS (1 << 15)
379
380 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
381 #define ARM_FLAG_THUMB (1 << 16)
382
383 /* Set if a TPCS style stack frame should be generated, for non-leaf
384 functions, even if they do not need one. */
385 #define THUMB_FLAG_BACKTRACE (1 << 17)
386
387 /* Set if a TPCS style stack frame should be generated, for leaf
388 functions, even if they do not need one. */
389 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
390
391 /* Set if externally visible functions should assume that they
392 might be called in ARM mode, from a non-thumb aware code. */
393 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
394
395 /* Set if calls via function pointers should assume that their
396 destination is non-Thumb aware. */
397 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
398
399 /* Nonzero means target uses VFP FP. */
400 #define ARM_FLAG_VFP (1 << 21)
401
402 /* Nonzero means to use ARM/Thumb Procedure Call Standard conventions. */
403 #define ARM_FLAG_ATPCS (1 << 22)
404
405 /* Fix invalid Cirrus instruction combinations by inserting NOPs. */
406 #define CIRRUS_FIX_INVALID_INSNS (1 << 23)
407
408 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
409 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
410 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
411 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
412 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
413 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
414 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
415 #define TARGET_ATPCS (target_flags & ARM_FLAG_ATPCS)
416 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
417 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
418 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
419 #define TARGET_CIRRUS (arm_is_cirrus)
420 #define TARGET_ANY_HARD_FLOAT (TARGET_HARD_FLOAT || TARGET_CIRRUS)
421 #define TARGET_IWMMXT (arm_arch_iwmmxt)
422 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
423 #define TARGET_VFP (target_flags & ARM_FLAG_VFP)
424 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
425 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
426 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
427 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
428 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
429 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
430 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
431 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
432 #define TARGET_ARM (! TARGET_THUMB)
433 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
434 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
435 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
436 #define TARGET_BACKTRACE (leaf_function_p () \
437 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
438 : (target_flags & THUMB_FLAG_BACKTRACE))
439 #define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS)
440
441 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
442 #ifndef SUBTARGET_SWITCHES
443 #define SUBTARGET_SWITCHES
444 #endif
445
446 #define TARGET_SWITCHES \
447 { \
448 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
449 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
450 N_("Generate APCS conformant stack frames") }, \
451 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
452 {"poke-function-name", ARM_FLAG_POKE, \
453 N_("Store function names in object code") }, \
454 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
455 {"fpe", ARM_FLAG_FPE, "" }, \
456 {"apcs-32", ARM_FLAG_APCS_32, \
457 N_("Use the 32-bit version of the APCS") }, \
458 {"apcs-26", -ARM_FLAG_APCS_32, \
459 N_("Use the 26-bit version of the APCS") }, \
460 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
461 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
462 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
463 N_("Pass FP arguments in FP registers") }, \
464 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
465 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
466 N_("Generate re-entrant, PIC code") }, \
467 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
468 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
469 N_("The MMU will trap on unaligned accesses") }, \
470 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
471 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
472 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
473 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
474 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
475 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
476 N_("Use library calls to perform FP operations") }, \
477 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
478 N_("Use hardware floating point instructions") }, \
479 {"big-endian", ARM_FLAG_BIG_END, \
480 N_("Assume target CPU is configured as big endian") }, \
481 {"little-endian", -ARM_FLAG_BIG_END, \
482 N_("Assume target CPU is configured as little endian") }, \
483 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
484 N_("Assume big endian bytes, little endian words") }, \
485 {"thumb-interwork", ARM_FLAG_INTERWORK, \
486 N_("Support calls between Thumb and ARM instruction sets") }, \
487 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
488 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
489 N_("Generate a call to abort if a noreturn function returns")}, \
490 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
491 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
492 N_("Do not move instructions into a function's prologue") }, \
493 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
494 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
495 N_("Do not load the PIC register in function prologues") }, \
496 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
497 {"long-calls", ARM_FLAG_LONG_CALLS, \
498 N_("Generate call insns as indirect calls, if necessary") }, \
499 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
500 {"thumb", ARM_FLAG_THUMB, \
501 N_("Compile for the Thumb not the ARM") }, \
502 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
503 {"arm", -ARM_FLAG_THUMB, "" }, \
504 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
505 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
506 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
507 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
508 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
509 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
510 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
511 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
512 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
513 "" }, \
514 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
515 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
516 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
517 "" }, \
518 {"cirrus-fix-invalid-insns", CIRRUS_FIX_INVALID_INSNS, \
519 N_("Cirrus: Place NOPs to avoid invalid instruction combinations") }, \
520 {"no-cirrus-fix-invalid-insns", -CIRRUS_FIX_INVALID_INSNS, \
521 N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\
522 SUBTARGET_SWITCHES \
523 {"", TARGET_DEFAULT, "" } \
524 }
525
526 #define TARGET_OPTIONS \
527 { \
528 {"cpu=", & arm_select[0].string, \
529 N_("Specify the name of the target CPU"), 0}, \
530 {"arch=", & arm_select[1].string, \
531 N_("Specify the name of the target architecture"), 0}, \
532 {"tune=", & arm_select[2].string, "", 0}, \
533 {"fpe=", & target_fp_name, "" , 0}, \
534 {"fp=", & target_fp_name, \
535 N_("Specify the version of the floating point emulator"), 0},\
536 {"structure-size-boundary=", & structure_size_string, \
537 N_("Specify the minimum bit alignment of structures"), 0}, \
538 {"pic-register=", & arm_pic_register_string, \
539 N_("Specify the register to be used for PIC addressing"), 0} \
540 }
541
542 /* Support for a compile-time default CPU, et cetera. The rules are:
543 --with-arch is ignored if -march or -mcpu are specified.
544 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
545 by --with-arch.
546 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
547 by -march).
548 --with-float is ignored if -mhard-float or -msoft-float are
549 specified. */
550 #define OPTION_DEFAULT_SPECS \
551 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
552 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
553 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
554 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
555
556 struct arm_cpu_select
557 {
558 const char * string;
559 const char * name;
560 const struct processors * processors;
561 };
562
563 /* This is a magic array. If the user specifies a command line switch
564 which matches one of the entries in TARGET_OPTIONS then the corresponding
565 string pointer will be set to the value specified by the user. */
566 extern struct arm_cpu_select arm_select[];
567
568 enum prog_mode_type
569 {
570 prog_mode26,
571 prog_mode32
572 };
573
574 /* Recast the program mode class to be the prog_mode attribute. */
575 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
576
577 extern enum prog_mode_type arm_prgmode;
578
579 /* What sort of floating point unit do we have? Hardware or software.
580 If software, is it issue 2 or issue 3? */
581 enum fputype
582 {
583 /* Software floating point, FPA style double fmt. */
584 FPUTYPE_SOFT_FPA,
585 /* Full FPA support. */
586 FPUTYPE_FPA,
587 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
588 FPUTYPE_FPA_EMU2,
589 /* Emulated FPA hardware, Issue 3 emulator. */
590 FPUTYPE_FPA_EMU3,
591 /* Cirrus Maverick floating point co-processor. */
592 FPUTYPE_MAVERICK
593 };
594
595 /* Recast the floating point class to be the floating point attribute. */
596 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
597
598 /* What type of floating point to tune for */
599 extern enum fputype arm_fpu_tune;
600
601 /* What type of floating point instructions are available */
602 extern enum fputype arm_fpu_arch;
603
604 /* Default floating point architecture. Override in sub-target if
605 necessary. */
606 #ifndef FPUTYPE_DEFAULT
607 #define FPUTYPE_DEFAULT FPUTYPE_FPA_EMU2
608 #endif
609
610 #if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312
611 #undef FPUTYPE_DEFAULT
612 #define FPUTYPE_DEFAULT FPUTYPE_MAVERICK
613 #endif
614
615 /* Nonzero if the processor has a fast multiply insn, and one that does
616 a 64-bit multiply of two 32-bit values. */
617 extern int arm_fast_multiply;
618
619 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
620 extern int arm_arch4;
621
622 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
623 extern int arm_arch5;
624
625 /* Nonzero if this chip supports the ARM Architecture 5E extensions */
626 extern int arm_arch5e;
627
628 /* Nonzero if this chip can benefit from load scheduling. */
629 extern int arm_ld_sched;
630
631 /* Nonzero if generating thumb code. */
632 extern int thumb_code;
633
634 /* Nonzero if this chip is a StrongARM. */
635 extern int arm_is_strong;
636
637 /* Nonzero if this chip is a Cirrus variant. */
638 extern int arm_is_cirrus;
639
640 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
641 extern int arm_arch_iwmmxt;
642
643 /* Nonzero if this chip is an XScale. */
644 extern int arm_arch_xscale;
645
646 /* Nonzero if tuning for XScale */
647 extern int arm_tune_xscale;
648
649 /* Nonzero if this chip is an ARM6 or an ARM7. */
650 extern int arm_is_6_or_7;
651
652 #ifndef TARGET_DEFAULT
653 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
654 #endif
655
656 /* The frame pointer register used in gcc has nothing to do with debugging;
657 that is controlled by the APCS-FRAME option. */
658 #define CAN_DEBUG_WITHOUT_FP
659
660 #undef TARGET_MEM_FUNCTIONS
661 #define TARGET_MEM_FUNCTIONS 1
662
663 #define OVERRIDE_OPTIONS arm_override_options ()
664
665 /* Nonzero if PIC code requires explicit qualifiers to generate
666 PLT and GOT relocs rather than the assembler doing so implicitly.
667 Subtargets can override these if required. */
668 #ifndef NEED_GOT_RELOC
669 #define NEED_GOT_RELOC 0
670 #endif
671 #ifndef NEED_PLT_RELOC
672 #define NEED_PLT_RELOC 0
673 #endif
674
675 /* Nonzero if we need to refer to the GOT with a PC-relative
676 offset. In other words, generate
677
678 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
679
680 rather than
681
682 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
683
684 The default is true, which matches NetBSD. Subtargets can
685 override this if required. */
686 #ifndef GOT_PCREL
687 #define GOT_PCREL 1
688 #endif
689 \f
690 /* Target machine storage Layout. */
691
692
693 /* Define this macro if it is advisable to hold scalars in registers
694 in a wider mode than that declared by the program. In such cases,
695 the value is constrained to be within the bounds of the declared
696 type, but kept valid in the wider mode. The signedness of the
697 extension may differ from that of the type. */
698
699 /* It is far faster to zero extend chars than to sign extend them */
700
701 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
702 if (GET_MODE_CLASS (MODE) == MODE_INT \
703 && GET_MODE_SIZE (MODE) < 4) \
704 { \
705 if (MODE == QImode) \
706 UNSIGNEDP = 1; \
707 else if (MODE == HImode) \
708 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
709 (MODE) = SImode; \
710 }
711
712 /* Define this macro if the promotion described by `PROMOTE_MODE'
713 should also be done for outgoing function arguments. */
714 /* This is required to ensure that push insns always push a word. */
715 #define PROMOTE_FUNCTION_ARGS
716
717 /* Define this if most significant bit is lowest numbered
718 in instructions that operate on numbered bit-fields. */
719 #define BITS_BIG_ENDIAN 0
720
721 /* Define this if most significant byte of a word is the lowest numbered.
722 Most ARM processors are run in little endian mode, so that is the default.
723 If you want to have it run-time selectable, change the definition in a
724 cover file to be TARGET_BIG_ENDIAN. */
725 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
726
727 /* Define this if most significant word of a multiword number is the lowest
728 numbered.
729 This is always false, even when in big-endian mode. */
730 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
731
732 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
733 on processor pre-defineds when compiling libgcc2.c. */
734 #if defined(__ARMEB__) && !defined(__ARMWEL__)
735 #define LIBGCC2_WORDS_BIG_ENDIAN 1
736 #else
737 #define LIBGCC2_WORDS_BIG_ENDIAN 0
738 #endif
739
740 /* Define this if most significant word of doubles is the lowest numbered.
741 The rules are different based on whether or not we use FPA-format,
742 VFP-format or some other floating point co-processor's format doubles. */
743 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
744
745 #define UNITS_PER_WORD 4
746
747 #define PARM_BOUNDARY 32
748
749 #define IWMMXT_ALIGNMENT 64
750
751 #define STACK_BOUNDARY 32
752
753 #define PREFERRED_STACK_BOUNDARY (TARGET_ATPCS ? 64 : 32)
754
755 #define FUNCTION_BOUNDARY 32
756
757 /* The lowest bit is used to indicate Thumb-mode functions, so the
758 vbit must go into the delta field of pointers to member
759 functions. */
760 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
761
762 #define EMPTY_FIELD_BOUNDARY 32
763
764 #define BIGGEST_ALIGNMENT (TARGET_REALLY_IWMMXT ? 64 : 32)
765
766 #define TYPE_NEEDS_IWMMXT_ALIGNMENT(TYPE) \
767 (TARGET_REALLY_IWMMXT \
768 && ((TREE_CODE (TYPE) == VECTOR_TYPE) || (TYPE_MODE (TYPE) == DImode) || (TYPE_MODE (TYPE) == DFmode)))
769
770 /* XXX Blah -- this macro is used directly by libobjc. Since it
771 supports no vector modes, cut out the complexity and fall back
772 on BIGGEST_FIELD_ALIGNMENT. */
773 #ifdef IN_TARGET_LIBS
774 #define BIGGEST_FIELD_ALIGNMENT 64
775 #else
776 /* An expression for the alignment of a structure field FIELD if the
777 alignment computed in the usual way is COMPUTED. GCC uses this
778 value instead of the value in `BIGGEST_ALIGNMENT' or
779 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
780 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
781 (TYPE_NEEDS_IWMMXT_ALIGNMENT (TREE_TYPE (FIELD)) \
782 ? IWMMXT_ALIGNMENT \
783 : (COMPUTED))
784 #endif
785
786 /* If defined, a C expression to compute the alignment for a static variable.
787 TYPE is the data type, and ALIGN is the alignment that the object
788 would ordinarily have. The value of this macro is used instead of that
789 alignment to align the object.
790
791 If this macro is not defined, then ALIGN is used. */
792 #define DATA_ALIGNMENT(TYPE, ALIGN) \
793 (TYPE_NEEDS_IWMMXT_ALIGNMENT (TYPE) ? IWMMXT_ALIGNMENT : ALIGN)
794
795 /* If defined, a C expression to compute the alignment for a
796 variables in the local store. TYPE is the data type, and
797 BASIC-ALIGN is the alignment that the object would ordinarily
798 have. The value of this macro is used instead of that alignment
799 to align the object.
800
801 If this macro is not defined, then BASIC-ALIGN is used. */
802 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
803 (TYPE_NEEDS_IWMMXT_ALIGNMENT (TYPE) ? IWMMXT_ALIGNMENT : ALIGN)
804
805 /* Make strings word-aligned so strcpy from constants will be faster. */
806 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
807
808 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
809 ((TARGET_REALLY_IWMMXT && TREE_CODE (EXP) == VECTOR_TYPE) ? IWMMXT_ALIGNMENT : \
810 (TREE_CODE (EXP) == STRING_CST \
811 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
812 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
813
814 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
815 value set in previous versions of this toolchain was 8, which produces more
816 compact structures. The command line option -mstructure_size_boundary=<n>
817 can be used to change this value. For compatibility with the ARM SDK
818 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
819 0020D) page 2-20 says "Structures are aligned on word boundaries". */
820 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
821 extern int arm_structure_size_boundary;
822
823 /* This is the value used to initialize arm_structure_size_boundary. If a
824 particular arm target wants to change the default value it should change
825 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
826 for an example of this. */
827 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
828 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
829 #endif
830
831 /* Used when parsing command line option -mstructure_size_boundary. */
832 extern const char * structure_size_string;
833
834 /* Nonzero if move instructions will actually fail to work
835 when given unaligned data. */
836 #define STRICT_ALIGNMENT 1
837 \f
838 /* Standard register usage. */
839
840 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
841 (S - saved over call).
842
843 r0 * argument word/integer result
844 r1-r3 argument word
845
846 r4-r8 S register variable
847 r9 S (rfp) register variable (real frame pointer)
848
849 r10 F S (sl) stack limit (used by -mapcs-stack-check)
850 r11 F S (fp) argument pointer
851 r12 (ip) temp workspace
852 r13 F S (sp) lower end of current stack frame
853 r14 (lr) link address/workspace
854 r15 F (pc) program counter
855
856 f0 floating point result
857 f1-f3 floating point scratch
858
859 f4-f7 S floating point variable
860
861 cc This is NOT a real register, but is used internally
862 to represent things that use or set the condition
863 codes.
864 sfp This isn't either. It is used during rtl generation
865 since the offset between the frame pointer and the
866 auto's isn't known until after register allocation.
867 afp Nor this, we only need this because of non-local
868 goto. Without it fp appears to be used and the
869 elimination code won't get rid of sfp. It tracks
870 fp exactly at all times.
871
872 *: See CONDITIONAL_REGISTER_USAGE */
873
874 /*
875 mvf0 Cirrus floating point result
876 mvf1-mvf3 Cirrus floating point scratch
877 mvf4-mvf15 S Cirrus floating point variable. */
878
879 /* The stack backtrace structure is as follows:
880 fp points to here: | save code pointer | [fp]
881 | return link value | [fp, #-4]
882 | return sp value | [fp, #-8]
883 | return fp value | [fp, #-12]
884 [| saved r10 value |]
885 [| saved r9 value |]
886 [| saved r8 value |]
887 [| saved r7 value |]
888 [| saved r6 value |]
889 [| saved r5 value |]
890 [| saved r4 value |]
891 [| saved r3 value |]
892 [| saved r2 value |]
893 [| saved r1 value |]
894 [| saved r0 value |]
895 [| saved f7 value |] three words
896 [| saved f6 value |] three words
897 [| saved f5 value |] three words
898 [| saved f4 value |] three words
899 r0-r3 are not normally saved in a C function. */
900
901 /* 1 for registers that have pervasive standard uses
902 and are not available for the register allocator. */
903 #define FIXED_REGISTERS \
904 { \
905 0,0,0,0,0,0,0,0, \
906 0,0,0,0,0,1,0,1, \
907 0,0,0,0,0,0,0,0, \
908 1,1,1, \
909 1,1,1,1,1,1,1,1, \
910 1,1,1,1,1,1,1,1, \
911 1,1,1,1,1,1,1,1, \
912 1,1,1,1,1,1,1,1, \
913 1,1,1,1 \
914 }
915
916 /* 1 for registers not available across function calls.
917 These must include the FIXED_REGISTERS and also any
918 registers that can be used without being saved.
919 The latter must include the registers where values are returned
920 and the register where structure-value addresses are passed.
921 Aside from that, you can include as many other registers as you like.
922 The CC is not preserved over function calls on the ARM 6, so it is
923 easier to assume this for all. SFP is preserved, since FP is. */
924 #define CALL_USED_REGISTERS \
925 { \
926 1,1,1,1,0,0,0,0, \
927 0,0,0,0,1,1,1,1, \
928 1,1,1,1,0,0,0,0, \
929 1,1,1, \
930 1,1,1,1,1,1,1,1, \
931 1,1,1,1,1,1,1,1, \
932 1,1,1,1,1,1,1,1, \
933 1,1,1,1,1,1,1,1, \
934 1,1,1,1 \
935 }
936
937 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
938 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
939 #endif
940
941 #define CONDITIONAL_REGISTER_USAGE \
942 { \
943 int regno; \
944 \
945 if (TARGET_SOFT_FLOAT || TARGET_THUMB) \
946 { \
947 for (regno = FIRST_ARM_FP_REGNUM; \
948 regno <= LAST_ARM_FP_REGNUM; ++regno) \
949 fixed_regs[regno] = call_used_regs[regno] = 1; \
950 } \
951 \
952 if (TARGET_THUMB && optimize_size) \
953 { \
954 /* When optimizing for size, it's better not to use \
955 the HI regs, because of the overhead of stacking \
956 them. */ \
957 for (regno = FIRST_HI_REGNUM; \
958 regno <= LAST_HI_REGNUM; ++regno) \
959 fixed_regs[regno] = call_used_regs[regno] = 1; \
960 } \
961 \
962 /* The link register can be clobbered by any branch insn, \
963 but we have no way to track that at present, so mark \
964 it as unavailable. */ \
965 if (TARGET_THUMB) \
966 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
967 \
968 if (TARGET_CIRRUS) \
969 { \
970 for (regno = FIRST_ARM_FP_REGNUM; \
971 regno <= LAST_ARM_FP_REGNUM; ++ regno) \
972 fixed_regs[regno] = call_used_regs[regno] = 1; \
973 for (regno = FIRST_CIRRUS_FP_REGNUM; \
974 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
975 { \
976 fixed_regs[regno] = 0; \
977 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
978 } \
979 } \
980 \
981 if (TARGET_REALLY_IWMMXT) \
982 { \
983 regno = FIRST_IWMMXT_GR_REGNUM; \
984 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
985 and wCG1 as call-preserved registers. The 2002/11/21 \
986 revision changed this so that all wCG registers are \
987 scratch registers. */ \
988 for (regno = FIRST_IWMMXT_GR_REGNUM; \
989 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
990 fixed_regs[regno] = call_used_regs[regno] = 0; \
991 /* The XScale ABI has wR0 - wR9 as scratch registers, \
992 the rest as call-preserved registers. */ \
993 for (regno = FIRST_IWMMXT_REGNUM; \
994 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
995 { \
996 fixed_regs[regno] = 0; \
997 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
998 } \
999 } \
1000 \
1001 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
1002 { \
1003 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1004 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1005 } \
1006 else if (TARGET_APCS_STACK) \
1007 { \
1008 fixed_regs[10] = 1; \
1009 call_used_regs[10] = 1; \
1010 } \
1011 if (TARGET_APCS_FRAME) \
1012 { \
1013 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
1014 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
1015 } \
1016 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
1017 }
1018
1019 /* These are a couple of extensions to the formats accepted
1020 by asm_fprintf:
1021 %@ prints out ASM_COMMENT_START
1022 %r prints out REGISTER_PREFIX reg_names[arg] */
1023 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
1024 case '@': \
1025 fputs (ASM_COMMENT_START, FILE); \
1026 break; \
1027 \
1028 case 'r': \
1029 fputs (REGISTER_PREFIX, FILE); \
1030 fputs (reg_names [va_arg (ARGS, int)], FILE); \
1031 break;
1032
1033 /* Round X up to the nearest word. */
1034 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
1035
1036 /* Convert fron bytes to ints. */
1037 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1038
1039 /* The number of (integer) registers required to hold a quantity of type MODE. */
1040 #define ARM_NUM_REGS(MODE) \
1041 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
1042
1043 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
1044 #define ARM_NUM_REGS2(MODE, TYPE) \
1045 ARM_NUM_INTS ((MODE) == BLKmode ? \
1046 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
1047
1048 /* The number of (integer) argument register available. */
1049 #define NUM_ARG_REGS 4
1050
1051 /* Return the register number of the N'th (integer) argument. */
1052 #define ARG_REGISTER(N) (N - 1)
1053
1054 #if 0 /* FIXME: The ARM backend has special code to handle structure
1055 returns, and will reserve its own hidden first argument. So
1056 if this macro is enabled a *second* hidden argument will be
1057 reserved, which will break binary compatibility with old
1058 toolchains and also thunk handling. One day this should be
1059 fixed. */
1060 /* RTX for structure returns. NULL means use a hidden first argument. */
1061 #define STRUCT_VALUE 0
1062 #else
1063 /* Register in which address to store a structure value
1064 is passed to a function. */
1065 #define STRUCT_VALUE_REGNUM ARG_REGISTER (1)
1066 #endif
1067
1068 /* Specify the registers used for certain standard purposes.
1069 The values of these macros are register numbers. */
1070
1071 /* The number of the last argument register. */
1072 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
1073
1074 /* The numbers of the Thumb register ranges. */
1075 #define FIRST_LO_REGNUM 0
1076 #define LAST_LO_REGNUM 7
1077 #define FIRST_HI_REGNUM 8
1078 #define LAST_HI_REGNUM 11
1079
1080 /* The register that holds the return address in exception handlers. */
1081 #define EXCEPTION_LR_REGNUM 2
1082
1083 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
1084 as an invisible last argument (possible since varargs don't exist in
1085 Pascal), so the following is not true. */
1086 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
1087
1088 /* Define this to be where the real frame pointer is if it is not possible to
1089 work out the offset between the frame pointer and the automatic variables
1090 until after register allocation has taken place. FRAME_POINTER_REGNUM
1091 should point to a special register that we will make sure is eliminated.
1092
1093 For the Thumb we have another problem. The TPCS defines the frame pointer
1094 as r11, and GCC believes that it is always possible to use the frame pointer
1095 as base register for addressing purposes. (See comments in
1096 find_reloads_address()). But - the Thumb does not allow high registers,
1097 including r11, to be used as base address registers. Hence our problem.
1098
1099 The solution used here, and in the old thumb port is to use r7 instead of
1100 r11 as the hard frame pointer and to have special code to generate
1101 backtrace structures on the stack (if required to do so via a command line
1102 option) using r11. This is the only 'user visible' use of r11 as a frame
1103 pointer. */
1104 #define ARM_HARD_FRAME_POINTER_REGNUM 11
1105 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
1106
1107 #define HARD_FRAME_POINTER_REGNUM \
1108 (TARGET_ARM \
1109 ? ARM_HARD_FRAME_POINTER_REGNUM \
1110 : THUMB_HARD_FRAME_POINTER_REGNUM)
1111
1112 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
1113
1114 /* Register to use for pushing function arguments. */
1115 #define STACK_POINTER_REGNUM SP_REGNUM
1116
1117 /* ARM floating pointer registers. */
1118 #define FIRST_ARM_FP_REGNUM 16
1119 #define LAST_ARM_FP_REGNUM 23
1120
1121 #define FIRST_IWMMXT_GR_REGNUM 43
1122 #define LAST_IWMMXT_GR_REGNUM 46
1123 #define FIRST_IWMMXT_REGNUM 47
1124 #define LAST_IWMMXT_REGNUM 62
1125 #define IS_IWMMXT_REGNUM(REGNUM) \
1126 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1127 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1128 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1129
1130 /* Base register for access to local variables of the function. */
1131 #define FRAME_POINTER_REGNUM 25
1132
1133 /* Base register for access to arguments of the function. */
1134 #define ARG_POINTER_REGNUM 26
1135
1136 #define FIRST_CIRRUS_FP_REGNUM 27
1137 #define LAST_CIRRUS_FP_REGNUM 42
1138 #define IS_CIRRUS_REGNUM(REGNUM) \
1139 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1140
1141 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1142 /* + 16 Cirrus registers take us up to 43. */
1143 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1144 #define FIRST_PSEUDO_REGISTER 63
1145
1146 /* Value should be nonzero if functions must have frame pointers.
1147 Zero means the frame pointer need not be set up (and parms may be accessed
1148 via the stack pointer) in functions that seem suitable.
1149 If we have to have a frame pointer we might as well make use of it.
1150 APCS says that the frame pointer does not need to be pushed in leaf
1151 functions, or simple tail call functions. */
1152 #define FRAME_POINTER_REQUIRED \
1153 (current_function_has_nonlocal_label \
1154 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1155
1156 /* Return number of consecutive hard regs needed starting at reg REGNO
1157 to hold something of mode MODE.
1158 This is ordinarily the length in words of a value of mode MODE
1159 but can be less for certain modes in special long registers.
1160
1161 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1162 mode. */
1163 #define HARD_REGNO_NREGS(REGNO, MODE) \
1164 ((TARGET_ARM \
1165 && REGNO >= FIRST_ARM_FP_REGNUM \
1166 && REGNO != FRAME_POINTER_REGNUM \
1167 && REGNO != ARG_POINTER_REGNUM) \
1168 ? 1 : ARM_NUM_REGS (MODE))
1169
1170 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1171 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1172 arm_hard_regno_mode_ok ((REGNO), (MODE))
1173
1174 /* Value is 1 if it is a good idea to tie two pseudo registers
1175 when one has mode MODE1 and one has mode MODE2.
1176 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1177 for any hard reg, then this must be 0 for correct output. */
1178 #define MODES_TIEABLE_P(MODE1, MODE2) \
1179 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1180
1181 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1182 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode)
1183
1184 #define VALID_IWMMXT_REG_MODE(MODE) \
1185 (VECTOR_MODE_SUPPORTED_P (MODE) || (MODE) == DImode)
1186
1187 /* The order in which register should be allocated. It is good to use ip
1188 since no saving is required (though calls clobber it) and it never contains
1189 function parameters. It is quite good to use lr since other calls may
1190 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1191 least likely to contain a function parameter; in addition results are
1192 returned in r0. */
1193 #define REG_ALLOC_ORDER \
1194 { \
1195 3, 2, 1, 0, 12, 14, 4, 5, \
1196 6, 7, 8, 10, 9, 11, 13, 15, \
1197 16, 17, 18, 19, 20, 21, 22, 23, \
1198 27, 28, 29, 30, 31, 32, 33, 34, \
1199 35, 36, 37, 38, 39, 40, 41, 42, \
1200 43, 44, 45, 46, 47, 48, 49, 50, \
1201 51, 52, 53, 54, 55, 56, 57, 58, \
1202 59, 60, 61, 62, \
1203 24, 25, 26 \
1204 }
1205
1206 /* Interrupt functions can only use registers that have already been
1207 saved by the prologue, even if they would normally be
1208 call-clobbered. */
1209 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1210 (! IS_INTERRUPT (cfun->machine->func_type) || \
1211 regs_ever_live[DST])
1212 \f
1213 /* Register and constant classes. */
1214
1215 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1216 Now that the Thumb is involved it has become more complicated. */
1217 enum reg_class
1218 {
1219 NO_REGS,
1220 FPA_REGS,
1221 CIRRUS_REGS,
1222 IWMMXT_GR_REGS,
1223 IWMMXT_REGS,
1224 LO_REGS,
1225 STACK_REG,
1226 BASE_REGS,
1227 HI_REGS,
1228 CC_REG,
1229 GENERAL_REGS,
1230 ALL_REGS,
1231 LIM_REG_CLASSES
1232 };
1233
1234 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1235
1236 /* Give names of register classes as strings for dump file. */
1237 #define REG_CLASS_NAMES \
1238 { \
1239 "NO_REGS", \
1240 "FPA_REGS", \
1241 "CIRRUS_REGS", \
1242 "IWMMXT_GR_REGS", \
1243 "IWMMXT_REGS", \
1244 "LO_REGS", \
1245 "STACK_REG", \
1246 "BASE_REGS", \
1247 "HI_REGS", \
1248 "CC_REG", \
1249 "GENERAL_REGS", \
1250 "ALL_REGS", \
1251 }
1252
1253 /* Define which registers fit in which classes.
1254 This is an initializer for a vector of HARD_REG_SET
1255 of length N_REG_CLASSES. */
1256 #define REG_CLASS_CONTENTS \
1257 { \
1258 { 0x00000000, 0x0 }, /* NO_REGS */ \
1259 { 0x00FF0000, 0x0 }, /* FPA_REGS */ \
1260 { 0xF8000000, 0x000007FF }, /* CIRRUS_REGS */ \
1261 { 0x00000000, 0x00007800 }, /* IWMMXT_GR_REGS */\
1262 { 0x00000000, 0x7FFF8000 }, /* IWMMXT_REGS */ \
1263 { 0x000000FF, 0x0 }, /* LO_REGS */ \
1264 { 0x00002000, 0x0 }, /* STACK_REG */ \
1265 { 0x000020FF, 0x0 }, /* BASE_REGS */ \
1266 { 0x0000FF00, 0x0 }, /* HI_REGS */ \
1267 { 0x01000000, 0x0 }, /* CC_REG */ \
1268 { 0x0200FFFF, 0x0 }, /* GENERAL_REGS */\
1269 { 0xFAFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1270 }
1271
1272 /* The same information, inverted:
1273 Return the class number of the smallest class containing
1274 reg number REGNO. This could be a conditional expression
1275 or could index an array. */
1276 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1277
1278 /* FPA registers can't do dubreg as all values are reformatted to internal
1279 precision. */
1280 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1281 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1282 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) : 0)
1283
1284 /* The class value for index registers, and the one for base regs. */
1285 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1286 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1287
1288 /* For the Thumb the high registers cannot be used as base registers
1289 when addressing quantities in QI or HI mode; if we don't know the
1290 mode, then we must be conservative. After reload we must also be
1291 conservative, since we can't support SP+reg addressing, and we
1292 can't fix up any bad substitutions. */
1293 #define MODE_BASE_REG_CLASS(MODE) \
1294 (TARGET_ARM ? GENERAL_REGS : \
1295 (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS))
1296
1297 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1298 registers explicitly used in the rtl to be used as spill registers
1299 but prevents the compiler from extending the lifetime of these
1300 registers. */
1301 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1302
1303 /* Get reg_class from a letter such as appears in the machine description.
1304 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
1305 ARM, but several more letters for the Thumb. */
1306 #define REG_CLASS_FROM_LETTER(C) \
1307 ( (C) == 'f' ? FPA_REGS \
1308 : (C) == 'v' ? CIRRUS_REGS \
1309 : (C) == 'y' ? IWMMXT_REGS \
1310 : (C) == 'z' ? IWMMXT_GR_REGS \
1311 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1312 : TARGET_ARM ? NO_REGS \
1313 : (C) == 'h' ? HI_REGS \
1314 : (C) == 'b' ? BASE_REGS \
1315 : (C) == 'k' ? STACK_REG \
1316 : (C) == 'c' ? CC_REG \
1317 : NO_REGS)
1318
1319 /* The letters I, J, K, L and M in a register constraint string
1320 can be used to stand for particular ranges of immediate operands.
1321 This macro defines what the ranges are.
1322 C is the letter, and VALUE is a constant value.
1323 Return 1 if VALUE is in the range specified by C.
1324 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1325 J: valid indexing constants.
1326 K: ~value ok in rhs argument of data operand.
1327 L: -value ok in rhs argument of data operand.
1328 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1329 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1330 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1331 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1332 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1333 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1334 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1335 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1336 : 0)
1337
1338 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1339 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1340 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1341 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1342 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1343 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1344 && ((VAL) & 3) == 0) : \
1345 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1346 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1347 : 0)
1348
1349 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1350 (TARGET_ARM ? \
1351 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1352
1353 /* Constant letter 'G' for the FPA immediate constants.
1354 'H' means the same constant negated. */
1355 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1356 ((C) == 'G' ? const_double_rtx_ok_for_fpa (X) : \
1357 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
1358
1359 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1360 (TARGET_ARM ? \
1361 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1362
1363 /* For the ARM, `Q' means that this is a memory operand that is just
1364 an offset from a register.
1365 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1366 address. This means that the symbol is in the text segment and can be
1367 accessed without using a load. */
1368
1369 #define EXTRA_CONSTRAINT_ARM(OP, C) \
1370 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \
1371 (C) == 'R' ? (GET_CODE (OP) == MEM \
1372 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1373 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1374 (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1375 (C) == 'T' ? cirrus_memory_offset (OP) : \
1376 0)
1377
1378 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1379 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1380 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1381
1382 #define EXTRA_CONSTRAINT(X, C) \
1383 (TARGET_ARM ? \
1384 EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C))
1385
1386 /* Given an rtx X being reloaded into a reg required to be
1387 in class CLASS, return the class of reg to actually use.
1388 In general this is just CLASS, but for the Thumb we prefer
1389 a LO_REGS class or a subset. */
1390 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1391 (TARGET_ARM ? (CLASS) : \
1392 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1393
1394 /* Must leave BASE_REGS reloads alone */
1395 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1396 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1397 ? ((true_regnum (X) == -1 ? LO_REGS \
1398 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1399 : NO_REGS)) \
1400 : NO_REGS)
1401
1402 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1403 ((CLASS) != LO_REGS \
1404 ? ((true_regnum (X) == -1 ? LO_REGS \
1405 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1406 : NO_REGS)) \
1407 : NO_REGS)
1408
1409 /* Return the register class of a scratch register needed to copy IN into
1410 or out of a register in CLASS in MODE. If it can be done directly,
1411 NO_REGS is returned. */
1412 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1413 (TARGET_ARM ? \
1414 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1415 ? GENERAL_REGS : NO_REGS) \
1416 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1417
1418 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1419 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1420 /* Cannot load constants into Cirrus registers. */ \
1421 ((TARGET_CIRRUS \
1422 && (CLASS) == CIRRUS_REGS \
1423 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1424 ? GENERAL_REGS : \
1425 (TARGET_ARM ? \
1426 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1427 && CONSTANT_P (X)) \
1428 ? GENERAL_REGS : \
1429 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1430 && (GET_CODE (X) == MEM \
1431 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1432 && true_regnum (X) == -1))) \
1433 ? GENERAL_REGS : NO_REGS) \
1434 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1435
1436 /* Try a machine-dependent way of reloading an illegitimate address
1437 operand. If we find one, push the reload and jump to WIN. This
1438 macro is used in only one place: `find_reloads_address' in reload.c.
1439
1440 For the ARM, we wish to handle large displacements off a base
1441 register by splitting the addend across a MOV and the mem insn.
1442 This can cut the number of reloads needed. */
1443 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1444 do \
1445 { \
1446 if (GET_CODE (X) == PLUS \
1447 && GET_CODE (XEXP (X, 0)) == REG \
1448 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1449 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1450 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1451 { \
1452 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1453 HOST_WIDE_INT low, high; \
1454 \
1455 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1456 low = ((val & 0xf) ^ 0x8) - 0x8; \
1457 else if (TARGET_CIRRUS) \
1458 /* Need to be careful, -256 is not a valid offset. */ \
1459 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1460 else if (MODE == SImode \
1461 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1462 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1463 /* Need to be careful, -4096 is not a valid offset. */ \
1464 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1465 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1466 /* Need to be careful, -256 is not a valid offset. */ \
1467 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1468 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1469 && TARGET_HARD_FLOAT) \
1470 /* Need to be careful, -1024 is not a valid offset. */ \
1471 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1472 else \
1473 break; \
1474 \
1475 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1476 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1477 - (unsigned HOST_WIDE_INT) 0x80000000); \
1478 /* Check for overflow or zero */ \
1479 if (low == 0 || high == 0 || (high + low != val)) \
1480 break; \
1481 \
1482 /* Reload the high part into a base reg; leave the low part \
1483 in the mem. */ \
1484 X = gen_rtx_PLUS (GET_MODE (X), \
1485 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1486 GEN_INT (high)), \
1487 GEN_INT (low)); \
1488 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1489 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1490 VOIDmode, 0, 0, OPNUM, TYPE); \
1491 goto WIN; \
1492 } \
1493 } \
1494 while (0)
1495
1496 /* XXX If an HImode FP+large_offset address is converted to an HImode
1497 SP+large_offset address, then reload won't know how to fix it. It sees
1498 only that SP isn't valid for HImode, and so reloads the SP into an index
1499 register, but the resulting address is still invalid because the offset
1500 is too big. We fix it here instead by reloading the entire address. */
1501 /* We could probably achieve better results by defining PROMOTE_MODE to help
1502 cope with the variances between the Thumb's signed and unsigned byte and
1503 halfword load instructions. */
1504 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1505 { \
1506 if (GET_CODE (X) == PLUS \
1507 && GET_MODE_SIZE (MODE) < 4 \
1508 && GET_CODE (XEXP (X, 0)) == REG \
1509 && XEXP (X, 0) == stack_pointer_rtx \
1510 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1511 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
1512 { \
1513 rtx orig_X = X; \
1514 X = copy_rtx (X); \
1515 push_reload (orig_X, NULL_RTX, &X, NULL, \
1516 MODE_BASE_REG_CLASS (MODE), \
1517 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1518 goto WIN; \
1519 } \
1520 }
1521
1522 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1523 if (TARGET_ARM) \
1524 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1525 else \
1526 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1527
1528 /* Return the maximum number of consecutive registers
1529 needed to represent mode MODE in a register of class CLASS.
1530 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1531 #define CLASS_MAX_NREGS(CLASS, MODE) \
1532 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1533
1534 /* If defined, gives a class of registers that cannot be used as the
1535 operand of a SUBREG that changes the mode of the object illegally. */
1536
1537 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1538 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1539 (TARGET_ARM ? \
1540 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1541 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1542 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1543 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1544 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1545 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1546 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1547 2) \
1548 : \
1549 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1550 \f
1551 /* Stack layout; function entry, exit and calling. */
1552
1553 /* Define this if pushing a word on the stack
1554 makes the stack pointer a smaller address. */
1555 #define STACK_GROWS_DOWNWARD 1
1556
1557 /* Define this if the nominal address of the stack frame
1558 is at the high-address end of the local variables;
1559 that is, each additional local variable allocated
1560 goes at a more negative offset in the frame. */
1561 #define FRAME_GROWS_DOWNWARD 1
1562
1563 /* Offset within stack frame to start allocating local variables at.
1564 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1565 first local allocated. Otherwise, it is the offset to the BEGINNING
1566 of the first local allocated. */
1567 #define STARTING_FRAME_OFFSET 0
1568
1569 /* If we generate an insn to push BYTES bytes,
1570 this says how many the stack pointer really advances by. */
1571 /* The push insns do not do this rounding implicitly.
1572 So don't define this. */
1573 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1574
1575 /* Define this if the maximum size of all the outgoing args is to be
1576 accumulated and pushed during the prologue. The amount can be
1577 found in the variable current_function_outgoing_args_size. */
1578 #define ACCUMULATE_OUTGOING_ARGS 1
1579
1580 /* Offset of first parameter from the argument pointer register value. */
1581 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1582
1583 /* Value is the number of byte of arguments automatically
1584 popped when returning from a subroutine call.
1585 FUNDECL is the declaration node of the function (as a tree),
1586 FUNTYPE is the data type of the function (as a tree),
1587 or for a library call it is an identifier node for the subroutine name.
1588 SIZE is the number of bytes of arguments passed on the stack.
1589
1590 On the ARM, the caller does not pop any of its arguments that were passed
1591 on the stack. */
1592 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1593
1594 /* Define how to find the value returned by a library function
1595 assuming the value has mode MODE. */
1596 #define LIBCALL_VALUE(MODE) \
1597 (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1598 ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \
1599 : TARGET_ARM && TARGET_CIRRUS && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1600 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1601 : TARGET_REALLY_IWMMXT && VECTOR_MODE_SUPPORTED_P (MODE) \
1602 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1603 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1604
1605 /* Define how to find the value returned by a function.
1606 VALTYPE is the data type of the value (as a tree).
1607 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1608 otherwise, FUNC is 0. */
1609 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1610 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1611
1612 /* 1 if N is a possible register number for a function value.
1613 On the ARM, only r0 and f0 can return results. */
1614 /* On a Cirrus chip, mvf0 can return results. */
1615 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1616 ((REGNO) == ARG_REGISTER (1) \
1617 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) && TARGET_CIRRUS) \
1618 || (TARGET_ARM && ((REGNO) == FIRST_IWMMXT_REGNUM) && TARGET_IWMMXT) \
1619 || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT))
1620
1621 /* How large values are returned */
1622 /* A C expression which can inhibit the returning of certain function values
1623 in registers, based on the type of value. */
1624 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1625
1626 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1627 values must be in memory. On the ARM, they need only do so if larger
1628 than a word, or if they contain elements offset from zero in the struct. */
1629 #define DEFAULT_PCC_STRUCT_RETURN 0
1630
1631 /* Flags for the call/call_value rtl operations set up by function_arg. */
1632 #define CALL_NORMAL 0x00000000 /* No special processing. */
1633 #define CALL_LONG 0x00000001 /* Always call indirect. */
1634 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1635
1636 /* These bits describe the different types of function supported
1637 by the ARM backend. They are exclusive. ie a function cannot be both a
1638 normal function and an interworked function, for example. Knowing the
1639 type of a function is important for determining its prologue and
1640 epilogue sequences.
1641 Note value 7 is currently unassigned. Also note that the interrupt
1642 function types all have bit 2 set, so that they can be tested for easily.
1643 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1644 machine_function structure is initialized (to zero) func_type will
1645 default to unknown. This will force the first use of arm_current_func_type
1646 to call arm_compute_func_type. */
1647 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1648 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1649 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1650 #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */
1651 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1652 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1653 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1654
1655 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1656
1657 /* In addition functions can have several type modifiers,
1658 outlined by these bit masks: */
1659 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1660 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1661 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1662 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1663
1664 /* Some macros to test these flags. */
1665 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1666 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1667 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1668 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1669 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1670
1671 /* A C structure for machine-specific, per-function data.
1672 This is added to the cfun structure. */
1673 typedef struct machine_function GTY(())
1674 {
1675 /* Additional stack adjustment in __builtin_eh_throw. */
1676 rtx eh_epilogue_sp_ofs;
1677 /* Records if LR has to be saved for far jumps. */
1678 int far_jump_used;
1679 /* Records if ARG_POINTER was ever live. */
1680 int arg_pointer_live;
1681 /* Records if the save of LR has been eliminated. */
1682 int lr_save_eliminated;
1683 /* The size of the stack frame. Only valid after reload. */
1684 int frame_size;
1685 /* Records the type of the current function. */
1686 unsigned long func_type;
1687 /* Record if the function has a variable argument list. */
1688 int uses_anonymous_args;
1689 /* Records if sibcalls are blocked because an argument
1690 register is needed to preserve stack alignment. */
1691 int sibcall_blocked;
1692 }
1693 machine_function;
1694
1695 /* A C type for declaring a variable that is used as the first argument of
1696 `FUNCTION_ARG' and other related values. For some target machines, the
1697 type `int' suffices and can hold the number of bytes of argument so far. */
1698 typedef struct
1699 {
1700 /* This is the number of registers of arguments scanned so far. */
1701 int nregs;
1702 /* This is the number of iWMMXt register arguments scanned so far. */
1703 int iwmmxt_nregs;
1704 int named_count;
1705 int nargs;
1706 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
1707 int call_cookie;
1708 } CUMULATIVE_ARGS;
1709
1710 /* Define where to put the arguments to a function.
1711 Value is zero to push the argument on the stack,
1712 or a hard register in which to store the argument.
1713
1714 MODE is the argument's machine mode.
1715 TYPE is the data type of the argument (as a tree).
1716 This is null for libcalls where that information may
1717 not be available.
1718 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1719 the preceding args and about the function being called.
1720 NAMED is nonzero if this argument is a named parameter
1721 (otherwise it is an extra parameter matching an ellipsis).
1722
1723 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1724 other arguments are passed on the stack. If (NAMED == 0) (which happens
1725 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1726 passed in the stack (function_prologue will indeed make it pass in the
1727 stack if necessary). */
1728 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1729 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1730
1731 /* For an arg passed partly in registers and partly in memory,
1732 this is the number of registers used.
1733 For args passed entirely in registers or entirely in memory, zero. */
1734 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1735 (VECTOR_MODE_SUPPORTED_P (MODE) ? 0 : \
1736 NUM_ARG_REGS > (CUM).nregs \
1737 && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE))) \
1738 ? NUM_ARG_REGS - (CUM).nregs : 0)
1739
1740 /* A C expression that indicates when an argument must be passed by
1741 reference. If nonzero for an argument, a copy of that argument is
1742 made in memory and a pointer to the argument is passed instead of
1743 the argument itself. The pointer is passed in whatever way is
1744 appropriate for passing a pointer to that type. */
1745 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1746 arm_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
1747
1748 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1749 for a call to a function whose data type is FNTYPE.
1750 For a library call, FNTYPE is 0.
1751 On the ARM, the offset starts at 0. */
1752 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL) \
1753 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1754
1755 /* Update the data in CUM to advance over an argument
1756 of mode MODE and data type TYPE.
1757 (TYPE is null for libcalls where that information may not be available.) */
1758 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1759 (CUM).nargs += 1; \
1760 if (VECTOR_MODE_SUPPORTED_P (MODE)) \
1761 if ((CUM).named_count <= (CUM).nargs) \
1762 (CUM).nregs += 2; \
1763 else \
1764 (CUM).iwmmxt_nregs += 1; \
1765 else \
1766 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1767
1768 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1769 argument with the specified mode and type. If it is not defined,
1770 `PARM_BOUNDARY' is used for all arguments. */
1771 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1772 (TARGET_REALLY_IWMMXT && (VALID_IWMMXT_REG_MODE (MODE) || ((MODE) == DFmode)) \
1773 ? IWMMXT_ALIGNMENT : PARM_BOUNDARY)
1774
1775 /* 1 if N is a possible register number for function argument passing.
1776 On the ARM, r0-r3 are used to pass args. */
1777 #define FUNCTION_ARG_REGNO_P(REGNO) \
1778 (IN_RANGE ((REGNO), 0, 3) \
1779 || (TARGET_REALLY_IWMMXT && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1780
1781 /* Implement `va_arg'. */
1782 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1783 arm_va_arg (valist, type)
1784
1785 \f
1786 /* Perform any actions needed for a function that is receiving a variable
1787 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1788 of the current parameter. PRETEND_SIZE is a variable that should be set to
1789 the amount of stack that must be pushed by the prolog to pretend that our
1790 caller pushed it.
1791
1792 Normally, this macro will push all remaining incoming registers on the
1793 stack and set PRETEND_SIZE to the length of the registers pushed.
1794
1795 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1796 named arg and all anonymous args onto the stack.
1797 XXX I know the prologue shouldn't be pushing registers, but it is faster
1798 that way. */
1799 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1800 { \
1801 cfun->machine->uses_anonymous_args = 1; \
1802 if ((CUM).nregs < NUM_ARG_REGS) \
1803 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \
1804 }
1805
1806 /* If your target environment doesn't prefix user functions with an
1807 underscore, you may wish to re-define this to prevent any conflicts.
1808 e.g. AOF may prefix mcount with an underscore. */
1809 #ifndef ARM_MCOUNT_NAME
1810 #define ARM_MCOUNT_NAME "*mcount"
1811 #endif
1812
1813 /* Call the function profiler with a given profile label. The Acorn
1814 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1815 On the ARM the full profile code will look like:
1816 .data
1817 LP1
1818 .word 0
1819 .text
1820 mov ip, lr
1821 bl mcount
1822 .word LP1
1823
1824 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1825 will output the .text section.
1826
1827 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1828 ``prof'' doesn't seem to mind about this!
1829
1830 Note - this version of the code is designed to work in both ARM and
1831 Thumb modes. */
1832 #ifndef ARM_FUNCTION_PROFILER
1833 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1834 { \
1835 char temp[20]; \
1836 rtx sym; \
1837 \
1838 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1839 IP_REGNUM, LR_REGNUM); \
1840 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1841 fputc ('\n', STREAM); \
1842 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1843 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1844 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1845 }
1846 #endif
1847
1848 #ifdef THUMB_FUNCTION_PROFILER
1849 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1850 if (TARGET_ARM) \
1851 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1852 else \
1853 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1854 #else
1855 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1856 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1857 #endif
1858
1859 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1860 the stack pointer does not matter. The value is tested only in
1861 functions that have frame pointers.
1862 No definition is equivalent to always zero.
1863
1864 On the ARM, the function epilogue recovers the stack pointer from the
1865 frame. */
1866 #define EXIT_IGNORE_STACK 1
1867
1868 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1869
1870 /* Determine if the epilogue should be output as RTL.
1871 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1872 #define USE_RETURN_INSN(ISCOND) \
1873 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1874
1875 /* Definitions for register eliminations.
1876
1877 This is an array of structures. Each structure initializes one pair
1878 of eliminable registers. The "from" register number is given first,
1879 followed by "to". Eliminations of the same "from" register are listed
1880 in order of preference.
1881
1882 We have two registers that can be eliminated on the ARM. First, the
1883 arg pointer register can often be eliminated in favor of the stack
1884 pointer register. Secondly, the pseudo frame pointer register can always
1885 be eliminated; it is replaced with either the stack or the real frame
1886 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1887 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1888
1889 #define ELIMINABLE_REGS \
1890 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1891 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1892 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1893 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1894 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1895 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1896 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1897
1898 /* Given FROM and TO register numbers, say whether this elimination is
1899 allowed. Frame pointer elimination is automatically handled.
1900
1901 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1902 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1903 pointer, we must eliminate FRAME_POINTER_REGNUM into
1904 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1905 ARG_POINTER_REGNUM. */
1906 #define CAN_ELIMINATE(FROM, TO) \
1907 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1908 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1909 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1910 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1911 1)
1912
1913 #define THUMB_REG_PUSHED_P(reg) \
1914 (regs_ever_live [reg] \
1915 && (! call_used_regs [reg] \
1916 || (flag_pic && (reg) == PIC_OFFSET_TABLE_REGNUM)) \
1917 && !(TARGET_SINGLE_PIC_BASE && ((reg) == arm_pic_register)))
1918
1919 /* Define the offset between two registers, one to be eliminated, and the
1920 other its replacement, at the start of a routine. */
1921 #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1922 do \
1923 { \
1924 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1925 } \
1926 while (0)
1927
1928 /* Note: This macro must match the code in thumb_function_prologue(). */
1929 #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1930 { \
1931 (OFFSET) = 0; \
1932 if ((FROM) == ARG_POINTER_REGNUM) \
1933 { \
1934 int count_regs = 0; \
1935 int regno; \
1936 for (regno = 8; regno < 13; regno ++) \
1937 if (THUMB_REG_PUSHED_P (regno)) \
1938 count_regs ++; \
1939 if (count_regs) \
1940 (OFFSET) += 4 * count_regs; \
1941 count_regs = 0; \
1942 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \
1943 if (THUMB_REG_PUSHED_P (regno)) \
1944 count_regs ++; \
1945 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\
1946 (OFFSET) += 4 * (count_regs + 1); \
1947 if (TARGET_BACKTRACE) \
1948 { \
1949 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
1950 (OFFSET) += 20; \
1951 else \
1952 (OFFSET) += 16; \
1953 } \
1954 } \
1955 if ((TO) == STACK_POINTER_REGNUM) \
1956 { \
1957 (OFFSET) += current_function_outgoing_args_size; \
1958 (OFFSET) += thumb_get_frame_size (); \
1959 } \
1960 }
1961
1962 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1963 if (TARGET_ARM) \
1964 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET); \
1965 else \
1966 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET)
1967
1968 /* Special case handling of the location of arguments passed on the stack. */
1969 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1970
1971 /* Initialize data used by insn expanders. This is called from insn_emit,
1972 once for every function before code is generated. */
1973 #define INIT_EXPANDERS arm_init_expanders ()
1974
1975 /* Output assembler code for a block containing the constant parts
1976 of a trampoline, leaving space for the variable parts.
1977
1978 On the ARM, (if r8 is the static chain regnum, and remembering that
1979 referencing pc adds an offset of 8) the trampoline looks like:
1980 ldr r8, [pc, #0]
1981 ldr pc, [pc]
1982 .word static chain value
1983 .word function's address
1984 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1985 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1986 { \
1987 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1988 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1989 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1990 PC_REGNUM, PC_REGNUM); \
1991 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1992 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1993 }
1994
1995 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1996 Why - because it is easier. This code will always be branched to via
1997 a BX instruction and since the compiler magically generates the address
1998 of the function the linker has no opportunity to ensure that the
1999 bottom bit is set. Thus the processor will be in ARM mode when it
2000 reaches this code. So we duplicate the ARM trampoline code and add
2001 a switch into Thumb mode as well. */
2002 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
2003 { \
2004 fprintf (FILE, "\t.code 32\n"); \
2005 fprintf (FILE, ".Ltrampoline_start:\n"); \
2006 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
2007 STATIC_CHAIN_REGNUM, PC_REGNUM); \
2008 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
2009 IP_REGNUM, PC_REGNUM); \
2010 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
2011 IP_REGNUM, IP_REGNUM); \
2012 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
2013 fprintf (FILE, "\t.word\t0\n"); \
2014 fprintf (FILE, "\t.word\t0\n"); \
2015 fprintf (FILE, "\t.code 16\n"); \
2016 }
2017
2018 #define TRAMPOLINE_TEMPLATE(FILE) \
2019 if (TARGET_ARM) \
2020 ARM_TRAMPOLINE_TEMPLATE (FILE) \
2021 else \
2022 THUMB_TRAMPOLINE_TEMPLATE (FILE)
2023
2024 /* Length in units of the trampoline for entering a nested function. */
2025 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
2026
2027 /* Alignment required for a trampoline in bits. */
2028 #define TRAMPOLINE_ALIGNMENT 32
2029
2030 /* Emit RTL insns to initialize the variable parts of a trampoline.
2031 FNADDR is an RTX for the address of the function's pure code.
2032 CXT is an RTX for the static chain value for the function. */
2033 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2034 { \
2035 emit_move_insn \
2036 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \
2037 emit_move_insn \
2038 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \
2039 }
2040
2041 \f
2042 /* Addressing modes, and classification of registers for them. */
2043 #define HAVE_POST_INCREMENT 1
2044 #define HAVE_PRE_INCREMENT TARGET_ARM
2045 #define HAVE_POST_DECREMENT TARGET_ARM
2046 #define HAVE_PRE_DECREMENT TARGET_ARM
2047 #define HAVE_PRE_MODIFY_DISP TARGET_ARM
2048 #define HAVE_POST_MODIFY_DISP TARGET_ARM
2049 #define HAVE_PRE_MODIFY_REG TARGET_ARM
2050 #define HAVE_POST_MODIFY_REG TARGET_ARM
2051
2052 /* Macros to check register numbers against specific register classes. */
2053
2054 /* These assume that REGNO is a hard or pseudo reg number.
2055 They give nonzero only if REGNO is a hard reg of the suitable class
2056 or a pseudo reg currently allocated to a suitable hard reg.
2057 Since they use reg_renumber, they are safe only once reg_renumber
2058 has been allocated, which happens in local-alloc.c. */
2059 #define TEST_REGNO(R, TEST, VALUE) \
2060 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
2061
2062 /* On the ARM, don't allow the pc to be used. */
2063 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
2064 (TEST_REGNO (REGNO, <, PC_REGNUM) \
2065 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
2066 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
2067
2068 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2069 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
2070 || (GET_MODE_SIZE (MODE) >= 4 \
2071 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
2072
2073 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2074 (TARGET_THUMB \
2075 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
2076 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
2077
2078 /* For ARM code, we don't care about the mode, but for Thumb, the index
2079 must be suitable for use in a QImode load. */
2080 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2081 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
2082
2083 /* Maximum number of registers that can appear in a valid memory address.
2084 Shifts in addresses can't be by a register. */
2085 #define MAX_REGS_PER_ADDRESS 2
2086
2087 /* Recognize any constant value that is a valid address. */
2088 /* XXX We can address any constant, eventually... */
2089
2090 #ifdef AOF_ASSEMBLER
2091
2092 #define CONSTANT_ADDRESS_P(X) \
2093 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
2094
2095 #else
2096
2097 #define CONSTANT_ADDRESS_P(X) \
2098 (GET_CODE (X) == SYMBOL_REF \
2099 && (CONSTANT_POOL_ADDRESS_P (X) \
2100 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
2101
2102 #endif /* AOF_ASSEMBLER */
2103
2104 /* Nonzero if the constant value X is a legitimate general operand.
2105 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2106
2107 On the ARM, allow any integer (invalid ones are removed later by insn
2108 patterns), nice doubles and symbol_refs which refer to the function's
2109 constant pool XXX.
2110
2111 When generating pic allow anything. */
2112 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
2113
2114 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
2115 ( GET_CODE (X) == CONST_INT \
2116 || GET_CODE (X) == CONST_DOUBLE \
2117 || CONSTANT_ADDRESS_P (X) \
2118 || flag_pic)
2119
2120 #define LEGITIMATE_CONSTANT_P(X) \
2121 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
2122
2123 /* Special characters prefixed to function names
2124 in order to encode attribute like information.
2125 Note, '@' and '*' have already been taken. */
2126 #define SHORT_CALL_FLAG_CHAR '^'
2127 #define LONG_CALL_FLAG_CHAR '#'
2128
2129 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
2130 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
2131
2132 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
2133 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
2134
2135 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
2136 #define SUBTARGET_NAME_ENCODING_LENGTHS
2137 #endif
2138
2139 /* This is a C fragment for the inside of a switch statement.
2140 Each case label should return the number of characters to
2141 be stripped from the start of a function's name, if that
2142 name starts with the indicated character. */
2143 #define ARM_NAME_ENCODING_LENGTHS \
2144 case SHORT_CALL_FLAG_CHAR: return 1; \
2145 case LONG_CALL_FLAG_CHAR: return 1; \
2146 case '*': return 1; \
2147 SUBTARGET_NAME_ENCODING_LENGTHS
2148
2149 /* This is how to output a reference to a user-level label named NAME.
2150 `assemble_name' uses this. */
2151 #undef ASM_OUTPUT_LABELREF
2152 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2153 arm_asm_output_labelref (FILE, NAME)
2154
2155 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
2156 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
2157
2158 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2159 and check its validity for a certain class.
2160 We have two alternate definitions for each of them.
2161 The usual definition accepts all pseudo regs; the other rejects
2162 them unless they have been allocated suitable hard regs.
2163 The symbol REG_OK_STRICT causes the latter definition to be used. */
2164 #ifndef REG_OK_STRICT
2165
2166 #define ARM_REG_OK_FOR_BASE_P(X) \
2167 (REGNO (X) <= LAST_ARM_REGNUM \
2168 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2169 || REGNO (X) == FRAME_POINTER_REGNUM \
2170 || REGNO (X) == ARG_POINTER_REGNUM)
2171
2172 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2173 (REGNO (X) <= LAST_LO_REGNUM \
2174 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2175 || (GET_MODE_SIZE (MODE) >= 4 \
2176 && (REGNO (X) == STACK_POINTER_REGNUM \
2177 || (X) == hard_frame_pointer_rtx \
2178 || (X) == arg_pointer_rtx)))
2179
2180 #define REG_STRICT_P 0
2181
2182 #else /* REG_OK_STRICT */
2183
2184 #define ARM_REG_OK_FOR_BASE_P(X) \
2185 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2186
2187 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2188 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2189
2190 #define REG_STRICT_P 1
2191
2192 #endif /* REG_OK_STRICT */
2193
2194 /* Now define some helpers in terms of the above. */
2195
2196 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2197 (TARGET_THUMB \
2198 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2199 : ARM_REG_OK_FOR_BASE_P (X))
2200
2201 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2202
2203 /* For Thumb, a valid index register is anything that can be used in
2204 a byte load instruction. */
2205 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2206
2207 /* Nonzero if X is a hard reg that can be used as an index
2208 or if it is a pseudo reg. On the Thumb, the stack pointer
2209 is not suitable. */
2210 #define REG_OK_FOR_INDEX_P(X) \
2211 (TARGET_THUMB \
2212 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2213 : ARM_REG_OK_FOR_INDEX_P (X))
2214
2215 \f
2216 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2217 that is a valid memory address for an instruction.
2218 The MODE argument is the machine mode for the MEM expression
2219 that wants to use this address. */
2220
2221 #define ARM_BASE_REGISTER_RTX_P(X) \
2222 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2223
2224 #define ARM_INDEX_REGISTER_RTX_P(X) \
2225 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2226
2227 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2228 { \
2229 if (arm_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2230 goto WIN; \
2231 }
2232
2233 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2234 { \
2235 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2236 goto WIN; \
2237 }
2238
2239 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2240 if (TARGET_ARM) \
2241 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2242 else /* if (TARGET_THUMB) */ \
2243 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2244
2245 \f
2246 /* Try machine-dependent ways of modifying an illegitimate address
2247 to be legitimate. If we find one, return the new, valid address. */
2248 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2249 do { \
2250 X = arm_legitimize_address (X, OLDX, MODE); \
2251 \
2252 if (memory_address_p (MODE, X)) \
2253 goto WIN; \
2254 } while (0)
2255
2256 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2257 do { \
2258 if (flag_pic) \
2259 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2260 } while (0)
2261
2262 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2263 do { \
2264 if (TARGET_ARM) \
2265 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2266 else \
2267 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2268 } while (0)
2269
2270 /* Go to LABEL if ADDR (a legitimate address expression)
2271 has an effect that depends on the machine mode it is used for. */
2272 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2273 { \
2274 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2275 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2276 goto LABEL; \
2277 }
2278
2279 /* Nothing helpful to do for the Thumb */
2280 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2281 if (TARGET_ARM) \
2282 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2283 \f
2284
2285 /* Specify the machine mode that this machine uses
2286 for the index in the tablejump instruction. */
2287 #define CASE_VECTOR_MODE Pmode
2288
2289 /* Define as C expression which evaluates to nonzero if the tablejump
2290 instruction expects the table to contain offsets from the address of the
2291 table.
2292 Do not define this if the table should contain absolute addresses. */
2293 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2294
2295 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2296 unsigned is probably best, but may break some code. */
2297 #ifndef DEFAULT_SIGNED_CHAR
2298 #define DEFAULT_SIGNED_CHAR 0
2299 #endif
2300
2301 /* Don't cse the address of the function being compiled. */
2302 #define NO_RECURSIVE_FUNCTION_CSE 1
2303
2304 /* Max number of bytes we can move from memory to memory
2305 in one reasonably fast instruction. */
2306 #define MOVE_MAX 4
2307
2308 #undef MOVE_RATIO
2309 #define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
2310
2311 /* Define if operations between registers always perform the operation
2312 on the full register even if a narrower mode is specified. */
2313 #define WORD_REGISTER_OPERATIONS
2314
2315 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2316 will either zero-extend or sign-extend. The value of this macro should
2317 be the code that says which one of the two operations is implicitly
2318 done, NIL if none. */
2319 #define LOAD_EXTEND_OP(MODE) \
2320 (TARGET_THUMB ? ZERO_EXTEND : \
2321 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2322 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2323
2324 /* Nonzero if access to memory by bytes is slow and undesirable. */
2325 #define SLOW_BYTE_ACCESS 0
2326
2327 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2328
2329 /* Immediate shift counts are truncated by the output routines (or was it
2330 the assembler?). Shift counts in a register are truncated by ARM. Note
2331 that the native compiler puts too large (> 32) immediate shift counts
2332 into a register and shifts by the register, letting the ARM decide what
2333 to do instead of doing that itself. */
2334 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2335 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2336 On the arm, Y in a register is used modulo 256 for the shift. Only for
2337 rotates is modulo 32 used. */
2338 /* #define SHIFT_COUNT_TRUNCATED 1 */
2339
2340 /* All integers have the same format so truncation is easy. */
2341 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2342
2343 /* Calling from registers is a massive pain. */
2344 #define NO_FUNCTION_CSE 1
2345
2346 /* Chars and shorts should be passed as ints. */
2347 #define PROMOTE_PROTOTYPES 1
2348
2349 /* The machine modes of pointers and functions */
2350 #define Pmode SImode
2351 #define FUNCTION_MODE Pmode
2352
2353 #define ARM_FRAME_RTX(X) \
2354 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2355 || (X) == arg_pointer_rtx)
2356
2357 /* Moves to and from memory are quite expensive */
2358 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2359 (TARGET_ARM ? 10 : \
2360 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2361 * (CLASS == LO_REGS ? 1 : 2)))
2362
2363 /* Try to generate sequences that don't involve branches, we can then use
2364 conditional instructions */
2365 #define BRANCH_COST \
2366 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2367 \f
2368 /* Position Independent Code. */
2369 /* We decide which register to use based on the compilation options and
2370 the assembler in use; this is more general than the APCS restriction of
2371 using sb (r9) all the time. */
2372 extern int arm_pic_register;
2373
2374 /* Used when parsing command line option -mpic-register=. */
2375 extern const char * arm_pic_register_string;
2376
2377 /* The register number of the register used to address a table of static
2378 data addresses in memory. */
2379 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2380
2381 #define FINALIZE_PIC arm_finalize_pic (1)
2382
2383 /* We can't directly access anything that contains a symbol,
2384 nor can we indirect via the constant pool. */
2385 #define LEGITIMATE_PIC_OPERAND_P(X) \
2386 (!(symbol_mentioned_p (X) \
2387 || label_mentioned_p (X) \
2388 || (GET_CODE (X) == SYMBOL_REF \
2389 && CONSTANT_POOL_ADDRESS_P (X) \
2390 && (symbol_mentioned_p (get_pool_constant (X)) \
2391 || label_mentioned_p (get_pool_constant (X))))))
2392
2393 /* We need to know when we are making a constant pool; this determines
2394 whether data needs to be in the GOT or can be referenced via a GOT
2395 offset. */
2396 extern int making_const_table;
2397 \f
2398 /* Handle pragmas for compatibility with Intel's compilers. */
2399 #define REGISTER_TARGET_PRAGMAS() do { \
2400 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2401 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2402 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2403 } while (0)
2404
2405 /* Condition code information. */
2406 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2407 return the mode to be used for the comparison. */
2408
2409 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2410
2411 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2412
2413 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2414 do \
2415 { \
2416 if (GET_CODE (OP1) == CONST_INT \
2417 && ! (const_ok_for_arm (INTVAL (OP1)) \
2418 || (const_ok_for_arm (- INTVAL (OP1))))) \
2419 { \
2420 rtx const_op = OP1; \
2421 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2422 OP1 = const_op; \
2423 } \
2424 } \
2425 while (0)
2426
2427 /* The arm5 clz instruction returns 32. */
2428 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2429 \f
2430 #undef ASM_APP_OFF
2431 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2432
2433 /* Output a push or a pop instruction (only used when profiling). */
2434 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2435 do \
2436 { \
2437 if (TARGET_ARM) \
2438 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2439 STACK_POINTER_REGNUM, REGNO); \
2440 else \
2441 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2442 } while (0)
2443
2444
2445 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2446 do \
2447 { \
2448 if (TARGET_ARM) \
2449 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2450 STACK_POINTER_REGNUM, REGNO); \
2451 else \
2452 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2453 } while (0)
2454
2455 /* This is how to output a label which precedes a jumptable. Since
2456 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2457 #undef ASM_OUTPUT_CASE_LABEL
2458 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2459 do \
2460 { \
2461 if (TARGET_THUMB) \
2462 ASM_OUTPUT_ALIGN (FILE, 2); \
2463 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2464 } \
2465 while (0)
2466
2467 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2468 do \
2469 { \
2470 if (TARGET_THUMB) \
2471 { \
2472 if (is_called_in_ARM_mode (DECL)) \
2473 fprintf (STREAM, "\t.code 32\n") ; \
2474 else \
2475 fprintf (STREAM, "\t.thumb_func\n") ; \
2476 } \
2477 if (TARGET_POKE_FUNCTION_NAME) \
2478 arm_poke_function_name (STREAM, (char *) NAME); \
2479 } \
2480 while (0)
2481
2482 /* For aliases of functions we use .thumb_set instead. */
2483 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2484 do \
2485 { \
2486 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2487 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2488 \
2489 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2490 { \
2491 fprintf (FILE, "\t.thumb_set "); \
2492 assemble_name (FILE, LABEL1); \
2493 fprintf (FILE, ","); \
2494 assemble_name (FILE, LABEL2); \
2495 fprintf (FILE, "\n"); \
2496 } \
2497 else \
2498 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2499 } \
2500 while (0)
2501
2502 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2503 /* To support -falign-* switches we need to use .p2align so
2504 that alignment directives in code sections will be padded
2505 with no-op instructions, rather than zeroes. */
2506 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2507 if ((LOG) != 0) \
2508 { \
2509 if ((MAX_SKIP) == 0) \
2510 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2511 else \
2512 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2513 (int) (LOG), (int) (MAX_SKIP)); \
2514 }
2515 #endif
2516 \f
2517 /* Only perform branch elimination (by making instructions conditional) if
2518 we're optimizing. Otherwise it's of no use anyway. */
2519 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2520 if (TARGET_ARM && optimize) \
2521 arm_final_prescan_insn (INSN); \
2522 else if (TARGET_THUMB) \
2523 thumb_final_prescan_insn (INSN)
2524
2525 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2526 (CODE == '@' || CODE == '|' \
2527 || (TARGET_ARM && (CODE == '?')) \
2528 || (TARGET_THUMB && (CODE == '_')))
2529
2530 /* Output an operand of an instruction. */
2531 #define PRINT_OPERAND(STREAM, X, CODE) \
2532 arm_print_operand (STREAM, X, CODE)
2533
2534 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2535 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2536 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2537 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2538 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2539 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2540 : 0))))
2541
2542 /* Output the address of an operand. */
2543 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2544 { \
2545 int is_minus = GET_CODE (X) == MINUS; \
2546 \
2547 if (GET_CODE (X) == REG) \
2548 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2549 else if (GET_CODE (X) == PLUS || is_minus) \
2550 { \
2551 rtx base = XEXP (X, 0); \
2552 rtx index = XEXP (X, 1); \
2553 HOST_WIDE_INT offset = 0; \
2554 if (GET_CODE (base) != REG) \
2555 { \
2556 /* Ensure that BASE is a register. */ \
2557 /* (one of them must be). */ \
2558 rtx temp = base; \
2559 base = index; \
2560 index = temp; \
2561 } \
2562 switch (GET_CODE (index)) \
2563 { \
2564 case CONST_INT: \
2565 offset = INTVAL (index); \
2566 if (is_minus) \
2567 offset = -offset; \
2568 asm_fprintf (STREAM, "[%r, #%wd]", \
2569 REGNO (base), offset); \
2570 break; \
2571 \
2572 case REG: \
2573 asm_fprintf (STREAM, "[%r, %s%r]", \
2574 REGNO (base), is_minus ? "-" : "", \
2575 REGNO (index)); \
2576 break; \
2577 \
2578 case MULT: \
2579 case ASHIFTRT: \
2580 case LSHIFTRT: \
2581 case ASHIFT: \
2582 case ROTATERT: \
2583 { \
2584 asm_fprintf (STREAM, "[%r, %s%r", \
2585 REGNO (base), is_minus ? "-" : "", \
2586 REGNO (XEXP (index, 0))); \
2587 arm_print_operand (STREAM, index, 'S'); \
2588 fputs ("]", STREAM); \
2589 break; \
2590 } \
2591 \
2592 default: \
2593 abort(); \
2594 } \
2595 } \
2596 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2597 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2598 { \
2599 extern enum machine_mode output_memory_reference_mode; \
2600 \
2601 if (GET_CODE (XEXP (X, 0)) != REG) \
2602 abort (); \
2603 \
2604 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2605 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2606 REGNO (XEXP (X, 0)), \
2607 GET_CODE (X) == PRE_DEC ? "-" : "", \
2608 GET_MODE_SIZE (output_memory_reference_mode)); \
2609 else \
2610 asm_fprintf (STREAM, "[%r], #%s%d", \
2611 REGNO (XEXP (X, 0)), \
2612 GET_CODE (X) == POST_DEC ? "-" : "", \
2613 GET_MODE_SIZE (output_memory_reference_mode)); \
2614 } \
2615 else if (GET_CODE (X) == PRE_MODIFY) \
2616 { \
2617 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2618 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2619 asm_fprintf (STREAM, "#%wd]!", \
2620 INTVAL (XEXP (XEXP (X, 1), 1))); \
2621 else \
2622 asm_fprintf (STREAM, "%r]!", \
2623 REGNO (XEXP (XEXP (X, 1), 1))); \
2624 } \
2625 else if (GET_CODE (X) == POST_MODIFY) \
2626 { \
2627 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2628 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2629 asm_fprintf (STREAM, "#%wd", \
2630 INTVAL (XEXP (XEXP (X, 1), 1))); \
2631 else \
2632 asm_fprintf (STREAM, "%r", \
2633 REGNO (XEXP (XEXP (X, 1), 1))); \
2634 } \
2635 else output_addr_const (STREAM, X); \
2636 }
2637
2638 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2639 { \
2640 if (GET_CODE (X) == REG) \
2641 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2642 else if (GET_CODE (X) == POST_INC) \
2643 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2644 else if (GET_CODE (X) == PLUS) \
2645 { \
2646 if (GET_CODE (XEXP (X, 0)) != REG) \
2647 abort (); \
2648 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2649 asm_fprintf (STREAM, "[%r, #%wd]", \
2650 REGNO (XEXP (X, 0)), \
2651 INTVAL (XEXP (X, 1))); \
2652 else \
2653 asm_fprintf (STREAM, "[%r, %r]", \
2654 REGNO (XEXP (X, 0)), \
2655 REGNO (XEXP (X, 1))); \
2656 } \
2657 else \
2658 output_addr_const (STREAM, X); \
2659 }
2660
2661 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2662 if (TARGET_ARM) \
2663 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2664 else \
2665 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2666
2667 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2668 if (GET_CODE (X) != CONST_VECTOR \
2669 || ! arm_emit_vector_const (FILE, X)) \
2670 goto FAIL;
2671
2672 /* A C expression whose value is RTL representing the value of the return
2673 address for the frame COUNT steps up from the current frame. */
2674
2675 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2676 arm_return_addr (COUNT, FRAME)
2677
2678 /* Mask of the bits in the PC that contain the real return address
2679 when running in 26-bit mode. */
2680 #define RETURN_ADDR_MASK26 (0x03fffffc)
2681
2682 /* Pick up the return address upon entry to a procedure. Used for
2683 dwarf2 unwind information. This also enables the table driven
2684 mechanism. */
2685 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2686 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2687
2688 /* Used to mask out junk bits from the return address, such as
2689 processor state, interrupt status, condition codes and the like. */
2690 #define MASK_RETURN_ADDR \
2691 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2692 in 26 bit mode, the condition codes must be masked out of the \
2693 return address. This does not apply to ARM6 and later processors \
2694 when running in 32 bit mode. */ \
2695 ((!TARGET_APCS_32) ? (gen_int_mode (RETURN_ADDR_MASK26, Pmode)) \
2696 : (arm_arch4 || TARGET_THUMB) ? \
2697 (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2698 : arm_gen_return_addr_mask ())
2699
2700 \f
2701 /* Define the codes that are matched by predicates in arm.c */
2702 #define PREDICATE_CODES \
2703 {"s_register_operand", {SUBREG, REG}}, \
2704 {"arm_hard_register_operand", {REG}}, \
2705 {"f_register_operand", {SUBREG, REG}}, \
2706 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2707 {"arm_addimm_operand", {CONST_INT}}, \
2708 {"fpa_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2709 {"fpa_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2710 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2711 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2712 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2713 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2714 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2715 {"thumb_cmpneg_operand", {CONST_INT}}, \
2716 {"thumb_cbrch_target_operand", {SUBREG, REG, MEM}}, \
2717 {"offsettable_memory_operand", {MEM}}, \
2718 {"bad_signed_byte_operand", {MEM}}, \
2719 {"alignable_memory_operand", {MEM}}, \
2720 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2721 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2722 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2723 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2724 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2725 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2726 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2727 {"load_multiple_operation", {PARALLEL}}, \
2728 {"store_multiple_operation", {PARALLEL}}, \
2729 {"equality_operator", {EQ, NE}}, \
2730 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2731 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2732 UNGE, UNGT}}, \
2733 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2734 {"const_shift_operand", {CONST_INT}}, \
2735 {"multi_register_push", {PARALLEL}}, \
2736 {"cc_register", {REG}}, \
2737 {"logical_binary_operator", {AND, IOR, XOR}}, \
2738 {"cirrus_register_operand", {REG}}, \
2739 {"cirrus_fp_register", {REG}}, \
2740 {"cirrus_shift_const", {CONST_INT}}, \
2741 {"dominant_cc_register", {REG}},
2742
2743 /* Define this if you have special predicates that know special things
2744 about modes. Genrecog will warn about certain forms of
2745 match_operand without a mode; if the operand predicate is listed in
2746 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2747 #define SPECIAL_MODE_PREDICATES \
2748 "cc_register", "dominant_cc_register",
2749
2750 enum arm_builtins
2751 {
2752 ARM_BUILTIN_GETWCX,
2753 ARM_BUILTIN_SETWCX,
2754
2755 ARM_BUILTIN_WZERO,
2756
2757 ARM_BUILTIN_WAVG2BR,
2758 ARM_BUILTIN_WAVG2HR,
2759 ARM_BUILTIN_WAVG2B,
2760 ARM_BUILTIN_WAVG2H,
2761
2762 ARM_BUILTIN_WACCB,
2763 ARM_BUILTIN_WACCH,
2764 ARM_BUILTIN_WACCW,
2765
2766 ARM_BUILTIN_WMACS,
2767 ARM_BUILTIN_WMACSZ,
2768 ARM_BUILTIN_WMACU,
2769 ARM_BUILTIN_WMACUZ,
2770
2771 ARM_BUILTIN_WSADB,
2772 ARM_BUILTIN_WSADBZ,
2773 ARM_BUILTIN_WSADH,
2774 ARM_BUILTIN_WSADHZ,
2775
2776 ARM_BUILTIN_WALIGN,
2777
2778 ARM_BUILTIN_TMIA,
2779 ARM_BUILTIN_TMIAPH,
2780 ARM_BUILTIN_TMIABB,
2781 ARM_BUILTIN_TMIABT,
2782 ARM_BUILTIN_TMIATB,
2783 ARM_BUILTIN_TMIATT,
2784
2785 ARM_BUILTIN_TMOVMSKB,
2786 ARM_BUILTIN_TMOVMSKH,
2787 ARM_BUILTIN_TMOVMSKW,
2788
2789 ARM_BUILTIN_TBCSTB,
2790 ARM_BUILTIN_TBCSTH,
2791 ARM_BUILTIN_TBCSTW,
2792
2793 ARM_BUILTIN_WMADDS,
2794 ARM_BUILTIN_WMADDU,
2795
2796 ARM_BUILTIN_WPACKHSS,
2797 ARM_BUILTIN_WPACKWSS,
2798 ARM_BUILTIN_WPACKDSS,
2799 ARM_BUILTIN_WPACKHUS,
2800 ARM_BUILTIN_WPACKWUS,
2801 ARM_BUILTIN_WPACKDUS,
2802
2803 ARM_BUILTIN_WADDB,
2804 ARM_BUILTIN_WADDH,
2805 ARM_BUILTIN_WADDW,
2806 ARM_BUILTIN_WADDSSB,
2807 ARM_BUILTIN_WADDSSH,
2808 ARM_BUILTIN_WADDSSW,
2809 ARM_BUILTIN_WADDUSB,
2810 ARM_BUILTIN_WADDUSH,
2811 ARM_BUILTIN_WADDUSW,
2812 ARM_BUILTIN_WSUBB,
2813 ARM_BUILTIN_WSUBH,
2814 ARM_BUILTIN_WSUBW,
2815 ARM_BUILTIN_WSUBSSB,
2816 ARM_BUILTIN_WSUBSSH,
2817 ARM_BUILTIN_WSUBSSW,
2818 ARM_BUILTIN_WSUBUSB,
2819 ARM_BUILTIN_WSUBUSH,
2820 ARM_BUILTIN_WSUBUSW,
2821
2822 ARM_BUILTIN_WAND,
2823 ARM_BUILTIN_WANDN,
2824 ARM_BUILTIN_WOR,
2825 ARM_BUILTIN_WXOR,
2826
2827 ARM_BUILTIN_WCMPEQB,
2828 ARM_BUILTIN_WCMPEQH,
2829 ARM_BUILTIN_WCMPEQW,
2830 ARM_BUILTIN_WCMPGTUB,
2831 ARM_BUILTIN_WCMPGTUH,
2832 ARM_BUILTIN_WCMPGTUW,
2833 ARM_BUILTIN_WCMPGTSB,
2834 ARM_BUILTIN_WCMPGTSH,
2835 ARM_BUILTIN_WCMPGTSW,
2836
2837 ARM_BUILTIN_TEXTRMSB,
2838 ARM_BUILTIN_TEXTRMSH,
2839 ARM_BUILTIN_TEXTRMSW,
2840 ARM_BUILTIN_TEXTRMUB,
2841 ARM_BUILTIN_TEXTRMUH,
2842 ARM_BUILTIN_TEXTRMUW,
2843 ARM_BUILTIN_TINSRB,
2844 ARM_BUILTIN_TINSRH,
2845 ARM_BUILTIN_TINSRW,
2846
2847 ARM_BUILTIN_WMAXSW,
2848 ARM_BUILTIN_WMAXSH,
2849 ARM_BUILTIN_WMAXSB,
2850 ARM_BUILTIN_WMAXUW,
2851 ARM_BUILTIN_WMAXUH,
2852 ARM_BUILTIN_WMAXUB,
2853 ARM_BUILTIN_WMINSW,
2854 ARM_BUILTIN_WMINSH,
2855 ARM_BUILTIN_WMINSB,
2856 ARM_BUILTIN_WMINUW,
2857 ARM_BUILTIN_WMINUH,
2858 ARM_BUILTIN_WMINUB,
2859
2860 ARM_BUILTIN_WMULUH,
2861 ARM_BUILTIN_WMULSH,
2862 ARM_BUILTIN_WMULUL,
2863
2864 ARM_BUILTIN_PSADBH,
2865 ARM_BUILTIN_WSHUFH,
2866
2867 ARM_BUILTIN_WSLLH,
2868 ARM_BUILTIN_WSLLW,
2869 ARM_BUILTIN_WSLLD,
2870 ARM_BUILTIN_WSRAH,
2871 ARM_BUILTIN_WSRAW,
2872 ARM_BUILTIN_WSRAD,
2873 ARM_BUILTIN_WSRLH,
2874 ARM_BUILTIN_WSRLW,
2875 ARM_BUILTIN_WSRLD,
2876 ARM_BUILTIN_WRORH,
2877 ARM_BUILTIN_WRORW,
2878 ARM_BUILTIN_WRORD,
2879 ARM_BUILTIN_WSLLHI,
2880 ARM_BUILTIN_WSLLWI,
2881 ARM_BUILTIN_WSLLDI,
2882 ARM_BUILTIN_WSRAHI,
2883 ARM_BUILTIN_WSRAWI,
2884 ARM_BUILTIN_WSRADI,
2885 ARM_BUILTIN_WSRLHI,
2886 ARM_BUILTIN_WSRLWI,
2887 ARM_BUILTIN_WSRLDI,
2888 ARM_BUILTIN_WRORHI,
2889 ARM_BUILTIN_WRORWI,
2890 ARM_BUILTIN_WRORDI,
2891
2892 ARM_BUILTIN_WUNPCKIHB,
2893 ARM_BUILTIN_WUNPCKIHH,
2894 ARM_BUILTIN_WUNPCKIHW,
2895 ARM_BUILTIN_WUNPCKILB,
2896 ARM_BUILTIN_WUNPCKILH,
2897 ARM_BUILTIN_WUNPCKILW,
2898
2899 ARM_BUILTIN_WUNPCKEHSB,
2900 ARM_BUILTIN_WUNPCKEHSH,
2901 ARM_BUILTIN_WUNPCKEHSW,
2902 ARM_BUILTIN_WUNPCKEHUB,
2903 ARM_BUILTIN_WUNPCKEHUH,
2904 ARM_BUILTIN_WUNPCKEHUW,
2905 ARM_BUILTIN_WUNPCKELSB,
2906 ARM_BUILTIN_WUNPCKELSH,
2907 ARM_BUILTIN_WUNPCKELSW,
2908 ARM_BUILTIN_WUNPCKELUB,
2909 ARM_BUILTIN_WUNPCKELUH,
2910 ARM_BUILTIN_WUNPCKELUW,
2911
2912 ARM_BUILTIN_MAX
2913 };
2914 #endif /* ! GCC_ARM_H */