gcc/config/arm/arm1136jfs.md

   1 ;; ARM 1136J[F]-S Pipeline Description
   2 ;; Copyright (C) 2003-2013 Free Software Foundation, Inc.
   3 ;; Written by CodeSourcery, LLC.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.  */
  20
  21 ;; These descriptions are based on the information contained in the
  22 ;; ARM1136JF-S Technical Reference Manual, Copyright (c) 2003 ARM
  23 ;; Limited.
  24 ;;
  25
  26 ;; This automaton provides a pipeline description for the ARM
  27 ;; 1136J-S and 1136JF-S cores.
  28 ;;
  29 ;; The model given here assumes that the condition for all conditional
  30 ;; instructions is "true", i.e., that all of the instructions are
  31 ;; actually executed.
  32
  33 (define_automaton "arm1136jfs")
  34
  35 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  36 ;; Pipelines
  37 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  38
  39 ;; There are three distinct pipelines (page 1-26 and following):
  40 ;;
  41 ;; - A 4-stage decode pipeline, shared by all three.  It has fetch (1),
  42 ;;   fetch (2), decode, and issue stages.  Since this is always involved,
  43 ;;   we do not model it in the scheduler.
  44 ;;
  45 ;; - A 4-stage ALU pipeline.  It has shifter, ALU (main integer operations),
  46 ;;   and saturation stages.  The fourth stage is writeback; see below.
  47 ;;
  48 ;; - A 4-stage multiply-accumulate pipeline.  It has three stages, called
  49 ;;   MAC1 through MAC3, and a fourth writeback stage.
  50 ;;
  51 ;;   The 4th-stage writeback is shared between the ALU and MAC pipelines,
  52 ;;   which operate in lockstep.  Results from either pipeline will be
  53 ;;   moved into the writeback stage.  Because the two pipelines operate
  54 ;;   in lockstep, we schedule them as a single "execute" pipeline.
  55 ;;
  56 ;; - A 4-stage LSU pipeline.  It has address generation, data cache (1),
  57 ;;   data cache (2), and writeback stages.  (Note that this pipeline,
  58 ;;   including the writeback stage, is independent from the ALU & LSU pipes.)
  59
  60 (define_cpu_unit "e_1,e_2,e_3,e_wb" "arm1136jfs")     ; ALU and MAC
  61 ; e_1 = Sh/Mac1, e_2 = ALU/Mac2, e_3 = SAT/Mac3
  62 (define_cpu_unit "l_a,l_dc1,l_dc2,l_wb" "arm1136jfs") ; Load/Store
  63
  64 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  65 ;; ALU Instructions
  66 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  67
  68 ;; ALU instructions require eight cycles to execute, and use the ALU
  69 ;; pipeline in each of the eight stages.  The results are available
  70 ;; after the alu stage has finished.
  71 ;;
  72 ;; If the destination register is the PC, the pipelines are stalled
  73 ;; for several cycles.  That case is not modelled here.
  74
  75 ;; ALU operations with no shifted operand
  76 (define_insn_reservation "11_alu_op" 2
  77  (and (eq_attr "tune" "arm1136js,arm1136jfs")
  78       (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
  79                        mov_imm,mov_reg,mvn_imm,mvn_reg"))
  80  "e_1,e_2,e_3,e_wb")
  81
  82 ;; ALU operations with a shift-by-constant operand
  83 (define_insn_reservation "11_alu_shift_op" 2
  84  (and (eq_attr "tune" "arm1136js,arm1136jfs")
  85       (eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift"))
  86  "e_1,e_2,e_3,e_wb")
  87
  88 ;; ALU operations with a shift-by-register operand
  89 ;; These really stall in the decoder, in order to read
  90 ;; the shift value in a second cycle. Pretend we take two cycles in
  91 ;; the shift stage.
  92 (define_insn_reservation "11_alu_shift_reg_op" 3
  93  (and (eq_attr "tune" "arm1136js,arm1136jfs")
  94       (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
  95  "e_1*2,e_2,e_3,e_wb")
  96
  97 ;; alu_ops can start sooner, if there is no shifter dependency
  98 (define_bypass 1 "11_alu_op,11_alu_shift_op"
  99                "11_alu_op")
 100 (define_bypass 1 "11_alu_op,11_alu_shift_op"
 101                "11_alu_shift_op"
 102                "arm_no_early_alu_shift_value_dep")
 103 (define_bypass 1 "11_alu_op,11_alu_shift_op"
 104                "11_alu_shift_reg_op"
 105                "arm_no_early_alu_shift_dep")
 106 (define_bypass 2 "11_alu_shift_reg_op"
 107                "11_alu_op")
 108 (define_bypass 2 "11_alu_shift_reg_op"
 109                "11_alu_shift_op"
 110                "arm_no_early_alu_shift_value_dep")
 111 (define_bypass 2 "11_alu_shift_reg_op"
 112                "11_alu_shift_reg_op"
 113                "arm_no_early_alu_shift_dep")
 114
 115 (define_bypass 1 "11_alu_op,11_alu_shift_op"
 116                "11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
 117                "arm_no_early_mul_dep")
 118 (define_bypass 2 "11_alu_shift_reg_op"
 119                "11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
 120                "arm_no_early_mul_dep")
 121
 122 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 123 ;; Multiplication Instructions
 124 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 125
 126 ;; Multiplication instructions loop in the first two execute stages until
 127 ;; the instruction has been passed through the multiplier array enough
 128 ;; times.
 129
 130 ;; Multiply and multiply-accumulate results are available after four stages.
 131 (define_insn_reservation "11_mult1" 4
 132  (and (eq_attr "tune" "arm1136js,arm1136jfs")
 133       (eq_attr "type" "mul,mla"))
 134  "e_1*2,e_2,e_3,e_wb")
 135
 136 ;; The *S variants set the condition flags, which requires three more cycles.
 137 (define_insn_reservation "11_mult2" 4
 138  (and (eq_attr "tune" "arm1136js,arm1136jfs")
 139       (eq_attr "type" "muls,mlas"))
 140  "e_1*2,e_2,e_3,e_wb")
 141
 142 (define_bypass 3 "11_mult1,11_mult2"
 143                "11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
 144                "arm_no_early_mul_dep")
 145 (define_bypass 3 "11_mult1,11_mult2"
 146                "11_alu_op")
 147 (define_bypass 3 "11_mult1,11_mult2"
 148                "11_alu_shift_op"
 149                "arm_no_early_alu_shift_value_dep")
 150 (define_bypass 3 "11_mult1,11_mult2"
 151                "11_alu_shift_reg_op"
 152                "arm_no_early_alu_shift_dep")
 153 (define_bypass 3 "11_mult1,11_mult2"
 154                "11_store1"
 155                "arm_no_early_store_addr_dep")
 156
 157 ;; Signed and unsigned multiply long results are available across two cycles;
 158 ;; the less significant word is available one cycle before the more significant
 159 ;; word.  Here we conservatively wait until both are available, which is
 160 ;; after three iterations and the memory cycle.  The same is also true of
 161 ;; the two multiply-accumulate instructions.
 162 (define_insn_reservation "11_mult3" 5
 163  (and (eq_attr "tune" "arm1136js,arm1136jfs")
 164       (eq_attr "type" "smull,umull,smlal,umlal"))
 165  "e_1*3,e_2,e_3,e_wb*2")
 166
 167 ;; The *S variants set the condition flags, which requires three more cycles.
 168 (define_insn_reservation "11_mult4" 5
 169  (and (eq_attr "tune" "arm1136js,arm1136jfs")
 170       (eq_attr "type" "smulls,umulls,smlals,umlals"))
 171  "e_1*3,e_2,e_3,e_wb*2")
 172
 173 (define_bypass 4 "11_mult3,11_mult4"
 174                "11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
 175                "arm_no_early_mul_dep")
 176 (define_bypass 4 "11_mult3,11_mult4"
 177                "11_alu_op")
 178 (define_bypass 4 "11_mult3,11_mult4"
 179                "11_alu_shift_op"
 180                "arm_no_early_alu_shift_value_dep")
 181 (define_bypass 4 "11_mult3,11_mult4"
 182                "11_alu_shift_reg_op"
 183                "arm_no_early_alu_shift_dep")
 184 (define_bypass 4 "11_mult3,11_mult4"
 185                "11_store1"
 186                "arm_no_early_store_addr_dep")
 187
 188 ;; Various 16x16->32 multiplies and multiply-accumulates, using combinations
 189 ;; of high and low halves of the argument registers.  They take a single
 190 ;; pass through the pipeline and make the result available after three
 191 ;; cycles.
 192 (define_insn_reservation "11_mult5" 3
 193  (and (eq_attr "tune" "arm1136js,arm1136jfs")
 194       (eq_attr "type" "smulxy,smlaxy,smulwy,smlawy,smuad,smuadx,smlad,smladx,\
 195                        smusd,smusdx,smlsd,smlsdx"))
 196  "e_1,e_2,e_3,e_wb")
 197
 198 (define_bypass 2 "11_mult5"
 199                "11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
 200                "arm_no_early_mul_dep")
 201 (define_bypass 2 "11_mult5"
 202                "11_alu_op")
 203 (define_bypass 2 "11_mult5"
 204                "11_alu_shift_op"
 205                "arm_no_early_alu_shift_value_dep")
 206 (define_bypass 2 "11_mult5"
 207                "11_alu_shift_reg_op"
 208                "arm_no_early_alu_shift_dep")
 209 (define_bypass 2 "11_mult5"
 210                "11_store1"
 211                "arm_no_early_store_addr_dep")
 212
 213 ;; The same idea, then the 32-bit result is added to a 64-bit quantity.
 214 (define_insn_reservation "11_mult6" 4
 215  (and (eq_attr "tune" "arm1136js,arm1136jfs")
 216       (eq_attr "type" "smlalxy"))
 217  "e_1*2,e_2,e_3,e_wb*2")
 218
 219 ;; Signed 32x32 multiply, then the most significant 32 bits are extracted
 220 ;; and are available after the memory stage.
 221 (define_insn_reservation "11_mult7" 4
 222  (and (eq_attr "tune" "arm1136js,arm1136jfs")
 223       (eq_attr "type" "smmul,smmulr"))
 224  "e_1*2,e_2,e_3,e_wb")
 225
 226 (define_bypass 3 "11_mult6,11_mult7"
 227                "11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
 228                "arm_no_early_mul_dep")
 229 (define_bypass 3 "11_mult6,11_mult7"
 230                "11_alu_op")
 231 (define_bypass 3 "11_mult6,11_mult7"
 232                "11_alu_shift_op"
 233                "arm_no_early_alu_shift_value_dep")
 234 (define_bypass 3 "11_mult6,11_mult7"
 235                "11_alu_shift_reg_op"
 236                "arm_no_early_alu_shift_dep")
 237 (define_bypass 3 "11_mult6,11_mult7"
 238                "11_store1"
 239                "arm_no_early_store_addr_dep")
 240
 241 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 242 ;; Branch Instructions
 243 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 244
 245 ;; These vary greatly depending on their arguments and the results of
 246 ;; stat prediction.  Cycle count ranges from zero (unconditional branch,
 247 ;; folded dynamic prediction) to seven (incorrect predictions, etc).  We
 248 ;; assume an optimal case for now, because the cost of a cache miss
 249 ;; overwhelms the cost of everything else anyhow.
 250
 251 (define_insn_reservation "11_branches" 0
 252  (and (eq_attr "tune" "arm1136js,arm1136jfs")
 253       (eq_attr "type" "branch"))
 254  "nothing")
 255
 256 ;; Call latencies are not predictable.  A semi-arbitrary very large
 257 ;; number is used as "positive infinity" so that everything should be
 258 ;; finished by the time of return.
 259 (define_insn_reservation "11_call" 32
 260  (and (eq_attr "tune" "arm1136js,arm1136jfs")
 261       (eq_attr "type" "call"))
 262  "nothing")
 263
 264 ;; Branches are predicted. A correctly predicted branch will be no
 265 ;; cost, but we're conservative here, and use the timings a
 266 ;; late-register would give us.
 267 (define_bypass 1 "11_alu_op,11_alu_shift_op"
 268                "11_branches")
 269 (define_bypass 2 "11_alu_shift_reg_op"
 270                "11_branches")
 271 (define_bypass 2 "11_load1,11_load2"
 272                "11_branches")
 273 (define_bypass 3 "11_load34"
 274                "11_branches")
 275
 276 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 277 ;; Load/Store Instructions
 278 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 279
 280 ;; The models for load/store instructions do not accurately describe
 281 ;; the difference between operations with a base register writeback.
 282 ;; These models assume that all memory references hit in dcache.  Also,
 283 ;; if the PC is one of the registers involved, there are additional stalls
 284 ;; not modelled here.  Addressing modes are also not modelled.
 285
 286 (define_insn_reservation "11_load1" 3
 287  (and (eq_attr "tune" "arm1136js,arm1136jfs")
 288       (eq_attr "type" "load1"))
 289  "l_a+e_1,l_dc1,l_dc2,l_wb")
 290
 291 ;; Load byte results are not available until the writeback stage, where
 292 ;; the correct byte is extracted.
 293
 294 (define_insn_reservation "11_loadb" 4
 295  (and (eq_attr "tune" "arm1136js,arm1136jfs")
 296       (eq_attr "type" "load_byte"))
 297  "l_a+e_1,l_dc1,l_dc2,l_wb")
 298
 299 (define_insn_reservation "11_store1" 0
 300  (and (eq_attr "tune" "arm1136js,arm1136jfs")
 301       (eq_attr "type" "store1"))
 302  "l_a+e_1,l_dc1,l_dc2,l_wb")
 303
 304 ;; Load/store double words into adjacent registers.  The timing and
 305 ;; latencies are different depending on whether the address is 64-bit
 306 ;; aligned.  This model assumes that it is.
 307 (define_insn_reservation "11_load2" 3
 308  (and (eq_attr "tune" "arm1136js,arm1136jfs")
 309       (eq_attr "type" "load2"))
 310  "l_a+e_1,l_dc1,l_dc2,l_wb")
 311
 312 (define_insn_reservation "11_store2" 0
 313  (and (eq_attr "tune" "arm1136js,arm1136jfs")
 314       (eq_attr "type" "store2"))
 315  "l_a+e_1,l_dc1,l_dc2,l_wb")
 316
 317 ;; Load/store multiple registers.  Two registers are stored per cycle.
 318 ;; Actual timing depends on how many registers are affected, so we
 319 ;; optimistically schedule a low latency.
 320 (define_insn_reservation "11_load34" 4
 321  (and (eq_attr "tune" "arm1136js,arm1136jfs")
 322       (eq_attr "type" "load3,load4"))
 323  "l_a+e_1,l_dc1*2,l_dc2,l_wb")
 324
 325 (define_insn_reservation "11_store34" 0
 326  (and (eq_attr "tune" "arm1136js,arm1136jfs")
 327       (eq_attr "type" "store3,store4"))
 328  "l_a+e_1,l_dc1*2,l_dc2,l_wb")
 329
 330 ;; A store can start immediately after an alu op, if that alu op does
 331 ;; not provide part of the address to access.
 332 (define_bypass 1 "11_alu_op,11_alu_shift_op"
 333                "11_store1"
 334                "arm_no_early_store_addr_dep")
 335 (define_bypass 2 "11_alu_shift_reg_op"
 336                "11_store1"
 337                "arm_no_early_store_addr_dep")
 338
 339 ;; An alu op can start sooner after a load, if that alu op does not
 340 ;; have an early register dependency on the load
 341 (define_bypass 2 "11_load1"
 342                "11_alu_op")
 343 (define_bypass 2 "11_load1"
 344                "11_alu_shift_op"
 345                "arm_no_early_alu_shift_value_dep")
 346 (define_bypass 2 "11_load1"
 347                "11_alu_shift_reg_op"
 348                "arm_no_early_alu_shift_dep")
 349
 350 (define_bypass 3 "11_loadb"
 351                "11_alu_op")
 352 (define_bypass 3 "11_loadb"
 353                "11_alu_shift_op"
 354                "arm_no_early_alu_shift_value_dep")
 355 (define_bypass 3 "11_loadb"
 356                "11_alu_shift_reg_op"
 357                "arm_no_early_alu_shift_dep")
 358
 359 ;; A mul op can start sooner after a load, if that mul op does not
 360 ;; have an early multiply dependency
 361 (define_bypass 2 "11_load1"
 362                "11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
 363                "arm_no_early_mul_dep")
 364 (define_bypass 3 "11_load34"
 365                "11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
 366                "arm_no_early_mul_dep")
 367 (define_bypass 3 "11_loadb"
 368                "11_mult1,11_mult2,11_mult3,11_mult4,11_mult5,11_mult6,11_mult7"
 369                "arm_no_early_mul_dep")
 370
 371 ;; A store can start sooner after a load, if that load does not
 372 ;; produce part of the address to access
 373 (define_bypass 2 "11_load1"
 374                "11_store1"
 375                "arm_no_early_store_addr_dep")
 376 (define_bypass 3 "11_loadb"
 377                "11_store1"
 378                "arm_no_early_store_addr_dep")