1 ;; ARM Cortex-M4 pipeline description
2 ;; Copyright (C) 2010 Free Software Foundation, Inc.
3 ;; Contributed by CodeSourcery.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_automaton "cortex_m4")
23 ;; We model the pipelining of LDR instructions by using two artificial units.
25 (define_cpu_unit "cortex_m4_a" "cortex_m4")
27 (define_cpu_unit "cortex_m4_b" "cortex_m4")
29 (define_reservation "cortex_m4_ex" "cortex_m4_a+cortex_m4_b")
31 ;; ALU and multiply is one cycle.
32 (define_insn_reservation "cortex_m4_alu" 1
33 (and (eq_attr "tune" "cortexm4")
34 (eq_attr "type" "alu,alu_shift,alu_shift_reg,mult"))
37 ;; Byte, half-word and word load is two cycles.
38 (define_insn_reservation "cortex_m4_load1" 2
39 (and (eq_attr "tune" "cortexm4")
40 (eq_attr "type" "load_byte,load1"))
41 "cortex_m4_a, cortex_m4_b")
43 ;; str rx, [ry, #imm] is always one cycle.
44 (define_insn_reservation "cortex_m4_store1_1" 1
45 (and (and (eq_attr "tune" "cortexm4")
46 (eq_attr "type" "store1"))
47 (match_test "arm_address_offset_is_imm (insn)"))
50 ;; Other byte, half-word and word load is two cycles.
51 (define_insn_reservation "cortex_m4_store1_2" 2
52 (and (and (eq_attr "tune" "cortexm4")
53 (eq_attr "type" "store1"))
54 (not (match_test "arm_address_offset_is_imm (insn)")))
57 (define_insn_reservation "cortex_m4_load2" 3
58 (and (eq_attr "tune" "cortexm4")
59 (eq_attr "type" "load2"))
62 (define_insn_reservation "cortex_m4_store2" 3
63 (and (eq_attr "tune" "cortexm4")
64 (eq_attr "type" "store2"))
67 (define_insn_reservation "cortex_m4_load3" 4
68 (and (eq_attr "tune" "cortexm4")
69 (eq_attr "type" "load3"))
72 (define_insn_reservation "cortex_m4_store3" 4
73 (and (eq_attr "tune" "cortexm4")
74 (eq_attr "type" "store3"))
77 (define_insn_reservation "cortex_m4_load4" 5
78 (and (eq_attr "tune" "cortexm4")
79 (eq_attr "type" "load4"))
82 (define_insn_reservation "cortex_m4_store4" 5
83 (and (eq_attr "tune" "cortexm4")
84 (eq_attr "type" "store4"))
87 ;; If the address of load or store depends on the result of the preceding
88 ;; instruction, the latency is increased by one.
90 (define_bypass 2 "cortex_m4_alu"
92 "arm_early_load_addr_dep")
94 (define_bypass 2 "cortex_m4_alu"
95 "cortex_m4_store1_1,cortex_m4_store1_2"
96 "arm_early_store_addr_dep")
98 (define_insn_reservation "cortex_m4_branch" 3
99 (and (eq_attr "tune" "cortexm4")
100 (eq_attr "type" "branch"))
103 (define_insn_reservation "cortex_m4_call" 3
104 (and (eq_attr "tune" "cortexm4")
105 (eq_attr "type" "call"))
108 (define_insn_reservation "cortex_m4_block" 1
109 (and (eq_attr "tune" "cortexm4")
110 (eq_attr "type" "block"))