gcc/config/arm/iterators.md

   1 ;; Code and mode itertator and attribute definitions for the ARM backend
   2 ;; Copyright (C) 2010-2017 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21
  22 ;;----------------------------------------------------------------------------
  23 ;; Mode iterators
  24 ;;----------------------------------------------------------------------------
  25
  26 ;; A list of modes that are exactly 64 bits in size. This is used to expand
  27 ;; some splits that are the same for all modes when operating on ARM
  28 ;; registers.
  29 (define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF])
  30
  31 (define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF])
  32
  33 ;; A list of integer modes that are up to one word long
  34 (define_mode_iterator QHSI [QI HI SI])
  35
  36 ;; A list of integer modes that are half and one word long
  37 (define_mode_iterator HSI [HI SI])
  38
  39 ;; A list of integer modes that are less than a word
  40 (define_mode_iterator NARROW [QI HI])
  41
  42 ;; A list of all the integer modes up to 64bit
  43 (define_mode_iterator QHSD [QI HI SI DI])
  44
  45 ;; A list of the 32bit and 64bit integer modes
  46 (define_mode_iterator SIDI [SI DI])
  47
  48 ;; A list of atomic compare and swap success return modes
  49 (define_mode_iterator CCSI [(CC_Z "TARGET_32BIT") (SI "TARGET_THUMB1")])
  50
  51 ;; A list of modes which the VFP unit can handle
  52 (define_mode_iterator SDF [(SF "") (DF "TARGET_VFP_DOUBLE")])
  53
  54 ;; Integer element sizes implemented by IWMMXT.
  55 (define_mode_iterator VMMX [V2SI V4HI V8QI])
  56
  57 (define_mode_iterator VMMX2 [V4HI V2SI])
  58
  59 ;; Integer element sizes for shifts.
  60 (define_mode_iterator VSHFT [V4HI V2SI DI])
  61
  62 ;; Integer and float modes supported by Neon and IWMMXT.
  63 (define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
  64
  65 ;; Integer and float modes supported by Neon and IWMMXT, except V2DI.
  66 (define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
  67
  68 ;; Integer modes supported by Neon and IWMMXT
  69 (define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI])
  70
  71 ;; Integer modes supported by Neon and IWMMXT, except V2DI
  72 (define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI])
  73
  74 ;; Double-width vector modes, on which we support arithmetic (no HF!)
  75 (define_mode_iterator VD [V8QI V4HI V2SI V2SF])
  76
  77 ;; Double-width vector modes plus 64-bit elements for vreinterpret + vcreate.
  78 (define_mode_iterator VD_RE [V8QI V4HI V2SI V2SF DI])
  79
  80 ;; Double-width vector modes plus 64-bit elements.
  81 (define_mode_iterator VDX [V8QI V4HI V4HF V2SI V2SF DI])
  82
  83 ;; Double-width vector modes, with V4HF - for vldN_lane and vstN_lane.
  84 (define_mode_iterator VD_LANE [V8QI V4HI V4HF V2SI V2SF])
  85
  86 ;; Double-width vector modes without floating-point elements.
  87 (define_mode_iterator VDI [V8QI V4HI V2SI])
  88
  89 ;; Quad-width vector modes supporting arithmetic (no HF!).
  90 (define_mode_iterator VQ [V16QI V8HI V4SI V4SF])
  91
  92 ;; Quad-width vector modes, including V8HF.
  93 (define_mode_iterator VQ2 [V16QI V8HI V8HF V4SI V4SF])
  94
  95 ;; Quad-width vector modes with 16- or 32-bit elements
  96 (define_mode_iterator VQ_HS [V8HI V8HF V4SI V4SF])
  97
  98 ;; Quad-width vector modes plus 64-bit elements.
  99 (define_mode_iterator VQX [V16QI V8HI V8HF V4SI V4SF V2DI])
 100
 101 ;; Quad-width vector modes without floating-point elements.
 102 (define_mode_iterator VQI [V16QI V8HI V4SI])
 103
 104 ;; Quad-width vector modes, with TImode added, for moves.
 105 (define_mode_iterator VQXMOV [V16QI V8HI V8HF V4SI V4SF V2DI TI])
 106
 107 ;; Opaque structure types wider than TImode.
 108 (define_mode_iterator VSTRUCT [EI OI CI XI])
 109
 110 ;; Opaque structure types used in table lookups (except vtbl1/vtbx1).
 111 (define_mode_iterator VTAB [TI EI OI])
 112
 113 ;; Widenable modes.
 114 (define_mode_iterator VW [V8QI V4HI V2SI])
 115
 116 ;; Narrowable modes.
 117 (define_mode_iterator VN [V8HI V4SI V2DI])
 118
 119 ;; All supported vector modes (except singleton DImode).
 120 (define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V4HF V8HF V2SF V4SF V2DI])
 121
 122 ;; All supported vector modes (except those with 64-bit integer elements).
 123 (define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF])
 124
 125 ;; All supported vector modes including 16-bit float modes.
 126 (define_mode_iterator VDQWH [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF
 127                              V8HF V4HF])
 128
 129 ;; Supported integer vector modes (not 64 bit elements).
 130 (define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI])
 131
 132 ;; Supported integer vector modes (not singleton DI)
 133 (define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
 134
 135 ;; Vector modes, including 64-bit integer elements.
 136 (define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI
 137                             V4HF V8HF V2SF V4SF DI V2DI])
 138
 139 ;; Vector modes including 64-bit integer elements, but no floats.
 140 (define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI])
 141
 142 ;; Vector modes for H, S and D types.
 143 (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
 144
 145 ;; Vector modes for float->int conversions.
 146 (define_mode_iterator VCVTF [V2SF V4SF])
 147
 148 ;; Vector modes form int->float conversions.
 149 (define_mode_iterator VCVTI [V2SI V4SI])
 150
 151 ;; Vector modes for int->half conversions.
 152 (define_mode_iterator VCVTHI [V4HI V8HI])
 153
 154 ;; Vector modes for doubleword multiply-accumulate, etc. insns.
 155 (define_mode_iterator VMD [V4HI V2SI V2SF])
 156
 157 ;; Vector modes for quadword multiply-accumulate, etc. insns.
 158 (define_mode_iterator VMQ [V8HI V4SI V4SF])
 159
 160 ;; Above modes combined.
 161 (define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF])
 162
 163 ;; As VMD, but integer modes only.
 164 (define_mode_iterator VMDI [V4HI V2SI])
 165
 166 ;; As VMQ, but integer modes only.
 167 (define_mode_iterator VMQI [V8HI V4SI])
 168
 169 ;; Above modes combined.
 170 (define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI])
 171
 172 ;; Modes with 8-bit and 16-bit elements.
 173 (define_mode_iterator VX [V8QI V4HI V16QI V8HI])
 174
 175 ;; Modes with 8-bit elements.
 176 (define_mode_iterator VE [V8QI V16QI])
 177
 178 ;; Modes with 64-bit elements only.
 179 (define_mode_iterator V64 [DI V2DI])
 180
 181 ;; Modes with 32-bit elements only.
 182 (define_mode_iterator V32 [V2SI V2SF V4SI V4SF])
 183
 184 ;; Modes with 8-bit, 16-bit and 32-bit elements.
 185 (define_mode_iterator VU [V16QI V8HI V4SI])
 186
 187 ;; Vector modes for 16-bit floating-point support.
 188 (define_mode_iterator VH [V8HF V4HF])
 189
 190 ;; Iterators used for fixed-point support.
 191 (define_mode_iterator FIXED [QQ HQ SQ UQQ UHQ USQ HA SA UHA USA])
 192
 193 (define_mode_iterator ADDSUB [V4QQ V2HQ V2HA])
 194
 195 (define_mode_iterator UQADDSUB [V4UQQ V2UHQ UQQ UHQ V2UHA UHA])
 196
 197 (define_mode_iterator QADDSUB [V4QQ V2HQ QQ HQ V2HA HA SQ SA])
 198
 199 (define_mode_iterator QMUL [HQ HA])
 200
 201 ;; Modes for polynomial or float values.
 202 (define_mode_iterator VPF [V8QI V16QI V2SF V4SF])
 203
 204 ;;----------------------------------------------------------------------------
 205 ;; Code iterators
 206 ;;----------------------------------------------------------------------------
 207
 208 ;; A list of condition codes used in compare instructions where
 209 ;; the carry flag from the addition is used instead of doing the
 210 ;; compare a second time.
 211 (define_code_iterator LTUGEU [ltu geu])
 212
 213 ;; The signed gt, ge comparisons
 214 (define_code_iterator GTGE [gt ge])
 215
 216 ;; The signed gt, ge, lt, le comparisons
 217 (define_code_iterator GLTE [gt ge lt le])
 218
 219 ;; The unsigned gt, ge comparisons
 220 (define_code_iterator GTUGEU [gtu geu])
 221
 222 ;; Comparisons for vc<cmp>
 223 (define_code_iterator COMPARISONS [eq gt ge le lt])
 224
 225 ;; A list of ...
 226 (define_code_iterator IOR_XOR [ior xor])
 227
 228 ;; Operations on two halves of a quadword vector.
 229 (define_code_iterator VQH_OPS [plus smin smax umin umax])
 230
 231 ;; Operations on two halves of a quadword vector,
 232 ;; without unsigned variants (for use with *SFmode pattern).
 233 (define_code_iterator VQHS_OPS [plus smin smax])
 234
 235 ;; A list of widening operators
 236 (define_code_iterator SE [sign_extend zero_extend])
 237
 238 ;; Right shifts
 239 (define_code_iterator RSHIFTS [ashiftrt lshiftrt])
 240
 241 ;; Iterator for integer conversions
 242 (define_code_iterator FIXUORS [fix unsigned_fix])
 243
 244 ;; Binary operators whose second operand can be shifted.
 245 (define_code_iterator SHIFTABLE_OPS [plus minus ior xor and])
 246
 247 ;; Operations on the sign of a number.
 248 (define_code_iterator ABSNEG [abs neg])
 249
 250 ;; Conversions.
 251 (define_code_iterator FCVT [unsigned_float float])
 252
 253 ;; plus and minus are the only SHIFTABLE_OPS for which Thumb2 allows
 254 ;; a stack pointer opoerand.  The minus operation is a candidate for an rsub
 255 ;; and hence only plus is supported.
 256 (define_code_attr t2_binop0
 257   [(plus "rk") (minus "r") (ior "r") (xor "r") (and "r")])
 258
 259 ;; The instruction to use when a SHIFTABLE_OPS has a shift operation as
 260 ;; its first operand.
 261 (define_code_attr arith_shift_insn
 262   [(plus "add") (minus "rsb") (ior "orr") (xor "eor") (and "and")])
 263
 264 (define_code_attr cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le")
 265                           (gtu "gt") (geu "ge")])
 266
 267 (define_code_attr cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s")])
 268
 269 ;;----------------------------------------------------------------------------
 270 ;; Int iterators
 271 ;;----------------------------------------------------------------------------
 272
 273 (define_int_iterator VRINT [UNSPEC_VRINTZ UNSPEC_VRINTP UNSPEC_VRINTM
 274                             UNSPEC_VRINTR UNSPEC_VRINTX UNSPEC_VRINTA])
 275
 276 (define_int_iterator NEON_VCMP [UNSPEC_VCEQ UNSPEC_VCGT UNSPEC_VCGE
 277                                 UNSPEC_VCLT UNSPEC_VCLE])
 278
 279 (define_int_iterator NEON_VACMP [UNSPEC_VCAGE UNSPEC_VCAGT])
 280
 281 (define_int_iterator NEON_VAGLTE [UNSPEC_VCAGE UNSPEC_VCAGT
 282                                   UNSPEC_VCALE UNSPEC_VCALT])
 283
 284 (define_int_iterator VCVT [UNSPEC_VRINTP UNSPEC_VRINTM UNSPEC_VRINTA])
 285
 286 (define_int_iterator NEON_VRINT [UNSPEC_NVRINTP UNSPEC_NVRINTZ UNSPEC_NVRINTM
 287                               UNSPEC_NVRINTX UNSPEC_NVRINTA UNSPEC_NVRINTN])
 288
 289 (define_int_iterator NEON_VCVT [UNSPEC_NVRINTP UNSPEC_NVRINTM UNSPEC_NVRINTA])
 290
 291 (define_int_iterator VADDL [UNSPEC_VADDL_S UNSPEC_VADDL_U])
 292
 293 (define_int_iterator VADDW [UNSPEC_VADDW_S UNSPEC_VADDW_U])
 294
 295 (define_int_iterator VHADD [UNSPEC_VRHADD_S UNSPEC_VRHADD_U
 296                             UNSPEC_VHADD_S UNSPEC_VHADD_U])
 297
 298 (define_int_iterator VQADD [UNSPEC_VQADD_S UNSPEC_VQADD_U])
 299
 300 (define_int_iterator VADDHN [UNSPEC_VADDHN UNSPEC_VRADDHN])
 301
 302 (define_int_iterator VMLAL [UNSPEC_VMLAL_S UNSPEC_VMLAL_U])
 303
 304 (define_int_iterator VMLAL_LANE [UNSPEC_VMLAL_S_LANE UNSPEC_VMLAL_U_LANE])
 305
 306 (define_int_iterator VMLSL [UNSPEC_VMLSL_S UNSPEC_VMLSL_U])
 307
 308 (define_int_iterator VMLSL_LANE [UNSPEC_VMLSL_S_LANE UNSPEC_VMLSL_U_LANE])
 309
 310 (define_int_iterator VQDMULH [UNSPEC_VQDMULH UNSPEC_VQRDMULH])
 311
 312 (define_int_iterator VQDMULH_LANE [UNSPEC_VQDMULH_LANE UNSPEC_VQRDMULH_LANE])
 313
 314 (define_int_iterator VMULL [UNSPEC_VMULL_S UNSPEC_VMULL_U UNSPEC_VMULL_P])
 315
 316 (define_int_iterator VMULL_LANE [UNSPEC_VMULL_S_LANE UNSPEC_VMULL_U_LANE])
 317
 318 (define_int_iterator VSUBL [UNSPEC_VSUBL_S UNSPEC_VSUBL_U])
 319
 320 (define_int_iterator VSUBW [UNSPEC_VSUBW_S UNSPEC_VSUBW_U])
 321
 322 (define_int_iterator VHSUB [UNSPEC_VHSUB_S UNSPEC_VHSUB_U])
 323
 324 (define_int_iterator VQSUB [UNSPEC_VQSUB_S UNSPEC_VQSUB_U])
 325
 326 (define_int_iterator VSUBHN [UNSPEC_VSUBHN UNSPEC_VRSUBHN])
 327
 328 (define_int_iterator VABD [UNSPEC_VABD_S UNSPEC_VABD_U])
 329
 330 (define_int_iterator VABDL [UNSPEC_VABDL_S UNSPEC_VABDL_U])
 331
 332 (define_int_iterator VMAXMIN [UNSPEC_VMAX UNSPEC_VMAX_U
 333                               UNSPEC_VMIN UNSPEC_VMIN_U])
 334
 335 (define_int_iterator VMAXMINF [UNSPEC_VMAX UNSPEC_VMIN])
 336
 337 (define_int_iterator VMAXMINFNM [UNSPEC_VMAXNM UNSPEC_VMINNM])
 338
 339 (define_int_iterator VPADDL [UNSPEC_VPADDL_S UNSPEC_VPADDL_U])
 340
 341 (define_int_iterator VPADAL [UNSPEC_VPADAL_S UNSPEC_VPADAL_U])
 342
 343 (define_int_iterator VPMAXMIN [UNSPEC_VPMAX UNSPEC_VPMAX_U
 344                                UNSPEC_VPMIN UNSPEC_VPMIN_U])
 345
 346 (define_int_iterator VPMAXMINF [UNSPEC_VPMAX UNSPEC_VPMIN])
 347
 348 (define_int_iterator VCVT_US [UNSPEC_VCVT_S UNSPEC_VCVT_U])
 349
 350 (define_int_iterator VCVT_US_N [UNSPEC_VCVT_S_N UNSPEC_VCVT_U_N])
 351
 352 (define_int_iterator VCVT_HF_US_N [UNSPEC_VCVT_HF_S_N UNSPEC_VCVT_HF_U_N])
 353
 354 (define_int_iterator VCVT_SI_US_N [UNSPEC_VCVT_SI_S_N UNSPEC_VCVT_SI_U_N])
 355
 356 (define_int_iterator VCVT_HF_US [UNSPEC_VCVTA_S UNSPEC_VCVTA_U
 357                                  UNSPEC_VCVTM_S UNSPEC_VCVTM_U
 358                                  UNSPEC_VCVTN_S UNSPEC_VCVTN_U
 359                                  UNSPEC_VCVTP_S UNSPEC_VCVTP_U])
 360
 361 (define_int_iterator VCVTH_US [UNSPEC_VCVTH_S UNSPEC_VCVTH_U])
 362
 363 ;; Operators for FP16 instructions.
 364 (define_int_iterator FP16_RND [UNSPEC_VRND UNSPEC_VRNDA
 365                                UNSPEC_VRNDM UNSPEC_VRNDN
 366                                UNSPEC_VRNDP UNSPEC_VRNDX])
 367
 368 (define_int_iterator VQMOVN [UNSPEC_VQMOVN_S UNSPEC_VQMOVN_U])
 369
 370 (define_int_iterator VMOVL [UNSPEC_VMOVL_S UNSPEC_VMOVL_U])
 371
 372 (define_int_iterator VSHL [UNSPEC_VSHL_S UNSPEC_VSHL_U
 373                            UNSPEC_VRSHL_S UNSPEC_VRSHL_U])
 374
 375 (define_int_iterator VQSHL [UNSPEC_VQSHL_S UNSPEC_VQSHL_U
 376                             UNSPEC_VQRSHL_S UNSPEC_VQRSHL_U])
 377
 378 (define_int_iterator VSHR_N [UNSPEC_VSHR_S_N UNSPEC_VSHR_U_N
 379                              UNSPEC_VRSHR_S_N UNSPEC_VRSHR_U_N])
 380
 381 (define_int_iterator VSHRN_N [UNSPEC_VSHRN_N UNSPEC_VRSHRN_N])
 382
 383 (define_int_iterator VQSHRN_N [UNSPEC_VQSHRN_S_N UNSPEC_VQSHRN_U_N
 384                                UNSPEC_VQRSHRN_S_N UNSPEC_VQRSHRN_U_N])
 385
 386 (define_int_iterator VQSHRUN_N [UNSPEC_VQSHRUN_N UNSPEC_VQRSHRUN_N])
 387
 388 (define_int_iterator VQSHL_N [UNSPEC_VQSHL_S_N UNSPEC_VQSHL_U_N])
 389
 390 (define_int_iterator VSHLL_N [UNSPEC_VSHLL_S_N UNSPEC_VSHLL_U_N])
 391
 392 (define_int_iterator VSRA_N [UNSPEC_VSRA_S_N UNSPEC_VSRA_U_N
 393                              UNSPEC_VRSRA_S_N UNSPEC_VRSRA_U_N])
 394
 395 (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
 396                           UNSPEC_CRC32CB UNSPEC_CRC32CH UNSPEC_CRC32CW])
 397
 398 (define_int_iterator CRYPTO_UNARY [UNSPEC_AESMC UNSPEC_AESIMC])
 399
 400 (define_int_iterator CRYPTO_BINARY [UNSPEC_AESD UNSPEC_AESE
 401                                     UNSPEC_SHA1SU1 UNSPEC_SHA256SU0])
 402
 403 (define_int_iterator CRYPTO_TERNARY [UNSPEC_SHA1SU0 UNSPEC_SHA256H
 404                                      UNSPEC_SHA256H2 UNSPEC_SHA256SU1])
 405
 406 (define_int_iterator CRYPTO_SELECTING [UNSPEC_SHA1C UNSPEC_SHA1M
 407                                        UNSPEC_SHA1P])
 408
 409 (define_int_iterator VQRDMLH_AS [UNSPEC_VQRDMLAH UNSPEC_VQRDMLSH])
 410
 411 (define_int_iterator VFM_LANE_AS [UNSPEC_VFMA_LANE UNSPEC_VFMS_LANE])
 412
 413 ;;----------------------------------------------------------------------------
 414 ;; Mode attributes
 415 ;;----------------------------------------------------------------------------
 416
 417 ;; Determine name of atomic compare and swap from success result mode.  This
 418 ;; distinguishes between 16-bit Thumb and 32-bit Thumb/ARM.
 419 (define_mode_attr arch [(CC_Z "32") (SI "t1")])
 420
 421 ;; Determine element size suffix from vector mode.
 422 (define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")])
 423
 424 ;; vtbl<n> suffix for NEON vector modes.
 425 (define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")])
 426
 427 ;; (Opposite) mode to convert to/from for NEON mode conversions.
 428 (define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI")
 429                (V4SI "V4SF") (V4SF "V4SI")])
 430
 431 ;; As above but in lower case.
 432 (define_mode_attr V_cvtto [(V2SI "v2sf") (V2SF "v2si")
 433                            (V4SI "v4sf") (V4SF "v4si")])
 434
 435 ;; (Opposite) mode to convert to/from for vector-half mode conversions.
 436 (define_mode_attr VH_CVTTO [(V4HI "V4HF") (V4HF "V4HI")
 437                             (V8HI "V8HF") (V8HF "V8HI")])
 438
 439 ;; Define element mode for each vector mode.
 440 (define_mode_attr V_elem [(V8QI "QI") (V16QI "QI")
 441                           (V4HI "HI") (V8HI "HI")
 442                           (V4HF "HF") (V8HF "HF")
 443                           (V2SI "SI") (V4SI "SI")
 444                           (V2SF "SF") (V4SF "SF")
 445                           (DI "DI")   (V2DI "DI")])
 446
 447 ;; As above but in lower case.
 448 (define_mode_attr V_elem_l [(V8QI "qi") (V16QI "qi")
 449                             (V4HI "hi") (V8HI "hi")
 450                             (V4HF "hf") (V8HF "hf")
 451                             (V2SI "si") (V4SI "si")
 452                             (V2SF "sf") (V4SF "sf")
 453                             (DI "di")   (V2DI "di")])
 454
 455 ;; Element modes for vector extraction, padded up to register size.
 456
 457 (define_mode_attr V_ext [(V8QI "SI") (V16QI "SI")
 458              (V4HI "SI") (V8HI "SI")
 459              (V2SI "SI") (V4SI "SI")
 460              (V2SF "SF") (V4SF "SF")
 461              (DI "DI") (V2DI "DI")])
 462
 463 ;; Mode of pair of elements for each vector mode, to define transfer
 464 ;; size for structure lane/dup loads and stores.
 465 (define_mode_attr V_two_elem [(V8QI "HI")   (V16QI "HI")
 466                               (V4HI "SI")   (V8HI "SI")
 467                               (V4HF "SF")   (V8HF "SF")
 468                               (V2SI "V2SI") (V4SI "V2SI")
 469                               (V2SF "V2SF") (V4SF "V2SF")
 470                               (DI "V2DI")   (V2DI "V2DI")])
 471
 472 ;; Similar, for three elements.
 473 (define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK")
 474                                 (V4HI "BLK") (V8HI "BLK")
 475                                 (V4HF "BLK") (V8HF "BLK")
 476                                 (V2SI "BLK") (V4SI "BLK")
 477                                 (V2SF "BLK") (V4SF "BLK")
 478                                 (DI "EI")    (V2DI "EI")])
 479
 480 ;; Similar, for four elements.
 481 (define_mode_attr V_four_elem [(V8QI "SI")   (V16QI "SI")
 482                                (V4HI "V4HI") (V8HI "V4HI")
 483                                (V4HF "V4HF") (V8HF "V4HF")
 484                                (V2SI "V4SI") (V4SI "V4SI")
 485                                (V2SF "V4SF") (V4SF "V4SF")
 486                                (DI "OI")     (V2DI "OI")])
 487
 488 ;; Register width from element mode
 489 (define_mode_attr V_reg [(V8QI "P") (V16QI "q")
 490                          (V4HI "P") (V8HI  "q")
 491                          (V4HF "P") (V8HF  "q")
 492                          (V2SI "P") (V4SI  "q")
 493                          (V2SF "P") (V4SF  "q")
 494                          (DI   "P") (V2DI  "q")
 495                          (SF   "")  (DF    "P")
 496                          (HF   "")])
 497
 498 ;; Wider modes with the same number of elements.
 499 (define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")])
 500
 501 ;; Narrower modes with the same number of elements.
 502 (define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")])
 503
 504 ;; Narrower modes with double the number of elements.
 505 (define_mode_attr V_narrow_pack [(V4SI "V8HI") (V8HI "V16QI") (V2DI "V4SI")
 506                                  (V4HI "V8QI") (V2SI "V4HI")  (DI "V2SI")])
 507
 508 ;; Modes with half the number of equal-sized elements.
 509 (define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI")
 510                           (V8HF "V4HF") (V4SI  "V2SI")
 511                           (V4SF "V2SF") (V2DF "DF")
 512                           (V2DI "DI") (V4HF "HF")])
 513
 514 ;; Same, but lower-case.
 515 (define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi")
 516               (V4SI  "v2si") (V4SF "v2sf")
 517                           (V2DI "di")])
 518
 519 ;; Modes with twice the number of equal-sized elements.
 520 (define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI")
 521                             (V2SI "V4SI") (V4HF "V8HF")
 522                             (V2SF "V4SF") (DF "V2DF")
 523                             (DI "V2DI")])
 524
 525 ;; Same, but lower-case.
 526 (define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi")
 527                 (V2SI "v4si") (V2SF "v4sf")
 528                             (DI "v2di")])
 529
 530 ;; Modes with double-width elements.
 531 (define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI")
 532                   (V4HI "V2SI") (V8HI "V4SI")
 533                   (V2SI "DI")   (V4SI "V2DI")])
 534
 535 ;; Double-sized modes with the same element size.
 536 ;; Used for neon_vdup_lane, where the second operand is double-sized
 537 ;; even when the first one is quad.
 538 (define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI")
 539                                         (V4SI "V2SI") (V4SF "V2SF")
 540                                         (V8QI "V8QI") (V4HI "V4HI")
 541                                         (V2SI "V2SI") (V2SF "V2SF")
 542                                         (V8HF "V4HF") (V4HF "V4HF")])
 543
 544 ;; Mode of result of comparison operations (and bit-select operand 1).
 545 (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
 546                                 (V4HI "V4HI") (V8HI  "V8HI")
 547                                 (V2SI "V2SI") (V4SI  "V4SI")
 548                                 (V4HF "V4HI") (V8HF  "V8HI")
 549                                 (V2SF "V2SI") (V4SF  "V4SI")
 550                                 (DI   "DI")   (V2DI  "V2DI")])
 551
 552 (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi")
 553                                 (V4HI "v4hi") (V8HI  "v8hi")
 554                                 (V2SI "v2si") (V4SI  "v4si")
 555                                 (DI   "di")   (V2DI  "v2di")
 556                                 (V2SF "v2si") (V4SF  "v4si")])
 557
 558 ;; Get element type from double-width mode, for operations where we
 559 ;; don't care about signedness.
 560 (define_mode_attr V_if_elem [(V8QI "i8")  (V16QI "i8")
 561                              (V4HI "i16") (V8HI  "i16")
 562                              (V2SI "i32") (V4SI  "i32")
 563                              (DI   "i64") (V2DI  "i64")
 564                              (V2SF "f32") (V4SF  "f32")
 565                              (SF   "f32") (DF    "f64")
 566                              (HF   "f16") (V4HF  "f16")
 567                              (V8HF "f16")])
 568
 569 ;; Same, but for operations which work on signed values.
 570 (define_mode_attr V_s_elem [(V8QI "s8")  (V16QI "s8")
 571                             (V4HI "s16") (V8HI  "s16")
 572                             (V2SI "s32") (V4SI  "s32")
 573                             (DI   "s64") (V2DI  "s64")
 574                             (V2SF "f32") (V4SF  "f32")
 575                             (HF   "f16") (V4HF  "f16")
 576                             (V8HF "f16")])
 577
 578 ;; Same, but for operations which work on unsigned values.
 579 (define_mode_attr V_u_elem [(V8QI "u8")  (V16QI "u8")
 580                 (V4HI "u16") (V8HI  "u16")
 581                             (V2SI "u32") (V4SI  "u32")
 582                             (DI   "u64") (V2DI  "u64")
 583                             (V2SF "f32") (V4SF  "f32")])
 584
 585 ;; Element types for extraction of unsigned scalars.
 586 (define_mode_attr V_uf_sclr [(V8QI "u8")  (V16QI "u8")
 587                  (V4HI "u16") (V8HI "u16")
 588                              (V2SI "32") (V4SI "32")
 589                              (V4HF "u16") (V8HF "u16")
 590                              (V2SF "32") (V4SF "32")])
 591
 592 (define_mode_attr V_sz_elem [(V8QI "8")  (V16QI "8")
 593                              (V4HI "16") (V8HI  "16")
 594                              (V2SI "32") (V4SI  "32")
 595                              (DI   "64") (V2DI  "64")
 596                              (V4HF "16") (V8HF "16")
 597                              (V2SF "32") (V4SF  "32")])
 598
 599 (define_mode_attr V_elem_ch [(V8QI "b")  (V16QI "b")
 600                              (V4HI "h") (V8HI  "h")
 601                              (V2SI "s") (V4SI  "s")
 602                              (DI   "d") (V2DI  "d")
 603                              (V2SF "s") (V4SF  "s")
 604                              (V2SF "s") (V4SF  "s")])
 605
 606 (define_mode_attr VH_elem_ch [(V4HI "s") (V8HI  "s")
 607                               (V4HF "s") (V8HF  "s")
 608                               (HF "s")])
 609
 610 ;; Element sizes for duplicating ARM registers to all elements of a vector.
 611 (define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")])
 612
 613 ;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.)
 614 (define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI")
 615               (V4HI "TI") (V8HI  "OI")
 616                           (V2SI "TI") (V4SI  "OI")
 617                           (V2SF "TI") (V4SF  "OI")
 618                           (DI   "TI") (V2DI  "OI")])
 619
 620 ;; Same, but lower-case.
 621 (define_mode_attr V_pair [(V8QI "ti") (V16QI "oi")
 622               (V4HI "ti") (V8HI  "oi")
 623                           (V2SI "ti") (V4SI  "oi")
 624                           (V2SF "ti") (V4SF  "oi")
 625                           (DI   "ti") (V2DI  "oi")])
 626
 627 ;; Extra suffix on some 64-bit insn names (to avoid collision with standard
 628 ;; names which we don't want to define).
 629 (define_mode_attr V_suf64 [(V8QI "") (V16QI "")
 630                            (V4HI "") (V8HI "")
 631                            (V2SI "") (V4SI "")
 632                            (V2SF "") (V4SF "")
 633                            (DI "_neon") (V2DI "")])
 634
 635
 636 ;; Scalars to be presented to scalar multiplication instructions
 637 ;; must satisfy the following constraints.
 638 ;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7.
 639 ;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15.
 640
 641 ;; This mode attribute is used to obtain the correct register constraints.
 642
 643 (define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t")
 644                                          (V8HI "x") (V4SI "t") (V4SF "t")
 645                                          (V8HF "x") (V4HF "x")])
 646
 647 ;; Predicates used for setting type for neon instructions
 648
 649 (define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false")
 650                                  (V4HI "false") (V8HI "false")
 651                                  (V2SI "false") (V4SI "false")
 652                                  (V4HF "true") (V8HF "true")
 653                                  (V2SF "true") (V4SF "true")
 654                                  (DI "false") (V2DI "false")])
 655
 656 (define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true")
 657                                    (V4HI "true") (V8HI "true")
 658                                    (V2SI "false") (V4SI "false")
 659                                    (V2SF "false") (V4SF "false")
 660                                    (DI "false") (V2DI "false")])
 661
 662 (define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false")
 663                             (V4HI "true") (V8HI  "false")
 664                             (V2SI "true") (V4SI  "false")
 665                             (V2SF "true") (V4SF  "false")
 666                             (DI   "true") (V2DI  "false")
 667                             (V4HF "true") (V8HF  "false")])
 668
 669 (define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16")
 670                                  (V4HF "4") (V8HF "8")
 671                                  (V4HI "4") (V8HI "8")
 672                                  (V2SI "2") (V4SI "4")
 673                                  (V2SF "2") (V4SF "4")
 674                                  (DI "1")   (V2DI "2")
 675                                  (DF "1")   (V2DF "2")])
 676
 677 ;; Same as V_widen, but lower-case.
 678 (define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")])
 679
 680 ;; Widen. Result is half the number of elements, but widened to double-width.
 681 (define_mode_attr V_unpack   [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")])
 682
 683 ;; Conditions to be used in extend<mode>di patterns.
 684 (define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")])
 685 (define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6")
 686                                       (QI "&& arm_arch6")])
 687 (define_mode_attr qhs_zextenddi_op [(SI "s_register_operand")
 688                                    (HI "nonimmediate_operand")
 689                                    (QI "nonimmediate_operand")])
 690 (define_mode_attr qhs_extenddi_op [(SI "s_register_operand")
 691                                    (HI "nonimmediate_operand")
 692                                    (QI "arm_reg_or_extendqisi_mem_op")])
 693 (define_mode_attr qhs_extenddi_cstr [(SI "r,0,r,r,r") (HI "r,0,rm,rm,r") (QI "r,0,rUq,rm,r")])
 694 (define_mode_attr qhs_zextenddi_cstr [(SI "r,0,r,r") (HI "r,0,rm,r") (QI "r,0,rm,r")])
 695
 696 ;; Mode attributes used for fixed-point support.
 697 (define_mode_attr qaddsub_suf [(V4UQQ "8") (V2UHQ "16") (UQQ "8") (UHQ "16")
 698                                (V2UHA "16") (UHA "16")
 699                                (V4QQ "8") (V2HQ "16") (QQ "8") (HQ "16")
 700                                (V2HA "16") (HA "16") (SQ "") (SA "")])
 701
 702 ;; Mode attribute for vshll.
 703 (define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")])
 704
 705 ;; Mode attributes used for VFP support.
 706 (define_mode_attr F_constraint [(SF "t") (DF "w")])
 707 (define_mode_attr vfp_type [(SF "s") (DF "d")])
 708 (define_mode_attr vfp_double_cond [(SF "") (DF "&& TARGET_VFP_DOUBLE")])
 709
 710 ;; Mode attribute used to build the "type" attribute.
 711 (define_mode_attr q [(V8QI "") (V16QI "_q")
 712                      (V4HI "") (V8HI "_q")
 713                      (V2SI "") (V4SI "_q")
 714                      (V4HF "") (V8HF "_q")
 715                      (V2SF "") (V4SF "_q")
 716                      (V4HF "") (V8HF "_q")
 717                      (DI "")   (V2DI "_q")
 718                      (DF "")   (V2DF "_q")
 719                      (HF "")])
 720
 721 (define_mode_attr pf [(V8QI "p") (V16QI "p") (V2SF "f") (V4SF "f")])
 722
 723 ;;----------------------------------------------------------------------------
 724 ;; Code attributes
 725 ;;----------------------------------------------------------------------------
 726
 727 ;; Assembler mnemonics for vqh_ops and vqhs_ops iterators.
 728 (define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax")
 729                 (umin "vmin") (umax "vmax")])
 730
 731 ;; Type attributes for vqh_ops and vqhs_ops iterators.
 732 (define_code_attr VQH_type [(plus "add") (smin "minmax") (smax "minmax")
 733                 (umin "minmax") (umax "minmax")])
 734
 735 ;; Signs of above, where relevant.
 736 (define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u")
 737                 (umax "u")])
 738
 739 (define_code_attr cnb [(ltu "CC_C") (geu "CC")])
 740 (define_code_attr optab [(ltu "ltu") (geu "geu")])
 741
 742 ;; Assembler mnemonics for signedness of widening operations.
 743 (define_code_attr US [(sign_extend "s") (zero_extend "u")])
 744
 745 ;; Signedness suffix for float->fixed conversions.  Empty for signed
 746 ;; conversion.
 747 (define_code_attr su_optab [(fix "") (unsigned_fix "u")])
 748
 749 ;; Sign prefix to use in instruction type suffixes, i.e. s32, u32.
 750 (define_code_attr su [(fix "s") (unsigned_fix "u")])
 751
 752 ;; Right shifts
 753 (define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")])
 754 (define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")])
 755
 756 ;; String reprentations of operations on the sign of a number.
 757 (define_code_attr absneg_str [(abs "abs") (neg "neg")])
 758
 759 ;; Conversions.
 760 (define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")])
 761
 762 (define_code_attr float_sup [(unsigned_float "u") (float "s")])
 763
 764 (define_code_attr float_SUP [(unsigned_float "U") (float "S")])
 765
 766 ;;----------------------------------------------------------------------------
 767 ;; Int attributes
 768 ;;----------------------------------------------------------------------------
 769
 770 ;; Mapping between vector UNSPEC operations and the signed ('s'),
 771 ;; unsigned ('u'), poly ('p') or float ('f') nature of their data type.
 772 (define_int_attr sup [
 773   (UNSPEC_VADDL_S "s") (UNSPEC_VADDL_U "u")
 774   (UNSPEC_VADDW_S "s") (UNSPEC_VADDW_U "u")
 775   (UNSPEC_VRHADD_S "s") (UNSPEC_VRHADD_U "u")
 776   (UNSPEC_VHADD_S "s") (UNSPEC_VHADD_U "u")
 777   (UNSPEC_VQADD_S "s") (UNSPEC_VQADD_U "u")
 778   (UNSPEC_VMLAL_S "s") (UNSPEC_VMLAL_U "u")
 779   (UNSPEC_VMLAL_S_LANE "s") (UNSPEC_VMLAL_U_LANE "u")
 780   (UNSPEC_VMLSL_S "s") (UNSPEC_VMLSL_U "u")
 781   (UNSPEC_VMLSL_S_LANE "s") (UNSPEC_VMLSL_U_LANE "u")
 782   (UNSPEC_VMULL_S "s") (UNSPEC_VMULL_U "u") (UNSPEC_VMULL_P "p")
 783   (UNSPEC_VMULL_S_LANE "s") (UNSPEC_VMULL_U_LANE "u")
 784   (UNSPEC_VSUBL_S "s") (UNSPEC_VSUBL_U "u")
 785   (UNSPEC_VSUBW_S "s") (UNSPEC_VSUBW_U "u")
 786   (UNSPEC_VHSUB_S "s") (UNSPEC_VHSUB_U "u")
 787   (UNSPEC_VQSUB_S "s") (UNSPEC_VQSUB_U "u")
 788   (UNSPEC_VABD_S "s") (UNSPEC_VABD_U "u")
 789   (UNSPEC_VABDL_S "s") (UNSPEC_VABDL_U "u")
 790   (UNSPEC_VMAX "s") (UNSPEC_VMAX_U "u")
 791   (UNSPEC_VMIN "s") (UNSPEC_VMIN_U "u")
 792   (UNSPEC_VPADDL_S "s") (UNSPEC_VPADDL_U "u")
 793   (UNSPEC_VPADAL_S "s") (UNSPEC_VPADAL_U "u")
 794   (UNSPEC_VPMAX "s") (UNSPEC_VPMAX_U "u")
 795   (UNSPEC_VPMIN "s") (UNSPEC_VPMIN_U "u")
 796   (UNSPEC_VCVT_S "s") (UNSPEC_VCVT_U "u")
 797   (UNSPEC_VCVTA_S "s") (UNSPEC_VCVTA_U "u")
 798   (UNSPEC_VCVTM_S "s") (UNSPEC_VCVTM_U "u")
 799   (UNSPEC_VCVTN_S "s") (UNSPEC_VCVTN_U "u")
 800   (UNSPEC_VCVTP_S "s") (UNSPEC_VCVTP_U "u")
 801   (UNSPEC_VCVT_S_N "s") (UNSPEC_VCVT_U_N "u")
 802   (UNSPEC_VCVT_HF_S_N "s") (UNSPEC_VCVT_HF_U_N "u")
 803   (UNSPEC_VCVT_SI_S_N "s") (UNSPEC_VCVT_SI_U_N "u")
 804   (UNSPEC_VQMOVN_S "s") (UNSPEC_VQMOVN_U "u")
 805   (UNSPEC_VMOVL_S "s") (UNSPEC_VMOVL_U "u")
 806   (UNSPEC_VSHL_S "s") (UNSPEC_VSHL_U "u")
 807   (UNSPEC_VRSHL_S "s") (UNSPEC_VRSHL_U "u")
 808   (UNSPEC_VQSHL_S "s") (UNSPEC_VQSHL_U "u")
 809   (UNSPEC_VQRSHL_S "s") (UNSPEC_VQRSHL_U "u")
 810   (UNSPEC_VSHR_S_N "s") (UNSPEC_VSHR_U_N "u")
 811   (UNSPEC_VRSHR_S_N "s") (UNSPEC_VRSHR_U_N "u")
 812   (UNSPEC_VQSHRN_S_N "s") (UNSPEC_VQSHRN_U_N "u")
 813   (UNSPEC_VQRSHRN_S_N "s") (UNSPEC_VQRSHRN_U_N "u")
 814   (UNSPEC_VQSHL_S_N "s") (UNSPEC_VQSHL_U_N "u")
 815   (UNSPEC_VSHLL_S_N "s") (UNSPEC_VSHLL_U_N "u")
 816   (UNSPEC_VSRA_S_N "s") (UNSPEC_VSRA_U_N "u")
 817   (UNSPEC_VRSRA_S_N "s") (UNSPEC_VRSRA_U_N "u")
 818   (UNSPEC_VCVTH_S "s") (UNSPEC_VCVTH_U "u")
 819 ])
 820
 821 (define_int_attr vcvth_op
 822  [(UNSPEC_VCVTA_S "a") (UNSPEC_VCVTA_U "a")
 823   (UNSPEC_VCVTM_S "m") (UNSPEC_VCVTM_U "m")
 824   (UNSPEC_VCVTN_S "n") (UNSPEC_VCVTN_U "n")
 825   (UNSPEC_VCVTP_S "p") (UNSPEC_VCVTP_U "p")])
 826
 827 (define_int_attr fp16_rnd_str
 828   [(UNSPEC_VRND "rnd") (UNSPEC_VRNDA "rnda")
 829    (UNSPEC_VRNDM "rndm") (UNSPEC_VRNDN "rndn")
 830    (UNSPEC_VRNDP "rndp") (UNSPEC_VRNDX "rndx")])
 831
 832 (define_int_attr fp16_rnd_insn
 833   [(UNSPEC_VRND "vrintz") (UNSPEC_VRNDA "vrinta")
 834    (UNSPEC_VRNDM "vrintm") (UNSPEC_VRNDN "vrintn")
 835    (UNSPEC_VRNDP "vrintp") (UNSPEC_VRNDX "vrintx")])
 836
 837 (define_int_attr cmp_op_unsp [(UNSPEC_VCEQ "eq") (UNSPEC_VCGT "gt")
 838                               (UNSPEC_VCGE "ge") (UNSPEC_VCLE "le")
 839                               (UNSPEC_VCLT "lt") (UNSPEC_VCAGE "ge")
 840                               (UNSPEC_VCAGT "gt") (UNSPEC_VCALE "le")
 841                               (UNSPEC_VCALT "lt")])
 842
 843 (define_int_attr r [
 844   (UNSPEC_VRHADD_S "r") (UNSPEC_VRHADD_U "r")
 845   (UNSPEC_VHADD_S "") (UNSPEC_VHADD_U "")
 846   (UNSPEC_VADDHN "") (UNSPEC_VRADDHN "r")
 847   (UNSPEC_VQDMULH "") (UNSPEC_VQRDMULH "r")
 848   (UNSPEC_VQDMULH_LANE "") (UNSPEC_VQRDMULH_LANE "r")
 849   (UNSPEC_VSUBHN "") (UNSPEC_VRSUBHN "r")
 850 ])
 851
 852 (define_int_attr maxmin [
 853   (UNSPEC_VMAX "max") (UNSPEC_VMAX_U "max")
 854   (UNSPEC_VMIN "min") (UNSPEC_VMIN_U "min")
 855   (UNSPEC_VPMAX "max") (UNSPEC_VPMAX_U "max")
 856   (UNSPEC_VPMIN "min") (UNSPEC_VPMIN_U "min")
 857 ])
 858
 859 (define_int_attr fmaxmin [
 860   (UNSPEC_VMAXNM "fmax") (UNSPEC_VMINNM "fmin")])
 861
 862 (define_int_attr fmaxmin_op [
 863   (UNSPEC_VMAXNM "vmaxnm") (UNSPEC_VMINNM "vminnm")
 864 ])
 865
 866 (define_int_attr shift_op [
 867   (UNSPEC_VSHL_S "shl") (UNSPEC_VSHL_U "shl")
 868   (UNSPEC_VRSHL_S "rshl") (UNSPEC_VRSHL_U "rshl")
 869   (UNSPEC_VQSHL_S "qshl") (UNSPEC_VQSHL_U "qshl")
 870   (UNSPEC_VQRSHL_S "qrshl") (UNSPEC_VQRSHL_U "qrshl")
 871   (UNSPEC_VSHR_S_N "shr") (UNSPEC_VSHR_U_N "shr")
 872   (UNSPEC_VRSHR_S_N "rshr") (UNSPEC_VRSHR_U_N "rshr")
 873   (UNSPEC_VSHRN_N "shrn") (UNSPEC_VRSHRN_N "rshrn")
 874   (UNSPEC_VQRSHRN_S_N "qrshrn") (UNSPEC_VQRSHRN_U_N "qrshrn")
 875   (UNSPEC_VQSHRN_S_N "qshrn") (UNSPEC_VQSHRN_U_N "qshrn")
 876   (UNSPEC_VQSHRUN_N "qshrun") (UNSPEC_VQRSHRUN_N "qrshrun")
 877   (UNSPEC_VSRA_S_N "sra") (UNSPEC_VSRA_U_N "sra")
 878   (UNSPEC_VRSRA_S_N "rsra") (UNSPEC_VRSRA_U_N "rsra")
 879 ])
 880
 881 ;; Standard names for floating point to integral rounding instructions.
 882 (define_int_attr vrint_pattern [(UNSPEC_VRINTZ "btrunc") (UNSPEC_VRINTP "ceil")
 883                          (UNSPEC_VRINTA "round") (UNSPEC_VRINTM "floor")
 884                          (UNSPEC_VRINTR "nearbyint") (UNSPEC_VRINTX "rint")])
 885
 886 ;; Suffixes for vrint instructions specifying rounding modes.
 887 (define_int_attr vrint_variant [(UNSPEC_VRINTZ "z") (UNSPEC_VRINTP "p")
 888                                (UNSPEC_VRINTA "a") (UNSPEC_VRINTM "m")
 889                                (UNSPEC_VRINTR "r") (UNSPEC_VRINTX "x")])
 890
 891 ;; Some of the vrint instuctions are predicable.
 892 (define_int_attr vrint_predicable [(UNSPEC_VRINTZ "yes") (UNSPEC_VRINTP "no")
 893                                   (UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no")
 894                                   (UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")])
 895
 896 (define_int_attr vrint_conds [(UNSPEC_VRINTZ "nocond") (UNSPEC_VRINTP "unconditional")
 897                               (UNSPEC_VRINTA "unconditional") (UNSPEC_VRINTM "unconditional")
 898                               (UNSPEC_VRINTR "nocond") (UNSPEC_VRINTX "nocond")])
 899
 900 (define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p")
 901                                 (UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m")
 902                                 (UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")])
 903
 904 (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
 905                         (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32CB "crc32cb")
 906                         (UNSPEC_CRC32CH "crc32ch") (UNSPEC_CRC32CW "crc32cw")])
 907
 908 (define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
 909                         (UNSPEC_CRC32W "SI") (UNSPEC_CRC32CB "QI")
 910                         (UNSPEC_CRC32CH "HI") (UNSPEC_CRC32CW "SI")])
 911
 912 (define_int_attr crypto_pattern [(UNSPEC_SHA1H "sha1h") (UNSPEC_AESMC "aesmc")
 913                           (UNSPEC_AESIMC "aesimc") (UNSPEC_AESD "aesd")
 914                           (UNSPEC_AESE "aese") (UNSPEC_SHA1SU1 "sha1su1")
 915                           (UNSPEC_SHA256SU0 "sha256su0") (UNSPEC_SHA1C "sha1c")
 916                           (UNSPEC_SHA1M "sha1m") (UNSPEC_SHA1P "sha1p")
 917                           (UNSPEC_SHA1SU0 "sha1su0") (UNSPEC_SHA256H "sha256h")
 918                           (UNSPEC_SHA256H2 "sha256h2")
 919                           (UNSPEC_SHA256SU1 "sha256su1")])
 920
 921 (define_int_attr crypto_type
 922  [(UNSPEC_AESE "crypto_aese") (UNSPEC_AESD "crypto_aese")
 923  (UNSPEC_AESMC "crypto_aesmc") (UNSPEC_AESIMC "crypto_aesmc")
 924  (UNSPEC_SHA1C "crypto_sha1_slow") (UNSPEC_SHA1P "crypto_sha1_slow")
 925  (UNSPEC_SHA1M "crypto_sha1_slow") (UNSPEC_SHA1SU1 "crypto_sha1_fast")
 926  (UNSPEC_SHA1SU0 "crypto_sha1_xor") (UNSPEC_SHA256H "crypto_sha256_slow")
 927  (UNSPEC_SHA256H2 "crypto_sha256_slow") (UNSPEC_SHA256SU0 "crypto_sha256_fast")
 928  (UNSPEC_SHA256SU1 "crypto_sha256_slow")])
 929
 930 (define_int_attr crypto_size_sfx [(UNSPEC_SHA1H "32") (UNSPEC_AESMC "8")
 931                           (UNSPEC_AESIMC "8") (UNSPEC_AESD "8")
 932                           (UNSPEC_AESE "8") (UNSPEC_SHA1SU1 "32")
 933                           (UNSPEC_SHA256SU0 "32") (UNSPEC_SHA1C "32")
 934                           (UNSPEC_SHA1M "32") (UNSPEC_SHA1P "32")
 935                           (UNSPEC_SHA1SU0 "32") (UNSPEC_SHA256H "32")
 936                           (UNSPEC_SHA256H2 "32") (UNSPEC_SHA256SU1 "32")])
 937
 938 (define_int_attr crypto_mode [(UNSPEC_SHA1H "V4SI") (UNSPEC_AESMC "V16QI")
 939                           (UNSPEC_AESIMC "V16QI") (UNSPEC_AESD "V16QI")
 940                           (UNSPEC_AESE "V16QI") (UNSPEC_SHA1SU1 "V4SI")
 941                           (UNSPEC_SHA256SU0 "V4SI") (UNSPEC_SHA1C "V4SI")
 942                           (UNSPEC_SHA1M "V4SI") (UNSPEC_SHA1P "V4SI")
 943                           (UNSPEC_SHA1SU0 "V4SI") (UNSPEC_SHA256H "V4SI")
 944                           (UNSPEC_SHA256H2 "V4SI") (UNSPEC_SHA256SU1 "V4SI")])
 945
 946 ;; Both kinds of return insn.
 947 (define_code_iterator RETURNS [return simple_return])
 948 (define_code_attr return_str [(return "") (simple_return "simple_")])
 949 (define_code_attr return_simple_p [(return "false") (simple_return "true")])
 950 (define_code_attr return_cond_false [(return " && USE_RETURN_INSN (FALSE)")
 951                                (simple_return " && use_simple_return_p ()")])
 952 (define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)")
 953                                (simple_return " && use_simple_return_p ()")])
 954
 955 ;; Attributes for VQRDMLAH/VQRDMLSH
 956 (define_int_attr neon_rdma_as [(UNSPEC_VQRDMLAH "a") (UNSPEC_VQRDMLSH "s")])
 957
 958 ;; Attributes for VFMA_LANE/ VFMS_LANE
 959 (define_int_attr neon_vfm_lane_as
 960  [(UNSPEC_VFMA_LANE "a") (UNSPEC_VFMS_LANE "s")])
 961
 962 ;; An iterator for the CDP coprocessor instructions
 963 (define_int_iterator CDPI [VUNSPEC_CDP VUNSPEC_CDP2])
 964 (define_int_attr cdp [(VUNSPEC_CDP "cdp") (VUNSPEC_CDP2 "cdp2")])
 965 (define_int_attr CDP [(VUNSPEC_CDP "CDP") (VUNSPEC_CDP2 "CDP2")])
 966
 967 ;; An iterator for the LDC coprocessor instruction
 968 (define_int_iterator LDCI [VUNSPEC_LDC VUNSPEC_LDC2
 969                            VUNSPEC_LDCL VUNSPEC_LDC2L])
 970 (define_int_attr ldc [(VUNSPEC_LDC "ldc") (VUNSPEC_LDC2 "ldc2")
 971                       (VUNSPEC_LDCL "ldcl") (VUNSPEC_LDC2L "ldc2l")])
 972 (define_int_attr LDC [(VUNSPEC_LDC "LDC") (VUNSPEC_LDC2 "LDC2")
 973                       (VUNSPEC_LDCL "LDCL") (VUNSPEC_LDC2L "LDC2L")])
 974
 975 ;; An iterator for the STC coprocessor instructions
 976 (define_int_iterator STCI [VUNSPEC_STC VUNSPEC_STC2
 977                            VUNSPEC_STCL VUNSPEC_STC2L])
 978 (define_int_attr stc [(VUNSPEC_STC "stc") (VUNSPEC_STC2 "stc2")
 979                       (VUNSPEC_STCL "stcl") (VUNSPEC_STC2L "stc2l")])
 980 (define_int_attr STC [(VUNSPEC_STC "STC") (VUNSPEC_STC2 "STC2")
 981                       (VUNSPEC_STCL "STCL") (VUNSPEC_STC2L "STC2L")])
 982
 983 ;; An iterator for the MCR coprocessor instructions
 984 (define_int_iterator MCRI [VUNSPEC_MCR VUNSPEC_MCR2])
 985
 986 (define_int_attr mcr [(VUNSPEC_MCR "mcr") (VUNSPEC_MCR2 "mcr2")])
 987 (define_int_attr MCR [(VUNSPEC_MCR "MCR") (VUNSPEC_MCR2 "MCR2")])
 988
 989 ;; An iterator for the MRC coprocessor instructions
 990 (define_int_iterator MRCI [VUNSPEC_MRC VUNSPEC_MRC2])
 991
 992 (define_int_attr mrc [(VUNSPEC_MRC "mrc") (VUNSPEC_MRC2 "mrc2")])
 993 (define_int_attr MRC [(VUNSPEC_MRC "MRC") (VUNSPEC_MRC2 "MRC2")])
 994
 995 ;; An iterator for the MCRR coprocessor instructions
 996 (define_int_iterator MCRRI [VUNSPEC_MCRR VUNSPEC_MCRR2])
 997
 998 (define_int_attr mcrr [(VUNSPEC_MCRR "mcrr") (VUNSPEC_MCRR2 "mcrr2")])
 999 (define_int_attr MCRR [(VUNSPEC_MCRR "MCRR") (VUNSPEC_MCRR2 "MCRR2")])
1000
1001 ;; An iterator for the MRRC coprocessor instructions
1002 (define_int_iterator MRRCI [VUNSPEC_MRRC VUNSPEC_MRRC2])
1003
1004 (define_int_attr mrrc [(VUNSPEC_MRRC "mrrc") (VUNSPEC_MRRC2 "mrrc2")])
1005 (define_int_attr MRRC [(VUNSPEC_MRRC "MRRC") (VUNSPEC_MRRC2 "MRRC2")])