1 ;; Predicate definitions for ARM and Thumb
2 ;; Copyright (C) 2004, 2007, 2008, 2010 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_predicate "s_register_operand"
22 (match_code "reg,subreg")
24 if (GET_CODE (op) == SUBREG)
26 /* We don't consider registers whose class is NO_REGS
27 to be a register operand. */
28 /* XXX might have to check for lo regs only for thumb ??? */
29 return (GET_CODE (op) == REG
30 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
31 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
35 (define_predicate "arm_hard_register_operand"
38 return REGNO (op) < FIRST_PSEUDO_REGISTER;
42 (define_predicate "low_register_operand"
43 (and (match_code "reg")
44 (match_test "REGNO (op) <= LAST_LO_REGNUM")))
46 ;; A low register or const_int.
47 (define_predicate "low_reg_or_int_operand"
48 (ior (match_code "const_int")
49 (match_operand 0 "low_register_operand")))
51 ;; Any core register, or any pseudo. */
52 (define_predicate "arm_general_register_operand"
53 (match_code "reg,subreg")
55 if (GET_CODE (op) == SUBREG)
58 return (GET_CODE (op) == REG
59 && (REGNO (op) <= LAST_ARM_REGNUM
60 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
63 (define_predicate "f_register_operand"
64 (match_code "reg,subreg")
66 if (GET_CODE (op) == SUBREG)
69 /* We don't consider registers whose class is NO_REGS
70 to be a register operand. */
71 return (GET_CODE (op) == REG
72 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
73 || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
76 (define_predicate "vfp_register_operand"
77 (match_code "reg,subreg")
79 if (GET_CODE (op) == SUBREG)
82 /* We don't consider registers whose class is NO_REGS
83 to be a register operand. */
84 return (GET_CODE (op) == REG
85 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
86 || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS
87 || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS
89 && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS)));
92 (define_special_predicate "subreg_lowpart_operator"
93 (and (match_code "subreg")
94 (match_test "subreg_lowpart_p (op)")))
96 ;; Reg, subreg(reg) or const_int.
97 (define_predicate "reg_or_int_operand"
98 (ior (match_code "const_int")
99 (match_operand 0 "s_register_operand")))
101 (define_predicate "arm_immediate_operand"
102 (and (match_code "const_int")
103 (match_test "const_ok_for_arm (INTVAL (op))")))
105 ;; A constant value which fits into two instructions, each taking
106 ;; an arithmetic constant operand for one of the words.
107 (define_predicate "arm_immediate_di_operand"
108 (and (match_code "const_int,const_double")
109 (match_test "arm_const_double_by_immediates (op)")))
111 (define_predicate "arm_neg_immediate_operand"
112 (and (match_code "const_int")
113 (match_test "const_ok_for_arm (-INTVAL (op))")))
115 (define_predicate "arm_not_immediate_operand"
116 (and (match_code "const_int")
117 (match_test "const_ok_for_arm (~INTVAL (op))")))
119 (define_predicate "const0_operand"
120 (and (match_code "const_int")
121 (match_test "INTVAL (op) == 0")))
123 ;; Something valid on the RHS of an ARM data-processing instruction
124 (define_predicate "arm_rhs_operand"
125 (ior (match_operand 0 "s_register_operand")
126 (match_operand 0 "arm_immediate_operand")))
128 (define_predicate "arm_rhsm_operand"
129 (ior (match_operand 0 "arm_rhs_operand")
130 (match_operand 0 "memory_operand")))
132 (define_predicate "shift_amount_operand"
133 (ior (and (match_test "TARGET_ARM")
134 (match_operand 0 "s_register_operand"))
135 (and (match_code "const_int")
136 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 32"))))
138 (define_predicate "arm_add_operand"
139 (ior (match_operand 0 "arm_rhs_operand")
140 (match_operand 0 "arm_neg_immediate_operand")))
142 (define_predicate "arm_addimm_operand"
143 (ior (match_operand 0 "arm_immediate_operand")
144 (match_operand 0 "arm_neg_immediate_operand")))
146 (define_predicate "arm_not_operand"
147 (ior (match_operand 0 "arm_rhs_operand")
148 (match_operand 0 "arm_not_immediate_operand")))
150 (define_predicate "arm_di_operand"
151 (ior (match_operand 0 "s_register_operand")
152 (match_operand 0 "arm_immediate_di_operand")))
154 ;; True if the operand is a memory reference which contains an
155 ;; offsettable address.
156 (define_predicate "offsettable_memory_operand"
157 (and (match_code "mem")
159 "offsettable_address_p (reload_completed | reload_in_progress,
160 mode, XEXP (op, 0))")))
162 ;; True if the operand is a memory operand that does not have an
163 ;; automodified base register (and thus will not generate output reloads).
164 (define_predicate "call_memory_operand"
165 (and (match_code "mem")
166 (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0)))
168 (match_operand 0 "memory_operand"))))
170 (define_predicate "arm_reload_memory_operand"
171 (and (match_code "mem,reg,subreg")
172 (match_test "(!CONSTANT_P (op)
173 && (true_regnum(op) == -1
174 || (GET_CODE (op) == REG
175 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
177 ;; True for valid operands for the rhs of an floating point insns.
178 ;; Allows regs or certain consts on FPA, just regs for everything else.
179 (define_predicate "arm_float_rhs_operand"
180 (ior (match_operand 0 "s_register_operand")
181 (and (match_code "const_double")
182 (match_test "TARGET_FPA && arm_const_double_rtx (op)"))))
184 (define_predicate "arm_float_add_operand"
185 (ior (match_operand 0 "arm_float_rhs_operand")
186 (and (match_code "const_double")
187 (match_test "TARGET_FPA && neg_const_double_rtx_ok_for_fpa (op)"))))
189 (define_predicate "vfp_compare_operand"
190 (ior (match_operand 0 "s_register_operand")
191 (and (match_code "const_double")
192 (match_test "arm_const_double_rtx (op)"))))
194 (define_predicate "arm_float_compare_operand"
195 (if_then_else (match_test "TARGET_VFP")
196 (match_operand 0 "vfp_compare_operand")
197 (match_operand 0 "arm_float_rhs_operand")))
199 ;; True for valid index operands.
200 (define_predicate "index_operand"
201 (ior (match_operand 0 "s_register_operand")
202 (and (match_operand 0 "immediate_operand")
203 (match_test "(GET_CODE (op) != CONST_INT
204 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))
206 ;; True for operators that can be combined with a shift in ARM state.
207 (define_special_predicate "shiftable_operator"
208 (and (match_code "plus,minus,ior,xor,and")
209 (match_test "mode == GET_MODE (op)")))
211 ;; True for logical binary operators.
212 (define_special_predicate "logical_binary_operator"
213 (and (match_code "ior,xor,and")
214 (match_test "mode == GET_MODE (op)")))
216 ;; True for commutative operators
217 (define_special_predicate "commutative_binary_operator"
218 (and (match_code "ior,xor,and,plus")
219 (match_test "mode == GET_MODE (op)")))
221 ;; True for shift operators.
222 (define_special_predicate "shift_operator"
223 (and (ior (ior (and (match_code "mult")
224 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
225 (and (match_code "rotate")
226 (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
227 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
228 (match_code "ashift,ashiftrt,lshiftrt,rotatert"))
229 (match_test "mode == GET_MODE (op)")))
231 ;; True for shift operators which can be used with saturation instructions.
232 (define_special_predicate "sat_shift_operator"
233 (and (match_code "ashift,ashiftrt")
234 (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
235 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) <= 32)")
236 (match_test "mode == GET_MODE (op)")))
238 ;; True for MULT, to identify which variant of shift_operator is in use.
239 (define_special_predicate "mult_operator"
242 ;; True for operators that have 16-bit thumb variants. */
243 (define_special_predicate "thumb_16bit_operator"
244 (match_code "plus,minus,and,ior,xor"))
247 (define_special_predicate "equality_operator"
248 (match_code "eq,ne"))
250 ;; True for integer comparisons and, if FP is active, for comparisons
251 ;; other than LTGT or UNEQ.
252 (define_special_predicate "expandable_comparison_operator"
253 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
254 unordered,ordered,unlt,unle,unge,ungt"))
256 ;; Likewise, but only accept comparisons that are directly supported
257 ;; by ARM condition codes.
258 (define_special_predicate "arm_comparison_operator"
259 (and (match_operand 0 "expandable_comparison_operator")
260 (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
262 (define_special_predicate "lt_ge_comparison_operator"
263 (match_code "lt,ge"))
265 (define_special_predicate "noov_comparison_operator"
266 (match_code "lt,ge,eq,ne"))
268 (define_special_predicate "minmax_operator"
269 (and (match_code "smin,smax,umin,umax")
270 (match_test "mode == GET_MODE (op)")))
272 (define_special_predicate "cc_register"
273 (and (match_code "reg")
274 (and (match_test "REGNO (op) == CC_REGNUM")
275 (ior (match_test "mode == GET_MODE (op)")
276 (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))))
278 (define_special_predicate "dominant_cc_register"
281 if (mode == VOIDmode)
283 mode = GET_MODE (op);
285 if (GET_MODE_CLASS (mode) != MODE_CC)
289 return (cc_register (op, mode)
290 && (mode == CC_DNEmode
291 || mode == CC_DEQmode
292 || mode == CC_DLEmode
293 || mode == CC_DLTmode
294 || mode == CC_DGEmode
295 || mode == CC_DGTmode
296 || mode == CC_DLEUmode
297 || mode == CC_DLTUmode
298 || mode == CC_DGEUmode
299 || mode == CC_DGTUmode));
302 (define_special_predicate "arm_extendqisi_mem_op"
303 (and (match_operand 0 "memory_operand")
304 (match_test "arm_legitimate_address_outer_p (mode, XEXP (op, 0),
307 (define_special_predicate "arm_reg_or_extendqisi_mem_op"
308 (ior (match_operand 0 "arm_extendqisi_mem_op")
309 (match_operand 0 "s_register_operand")))
311 (define_predicate "power_of_two_operand"
312 (match_code "const_int")
314 unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff;
316 return value != 0 && (value & (value - 1)) == 0;
319 (define_predicate "nonimmediate_di_operand"
320 (match_code "reg,subreg,mem")
322 if (s_register_operand (op, mode))
325 if (GET_CODE (op) == SUBREG)
326 op = SUBREG_REG (op);
328 return GET_CODE (op) == MEM && memory_address_p (DImode, XEXP (op, 0));
331 (define_predicate "di_operand"
332 (ior (match_code "const_int,const_double")
333 (and (match_code "reg,subreg,mem")
334 (match_operand 0 "nonimmediate_di_operand"))))
336 (define_predicate "nonimmediate_soft_df_operand"
337 (match_code "reg,subreg,mem")
339 if (s_register_operand (op, mode))
342 if (GET_CODE (op) == SUBREG)
343 op = SUBREG_REG (op);
345 return GET_CODE (op) == MEM && memory_address_p (DFmode, XEXP (op, 0));
348 (define_predicate "soft_df_operand"
349 (ior (match_code "const_double")
350 (and (match_code "reg,subreg,mem")
351 (match_operand 0 "nonimmediate_soft_df_operand"))))
353 (define_special_predicate "load_multiple_operation"
354 (match_code "parallel")
356 HOST_WIDE_INT count = XVECLEN (op, 0);
359 HOST_WIDE_INT i = 1, base = 0;
360 HOST_WIDE_INT offset = 0;
362 bool addr_reg_loaded = false;
366 || GET_CODE (XVECEXP (op, 0, 0)) != SET
367 || !REG_P (SET_DEST (XVECEXP (op, 0, 0))))
370 /* Check to see if this might be a write-back. */
371 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
377 /* Now check it more carefully. */
378 if (GET_CODE (SET_DEST (elt)) != REG
379 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
380 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
381 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
385 /* Perform a quick check so we don't blow up below. */
387 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
388 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
389 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
392 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
393 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
394 if (GET_CODE (src_addr) == PLUS)
396 if (GET_CODE (XEXP (src_addr, 1)) != CONST_INT)
398 offset = INTVAL (XEXP (src_addr, 1));
399 src_addr = XEXP (src_addr, 0);
401 if (!REG_P (src_addr))
404 for (; i < count; i++)
406 elt = XVECEXP (op, 0, i);
408 if (GET_CODE (elt) != SET
409 || GET_CODE (SET_DEST (elt)) != REG
410 || GET_MODE (SET_DEST (elt)) != SImode
411 || REGNO (SET_DEST (elt)) <= dest_regno
412 || GET_CODE (SET_SRC (elt)) != MEM
413 || GET_MODE (SET_SRC (elt)) != SImode
414 || ((GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
415 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
416 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
417 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != offset + (i - base) * 4)
418 && (!REG_P (XEXP (SET_SRC (elt), 0))
419 || offset + (i - base) * 4 != 0)))
421 dest_regno = REGNO (SET_DEST (elt));
422 if (dest_regno == REGNO (src_addr))
423 addr_reg_loaded = true;
425 /* For Thumb, we only have updating instructions. If the pattern does
426 not describe an update, it must be because the address register is
427 in the list of loaded registers - on the hardware, this has the effect
428 of overriding the update. */
429 if (update && addr_reg_loaded)
432 return update || addr_reg_loaded;
436 (define_special_predicate "store_multiple_operation"
437 (match_code "parallel")
439 HOST_WIDE_INT count = XVECLEN (op, 0);
442 HOST_WIDE_INT i = 1, base = 0, offset = 0;
446 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
449 /* Check to see if this might be a write-back. */
450 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
455 /* Now check it more carefully. */
456 if (GET_CODE (SET_DEST (elt)) != REG
457 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
458 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
459 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
463 /* Perform a quick check so we don't blow up below. */
465 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
466 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
467 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
470 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
471 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
473 if (GET_CODE (dest_addr) == PLUS)
475 if (GET_CODE (XEXP (dest_addr, 1)) != CONST_INT)
477 offset = INTVAL (XEXP (dest_addr, 1));
478 dest_addr = XEXP (dest_addr, 0);
480 if (!REG_P (dest_addr))
483 for (; i < count; i++)
485 elt = XVECEXP (op, 0, i);
487 if (GET_CODE (elt) != SET
488 || GET_CODE (SET_SRC (elt)) != REG
489 || GET_MODE (SET_SRC (elt)) != SImode
490 || REGNO (SET_SRC (elt)) <= src_regno
491 || GET_CODE (SET_DEST (elt)) != MEM
492 || GET_MODE (SET_DEST (elt)) != SImode
493 || ((GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
494 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
495 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
496 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != offset + (i - base) * 4)
497 && (!REG_P (XEXP (SET_DEST (elt), 0))
498 || offset + (i - base) * 4 != 0)))
500 src_regno = REGNO (SET_SRC (elt));
506 (define_special_predicate "multi_register_push"
507 (match_code "parallel")
509 if ((GET_CODE (XVECEXP (op, 0, 0)) != SET)
510 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
511 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
517 (define_predicate "push_mult_memory_operand"
520 /* ??? Given how PUSH_MULT is generated in the prologues, is there
521 any point in testing for thumb1 specially? All of the variants
522 use the same form. */
525 /* ??? No attempt is made to represent STMIA, or validate that
526 the stack adjustment matches the register count. This is
527 true of the ARM/Thumb2 path as well. */
528 rtx x = XEXP (op, 0);
529 if (GET_CODE (x) != PRE_MODIFY)
531 if (XEXP (x, 0) != stack_pointer_rtx)
534 if (GET_CODE (x) != PLUS)
536 if (XEXP (x, 0) != stack_pointer_rtx)
538 return CONST_INT_P (XEXP (x, 1));
541 /* ARM and Thumb2 handle pre-modify in their legitimate_address. */
542 return memory_operand (op, mode);
545 ;;-------------------------------------------------------------------------
550 (define_predicate "thumb1_cmp_operand"
551 (ior (and (match_code "reg,subreg")
552 (match_operand 0 "s_register_operand"))
553 (and (match_code "const_int")
554 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256"))))
556 (define_predicate "thumb1_cmpneg_operand"
557 (and (match_code "const_int")
558 (match_test "INTVAL (op) < 0 && INTVAL (op) > -256")))
560 ;; Return TRUE if a result can be stored in OP without clobbering the
561 ;; condition code register. Prior to reload we only accept a
562 ;; register. After reload we have to be able to handle memory as
563 ;; well, since a pseudo may not get a hard reg and reload cannot
564 ;; handle output-reloads on jump insns.
566 ;; We could possibly handle mem before reload as well, but that might
567 ;; complicate things with the need to handle increment
569 (define_predicate "thumb_cbrch_target_operand"
570 (and (match_code "reg,subreg,mem")
571 (ior (match_operand 0 "s_register_operand")
572 (and (match_test "reload_in_progress || reload_completed")
573 (match_operand 0 "memory_operand")))))
575 ;;-------------------------------------------------------------------------
577 ;; MAVERICK predicates
580 (define_predicate "cirrus_register_operand"
581 (match_code "reg,subreg")
583 if (GET_CODE (op) == SUBREG)
584 op = SUBREG_REG (op);
586 return (GET_CODE (op) == REG
587 && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
588 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
591 (define_predicate "cirrus_fp_register"
592 (match_code "reg,subreg")
594 if (GET_CODE (op) == SUBREG)
595 op = SUBREG_REG (op);
597 return (GET_CODE (op) == REG
598 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
599 || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
602 (define_predicate "cirrus_shift_const"
603 (and (match_code "const_int")
604 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 64")))
609 (define_predicate "const_multiple_of_8_operand"
610 (match_code "const_int")
612 unsigned HOST_WIDE_INT val = INTVAL (op);
613 return (val & 7) == 0;
616 (define_predicate "imm_for_neon_mov_operand"
617 (match_code "const_vector")
619 return neon_immediate_valid_for_move (op, mode, NULL, NULL);
622 (define_predicate "imm_for_neon_lshift_operand"
623 (match_code "const_vector")
625 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true);
628 (define_predicate "imm_for_neon_rshift_operand"
629 (match_code "const_vector")
631 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false);
634 (define_predicate "imm_lshift_or_reg_neon"
635 (ior (match_operand 0 "s_register_operand")
636 (match_operand 0 "imm_for_neon_lshift_operand")))
638 (define_predicate "imm_rshift_or_reg_neon"
639 (ior (match_operand 0 "s_register_operand")
640 (match_operand 0 "imm_for_neon_rshift_operand")))
642 (define_predicate "imm_for_neon_logic_operand"
643 (match_code "const_vector")
646 && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL));
649 (define_predicate "imm_for_neon_inv_logic_operand"
650 (match_code "const_vector")
653 && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL));
656 (define_predicate "neon_logic_op2"
657 (ior (match_operand 0 "imm_for_neon_logic_operand")
658 (match_operand 0 "s_register_operand")))
660 (define_predicate "neon_inv_logic_op2"
661 (ior (match_operand 0 "imm_for_neon_inv_logic_operand")
662 (match_operand 0 "s_register_operand")))
664 ;; TODO: We could check lane numbers more precisely based on the mode.
665 (define_predicate "neon_lane_number"
666 (and (match_code "const_int")
667 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 15")))
668 ;; Predicates for named expanders that overlap multiple ISAs.
670 (define_predicate "cmpdi_operand"
671 (if_then_else (match_test "TARGET_HARD_FLOAT && TARGET_MAVERICK")
672 (and (match_test "TARGET_ARM")
673 (match_operand 0 "cirrus_fp_register"))
674 (and (match_test "TARGET_32BIT")
675 (match_operand 0 "arm_di_operand"))))
677 ;; True if the operand is memory reference suitable for a ldrex/strex.
678 (define_predicate "arm_sync_memory_operand"
679 (and (match_operand 0 "memory_operand")
680 (match_code "reg" "0")))
682 ;; Predicates for parallel expanders based on mode.
683 (define_special_predicate "vect_par_constant_high"
684 (match_code "parallel")
686 HOST_WIDE_INT count = XVECLEN (op, 0);
688 int base = GET_MODE_NUNITS (mode);
691 || (count != base/2))
694 if (!VECTOR_MODE_P (mode))
697 for (i = 0; i < count; i++)
699 rtx elt = XVECEXP (op, 0, i);
702 if (GET_CODE (elt) != CONST_INT)
706 if (val != (base/2) + i)
712 (define_special_predicate "vect_par_constant_low"
713 (match_code "parallel")
715 HOST_WIDE_INT count = XVECLEN (op, 0);
717 int base = GET_MODE_NUNITS (mode);
720 || (count != base/2))
723 if (!VECTOR_MODE_P (mode))
726 for (i = 0; i < count; i++)
728 rtx elt = XVECEXP (op, 0, i);
731 if (GET_CODE (elt) != CONST_INT)
741 (define_predicate "neon_struct_operand"
742 (and (match_code "mem")
743 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
745 (define_predicate "neon_struct_or_register_operand"
746 (ior (match_operand 0 "neon_struct_operand")
747 (match_operand 0 "s_register_operand")))
749 (define_special_predicate "add_operator"