gcc/config/arm/predicates.md

   1 ;; Predicate definitions for ARM and Thumb
   2 ;; Copyright (C) 2004, 2007, 2008, 2010 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_predicate "s_register_operand"
  22   (match_code "reg,subreg")
  23 {
  24   if (GET_CODE (op) == SUBREG)
  25     op = SUBREG_REG (op);
  26   /* We don't consider registers whose class is NO_REGS
  27      to be a register operand.  */
  28   /* XXX might have to check for lo regs only for thumb ??? */
  29   return (GET_CODE (op) == REG
  30           && (REGNO (op) >= FIRST_PSEUDO_REGISTER
  31               || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
  32 })
  33
  34 ;; Any hard register.
  35 (define_predicate "arm_hard_register_operand"
  36   (match_code "reg")
  37 {
  38   return REGNO (op) < FIRST_PSEUDO_REGISTER;
  39 })
  40
  41 ;; A low register.
  42 (define_predicate "low_register_operand"
  43   (and (match_code "reg")
  44        (match_test "REGNO (op) <= LAST_LO_REGNUM")))
  45
  46 ;; A low register or const_int.
  47 (define_predicate "low_reg_or_int_operand"
  48   (ior (match_code "const_int")
  49        (match_operand 0 "low_register_operand")))
  50
  51 ;; Any core register, or any pseudo.  */
  52 (define_predicate "arm_general_register_operand"
  53   (match_code "reg,subreg")
  54 {
  55   if (GET_CODE (op) == SUBREG)
  56     op = SUBREG_REG (op);
  57
  58   return (GET_CODE (op) == REG
  59           && (REGNO (op) <= LAST_ARM_REGNUM
  60               || REGNO (op) >= FIRST_PSEUDO_REGISTER));
  61 })
  62
  63 (define_predicate "f_register_operand"
  64   (match_code "reg,subreg")
  65 {
  66   if (GET_CODE (op) == SUBREG)
  67     op = SUBREG_REG (op);
  68
  69   /* We don't consider registers whose class is NO_REGS
  70      to be a register operand.  */
  71   return (GET_CODE (op) == REG
  72           && (REGNO (op) >= FIRST_PSEUDO_REGISTER
  73               || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
  74 })
  75
  76 (define_predicate "vfp_register_operand"
  77   (match_code "reg,subreg")
  78 {
  79   if (GET_CODE (op) == SUBREG)
  80     op = SUBREG_REG (op);
  81
  82   /* We don't consider registers whose class is NO_REGS
  83      to be a register operand.  */
  84   return (GET_CODE (op) == REG
  85           && (REGNO (op) >= FIRST_PSEUDO_REGISTER
  86               || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS
  87               || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS
  88               || (TARGET_VFPD32
  89                   && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS)));
  90 })
  91
  92 (define_special_predicate "subreg_lowpart_operator"
  93   (and (match_code "subreg")
  94        (match_test "subreg_lowpart_p (op)")))
  95
  96 ;; Reg, subreg(reg) or const_int.
  97 (define_predicate "reg_or_int_operand"
  98   (ior (match_code "const_int")
  99        (match_operand 0 "s_register_operand")))
 100
 101 (define_predicate "arm_immediate_operand"
 102   (and (match_code "const_int")
 103        (match_test "const_ok_for_arm (INTVAL (op))")))
 104
 105 ;; A constant value which fits into two instructions, each taking
 106 ;; an arithmetic constant operand for one of the words.
 107 (define_predicate "arm_immediate_di_operand"
 108   (and (match_code "const_int,const_double")
 109        (match_test "arm_const_double_by_immediates (op)")))
 110
 111 (define_predicate "arm_neg_immediate_operand"
 112   (and (match_code "const_int")
 113        (match_test "const_ok_for_arm (-INTVAL (op))")))
 114
 115 (define_predicate "arm_not_immediate_operand"
 116   (and (match_code "const_int")
 117        (match_test "const_ok_for_arm (~INTVAL (op))")))
 118
 119 (define_predicate "const0_operand"
 120   (and (match_code "const_int")
 121        (match_test "INTVAL (op) == 0")))
 122
 123 ;; Something valid on the RHS of an ARM data-processing instruction
 124 (define_predicate "arm_rhs_operand"
 125   (ior (match_operand 0 "s_register_operand")
 126        (match_operand 0 "arm_immediate_operand")))
 127
 128 (define_predicate "arm_rhsm_operand"
 129   (ior (match_operand 0 "arm_rhs_operand")
 130        (match_operand 0 "memory_operand")))
 131
 132 (define_predicate "shift_amount_operand"
 133   (ior (and (match_test "TARGET_ARM")
 134             (match_operand 0 "s_register_operand"))
 135        (and (match_code "const_int")
 136             (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 32"))))
 137
 138 (define_predicate "arm_add_operand"
 139   (ior (match_operand 0 "arm_rhs_operand")
 140        (match_operand 0 "arm_neg_immediate_operand")))
 141
 142 (define_predicate "arm_addimm_operand"
 143   (ior (match_operand 0 "arm_immediate_operand")
 144        (match_operand 0 "arm_neg_immediate_operand")))
 145
 146 (define_predicate "arm_not_operand"
 147   (ior (match_operand 0 "arm_rhs_operand")
 148        (match_operand 0 "arm_not_immediate_operand")))
 149
 150 (define_predicate "arm_di_operand"
 151   (ior (match_operand 0 "s_register_operand")
 152        (match_operand 0 "arm_immediate_di_operand")))
 153
 154 ;; True if the operand is a memory reference which contains an
 155 ;; offsettable address.
 156 (define_predicate "offsettable_memory_operand"
 157   (and (match_code "mem")
 158        (match_test
 159         "offsettable_address_p (reload_completed | reload_in_progress,
 160                                 mode, XEXP (op, 0))")))
 161
 162 ;; True if the operand is a memory operand that does not have an
 163 ;; automodified base register (and thus will not generate output reloads).
 164 (define_predicate "call_memory_operand"
 165   (and (match_code "mem")
 166        (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0)))
 167                          != RTX_AUTOINC")
 168             (match_operand 0 "memory_operand"))))
 169
 170 (define_predicate "arm_reload_memory_operand"
 171   (and (match_code "mem,reg,subreg")
 172        (match_test "(!CONSTANT_P (op)
 173                      && (true_regnum(op) == -1
 174                          || (GET_CODE (op) == REG
 175                              && REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
 176
 177 ;; True for valid operands for the rhs of an floating point insns.
 178 ;;   Allows regs or certain consts on FPA, just regs for everything else.
 179 (define_predicate "arm_float_rhs_operand"
 180   (ior (match_operand 0 "s_register_operand")
 181        (and (match_code "const_double")
 182             (match_test "TARGET_FPA && arm_const_double_rtx (op)"))))
 183
 184 (define_predicate "arm_float_add_operand"
 185   (ior (match_operand 0 "arm_float_rhs_operand")
 186        (and (match_code "const_double")
 187             (match_test "TARGET_FPA && neg_const_double_rtx_ok_for_fpa (op)"))))
 188
 189 (define_predicate "vfp_compare_operand"
 190   (ior (match_operand 0 "s_register_operand")
 191        (and (match_code "const_double")
 192             (match_test "arm_const_double_rtx (op)"))))
 193
 194 (define_predicate "arm_float_compare_operand"
 195   (if_then_else (match_test "TARGET_VFP")
 196                 (match_operand 0 "vfp_compare_operand")
 197                 (match_operand 0 "arm_float_rhs_operand")))
 198
 199 ;; True for valid index operands.
 200 (define_predicate "index_operand"
 201   (ior (match_operand 0 "s_register_operand")
 202        (and (match_operand 0 "immediate_operand")
 203             (match_test "(GET_CODE (op) != CONST_INT
 204                           || (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))
 205
 206 ;; True for operators that can be combined with a shift in ARM state.
 207 (define_special_predicate "shiftable_operator"
 208   (and (match_code "plus,minus,ior,xor,and")
 209        (match_test "mode == GET_MODE (op)")))
 210
 211 ;; True for logical binary operators.
 212 (define_special_predicate "logical_binary_operator"
 213   (and (match_code "ior,xor,and")
 214        (match_test "mode == GET_MODE (op)")))
 215
 216 ;; True for commutative operators
 217 (define_special_predicate "commutative_binary_operator"
 218   (and (match_code "ior,xor,and,plus")
 219        (match_test "mode == GET_MODE (op)")))
 220
 221 ;; True for shift operators.
 222 (define_special_predicate "shift_operator"
 223   (and (ior (ior (and (match_code "mult")
 224                       (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
 225                  (and (match_code "rotate")
 226                       (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
 227                                    && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
 228             (match_code "ashift,ashiftrt,lshiftrt,rotatert"))
 229        (match_test "mode == GET_MODE (op)")))
 230
 231 ;; True for shift operators which can be used with saturation instructions.
 232 (define_special_predicate "sat_shift_operator"
 233   (and (match_code "ashift,ashiftrt")
 234        (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
 235                     && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) <= 32)")
 236        (match_test "mode == GET_MODE (op)")))
 237
 238 ;; True for MULT, to identify which variant of shift_operator is in use.
 239 (define_special_predicate "mult_operator"
 240   (match_code "mult"))
 241
 242 ;; True for operators that have 16-bit thumb variants.  */
 243 (define_special_predicate "thumb_16bit_operator"
 244   (match_code "plus,minus,and,ior,xor"))
 245
 246 ;; True for EQ & NE
 247 (define_special_predicate "equality_operator"
 248   (match_code "eq,ne"))
 249
 250 ;; True for integer comparisons and, if FP is active, for comparisons
 251 ;; other than LTGT or UNEQ.
 252 (define_special_predicate "arm_comparison_operator"
 253   (and (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
 254                     unordered,ordered,unlt,unle,unge,ungt")
 255        (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
 256
 257 (define_special_predicate "lt_ge_comparison_operator"
 258   (match_code "lt,ge"))
 259
 260 (define_special_predicate "noov_comparison_operator"
 261   (match_code "lt,ge,eq,ne"))
 262
 263 (define_special_predicate "minmax_operator"
 264   (and (match_code "smin,smax,umin,umax")
 265        (match_test "mode == GET_MODE (op)")))
 266
 267 (define_special_predicate "cc_register"
 268   (and (match_code "reg")
 269        (and (match_test "REGNO (op) == CC_REGNUM")
 270             (ior (match_test "mode == GET_MODE (op)")
 271                  (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))))
 272
 273 (define_special_predicate "dominant_cc_register"
 274   (match_code "reg")
 275 {
 276   if (mode == VOIDmode)
 277     {
 278       mode = GET_MODE (op);
 279
 280       if (GET_MODE_CLASS (mode) != MODE_CC)
 281         return false;
 282     }
 283
 284   return (cc_register (op, mode)
 285           && (mode == CC_DNEmode
 286              || mode == CC_DEQmode
 287              || mode == CC_DLEmode
 288              || mode == CC_DLTmode
 289              || mode == CC_DGEmode
 290              || mode == CC_DGTmode
 291              || mode == CC_DLEUmode
 292              || mode == CC_DLTUmode
 293              || mode == CC_DGEUmode
 294              || mode == CC_DGTUmode));
 295 })
 296
 297 (define_special_predicate "arm_extendqisi_mem_op"
 298   (and (match_operand 0 "memory_operand")
 299        (match_test "arm_legitimate_address_outer_p (mode, XEXP (op, 0),
 300                                                     SIGN_EXTEND, 0)")))
 301
 302 (define_special_predicate "arm_reg_or_extendqisi_mem_op"
 303   (ior (match_operand 0 "arm_extendqisi_mem_op")
 304        (match_operand 0 "s_register_operand")))
 305
 306 (define_predicate "power_of_two_operand"
 307   (match_code "const_int")
 308 {
 309   unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff;
 310
 311   return value != 0 && (value & (value - 1)) == 0;
 312 })
 313
 314 (define_predicate "nonimmediate_di_operand"
 315   (match_code "reg,subreg,mem")
 316 {
 317    if (s_register_operand (op, mode))
 318      return true;
 319
 320    if (GET_CODE (op) == SUBREG)
 321      op = SUBREG_REG (op);
 322
 323    return GET_CODE (op) == MEM && memory_address_p (DImode, XEXP (op, 0));
 324 })
 325
 326 (define_predicate "di_operand"
 327   (ior (match_code "const_int,const_double")
 328        (and (match_code "reg,subreg,mem")
 329             (match_operand 0 "nonimmediate_di_operand"))))
 330
 331 (define_predicate "nonimmediate_soft_df_operand"
 332   (match_code "reg,subreg,mem")
 333 {
 334   if (s_register_operand (op, mode))
 335     return true;
 336
 337   if (GET_CODE (op) == SUBREG)
 338     op = SUBREG_REG (op);
 339
 340   return GET_CODE (op) == MEM && memory_address_p (DFmode, XEXP (op, 0));
 341 })
 342
 343 (define_predicate "soft_df_operand"
 344   (ior (match_code "const_double")
 345        (and (match_code "reg,subreg,mem")
 346             (match_operand 0 "nonimmediate_soft_df_operand"))))
 347
 348 (define_special_predicate "load_multiple_operation"
 349   (match_code "parallel")
 350 {
 351   HOST_WIDE_INT count = XVECLEN (op, 0);
 352   unsigned dest_regno;
 353   rtx src_addr;
 354   HOST_WIDE_INT i = 1, base = 0;
 355   HOST_WIDE_INT offset = 0;
 356   rtx elt;
 357   bool addr_reg_loaded = false;
 358   bool update = false;
 359
 360   if (count <= 1
 361       || GET_CODE (XVECEXP (op, 0, 0)) != SET
 362       || !REG_P (SET_DEST (XVECEXP (op, 0, 0))))
 363     return false;
 364
 365   /* Check to see if this might be a write-back.  */
 366   if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
 367     {
 368       i++;
 369       base = 1;
 370       update = true;
 371
 372       /* Now check it more carefully.  */
 373       if (GET_CODE (SET_DEST (elt)) != REG
 374           || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
 375           || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
 376           || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
 377         return false;
 378     }
 379
 380   /* Perform a quick check so we don't blow up below.  */
 381   if (count <= i
 382       || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
 383       || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
 384       || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
 385     return false;
 386
 387   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
 388   src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
 389   if (GET_CODE (src_addr) == PLUS)
 390     {
 391       if (GET_CODE (XEXP (src_addr, 1)) != CONST_INT)
 392         return false;
 393       offset = INTVAL (XEXP (src_addr, 1));
 394       src_addr = XEXP (src_addr, 0);
 395     }
 396   if (!REG_P (src_addr))
 397     return false;
 398
 399   for (; i < count; i++)
 400     {
 401       elt = XVECEXP (op, 0, i);
 402
 403       if (GET_CODE (elt) != SET
 404           || GET_CODE (SET_DEST (elt)) != REG
 405           || GET_MODE (SET_DEST (elt)) != SImode
 406           || REGNO (SET_DEST (elt)) <= dest_regno
 407           || GET_CODE (SET_SRC (elt)) != MEM
 408           || GET_MODE (SET_SRC (elt)) != SImode
 409           || ((GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
 410                || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
 411                || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
 412                || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != offset + (i - base) * 4)
 413               && (!REG_P (XEXP (SET_SRC (elt), 0))
 414                   || offset + (i - base) * 4 != 0)))
 415         return false;
 416       dest_regno = REGNO (SET_DEST (elt));
 417       if (dest_regno == REGNO (src_addr))
 418         addr_reg_loaded = true;
 419     }
 420   /* For Thumb, we only have updating instructions.  If the pattern does
 421      not describe an update, it must be because the address register is
 422      in the list of loaded registers - on the hardware, this has the effect
 423      of overriding the update.  */
 424   if (update && addr_reg_loaded)
 425     return false;
 426   if (TARGET_THUMB1)
 427     return update || addr_reg_loaded;
 428   return true;
 429 })
 430
 431 (define_special_predicate "store_multiple_operation"
 432   (match_code "parallel")
 433 {
 434   HOST_WIDE_INT count = XVECLEN (op, 0);
 435   unsigned src_regno;
 436   rtx dest_addr;
 437   HOST_WIDE_INT i = 1, base = 0, offset = 0;
 438   rtx elt;
 439
 440   if (count <= 1
 441       || GET_CODE (XVECEXP (op, 0, 0)) != SET)
 442     return false;
 443
 444   /* Check to see if this might be a write-back.  */
 445   if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
 446     {
 447       i++;
 448       base = 1;
 449
 450       /* Now check it more carefully.  */
 451       if (GET_CODE (SET_DEST (elt)) != REG
 452           || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
 453           || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
 454           || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
 455         return false;
 456     }
 457
 458   /* Perform a quick check so we don't blow up below.  */
 459   if (count <= i
 460       || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
 461       || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
 462       || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
 463     return false;
 464
 465   src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
 466   dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
 467
 468   if (GET_CODE (dest_addr) == PLUS)
 469     {
 470       if (GET_CODE (XEXP (dest_addr, 1)) != CONST_INT)
 471         return false;
 472       offset = INTVAL (XEXP (dest_addr, 1));
 473       dest_addr = XEXP (dest_addr, 0);
 474     }
 475   if (!REG_P (dest_addr))
 476     return false;
 477
 478   for (; i < count; i++)
 479     {
 480       elt = XVECEXP (op, 0, i);
 481
 482       if (GET_CODE (elt) != SET
 483           || GET_CODE (SET_SRC (elt)) != REG
 484           || GET_MODE (SET_SRC (elt)) != SImode
 485           || REGNO (SET_SRC (elt)) <= src_regno
 486           || GET_CODE (SET_DEST (elt)) != MEM
 487           || GET_MODE (SET_DEST (elt)) != SImode
 488           || ((GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
 489                || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
 490                || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
 491                || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != offset + (i - base) * 4)
 492               && (!REG_P (XEXP (SET_DEST (elt), 0))
 493                   || offset + (i - base) * 4 != 0)))
 494         return false;
 495       src_regno = REGNO (SET_SRC (elt));
 496     }
 497
 498   return true;
 499 })
 500
 501 (define_special_predicate "multi_register_push"
 502   (match_code "parallel")
 503 {
 504   if ((GET_CODE (XVECEXP (op, 0, 0)) != SET)
 505       || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
 506       || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
 507     return false;
 508
 509   return true;
 510 })
 511
 512 (define_predicate "push_mult_memory_operand"
 513   (match_code "mem")
 514 {
 515   /* ??? Given how PUSH_MULT is generated in the prologues, is there
 516      any point in testing for thumb1 specially?  All of the variants
 517      use the same form.  */
 518   if (TARGET_THUMB1)
 519     {
 520       /* ??? No attempt is made to represent STMIA, or validate that
 521          the stack adjustment matches the register count.  This is
 522          true of the ARM/Thumb2 path as well.  */
 523       rtx x = XEXP (op, 0);
 524       if (GET_CODE (x) != PRE_MODIFY)
 525         return false;
 526       if (XEXP (x, 0) != stack_pointer_rtx)
 527         return false;
 528       x = XEXP (x, 1);
 529       if (GET_CODE (x) != PLUS)
 530         return false;
 531       if (XEXP (x, 0) != stack_pointer_rtx)
 532         return false;
 533       return CONST_INT_P (XEXP (x, 1));
 534     }
 535
 536   /* ARM and Thumb2 handle pre-modify in their legitimate_address.  */
 537   return memory_operand (op, mode);
 538 })
 539
 540 ;;-------------------------------------------------------------------------
 541 ;;
 542 ;; Thumb predicates
 543 ;;
 544
 545 (define_predicate "thumb1_cmp_operand"
 546   (ior (and (match_code "reg,subreg")
 547             (match_operand 0 "s_register_operand"))
 548        (and (match_code "const_int")
 549             (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256"))))
 550
 551 (define_predicate "thumb1_cmpneg_operand"
 552   (and (match_code "const_int")
 553        (match_test "INTVAL (op) < 0 && INTVAL (op) > -256")))
 554
 555 ;; Return TRUE if a result can be stored in OP without clobbering the
 556 ;; condition code register.  Prior to reload we only accept a
 557 ;; register.  After reload we have to be able to handle memory as
 558 ;; well, since a pseudo may not get a hard reg and reload cannot
 559 ;; handle output-reloads on jump insns.
 560
 561 ;; We could possibly handle mem before reload as well, but that might
 562 ;; complicate things with the need to handle increment
 563 ;; side-effects.
 564 (define_predicate "thumb_cbrch_target_operand"
 565   (and (match_code "reg,subreg,mem")
 566        (ior (match_operand 0 "s_register_operand")
 567             (and (match_test "reload_in_progress || reload_completed")
 568                  (match_operand 0 "memory_operand")))))
 569
 570 ;;-------------------------------------------------------------------------
 571 ;;
 572 ;; MAVERICK predicates
 573 ;;
 574
 575 (define_predicate "cirrus_register_operand"
 576   (match_code "reg,subreg")
 577 {
 578   if (GET_CODE (op) == SUBREG)
 579     op = SUBREG_REG (op);
 580
 581   return (GET_CODE (op) == REG
 582           && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
 583               || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
 584 })
 585
 586 (define_predicate "cirrus_fp_register"
 587   (match_code "reg,subreg")
 588 {
 589   if (GET_CODE (op) == SUBREG)
 590     op = SUBREG_REG (op);
 591
 592   return (GET_CODE (op) == REG
 593           && (REGNO (op) >= FIRST_PSEUDO_REGISTER
 594               || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
 595 })
 596
 597 (define_predicate "cirrus_shift_const"
 598   (and (match_code "const_int")
 599        (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 64")))
 600
 601
 602 ;; Neon predicates
 603
 604 (define_predicate "const_multiple_of_8_operand"
 605   (match_code "const_int")
 606 {
 607   unsigned HOST_WIDE_INT val = INTVAL (op);
 608   return (val & 7) == 0;
 609 })
 610
 611 (define_predicate "imm_for_neon_mov_operand"
 612   (match_code "const_vector")
 613 {
 614   return neon_immediate_valid_for_move (op, mode, NULL, NULL);
 615 })
 616
 617 (define_predicate "imm_for_neon_lshift_operand"
 618   (match_code "const_vector")
 619 {
 620   return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true);
 621 })
 622
 623 (define_predicate "imm_for_neon_rshift_operand"
 624   (match_code "const_vector")
 625 {
 626   return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false);
 627 })
 628
 629 (define_predicate "imm_lshift_or_reg_neon"
 630   (ior (match_operand 0 "s_register_operand")
 631        (match_operand 0 "imm_for_neon_lshift_operand")))
 632
 633 (define_predicate "imm_rshift_or_reg_neon"
 634   (ior (match_operand 0 "s_register_operand")
 635        (match_operand 0 "imm_for_neon_rshift_operand")))
 636
 637 (define_predicate "imm_for_neon_logic_operand"
 638   (match_code "const_vector")
 639 {
 640   return (TARGET_NEON
 641           && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL));
 642 })
 643
 644 (define_predicate "imm_for_neon_inv_logic_operand"
 645   (match_code "const_vector")
 646 {
 647   return (TARGET_NEON
 648           && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL));
 649 })
 650
 651 (define_predicate "neon_logic_op2"
 652   (ior (match_operand 0 "imm_for_neon_logic_operand")
 653        (match_operand 0 "s_register_operand")))
 654
 655 (define_predicate "neon_inv_logic_op2"
 656   (ior (match_operand 0 "imm_for_neon_inv_logic_operand")
 657        (match_operand 0 "s_register_operand")))
 658
 659 ;; TODO: We could check lane numbers more precisely based on the mode.
 660 (define_predicate "neon_lane_number"
 661   (and (match_code "const_int")
 662        (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 15")))
 663 ;; Predicates for named expanders that overlap multiple ISAs.
 664
 665 (define_predicate "cmpdi_operand"
 666   (if_then_else (match_test "TARGET_HARD_FLOAT && TARGET_MAVERICK")
 667                 (and (match_test "TARGET_ARM")
 668                      (match_operand 0 "cirrus_fp_register"))
 669                 (and (match_test "TARGET_32BIT")
 670                      (match_operand 0 "arm_di_operand"))))
 671
 672 ;; True if the operand is memory reference suitable for a ldrex/strex.
 673 (define_predicate "arm_sync_memory_operand"
 674   (and (match_operand 0 "memory_operand")
 675        (match_code "reg" "0")))
 676
 677 ;; Predicates for parallel expanders based on mode.
 678 (define_special_predicate "vect_par_constant_high"
 679   (match_code "parallel")
 680 {
 681   HOST_WIDE_INT count = XVECLEN (op, 0);
 682   int i;
 683   int base = GET_MODE_NUNITS (mode);
 684
 685   if ((count < 1)
 686       || (count != base/2))
 687     return false;
 688
 689   if (!VECTOR_MODE_P (mode))
 690     return false;
 691
 692   for (i = 0; i < count; i++)
 693    {
 694      rtx elt = XVECEXP (op, 0, i);
 695      int val;
 696
 697      if (GET_CODE (elt) != CONST_INT)
 698        return false;
 699
 700      val = INTVAL (elt);
 701      if (val != (base/2) + i)
 702        return false;
 703    }
 704   return true;
 705 })
 706
 707 (define_special_predicate "vect_par_constant_low"
 708   (match_code "parallel")
 709 {
 710   HOST_WIDE_INT count = XVECLEN (op, 0);
 711   int i;
 712   int base = GET_MODE_NUNITS (mode);
 713
 714   if ((count < 1)
 715       || (count != base/2))
 716     return false;
 717
 718   if (!VECTOR_MODE_P (mode))
 719     return false;
 720
 721   for (i = 0; i < count; i++)
 722    {
 723      rtx elt = XVECEXP (op, 0, i);
 724      int val;
 725
 726      if (GET_CODE (elt) != CONST_INT)
 727        return false;
 728
 729      val = INTVAL (elt);
 730      if (val != i)
 731        return false;
 732    }
 733   return true;
 734 })
 735
 736 (define_predicate "neon_struct_operand"
 737   (and (match_code "mem")
 738        (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
 739
 740 (define_predicate "neon_struct_or_register_operand"
 741   (ior (match_operand 0 "neon_struct_operand")
 742        (match_operand 0 "s_register_operand")))
 743
 744 (define_special_predicate "add_operator"
 745   (match_code "plus"))