gcc/config/arm/thumb2.md

   1 ;; ARM Thumb-2 Machine Description
   2 ;; Copyright (C) 2007, 2008, 2010 Free Software Foundation, Inc.
   3 ;; Written by CodeSourcery, LLC.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.  */
  20
  21 ;; Note: Thumb-2 is the variant of the Thumb architecture that adds
  22 ;; 32-bit encodings of [almost all of] the Arm instruction set.
  23 ;; Some old documents refer to the relatively minor interworking
  24 ;; changes made in armv5t as "thumb2".  These are considered part
  25 ;; the 16-bit Thumb-1 instruction set.
  26
  27 (define_insn "*thumb2_incscc"
  28   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
  29         (plus:SI (match_operator:SI 2 "arm_comparison_operator"
  30                     [(match_operand:CC 3 "cc_register" "") (const_int 0)])
  31                  (match_operand:SI 1 "s_register_operand" "0,?r")))]
  32   "TARGET_THUMB2"
  33   "@
  34   it\\t%d2\;add%d2\\t%0, %1, #1
  35   ite\\t%D2\;mov%D2\\t%0, %1\;add%d2\\t%0, %1, #1"
  36   [(set_attr "conds" "use")
  37    (set_attr "length" "6,10")]
  38 )
  39
  40 (define_insn "*thumb2_decscc"
  41   [(set (match_operand:SI            0 "s_register_operand" "=r,r")
  42         (minus:SI (match_operand:SI  1 "s_register_operand" "0,?r")
  43                   (match_operator:SI 2 "arm_comparison_operator"
  44                    [(match_operand   3 "cc_register" "") (const_int 0)])))]
  45   "TARGET_THUMB2"
  46   "@
  47    it\\t%d2\;sub%d2\\t%0, %1, #1
  48    ite\\t%D2\;mov%D2\\t%0, %1\;sub%d2\\t%0, %1, #1"
  49   [(set_attr "conds" "use")
  50    (set_attr "length" "6,10")]
  51 )
  52
  53 ;; Thumb-2 only allows shift by constant on data processing instructions
  54 (define_insn "*thumb_andsi_not_shiftsi_si"
  55   [(set (match_operand:SI 0 "s_register_operand" "=r")
  56         (and:SI (not:SI (match_operator:SI 4 "shift_operator"
  57                          [(match_operand:SI 2 "s_register_operand" "r")
  58                           (match_operand:SI 3 "const_int_operand" "M")]))
  59                 (match_operand:SI 1 "s_register_operand" "r")))]
  60   "TARGET_THUMB2"
  61   "bic%?\\t%0, %1, %2%S4"
  62   [(set_attr "predicable" "yes")
  63    (set_attr "shift" "2")
  64    (set_attr "type" "alu_shift")]
  65 )
  66
  67 (define_insn "*thumb2_smaxsi3"
  68   [(set (match_operand:SI          0 "s_register_operand" "=r,r,r")
  69         (smax:SI (match_operand:SI 1 "s_register_operand"  "0,r,?r")
  70                  (match_operand:SI 2 "arm_rhs_operand"    "rI,0,rI")))
  71    (clobber (reg:CC CC_REGNUM))]
  72   "TARGET_THUMB2"
  73   "@
  74    cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2
  75    cmp\\t%1, %2\;it\\tge\;movge\\t%0, %1
  76    cmp\\t%1, %2\;ite\\tge\;movge\\t%0, %1\;movlt\\t%0, %2"
  77   [(set_attr "conds" "clob")
  78    (set_attr "length" "10,10,14")]
  79 )
  80
  81 (define_insn "*thumb2_sminsi3"
  82   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
  83         (smin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
  84                  (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
  85    (clobber (reg:CC CC_REGNUM))]
  86   "TARGET_THUMB2"
  87   "@
  88    cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2
  89    cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %1
  90    cmp\\t%1, %2\;ite\\tlt\;movlt\\t%0, %1\;movge\\t%0, %2"
  91   [(set_attr "conds" "clob")
  92    (set_attr "length" "10,10,14")]
  93 )
  94
  95 (define_insn "*thumb32_umaxsi3"
  96   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
  97         (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
  98                  (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
  99    (clobber (reg:CC CC_REGNUM))]
 100   "TARGET_THUMB2"
 101   "@
 102    cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2
 103    cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %1
 104    cmp\\t%1, %2\;ite\\tcs\;movcs\\t%0, %1\;movcc\\t%0, %2"
 105   [(set_attr "conds" "clob")
 106    (set_attr "length" "10,10,14")]
 107 )
 108
 109 (define_insn "*thumb2_uminsi3"
 110   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
 111         (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
 112                  (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
 113    (clobber (reg:CC CC_REGNUM))]
 114   "TARGET_THUMB2"
 115   "@
 116    cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2
 117    cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %1
 118    cmp\\t%1, %2\;ite\\tcc\;movcc\\t%0, %1\;movcs\\t%0, %2"
 119   [(set_attr "conds" "clob")
 120    (set_attr "length" "10,10,14")]
 121 )
 122
 123 ;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
 124 (define_insn "*thumb2_negdi2"
 125   [(set (match_operand:DI         0 "s_register_operand" "=&r,r")
 126         (neg:DI (match_operand:DI 1 "s_register_operand"  "?r,0")))
 127    (clobber (reg:CC CC_REGNUM))]
 128   "TARGET_THUMB2"
 129   "negs\\t%Q0, %Q1\;sbc\\t%R0, %R1, %R1, lsl #1"
 130   [(set_attr "conds" "clob")
 131    (set_attr "length" "8")]
 132 )
 133
 134 (define_insn "*thumb2_abssi2"
 135   [(set (match_operand:SI         0 "s_register_operand" "=r,&r")
 136         (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
 137    (clobber (reg:CC CC_REGNUM))]
 138   "TARGET_THUMB2"
 139   "@
 140    cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
 141    eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31"
 142   [(set_attr "conds" "clob,*")
 143    (set_attr "shift" "1")
 144    ;; predicable can't be set based on the variant, so left as no
 145    (set_attr "length" "10,8")]
 146 )
 147
 148 (define_insn "*thumb2_neg_abssi2"
 149   [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
 150         (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
 151    (clobber (reg:CC CC_REGNUM))]
 152   "TARGET_THUMB2"
 153   "@
 154    cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
 155    eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31"
 156   [(set_attr "conds" "clob,*")
 157    (set_attr "shift" "1")
 158    ;; predicable can't be set based on the variant, so left as no
 159    (set_attr "length" "10,8")]
 160 )
 161
 162 ;; We have two alternatives here for memory loads (and similarly for stores)
 163 ;; to reflect the fact that the permissible constant pool ranges differ
 164 ;; between ldr instructions taking low regs and ldr instructions taking high
 165 ;; regs.  The high register alternatives are not taken into account when
 166 ;; choosing register preferences in order to reflect their expense.
 167 (define_insn "*thumb2_movsi_insn"
 168   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l ,*hk,m,*m")
 169         (match_operand:SI 1 "general_operand"      "rk ,I,K,j,mi,*mi,l,*hk"))]
 170   "TARGET_THUMB2 && ! TARGET_IWMMXT
 171    && !(TARGET_HARD_FLOAT && TARGET_VFP)
 172    && (   register_operand (operands[0], SImode)
 173        || register_operand (operands[1], SImode))"
 174   "@
 175    mov%?\\t%0, %1
 176    mov%?\\t%0, %1
 177    mvn%?\\t%0, #%B1
 178    movw%?\\t%0, %1
 179    ldr%?\\t%0, %1
 180    ldr%?\\t%0, %1
 181    str%?\\t%1, %0
 182    str%?\\t%1, %0"
 183   [(set_attr "type" "*,*,*,*,load1,load1,store1,store1")
 184    (set_attr "predicable" "yes")
 185    (set_attr "pool_range" "*,*,*,*,1020,4096,*,*")
 186    (set_attr "neg_pool_range" "*,*,*,*,0,0,*,*")]
 187 )
 188
 189 (define_insn "tls_load_dot_plus_four"
 190   [(set (match_operand:SI 0 "register_operand" "=l,l,r,r")
 191         (mem:SI (unspec:SI [(match_operand:SI 2 "register_operand" "0,1,0,1")
 192                             (const_int 4)
 193                             (match_operand 3 "" "")]
 194                            UNSPEC_PIC_BASE)))
 195    (clobber (match_scratch:SI 1 "=X,l,X,r"))]
 196   "TARGET_THUMB2"
 197   "*
 198   (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
 199                              INTVAL (operands[3]));
 200   return \"add\\t%2, %|pc\;ldr%?\\t%0, [%2]\";
 201   "
 202   [(set_attr "length" "4,4,6,6")]
 203 )
 204
 205 ;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
 206 ;; of the messiness associated with the ARM patterns.
 207 (define_insn "*thumb2_movhi_insn"
 208   [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
 209         (match_operand:HI 1 "general_operand"      "rI,n,r,m"))]
 210   "TARGET_THUMB2
 211   && (register_operand (operands[0], HImode)
 212      || register_operand (operands[1], HImode))"
 213   "@
 214    mov%?\\t%0, %1\\t%@ movhi
 215    movw%?\\t%0, %L1\\t%@ movhi
 216    str%(h%)\\t%1, %0\\t%@ movhi
 217    ldr%(h%)\\t%0, %1\\t%@ movhi"
 218   [(set_attr "type" "*,*,store1,load1")
 219    (set_attr "predicable" "yes")
 220    (set_attr "pool_range" "*,*,*,4096")
 221    (set_attr "neg_pool_range" "*,*,*,250")]
 222 )
 223
 224 (define_insn "*thumb2_cmpsi_neg_shiftsi"
 225   [(set (reg:CC CC_REGNUM)
 226         (compare:CC (match_operand:SI 0 "s_register_operand" "r")
 227                     (neg:SI (match_operator:SI 3 "shift_operator"
 228                              [(match_operand:SI 1 "s_register_operand" "r")
 229                               (match_operand:SI 2 "const_int_operand" "M")]))))]
 230   "TARGET_THUMB2"
 231   "cmn%?\\t%0, %1%S3"
 232   [(set_attr "conds" "set")
 233    (set_attr "shift" "1")
 234    (set_attr "type" "alu_shift")]
 235 )
 236
 237 (define_insn "*thumb2_mov_scc"
 238   [(set (match_operand:SI 0 "s_register_operand" "=r")
 239         (match_operator:SI 1 "arm_comparison_operator"
 240          [(match_operand 2 "cc_register" "") (const_int 0)]))]
 241   "TARGET_THUMB2"
 242   "ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
 243   [(set_attr "conds" "use")
 244    (set_attr "length" "10")]
 245 )
 246
 247 (define_insn "*thumb2_mov_negscc"
 248   [(set (match_operand:SI 0 "s_register_operand" "=r")
 249         (neg:SI (match_operator:SI 1 "arm_comparison_operator"
 250                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 251   "TARGET_THUMB2"
 252   "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
 253   [(set_attr "conds" "use")
 254    (set_attr "length" "10")]
 255 )
 256
 257 (define_insn "*thumb2_mov_notscc"
 258   [(set (match_operand:SI 0 "s_register_operand" "=r")
 259         (not:SI (match_operator:SI 1 "arm_comparison_operator"
 260                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 261   "TARGET_THUMB2"
 262   "ite\\t%D1\;mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1"
 263   [(set_attr "conds" "use")
 264    (set_attr "length" "10")]
 265 )
 266
 267 (define_insn "*thumb2_movsicc_insn"
 268   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r")
 269         (if_then_else:SI
 270          (match_operator 3 "arm_comparison_operator"
 271           [(match_operand 4 "cc_register" "") (const_int 0)])
 272          (match_operand:SI 1 "arm_not_operand" "0,0,rI,K,rI,rI,K,K")
 273          (match_operand:SI 2 "arm_not_operand" "rI,K,0,0,rI,K,rI,K")))]
 274   "TARGET_THUMB2"
 275   "@
 276    it\\t%D3\;mov%D3\\t%0, %2
 277    it\\t%D3\;mvn%D3\\t%0, #%B2
 278    it\\t%d3\;mov%d3\\t%0, %1
 279    it\\t%d3\;mvn%d3\\t%0, #%B1
 280    ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
 281    ite\\t%d3\;mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2
 282    ite\\t%d3\;mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2
 283    ite\\t%d3\;mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2"
 284   [(set_attr "length" "6,6,6,6,10,10,10,10")
 285    (set_attr "conds" "use")]
 286 )
 287
 288 (define_insn "*thumb2_movsfcc_soft_insn"
 289   [(set (match_operand:SF 0 "s_register_operand" "=r,r")
 290         (if_then_else:SF (match_operator 3 "arm_comparison_operator"
 291                           [(match_operand 4 "cc_register" "") (const_int 0)])
 292                          (match_operand:SF 1 "s_register_operand" "0,r")
 293                          (match_operand:SF 2 "s_register_operand" "r,0")))]
 294   "TARGET_THUMB2 && TARGET_SOFT_FLOAT"
 295   "@
 296    it\\t%D3\;mov%D3\\t%0, %2
 297    it\\t%d3\;mov%d3\\t%0, %1"
 298   [(set_attr "length" "6,6")
 299    (set_attr "conds" "use")]
 300 )
 301
 302 (define_insn "*call_reg_thumb2"
 303   [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
 304          (match_operand 1 "" ""))
 305    (use (match_operand 2 "" ""))
 306    (clobber (reg:SI LR_REGNUM))]
 307   "TARGET_THUMB2"
 308   "blx%?\\t%0"
 309   [(set_attr "type" "call")]
 310 )
 311
 312 (define_insn "*call_value_reg_thumb2"
 313   [(set (match_operand 0 "" "")
 314         (call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
 315               (match_operand 2 "" "")))
 316    (use (match_operand 3 "" ""))
 317    (clobber (reg:SI LR_REGNUM))]
 318   "TARGET_THUMB2"
 319   "blx\\t%1"
 320   [(set_attr "type" "call")]
 321 )
 322
 323 (define_insn "*thumb2_indirect_jump"
 324   [(set (pc)
 325         (match_operand:SI 0 "register_operand" "l*r"))]
 326   "TARGET_THUMB2"
 327   "bx\\t%0"
 328   [(set_attr "conds" "clob")]
 329 )
 330 ;; Don't define thumb2_load_indirect_jump because we can't guarantee label
 331 ;; addresses will have the thumb bit set correctly.
 332
 333
 334 (define_insn "*thumb2_and_scc"
 335   [(set (match_operand:SI 0 "s_register_operand" "=r")
 336         (and:SI (match_operator:SI 1 "arm_comparison_operator"
 337                  [(match_operand 3 "cc_register" "") (const_int 0)])
 338                 (match_operand:SI 2 "s_register_operand" "r")))]
 339   "TARGET_THUMB2"
 340   "ite\\t%D1\;mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1"
 341   [(set_attr "conds" "use")
 342    (set_attr "length" "10")]
 343 )
 344
 345 (define_insn "*thumb2_ior_scc"
 346   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 347         (ior:SI (match_operator:SI 2 "arm_comparison_operator"
 348                  [(match_operand 3 "cc_register" "") (const_int 0)])
 349                 (match_operand:SI 1 "s_register_operand" "0,?r")))]
 350   "TARGET_THUMB2"
 351   "@
 352    it\\t%d2\;orr%d2\\t%0, %1, #1
 353    ite\\t%D2\;mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1"
 354   [(set_attr "conds" "use")
 355    (set_attr "length" "6,10")]
 356 )
 357
 358 (define_insn "*thumb2_cond_move"
 359   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
 360         (if_then_else:SI (match_operator 3 "equality_operator"
 361                           [(match_operator 4 "arm_comparison_operator"
 362                             [(match_operand 5 "cc_register" "") (const_int 0)])
 363                            (const_int 0)])
 364                          (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
 365                          (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))]
 366   "TARGET_THUMB2"
 367   "*
 368     if (GET_CODE (operands[3]) == NE)
 369       {
 370         if (which_alternative != 1)
 371           output_asm_insn (\"it\\t%D4\;mov%D4\\t%0, %2\", operands);
 372         if (which_alternative != 0)
 373           output_asm_insn (\"it\\t%d4\;mov%d4\\t%0, %1\", operands);
 374         return \"\";
 375       }
 376     switch (which_alternative)
 377       {
 378       case 0:
 379         output_asm_insn (\"it\\t%d4\", operands);
 380         break;
 381       case 1:
 382         output_asm_insn (\"it\\t%D4\", operands);
 383         break;
 384       case 2:
 385         output_asm_insn (\"ite\\t%D4\", operands);
 386         break;
 387       default:
 388         abort();
 389       }
 390     if (which_alternative != 0)
 391       output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 392     if (which_alternative != 1)
 393       output_asm_insn (\"mov%d4\\t%0, %2\", operands);
 394     return \"\";
 395   "
 396   [(set_attr "conds" "use")
 397    (set_attr "length" "6,6,10")]
 398 )
 399
 400 (define_insn "*thumb2_cond_arith"
 401   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 402         (match_operator:SI 5 "shiftable_operator"
 403          [(match_operator:SI 4 "arm_comparison_operator"
 404            [(match_operand:SI 2 "s_register_operand" "r,r")
 405             (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
 406           (match_operand:SI 1 "s_register_operand" "0,?r")]))
 407    (clobber (reg:CC CC_REGNUM))]
 408   "TARGET_THUMB2"
 409   "*
 410     if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
 411       return \"%i5\\t%0, %1, %2, lsr #31\";
 412
 413     output_asm_insn (\"cmp\\t%2, %3\", operands);
 414     if (GET_CODE (operands[5]) == AND)
 415       {
 416         output_asm_insn (\"ite\\t%D4\", operands);
 417         output_asm_insn (\"mov%D4\\t%0, #0\", operands);
 418       }
 419     else if (GET_CODE (operands[5]) == MINUS)
 420       {
 421         output_asm_insn (\"ite\\t%D4\", operands);
 422         output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands);
 423       }
 424     else if (which_alternative != 0)
 425       {
 426         output_asm_insn (\"ite\\t%D4\", operands);
 427         output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 428       }
 429     else
 430       output_asm_insn (\"it\\t%d4\", operands);
 431     return \"%i5%d4\\t%0, %1, #1\";
 432   "
 433   [(set_attr "conds" "clob")
 434    (set_attr "length" "14")]
 435 )
 436
 437 (define_insn "*thumb2_cond_sub"
 438   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 439         (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r")
 440                   (match_operator:SI 4 "arm_comparison_operator"
 441                    [(match_operand:SI 2 "s_register_operand" "r,r")
 442                     (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
 443    (clobber (reg:CC CC_REGNUM))]
 444   "TARGET_THUMB2"
 445   "*
 446     output_asm_insn (\"cmp\\t%2, %3\", operands);
 447     if (which_alternative != 0)
 448       {
 449         output_asm_insn (\"ite\\t%D4\", operands);
 450         output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 451       }
 452     else
 453       output_asm_insn (\"it\\t%d4\", operands);
 454     return \"sub%d4\\t%0, %1, #1\";
 455   "
 456   [(set_attr "conds" "clob")
 457    (set_attr "length" "10,14")]
 458 )
 459
 460 (define_insn "*thumb2_negscc"
 461   [(set (match_operand:SI 0 "s_register_operand" "=r")
 462         (neg:SI (match_operator 3 "arm_comparison_operator"
 463                  [(match_operand:SI 1 "s_register_operand" "r")
 464                   (match_operand:SI 2 "arm_rhs_operand" "rI")])))
 465    (clobber (reg:CC CC_REGNUM))]
 466   "TARGET_THUMB2"
 467   "*
 468   if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx)
 469     return \"asr\\t%0, %1, #31\";
 470
 471   if (GET_CODE (operands[3]) == NE)
 472     return \"subs\\t%0, %1, %2\;it\\tne\;mvnne\\t%0, #0\";
 473
 474   output_asm_insn (\"cmp\\t%1, %2\", operands);
 475   output_asm_insn (\"ite\\t%D3\", operands);
 476   output_asm_insn (\"mov%D3\\t%0, #0\", operands);
 477   return \"mvn%d3\\t%0, #0\";
 478   "
 479   [(set_attr "conds" "clob")
 480    (set_attr "length" "14")]
 481 )
 482
 483 (define_insn "*thumb2_movcond"
 484   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
 485         (if_then_else:SI
 486          (match_operator 5 "arm_comparison_operator"
 487           [(match_operand:SI 3 "s_register_operand" "r,r,r")
 488            (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
 489          (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
 490          (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
 491    (clobber (reg:CC CC_REGNUM))]
 492   "TARGET_THUMB2"
 493   "*
 494   if (GET_CODE (operands[5]) == LT
 495       && (operands[4] == const0_rtx))
 496     {
 497       if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
 498         {
 499           if (operands[2] == const0_rtx)
 500             return \"and\\t%0, %1, %3, asr #31\";
 501           return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\";
 502         }
 503       else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
 504         {
 505           if (operands[1] == const0_rtx)
 506             return \"bic\\t%0, %2, %3, asr #31\";
 507           return \"bics\\t%0, %2, %3, asr #32\;it\\tcs\;movcs\\t%0, %1\";
 508         }
 509       /* The only case that falls through to here is when both ops 1 & 2
 510          are constants.  */
 511     }
 512
 513   if (GET_CODE (operands[5]) == GE
 514       && (operands[4] == const0_rtx))
 515     {
 516       if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
 517         {
 518           if (operands[2] == const0_rtx)
 519             return \"bic\\t%0, %1, %3, asr #31\";
 520           return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\";
 521         }
 522       else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
 523         {
 524           if (operands[1] == const0_rtx)
 525             return \"and\\t%0, %2, %3, asr #31\";
 526           return \"ands\\t%0, %2, %3, asr #32\;it\tcc\;movcc\\t%0, %1\";
 527         }
 528       /* The only case that falls through to here is when both ops 1 & 2
 529          are constants.  */
 530     }
 531   if (GET_CODE (operands[4]) == CONST_INT
 532       && !const_ok_for_arm (INTVAL (operands[4])))
 533     output_asm_insn (\"cmn\\t%3, #%n4\", operands);
 534   else
 535     output_asm_insn (\"cmp\\t%3, %4\", operands);
 536   switch (which_alternative)
 537     {
 538     case 0:
 539       output_asm_insn (\"it\\t%D5\", operands);
 540       break;
 541     case 1:
 542       output_asm_insn (\"it\\t%d5\", operands);
 543       break;
 544     case 2:
 545       output_asm_insn (\"ite\\t%d5\", operands);
 546       break;
 547     default:
 548       abort();
 549     }
 550   if (which_alternative != 0)
 551     output_asm_insn (\"mov%d5\\t%0, %1\", operands);
 552   if (which_alternative != 1)
 553     output_asm_insn (\"mov%D5\\t%0, %2\", operands);
 554   return \"\";
 555   "
 556   [(set_attr "conds" "clob")
 557    (set_attr "length" "10,10,14")]
 558 )
 559
 560 ;; Zero and sign extension instructions.
 561
 562 ;; All supported Thumb2 implementations are armv6, so only that case is
 563 ;; provided.
 564 (define_insn "*thumb2_extendqisi_v6"
 565   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 566         (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
 567   "TARGET_THUMB2 && arm_arch6"
 568   "@
 569    sxtb%?\\t%0, %1
 570    ldr%(sb%)\\t%0, %1"
 571   [(set_attr "type" "alu_shift,load_byte")
 572    (set_attr "predicable" "yes")
 573    (set_attr "pool_range" "*,4096")
 574    (set_attr "neg_pool_range" "*,250")]
 575 )
 576
 577 (define_insn "*thumb2_zero_extendhisi2_v6"
 578   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 579         (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
 580   "TARGET_THUMB2 && arm_arch6"
 581   "@
 582    uxth%?\\t%0, %1
 583    ldr%(h%)\\t%0, %1"
 584   [(set_attr "type" "alu_shift,load_byte")
 585    (set_attr "predicable" "yes")
 586    (set_attr "pool_range" "*,4096")
 587    (set_attr "neg_pool_range" "*,250")]
 588 )
 589
 590 (define_insn "thumb2_zero_extendqisi2_v6"
 591   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 592         (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
 593   "TARGET_THUMB2 && arm_arch6"
 594   "@
 595    uxtb%(%)\\t%0, %1
 596    ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
 597   [(set_attr "type" "alu_shift,load_byte")
 598    (set_attr "predicable" "yes")
 599    (set_attr "pool_range" "*,4096")
 600    (set_attr "neg_pool_range" "*,250")]
 601 )
 602
 603 (define_insn "thumb2_casesi_internal"
 604   [(parallel [(set (pc)
 605                (if_then_else
 606                 (leu (match_operand:SI 0 "s_register_operand" "r")
 607                      (match_operand:SI 1 "arm_rhs_operand" "rI"))
 608                 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
 609                                  (label_ref (match_operand 2 "" ""))))
 610                 (label_ref (match_operand 3 "" ""))))
 611               (clobber (reg:CC CC_REGNUM))
 612               (clobber (match_scratch:SI 4 "=&r"))
 613               (use (label_ref (match_dup 2)))])]
 614   "TARGET_THUMB2 && !flag_pic"
 615   "* return thumb2_output_casesi(operands);"
 616   [(set_attr "conds" "clob")
 617    (set_attr "length" "16")]
 618 )
 619
 620 (define_insn "thumb2_casesi_internal_pic"
 621   [(parallel [(set (pc)
 622                (if_then_else
 623                 (leu (match_operand:SI 0 "s_register_operand" "r")
 624                      (match_operand:SI 1 "arm_rhs_operand" "rI"))
 625                 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
 626                                  (label_ref (match_operand 2 "" ""))))
 627                 (label_ref (match_operand 3 "" ""))))
 628               (clobber (reg:CC CC_REGNUM))
 629               (clobber (match_scratch:SI 4 "=&r"))
 630               (clobber (match_scratch:SI 5 "=r"))
 631               (use (label_ref (match_dup 2)))])]
 632   "TARGET_THUMB2 && flag_pic"
 633   "* return thumb2_output_casesi(operands);"
 634   [(set_attr "conds" "clob")
 635    (set_attr "length" "20")]
 636 )
 637
 638 ;; Note: this is not predicable, to avoid issues with linker-generated
 639 ;; interworking stubs.
 640 (define_insn "*thumb2_return"
 641   [(return)]
 642   "TARGET_THUMB2 && USE_RETURN_INSN (FALSE)"
 643   "*
 644   {
 645     return output_return_instruction (const_true_rtx, TRUE, FALSE);
 646   }"
 647   [(set_attr "type" "load1")
 648    (set_attr "length" "12")]
 649 )
 650
 651 (define_insn_and_split "thumb2_eh_return"
 652   [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
 653                     VUNSPEC_EH_RETURN)
 654    (clobber (match_scratch:SI 1 "=&r"))]
 655   "TARGET_THUMB2"
 656   "#"
 657   "&& reload_completed"
 658   [(const_int 0)]
 659   "
 660   {
 661     thumb_set_return_address (operands[0], operands[1]);
 662     DONE;
 663   }"
 664 )
 665
 666 (define_insn "*thumb2_alusi3_short"
 667   [(set (match_operand:SI          0 "s_register_operand" "=l")
 668         (match_operator:SI 3 "thumb_16bit_operator"
 669          [(match_operand:SI 1 "s_register_operand" "0")
 670           (match_operand:SI 2 "s_register_operand" "l")]))
 671    (clobber (reg:CC CC_REGNUM))]
 672   "TARGET_THUMB2 && reload_completed
 673    && GET_CODE(operands[3]) != PLUS
 674    && GET_CODE(operands[3]) != MINUS"
 675   "%I3%!\\t%0, %1, %2"
 676   [(set_attr "predicable" "yes")
 677    (set_attr "length" "2")]
 678 )
 679
 680 ;; Similarly for 16-bit shift instructions
 681 ;; There is no 16-bit rotate by immediate instruction.
 682 (define_peephole2
 683   [(set (match_operand:SI   0 "low_register_operand" "")
 684         (match_operator:SI  3 "shift_operator"
 685          [(match_operand:SI 1 "low_register_operand" "")
 686           (match_operand:SI 2 "low_reg_or_int_operand" "")]))]
 687   "TARGET_THUMB2
 688    && peep2_regno_dead_p(0, CC_REGNUM)
 689    && (CONST_INT_P (operands[2]) || operands[1] == operands[0])
 690    && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
 691        || REG_P(operands[2]))"
 692   [(parallel
 693     [(set (match_dup 0)
 694           (match_op_dup 3
 695            [(match_dup 1)
 696             (match_dup 2)]))
 697      (clobber (reg:CC CC_REGNUM))])]
 698   ""
 699 )
 700
 701 (define_insn "*thumb2_shiftsi3_short"
 702   [(set (match_operand:SI   0 "low_register_operand" "=l,l")
 703         (match_operator:SI  3 "shift_operator"
 704          [(match_operand:SI 1 "low_register_operand"  "0,l")
 705           (match_operand:SI 2 "low_reg_or_int_operand" "l,M")]))
 706    (clobber (reg:CC CC_REGNUM))]
 707   "TARGET_THUMB2 && reload_completed
 708    && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
 709        || REG_P(operands[2]))"
 710   "* return arm_output_shift(operands, 2);"
 711   [(set_attr "predicable" "yes")
 712    (set_attr "shift" "1")
 713    (set_attr "length" "2")
 714    (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
 715                       (const_string "alu_shift")
 716                       (const_string "alu_shift_reg")))]
 717 )
 718
 719 ;; 16-bit load immediate
 720 (define_peephole2
 721   [(set (match_operand:QHSI 0 "low_register_operand" "")
 722         (match_operand:QHSI 1 "const_int_operand" ""))]
 723   "TARGET_THUMB2
 724    && peep2_regno_dead_p(0, CC_REGNUM)
 725    && (unsigned HOST_WIDE_INT) INTVAL(operands[1]) < 256"
 726   [(parallel
 727     [(set (match_dup 0)
 728           (match_dup 1))
 729      (clobber (reg:CC CC_REGNUM))])]
 730   ""
 731 )
 732
 733 (define_insn "*thumb2_mov<mode>_shortim"
 734   [(set (match_operand:QHSI 0 "low_register_operand" "=l")
 735         (match_operand:QHSI 1 "const_int_operand" "I"))
 736    (clobber (reg:CC CC_REGNUM))]
 737   "TARGET_THUMB2 && reload_completed"
 738   "mov%!\t%0, %1"
 739   [(set_attr "predicable" "yes")
 740    (set_attr "length" "2")]
 741 )
 742
 743 ;; 16-bit add/sub immediate
 744 (define_peephole2
 745   [(set (match_operand:SI 0 "low_register_operand" "")
 746         (plus:SI (match_operand:SI 1 "low_register_operand" "")
 747                  (match_operand:SI 2 "const_int_operand" "")))]
 748   "TARGET_THUMB2
 749    && peep2_regno_dead_p(0, CC_REGNUM)
 750    && ((rtx_equal_p(operands[0], operands[1])
 751         && INTVAL(operands[2]) > -256 && INTVAL(operands[2]) < 256)
 752        || (INTVAL(operands[2]) > -8 && INTVAL(operands[2]) < 8))"
 753   [(parallel
 754     [(set (match_dup 0)
 755           (plus:SI (match_dup 1)
 756                    (match_dup 2)))
 757      (clobber (reg:CC CC_REGNUM))])]
 758   ""
 759 )
 760
 761 (define_insn "*thumb2_addsi_short"
 762   [(set (match_operand:SI 0 "low_register_operand" "=l,l")
 763         (plus:SI (match_operand:SI 1 "low_register_operand" "l,0")
 764                  (match_operand:SI 2 "low_reg_or_int_operand" "lPt,Ps")))
 765    (clobber (reg:CC CC_REGNUM))]
 766   "TARGET_THUMB2 && reload_completed"
 767   "*
 768     HOST_WIDE_INT val;
 769
 770     if (GET_CODE (operands[2]) == CONST_INT)
 771       val = INTVAL(operands[2]);
 772     else
 773       val = 0;
 774
 775     /* We prefer eg. subs rn, rn, #1 over adds rn, rn, #0xffffffff.  */
 776     if (val < 0 && const_ok_for_arm(ARM_SIGN_EXTEND (-val)))
 777       return \"sub%!\\t%0, %1, #%n2\";
 778     else
 779       return \"add%!\\t%0, %1, %2\";
 780   "
 781   [(set_attr "predicable" "yes")
 782    (set_attr "length" "2")]
 783 )
 784
 785 (define_insn "*thumb2_subsi_short"
 786   [(set (match_operand:SI 0 "low_register_operand" "=l")
 787         (minus:SI (match_operand:SI 1 "low_register_operand" "l")
 788                   (match_operand:SI 2 "low_register_operand" "l")))
 789    (clobber (reg:CC CC_REGNUM))]
 790   "TARGET_THUMB2 && reload_completed"
 791   "sub%!\\t%0, %1, %2"
 792   [(set_attr "predicable" "yes")
 793    (set_attr "length" "2")]
 794 )
 795
 796 (define_peephole2
 797   [(set (match_operand:CC 0 "cc_register" "")
 798         (compare:CC (match_operand:SI 1 "low_register_operand" "")
 799                     (match_operand:SI 2 "const_int_operand" "")))]
 800   "TARGET_THUMB2
 801    && peep2_reg_dead_p (1, operands[1])
 802    && satisfies_constraint_Pw (operands[2])"
 803   [(parallel
 804     [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
 805      (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 3)))])]
 806   "operands[3] = GEN_INT (- INTVAL (operands[2]));"
 807 )
 808
 809 (define_peephole2
 810   [(match_scratch:SI 3 "l")
 811    (set (match_operand:CC 0 "cc_register" "")
 812         (compare:CC (match_operand:SI 1 "low_register_operand" "")
 813                     (match_operand:SI 2 "const_int_operand" "")))]
 814   "TARGET_THUMB2
 815    && satisfies_constraint_Px (operands[2])"
 816   [(parallel
 817     [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
 818      (set (match_dup 3) (plus:SI (match_dup 1) (match_dup 4)))])]
 819   "operands[4] = GEN_INT (- INTVAL (operands[2]));"
 820 )
 821
 822 (define_insn "thumb2_addsi3_compare0"
 823   [(set (reg:CC_NOOV CC_REGNUM)
 824         (compare:CC_NOOV
 825           (plus:SI (match_operand:SI 1 "s_register_operand" "l,  0, r")
 826                    (match_operand:SI 2 "arm_add_operand"    "lPt,Ps,rIL"))
 827           (const_int 0)))
 828    (set (match_operand:SI 0 "s_register_operand" "=l,l,r")
 829         (plus:SI (match_dup 1) (match_dup 2)))]
 830   "TARGET_THUMB2"
 831   "*
 832     HOST_WIDE_INT val;
 833
 834     if (GET_CODE (operands[2]) == CONST_INT)
 835       val = INTVAL (operands[2]);
 836     else
 837       val = 0;
 838
 839     if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
 840       return \"subs\\t%0, %1, #%n2\";
 841     else
 842       return \"adds\\t%0, %1, %2\";
 843   "
 844   [(set_attr "conds" "set")
 845    (set_attr "length" "2,2,4")]
 846 )
 847
 848 (define_insn "*thumb2_addsi3_compare0_scratch"
 849   [(set (reg:CC_NOOV CC_REGNUM)
 850         (compare:CC_NOOV
 851           (plus:SI (match_operand:SI 0 "s_register_operand" "l,  r")
 852                    (match_operand:SI 1 "arm_add_operand"    "lPv,rIL"))
 853           (const_int 0)))]
 854   "TARGET_THUMB2"
 855   "*
 856     HOST_WIDE_INT val;
 857
 858     if (GET_CODE (operands[1]) == CONST_INT)
 859       val = INTVAL (operands[1]);
 860     else
 861       val = 0;
 862
 863     if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
 864       return \"cmp\\t%0, #%n1\";
 865     else
 866       return \"cmn\\t%0, %1\";
 867   "
 868   [(set_attr "conds" "set")
 869    (set_attr "length" "2,4")]
 870 )
 871
 872 ;; 16-bit encodings of "muls" and "mul<c>".  We only use these when
 873 ;; optimizing for size since "muls" is slow on all known
 874 ;; implementations and since "mul<c>" will be generated by
 875 ;; "*arm_mulsi3_v6" anyhow.  The assembler will use a 16-bit encoding
 876 ;; for "mul<c>" whenever possible anyhow.
 877 (define_peephole2
 878   [(set (match_operand:SI 0 "low_register_operand" "")
 879         (mult:SI (match_operand:SI 1 "low_register_operand" "")
 880                  (match_dup 0)))]
 881   "TARGET_THUMB2 && optimize_size && peep2_regno_dead_p (0, CC_REGNUM)"
 882   [(parallel
 883     [(set (match_dup 0)
 884            (mult:SI (match_dup 0) (match_dup 1)))
 885      (clobber (reg:CC CC_REGNUM))])]
 886   ""
 887 )
 888
 889 (define_peephole2
 890   [(set (match_operand:SI 0 "low_register_operand" "")
 891         (mult:SI (match_dup 0)
 892                  (match_operand:SI 1 "low_register_operand" "")))]
 893   "TARGET_THUMB2 && optimize_size && peep2_regno_dead_p (0, CC_REGNUM)"
 894   [(parallel
 895     [(set (match_dup 0)
 896            (mult:SI (match_dup 0) (match_dup 1)))
 897      (clobber (reg:CC CC_REGNUM))])]
 898   ""
 899 )
 900
 901 (define_insn "*thumb2_mulsi_short"
 902   [(set (match_operand:SI 0 "low_register_operand" "=l")
 903         (mult:SI (match_operand:SI 1 "low_register_operand" "%0")
 904                  (match_operand:SI 2 "low_register_operand" "l")))
 905    (clobber (reg:CC CC_REGNUM))]
 906   "TARGET_THUMB2 && optimize_size && reload_completed"
 907   "mul%!\\t%0, %2, %0"
 908   [(set_attr "predicable" "yes")
 909    (set_attr "length" "2")
 910    (set_attr "insn" "muls")])
 911
 912 (define_insn "*thumb2_mulsi_short_compare0"
 913   [(set (reg:CC_NOOV CC_REGNUM)
 914         (compare:CC_NOOV
 915          (mult:SI (match_operand:SI 1 "register_operand" "%0")
 916                   (match_operand:SI 2 "register_operand" "l"))
 917          (const_int 0)))
 918    (set (match_operand:SI 0 "register_operand" "=l")
 919         (mult:SI (match_dup 1) (match_dup 2)))]
 920   "TARGET_THUMB2 && optimize_size"
 921   "muls\\t%0, %2, %0"
 922   [(set_attr "length" "2")
 923    (set_attr "insn" "muls")])
 924
 925 (define_insn "*thumb2_mulsi_short_compare0_scratch"
 926   [(set (reg:CC_NOOV CC_REGNUM)
 927         (compare:CC_NOOV
 928          (mult:SI (match_operand:SI 1 "register_operand" "%0")
 929                   (match_operand:SI 2 "register_operand" "l"))
 930          (const_int 0)))
 931    (clobber (match_scratch:SI 0 "=l"))]
 932   "TARGET_THUMB2 && optimize_size"
 933   "muls\\t%0, %2, %0"
 934   [(set_attr "length" "2")
 935    (set_attr "insn" "muls")])
 936
 937 (define_insn "*thumb2_cbz"
 938   [(set (pc) (if_then_else
 939               (eq (match_operand:SI 0 "s_register_operand" "l,?r")
 940                   (const_int 0))
 941               (label_ref (match_operand 1 "" ""))
 942               (pc)))
 943    (clobber (reg:CC CC_REGNUM))]
 944   "TARGET_THUMB2"
 945   "*
 946   if (get_attr_length (insn) == 2)
 947     return \"cbz\\t%0, %l1\";
 948   else
 949     return \"cmp\\t%0, #0\;beq\\t%l1\";
 950   "
 951   [(set (attr "length")
 952         (if_then_else
 953             (and (ge (minus (match_dup 1) (pc)) (const_int 2))
 954                  (le (minus (match_dup 1) (pc)) (const_int 128))
 955                  (not (match_test "which_alternative")))
 956             (const_int 2)
 957             (const_int 8)))]
 958 )
 959
 960 (define_insn "*thumb2_cbnz"
 961   [(set (pc) (if_then_else
 962               (ne (match_operand:SI 0 "s_register_operand" "l,?r")
 963                   (const_int 0))
 964               (label_ref (match_operand 1 "" ""))
 965               (pc)))
 966    (clobber (reg:CC CC_REGNUM))]
 967   "TARGET_THUMB2"
 968   "*
 969   if (get_attr_length (insn) == 2)
 970     return \"cbnz\\t%0, %l1\";
 971   else
 972     return \"cmp\\t%0, #0\;bne\\t%l1\";
 973   "
 974   [(set (attr "length")
 975         (if_then_else
 976             (and (ge (minus (match_dup 1) (pc)) (const_int 2))
 977                  (le (minus (match_dup 1) (pc)) (const_int 128))
 978                  (not (match_test "which_alternative")))
 979             (const_int 2)
 980             (const_int 8)))]
 981 )
 982
 983 ;; 16-bit complement
 984 (define_peephole2
 985   [(set (match_operand:SI 0 "low_register_operand" "")
 986         (not:SI (match_operand:SI 1 "low_register_operand" "")))]
 987   "TARGET_THUMB2
 988    && peep2_regno_dead_p(0, CC_REGNUM)"
 989   [(parallel
 990     [(set (match_dup 0)
 991           (not:SI (match_dup 1)))
 992      (clobber (reg:CC CC_REGNUM))])]
 993   ""
 994 )
 995
 996 (define_insn "*thumb2_one_cmplsi2_short"
 997   [(set (match_operand:SI 0 "low_register_operand" "=l")
 998         (not:SI (match_operand:SI 1 "low_register_operand" "l")))
 999    (clobber (reg:CC CC_REGNUM))]
1000   "TARGET_THUMB2 && reload_completed"
1001   "mvn%!\t%0, %1"
1002   [(set_attr "predicable" "yes")
1003    (set_attr "length" "2")]
1004 )
1005
1006 ;; 16-bit negate
1007 (define_peephole2
1008   [(set (match_operand:SI 0 "low_register_operand" "")
1009         (neg:SI (match_operand:SI 1 "low_register_operand" "")))]
1010   "TARGET_THUMB2
1011    && peep2_regno_dead_p(0, CC_REGNUM)"
1012   [(parallel
1013     [(set (match_dup 0)
1014           (neg:SI (match_dup 1)))
1015      (clobber (reg:CC CC_REGNUM))])]
1016   ""
1017 )
1018
1019 (define_insn "*thumb2_negsi2_short"
1020   [(set (match_operand:SI 0 "low_register_operand" "=l")
1021         (neg:SI (match_operand:SI 1 "low_register_operand" "l")))
1022    (clobber (reg:CC CC_REGNUM))]
1023   "TARGET_THUMB2 && reload_completed"
1024   "neg%!\t%0, %1"
1025   [(set_attr "predicable" "yes")
1026    (set_attr "length" "2")]
1027 )
1028
1029 (define_insn "*orsi_notsi_si"
1030   [(set (match_operand:SI 0 "s_register_operand" "=r")
1031         (ior:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
1032                 (match_operand:SI 1 "s_register_operand" "r")))]
1033   "TARGET_THUMB2"
1034   "orn%?\\t%0, %1, %2"
1035   [(set_attr "predicable" "yes")]
1036 )
1037
1038 (define_insn "*orsi_not_shiftsi_si"
1039   [(set (match_operand:SI 0 "s_register_operand" "=r")
1040         (ior:SI (not:SI (match_operator:SI 4 "shift_operator"
1041                          [(match_operand:SI 2 "s_register_operand" "r")
1042                           (match_operand:SI 3 "const_int_operand" "M")]))
1043                 (match_operand:SI 1 "s_register_operand" "r")))]
1044   "TARGET_THUMB2"
1045   "orn%?\\t%0, %1, %2%S4"
1046   [(set_attr "predicable" "yes")
1047    (set_attr "shift" "2")
1048    (set_attr "type" "alu_shift")]
1049 )
1050
1051 (define_peephole2
1052   [(set (match_operand:CC_NOOV 0 "cc_register" "")
1053         (compare:CC_NOOV (zero_extract:SI
1054                           (match_operand:SI 1 "low_register_operand" "")
1055                           (const_int 1)
1056                           (match_operand:SI 2 "const_int_operand" ""))
1057                          (const_int 0)))
1058    (match_scratch:SI 3 "l")
1059    (set (pc)
1060         (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
1061                        [(match_dup 0) (const_int 0)])
1062                       (match_operand 5 "" "")
1063                       (match_operand 6 "" "")))]
1064   "TARGET_THUMB2
1065    && (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32)"
1066   [(parallel [(set (match_dup 0)
1067                    (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
1068                                     (const_int 0)))
1069               (clobber (match_dup 3))])
1070    (set (pc)
1071         (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1072                       (match_dup 5) (match_dup 6)))]
1073   "
1074   operands[2] = GEN_INT (31 - INTVAL (operands[2]));
1075   operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? LT : GE,
1076                                 VOIDmode, operands[0], const0_rtx);
1077   ")
1078
1079 (define_peephole2
1080   [(set (match_operand:CC_NOOV 0 "cc_register" "")
1081         (compare:CC_NOOV (zero_extract:SI
1082                           (match_operand:SI 1 "low_register_operand" "")
1083                           (match_operand:SI 2 "const_int_operand" "")
1084                           (const_int 0))
1085                          (const_int 0)))
1086    (match_scratch:SI 3 "l")
1087    (set (pc)
1088         (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
1089                        [(match_dup 0) (const_int 0)])
1090                       (match_operand 5 "" "")
1091                       (match_operand 6 "" "")))]
1092   "TARGET_THUMB2
1093    && (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 32)"
1094   [(parallel [(set (match_dup 0)
1095                    (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
1096                                     (const_int 0)))
1097               (clobber (match_dup 3))])
1098    (set (pc)
1099         (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1100                       (match_dup 5) (match_dup 6)))]
1101   "
1102   operands[2] = GEN_INT (32 - INTVAL (operands[2]));
1103   ")
1104
1105 ;; Define the subtract-one-and-jump insns so loop.c
1106 ;; knows what to generate.
1107 (define_expand "doloop_end"
1108   [(use (match_operand 0 "" ""))      ; loop pseudo
1109    (use (match_operand 1 "" ""))      ; iterations; zero if unknown
1110    (use (match_operand 2 "" ""))      ; max iterations
1111    (use (match_operand 3 "" ""))      ; loop level
1112    (use (match_operand 4 "" ""))]     ; label
1113   "TARGET_32BIT"
1114   "
1115  {
1116    /* Currently SMS relies on the do-loop pattern to recognize loops
1117       where (1) the control part consists of all insns defining and/or
1118       using a certain 'count' register and (2) the loop count can be
1119       adjusted by modifying this register prior to the loop.
1120       ??? The possible introduction of a new block to initialize the
1121       new IV can potentially affect branch optimizations.  */
1122    if (optimize > 0 && flag_modulo_sched)
1123    {
1124      rtx s0;
1125      rtx bcomp;
1126      rtx loc_ref;
1127      rtx cc_reg;
1128      rtx insn;
1129      rtx cmp;
1130
1131      /* Only use this on innermost loops.  */
1132      if (INTVAL (operands[3]) > 1)
1133        FAIL;
1134
1135      if (GET_MODE (operands[0]) != SImode)
1136        FAIL;
1137
1138      s0 = operands [0];
1139      if (TARGET_THUMB2)
1140        insn = emit_insn (gen_thumb2_addsi3_compare0 (s0, s0, GEN_INT (-1)));
1141      else
1142        insn = emit_insn (gen_addsi3_compare0 (s0, s0, GEN_INT (-1)));
1143
1144      cmp = XVECEXP (PATTERN (insn), 0, 0);
1145      cc_reg = SET_DEST (cmp);
1146      bcomp = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx);
1147      loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [4]);
1148      emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
1149                                   gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
1150                                                         loc_ref, pc_rtx)));
1151      DONE;
1152    }else
1153       FAIL;
1154  }")
1155