gcc/config/arm/thumb2.md

   1 ;; ARM Thumb-2 Machine Description
   2 ;; Copyright (C) 2007-2015 Free Software Foundation, Inc.
   3 ;; Written by CodeSourcery, LLC.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.  */
  20
  21 ;; Note: Thumb-2 is the variant of the Thumb architecture that adds
  22 ;; 32-bit encodings of [almost all of] the Arm instruction set.
  23 ;; Some old documents refer to the relatively minor interworking
  24 ;; changes made in armv5t as "thumb2".  These are considered part
  25 ;; the 16-bit Thumb-1 instruction set.
  26
  27 ;; Thumb-2 only allows shift by constant on data processing instructions
  28 (define_insn "*thumb_andsi_not_shiftsi_si"
  29   [(set (match_operand:SI 0 "s_register_operand" "=r")
  30         (and:SI (not:SI (match_operator:SI 4 "shift_operator"
  31                          [(match_operand:SI 2 "s_register_operand" "r")
  32                           (match_operand:SI 3 "const_int_operand" "M")]))
  33                 (match_operand:SI 1 "s_register_operand" "r")))]
  34   "TARGET_THUMB2"
  35   "bic%?\\t%0, %1, %2%S4"
  36   [(set_attr "predicable" "yes")
  37    (set_attr "predicable_short_it" "no")
  38    (set_attr "shift" "2")
  39    (set_attr "type" "alu_shift_imm")]
  40 )
  41
  42 ;; We use the '0' constraint for operand 1 because reload should
  43 ;; be smart enough to generate an appropriate move for the r/r/r case.
  44 (define_insn_and_split "*thumb2_smaxsi3"
  45   [(set (match_operand:SI          0 "s_register_operand" "=r,l,r")
  46         (smax:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
  47                  (match_operand:SI 2 "arm_rhs_operand"    "r,Py,I")))
  48    (clobber (reg:CC CC_REGNUM))]
  49    "TARGET_THUMB2"
  50    "#"
  51    ; cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2
  52   "TARGET_THUMB2 && reload_completed"
  53   [(set (reg:CC CC_REGNUM)
  54         (compare:CC (match_dup 1) (match_dup 2)))
  55    (cond_exec (lt:SI (reg:CC CC_REGNUM) (const_int 0))
  56               (set (match_dup 0)
  57                    (match_dup 2)))]
  58   ""
  59   [(set_attr "conds" "clob")
  60    (set_attr "enabled_for_depr_it" "yes,yes,no")
  61    (set_attr "length" "6,6,10")
  62    (set_attr "type" "multiple")]
  63 )
  64
  65 (define_insn_and_split "*thumb2_sminsi3"
  66   [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
  67         (smin:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
  68                  (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
  69    (clobber (reg:CC CC_REGNUM))]
  70   "TARGET_THUMB2"
  71   "#"
  72   ; cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2
  73   "TARGET_THUMB2 && reload_completed"
  74   [(set (reg:CC CC_REGNUM)
  75         (compare:CC (match_dup 1) (match_dup 2)))
  76    (cond_exec (ge:SI (reg:CC CC_REGNUM) (const_int 0))
  77               (set (match_dup 0)
  78                    (match_dup 2)))]
  79   ""
  80   [(set_attr "conds" "clob")
  81    (set_attr "enabled_for_depr_it" "yes,yes,no")
  82    (set_attr "length" "6,6,10")
  83    (set_attr "type" "multiple")]
  84 )
  85
  86 (define_insn_and_split "*thumb32_umaxsi3"
  87   [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
  88         (umax:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
  89                  (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
  90   (clobber (reg:CC CC_REGNUM))]
  91   "TARGET_THUMB2"
  92   "#"
  93   ; cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2
  94   "TARGET_THUMB2 && reload_completed"
  95   [(set (reg:CC CC_REGNUM)
  96         (compare:CC (match_dup 1) (match_dup 2)))
  97    (cond_exec (ltu:SI (reg:CC CC_REGNUM) (const_int 0))
  98               (set (match_dup 0)
  99                    (match_dup 2)))]
 100   ""
 101   [(set_attr "conds" "clob")
 102    (set_attr "length" "6,6,10")
 103    (set_attr "enabled_for_depr_it" "yes,yes,no")
 104    (set_attr "type" "multiple")]
 105 )
 106
 107 (define_insn_and_split "*thumb2_uminsi3"
 108   [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
 109         (umin:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
 110                  (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
 111    (clobber (reg:CC CC_REGNUM))]
 112   "TARGET_THUMB2"
 113   "#"
 114   ; cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2
 115   "TARGET_THUMB2 && reload_completed"
 116   [(set (reg:CC CC_REGNUM)
 117         (compare:CC (match_dup 1) (match_dup 2)))
 118    (cond_exec (geu:SI (reg:CC CC_REGNUM) (const_int 0))
 119               (set (match_dup 0)
 120                    (match_dup 2)))]
 121   ""
 122   [(set_attr "conds" "clob")
 123    (set_attr "length" "6,6,10")
 124    (set_attr "enabled_for_depr_it" "yes,yes,no")
 125    (set_attr "type" "multiple")]
 126 )
 127
 128 ;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
 129 (define_insn_and_split "*thumb2_negdi2"
 130   [(set (match_operand:DI         0 "s_register_operand" "=&r,r")
 131         (neg:DI (match_operand:DI 1 "s_register_operand"  "?r,0")))
 132    (clobber (reg:CC CC_REGNUM))]
 133   "TARGET_THUMB2"
 134   "#" ; negs\\t%Q0, %Q1\;sbc\\t%R0, %R1, %R1, lsl #1
 135   "&& reload_completed"
 136   [(parallel [(set (reg:CC CC_REGNUM)
 137                    (compare:CC (const_int 0) (match_dup 1)))
 138               (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))])
 139    (set (match_dup 2) (minus:SI (minus:SI (match_dup 3)
 140                                           (ashift:SI (match_dup 3)
 141                                                      (const_int 1)))
 142                                 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
 143   {
 144     operands[2] = gen_highpart (SImode, operands[0]);
 145     operands[0] = gen_lowpart (SImode, operands[0]);
 146     operands[3] = gen_highpart (SImode, operands[1]);
 147     operands[1] = gen_lowpart (SImode, operands[1]);
 148   }
 149   [(set_attr "conds" "clob")
 150    (set_attr "length" "8")
 151    (set_attr "type" "multiple")]
 152 )
 153
 154 (define_insn_and_split "*thumb2_abssi2"
 155   [(set (match_operand:SI         0 "s_register_operand" "=&r,l,r")
 156         (abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0")))
 157    (clobber (reg:CC CC_REGNUM))]
 158   "TARGET_THUMB2"
 159   "#"
 160    ; eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31
 161    ; cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
 162    ; cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
 163   "&& reload_completed"
 164   [(const_int 0)]
 165   {
 166     if (REGNO(operands[0]) == REGNO(operands[1]))
 167       {
 168        rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
 169
 170        emit_insn (gen_rtx_SET (VOIDmode,
 171                                cc_reg,
 172                                gen_rtx_COMPARE (CCmode, operands[0], const0_rtx)));
 173        emit_insn (gen_rtx_COND_EXEC (VOIDmode,
 174                                     (gen_rtx_LT (SImode,
 175                                                  cc_reg,
 176                                                  const0_rtx)),
 177                                     (gen_rtx_SET (VOIDmode,
 178                                                   operands[0],
 179                                                   (gen_rtx_MINUS (SImode,
 180                                                                   const0_rtx,
 181                                                                   operands[1]))))));
 182       }
 183     else
 184       {
 185         emit_insn (gen_rtx_SET (VOIDmode,
 186                                 operands[0],
 187                                 gen_rtx_XOR (SImode,
 188                                              gen_rtx_ASHIFTRT (SImode,
 189                                                                operands[1],
 190                                                                GEN_INT (31)),
 191                                              operands[1])));
 192         emit_insn (gen_rtx_SET (VOIDmode,
 193                                 operands[0],
 194                                 gen_rtx_MINUS (SImode,
 195                                                operands[0],
 196                                                gen_rtx_ASHIFTRT (SImode,
 197                                                                  operands[1],
 198                                                                  GEN_INT (31)))));
 199       }
 200     DONE;
 201   }
 202   [(set_attr "conds" "*,clob,clob")
 203    (set_attr "shift" "1")
 204    (set_attr "predicable" "yes,no,no")
 205    (set_attr "predicable_short_it" "no")
 206    (set_attr "enabled_for_depr_it" "yes,yes,no")
 207    (set_attr "ce_count" "2")
 208    (set_attr "length" "8,6,10")
 209    (set_attr "type" "multiple")]
 210 )
 211
 212 (define_insn_and_split "*thumb2_neg_abssi2"
 213   [(set (match_operand:SI 0 "s_register_operand" "=&r,l,r")
 214         (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0"))))
 215    (clobber (reg:CC CC_REGNUM))]
 216   "TARGET_THUMB2"
 217   "#"
 218    ; eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31
 219    ; cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
 220    ; cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
 221   "&& reload_completed"
 222   [(const_int 0)]
 223   {
 224     if (REGNO(operands[0]) == REGNO(operands[1]))
 225       {
 226        rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
 227
 228        emit_insn (gen_rtx_SET (VOIDmode,
 229                                cc_reg,
 230                                gen_rtx_COMPARE (CCmode, operands[0], const0_rtx)));
 231        emit_insn (gen_rtx_COND_EXEC (VOIDmode,
 232                                     (gen_rtx_GT (SImode,
 233                                                  cc_reg,
 234                                                  const0_rtx)),
 235                                     (gen_rtx_SET (VOIDmode,
 236                                                   operands[0],
 237                                                   (gen_rtx_MINUS (SImode,
 238                                                                   const0_rtx,
 239                                                                   operands[1]))))));
 240       }
 241     else
 242       {
 243         emit_insn (gen_rtx_SET (VOIDmode,
 244                                 operands[0],
 245                                 gen_rtx_XOR (SImode,
 246                                              gen_rtx_ASHIFTRT (SImode,
 247                                                                operands[1],
 248                                                                GEN_INT (31)),
 249                                              operands[1])));
 250         emit_insn (gen_rtx_SET (VOIDmode,
 251                                 operands[0],
 252                                 gen_rtx_MINUS (SImode,
 253                                                gen_rtx_ASHIFTRT (SImode,
 254                                                                  operands[1],
 255                                                                  GEN_INT (31)),
 256                                                operands[0])));
 257       }
 258     DONE;
 259   }
 260   [(set_attr "conds" "*,clob,clob")
 261    (set_attr "shift" "1")
 262    (set_attr "predicable" "yes,no,no")
 263    (set_attr "enabled_for_depr_it" "yes,yes,no")
 264    (set_attr "predicable_short_it" "no")
 265    (set_attr "ce_count" "2")
 266    (set_attr "length" "8,6,10")
 267    (set_attr "type" "multiple")]
 268 )
 269
 270 ;; We have two alternatives here for memory loads (and similarly for stores)
 271 ;; to reflect the fact that the permissible constant pool ranges differ
 272 ;; between ldr instructions taking low regs and ldr instructions taking high
 273 ;; regs.  The high register alternatives are not taken into account when
 274 ;; choosing register preferences in order to reflect their expense.
 275 (define_insn "*thumb2_movsi_insn"
 276   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,l ,*hk,m,*m")
 277         (match_operand:SI 1 "general_operand"      "rk,I,Py,K,j,mi,*mi,l,*hk"))]
 278   "TARGET_THUMB2 && ! TARGET_IWMMXT
 279    && !(TARGET_HARD_FLOAT && TARGET_VFP)
 280    && (   register_operand (operands[0], SImode)
 281        || register_operand (operands[1], SImode))"
 282   "@
 283    mov%?\\t%0, %1
 284    mov%?\\t%0, %1
 285    mov%?\\t%0, %1
 286    mvn%?\\t%0, #%B1
 287    movw%?\\t%0, %1
 288    ldr%?\\t%0, %1
 289    ldr%?\\t%0, %1
 290    str%?\\t%1, %0
 291    str%?\\t%1, %0"
 292   [(set_attr "type" "mov_reg,alu_imm,alu_imm,alu_imm,mov_imm,load1,load1,store1,store1")
 293    (set_attr "length" "2,4,2,4,4,4,4,4,4")
 294    (set_attr "predicable" "yes")
 295    (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no")
 296    (set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*")
 297    (set_attr "neg_pool_range" "*,*,*,*,*,0,0,*,*")]
 298 )
 299
 300 (define_insn "tls_load_dot_plus_four"
 301   [(set (match_operand:SI 0 "register_operand" "=l,l,r,r")
 302         (mem:SI (unspec:SI [(match_operand:SI 2 "register_operand" "0,1,0,1")
 303                             (const_int 4)
 304                             (match_operand 3 "" "")]
 305                            UNSPEC_PIC_BASE)))
 306    (clobber (match_scratch:SI 1 "=X,l,X,r"))]
 307   "TARGET_THUMB2"
 308   "*
 309   (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
 310                              INTVAL (operands[3]));
 311   return \"add\\t%2, %|pc\;ldr%?\\t%0, [%2]\";
 312   "
 313   [(set_attr "length" "4,4,6,6")
 314    (set_attr "type" "multiple")]
 315 )
 316
 317 ;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
 318 ;; of the messiness associated with the ARM patterns.
 319 (define_insn "*thumb2_movhi_insn"
 320   [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,l,r,m,r")
 321         (match_operand:HI 1 "general_operand"      "rk,I,Py,n,r,m"))]
 322   "TARGET_THUMB2
 323   && (register_operand (operands[0], HImode)
 324      || register_operand (operands[1], HImode))"
 325   "@
 326    mov%?\\t%0, %1\\t%@ movhi
 327    mov%?\\t%0, %1\\t%@ movhi
 328    mov%?\\t%0, %1\\t%@ movhi
 329    movw%?\\t%0, %L1\\t%@ movhi
 330    str%(h%)\\t%1, %0\\t%@ movhi
 331    ldr%(h%)\\t%0, %1\\t%@ movhi"
 332   [(set_attr "type" "mov_reg,mov_imm,mov_imm,mov_imm,store1,load1")
 333    (set_attr "predicable" "yes")
 334    (set_attr "predicable_short_it" "yes,no,yes,no,no,no")
 335    (set_attr "length" "2,4,2,4,4,4")
 336    (set_attr "pool_range" "*,*,*,*,*,4094")
 337    (set_attr "neg_pool_range" "*,*,*,*,*,250")]
 338 )
 339
 340 (define_insn "*thumb2_storewb_pairsi"
 341   [(set (match_operand:SI 0 "register_operand" "=&kr")
 342         (plus:SI (match_operand:SI 1 "register_operand" "0")
 343                  (match_operand:SI 2 "const_int_operand" "n")))
 344    (set (mem:SI (plus:SI (match_dup 0) (match_dup 2)))
 345         (match_operand:SI 3 "register_operand" "r"))
 346    (set (mem:SI (plus:SI (match_dup 0)
 347                          (match_operand:SI 5 "const_int_operand" "n")))
 348         (match_operand:SI 4 "register_operand" "r"))]
 349   "TARGET_THUMB2
 350    && INTVAL (operands[5]) == INTVAL (operands[2]) + 4"
 351   "strd\\t%3, %4, [%0, %2]!"
 352   [(set_attr "type" "store2")]
 353 )
 354
 355 (define_insn "*thumb2_cmpsi_neg_shiftsi"
 356   [(set (reg:CC CC_REGNUM)
 357         (compare:CC (match_operand:SI 0 "s_register_operand" "r")
 358                     (neg:SI (match_operator:SI 3 "shift_operator"
 359                              [(match_operand:SI 1 "s_register_operand" "r")
 360                               (match_operand:SI 2 "const_int_operand" "M")]))))]
 361   "TARGET_THUMB2"
 362   "cmn%?\\t%0, %1%S3"
 363   [(set_attr "conds" "set")
 364    (set_attr "shift" "1")
 365    (set_attr "type" "alus_shift_imm")]
 366 )
 367
 368 (define_insn_and_split "*thumb2_mov_scc"
 369   [(set (match_operand:SI 0 "s_register_operand" "=l,r")
 370         (match_operator:SI 1 "arm_comparison_operator"
 371          [(match_operand 2 "cc_register" "") (const_int 0)]))]
 372   "TARGET_THUMB2"
 373   "#"   ; "ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
 374   "TARGET_THUMB2"
 375   [(set (match_dup 0)
 376         (if_then_else:SI (match_dup 1)
 377                          (const_int 1)
 378                          (const_int 0)))]
 379   ""
 380   [(set_attr "conds" "use")
 381    (set_attr "enabled_for_depr_it" "yes,no")
 382    (set_attr "length" "8,10")
 383    (set_attr "type" "multiple")]
 384 )
 385
 386 (define_insn_and_split "*thumb2_mov_negscc"
 387   [(set (match_operand:SI 0 "s_register_operand" "=r")
 388         (neg:SI (match_operator:SI 1 "arm_comparison_operator"
 389                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 390   "TARGET_THUMB2 && !arm_restrict_it"
 391   "#"   ; "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
 392   "TARGET_THUMB2"
 393   [(set (match_dup 0)
 394         (if_then_else:SI (match_dup 1)
 395                          (match_dup 3)
 396                          (const_int 0)))]
 397   {
 398     operands[3] = GEN_INT (~0);
 399   }
 400   [(set_attr "conds" "use")
 401    (set_attr "length" "10")
 402    (set_attr "type" "multiple")]
 403 )
 404
 405 (define_insn_and_split "*thumb2_mov_negscc_strict_it"
 406   [(set (match_operand:SI 0 "low_register_operand" "=l")
 407         (neg:SI (match_operator:SI 1 "arm_comparison_operator"
 408                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 409   "TARGET_THUMB2 && arm_restrict_it"
 410   "#"   ; ";mvn\\t%0, #0 ;it\\t%D1\;mov%D1\\t%0, #0\"
 411   "&& reload_completed"
 412   [(set (match_dup 0)
 413         (match_dup 3))
 414    (cond_exec (match_dup 4)
 415               (set (match_dup 0)
 416                    (const_int 0)))]
 417   {
 418     operands[3] = GEN_INT (~0);
 419     machine_mode mode = GET_MODE (operands[2]);
 420     enum rtx_code rc = GET_CODE (operands[1]);
 421
 422     if (mode == CCFPmode || mode == CCFPEmode)
 423       rc = reverse_condition_maybe_unordered (rc);
 424     else
 425       rc = reverse_condition (rc);
 426     operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
 427
 428   }
 429   [(set_attr "conds" "use")
 430    (set_attr "length" "8")
 431    (set_attr "type" "multiple")]
 432 )
 433
 434 (define_insn_and_split "*thumb2_mov_notscc"
 435   [(set (match_operand:SI 0 "s_register_operand" "=r")
 436         (not:SI (match_operator:SI 1 "arm_comparison_operator"
 437                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 438   "TARGET_THUMB2 && !arm_restrict_it"
 439   "#"   ; "ite\\t%D1\;mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1"
 440   "TARGET_THUMB2"
 441   [(set (match_dup 0)
 442         (if_then_else:SI (match_dup 1)
 443                          (match_dup 3)
 444                          (match_dup 4)))]
 445   {
 446     operands[3] = GEN_INT (~1);
 447     operands[4] = GEN_INT (~0);
 448   }
 449   [(set_attr "conds" "use")
 450    (set_attr "length" "10")
 451    (set_attr "type" "multiple")]
 452 )
 453
 454 (define_insn_and_split "*thumb2_mov_notscc_strict_it"
 455   [(set (match_operand:SI 0 "low_register_operand" "=l")
 456         (not:SI (match_operator:SI 1 "arm_comparison_operator"
 457                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 458   "TARGET_THUMB2 && arm_restrict_it"
 459   "#"   ; "mvn %0, #0 ; it%d1 ; lsl%d1 %0, %0, #1"
 460   "&& reload_completed"
 461   [(set (match_dup 0)
 462         (match_dup 3))
 463    (cond_exec (match_dup 4)
 464               (set (match_dup 0)
 465                    (ashift:SI (match_dup 0)
 466                               (const_int 1))))]
 467   {
 468     operands[3] = GEN_INT (~0);
 469     operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
 470                                   VOIDmode, operands[2], const0_rtx);
 471   }
 472   [(set_attr "conds" "use")
 473    (set_attr "length" "8")
 474    (set_attr "type" "multiple")]
 475 )
 476
 477 (define_insn_and_split "*thumb2_movsicc_insn"
 478   [(set (match_operand:SI 0 "s_register_operand" "=l,l,r,r,r,r,r,r,r,r,r")
 479         (if_then_else:SI
 480          (match_operator 3 "arm_comparison_operator"
 481           [(match_operand 4 "cc_register" "") (const_int 0)])
 482          (match_operand:SI 1 "arm_not_operand" "0 ,lPy,0 ,0,rI,K,rI,rI,K ,K,r")
 483          (match_operand:SI 2 "arm_not_operand" "lPy,0 ,rI,K,0 ,0,rI,K ,rI,K,r")))]
 484   "TARGET_THUMB2"
 485   "@
 486    it\\t%D3\;mov%D3\\t%0, %2
 487    it\\t%d3\;mov%d3\\t%0, %1
 488    it\\t%D3\;mov%D3\\t%0, %2
 489    it\\t%D3\;mvn%D3\\t%0, #%B2
 490    it\\t%d3\;mov%d3\\t%0, %1
 491    it\\t%d3\;mvn%d3\\t%0, #%B1
 492    #
 493    #
 494    #
 495    #
 496    #"
 497    ; alt 6: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
 498    ; alt 7: ite\\t%d3\;mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2
 499    ; alt 8: ite\\t%d3\;mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2
 500    ; alt 9: ite\\t%d3\;mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2
 501    ; alt 10: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
 502   "&& reload_completed"
 503   [(const_int 0)]
 504   {
 505     enum rtx_code rev_code;
 506     machine_mode mode;
 507     rtx rev_cond;
 508
 509     emit_insn (gen_rtx_COND_EXEC (VOIDmode,
 510                                   operands[3],
 511                                   gen_rtx_SET (VOIDmode,
 512                                                operands[0],
 513                                                operands[1])));
 514     rev_code = GET_CODE (operands[3]);
 515     mode = GET_MODE (operands[4]);
 516     if (mode == CCFPmode || mode == CCFPEmode)
 517       rev_code = reverse_condition_maybe_unordered (rev_code);
 518     else
 519       rev_code = reverse_condition (rev_code);
 520
 521     rev_cond = gen_rtx_fmt_ee (rev_code,
 522                                VOIDmode,
 523                                gen_rtx_REG (mode, CC_REGNUM),
 524                                const0_rtx);
 525     emit_insn (gen_rtx_COND_EXEC (VOIDmode,
 526                                   rev_cond,
 527                                   gen_rtx_SET (VOIDmode,
 528                                                operands[0],
 529                                                operands[2])));
 530     DONE;
 531   }
 532   [(set_attr "length" "4,4,6,6,6,6,10,10,10,10,6")
 533    (set_attr "enabled_for_depr_it" "yes,yes,no,no,no,no,no,no,no,no,yes")
 534    (set_attr "conds" "use")
 535    (set_attr "type" "multiple")]
 536 )
 537
 538 (define_insn "*thumb2_movsfcc_soft_insn"
 539   [(set (match_operand:SF 0 "s_register_operand" "=r,r")
 540         (if_then_else:SF (match_operator 3 "arm_comparison_operator"
 541                           [(match_operand 4 "cc_register" "") (const_int 0)])
 542                          (match_operand:SF 1 "s_register_operand" "0,r")
 543                          (match_operand:SF 2 "s_register_operand" "r,0")))]
 544   "TARGET_THUMB2 && TARGET_SOFT_FLOAT"
 545   "@
 546    it\\t%D3\;mov%D3\\t%0, %2
 547    it\\t%d3\;mov%d3\\t%0, %1"
 548   [(set_attr "length" "6,6")
 549    (set_attr "conds" "use")
 550    (set_attr "type" "multiple")]
 551 )
 552
 553 (define_insn "*call_reg_thumb2"
 554   [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
 555          (match_operand 1 "" ""))
 556    (use (match_operand 2 "" ""))
 557    (clobber (reg:SI LR_REGNUM))]
 558   "TARGET_THUMB2"
 559   "blx%?\\t%0"
 560   [(set_attr "type" "call")]
 561 )
 562
 563 (define_insn "*call_value_reg_thumb2"
 564   [(set (match_operand 0 "" "")
 565         (call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
 566               (match_operand 2 "" "")))
 567    (use (match_operand 3 "" ""))
 568    (clobber (reg:SI LR_REGNUM))]
 569   "TARGET_THUMB2"
 570   "blx\\t%1"
 571   [(set_attr "type" "call")]
 572 )
 573
 574 (define_insn "*thumb2_indirect_jump"
 575   [(set (pc)
 576         (match_operand:SI 0 "register_operand" "l*r"))]
 577   "TARGET_THUMB2"
 578   "bx\\t%0"
 579   [(set_attr "conds" "clob")
 580    (set_attr "type" "branch")]
 581 )
 582 ;; Don't define thumb2_load_indirect_jump because we can't guarantee label
 583 ;; addresses will have the thumb bit set correctly.
 584
 585
 586 (define_insn_and_split "*thumb2_and_scc"
 587   [(set (match_operand:SI 0 "s_register_operand" "=Ts")
 588         (and:SI (match_operator:SI 1 "arm_comparison_operator"
 589                  [(match_operand 2 "cc_register" "") (const_int 0)])
 590                 (match_operand:SI 3 "s_register_operand" "r")))]
 591   "TARGET_THUMB2"
 592   "#"   ; "and\\t%0, %3, #1\;it\\t%D1\;mov%D1\\t%0, #0"
 593   "&& reload_completed"
 594   [(set (match_dup 0)
 595         (and:SI (match_dup 3) (const_int 1)))
 596    (cond_exec (match_dup 4) (set (match_dup 0) (const_int 0)))]
 597   {
 598     machine_mode mode = GET_MODE (operands[2]);
 599     enum rtx_code rc = GET_CODE (operands[1]);
 600
 601     if (mode == CCFPmode || mode == CCFPEmode)
 602       rc = reverse_condition_maybe_unordered (rc);
 603     else
 604       rc = reverse_condition (rc);
 605     operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
 606   }
 607   [(set_attr "conds" "use")
 608    (set_attr "type" "multiple")
 609    (set (attr "length") (if_then_else (match_test "arm_restrict_it")
 610                                       (const_int 8)
 611                                       (const_int 10)))]
 612 )
 613
 614 (define_insn_and_split "*thumb2_ior_scc"
 615   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 616         (ior:SI (match_operator:SI 1 "arm_comparison_operator"
 617                  [(match_operand 2 "cc_register" "") (const_int 0)])
 618                 (match_operand:SI 3 "s_register_operand" "0,?r")))]
 619   "TARGET_THUMB2 && !arm_restrict_it"
 620   "@
 621    it\\t%d1\;orr%d1\\t%0, %3, #1
 622    #"
 623    ; alt 1: ite\\t%D1\;mov%D1\\t%0, %3\;orr%d1\\t%0, %3, #1
 624    "&& reload_completed
 625     && REGNO (operands [0]) != REGNO (operands[3])"
 626    [(cond_exec (match_dup 5) (set (match_dup 0) (match_dup 3)))
 627     (cond_exec (match_dup 4) (set (match_dup 0)
 628                                   (ior:SI (match_dup 3) (const_int 1))))]
 629   {
 630     machine_mode mode = GET_MODE (operands[2]);
 631     enum rtx_code rc = GET_CODE (operands[1]);
 632
 633     operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
 634     if (mode == CCFPmode || mode == CCFPEmode)
 635       rc = reverse_condition_maybe_unordered (rc);
 636     else
 637       rc = reverse_condition (rc);
 638     operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
 639   }
 640   [(set_attr "conds" "use")
 641    (set_attr "length" "6,10")
 642    (set_attr "type" "multiple")]
 643 )
 644
 645 (define_insn "*thumb2_ior_scc_strict_it"
 646   [(set (match_operand:SI 0 "s_register_operand" "=l,l")
 647         (ior:SI (match_operator:SI 2 "arm_comparison_operator"
 648                  [(match_operand 3 "cc_register" "") (const_int 0)])
 649                 (match_operand:SI 1 "s_register_operand" "0,?l")))]
 650   "TARGET_THUMB2 && arm_restrict_it"
 651   "@
 652    it\\t%d2\;mov%d2\\t%0, #1\;it\\t%d2\;orr%d2\\t%0, %1
 653    mov\\t%0, #1\;orr\\t%0, %1\;it\\t%D2\;mov%D2\\t%0, %1"
 654   [(set_attr "conds" "use")
 655    (set_attr "length" "8")
 656    (set_attr "type" "multiple")]
 657 )
 658
 659 (define_insn "*thumb2_cond_move"
 660   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
 661         (if_then_else:SI (match_operator 3 "equality_operator"
 662                           [(match_operator 4 "arm_comparison_operator"
 663                             [(match_operand 5 "cc_register" "") (const_int 0)])
 664                            (const_int 0)])
 665                          (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
 666                          (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))]
 667   "TARGET_THUMB2"
 668   "*
 669     if (GET_CODE (operands[3]) == NE)
 670       {
 671         if (which_alternative != 1)
 672           output_asm_insn (\"it\\t%D4\;mov%D4\\t%0, %2\", operands);
 673         if (which_alternative != 0)
 674           output_asm_insn (\"it\\t%d4\;mov%d4\\t%0, %1\", operands);
 675         return \"\";
 676       }
 677     switch (which_alternative)
 678       {
 679       case 0:
 680         output_asm_insn (\"it\\t%d4\", operands);
 681         break;
 682       case 1:
 683         output_asm_insn (\"it\\t%D4\", operands);
 684         break;
 685       case 2:
 686         if (arm_restrict_it)
 687           output_asm_insn (\"it\\t%D4\", operands);
 688         else
 689           output_asm_insn (\"ite\\t%D4\", operands);
 690         break;
 691       default:
 692         abort();
 693       }
 694     if (which_alternative != 0)
 695       {
 696         output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 697         if (arm_restrict_it && which_alternative == 2)
 698           output_asm_insn (\"it\\t%d4\", operands);
 699       }
 700     if (which_alternative != 1)
 701       output_asm_insn (\"mov%d4\\t%0, %2\", operands);
 702     return \"\";
 703   "
 704   [(set_attr "conds" "use")
 705    (set_attr "length" "6,6,10")
 706    (set_attr "type" "multiple")]
 707 )
 708
 709 (define_insn "*thumb2_cond_arith"
 710   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 711         (match_operator:SI 5 "shiftable_operator"
 712          [(match_operator:SI 4 "arm_comparison_operator"
 713            [(match_operand:SI 2 "s_register_operand" "r,r")
 714             (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
 715           (match_operand:SI 1 "s_register_operand" "0,?r")]))
 716    (clobber (reg:CC CC_REGNUM))]
 717   "TARGET_THUMB2 && !arm_restrict_it"
 718   "*
 719     if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
 720       return \"%i5\\t%0, %1, %2, lsr #31\";
 721
 722     output_asm_insn (\"cmp\\t%2, %3\", operands);
 723     if (GET_CODE (operands[5]) == AND)
 724       {
 725         output_asm_insn (\"ite\\t%D4\", operands);
 726         output_asm_insn (\"mov%D4\\t%0, #0\", operands);
 727       }
 728     else if (GET_CODE (operands[5]) == MINUS)
 729       {
 730         output_asm_insn (\"ite\\t%D4\", operands);
 731         output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands);
 732       }
 733     else if (which_alternative != 0)
 734       {
 735         output_asm_insn (\"ite\\t%D4\", operands);
 736         output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 737       }
 738     else
 739       output_asm_insn (\"it\\t%d4\", operands);
 740     return \"%i5%d4\\t%0, %1, #1\";
 741   "
 742   [(set_attr "conds" "clob")
 743    (set_attr "length" "14")
 744    (set_attr "type" "multiple")]
 745 )
 746
 747 (define_insn_and_split "*thumb2_cond_arith_strict_it"
 748   [(set (match_operand:SI 0 "s_register_operand" "=l")
 749         (match_operator:SI 5 "shiftable_operator_strict_it"
 750          [(match_operator:SI 4 "arm_comparison_operator"
 751            [(match_operand:SI 2 "s_register_operand" "r")
 752             (match_operand:SI 3 "arm_rhs_operand" "rI")])
 753           (match_operand:SI 1 "s_register_operand" "0")]))
 754    (clobber (reg:CC CC_REGNUM))]
 755   "TARGET_THUMB2 && arm_restrict_it"
 756   "#"
 757   "&& reload_completed"
 758   [(const_int 0)]
 759   {
 760     if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
 761       {
 762         /*  %i5 %0, %1, %2, lsr #31  */
 763         rtx shifted_op = gen_rtx_LSHIFTRT (SImode, operands[2], GEN_INT (31));
 764         rtx op = NULL_RTX;
 765
 766         switch (GET_CODE (operands[5]))
 767           {
 768           case AND:
 769             op = gen_rtx_AND (SImode, shifted_op, operands[1]);
 770             break;
 771            case PLUS:
 772             op = gen_rtx_PLUS (SImode, shifted_op, operands[1]);
 773             break;
 774           default: gcc_unreachable ();
 775           }
 776         emit_insn (gen_rtx_SET (VOIDmode, operands[0], op));
 777         DONE;
 778       }
 779
 780     /*  "cmp  %2, %3"  */
 781     emit_insn (gen_rtx_SET (VOIDmode,
 782                                gen_rtx_REG (CCmode, CC_REGNUM),
 783                                gen_rtx_COMPARE (CCmode, operands[2], operands[3])));
 784
 785     if (GET_CODE (operands[5]) == AND)
 786       {
 787         /*  %i5  %0, %1, #1
 788             it%D4
 789             mov%D4  %0, #0  */
 790         enum rtx_code rc = reverse_condition (GET_CODE (operands[4]));
 791         emit_insn (gen_rtx_SET (VOIDmode, operands[0], gen_rtx_AND (SImode, operands[1], GEN_INT (1))));
 792         emit_insn (gen_rtx_COND_EXEC (VOIDmode,
 793                                       gen_rtx_fmt_ee (rc, VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM), const0_rtx),
 794                                       gen_rtx_SET (VOIDmode, operands[0], const0_rtx)));
 795         DONE;
 796       }
 797     else
 798       {
 799         /*  it\\t%d4
 800             %i5%d4\\t%0, %1, #1   */
 801         emit_insn (gen_rtx_COND_EXEC (VOIDmode, gen_rtx_fmt_ee (GET_CODE (operands[4]),
 802                                                                 VOIDmode,
 803                                                                 gen_rtx_REG (CCmode, CC_REGNUM), const0_rtx),
 804                                                 gen_rtx_SET(VOIDmode, operands[0],
 805                                                             gen_rtx_PLUS (SImode,
 806                                                                           operands[1],
 807                                                                           GEN_INT (1)))));
 808         DONE;
 809       }
 810      FAIL;
 811   }
 812   [(set_attr "conds" "clob")
 813    (set_attr "length" "12")
 814    (set_attr "type" "multiple")]
 815 )
 816
 817 (define_insn "*thumb2_cond_sub"
 818   [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts")
 819         (minus:SI (match_operand:SI 1 "s_register_operand" "0,?Ts")
 820                   (match_operator:SI 4 "arm_comparison_operator"
 821                    [(match_operand:SI 2 "s_register_operand" "r,r")
 822                     (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
 823    (clobber (reg:CC CC_REGNUM))]
 824   "TARGET_THUMB2"
 825   "*
 826     output_asm_insn (\"cmp\\t%2, %3\", operands);
 827     if (which_alternative != 0)
 828       {
 829         if (arm_restrict_it)
 830           {
 831             output_asm_insn (\"mov\\t%0, %1\", operands);
 832             output_asm_insn (\"it\\t%d4\", operands);
 833           }
 834         else
 835         {
 836           output_asm_insn (\"ite\\t%D4\", operands);
 837           output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 838         }
 839       }
 840     else
 841       output_asm_insn (\"it\\t%d4\", operands);
 842     return \"sub%d4\\t%0, %1, #1\";
 843   "
 844   [(set_attr "conds" "clob")
 845    (set_attr "length" "10,14")
 846    (set_attr "type" "multiple")]
 847 )
 848
 849 (define_insn_and_split "*thumb2_negscc"
 850   [(set (match_operand:SI 0 "s_register_operand" "=Ts")
 851         (neg:SI (match_operator 3 "arm_comparison_operator"
 852                  [(match_operand:SI 1 "s_register_operand" "r")
 853                   (match_operand:SI 2 "arm_rhs_operand" "rI")])))
 854    (clobber (reg:CC CC_REGNUM))]
 855   "TARGET_THUMB2"
 856   "#"
 857   "&& reload_completed"
 858   [(const_int 0)]
 859   {
 860     rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
 861
 862     if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx)
 863       {
 864         /* Emit asr\\t%0, %1, #31 */
 865         emit_insn (gen_rtx_SET (VOIDmode,
 866                                 operands[0],
 867                                 gen_rtx_ASHIFTRT (SImode,
 868                                                   operands[1],
 869                                                   GEN_INT (31))));
 870         DONE;
 871       }
 872     else if (GET_CODE (operands[3]) == NE && !arm_restrict_it)
 873       {
 874         /* Emit subs\\t%0, %1, %2\;it\\tne\;mvnne\\t%0, #0 */
 875         if (CONST_INT_P (operands[2]))
 876           emit_insn (gen_cmpsi2_addneg (operands[0], operands[1], operands[2],
 877                                         GEN_INT (- INTVAL (operands[2]))));
 878         else
 879           emit_insn (gen_subsi3_compare (operands[0], operands[1], operands[2]));
 880
 881         emit_insn (gen_rtx_COND_EXEC (VOIDmode,
 882                                       gen_rtx_NE (SImode,
 883                                                   cc_reg,
 884                                                   const0_rtx),
 885                                       gen_rtx_SET (SImode,
 886                                                    operands[0],
 887                                                    GEN_INT (~0))));
 888         DONE;
 889       }
 890     else
 891       {
 892        /* Emit:  cmp\\t%1, %2\;mvn\\t%0, #0\;it\\t%D3\;mov%D3\\t%0, #0\;*/
 893        enum rtx_code rc = reverse_condition (GET_CODE (operands[3]));
 894        machine_mode mode = SELECT_CC_MODE (rc, operands[1], operands[2]);
 895        rtx tmp1 = gen_rtx_REG (mode, CC_REGNUM);
 896
 897        emit_insn (gen_rtx_SET (VOIDmode,
 898                                cc_reg,
 899                                gen_rtx_COMPARE (CCmode, operands[1], operands[2])));
 900
 901        emit_insn (gen_rtx_SET (VOIDmode, operands[0], GEN_INT (~0)));
 902
 903        emit_insn (gen_rtx_COND_EXEC (VOIDmode,
 904                                      gen_rtx_fmt_ee (rc,
 905                                                      VOIDmode,
 906                                                      tmp1,
 907                                                      const0_rtx),
 908                                      gen_rtx_SET (VOIDmode, operands[0], const0_rtx)));
 909        DONE;
 910       }
 911     FAIL;
 912   }
 913   [(set_attr "conds" "clob")
 914    (set_attr "length" "14")
 915    (set_attr "type" "multiple")]
 916 )
 917
 918 (define_insn "*thumb2_movcond"
 919   [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts,Ts")
 920         (if_then_else:SI
 921          (match_operator 5 "arm_comparison_operator"
 922           [(match_operand:SI 3 "s_register_operand" "r,r,r")
 923            (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
 924          (match_operand:SI 1 "arm_rhs_operand" "0,TsI,?TsI")
 925          (match_operand:SI 2 "arm_rhs_operand" "TsI,0,TsI")))
 926    (clobber (reg:CC CC_REGNUM))]
 927   "TARGET_THUMB2"
 928   "*
 929   if (GET_CODE (operands[5]) == LT
 930       && (operands[4] == const0_rtx))
 931     {
 932       if (which_alternative != 1 && REG_P (operands[1]))
 933         {
 934           if (operands[2] == const0_rtx)
 935             return \"and\\t%0, %1, %3, asr #31\";
 936           return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\";
 937         }
 938       else if (which_alternative != 0 && REG_P (operands[2]))
 939         {
 940           if (operands[1] == const0_rtx)
 941             return \"bic\\t%0, %2, %3, asr #31\";
 942           return \"bics\\t%0, %2, %3, asr #32\;it\\tcs\;movcs\\t%0, %1\";
 943         }
 944       /* The only case that falls through to here is when both ops 1 & 2
 945          are constants.  */
 946     }
 947
 948   if (GET_CODE (operands[5]) == GE
 949       && (operands[4] == const0_rtx))
 950     {
 951       if (which_alternative != 1 && REG_P (operands[1]))
 952         {
 953           if (operands[2] == const0_rtx)
 954             return \"bic\\t%0, %1, %3, asr #31\";
 955           return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\";
 956         }
 957       else if (which_alternative != 0 && REG_P (operands[2]))
 958         {
 959           if (operands[1] == const0_rtx)
 960             return \"and\\t%0, %2, %3, asr #31\";
 961           return \"ands\\t%0, %2, %3, asr #32\;it\tcc\;movcc\\t%0, %1\";
 962         }
 963       /* The only case that falls through to here is when both ops 1 & 2
 964          are constants.  */
 965     }
 966   if (CONST_INT_P (operands[4])
 967       && !const_ok_for_arm (INTVAL (operands[4])))
 968     output_asm_insn (\"cmn\\t%3, #%n4\", operands);
 969   else
 970     output_asm_insn (\"cmp\\t%3, %4\", operands);
 971   switch (which_alternative)
 972     {
 973     case 0:
 974       output_asm_insn (\"it\\t%D5\", operands);
 975       break;
 976     case 1:
 977       output_asm_insn (\"it\\t%d5\", operands);
 978       break;
 979     case 2:
 980       if (arm_restrict_it)
 981         {
 982           output_asm_insn (\"mov\\t%0, %1\", operands);
 983           output_asm_insn (\"it\\t%D5\", operands);
 984         }
 985       else
 986         output_asm_insn (\"ite\\t%d5\", operands);
 987       break;
 988     default:
 989       abort();
 990     }
 991   if (which_alternative != 0 && !(arm_restrict_it && which_alternative == 2))
 992     output_asm_insn (\"mov%d5\\t%0, %1\", operands);
 993   if (which_alternative != 1)
 994     output_asm_insn (\"mov%D5\\t%0, %2\", operands);
 995   return \"\";
 996   "
 997   [(set_attr "conds" "clob")
 998    (set_attr "length" "10,10,14")
 999    (set_attr "type" "multiple")]
1000 )
1001
1002 ;; Zero and sign extension instructions.
1003
1004 ;; All supported Thumb2 implementations are armv6, so only that case is
1005 ;; provided.
1006 (define_insn "*thumb2_extendqisi_v6"
1007   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1008         (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1009   "TARGET_THUMB2 && arm_arch6"
1010   "@
1011    sxtb%?\\t%0, %1
1012    ldr%(sb%)\\t%0, %1"
1013   [(set_attr "type" "extend,load_byte")
1014    (set_attr "predicable" "yes")
1015    (set_attr "predicable_short_it" "no")
1016    (set_attr "pool_range" "*,4094")
1017    (set_attr "neg_pool_range" "*,250")]
1018 )
1019
1020 (define_insn "*thumb2_zero_extendhisi2_v6"
1021   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1022         (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1023   "TARGET_THUMB2 && arm_arch6"
1024   "@
1025    uxth%?\\t%0, %1
1026    ldr%(h%)\\t%0, %1"
1027   [(set_attr "type" "extend,load_byte")
1028    (set_attr "predicable" "yes")
1029    (set_attr "predicable_short_it" "no")
1030    (set_attr "pool_range" "*,4094")
1031    (set_attr "neg_pool_range" "*,250")]
1032 )
1033
1034 (define_insn "thumb2_zero_extendqisi2_v6"
1035   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1036         (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1037   "TARGET_THUMB2 && arm_arch6"
1038   "@
1039    uxtb%(%)\\t%0, %1
1040    ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
1041   [(set_attr "type" "extend,load_byte")
1042    (set_attr "predicable" "yes")
1043    (set_attr "predicable_short_it" "no")
1044    (set_attr "pool_range" "*,4094")
1045    (set_attr "neg_pool_range" "*,250")]
1046 )
1047
1048 (define_insn "thumb2_casesi_internal"
1049   [(parallel [(set (pc)
1050                (if_then_else
1051                 (leu (match_operand:SI 0 "s_register_operand" "r")
1052                      (match_operand:SI 1 "arm_rhs_operand" "rI"))
1053                 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
1054                                  (label_ref (match_operand 2 "" ""))))
1055                 (label_ref (match_operand 3 "" ""))))
1056               (clobber (reg:CC CC_REGNUM))
1057               (clobber (match_scratch:SI 4 "=&r"))
1058               (use (label_ref (match_dup 2)))])]
1059   "TARGET_THUMB2 && !flag_pic"
1060   "* return thumb2_output_casesi(operands);"
1061   [(set_attr "conds" "clob")
1062    (set_attr "length" "16")
1063    (set_attr "type" "multiple")]
1064 )
1065
1066 (define_insn "thumb2_casesi_internal_pic"
1067   [(parallel [(set (pc)
1068                (if_then_else
1069                 (leu (match_operand:SI 0 "s_register_operand" "r")
1070                      (match_operand:SI 1 "arm_rhs_operand" "rI"))
1071                 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
1072                                  (label_ref (match_operand 2 "" ""))))
1073                 (label_ref (match_operand 3 "" ""))))
1074               (clobber (reg:CC CC_REGNUM))
1075               (clobber (match_scratch:SI 4 "=&r"))
1076               (clobber (match_scratch:SI 5 "=r"))
1077               (use (label_ref (match_dup 2)))])]
1078   "TARGET_THUMB2 && flag_pic"
1079   "* return thumb2_output_casesi(operands);"
1080   [(set_attr "conds" "clob")
1081    (set_attr "length" "20")
1082    (set_attr "type" "multiple")]
1083 )
1084
1085 (define_insn "*thumb2_return"
1086   [(simple_return)]
1087   "TARGET_THUMB2"
1088   "* return output_return_instruction (const_true_rtx, true, false, true);"
1089   [(set_attr "type" "branch")
1090    (set_attr "length" "4")]
1091 )
1092
1093 (define_insn_and_split "thumb2_eh_return"
1094   [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
1095                     VUNSPEC_EH_RETURN)
1096    (clobber (match_scratch:SI 1 "=&r"))]
1097   "TARGET_THUMB2"
1098   "#"
1099   "&& reload_completed"
1100   [(const_int 0)]
1101   "
1102   {
1103     thumb_set_return_address (operands[0], operands[1]);
1104     DONE;
1105   }"
1106 )
1107
1108 (define_insn "*thumb2_alusi3_short"
1109   [(set (match_operand:SI          0 "s_register_operand" "=l")
1110         (match_operator:SI 3 "thumb_16bit_operator"
1111          [(match_operand:SI 1 "s_register_operand" "0")
1112           (match_operand:SI 2 "s_register_operand" "l")]))
1113    (clobber (reg:CC CC_REGNUM))]
1114   "TARGET_THUMB2 && reload_completed
1115    && GET_CODE(operands[3]) != PLUS
1116    && GET_CODE(operands[3]) != MINUS"
1117   "%I3%!\\t%0, %1, %2"
1118   [(set_attr "predicable" "yes")
1119    (set_attr "length" "2")
1120    (set_attr "type" "alu_sreg")]
1121 )
1122
1123 (define_insn "*thumb2_shiftsi3_short"
1124   [(set (match_operand:SI   0 "low_register_operand" "=l,l")
1125         (match_operator:SI  3 "shift_operator"
1126          [(match_operand:SI 1 "low_register_operand"  "0,l")
1127           (match_operand:SI 2 "low_reg_or_int_operand" "l,M")]))
1128    (clobber (reg:CC CC_REGNUM))]
1129   "TARGET_THUMB2 && reload_completed
1130    && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
1131        || REG_P (operands[2]))"
1132   "* return arm_output_shift(operands, 2);"
1133   [(set_attr "predicable" "yes")
1134    (set_attr "shift" "1")
1135    (set_attr "length" "2")
1136    (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
1137                       (const_string "alu_shift_imm")
1138                       (const_string "alu_shift_reg")))]
1139 )
1140
1141 (define_insn "*thumb2_mov<mode>_shortim"
1142   [(set (match_operand:QHSI 0 "low_register_operand" "=l")
1143         (match_operand:QHSI 1 "const_int_operand" "I"))
1144    (clobber (reg:CC CC_REGNUM))]
1145   "TARGET_THUMB2 && reload_completed"
1146   "mov%!\t%0, %1"
1147   [(set_attr "predicable" "yes")
1148    (set_attr "length" "2")
1149    (set_attr "type" "mov_imm")]
1150 )
1151
1152 (define_insn "*thumb2_addsi_short"
1153   [(set (match_operand:SI 0 "low_register_operand" "=l,l")
1154         (plus:SI (match_operand:SI 1 "low_register_operand" "l,0")
1155                  (match_operand:SI 2 "low_reg_or_int_operand" "lPt,Ps")))
1156    (clobber (reg:CC CC_REGNUM))]
1157   "TARGET_THUMB2 && reload_completed"
1158   "*
1159     HOST_WIDE_INT val;
1160
1161     if (CONST_INT_P (operands[2]))
1162       val = INTVAL(operands[2]);
1163     else
1164       val = 0;
1165
1166     /* We prefer eg. subs rn, rn, #1 over adds rn, rn, #0xffffffff.  */
1167     if (val < 0 && const_ok_for_arm(ARM_SIGN_EXTEND (-val)))
1168       return \"sub%!\\t%0, %1, #%n2\";
1169     else
1170       return \"add%!\\t%0, %1, %2\";
1171   "
1172   [(set_attr "predicable" "yes")
1173    (set_attr "length" "2")
1174    (set_attr "type" "alu_sreg")]
1175 )
1176
1177 (define_insn "*thumb2_subsi_short"
1178   [(set (match_operand:SI 0 "low_register_operand" "=l")
1179         (minus:SI (match_operand:SI 1 "low_register_operand" "l")
1180                   (match_operand:SI 2 "low_register_operand" "l")))
1181    (clobber (reg:CC CC_REGNUM))]
1182   "TARGET_THUMB2 && reload_completed"
1183   "sub%!\\t%0, %1, %2"
1184   [(set_attr "predicable" "yes")
1185    (set_attr "length" "2")
1186    (set_attr "type" "alu_sreg")]
1187 )
1188
1189 (define_peephole2
1190   [(set (match_operand:CC 0 "cc_register" "")
1191         (compare:CC (match_operand:SI 1 "low_register_operand" "")
1192                     (match_operand:SI 2 "const_int_operand" "")))]
1193   "TARGET_THUMB2
1194    && peep2_reg_dead_p (1, operands[1])
1195    && satisfies_constraint_Pw (operands[2])"
1196   [(parallel
1197     [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
1198      (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 3)))])]
1199   "operands[3] = GEN_INT (- INTVAL (operands[2]));"
1200 )
1201
1202 (define_peephole2
1203   [(match_scratch:SI 3 "l")
1204    (set (match_operand:CC 0 "cc_register" "")
1205         (compare:CC (match_operand:SI 1 "low_register_operand" "")
1206                     (match_operand:SI 2 "const_int_operand" "")))]
1207   "TARGET_THUMB2
1208    && satisfies_constraint_Px (operands[2])"
1209   [(parallel
1210     [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
1211      (set (match_dup 3) (plus:SI (match_dup 1) (match_dup 4)))])]
1212   "operands[4] = GEN_INT (- INTVAL (operands[2]));"
1213 )
1214
1215 (define_insn "thumb2_addsi3_compare0"
1216   [(set (reg:CC_NOOV CC_REGNUM)
1217         (compare:CC_NOOV
1218           (plus:SI (match_operand:SI 1 "s_register_operand" "l,  0, r")
1219                    (match_operand:SI 2 "arm_add_operand"    "lPt,Ps,rIL"))
1220           (const_int 0)))
1221    (set (match_operand:SI 0 "s_register_operand" "=l,l,r")
1222         (plus:SI (match_dup 1) (match_dup 2)))]
1223   "TARGET_THUMB2"
1224   "*
1225     HOST_WIDE_INT val;
1226
1227     if (CONST_INT_P (operands[2]))
1228       val = INTVAL (operands[2]);
1229     else
1230       val = 0;
1231
1232     if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
1233       return \"subs\\t%0, %1, #%n2\";
1234     else
1235       return \"adds\\t%0, %1, %2\";
1236   "
1237   [(set_attr "conds" "set")
1238    (set_attr "length" "2,2,4")
1239    (set_attr "type" "alu_sreg")]
1240 )
1241
1242 (define_insn "*thumb2_addsi3_compare0_scratch"
1243   [(set (reg:CC_NOOV CC_REGNUM)
1244         (compare:CC_NOOV
1245           (plus:SI (match_operand:SI 0 "s_register_operand" "l,l,  r,r")
1246                    (match_operand:SI 1 "arm_add_operand"    "Pv,l,IL,r"))
1247           (const_int 0)))]
1248   "TARGET_THUMB2"
1249   "*
1250     HOST_WIDE_INT val;
1251
1252     if (CONST_INT_P (operands[1]))
1253       val = INTVAL (operands[1]);
1254     else
1255       val = 0;
1256
1257     if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
1258       return \"cmp\\t%0, #%n1\";
1259     else
1260       return \"cmn\\t%0, %1\";
1261   "
1262   [(set_attr "conds" "set")
1263    (set_attr "length" "2,2,4,4")
1264    (set_attr "type" "alus_imm,alus_sreg,alus_imm,alus_sreg")]
1265 )
1266
1267 (define_insn "*thumb2_mulsi_short"
1268   [(set (match_operand:SI 0 "low_register_operand" "=l")
1269         (mult:SI (match_operand:SI 1 "low_register_operand" "%0")
1270                  (match_operand:SI 2 "low_register_operand" "l")))
1271    (clobber (reg:CC CC_REGNUM))]
1272   "TARGET_THUMB2 && optimize_size && reload_completed"
1273   "mul%!\\t%0, %2, %0"
1274   [(set_attr "predicable" "yes")
1275    (set_attr "length" "2")
1276    (set_attr "type" "muls")])
1277
1278 (define_insn "*thumb2_mulsi_short_compare0"
1279   [(set (reg:CC_NOOV CC_REGNUM)
1280         (compare:CC_NOOV
1281          (mult:SI (match_operand:SI 1 "register_operand" "%0")
1282                   (match_operand:SI 2 "register_operand" "l"))
1283          (const_int 0)))
1284    (set (match_operand:SI 0 "register_operand" "=l")
1285         (mult:SI (match_dup 1) (match_dup 2)))]
1286   "TARGET_THUMB2 && optimize_size"
1287   "muls\\t%0, %2, %0"
1288   [(set_attr "length" "2")
1289    (set_attr "type" "muls")])
1290
1291 (define_insn "*thumb2_mulsi_short_compare0_scratch"
1292   [(set (reg:CC_NOOV CC_REGNUM)
1293         (compare:CC_NOOV
1294          (mult:SI (match_operand:SI 1 "register_operand" "%0")
1295                   (match_operand:SI 2 "register_operand" "l"))
1296          (const_int 0)))
1297    (clobber (match_scratch:SI 0 "=l"))]
1298   "TARGET_THUMB2 && optimize_size"
1299   "muls\\t%0, %2, %0"
1300   [(set_attr "length" "2")
1301    (set_attr "type" "muls")])
1302
1303 (define_insn "*thumb2_cbz"
1304   [(set (pc) (if_then_else
1305               (eq (match_operand:SI 0 "s_register_operand" "l,?r")
1306                   (const_int 0))
1307               (label_ref (match_operand 1 "" ""))
1308               (pc)))
1309    (clobber (reg:CC CC_REGNUM))]
1310   "TARGET_THUMB2"
1311   "*
1312   if (get_attr_length (insn) == 2)
1313     return \"cbz\\t%0, %l1\";
1314   else
1315     return \"cmp\\t%0, #0\;beq\\t%l1\";
1316   "
1317   [(set (attr "length")
1318         (if_then_else
1319             (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1320                  (le (minus (match_dup 1) (pc)) (const_int 128))
1321                  (not (match_test "which_alternative")))
1322             (const_int 2)
1323             (const_int 8)))
1324    (set_attr "type" "branch,multiple")]
1325 )
1326
1327 (define_insn "*thumb2_cbnz"
1328   [(set (pc) (if_then_else
1329               (ne (match_operand:SI 0 "s_register_operand" "l,?r")
1330                   (const_int 0))
1331               (label_ref (match_operand 1 "" ""))
1332               (pc)))
1333    (clobber (reg:CC CC_REGNUM))]
1334   "TARGET_THUMB2"
1335   "*
1336   if (get_attr_length (insn) == 2)
1337     return \"cbnz\\t%0, %l1\";
1338   else
1339     return \"cmp\\t%0, #0\;bne\\t%l1\";
1340   "
1341   [(set (attr "length")
1342         (if_then_else
1343             (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1344                  (le (minus (match_dup 1) (pc)) (const_int 128))
1345                  (not (match_test "which_alternative")))
1346             (const_int 2)
1347             (const_int 8)))
1348    (set_attr "type" "branch,multiple")]
1349 )
1350
1351 (define_insn "*thumb2_one_cmplsi2_short"
1352   [(set (match_operand:SI 0 "low_register_operand" "=l")
1353         (not:SI (match_operand:SI 1 "low_register_operand" "l")))
1354    (clobber (reg:CC CC_REGNUM))]
1355   "TARGET_THUMB2 && reload_completed"
1356   "mvn%!\t%0, %1"
1357   [(set_attr "predicable" "yes")
1358    (set_attr "length" "2")
1359    (set_attr "type" "mvn_reg")]
1360 )
1361
1362 (define_insn "*thumb2_negsi2_short"
1363   [(set (match_operand:SI 0 "low_register_operand" "=l")
1364         (neg:SI (match_operand:SI 1 "low_register_operand" "l")))
1365    (clobber (reg:CC CC_REGNUM))]
1366   "TARGET_THUMB2 && reload_completed"
1367   "neg%!\t%0, %1"
1368   [(set_attr "predicable" "yes")
1369    (set_attr "length" "2")
1370    (set_attr "type" "alu_sreg")]
1371 )
1372
1373 ; Constants for op 2 will never be given to these patterns.
1374 (define_insn_and_split "*iordi_notdi_di"
1375   [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1376         (ior:DI (not:DI (match_operand:DI 1 "s_register_operand" "0,r"))
1377                 (match_operand:DI 2 "s_register_operand" "r,0")))]
1378   "TARGET_THUMB2"
1379   "#"
1380   "TARGET_THUMB2 && reload_completed"
1381   [(set (match_dup 0) (ior:SI (not:SI (match_dup 1)) (match_dup 2)))
1382    (set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))]
1383   "
1384   {
1385     operands[3] = gen_highpart (SImode, operands[0]);
1386     operands[0] = gen_lowpart (SImode, operands[0]);
1387     operands[4] = gen_highpart (SImode, operands[1]);
1388     operands[1] = gen_lowpart (SImode, operands[1]);
1389     operands[5] = gen_highpart (SImode, operands[2]);
1390     operands[2] = gen_lowpart (SImode, operands[2]);
1391   }"
1392   [(set_attr "length" "8")
1393    (set_attr "predicable" "yes")
1394    (set_attr "predicable_short_it" "no")
1395    (set_attr "type" "multiple")]
1396 )
1397
1398 (define_insn_and_split "*iordi_notzesidi_di"
1399   [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1400         (ior:DI (not:DI (zero_extend:DI
1401                          (match_operand:SI 2 "s_register_operand" "r,r")))
1402                 (match_operand:DI 1 "s_register_operand" "0,?r")))]
1403   "TARGET_THUMB2"
1404   "#"
1405   ; (not (zero_extend...)) means operand0 will always be 0xffffffff
1406   "TARGET_THUMB2 && reload_completed"
1407   [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
1408    (set (match_dup 3) (const_int -1))]
1409   "
1410   {
1411     operands[3] = gen_highpart (SImode, operands[0]);
1412     operands[0] = gen_lowpart (SImode, operands[0]);
1413     operands[1] = gen_lowpart (SImode, operands[1]);
1414   }"
1415   [(set_attr "length" "4,8")
1416    (set_attr "predicable" "yes")
1417    (set_attr "predicable_short_it" "no")
1418    (set_attr "type" "multiple")]
1419 )
1420
1421 (define_insn_and_split "*iordi_notdi_zesidi"
1422   [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1423         (ior:DI (not:DI (match_operand:DI 2 "s_register_operand" "0,?r"))
1424                 (zero_extend:DI
1425                  (match_operand:SI 1 "s_register_operand" "r,r"))))]
1426   "TARGET_THUMB2"
1427   "#"
1428   "TARGET_THUMB2 && reload_completed"
1429   [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
1430    (set (match_dup 3) (not:SI (match_dup 4)))]
1431   "
1432   {
1433     operands[3] = gen_highpart (SImode, operands[0]);
1434     operands[0] = gen_lowpart (SImode, operands[0]);
1435     operands[1] = gen_lowpart (SImode, operands[1]);
1436     operands[4] = gen_highpart (SImode, operands[2]);
1437     operands[2] = gen_lowpart (SImode, operands[2]);
1438   }"
1439   [(set_attr "length" "8")
1440    (set_attr "predicable" "yes")
1441    (set_attr "predicable_short_it" "no")
1442    (set_attr "type" "multiple")]
1443 )
1444
1445 (define_insn_and_split "*iordi_notsesidi_di"
1446   [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1447         (ior:DI (not:DI (sign_extend:DI
1448                          (match_operand:SI 2 "s_register_operand" "r,r")))
1449                 (match_operand:DI 1 "s_register_operand" "0,r")))]
1450   "TARGET_THUMB2"
1451   "#"
1452   "TARGET_THUMB2 && reload_completed"
1453   [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
1454    (set (match_dup 3) (ior:SI (not:SI
1455                                 (ashiftrt:SI (match_dup 2) (const_int 31)))
1456                                (match_dup 4)))]
1457   "
1458   {
1459     operands[3] = gen_highpart (SImode, operands[0]);
1460     operands[0] = gen_lowpart (SImode, operands[0]);
1461     operands[4] = gen_highpart (SImode, operands[1]);
1462     operands[1] = gen_lowpart (SImode, operands[1]);
1463   }"
1464   [(set_attr "length" "8")
1465    (set_attr "predicable" "yes")
1466    (set_attr "predicable_short_it" "no")
1467    (set_attr "type" "multiple")]
1468 )
1469
1470 (define_insn "*orsi_notsi_si"
1471   [(set (match_operand:SI 0 "s_register_operand" "=r")
1472         (ior:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
1473                 (match_operand:SI 1 "s_register_operand" "r")))]
1474   "TARGET_THUMB2"
1475   "orn%?\\t%0, %1, %2"
1476   [(set_attr "predicable" "yes")
1477    (set_attr "predicable_short_it" "no")
1478    (set_attr "type" "logic_reg")]
1479 )
1480
1481 (define_insn "*orsi_not_shiftsi_si"
1482   [(set (match_operand:SI 0 "s_register_operand" "=r")
1483         (ior:SI (not:SI (match_operator:SI 4 "shift_operator"
1484                          [(match_operand:SI 2 "s_register_operand" "r")
1485                           (match_operand:SI 3 "const_int_operand" "M")]))
1486                 (match_operand:SI 1 "s_register_operand" "r")))]
1487   "TARGET_THUMB2"
1488   "orn%?\\t%0, %1, %2%S4"
1489   [(set_attr "predicable" "yes")
1490    (set_attr "predicable_short_it" "no")
1491    (set_attr "shift" "2")
1492    (set_attr "type" "alu_shift_imm")]
1493 )
1494
1495 (define_peephole2
1496   [(set (match_operand:CC_NOOV 0 "cc_register" "")
1497         (compare:CC_NOOV (zero_extract:SI
1498                           (match_operand:SI 1 "low_register_operand" "")
1499                           (const_int 1)
1500                           (match_operand:SI 2 "const_int_operand" ""))
1501                          (const_int 0)))
1502    (match_scratch:SI 3 "l")
1503    (set (pc)
1504         (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
1505                        [(match_dup 0) (const_int 0)])
1506                       (match_operand 5 "" "")
1507                       (match_operand 6 "" "")))]
1508   "TARGET_THUMB2
1509    && (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32)"
1510   [(parallel [(set (match_dup 0)
1511                    (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
1512                                     (const_int 0)))
1513               (clobber (match_dup 3))])
1514    (set (pc)
1515         (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1516                       (match_dup 5) (match_dup 6)))]
1517   "
1518   operands[2] = GEN_INT (31 - INTVAL (operands[2]));
1519   operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? LT : GE,
1520                                 VOIDmode, operands[0], const0_rtx);
1521   ")
1522
1523 (define_peephole2
1524   [(set (match_operand:CC_NOOV 0 "cc_register" "")
1525         (compare:CC_NOOV (zero_extract:SI
1526                           (match_operand:SI 1 "low_register_operand" "")
1527                           (match_operand:SI 2 "const_int_operand" "")
1528                           (const_int 0))
1529                          (const_int 0)))
1530    (match_scratch:SI 3 "l")
1531    (set (pc)
1532         (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
1533                        [(match_dup 0) (const_int 0)])
1534                       (match_operand 5 "" "")
1535                       (match_operand 6 "" "")))]
1536   "TARGET_THUMB2
1537    && (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 32)"
1538   [(parallel [(set (match_dup 0)
1539                    (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
1540                                     (const_int 0)))
1541               (clobber (match_dup 3))])
1542    (set (pc)
1543         (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1544                       (match_dup 5) (match_dup 6)))]
1545   "
1546   operands[2] = GEN_INT (32 - INTVAL (operands[2]));
1547   ")
1548
1549 ;; Define the subtract-one-and-jump insns so loop.c
1550 ;; knows what to generate.
1551 (define_expand "doloop_end"
1552   [(use (match_operand 0 "" ""))      ; loop pseudo
1553    (use (match_operand 1 "" ""))]     ; label
1554   "TARGET_32BIT"
1555   "
1556  {
1557    /* Currently SMS relies on the do-loop pattern to recognize loops
1558       where (1) the control part consists of all insns defining and/or
1559       using a certain 'count' register and (2) the loop count can be
1560       adjusted by modifying this register prior to the loop.
1561       ??? The possible introduction of a new block to initialize the
1562       new IV can potentially affect branch optimizations.  */
1563    if (optimize > 0 && flag_modulo_sched)
1564    {
1565      rtx s0;
1566      rtx bcomp;
1567      rtx loc_ref;
1568      rtx cc_reg;
1569      rtx insn;
1570      rtx cmp;
1571
1572      if (GET_MODE (operands[0]) != SImode)
1573        FAIL;
1574
1575      s0 = operands [0];
1576      if (TARGET_THUMB2)
1577        insn = emit_insn (gen_thumb2_addsi3_compare0 (s0, s0, GEN_INT (-1)));
1578      else
1579        insn = emit_insn (gen_addsi3_compare0 (s0, s0, GEN_INT (-1)));
1580
1581      cmp = XVECEXP (PATTERN (insn), 0, 0);
1582      cc_reg = SET_DEST (cmp);
1583      bcomp = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx);
1584      loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [1]);
1585      emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
1586                                   gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
1587                                                         loc_ref, pc_rtx)));
1588      DONE;
1589    }else
1590       FAIL;
1591  }")
1592