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[gcc.git] / gcc / config / arm / thumb2.md
1 ;; ARM Thumb-2 Machine Description
2 ;; Copyright (C) 2007, 2008, 2010 Free Software Foundation, Inc.
3 ;; Written by CodeSourcery, LLC.
4 ;;
5 ;; This file is part of GCC.
6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
10 ;; any later version.
11 ;;
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
16 ;;
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>. */
20
21 ;; Note: Thumb-2 is the variant of the Thumb architecture that adds
22 ;; 32-bit encodings of [almost all of] the Arm instruction set.
23 ;; Some old documents refer to the relatively minor interworking
24 ;; changes made in armv5t as "thumb2". These are considered part
25 ;; the 16-bit Thumb-1 instruction set.
26
27 (define_insn "*thumb2_incscc"
28 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
29 (plus:SI (match_operator:SI 2 "arm_comparison_operator"
30 [(match_operand:CC 3 "cc_register" "") (const_int 0)])
31 (match_operand:SI 1 "s_register_operand" "0,?r")))]
32 "TARGET_THUMB2"
33 "@
34 it\\t%d2\;add%d2\\t%0, %1, #1
35 ite\\t%D2\;mov%D2\\t%0, %1\;add%d2\\t%0, %1, #1"
36 [(set_attr "conds" "use")
37 (set_attr "length" "6,10")]
38 )
39
40 (define_insn "*thumb2_decscc"
41 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
42 (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r")
43 (match_operator:SI 2 "arm_comparison_operator"
44 [(match_operand 3 "cc_register" "") (const_int 0)])))]
45 "TARGET_THUMB2"
46 "@
47 it\\t%d2\;sub%d2\\t%0, %1, #1
48 ite\\t%D2\;mov%D2\\t%0, %1\;sub%d2\\t%0, %1, #1"
49 [(set_attr "conds" "use")
50 (set_attr "length" "6,10")]
51 )
52
53 ;; Thumb-2 only allows shift by constant on data processing instructions
54 (define_insn "*thumb_andsi_not_shiftsi_si"
55 [(set (match_operand:SI 0 "s_register_operand" "=r")
56 (and:SI (not:SI (match_operator:SI 4 "shift_operator"
57 [(match_operand:SI 2 "s_register_operand" "r")
58 (match_operand:SI 3 "const_int_operand" "M")]))
59 (match_operand:SI 1 "s_register_operand" "r")))]
60 "TARGET_THUMB2"
61 "bic%?\\t%0, %1, %2%S4"
62 [(set_attr "predicable" "yes")
63 (set_attr "shift" "2")
64 (set_attr "type" "alu_shift")]
65 )
66
67 (define_insn "*thumb2_smaxsi3"
68 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
69 (smax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
70 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
71 (clobber (reg:CC CC_REGNUM))]
72 "TARGET_THUMB2"
73 "@
74 cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2
75 cmp\\t%1, %2\;it\\tge\;movge\\t%0, %1
76 cmp\\t%1, %2\;ite\\tge\;movge\\t%0, %1\;movlt\\t%0, %2"
77 [(set_attr "conds" "clob")
78 (set_attr "length" "10,10,14")]
79 )
80
81 (define_insn "*thumb2_sminsi3"
82 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
83 (smin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
84 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
85 (clobber (reg:CC CC_REGNUM))]
86 "TARGET_THUMB2"
87 "@
88 cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2
89 cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %1
90 cmp\\t%1, %2\;ite\\tlt\;movlt\\t%0, %1\;movge\\t%0, %2"
91 [(set_attr "conds" "clob")
92 (set_attr "length" "10,10,14")]
93 )
94
95 (define_insn "*thumb32_umaxsi3"
96 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
97 (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
98 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
99 (clobber (reg:CC CC_REGNUM))]
100 "TARGET_THUMB2"
101 "@
102 cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2
103 cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %1
104 cmp\\t%1, %2\;ite\\tcs\;movcs\\t%0, %1\;movcc\\t%0, %2"
105 [(set_attr "conds" "clob")
106 (set_attr "length" "10,10,14")]
107 )
108
109 (define_insn "*thumb2_uminsi3"
110 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
111 (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
112 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
113 (clobber (reg:CC CC_REGNUM))]
114 "TARGET_THUMB2"
115 "@
116 cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2
117 cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %1
118 cmp\\t%1, %2\;ite\\tcc\;movcc\\t%0, %1\;movcs\\t%0, %2"
119 [(set_attr "conds" "clob")
120 (set_attr "length" "10,10,14")]
121 )
122
123 ;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
124 (define_insn "*thumb2_negdi2"
125 [(set (match_operand:DI 0 "s_register_operand" "=&r,r")
126 (neg:DI (match_operand:DI 1 "s_register_operand" "?r,0")))
127 (clobber (reg:CC CC_REGNUM))]
128 "TARGET_THUMB2"
129 "negs\\t%Q0, %Q1\;sbc\\t%R0, %R1, %R1, lsl #1"
130 [(set_attr "conds" "clob")
131 (set_attr "length" "8")]
132 )
133
134 (define_insn "*thumb2_abssi2"
135 [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
136 (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
137 (clobber (reg:CC CC_REGNUM))]
138 "TARGET_THUMB2"
139 "@
140 cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
141 eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31"
142 [(set_attr "conds" "clob,*")
143 (set_attr "shift" "1")
144 ;; predicable can't be set based on the variant, so left as no
145 (set_attr "length" "10,8")]
146 )
147
148 (define_insn "*thumb2_neg_abssi2"
149 [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
150 (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
151 (clobber (reg:CC CC_REGNUM))]
152 "TARGET_THUMB2"
153 "@
154 cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
155 eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31"
156 [(set_attr "conds" "clob,*")
157 (set_attr "shift" "1")
158 ;; predicable can't be set based on the variant, so left as no
159 (set_attr "length" "10,8")]
160 )
161
162 ;; We have two alternatives here for memory loads (and similarly for stores)
163 ;; to reflect the fact that the permissible constant pool ranges differ
164 ;; between ldr instructions taking low regs and ldr instructions taking high
165 ;; regs. The high register alternatives are not taken into account when
166 ;; choosing register preferences in order to reflect their expense.
167 (define_insn "*thumb2_movsi_insn"
168 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l ,*hk,m,*m")
169 (match_operand:SI 1 "general_operand" "rk ,I,K,j,mi,*mi,l,*hk"))]
170 "TARGET_THUMB2 && ! TARGET_IWMMXT
171 && !(TARGET_HARD_FLOAT && TARGET_VFP)
172 && ( register_operand (operands[0], SImode)
173 || register_operand (operands[1], SImode))"
174 "@
175 mov%?\\t%0, %1
176 mov%?\\t%0, %1
177 mvn%?\\t%0, #%B1
178 movw%?\\t%0, %1
179 ldr%?\\t%0, %1
180 ldr%?\\t%0, %1
181 str%?\\t%1, %0
182 str%?\\t%1, %0"
183 [(set_attr "type" "*,*,*,*,load1,load1,store1,store1")
184 (set_attr "predicable" "yes")
185 (set_attr "pool_range" "*,*,*,*,1020,4096,*,*")
186 (set_attr "neg_pool_range" "*,*,*,*,0,0,*,*")]
187 )
188
189 (define_insn "tls_load_dot_plus_four"
190 [(set (match_operand:SI 0 "register_operand" "=l,l,r,r")
191 (mem:SI (unspec:SI [(match_operand:SI 2 "register_operand" "0,1,0,1")
192 (const_int 4)
193 (match_operand 3 "" "")]
194 UNSPEC_PIC_BASE)))
195 (clobber (match_scratch:SI 1 "=X,l,X,r"))]
196 "TARGET_THUMB2"
197 "*
198 (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
199 INTVAL (operands[3]));
200 return \"add\\t%2, %|pc\;ldr%?\\t%0, [%2]\";
201 "
202 [(set_attr "length" "4,4,6,6")]
203 )
204
205 ;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
206 ;; of the messiness associated with the ARM patterns.
207 (define_insn "*thumb2_movhi_insn"
208 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
209 (match_operand:HI 1 "general_operand" "rI,n,r,m"))]
210 "TARGET_THUMB2
211 && (register_operand (operands[0], HImode)
212 || register_operand (operands[1], HImode))"
213 "@
214 mov%?\\t%0, %1\\t%@ movhi
215 movw%?\\t%0, %L1\\t%@ movhi
216 str%(h%)\\t%1, %0\\t%@ movhi
217 ldr%(h%)\\t%0, %1\\t%@ movhi"
218 [(set_attr "type" "*,*,store1,load1")
219 (set_attr "predicable" "yes")
220 (set_attr "pool_range" "*,*,*,4096")
221 (set_attr "neg_pool_range" "*,*,*,250")]
222 )
223
224 (define_insn "*thumb2_cmpsi_neg_shiftsi"
225 [(set (reg:CC CC_REGNUM)
226 (compare:CC (match_operand:SI 0 "s_register_operand" "r")
227 (neg:SI (match_operator:SI 3 "shift_operator"
228 [(match_operand:SI 1 "s_register_operand" "r")
229 (match_operand:SI 2 "const_int_operand" "M")]))))]
230 "TARGET_THUMB2"
231 "cmn%?\\t%0, %1%S3"
232 [(set_attr "conds" "set")
233 (set_attr "shift" "1")
234 (set_attr "type" "alu_shift")]
235 )
236
237 (define_insn "*thumb2_mov_scc"
238 [(set (match_operand:SI 0 "s_register_operand" "=r")
239 (match_operator:SI 1 "arm_comparison_operator"
240 [(match_operand 2 "cc_register" "") (const_int 0)]))]
241 "TARGET_THUMB2"
242 "ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
243 [(set_attr "conds" "use")
244 (set_attr "length" "10")]
245 )
246
247 (define_insn "*thumb2_mov_negscc"
248 [(set (match_operand:SI 0 "s_register_operand" "=r")
249 (neg:SI (match_operator:SI 1 "arm_comparison_operator"
250 [(match_operand 2 "cc_register" "") (const_int 0)])))]
251 "TARGET_THUMB2"
252 "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
253 [(set_attr "conds" "use")
254 (set_attr "length" "10")]
255 )
256
257 (define_insn "*thumb2_mov_notscc"
258 [(set (match_operand:SI 0 "s_register_operand" "=r")
259 (not:SI (match_operator:SI 1 "arm_comparison_operator"
260 [(match_operand 2 "cc_register" "") (const_int 0)])))]
261 "TARGET_THUMB2"
262 "ite\\t%D1\;mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1"
263 [(set_attr "conds" "use")
264 (set_attr "length" "10")]
265 )
266
267 (define_insn "*thumb2_movsicc_insn"
268 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r")
269 (if_then_else:SI
270 (match_operator 3 "arm_comparison_operator"
271 [(match_operand 4 "cc_register" "") (const_int 0)])
272 (match_operand:SI 1 "arm_not_operand" "0,0,rI,K,rI,rI,K,K")
273 (match_operand:SI 2 "arm_not_operand" "rI,K,0,0,rI,K,rI,K")))]
274 "TARGET_THUMB2"
275 "@
276 it\\t%D3\;mov%D3\\t%0, %2
277 it\\t%D3\;mvn%D3\\t%0, #%B2
278 it\\t%d3\;mov%d3\\t%0, %1
279 it\\t%d3\;mvn%d3\\t%0, #%B1
280 ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
281 ite\\t%d3\;mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2
282 ite\\t%d3\;mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2
283 ite\\t%d3\;mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2"
284 [(set_attr "length" "6,6,6,6,10,10,10,10")
285 (set_attr "conds" "use")]
286 )
287
288 (define_insn "*thumb2_movsfcc_soft_insn"
289 [(set (match_operand:SF 0 "s_register_operand" "=r,r")
290 (if_then_else:SF (match_operator 3 "arm_comparison_operator"
291 [(match_operand 4 "cc_register" "") (const_int 0)])
292 (match_operand:SF 1 "s_register_operand" "0,r")
293 (match_operand:SF 2 "s_register_operand" "r,0")))]
294 "TARGET_THUMB2 && TARGET_SOFT_FLOAT"
295 "@
296 it\\t%D3\;mov%D3\\t%0, %2
297 it\\t%d3\;mov%d3\\t%0, %1"
298 [(set_attr "length" "6,6")
299 (set_attr "conds" "use")]
300 )
301
302 (define_insn "*call_reg_thumb2"
303 [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
304 (match_operand 1 "" ""))
305 (use (match_operand 2 "" ""))
306 (clobber (reg:SI LR_REGNUM))]
307 "TARGET_THUMB2"
308 "blx%?\\t%0"
309 [(set_attr "type" "call")]
310 )
311
312 (define_insn "*call_value_reg_thumb2"
313 [(set (match_operand 0 "" "")
314 (call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
315 (match_operand 2 "" "")))
316 (use (match_operand 3 "" ""))
317 (clobber (reg:SI LR_REGNUM))]
318 "TARGET_THUMB2"
319 "blx\\t%1"
320 [(set_attr "type" "call")]
321 )
322
323 (define_insn "*thumb2_indirect_jump"
324 [(set (pc)
325 (match_operand:SI 0 "register_operand" "l*r"))]
326 "TARGET_THUMB2"
327 "bx\\t%0"
328 [(set_attr "conds" "clob")]
329 )
330 ;; Don't define thumb2_load_indirect_jump because we can't guarantee label
331 ;; addresses will have the thumb bit set correctly.
332
333
334 (define_insn "*thumb2_and_scc"
335 [(set (match_operand:SI 0 "s_register_operand" "=r")
336 (and:SI (match_operator:SI 1 "arm_comparison_operator"
337 [(match_operand 3 "cc_register" "") (const_int 0)])
338 (match_operand:SI 2 "s_register_operand" "r")))]
339 "TARGET_THUMB2"
340 "ite\\t%D1\;mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1"
341 [(set_attr "conds" "use")
342 (set_attr "length" "10")]
343 )
344
345 (define_insn "*thumb2_ior_scc"
346 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
347 (ior:SI (match_operator:SI 2 "arm_comparison_operator"
348 [(match_operand 3 "cc_register" "") (const_int 0)])
349 (match_operand:SI 1 "s_register_operand" "0,?r")))]
350 "TARGET_THUMB2"
351 "@
352 it\\t%d2\;orr%d2\\t%0, %1, #1
353 ite\\t%D2\;mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1"
354 [(set_attr "conds" "use")
355 (set_attr "length" "6,10")]
356 )
357
358 (define_insn "*thumb2_cond_move"
359 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
360 (if_then_else:SI (match_operator 3 "equality_operator"
361 [(match_operator 4 "arm_comparison_operator"
362 [(match_operand 5 "cc_register" "") (const_int 0)])
363 (const_int 0)])
364 (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
365 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))]
366 "TARGET_THUMB2"
367 "*
368 if (GET_CODE (operands[3]) == NE)
369 {
370 if (which_alternative != 1)
371 output_asm_insn (\"it\\t%D4\;mov%D4\\t%0, %2\", operands);
372 if (which_alternative != 0)
373 output_asm_insn (\"it\\t%d4\;mov%d4\\t%0, %1\", operands);
374 return \"\";
375 }
376 switch (which_alternative)
377 {
378 case 0:
379 output_asm_insn (\"it\\t%d4\", operands);
380 break;
381 case 1:
382 output_asm_insn (\"it\\t%D4\", operands);
383 break;
384 case 2:
385 output_asm_insn (\"ite\\t%D4\", operands);
386 break;
387 default:
388 abort();
389 }
390 if (which_alternative != 0)
391 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
392 if (which_alternative != 1)
393 output_asm_insn (\"mov%d4\\t%0, %2\", operands);
394 return \"\";
395 "
396 [(set_attr "conds" "use")
397 (set_attr "length" "6,6,10")]
398 )
399
400 (define_insn "*thumb2_cond_arith"
401 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
402 (match_operator:SI 5 "shiftable_operator"
403 [(match_operator:SI 4 "arm_comparison_operator"
404 [(match_operand:SI 2 "s_register_operand" "r,r")
405 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
406 (match_operand:SI 1 "s_register_operand" "0,?r")]))
407 (clobber (reg:CC CC_REGNUM))]
408 "TARGET_THUMB2"
409 "*
410 if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
411 return \"%i5\\t%0, %1, %2, lsr #31\";
412
413 output_asm_insn (\"cmp\\t%2, %3\", operands);
414 if (GET_CODE (operands[5]) == AND)
415 {
416 output_asm_insn (\"ite\\t%D4\", operands);
417 output_asm_insn (\"mov%D4\\t%0, #0\", operands);
418 }
419 else if (GET_CODE (operands[5]) == MINUS)
420 {
421 output_asm_insn (\"ite\\t%D4\", operands);
422 output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands);
423 }
424 else if (which_alternative != 0)
425 {
426 output_asm_insn (\"ite\\t%D4\", operands);
427 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
428 }
429 else
430 output_asm_insn (\"it\\t%d4\", operands);
431 return \"%i5%d4\\t%0, %1, #1\";
432 "
433 [(set_attr "conds" "clob")
434 (set_attr "length" "14")]
435 )
436
437 (define_insn "*thumb2_cond_sub"
438 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
439 (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r")
440 (match_operator:SI 4 "arm_comparison_operator"
441 [(match_operand:SI 2 "s_register_operand" "r,r")
442 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
443 (clobber (reg:CC CC_REGNUM))]
444 "TARGET_THUMB2"
445 "*
446 output_asm_insn (\"cmp\\t%2, %3\", operands);
447 if (which_alternative != 0)
448 {
449 output_asm_insn (\"ite\\t%D4\", operands);
450 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
451 }
452 else
453 output_asm_insn (\"it\\t%d4\", operands);
454 return \"sub%d4\\t%0, %1, #1\";
455 "
456 [(set_attr "conds" "clob")
457 (set_attr "length" "10,14")]
458 )
459
460 (define_insn "*thumb2_negscc"
461 [(set (match_operand:SI 0 "s_register_operand" "=r")
462 (neg:SI (match_operator 3 "arm_comparison_operator"
463 [(match_operand:SI 1 "s_register_operand" "r")
464 (match_operand:SI 2 "arm_rhs_operand" "rI")])))
465 (clobber (reg:CC CC_REGNUM))]
466 "TARGET_THUMB2"
467 "*
468 if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx)
469 return \"asr\\t%0, %1, #31\";
470
471 if (GET_CODE (operands[3]) == NE)
472 return \"subs\\t%0, %1, %2\;it\\tne\;mvnne\\t%0, #0\";
473
474 output_asm_insn (\"cmp\\t%1, %2\", operands);
475 output_asm_insn (\"ite\\t%D3\", operands);
476 output_asm_insn (\"mov%D3\\t%0, #0\", operands);
477 return \"mvn%d3\\t%0, #0\";
478 "
479 [(set_attr "conds" "clob")
480 (set_attr "length" "14")]
481 )
482
483 (define_insn "*thumb2_movcond"
484 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
485 (if_then_else:SI
486 (match_operator 5 "arm_comparison_operator"
487 [(match_operand:SI 3 "s_register_operand" "r,r,r")
488 (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
489 (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
490 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
491 (clobber (reg:CC CC_REGNUM))]
492 "TARGET_THUMB2"
493 "*
494 if (GET_CODE (operands[5]) == LT
495 && (operands[4] == const0_rtx))
496 {
497 if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
498 {
499 if (operands[2] == const0_rtx)
500 return \"and\\t%0, %1, %3, asr #31\";
501 return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\";
502 }
503 else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
504 {
505 if (operands[1] == const0_rtx)
506 return \"bic\\t%0, %2, %3, asr #31\";
507 return \"bics\\t%0, %2, %3, asr #32\;it\\tcs\;movcs\\t%0, %1\";
508 }
509 /* The only case that falls through to here is when both ops 1 & 2
510 are constants. */
511 }
512
513 if (GET_CODE (operands[5]) == GE
514 && (operands[4] == const0_rtx))
515 {
516 if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
517 {
518 if (operands[2] == const0_rtx)
519 return \"bic\\t%0, %1, %3, asr #31\";
520 return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\";
521 }
522 else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
523 {
524 if (operands[1] == const0_rtx)
525 return \"and\\t%0, %2, %3, asr #31\";
526 return \"ands\\t%0, %2, %3, asr #32\;it\tcc\;movcc\\t%0, %1\";
527 }
528 /* The only case that falls through to here is when both ops 1 & 2
529 are constants. */
530 }
531 if (GET_CODE (operands[4]) == CONST_INT
532 && !const_ok_for_arm (INTVAL (operands[4])))
533 output_asm_insn (\"cmn\\t%3, #%n4\", operands);
534 else
535 output_asm_insn (\"cmp\\t%3, %4\", operands);
536 switch (which_alternative)
537 {
538 case 0:
539 output_asm_insn (\"it\\t%D5\", operands);
540 break;
541 case 1:
542 output_asm_insn (\"it\\t%d5\", operands);
543 break;
544 case 2:
545 output_asm_insn (\"ite\\t%d5\", operands);
546 break;
547 default:
548 abort();
549 }
550 if (which_alternative != 0)
551 output_asm_insn (\"mov%d5\\t%0, %1\", operands);
552 if (which_alternative != 1)
553 output_asm_insn (\"mov%D5\\t%0, %2\", operands);
554 return \"\";
555 "
556 [(set_attr "conds" "clob")
557 (set_attr "length" "10,10,14")]
558 )
559
560 ;; Zero and sign extension instructions.
561
562 ;; All supported Thumb2 implementations are armv6, so only that case is
563 ;; provided.
564 (define_insn "*thumb2_extendqisi_v6"
565 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
566 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
567 "TARGET_THUMB2 && arm_arch6"
568 "@
569 sxtb%?\\t%0, %1
570 ldr%(sb%)\\t%0, %1"
571 [(set_attr "type" "alu_shift,load_byte")
572 (set_attr "predicable" "yes")
573 (set_attr "pool_range" "*,4096")
574 (set_attr "neg_pool_range" "*,250")]
575 )
576
577 (define_insn "*thumb2_zero_extendhisi2_v6"
578 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
579 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
580 "TARGET_THUMB2 && arm_arch6"
581 "@
582 uxth%?\\t%0, %1
583 ldr%(h%)\\t%0, %1"
584 [(set_attr "type" "alu_shift,load_byte")
585 (set_attr "predicable" "yes")
586 (set_attr "pool_range" "*,4096")
587 (set_attr "neg_pool_range" "*,250")]
588 )
589
590 (define_insn "thumb2_zero_extendqisi2_v6"
591 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
592 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
593 "TARGET_THUMB2 && arm_arch6"
594 "@
595 uxtb%(%)\\t%0, %1
596 ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
597 [(set_attr "type" "alu_shift,load_byte")
598 (set_attr "predicable" "yes")
599 (set_attr "pool_range" "*,4096")
600 (set_attr "neg_pool_range" "*,250")]
601 )
602
603 (define_insn "thumb2_casesi_internal"
604 [(parallel [(set (pc)
605 (if_then_else
606 (leu (match_operand:SI 0 "s_register_operand" "r")
607 (match_operand:SI 1 "arm_rhs_operand" "rI"))
608 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
609 (label_ref (match_operand 2 "" ""))))
610 (label_ref (match_operand 3 "" ""))))
611 (clobber (reg:CC CC_REGNUM))
612 (clobber (match_scratch:SI 4 "=&r"))
613 (use (label_ref (match_dup 2)))])]
614 "TARGET_THUMB2 && !flag_pic"
615 "* return thumb2_output_casesi(operands);"
616 [(set_attr "conds" "clob")
617 (set_attr "length" "16")]
618 )
619
620 (define_insn "thumb2_casesi_internal_pic"
621 [(parallel [(set (pc)
622 (if_then_else
623 (leu (match_operand:SI 0 "s_register_operand" "r")
624 (match_operand:SI 1 "arm_rhs_operand" "rI"))
625 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
626 (label_ref (match_operand 2 "" ""))))
627 (label_ref (match_operand 3 "" ""))))
628 (clobber (reg:CC CC_REGNUM))
629 (clobber (match_scratch:SI 4 "=&r"))
630 (clobber (match_scratch:SI 5 "=r"))
631 (use (label_ref (match_dup 2)))])]
632 "TARGET_THUMB2 && flag_pic"
633 "* return thumb2_output_casesi(operands);"
634 [(set_attr "conds" "clob")
635 (set_attr "length" "20")]
636 )
637
638 ;; Note: this is not predicable, to avoid issues with linker-generated
639 ;; interworking stubs.
640 (define_insn "*thumb2_return"
641 [(return)]
642 "TARGET_THUMB2 && USE_RETURN_INSN (FALSE)"
643 "*
644 {
645 return output_return_instruction (const_true_rtx, TRUE, FALSE);
646 }"
647 [(set_attr "type" "load1")
648 (set_attr "length" "12")]
649 )
650
651 (define_insn_and_split "thumb2_eh_return"
652 [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
653 VUNSPEC_EH_RETURN)
654 (clobber (match_scratch:SI 1 "=&r"))]
655 "TARGET_THUMB2"
656 "#"
657 "&& reload_completed"
658 [(const_int 0)]
659 "
660 {
661 thumb_set_return_address (operands[0], operands[1]);
662 DONE;
663 }"
664 )
665
666 (define_insn "*thumb2_alusi3_short"
667 [(set (match_operand:SI 0 "s_register_operand" "=l")
668 (match_operator:SI 3 "thumb_16bit_operator"
669 [(match_operand:SI 1 "s_register_operand" "0")
670 (match_operand:SI 2 "s_register_operand" "l")]))
671 (clobber (reg:CC CC_REGNUM))]
672 "TARGET_THUMB2 && reload_completed
673 && GET_CODE(operands[3]) != PLUS
674 && GET_CODE(operands[3]) != MINUS"
675 "%I3%!\\t%0, %1, %2"
676 [(set_attr "predicable" "yes")
677 (set_attr "length" "2")]
678 )
679
680 ;; Similarly for 16-bit shift instructions
681 ;; There is no 16-bit rotate by immediate instruction.
682 (define_peephole2
683 [(set (match_operand:SI 0 "low_register_operand" "")
684 (match_operator:SI 3 "shift_operator"
685 [(match_operand:SI 1 "low_register_operand" "")
686 (match_operand:SI 2 "low_reg_or_int_operand" "")]))]
687 "TARGET_THUMB2
688 && peep2_regno_dead_p(0, CC_REGNUM)
689 && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
690 || REG_P(operands[2]))"
691 [(parallel
692 [(set (match_dup 0)
693 (match_op_dup 3
694 [(match_dup 1)
695 (match_dup 2)]))
696 (clobber (reg:CC CC_REGNUM))])]
697 ""
698 )
699
700 (define_insn "*thumb2_shiftsi3_short"
701 [(set (match_operand:SI 0 "low_register_operand" "=l")
702 (match_operator:SI 3 "shift_operator"
703 [(match_operand:SI 1 "low_register_operand" "l")
704 (match_operand:SI 2 "low_reg_or_int_operand" "lM")]))
705 (clobber (reg:CC CC_REGNUM))]
706 "TARGET_THUMB2 && reload_completed
707 && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
708 || REG_P(operands[2]))"
709 "* return arm_output_shift(operands, 2);"
710 [(set_attr "predicable" "yes")
711 (set_attr "shift" "1")
712 (set_attr "length" "2")
713 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
714 (const_string "alu_shift")
715 (const_string "alu_shift_reg")))]
716 )
717
718 ;; 16-bit load immediate
719 (define_peephole2
720 [(set (match_operand:QHSI 0 "low_register_operand" "")
721 (match_operand:QHSI 1 "const_int_operand" ""))]
722 "TARGET_THUMB2
723 && peep2_regno_dead_p(0, CC_REGNUM)
724 && (unsigned HOST_WIDE_INT) INTVAL(operands[1]) < 256"
725 [(parallel
726 [(set (match_dup 0)
727 (match_dup 1))
728 (clobber (reg:CC CC_REGNUM))])]
729 ""
730 )
731
732 (define_insn "*thumb2_mov<mode>_shortim"
733 [(set (match_operand:QHSI 0 "low_register_operand" "=l")
734 (match_operand:QHSI 1 "const_int_operand" "I"))
735 (clobber (reg:CC CC_REGNUM))]
736 "TARGET_THUMB2 && reload_completed"
737 "mov%!\t%0, %1"
738 [(set_attr "predicable" "yes")
739 (set_attr "length" "2")]
740 )
741
742 ;; 16-bit add/sub immediate
743 (define_peephole2
744 [(set (match_operand:SI 0 "low_register_operand" "")
745 (plus:SI (match_operand:SI 1 "low_register_operand" "")
746 (match_operand:SI 2 "const_int_operand" "")))]
747 "TARGET_THUMB2
748 && peep2_regno_dead_p(0, CC_REGNUM)
749 && ((rtx_equal_p(operands[0], operands[1])
750 && INTVAL(operands[2]) > -256 && INTVAL(operands[2]) < 256)
751 || (INTVAL(operands[2]) > -8 && INTVAL(operands[2]) < 8))"
752 [(parallel
753 [(set (match_dup 0)
754 (plus:SI (match_dup 1)
755 (match_dup 2)))
756 (clobber (reg:CC CC_REGNUM))])]
757 ""
758 )
759
760 (define_insn "*thumb2_addsi_short"
761 [(set (match_operand:SI 0 "low_register_operand" "=l,l")
762 (plus:SI (match_operand:SI 1 "low_register_operand" "l,0")
763 (match_operand:SI 2 "low_reg_or_int_operand" "lPt,Ps")))
764 (clobber (reg:CC CC_REGNUM))]
765 "TARGET_THUMB2 && reload_completed"
766 "*
767 HOST_WIDE_INT val;
768
769 if (GET_CODE (operands[2]) == CONST_INT)
770 val = INTVAL(operands[2]);
771 else
772 val = 0;
773
774 /* We prefer eg. subs rn, rn, #1 over adds rn, rn, #0xffffffff. */
775 if (val < 0 && const_ok_for_arm(ARM_SIGN_EXTEND (-val)))
776 return \"sub%!\\t%0, %1, #%n2\";
777 else
778 return \"add%!\\t%0, %1, %2\";
779 "
780 [(set_attr "predicable" "yes")
781 (set_attr "length" "2")]
782 )
783
784 (define_insn "*thumb2_subsi_short"
785 [(set (match_operand:SI 0 "low_register_operand" "=l")
786 (minus:SI (match_operand:SI 1 "low_register_operand" "l")
787 (match_operand:SI 2 "low_register_operand" "l")))
788 (clobber (reg:CC CC_REGNUM))]
789 "TARGET_THUMB2 && reload_completed"
790 "sub%!\\t%0, %1, %2"
791 [(set_attr "predicable" "yes")
792 (set_attr "length" "2")]
793 )
794
795 (define_peephole2
796 [(set (match_operand:CC 0 "cc_register" "")
797 (compare:CC (match_operand:SI 1 "low_register_operand" "")
798 (match_operand:SI 2 "const_int_operand" "")))]
799 "TARGET_THUMB2
800 && peep2_reg_dead_p (1, operands[1])
801 && satisfies_constraint_Pw (operands[2])"
802 [(parallel
803 [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
804 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 3)))])]
805 "operands[3] = GEN_INT (- INTVAL (operands[2]));"
806 )
807
808 (define_peephole2
809 [(match_scratch:SI 3 "l")
810 (set (match_operand:CC 0 "cc_register" "")
811 (compare:CC (match_operand:SI 1 "low_register_operand" "")
812 (match_operand:SI 2 "const_int_operand" "")))]
813 "TARGET_THUMB2
814 && satisfies_constraint_Px (operands[2])"
815 [(parallel
816 [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
817 (set (match_dup 3) (plus:SI (match_dup 1) (match_dup 4)))])]
818 "operands[4] = GEN_INT (- INTVAL (operands[2]));"
819 )
820
821 (define_insn "thumb2_addsi3_compare0"
822 [(set (reg:CC_NOOV CC_REGNUM)
823 (compare:CC_NOOV
824 (plus:SI (match_operand:SI 1 "s_register_operand" "l, 0, r")
825 (match_operand:SI 2 "arm_add_operand" "lPt,Ps,rIL"))
826 (const_int 0)))
827 (set (match_operand:SI 0 "s_register_operand" "=l,l,r")
828 (plus:SI (match_dup 1) (match_dup 2)))]
829 "TARGET_THUMB2"
830 "*
831 HOST_WIDE_INT val;
832
833 if (GET_CODE (operands[2]) == CONST_INT)
834 val = INTVAL (operands[2]);
835 else
836 val = 0;
837
838 if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
839 return \"subs\\t%0, %1, #%n2\";
840 else
841 return \"adds\\t%0, %1, %2\";
842 "
843 [(set_attr "conds" "set")
844 (set_attr "length" "2,2,4")]
845 )
846
847 (define_insn "*thumb2_addsi3_compare0_scratch"
848 [(set (reg:CC_NOOV CC_REGNUM)
849 (compare:CC_NOOV
850 (plus:SI (match_operand:SI 0 "s_register_operand" "l, r")
851 (match_operand:SI 1 "arm_add_operand" "lPv,rIL"))
852 (const_int 0)))]
853 "TARGET_THUMB2"
854 "*
855 HOST_WIDE_INT val;
856
857 if (GET_CODE (operands[1]) == CONST_INT)
858 val = INTVAL (operands[1]);
859 else
860 val = 0;
861
862 if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
863 return \"cmp\\t%0, #%n1\";
864 else
865 return \"cmn\\t%0, %1\";
866 "
867 [(set_attr "conds" "set")
868 (set_attr "length" "2,4")]
869 )
870
871 ;; 16-bit encodings of "muls" and "mul<c>". We only use these when
872 ;; optimizing for size since "muls" is slow on all known
873 ;; implementations and since "mul<c>" will be generated by
874 ;; "*arm_mulsi3_v6" anyhow. The assembler will use a 16-bit encoding
875 ;; for "mul<c>" whenever possible anyhow.
876 (define_peephole2
877 [(set (match_operand:SI 0 "low_register_operand" "")
878 (mult:SI (match_operand:SI 1 "low_register_operand" "")
879 (match_dup 0)))]
880 "TARGET_THUMB2 && optimize_size && peep2_regno_dead_p (0, CC_REGNUM)"
881 [(parallel
882 [(set (match_dup 0)
883 (mult:SI (match_dup 0) (match_dup 1)))
884 (clobber (reg:CC CC_REGNUM))])]
885 ""
886 )
887
888 (define_peephole2
889 [(set (match_operand:SI 0 "low_register_operand" "")
890 (mult:SI (match_dup 0)
891 (match_operand:SI 1 "low_register_operand" "")))]
892 "TARGET_THUMB2 && optimize_size && peep2_regno_dead_p (0, CC_REGNUM)"
893 [(parallel
894 [(set (match_dup 0)
895 (mult:SI (match_dup 0) (match_dup 1)))
896 (clobber (reg:CC CC_REGNUM))])]
897 ""
898 )
899
900 (define_insn "*thumb2_mulsi_short"
901 [(set (match_operand:SI 0 "low_register_operand" "=l")
902 (mult:SI (match_operand:SI 1 "low_register_operand" "%0")
903 (match_operand:SI 2 "low_register_operand" "l")))
904 (clobber (reg:CC CC_REGNUM))]
905 "TARGET_THUMB2 && optimize_size && reload_completed"
906 "mul%!\\t%0, %2, %0"
907 [(set_attr "predicable" "yes")
908 (set_attr "length" "2")
909 (set_attr "insn" "muls")])
910
911 (define_insn "*thumb2_mulsi_short_compare0"
912 [(set (reg:CC_NOOV CC_REGNUM)
913 (compare:CC_NOOV
914 (mult:SI (match_operand:SI 1 "register_operand" "%0")
915 (match_operand:SI 2 "register_operand" "l"))
916 (const_int 0)))
917 (set (match_operand:SI 0 "register_operand" "=l")
918 (mult:SI (match_dup 1) (match_dup 2)))]
919 "TARGET_THUMB2 && optimize_size"
920 "muls\\t%0, %2, %0"
921 [(set_attr "length" "2")
922 (set_attr "insn" "muls")])
923
924 (define_insn "*thumb2_mulsi_short_compare0_scratch"
925 [(set (reg:CC_NOOV CC_REGNUM)
926 (compare:CC_NOOV
927 (mult:SI (match_operand:SI 1 "register_operand" "%0")
928 (match_operand:SI 2 "register_operand" "l"))
929 (const_int 0)))
930 (clobber (match_scratch:SI 0 "=l"))]
931 "TARGET_THUMB2 && optimize_size"
932 "muls\\t%0, %2, %0"
933 [(set_attr "length" "2")
934 (set_attr "insn" "muls")])
935
936 (define_insn "*thumb2_cbz"
937 [(set (pc) (if_then_else
938 (eq (match_operand:SI 0 "s_register_operand" "l,?r")
939 (const_int 0))
940 (label_ref (match_operand 1 "" ""))
941 (pc)))
942 (clobber (reg:CC CC_REGNUM))]
943 "TARGET_THUMB2"
944 "*
945 if (get_attr_length (insn) == 2)
946 return \"cbz\\t%0, %l1\";
947 else
948 return \"cmp\\t%0, #0\;beq\\t%l1\";
949 "
950 [(set (attr "length")
951 (if_then_else
952 (and (ge (minus (match_dup 1) (pc)) (const_int 2))
953 (le (minus (match_dup 1) (pc)) (const_int 128))
954 (not (match_test "which_alternative")))
955 (const_int 2)
956 (const_int 8)))]
957 )
958
959 (define_insn "*thumb2_cbnz"
960 [(set (pc) (if_then_else
961 (ne (match_operand:SI 0 "s_register_operand" "l,?r")
962 (const_int 0))
963 (label_ref (match_operand 1 "" ""))
964 (pc)))
965 (clobber (reg:CC CC_REGNUM))]
966 "TARGET_THUMB2"
967 "*
968 if (get_attr_length (insn) == 2)
969 return \"cbnz\\t%0, %l1\";
970 else
971 return \"cmp\\t%0, #0\;bne\\t%l1\";
972 "
973 [(set (attr "length")
974 (if_then_else
975 (and (ge (minus (match_dup 1) (pc)) (const_int 2))
976 (le (minus (match_dup 1) (pc)) (const_int 128))
977 (not (match_test "which_alternative")))
978 (const_int 2)
979 (const_int 8)))]
980 )
981
982 ;; 16-bit complement
983 (define_peephole2
984 [(set (match_operand:SI 0 "low_register_operand" "")
985 (not:SI (match_operand:SI 1 "low_register_operand" "")))]
986 "TARGET_THUMB2
987 && peep2_regno_dead_p(0, CC_REGNUM)"
988 [(parallel
989 [(set (match_dup 0)
990 (not:SI (match_dup 1)))
991 (clobber (reg:CC CC_REGNUM))])]
992 ""
993 )
994
995 (define_insn "*thumb2_one_cmplsi2_short"
996 [(set (match_operand:SI 0 "low_register_operand" "=l")
997 (not:SI (match_operand:SI 1 "low_register_operand" "l")))
998 (clobber (reg:CC CC_REGNUM))]
999 "TARGET_THUMB2 && reload_completed"
1000 "mvn%!\t%0, %1"
1001 [(set_attr "predicable" "yes")
1002 (set_attr "length" "2")]
1003 )
1004
1005 ;; 16-bit negate
1006 (define_peephole2
1007 [(set (match_operand:SI 0 "low_register_operand" "")
1008 (neg:SI (match_operand:SI 1 "low_register_operand" "")))]
1009 "TARGET_THUMB2
1010 && peep2_regno_dead_p(0, CC_REGNUM)"
1011 [(parallel
1012 [(set (match_dup 0)
1013 (neg:SI (match_dup 1)))
1014 (clobber (reg:CC CC_REGNUM))])]
1015 ""
1016 )
1017
1018 (define_insn "*thumb2_negsi2_short"
1019 [(set (match_operand:SI 0 "low_register_operand" "=l")
1020 (neg:SI (match_operand:SI 1 "low_register_operand" "l")))
1021 (clobber (reg:CC CC_REGNUM))]
1022 "TARGET_THUMB2 && reload_completed"
1023 "neg%!\t%0, %1"
1024 [(set_attr "predicable" "yes")
1025 (set_attr "length" "2")]
1026 )
1027
1028 (define_insn "*orsi_notsi_si"
1029 [(set (match_operand:SI 0 "s_register_operand" "=r")
1030 (ior:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
1031 (match_operand:SI 1 "s_register_operand" "r")))]
1032 "TARGET_THUMB2"
1033 "orn%?\\t%0, %1, %2"
1034 [(set_attr "predicable" "yes")]
1035 )
1036
1037 (define_insn "*orsi_not_shiftsi_si"
1038 [(set (match_operand:SI 0 "s_register_operand" "=r")
1039 (ior:SI (not:SI (match_operator:SI 4 "shift_operator"
1040 [(match_operand:SI 2 "s_register_operand" "r")
1041 (match_operand:SI 3 "const_int_operand" "M")]))
1042 (match_operand:SI 1 "s_register_operand" "r")))]
1043 "TARGET_THUMB2"
1044 "orn%?\\t%0, %1, %2%S4"
1045 [(set_attr "predicable" "yes")
1046 (set_attr "shift" "2")
1047 (set_attr "type" "alu_shift")]
1048 )
1049
1050 (define_peephole2
1051 [(set (match_operand:CC_NOOV 0 "cc_register" "")
1052 (compare:CC_NOOV (zero_extract:SI
1053 (match_operand:SI 1 "low_register_operand" "")
1054 (const_int 1)
1055 (match_operand:SI 2 "const_int_operand" ""))
1056 (const_int 0)))
1057 (match_scratch:SI 3 "l")
1058 (set (pc)
1059 (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
1060 [(match_dup 0) (const_int 0)])
1061 (match_operand 5 "" "")
1062 (match_operand 6 "" "")))]
1063 "TARGET_THUMB2
1064 && (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32)"
1065 [(parallel [(set (match_dup 0)
1066 (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
1067 (const_int 0)))
1068 (clobber (match_dup 3))])
1069 (set (pc)
1070 (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1071 (match_dup 5) (match_dup 6)))]
1072 "
1073 operands[2] = GEN_INT (31 - INTVAL (operands[2]));
1074 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? LT : GE,
1075 VOIDmode, operands[0], const0_rtx);
1076 ")
1077
1078 (define_peephole2
1079 [(set (match_operand:CC_NOOV 0 "cc_register" "")
1080 (compare:CC_NOOV (zero_extract:SI
1081 (match_operand:SI 1 "low_register_operand" "")
1082 (match_operand:SI 2 "const_int_operand" "")
1083 (const_int 0))
1084 (const_int 0)))
1085 (match_scratch:SI 3 "l")
1086 (set (pc)
1087 (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
1088 [(match_dup 0) (const_int 0)])
1089 (match_operand 5 "" "")
1090 (match_operand 6 "" "")))]
1091 "TARGET_THUMB2
1092 && (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 32)"
1093 [(parallel [(set (match_dup 0)
1094 (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
1095 (const_int 0)))
1096 (clobber (match_dup 3))])
1097 (set (pc)
1098 (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1099 (match_dup 5) (match_dup 6)))]
1100 "
1101 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
1102 ")
1103
1104 ;; Define the subtract-one-and-jump insns so loop.c
1105 ;; knows what to generate.
1106 (define_expand "doloop_end"
1107 [(use (match_operand 0 "" "")) ; loop pseudo
1108 (use (match_operand 1 "" "")) ; iterations; zero if unknown
1109 (use (match_operand 2 "" "")) ; max iterations
1110 (use (match_operand 3 "" "")) ; loop level
1111 (use (match_operand 4 "" ""))] ; label
1112 "TARGET_32BIT"
1113 "
1114 {
1115 /* Currently SMS relies on the do-loop pattern to recognize loops
1116 where (1) the control part consists of all insns defining and/or
1117 using a certain 'count' register and (2) the loop count can be
1118 adjusted by modifying this register prior to the loop.
1119 ??? The possible introduction of a new block to initialize the
1120 new IV can potentially affect branch optimizations. */
1121 if (optimize > 0 && flag_modulo_sched)
1122 {
1123 rtx s0;
1124 rtx bcomp;
1125 rtx loc_ref;
1126 rtx cc_reg;
1127 rtx insn;
1128 rtx cmp;
1129
1130 /* Only use this on innermost loops. */
1131 if (INTVAL (operands[3]) > 1)
1132 FAIL;
1133
1134 if (GET_MODE (operands[0]) != SImode)
1135 FAIL;
1136
1137 s0 = operands [0];
1138 if (TARGET_THUMB2)
1139 insn = emit_insn (gen_thumb2_addsi3_compare0 (s0, s0, GEN_INT (-1)));
1140 else
1141 insn = emit_insn (gen_addsi3_compare0 (s0, s0, GEN_INT (-1)));
1142
1143 cmp = XVECEXP (PATTERN (insn), 0, 0);
1144 cc_reg = SET_DEST (cmp);
1145 bcomp = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx);
1146 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [4]);
1147 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
1148 gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
1149 loc_ref, pc_rtx)));
1150 DONE;
1151 }else
1152 FAIL;
1153 }")
1154