gcc/config/arm/thumb2.md

   1 ;; ARM Thumb-2 Machine Description
   2 ;; Copyright (C) 2007 Free Software Foundation, Inc.
   3 ;; Written by CodeSourcery, LLC.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 2, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING.  If not, write to the Free
  19 ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  20 ;; 02111-1307, USA.  */
  21
  22 ;; Note: Thumb-2 is the variant of the Thumb architecture that adds
  23 ;; 32-bit encodings of [almost all of] the Arm instruction set.
  24 ;; Some old documents refer to the relatively minor interworking
  25 ;; changes made in armv5t as "thumb2".  These are considered part
  26 ;; the 16-bit Thumb-1 instruction set.
  27
  28 (define_insn "*thumb2_incscc"
  29   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
  30         (plus:SI (match_operator:SI 2 "arm_comparison_operator"
  31                     [(match_operand:CC 3 "cc_register" "") (const_int 0)])
  32                  (match_operand:SI 1 "s_register_operand" "0,?r")))]
  33   "TARGET_THUMB2"
  34   "@
  35   it\\t%d2\;add%d2\\t%0, %1, #1
  36   ite\\t%D2\;mov%D2\\t%0, %1\;add%d2\\t%0, %1, #1"
  37   [(set_attr "conds" "use")
  38    (set_attr "length" "6,10")]
  39 )
  40
  41 (define_insn "*thumb2_decscc"
  42   [(set (match_operand:SI            0 "s_register_operand" "=r,r")
  43         (minus:SI (match_operand:SI  1 "s_register_operand" "0,?r")
  44                   (match_operator:SI 2 "arm_comparison_operator"
  45                    [(match_operand   3 "cc_register" "") (const_int 0)])))]
  46   "TARGET_THUMB2"
  47   "@
  48    it\\t%d2\;sub%d2\\t%0, %1, #1
  49    ite\\t%D2\;mov%D2\\t%0, %1\;sub%d2\\t%0, %1, #1"
  50   [(set_attr "conds" "use")
  51    (set_attr "length" "6,10")]
  52 )
  53
  54 ;; Thumb-2 only allows shift by constant on data processing instructions
  55 (define_insn "*thumb_andsi_not_shiftsi_si"
  56   [(set (match_operand:SI 0 "s_register_operand" "=r")
  57         (and:SI (not:SI (match_operator:SI 4 "shift_operator"
  58                          [(match_operand:SI 2 "s_register_operand" "r")
  59                           (match_operand:SI 3 "const_int_operand" "M")]))
  60                 (match_operand:SI 1 "s_register_operand" "r")))]
  61   "TARGET_ARM"
  62   "bic%?\\t%0, %1, %2%S4"
  63   [(set_attr "predicable" "yes")
  64    (set_attr "shift" "2")
  65    (set_attr "type" "alu_shift")]
  66 )
  67
  68 (define_insn "*thumb2_smaxsi3"
  69   [(set (match_operand:SI          0 "s_register_operand" "=r,r,r")
  70         (smax:SI (match_operand:SI 1 "s_register_operand"  "0,r,?r")
  71                  (match_operand:SI 2 "arm_rhs_operand"    "rI,0,rI")))
  72    (clobber (reg:CC CC_REGNUM))]
  73   "TARGET_THUMB2"
  74   "@
  75    cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2
  76    cmp\\t%1, %2\;it\\tge\;movge\\t%0, %1
  77    cmp\\t%1, %2\;ite\\tge\;movge\\t%0, %1\;movlt\\t%0, %2"
  78   [(set_attr "conds" "clob")
  79    (set_attr "length" "10,10,14")]
  80 )
  81
  82 (define_insn "*thumb2_sminsi3"
  83   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
  84         (smin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
  85                  (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
  86    (clobber (reg:CC CC_REGNUM))]
  87   "TARGET_THUMB2"
  88   "@
  89    cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2
  90    cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %1
  91    cmp\\t%1, %2\;ite\\tlt\;movlt\\t%0, %1\;movge\\t%0, %2"
  92   [(set_attr "conds" "clob")
  93    (set_attr "length" "10,10,14")]
  94 )
  95
  96 (define_insn "*thumb32_umaxsi3"
  97   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
  98         (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
  99                  (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
 100    (clobber (reg:CC CC_REGNUM))]
 101   "TARGET_THUMB2"
 102   "@
 103    cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2
 104    cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %1
 105    cmp\\t%1, %2\;ite\\tcs\;movcs\\t%0, %1\;movcc\\t%0, %2"
 106   [(set_attr "conds" "clob")
 107    (set_attr "length" "10,10,14")]
 108 )
 109
 110 (define_insn "*thumb2_uminsi3"
 111   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
 112         (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
 113                  (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
 114    (clobber (reg:CC CC_REGNUM))]
 115   "TARGET_THUMB2"
 116   "@
 117    cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2
 118    cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %1
 119    cmp\\t%1, %2\;ite\\tcc\;movcc\\t%0, %1\;movcs\\t%0, %2"
 120   [(set_attr "conds" "clob")
 121    (set_attr "length" "10,10,14")]
 122 )
 123
 124 (define_insn "*thumb2_notsi_shiftsi"
 125   [(set (match_operand:SI 0 "s_register_operand" "=r")
 126         (not:SI (match_operator:SI 3 "shift_operator"
 127                  [(match_operand:SI 1 "s_register_operand" "r")
 128                   (match_operand:SI 2 "const_int_operand"  "M")])))]
 129   "TARGET_THUMB2"
 130   "mvn%?\\t%0, %1%S3"
 131   [(set_attr "predicable" "yes")
 132    (set_attr "shift" "1")
 133    (set_attr "type" "alu_shift")]
 134 )
 135
 136 (define_insn "*thumb2_notsi_shiftsi_compare0"
 137   [(set (reg:CC_NOOV CC_REGNUM)
 138         (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
 139                           [(match_operand:SI 1 "s_register_operand" "r")
 140                            (match_operand:SI 2 "const_int_operand"  "M")]))
 141                          (const_int 0)))
 142    (set (match_operand:SI 0 "s_register_operand" "=r")
 143         (not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))]
 144   "TARGET_THUMB2"
 145   "mvn%.\\t%0, %1%S3"
 146   [(set_attr "conds" "set")
 147    (set_attr "shift" "1")
 148    (set_attr "type" "alu_shift")]
 149 )
 150
 151 (define_insn "*thumb2_not_shiftsi_compare0_scratch"
 152   [(set (reg:CC_NOOV CC_REGNUM)
 153         (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
 154                           [(match_operand:SI 1 "s_register_operand" "r")
 155                            (match_operand:SI 2 "const_int_operand"  "M")]))
 156                          (const_int 0)))
 157    (clobber (match_scratch:SI 0 "=r"))]
 158   "TARGET_THUMB2"
 159   "mvn%.\\t%0, %1%S3"
 160   [(set_attr "conds" "set")
 161    (set_attr "shift" "1")
 162    (set_attr "type" "alu_shift")]
 163 )
 164
 165 ;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
 166 (define_insn "*thumb2_negdi2"
 167   [(set (match_operand:DI         0 "s_register_operand" "=&r,r")
 168         (neg:DI (match_operand:DI 1 "s_register_operand"  "?r,0")))
 169    (clobber (reg:CC CC_REGNUM))]
 170   "TARGET_THUMB2"
 171   "negs\\t%Q0, %Q1\;sbc\\t%R0, %R1, %R1, lsl #1"
 172   [(set_attr "conds" "clob")
 173    (set_attr "length" "8")]
 174 )
 175
 176 (define_insn "*thumb2_abssi2"
 177   [(set (match_operand:SI         0 "s_register_operand" "=r,&r")
 178         (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
 179    (clobber (reg:CC CC_REGNUM))]
 180   "TARGET_THUMB2"
 181   "@
 182    cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
 183    eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31"
 184   [(set_attr "conds" "clob,*")
 185    (set_attr "shift" "1")
 186    ;; predicable can't be set based on the variant, so left as no
 187    (set_attr "length" "10,8")]
 188 )
 189
 190 (define_insn "*thumb2_neg_abssi2"
 191   [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
 192         (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
 193    (clobber (reg:CC CC_REGNUM))]
 194   "TARGET_THUMB2"
 195   "@
 196    cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
 197    eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31"
 198   [(set_attr "conds" "clob,*")
 199    (set_attr "shift" "1")
 200    ;; predicable can't be set based on the variant, so left as no
 201    (set_attr "length" "10,8")]
 202 )
 203
 204 (define_insn "*thumb2_movdi"
 205   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m")
 206         (match_operand:DI 1 "di_operand"              "rDa,Db,Dc,mi,r"))]
 207   "TARGET_THUMB2
 208   && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP))
 209   && !TARGET_IWMMXT"
 210   "*
 211   switch (which_alternative)
 212     {
 213     case 0:
 214     case 1:
 215     case 2:
 216       return \"#\";
 217     default:
 218       return output_move_double (operands);
 219     }
 220   "
 221   [(set_attr "length" "8,12,16,8,8")
 222    (set_attr "type" "*,*,*,load2,store2")
 223    (set_attr "pool_range" "*,*,*,4096,*")
 224    (set_attr "neg_pool_range" "*,*,*,0,*")]
 225 )
 226
 227 (define_insn "*thumb2_movsi_insn"
 228   [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r, m")
 229         (match_operand:SI 1 "general_operand"      "rI,K,N,mi,r"))]
 230   "TARGET_THUMB2 && ! TARGET_IWMMXT
 231    && !(TARGET_HARD_FLOAT && TARGET_VFP)
 232    && (   register_operand (operands[0], SImode)
 233        || register_operand (operands[1], SImode))"
 234   "@
 235    mov%?\\t%0, %1
 236    mvn%?\\t%0, #%B1
 237    movw%?\\t%0, %1
 238    ldr%?\\t%0, %1
 239    str%?\\t%1, %0"
 240   [(set_attr "type" "*,*,*,load1,store1")
 241    (set_attr "predicable" "yes")
 242    (set_attr "pool_range" "*,*,*,4096,*")
 243    (set_attr "neg_pool_range" "*,*,*,0,*")]
 244 )
 245
 246 ;; ??? We can probably do better with thumb2
 247 (define_insn "pic_load_addr_thumb2"
 248   [(set (match_operand:SI 0 "s_register_operand" "=r")
 249         (unspec:SI [(match_operand:SI 1 "" "mX")] UNSPEC_PIC_SYM))]
 250   "TARGET_THUMB2 && flag_pic"
 251   "ldr%?\\t%0, %1"
 252   [(set_attr "type" "load1")
 253    (set_attr "pool_range" "4096")
 254    (set_attr "neg_pool_range" "0")]
 255 )
 256
 257 ;; Set reg to the address of this instruction plus four.  The low two
 258 ;; bits of the PC are always read as zero, so ensure the instructions is
 259 ;; word aligned.
 260 (define_insn "pic_load_dot_plus_four"
 261   [(set (match_operand:SI 0 "register_operand" "=r")
 262         (unspec:SI [(const (plus:SI (pc) (const_int 4)))
 263                     (use (match_operand 1 "" ""))]
 264                    UNSPEC_PIC_BASE))]
 265   "TARGET_THUMB2"
 266   "*
 267   assemble_align(BITS_PER_WORD);
 268   (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
 269                              INTVAL (operands[1]));
 270   /* We use adr because some buggy gas assemble add r8, pc, #0
 271      to add.w r8, pc, #0, not addw r8, pc, #0.  */
 272   asm_fprintf (asm_out_file, \"\\tadr\\t%r, %LLPIC%d + 4\\n\",
 273                REGNO(operands[0]), (int)INTVAL (operands[1]));
 274   return \"\";
 275   "
 276   [(set_attr "length" "6")]
 277 )
 278
 279 ;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
 280 ;; of the messiness associated with the ARM patterns.
 281 (define_insn "*thumb2_movhi_insn"
 282   [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
 283         (match_operand:HI 1 "general_operand"      "rI,n,r,m"))]
 284   "TARGET_THUMB2"
 285   "@
 286    mov%?\\t%0, %1\\t%@ movhi
 287    movw%?\\t%0, %L1\\t%@ movhi
 288    str%(h%)\\t%1, %0\\t%@ movhi
 289    ldr%(h%)\\t%0, %1\\t%@ movhi"
 290   [(set_attr "type" "*,*,store1,load1")
 291    (set_attr "predicable" "yes")
 292    (set_attr "pool_range" "*,*,*,4096")
 293    (set_attr "neg_pool_range" "*,*,*,250")]
 294 )
 295
 296 (define_insn "*thumb2_movsf_soft_insn"
 297   [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
 298         (match_operand:SF 1 "general_operand"  "r,mE,r"))]
 299   "TARGET_THUMB2
 300    && TARGET_SOFT_FLOAT
 301    && (GET_CODE (operands[0]) != MEM
 302        || register_operand (operands[1], SFmode))"
 303   "@
 304    mov%?\\t%0, %1
 305    ldr%?\\t%0, %1\\t%@ float
 306    str%?\\t%1, %0\\t%@ float"
 307   [(set_attr "predicable" "yes")
 308    (set_attr "type" "*,load1,store1")
 309    (set_attr "pool_range" "*,4096,*")
 310    (set_attr "neg_pool_range" "*,0,*")]
 311 )
 312
 313 (define_insn "*thumb2_movdf_soft_insn"
 314   [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,r,r,m")
 315         (match_operand:DF 1 "soft_df_operand" "rDa,Db,Dc,mF,r"))]
 316   "TARGET_THUMB2 && TARGET_SOFT_FLOAT
 317    && (   register_operand (operands[0], DFmode)
 318        || register_operand (operands[1], DFmode))"
 319   "*
 320   switch (which_alternative)
 321     {
 322     case 0:
 323     case 1:
 324     case 2:
 325       return \"#\";
 326     default:
 327       return output_move_double (operands);
 328     }
 329   "
 330   [(set_attr "length" "8,12,16,8,8")
 331    (set_attr "type" "*,*,*,load2,store2")
 332    (set_attr "pool_range" "1020")
 333    (set_attr "neg_pool_range" "0")]
 334 )
 335
 336 (define_insn "*thumb2_cmpsi_shiftsi"
 337   [(set (reg:CC CC_REGNUM)
 338         (compare:CC (match_operand:SI   0 "s_register_operand" "r")
 339                     (match_operator:SI  3 "shift_operator"
 340                      [(match_operand:SI 1 "s_register_operand" "r")
 341                       (match_operand:SI 2 "const_int_operand"  "M")])))]
 342   "TARGET_THUMB2"
 343   "cmp%?\\t%0, %1%S3"
 344   [(set_attr "conds" "set")
 345    (set_attr "shift" "1")
 346    (set_attr "type" "alu_shift")]
 347 )
 348
 349 (define_insn "*thumb2_cmpsi_shiftsi_swp"
 350   [(set (reg:CC_SWP CC_REGNUM)
 351         (compare:CC_SWP (match_operator:SI 3 "shift_operator"
 352                          [(match_operand:SI 1 "s_register_operand" "r")
 353                           (match_operand:SI 2 "const_int_operand" "M")])
 354                         (match_operand:SI 0 "s_register_operand" "r")))]
 355   "TARGET_THUMB2"
 356   "cmp%?\\t%0, %1%S3"
 357   [(set_attr "conds" "set")
 358    (set_attr "shift" "1")
 359    (set_attr "type" "alu_shift")]
 360 )
 361
 362 (define_insn "*thumb2_cmpsi_neg_shiftsi"
 363   [(set (reg:CC CC_REGNUM)
 364         (compare:CC (match_operand:SI 0 "s_register_operand" "r")
 365                     (neg:SI (match_operator:SI 3 "shift_operator"
 366                              [(match_operand:SI 1 "s_register_operand" "r")
 367                               (match_operand:SI 2 "const_int_operand" "M")]))))]
 368   "TARGET_THUMB2"
 369   "cmn%?\\t%0, %1%S3"
 370   [(set_attr "conds" "set")
 371    (set_attr "shift" "1")
 372    (set_attr "type" "alu_shift")]
 373 )
 374
 375 (define_insn "*thumb2_mov_scc"
 376   [(set (match_operand:SI 0 "s_register_operand" "=r")
 377         (match_operator:SI 1 "arm_comparison_operator"
 378          [(match_operand 2 "cc_register" "") (const_int 0)]))]
 379   "TARGET_THUMB2"
 380   "ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
 381   [(set_attr "conds" "use")
 382    (set_attr "length" "10")]
 383 )
 384
 385 (define_insn "*thumb2_mov_negscc"
 386   [(set (match_operand:SI 0 "s_register_operand" "=r")
 387         (neg:SI (match_operator:SI 1 "arm_comparison_operator"
 388                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 389   "TARGET_THUMB2"
 390   "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
 391   [(set_attr "conds" "use")
 392    (set_attr "length" "10")]
 393 )
 394
 395 (define_insn "*thumb2_mov_notscc"
 396   [(set (match_operand:SI 0 "s_register_operand" "=r")
 397         (not:SI (match_operator:SI 1 "arm_comparison_operator"
 398                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 399   "TARGET_THUMB2"
 400   "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #1"
 401   [(set_attr "conds" "use")
 402    (set_attr "length" "10")]
 403 )
 404
 405 (define_insn "*thumb2_movsicc_insn"
 406   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r")
 407         (if_then_else:SI
 408          (match_operator 3 "arm_comparison_operator"
 409           [(match_operand 4 "cc_register" "") (const_int 0)])
 410          (match_operand:SI 1 "arm_not_operand" "0,0,rI,K,rI,rI,K,K")
 411          (match_operand:SI 2 "arm_not_operand" "rI,K,0,0,rI,K,rI,K")))]
 412   "TARGET_THUMB2"
 413   "@
 414    it\\t%D3\;mov%D3\\t%0, %2
 415    it\\t%D3\;mvn%D3\\t%0, #%B2
 416    it\\t%d3\;mov%d3\\t%0, %1
 417    it\\t%d3\;mvn%d3\\t%0, #%B1
 418    ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
 419    ite\\t%d3\;mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2
 420    ite\\t%d3\;mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2
 421    ite\\t%d3\;mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2"
 422   [(set_attr "length" "6,6,6,6,10,10,10,10")
 423    (set_attr "conds" "use")]
 424 )
 425
 426 (define_insn "*thumb2_movsfcc_soft_insn"
 427   [(set (match_operand:SF 0 "s_register_operand" "=r,r")
 428         (if_then_else:SF (match_operator 3 "arm_comparison_operator"
 429                           [(match_operand 4 "cc_register" "") (const_int 0)])
 430                          (match_operand:SF 1 "s_register_operand" "0,r")
 431                          (match_operand:SF 2 "s_register_operand" "r,0")))]
 432   "TARGET_THUMB2 && TARGET_SOFT_FLOAT"
 433   "@
 434    it\\t%D3\;mov%D3\\t%0, %2
 435    it\\t%d3\;mov%d3\\t%0, %1"
 436   [(set_attr "length" "6,6")
 437    (set_attr "conds" "use")]
 438 )
 439
 440 (define_insn "*call_reg_thumb2"
 441   [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
 442          (match_operand 1 "" ""))
 443    (use (match_operand 2 "" ""))
 444    (clobber (reg:SI LR_REGNUM))]
 445   "TARGET_THUMB2"
 446   "blx%?\\t%0"
 447   [(set_attr "type" "call")]
 448 )
 449
 450 (define_insn "*call_value_reg_thumb2"
 451   [(set (match_operand 0 "" "")
 452         (call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
 453               (match_operand 2 "" "")))
 454    (use (match_operand 3 "" ""))
 455    (clobber (reg:SI LR_REGNUM))]
 456   "TARGET_THUMB2"
 457   "blx\\t%1"
 458   [(set_attr "type" "call")]
 459 )
 460
 461 (define_insn "*thumb2_indirect_jump"
 462   [(set (pc)
 463         (match_operand:SI 0 "register_operand" "l*r"))]
 464   "TARGET_THUMB2"
 465   "bx\\t%0"
 466   [(set_attr "conds" "clob")]
 467 )
 468 ;; Don't define thumb2_load_indirect_jump because we can't guarantee label
 469 ;; addresses will have the thumb bit set correctly.
 470
 471
 472 ;; Patterns to allow combination of arithmetic, cond code and shifts
 473
 474 (define_insn "*thumb2_arith_shiftsi"
 475   [(set (match_operand:SI 0 "s_register_operand" "=r")
 476         (match_operator:SI 1 "shiftable_operator"
 477           [(match_operator:SI 3 "shift_operator"
 478              [(match_operand:SI 4 "s_register_operand" "r")
 479               (match_operand:SI 5 "const_int_operand" "M")])
 480            (match_operand:SI 2 "s_register_operand" "r")]))]
 481   "TARGET_THUMB2"
 482   "%i1%?\\t%0, %2, %4%S3"
 483   [(set_attr "predicable" "yes")
 484    (set_attr "shift" "4")
 485    (set_attr "type" "alu_shift")]
 486 )
 487
 488 ;; ??? What does this splitter do?  Copied from the ARM version
 489 (define_split
 490   [(set (match_operand:SI 0 "s_register_operand" "")
 491         (match_operator:SI 1 "shiftable_operator"
 492          [(match_operator:SI 2 "shiftable_operator"
 493            [(match_operator:SI 3 "shift_operator"
 494              [(match_operand:SI 4 "s_register_operand" "")
 495               (match_operand:SI 5 "const_int_operand" "")])
 496             (match_operand:SI 6 "s_register_operand" "")])
 497           (match_operand:SI 7 "arm_rhs_operand" "")]))
 498    (clobber (match_operand:SI 8 "s_register_operand" ""))]
 499   "TARGET_32BIT"
 500   [(set (match_dup 8)
 501         (match_op_dup 2 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
 502                          (match_dup 6)]))
 503    (set (match_dup 0)
 504         (match_op_dup 1 [(match_dup 8) (match_dup 7)]))]
 505   "")
 506
 507 (define_insn "*thumb2_arith_shiftsi_compare0"
 508   [(set (reg:CC_NOOV CC_REGNUM)
 509         (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
 510                           [(match_operator:SI 3 "shift_operator"
 511                             [(match_operand:SI 4 "s_register_operand" "r")
 512                              (match_operand:SI 5 "const_int_operand" "M")])
 513                            (match_operand:SI 2 "s_register_operand" "r")])
 514                          (const_int 0)))
 515    (set (match_operand:SI 0 "s_register_operand" "=r")
 516         (match_op_dup 1 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
 517                          (match_dup 2)]))]
 518   "TARGET_32BIT"
 519   "%i1%.\\t%0, %2, %4%S3"
 520   [(set_attr "conds" "set")
 521    (set_attr "shift" "4")
 522    (set_attr "type" "alu_shift")]
 523 )
 524
 525 (define_insn "*thumb2_arith_shiftsi_compare0_scratch"
 526   [(set (reg:CC_NOOV CC_REGNUM)
 527         (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
 528                           [(match_operator:SI 3 "shift_operator"
 529                             [(match_operand:SI 4 "s_register_operand" "r")
 530                              (match_operand:SI 5 "const_int_operand" "M")])
 531                            (match_operand:SI 2 "s_register_operand" "r")])
 532                          (const_int 0)))
 533    (clobber (match_scratch:SI 0 "=r"))]
 534   "TARGET_THUMB2"
 535   "%i1%.\\t%0, %2, %4%S3"
 536   [(set_attr "conds" "set")
 537    (set_attr "shift" "4")
 538    (set_attr "type" "alu_shift")]
 539 )
 540
 541 (define_insn "*thumb2_sub_shiftsi"
 542   [(set (match_operand:SI 0 "s_register_operand" "=r")
 543         (minus:SI (match_operand:SI 1 "s_register_operand" "r")
 544                   (match_operator:SI 2 "shift_operator"
 545                    [(match_operand:SI 3 "s_register_operand" "r")
 546                     (match_operand:SI 4 "const_int_operand" "M")])))]
 547   "TARGET_THUMB2"
 548   "sub%?\\t%0, %1, %3%S2"
 549   [(set_attr "predicable" "yes")
 550    (set_attr "shift" "3")
 551    (set_attr "type" "alu_shift")]
 552 )
 553
 554 (define_insn "*thumb2_sub_shiftsi_compare0"
 555   [(set (reg:CC_NOOV CC_REGNUM)
 556         (compare:CC_NOOV
 557          (minus:SI (match_operand:SI 1 "s_register_operand" "r")
 558                    (match_operator:SI 2 "shift_operator"
 559                     [(match_operand:SI 3 "s_register_operand" "r")
 560                      (match_operand:SI 4 "const_int_operand" "M")]))
 561          (const_int 0)))
 562    (set (match_operand:SI 0 "s_register_operand" "=r")
 563         (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
 564                                                  (match_dup 4)])))]
 565   "TARGET_THUMB2"
 566   "sub%.\\t%0, %1, %3%S2"
 567   [(set_attr "conds" "set")
 568    (set_attr "shift" "3")
 569    (set_attr "type" "alu_shift")]
 570 )
 571
 572 (define_insn "*thumb2_sub_shiftsi_compare0_scratch"
 573   [(set (reg:CC_NOOV CC_REGNUM)
 574         (compare:CC_NOOV
 575          (minus:SI (match_operand:SI 1 "s_register_operand" "r")
 576                    (match_operator:SI 2 "shift_operator"
 577                     [(match_operand:SI 3 "s_register_operand" "r")
 578                      (match_operand:SI 4 "const_int_operand" "M")]))
 579          (const_int 0)))
 580    (clobber (match_scratch:SI 0 "=r"))]
 581   "TARGET_THUMB2"
 582   "sub%.\\t%0, %1, %3%S2"
 583   [(set_attr "conds" "set")
 584    (set_attr "shift" "3")
 585    (set_attr "type" "alu_shift")]
 586 )
 587
 588 (define_insn "*thumb2_and_scc"
 589   [(set (match_operand:SI 0 "s_register_operand" "=r")
 590         (and:SI (match_operator:SI 1 "arm_comparison_operator"
 591                  [(match_operand 3 "cc_register" "") (const_int 0)])
 592                 (match_operand:SI 2 "s_register_operand" "r")))]
 593   "TARGET_THUMB2"
 594   "ite\\t%D1\;mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1"
 595   [(set_attr "conds" "use")
 596    (set_attr "length" "10")]
 597 )
 598
 599 (define_insn "*thumb2_ior_scc"
 600   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 601         (ior:SI (match_operator:SI 2 "arm_comparison_operator"
 602                  [(match_operand 3 "cc_register" "") (const_int 0)])
 603                 (match_operand:SI 1 "s_register_operand" "0,?r")))]
 604   "TARGET_THUMB2"
 605   "@
 606    it\\t%d2\;orr%d2\\t%0, %1, #1
 607    ite\\t%D2\;mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1"
 608   [(set_attr "conds" "use")
 609    (set_attr "length" "6,10")]
 610 )
 611
 612 (define_insn "*thumb2_compare_scc"
 613   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 614         (match_operator:SI 1 "arm_comparison_operator"
 615          [(match_operand:SI 2 "s_register_operand" "r,r")
 616           (match_operand:SI 3 "arm_add_operand" "rI,L")]))
 617    (clobber (reg:CC CC_REGNUM))]
 618   "TARGET_THUMB2"
 619   "*
 620     if (operands[3] == const0_rtx)
 621       {
 622         if (GET_CODE (operands[1]) == LT)
 623           return \"lsr\\t%0, %2, #31\";
 624
 625         if (GET_CODE (operands[1]) == GE)
 626           return \"mvn\\t%0, %2\;lsr\\t%0, %0, #31\";
 627
 628         if (GET_CODE (operands[1]) == EQ)
 629           return \"rsbs\\t%0, %2, #1\;it\\tcc\;movcc\\t%0, #0\";
 630       }
 631
 632     if (GET_CODE (operands[1]) == NE)
 633       {
 634         if (which_alternative == 1)
 635           return \"adds\\t%0, %2, #%n3\;it\\tne\;movne\\t%0, #1\";
 636         return \"subs\\t%0, %2, %3\;it\\tne\;movne\\t%0, #1\";
 637       }
 638     if (which_alternative == 1)
 639       output_asm_insn (\"cmn\\t%2, #%n3\", operands);
 640     else
 641       output_asm_insn (\"cmp\\t%2, %3\", operands);
 642     return \"ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1\";
 643   "
 644   [(set_attr "conds" "clob")
 645    (set_attr "length" "14")]
 646 )
 647
 648 (define_insn "*thumb2_cond_move"
 649   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
 650         (if_then_else:SI (match_operator 3 "equality_operator"
 651                           [(match_operator 4 "arm_comparison_operator"
 652                             [(match_operand 5 "cc_register" "") (const_int 0)])
 653                            (const_int 0)])
 654                          (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
 655                          (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))]
 656   "TARGET_THUMB2"
 657   "*
 658     if (GET_CODE (operands[3]) == NE)
 659       {
 660         if (which_alternative != 1)
 661           output_asm_insn (\"it\\t%D4\;mov%D4\\t%0, %2\", operands);
 662         if (which_alternative != 0)
 663           output_asm_insn (\"it\\t%d4\;mov%d4\\t%0, %1\", operands);
 664         return \"\";
 665       }
 666     switch (which_alternative)
 667       {
 668       case 0:
 669         output_asm_insn (\"it\\t%d4\", operands);
 670         break;
 671       case 1:
 672         output_asm_insn (\"it\\t%D4\", operands);
 673         break;
 674       case 2:
 675         output_asm_insn (\"ite\\t%D4\", operands);
 676         break;
 677       default:
 678         abort();
 679       }
 680     if (which_alternative != 0)
 681       output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 682     if (which_alternative != 1)
 683       output_asm_insn (\"mov%d4\\t%0, %2\", operands);
 684     return \"\";
 685   "
 686   [(set_attr "conds" "use")
 687    (set_attr "length" "6,6,10")]
 688 )
 689
 690 (define_insn "*thumb2_cond_arith"
 691   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 692         (match_operator:SI 5 "shiftable_operator"
 693          [(match_operator:SI 4 "arm_comparison_operator"
 694            [(match_operand:SI 2 "s_register_operand" "r,r")
 695             (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
 696           (match_operand:SI 1 "s_register_operand" "0,?r")]))
 697    (clobber (reg:CC CC_REGNUM))]
 698   "TARGET_THUMB2"
 699   "*
 700     if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
 701       return \"%i5\\t%0, %1, %2, lsr #31\";
 702
 703     output_asm_insn (\"cmp\\t%2, %3\", operands);
 704     if (GET_CODE (operands[5]) == AND)
 705       {
 706         output_asm_insn (\"ite\\t%D4\", operands);
 707         output_asm_insn (\"mov%D4\\t%0, #0\", operands);
 708       }
 709     else if (GET_CODE (operands[5]) == MINUS)
 710       {
 711         output_asm_insn (\"ite\\t%D4\", operands);
 712         output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands);
 713       }
 714     else if (which_alternative != 0)
 715       {
 716         output_asm_insn (\"ite\\t%D4\", operands);
 717         output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 718       }
 719     else
 720       output_asm_insn (\"it\\t%d4\", operands);
 721     return \"%i5%d4\\t%0, %1, #1\";
 722   "
 723   [(set_attr "conds" "clob")
 724    (set_attr "length" "14")]
 725 )
 726
 727 (define_insn "*thumb2_cond_sub"
 728   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 729         (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r")
 730                   (match_operator:SI 4 "arm_comparison_operator"
 731                    [(match_operand:SI 2 "s_register_operand" "r,r")
 732                     (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
 733    (clobber (reg:CC CC_REGNUM))]
 734   "TARGET_THUMB2"
 735   "*
 736     output_asm_insn (\"cmp\\t%2, %3\", operands);
 737     if (which_alternative != 0)
 738       {
 739         output_asm_insn (\"ite\\t%D4\", operands);
 740         output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 741       }
 742     else
 743       output_asm_insn (\"it\\t%d4\", operands);
 744     return \"sub%d4\\t%0, %1, #1\";
 745   "
 746   [(set_attr "conds" "clob")
 747    (set_attr "length" "10,14")]
 748 )
 749
 750 (define_insn "*thumb2_negscc"
 751   [(set (match_operand:SI 0 "s_register_operand" "=r")
 752         (neg:SI (match_operator 3 "arm_comparison_operator"
 753                  [(match_operand:SI 1 "s_register_operand" "r")
 754                   (match_operand:SI 2 "arm_rhs_operand" "rI")])))
 755    (clobber (reg:CC CC_REGNUM))]
 756   "TARGET_THUMB2"
 757   "*
 758   if (GET_CODE (operands[3]) == LT && operands[3] == const0_rtx)
 759     return \"asr\\t%0, %1, #31\";
 760
 761   if (GET_CODE (operands[3]) == NE)
 762     return \"subs\\t%0, %1, %2\;it\\tne\;mvnne\\t%0, #0\";
 763
 764   if (GET_CODE (operands[3]) == GT)
 765     return \"subs\\t%0, %1, %2\;it\\tne\;mvnne\\t%0, %0, asr #31\";
 766
 767   output_asm_insn (\"cmp\\t%1, %2\", operands);
 768   output_asm_insn (\"ite\\t%D3\", operands);
 769   output_asm_insn (\"mov%D3\\t%0, #0\", operands);
 770   return \"mvn%d3\\t%0, #0\";
 771   "
 772   [(set_attr "conds" "clob")
 773    (set_attr "length" "14")]
 774 )
 775
 776 (define_insn "*thumb2_movcond"
 777   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
 778         (if_then_else:SI
 779          (match_operator 5 "arm_comparison_operator"
 780           [(match_operand:SI 3 "s_register_operand" "r,r,r")
 781            (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
 782          (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
 783          (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
 784    (clobber (reg:CC CC_REGNUM))]
 785   "TARGET_THUMB2"
 786   "*
 787   if (GET_CODE (operands[5]) == LT
 788       && (operands[4] == const0_rtx))
 789     {
 790       if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
 791         {
 792           if (operands[2] == const0_rtx)
 793             return \"and\\t%0, %1, %3, asr #31\";
 794           return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\";
 795         }
 796       else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
 797         {
 798           if (operands[1] == const0_rtx)
 799             return \"bic\\t%0, %2, %3, asr #31\";
 800           return \"bics\\t%0, %2, %3, asr #32\;it\\tcs\;movcs\\t%0, %1\";
 801         }
 802       /* The only case that falls through to here is when both ops 1 & 2
 803          are constants.  */
 804     }
 805
 806   if (GET_CODE (operands[5]) == GE
 807       && (operands[4] == const0_rtx))
 808     {
 809       if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
 810         {
 811           if (operands[2] == const0_rtx)
 812             return \"bic\\t%0, %1, %3, asr #31\";
 813           return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\";
 814         }
 815       else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
 816         {
 817           if (operands[1] == const0_rtx)
 818             return \"and\\t%0, %2, %3, asr #31\";
 819           return \"ands\\t%0, %2, %3, asr #32\;it\tcc\;movcc\\t%0, %1\";
 820         }
 821       /* The only case that falls through to here is when both ops 1 & 2
 822          are constants.  */
 823     }
 824   if (GET_CODE (operands[4]) == CONST_INT
 825       && !const_ok_for_arm (INTVAL (operands[4])))
 826     output_asm_insn (\"cmn\\t%3, #%n4\", operands);
 827   else
 828     output_asm_insn (\"cmp\\t%3, %4\", operands);
 829   switch (which_alternative)
 830     {
 831     case 0:
 832       output_asm_insn (\"it\\t%D5\", operands);
 833       break;
 834     case 1:
 835       output_asm_insn (\"it\\t%d5\", operands);
 836       break;
 837     case 2:
 838       output_asm_insn (\"ite\\t%d5\", operands);
 839       break;
 840     default:
 841       abort();
 842     }
 843   if (which_alternative != 0)
 844     output_asm_insn (\"mov%d5\\t%0, %1\", operands);
 845   if (which_alternative != 1)
 846     output_asm_insn (\"mov%D5\\t%0, %2\", operands);
 847   return \"\";
 848   "
 849   [(set_attr "conds" "clob")
 850    (set_attr "length" "10,10,14")]
 851 )
 852
 853 ;; Zero and sign extension instructions.
 854
 855 (define_insn "*thumb2_zero_extendsidi2"
 856   [(set (match_operand:DI 0 "s_register_operand" "=r")
 857         (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
 858   "TARGET_THUMB2"
 859   "*
 860     /* ??? Output both instructions unconditionally, otherwise the conditional
 861        execution insn counter gets confused.
 862     if (REGNO (operands[1])
 863         != REGNO (operands[0]) + (WORDS_BIG_ENDIAN ? 1 : 0)) */
 864       output_asm_insn (\"mov%?\\t%Q0, %1\", operands);
 865     return \"mov%?\\t%R0, #0\";
 866   "
 867   [(set_attr "length" "8")
 868    (set_attr "ce_count" "2")
 869    (set_attr "predicable" "yes")]
 870 )
 871
 872 (define_insn "*thumb2_zero_extendqidi2"
 873   [(set (match_operand:DI                 0 "s_register_operand"  "=r,r")
 874         (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
 875   "TARGET_THUMB2"
 876   "@
 877    and%?\\t%Q0, %1, #255\;mov%?\\t%R0, #0
 878    ldr%(b%)\\t%Q0, %1\;mov%?\\t%R0, #0"
 879   [(set_attr "length" "8")
 880    (set_attr "ce_count" "2")
 881    (set_attr "predicable" "yes")
 882    (set_attr "type" "*,load_byte")
 883    (set_attr "pool_range" "*,4092")
 884    (set_attr "neg_pool_range" "*,250")]
 885 )
 886
 887 (define_insn "*thumb2_extendsidi2"
 888   [(set (match_operand:DI 0 "s_register_operand" "=r")
 889         (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
 890   "TARGET_THUMB2"
 891   "*
 892     /* ??? Output both instructions unconditionally, otherwise the conditional
 893        execution insn counter gets confused.
 894     if (REGNO (operands[1])
 895         != REGNO (operands[0]) + (WORDS_BIG_ENDIAN ? 1 : 0)) */
 896       output_asm_insn (\"mov%?\\t%Q0, %1\", operands);
 897     return \"asr%?\\t%R0, %Q0, #31\";
 898   "
 899   [(set_attr "length" "8")
 900    (set_attr "ce_count" "2")
 901    (set_attr "shift" "1")
 902    (set_attr "predicable" "yes")]
 903 )
 904
 905 ;; All supported Thumb2 implementations are armv6, so only that case is
 906 ;; provided.
 907 (define_insn "*thumb2_extendqisi_v6"
 908   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 909         (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
 910   "TARGET_THUMB2 && arm_arch6"
 911   "@
 912    sxtb%?\\t%0, %1
 913    ldr%(sb%)\\t%0, %1"
 914   [(set_attr "type" "alu_shift,load_byte")
 915    (set_attr "predicable" "yes")
 916    (set_attr "pool_range" "*,4096")
 917    (set_attr "neg_pool_range" "*,250")]
 918 )
 919
 920 (define_insn "*thumb2_zero_extendhisi2_v6"
 921   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 922         (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
 923   "TARGET_THUMB2 && arm_arch6"
 924   "@
 925    uxth%?\\t%0, %1
 926    ldr%(h%)\\t%0, %1"
 927   [(set_attr "type" "alu_shift,load_byte")
 928    (set_attr "predicable" "yes")
 929    (set_attr "pool_range" "*,4096")
 930    (set_attr "neg_pool_range" "*,250")]
 931 )
 932
 933 (define_insn "*thumb2_zero_extendqisi2_v6"
 934   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 935         (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
 936   "TARGET_THUMB2 && arm_arch6"
 937   "@
 938    uxtb%(%)\\t%0, %1
 939    ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
 940   [(set_attr "type" "alu_shift,load_byte")
 941    (set_attr "predicable" "yes")
 942    (set_attr "pool_range" "*,4096")
 943    (set_attr "neg_pool_range" "*,250")]
 944 )
 945
 946 (define_insn "thumb2_casesi_internal"
 947   [(parallel [(set (pc)
 948                (if_then_else
 949                 (leu (match_operand:SI 0 "s_register_operand" "r")
 950                      (match_operand:SI 1 "arm_rhs_operand" "rI"))
 951                 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
 952                                  (label_ref (match_operand 2 "" ""))))
 953                 (label_ref (match_operand 3 "" ""))))
 954               (clobber (reg:CC CC_REGNUM))
 955               (clobber (match_scratch:SI 4 "=r"))
 956               (use (label_ref (match_dup 2)))])]
 957   "TARGET_THUMB2 && !flag_pic"
 958   "* return thumb2_output_casesi(operands);"
 959   [(set_attr "conds" "clob")
 960    (set_attr "length" "16")]
 961 )
 962
 963 (define_insn "thumb2_casesi_internal_pic"
 964   [(parallel [(set (pc)
 965                (if_then_else
 966                 (leu (match_operand:SI 0 "s_register_operand" "r")
 967                      (match_operand:SI 1 "arm_rhs_operand" "rI"))
 968                 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
 969                                  (label_ref (match_operand 2 "" ""))))
 970                 (label_ref (match_operand 3 "" ""))))
 971               (clobber (reg:CC CC_REGNUM))
 972               (clobber (match_scratch:SI 4 "=r"))
 973               (clobber (match_scratch:SI 5 "=r"))
 974               (use (label_ref (match_dup 2)))])]
 975   "TARGET_THUMB2 && flag_pic"
 976   "* return thumb2_output_casesi(operands);"
 977   [(set_attr "conds" "clob")
 978    (set_attr "length" "20")]
 979 )
 980
 981 (define_insn_and_split "thumb2_eh_return"
 982   [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
 983                     VUNSPEC_EH_RETURN)
 984    (clobber (match_scratch:SI 1 "=&r"))]
 985   "TARGET_THUMB2"
 986   "#"
 987   "&& reload_completed"
 988   [(const_int 0)]
 989   "
 990   {
 991     thumb_set_return_address (operands[0], operands[1]);
 992     DONE;
 993   }"
 994 )
 995
 996 ;; Peepholes and insns for 16-bit flag clobbering instructions.
 997 ;; The conditional forms of these instructions do not clobber CC.
 998 ;; However by the time peepholes are run it is probably too late to do
 999 ;; anything useful with this information.
1000 (define_peephole2
1001   [(set (match_operand:SI          0 "low_register_operand" "")
1002         (match_operator:SI 3 "thumb_16bit_operator"
1003          [(match_operand:SI 1  "low_register_operand" "")
1004           (match_operand:SI 2 "low_register_operand" "")]))]
1005   "TARGET_THUMB2 && rtx_equal_p(operands[0], operands[1])
1006    && peep2_regno_dead_p(0, CC_REGNUM)"
1007   [(parallel
1008     [(set (match_dup 0)
1009           (match_op_dup 3
1010            [(match_dup 1)
1011             (match_dup 2)]))
1012      (clobber (reg:CC CC_REGNUM))])]
1013   ""
1014 )
1015
1016 (define_insn "*thumb2_alusi3_short"
1017   [(set (match_operand:SI          0 "s_register_operand" "=l")
1018         (match_operator:SI 3 "thumb_16bit_operator"
1019          [(match_operand:SI 1 "s_register_operand" "0")
1020           (match_operand:SI 2 "s_register_operand" "l")]))
1021    (clobber (reg:CC CC_REGNUM))]
1022   "TARGET_THUMB2 && reload_completed"
1023   "%I3%!\\t%0, %1, %2"
1024   [(set_attr "predicable" "yes")
1025    (set_attr "length" "2")]
1026 )
1027
1028 ;; Similarly for 16-bit shift instructions
1029 ;; There is no 16-bit rotate by immediate instruction.
1030 (define_peephole2
1031   [(set (match_operand:SI   0 "low_register_operand" "")
1032         (match_operator:SI  3 "shift_operator"
1033          [(match_operand:SI 1 "low_register_operand" "")
1034           (match_operand:SI 2 "low_reg_or_int_operand" "")]))]
1035   "TARGET_THUMB2
1036    && peep2_regno_dead_p(0, CC_REGNUM)
1037    && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
1038        || REG_P(operands[2]))"
1039   [(parallel
1040     [(set (match_dup 0)
1041           (match_op_dup 3
1042            [(match_dup 1)
1043             (match_dup 2)]))
1044      (clobber (reg:CC CC_REGNUM))])]
1045   ""
1046 )
1047
1048 (define_insn "*thumb2_shiftsi3_short"
1049   [(set (match_operand:SI   0 "low_register_operand" "=l")
1050         (match_operator:SI  3 "shift_operator"
1051          [(match_operand:SI 1 "low_register_operand"  "l")
1052           (match_operand:SI 2 "low_reg_or_int_operand" "lM")]))
1053    (clobber (reg:CC CC_REGNUM))]
1054   "TARGET_THUMB2 && reload_completed
1055    && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
1056        || REG_P(operands[2]))"
1057   "* return arm_output_shift(operands, 2);"
1058   [(set_attr "predicable" "yes")
1059    (set_attr "shift" "1")
1060    (set_attr "length" "2")
1061    (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
1062                       (const_string "alu_shift")
1063                       (const_string "alu_shift_reg")))]
1064 )
1065
1066 ;; 16-bit load immediate
1067 (define_peephole2
1068   [(set (match_operand:SI 0 "low_register_operand" "")
1069         (match_operand:SI 1 "const_int_operand" ""))]
1070   "TARGET_THUMB2
1071    && peep2_regno_dead_p(0, CC_REGNUM)
1072    && (unsigned HOST_WIDE_INT) INTVAL(operands[1]) < 256"
1073   [(parallel
1074     [(set (match_dup 0)
1075           (match_dup 1))
1076      (clobber (reg:CC CC_REGNUM))])]
1077   ""
1078 )
1079
1080 (define_insn "*thumb2_movsi_shortim"
1081   [(set (match_operand:SI 0 "low_register_operand" "=l")
1082         (match_operand:SI 1 "const_int_operand" "I"))
1083    (clobber (reg:CC CC_REGNUM))]
1084   "TARGET_THUMB2 && reload_completed"
1085   "mov%!\t%0, %1"
1086   [(set_attr "predicable" "yes")
1087    (set_attr "length" "2")]
1088 )
1089
1090 ;; 16-bit add/sub immediate
1091 (define_peephole2
1092   [(set (match_operand:SI 0 "low_register_operand" "")
1093         (plus:SI (match_operand:SI 1 "low_register_operand" "")
1094                  (match_operand:SI 2 "const_int_operand" "")))]
1095   "TARGET_THUMB2
1096    && peep2_regno_dead_p(0, CC_REGNUM)
1097    && ((rtx_equal_p(operands[0], operands[1])
1098         && INTVAL(operands[2]) > -256 && INTVAL(operands[2]) < 256)
1099        || (INTVAL(operands[2]) > -8 && INTVAL(operands[2]) < 8))"
1100   [(parallel
1101     [(set (match_dup 0)
1102           (plus:SI (match_dup 1)
1103                    (match_dup 2)))
1104      (clobber (reg:CC CC_REGNUM))])]
1105   ""
1106 )
1107
1108 (define_insn "*thumb2_addsi_shortim"
1109   [(set (match_operand:SI 0 "low_register_operand" "=l")
1110         (plus:SI (match_operand:SI 1 "low_register_operand" "l")
1111                  (match_operand:SI 2 "const_int_operand" "IL")))
1112    (clobber (reg:CC CC_REGNUM))]
1113   "TARGET_THUMB2 && reload_completed"
1114   "*
1115     HOST_WIDE_INT val;
1116
1117     val = INTVAL(operands[2]);
1118     /* We prefer eg. subs rn, rn, #1 over adds rn, rn, #0xffffffff.  */
1119     if (val < 0 && const_ok_for_arm(ARM_SIGN_EXTEND (-val)))
1120       return \"sub%!\\t%0, %1, #%n2\";
1121     else
1122       return \"add%!\\t%0, %1, %2\";
1123   "
1124   [(set_attr "predicable" "yes")
1125    (set_attr "length" "2")]
1126 )
1127
1128 (define_insn "divsi3"
1129   [(set (match_operand:SI         0 "s_register_operand" "=r")
1130         (div:SI (match_operand:SI 1 "s_register_operand"  "r")
1131                 (match_operand:SI 2 "s_register_operand"  "r")))]
1132   "TARGET_THUMB2 && arm_arch_hwdiv"
1133   "sdiv%?\t%0, %1, %2"
1134   [(set_attr "predicable" "yes")]
1135 )
1136
1137 (define_insn "udivsi3"
1138   [(set (match_operand:SI          0 "s_register_operand" "=r")
1139         (udiv:SI (match_operand:SI 1 "s_register_operand"  "r")
1140                  (match_operand:SI 2 "s_register_operand"  "r")))]
1141   "TARGET_THUMB2 && arm_arch_hwdiv"
1142   "udiv%?\t%0, %1, %2"
1143   [(set_attr "predicable" "yes")]
1144 )
1145
1146 (define_insn "*thumb2_cbz"
1147   [(set (pc) (if_then_else
1148               (eq (match_operand:SI 0 "s_register_operand" "l,?r")
1149                   (const_int 0))
1150               (label_ref (match_operand 1 "" ""))
1151               (pc)))
1152    (clobber (reg:CC CC_REGNUM))]
1153   "TARGET_THUMB2"
1154   "*
1155   if (get_attr_length (insn) == 2 && which_alternative == 0)
1156     return \"cbz\\t%0, %l1\";
1157   else
1158     return \"cmp\\t%0, #0\;beq\\t%l1\";
1159   "
1160   [(set (attr "length")
1161         (if_then_else
1162             (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1163                  (le (minus (match_dup 1) (pc)) (const_int 128)))
1164             (const_int 2)
1165             (const_int 8)))]
1166 )
1167
1168 (define_insn "*thumb2_cbnz"
1169   [(set (pc) (if_then_else
1170               (ne (match_operand:SI 0 "s_register_operand" "l,?r")
1171                   (const_int 0))
1172               (label_ref (match_operand 1 "" ""))
1173               (pc)))
1174    (clobber (reg:CC CC_REGNUM))]
1175   "TARGET_THUMB2"
1176   "*
1177   if (get_attr_length (insn) == 2 && which_alternative == 0)
1178     return \"cbnz\\t%0, %l1\";
1179   else
1180     return \"cmp\\t%0, #0\;bne\\t%l1\";
1181   "
1182   [(set (attr "length")
1183         (if_then_else
1184             (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1185                  (le (minus (match_dup 1) (pc)) (const_int 128)))
1186             (const_int 2)
1187             (const_int 8)))]
1188 )