1 ;; ARM Thumb-2 Machine Description
2 ;; Copyright (C) 2007, 2008 Free Software Foundation, Inc.
3 ;; Written by CodeSourcery, LLC.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>. */
21 ;; Note: Thumb-2 is the variant of the Thumb architecture that adds
22 ;; 32-bit encodings of [almost all of] the Arm instruction set.
23 ;; Some old documents refer to the relatively minor interworking
24 ;; changes made in armv5t as "thumb2". These are considered part
25 ;; the 16-bit Thumb-1 instruction set.
27 (define_insn "*thumb2_incscc"
28 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
29 (plus:SI (match_operator:SI 2 "arm_comparison_operator"
30 [(match_operand:CC 3 "cc_register" "") (const_int 0)])
31 (match_operand:SI 1 "s_register_operand" "0,?r")))]
34 it\\t%d2\;add%d2\\t%0, %1, #1
35 ite\\t%D2\;mov%D2\\t%0, %1\;add%d2\\t%0, %1, #1"
36 [(set_attr "conds" "use")
37 (set_attr "length" "6,10")]
40 (define_insn "*thumb2_decscc"
41 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
42 (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r")
43 (match_operator:SI 2 "arm_comparison_operator"
44 [(match_operand 3 "cc_register" "") (const_int 0)])))]
47 it\\t%d2\;sub%d2\\t%0, %1, #1
48 ite\\t%D2\;mov%D2\\t%0, %1\;sub%d2\\t%0, %1, #1"
49 [(set_attr "conds" "use")
50 (set_attr "length" "6,10")]
53 ;; Thumb-2 only allows shift by constant on data processing instructions
54 (define_insn "*thumb_andsi_not_shiftsi_si"
55 [(set (match_operand:SI 0 "s_register_operand" "=r")
56 (and:SI (not:SI (match_operator:SI 4 "shift_operator"
57 [(match_operand:SI 2 "s_register_operand" "r")
58 (match_operand:SI 3 "const_int_operand" "M")]))
59 (match_operand:SI 1 "s_register_operand" "r")))]
61 "bic%?\\t%0, %1, %2%S4"
62 [(set_attr "predicable" "yes")
63 (set_attr "shift" "2")
64 (set_attr "type" "alu_shift")]
67 (define_insn "*thumb2_smaxsi3"
68 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
69 (smax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
70 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
71 (clobber (reg:CC CC_REGNUM))]
74 cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2
75 cmp\\t%1, %2\;it\\tge\;movge\\t%0, %1
76 cmp\\t%1, %2\;ite\\tge\;movge\\t%0, %1\;movlt\\t%0, %2"
77 [(set_attr "conds" "clob")
78 (set_attr "length" "10,10,14")]
81 (define_insn "*thumb2_sminsi3"
82 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
83 (smin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
84 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
85 (clobber (reg:CC CC_REGNUM))]
88 cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2
89 cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %1
90 cmp\\t%1, %2\;ite\\tlt\;movlt\\t%0, %1\;movge\\t%0, %2"
91 [(set_attr "conds" "clob")
92 (set_attr "length" "10,10,14")]
95 (define_insn "*thumb32_umaxsi3"
96 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
97 (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
98 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
99 (clobber (reg:CC CC_REGNUM))]
102 cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2
103 cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %1
104 cmp\\t%1, %2\;ite\\tcs\;movcs\\t%0, %1\;movcc\\t%0, %2"
105 [(set_attr "conds" "clob")
106 (set_attr "length" "10,10,14")]
109 (define_insn "*thumb2_uminsi3"
110 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
111 (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
112 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
113 (clobber (reg:CC CC_REGNUM))]
116 cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2
117 cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %1
118 cmp\\t%1, %2\;ite\\tcc\;movcc\\t%0, %1\;movcs\\t%0, %2"
119 [(set_attr "conds" "clob")
120 (set_attr "length" "10,10,14")]
123 (define_insn "*thumb2_notsi_shiftsi"
124 [(set (match_operand:SI 0 "s_register_operand" "=r")
125 (not:SI (match_operator:SI 3 "shift_operator"
126 [(match_operand:SI 1 "s_register_operand" "r")
127 (match_operand:SI 2 "const_int_operand" "M")])))]
130 [(set_attr "predicable" "yes")
131 (set_attr "shift" "1")
132 (set_attr "type" "alu_shift")]
135 (define_insn "*thumb2_notsi_shiftsi_compare0"
136 [(set (reg:CC_NOOV CC_REGNUM)
137 (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
138 [(match_operand:SI 1 "s_register_operand" "r")
139 (match_operand:SI 2 "const_int_operand" "M")]))
141 (set (match_operand:SI 0 "s_register_operand" "=r")
142 (not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))]
145 [(set_attr "conds" "set")
146 (set_attr "shift" "1")
147 (set_attr "type" "alu_shift")]
150 (define_insn "*thumb2_not_shiftsi_compare0_scratch"
151 [(set (reg:CC_NOOV CC_REGNUM)
152 (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
153 [(match_operand:SI 1 "s_register_operand" "r")
154 (match_operand:SI 2 "const_int_operand" "M")]))
156 (clobber (match_scratch:SI 0 "=r"))]
159 [(set_attr "conds" "set")
160 (set_attr "shift" "1")
161 (set_attr "type" "alu_shift")]
164 ;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
165 (define_insn "*thumb2_negdi2"
166 [(set (match_operand:DI 0 "s_register_operand" "=&r,r")
167 (neg:DI (match_operand:DI 1 "s_register_operand" "?r,0")))
168 (clobber (reg:CC CC_REGNUM))]
170 "negs\\t%Q0, %Q1\;sbc\\t%R0, %R1, %R1, lsl #1"
171 [(set_attr "conds" "clob")
172 (set_attr "length" "8")]
175 (define_insn "*thumb2_abssi2"
176 [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
177 (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
178 (clobber (reg:CC CC_REGNUM))]
181 cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
182 eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31"
183 [(set_attr "conds" "clob,*")
184 (set_attr "shift" "1")
185 ;; predicable can't be set based on the variant, so left as no
186 (set_attr "length" "10,8")]
189 (define_insn "*thumb2_neg_abssi2"
190 [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
191 (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
192 (clobber (reg:CC CC_REGNUM))]
195 cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
196 eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31"
197 [(set_attr "conds" "clob,*")
198 (set_attr "shift" "1")
199 ;; predicable can't be set based on the variant, so left as no
200 (set_attr "length" "10,8")]
203 (define_insn "*thumb2_movdi"
204 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m")
205 (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r"))]
207 && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP))
210 switch (which_alternative)
217 return output_move_double (operands);
220 [(set_attr "length" "8,12,16,8,8")
221 (set_attr "type" "*,*,*,load2,store2")
222 (set_attr "pool_range" "*,*,*,4096,*")
223 (set_attr "neg_pool_range" "*,*,*,0,*")]
226 ;; We have two alternatives here for memory loads (and similarly for stores)
227 ;; to reflect the fact that the permissible constant pool ranges differ
228 ;; between ldr instructions taking low regs and ldr instructions taking high
229 ;; regs. The high register alternatives are not taken into account when
230 ;; choosing register preferences in order to reflect their expense.
231 (define_insn "*thumb2_movsi_insn"
232 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l ,*hk,m,*m")
233 (match_operand:SI 1 "general_operand" "rk ,I,K,j,mi,*mi,l,*hk"))]
234 "TARGET_THUMB2 && ! TARGET_IWMMXT
235 && !(TARGET_HARD_FLOAT && TARGET_VFP)
236 && ( register_operand (operands[0], SImode)
237 || register_operand (operands[1], SImode))"
247 [(set_attr "type" "*,*,*,*,load1,load1,store1,store1")
248 (set_attr "predicable" "yes")
249 (set_attr "pool_range" "*,*,*,*,1020,4096,*,*")
250 (set_attr "neg_pool_range" "*,*,*,*,0,0,*,*")]
253 (define_insn "tls_load_dot_plus_four"
254 [(set (match_operand:SI 0 "register_operand" "=l,l,r,r")
255 (mem:SI (unspec:SI [(match_operand:SI 2 "register_operand" "0,1,0,1")
257 (match_operand 3 "" "")]
259 (clobber (match_scratch:SI 1 "=X,l,X,r"))]
262 (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
263 INTVAL (operands[3]));
264 return \"add\\t%2, %|pc\;ldr%?\\t%0, [%2]\";
266 [(set_attr "length" "4,4,6,6")]
269 ;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
270 ;; of the messiness associated with the ARM patterns.
271 (define_insn "*thumb2_movhi_insn"
272 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
273 (match_operand:HI 1 "general_operand" "rI,n,r,m"))]
276 mov%?\\t%0, %1\\t%@ movhi
277 movw%?\\t%0, %L1\\t%@ movhi
278 str%(h%)\\t%1, %0\\t%@ movhi
279 ldr%(h%)\\t%0, %1\\t%@ movhi"
280 [(set_attr "type" "*,*,store1,load1")
281 (set_attr "predicable" "yes")
282 (set_attr "pool_range" "*,*,*,4096")
283 (set_attr "neg_pool_range" "*,*,*,250")]
286 (define_insn "*thumb2_movsf_soft_insn"
287 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
288 (match_operand:SF 1 "general_operand" "r,mE,r"))]
291 && (GET_CODE (operands[0]) != MEM
292 || register_operand (operands[1], SFmode))"
295 ldr%?\\t%0, %1\\t%@ float
296 str%?\\t%1, %0\\t%@ float"
297 [(set_attr "predicable" "yes")
298 (set_attr "type" "*,load1,store1")
299 (set_attr "pool_range" "*,4096,*")
300 (set_attr "neg_pool_range" "*,0,*")]
303 (define_insn "*thumb2_movdf_soft_insn"
304 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,r,r,m")
305 (match_operand:DF 1 "soft_df_operand" "rDa,Db,Dc,mF,r"))]
306 "TARGET_THUMB2 && TARGET_SOFT_FLOAT
307 && ( register_operand (operands[0], DFmode)
308 || register_operand (operands[1], DFmode))"
310 switch (which_alternative)
317 return output_move_double (operands);
320 [(set_attr "length" "8,12,16,8,8")
321 (set_attr "type" "*,*,*,load2,store2")
322 (set_attr "pool_range" "*,*,*,1020,*")
323 (set_attr "neg_pool_range" "*,*,*,0,*")]
326 (define_insn "*thumb2_cmpsi_shiftsi"
327 [(set (reg:CC CC_REGNUM)
328 (compare:CC (match_operand:SI 0 "s_register_operand" "r")
329 (match_operator:SI 3 "shift_operator"
330 [(match_operand:SI 1 "s_register_operand" "r")
331 (match_operand:SI 2 "const_int_operand" "M")])))]
334 [(set_attr "conds" "set")
335 (set_attr "shift" "1")
336 (set_attr "type" "alu_shift")]
339 (define_insn "*thumb2_cmpsi_shiftsi_swp"
340 [(set (reg:CC_SWP CC_REGNUM)
341 (compare:CC_SWP (match_operator:SI 3 "shift_operator"
342 [(match_operand:SI 1 "s_register_operand" "r")
343 (match_operand:SI 2 "const_int_operand" "M")])
344 (match_operand:SI 0 "s_register_operand" "r")))]
347 [(set_attr "conds" "set")
348 (set_attr "shift" "1")
349 (set_attr "type" "alu_shift")]
352 (define_insn "*thumb2_cmpsi_neg_shiftsi"
353 [(set (reg:CC CC_REGNUM)
354 (compare:CC (match_operand:SI 0 "s_register_operand" "r")
355 (neg:SI (match_operator:SI 3 "shift_operator"
356 [(match_operand:SI 1 "s_register_operand" "r")
357 (match_operand:SI 2 "const_int_operand" "M")]))))]
360 [(set_attr "conds" "set")
361 (set_attr "shift" "1")
362 (set_attr "type" "alu_shift")]
365 (define_insn "*thumb2_mov_scc"
366 [(set (match_operand:SI 0 "s_register_operand" "=r")
367 (match_operator:SI 1 "arm_comparison_operator"
368 [(match_operand 2 "cc_register" "") (const_int 0)]))]
370 "ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
371 [(set_attr "conds" "use")
372 (set_attr "length" "10")]
375 (define_insn "*thumb2_mov_negscc"
376 [(set (match_operand:SI 0 "s_register_operand" "=r")
377 (neg:SI (match_operator:SI 1 "arm_comparison_operator"
378 [(match_operand 2 "cc_register" "") (const_int 0)])))]
380 "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
381 [(set_attr "conds" "use")
382 (set_attr "length" "10")]
385 (define_insn "*thumb2_mov_notscc"
386 [(set (match_operand:SI 0 "s_register_operand" "=r")
387 (not:SI (match_operator:SI 1 "arm_comparison_operator"
388 [(match_operand 2 "cc_register" "") (const_int 0)])))]
390 "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #1"
391 [(set_attr "conds" "use")
392 (set_attr "length" "10")]
395 (define_insn "*thumb2_movsicc_insn"
396 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r")
398 (match_operator 3 "arm_comparison_operator"
399 [(match_operand 4 "cc_register" "") (const_int 0)])
400 (match_operand:SI 1 "arm_not_operand" "0,0,rI,K,rI,rI,K,K")
401 (match_operand:SI 2 "arm_not_operand" "rI,K,0,0,rI,K,rI,K")))]
404 it\\t%D3\;mov%D3\\t%0, %2
405 it\\t%D3\;mvn%D3\\t%0, #%B2
406 it\\t%d3\;mov%d3\\t%0, %1
407 it\\t%d3\;mvn%d3\\t%0, #%B1
408 ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
409 ite\\t%d3\;mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2
410 ite\\t%d3\;mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2
411 ite\\t%d3\;mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2"
412 [(set_attr "length" "6,6,6,6,10,10,10,10")
413 (set_attr "conds" "use")]
416 (define_insn "*thumb2_movsfcc_soft_insn"
417 [(set (match_operand:SF 0 "s_register_operand" "=r,r")
418 (if_then_else:SF (match_operator 3 "arm_comparison_operator"
419 [(match_operand 4 "cc_register" "") (const_int 0)])
420 (match_operand:SF 1 "s_register_operand" "0,r")
421 (match_operand:SF 2 "s_register_operand" "r,0")))]
422 "TARGET_THUMB2 && TARGET_SOFT_FLOAT"
424 it\\t%D3\;mov%D3\\t%0, %2
425 it\\t%d3\;mov%d3\\t%0, %1"
426 [(set_attr "length" "6,6")
427 (set_attr "conds" "use")]
430 (define_insn "*call_reg_thumb2"
431 [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
432 (match_operand 1 "" ""))
433 (use (match_operand 2 "" ""))
434 (clobber (reg:SI LR_REGNUM))]
437 [(set_attr "type" "call")]
440 (define_insn "*call_value_reg_thumb2"
441 [(set (match_operand 0 "" "")
442 (call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
443 (match_operand 2 "" "")))
444 (use (match_operand 3 "" ""))
445 (clobber (reg:SI LR_REGNUM))]
448 [(set_attr "type" "call")]
451 (define_insn "*thumb2_indirect_jump"
453 (match_operand:SI 0 "register_operand" "l*r"))]
456 [(set_attr "conds" "clob")]
458 ;; Don't define thumb2_load_indirect_jump because we can't guarantee label
459 ;; addresses will have the thumb bit set correctly.
462 ;; Patterns to allow combination of arithmetic, cond code and shifts
464 (define_insn "*thumb2_arith_shiftsi"
465 [(set (match_operand:SI 0 "s_register_operand" "=r")
466 (match_operator:SI 1 "shiftable_operator"
467 [(match_operator:SI 3 "shift_operator"
468 [(match_operand:SI 4 "s_register_operand" "r")
469 (match_operand:SI 5 "const_int_operand" "M")])
470 (match_operand:SI 2 "s_register_operand" "r")]))]
472 "%i1%?\\t%0, %2, %4%S3"
473 [(set_attr "predicable" "yes")
474 (set_attr "shift" "4")
475 (set_attr "type" "alu_shift")]
478 ;; ??? What does this splitter do? Copied from the ARM version
480 [(set (match_operand:SI 0 "s_register_operand" "")
481 (match_operator:SI 1 "shiftable_operator"
482 [(match_operator:SI 2 "shiftable_operator"
483 [(match_operator:SI 3 "shift_operator"
484 [(match_operand:SI 4 "s_register_operand" "")
485 (match_operand:SI 5 "const_int_operand" "")])
486 (match_operand:SI 6 "s_register_operand" "")])
487 (match_operand:SI 7 "arm_rhs_operand" "")]))
488 (clobber (match_operand:SI 8 "s_register_operand" ""))]
491 (match_op_dup 2 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
494 (match_op_dup 1 [(match_dup 8) (match_dup 7)]))]
497 (define_insn "*thumb2_arith_shiftsi_compare0"
498 [(set (reg:CC_NOOV CC_REGNUM)
499 (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
500 [(match_operator:SI 3 "shift_operator"
501 [(match_operand:SI 4 "s_register_operand" "r")
502 (match_operand:SI 5 "const_int_operand" "M")])
503 (match_operand:SI 2 "s_register_operand" "r")])
505 (set (match_operand:SI 0 "s_register_operand" "=r")
506 (match_op_dup 1 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
509 "%i1%.\\t%0, %2, %4%S3"
510 [(set_attr "conds" "set")
511 (set_attr "shift" "4")
512 (set_attr "type" "alu_shift")]
515 (define_insn "*thumb2_arith_shiftsi_compare0_scratch"
516 [(set (reg:CC_NOOV CC_REGNUM)
517 (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
518 [(match_operator:SI 3 "shift_operator"
519 [(match_operand:SI 4 "s_register_operand" "r")
520 (match_operand:SI 5 "const_int_operand" "M")])
521 (match_operand:SI 2 "s_register_operand" "r")])
523 (clobber (match_scratch:SI 0 "=r"))]
525 "%i1%.\\t%0, %2, %4%S3"
526 [(set_attr "conds" "set")
527 (set_attr "shift" "4")
528 (set_attr "type" "alu_shift")]
531 (define_insn "*thumb2_sub_shiftsi"
532 [(set (match_operand:SI 0 "s_register_operand" "=r")
533 (minus:SI (match_operand:SI 1 "s_register_operand" "r")
534 (match_operator:SI 2 "shift_operator"
535 [(match_operand:SI 3 "s_register_operand" "r")
536 (match_operand:SI 4 "const_int_operand" "M")])))]
538 "sub%?\\t%0, %1, %3%S2"
539 [(set_attr "predicable" "yes")
540 (set_attr "shift" "3")
541 (set_attr "type" "alu_shift")]
544 (define_insn "*thumb2_sub_shiftsi_compare0"
545 [(set (reg:CC_NOOV CC_REGNUM)
547 (minus:SI (match_operand:SI 1 "s_register_operand" "r")
548 (match_operator:SI 2 "shift_operator"
549 [(match_operand:SI 3 "s_register_operand" "r")
550 (match_operand:SI 4 "const_int_operand" "M")]))
552 (set (match_operand:SI 0 "s_register_operand" "=r")
553 (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
556 "sub%.\\t%0, %1, %3%S2"
557 [(set_attr "conds" "set")
558 (set_attr "shift" "3")
559 (set_attr "type" "alu_shift")]
562 (define_insn "*thumb2_sub_shiftsi_compare0_scratch"
563 [(set (reg:CC_NOOV CC_REGNUM)
565 (minus:SI (match_operand:SI 1 "s_register_operand" "r")
566 (match_operator:SI 2 "shift_operator"
567 [(match_operand:SI 3 "s_register_operand" "r")
568 (match_operand:SI 4 "const_int_operand" "M")]))
570 (clobber (match_scratch:SI 0 "=r"))]
572 "sub%.\\t%0, %1, %3%S2"
573 [(set_attr "conds" "set")
574 (set_attr "shift" "3")
575 (set_attr "type" "alu_shift")]
578 (define_insn "*thumb2_and_scc"
579 [(set (match_operand:SI 0 "s_register_operand" "=r")
580 (and:SI (match_operator:SI 1 "arm_comparison_operator"
581 [(match_operand 3 "cc_register" "") (const_int 0)])
582 (match_operand:SI 2 "s_register_operand" "r")))]
584 "ite\\t%D1\;mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1"
585 [(set_attr "conds" "use")
586 (set_attr "length" "10")]
589 (define_insn "*thumb2_ior_scc"
590 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
591 (ior:SI (match_operator:SI 2 "arm_comparison_operator"
592 [(match_operand 3 "cc_register" "") (const_int 0)])
593 (match_operand:SI 1 "s_register_operand" "0,?r")))]
596 it\\t%d2\;orr%d2\\t%0, %1, #1
597 ite\\t%D2\;mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1"
598 [(set_attr "conds" "use")
599 (set_attr "length" "6,10")]
602 (define_insn "*thumb2_cond_move"
603 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
604 (if_then_else:SI (match_operator 3 "equality_operator"
605 [(match_operator 4 "arm_comparison_operator"
606 [(match_operand 5 "cc_register" "") (const_int 0)])
608 (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
609 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))]
612 if (GET_CODE (operands[3]) == NE)
614 if (which_alternative != 1)
615 output_asm_insn (\"it\\t%D4\;mov%D4\\t%0, %2\", operands);
616 if (which_alternative != 0)
617 output_asm_insn (\"it\\t%d4\;mov%d4\\t%0, %1\", operands);
620 switch (which_alternative)
623 output_asm_insn (\"it\\t%d4\", operands);
626 output_asm_insn (\"it\\t%D4\", operands);
629 output_asm_insn (\"ite\\t%D4\", operands);
634 if (which_alternative != 0)
635 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
636 if (which_alternative != 1)
637 output_asm_insn (\"mov%d4\\t%0, %2\", operands);
640 [(set_attr "conds" "use")
641 (set_attr "length" "6,6,10")]
644 (define_insn "*thumb2_cond_arith"
645 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
646 (match_operator:SI 5 "shiftable_operator"
647 [(match_operator:SI 4 "arm_comparison_operator"
648 [(match_operand:SI 2 "s_register_operand" "r,r")
649 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
650 (match_operand:SI 1 "s_register_operand" "0,?r")]))
651 (clobber (reg:CC CC_REGNUM))]
654 if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
655 return \"%i5\\t%0, %1, %2, lsr #31\";
657 output_asm_insn (\"cmp\\t%2, %3\", operands);
658 if (GET_CODE (operands[5]) == AND)
660 output_asm_insn (\"ite\\t%D4\", operands);
661 output_asm_insn (\"mov%D4\\t%0, #0\", operands);
663 else if (GET_CODE (operands[5]) == MINUS)
665 output_asm_insn (\"ite\\t%D4\", operands);
666 output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands);
668 else if (which_alternative != 0)
670 output_asm_insn (\"ite\\t%D4\", operands);
671 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
674 output_asm_insn (\"it\\t%d4\", operands);
675 return \"%i5%d4\\t%0, %1, #1\";
677 [(set_attr "conds" "clob")
678 (set_attr "length" "14")]
681 (define_insn "*thumb2_cond_sub"
682 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
683 (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r")
684 (match_operator:SI 4 "arm_comparison_operator"
685 [(match_operand:SI 2 "s_register_operand" "r,r")
686 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
687 (clobber (reg:CC CC_REGNUM))]
690 output_asm_insn (\"cmp\\t%2, %3\", operands);
691 if (which_alternative != 0)
693 output_asm_insn (\"ite\\t%D4\", operands);
694 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
697 output_asm_insn (\"it\\t%d4\", operands);
698 return \"sub%d4\\t%0, %1, #1\";
700 [(set_attr "conds" "clob")
701 (set_attr "length" "10,14")]
704 (define_insn "*thumb2_negscc"
705 [(set (match_operand:SI 0 "s_register_operand" "=r")
706 (neg:SI (match_operator 3 "arm_comparison_operator"
707 [(match_operand:SI 1 "s_register_operand" "r")
708 (match_operand:SI 2 "arm_rhs_operand" "rI")])))
709 (clobber (reg:CC CC_REGNUM))]
712 if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx)
713 return \"asr\\t%0, %1, #31\";
715 if (GET_CODE (operands[3]) == NE)
716 return \"subs\\t%0, %1, %2\;it\\tne\;mvnne\\t%0, #0\";
718 output_asm_insn (\"cmp\\t%1, %2\", operands);
719 output_asm_insn (\"ite\\t%D3\", operands);
720 output_asm_insn (\"mov%D3\\t%0, #0\", operands);
721 return \"mvn%d3\\t%0, #0\";
723 [(set_attr "conds" "clob")
724 (set_attr "length" "14")]
727 (define_insn "*thumb2_movcond"
728 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
730 (match_operator 5 "arm_comparison_operator"
731 [(match_operand:SI 3 "s_register_operand" "r,r,r")
732 (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
733 (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
734 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
735 (clobber (reg:CC CC_REGNUM))]
738 if (GET_CODE (operands[5]) == LT
739 && (operands[4] == const0_rtx))
741 if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
743 if (operands[2] == const0_rtx)
744 return \"and\\t%0, %1, %3, asr #31\";
745 return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\";
747 else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
749 if (operands[1] == const0_rtx)
750 return \"bic\\t%0, %2, %3, asr #31\";
751 return \"bics\\t%0, %2, %3, asr #32\;it\\tcs\;movcs\\t%0, %1\";
753 /* The only case that falls through to here is when both ops 1 & 2
757 if (GET_CODE (operands[5]) == GE
758 && (operands[4] == const0_rtx))
760 if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
762 if (operands[2] == const0_rtx)
763 return \"bic\\t%0, %1, %3, asr #31\";
764 return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\";
766 else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
768 if (operands[1] == const0_rtx)
769 return \"and\\t%0, %2, %3, asr #31\";
770 return \"ands\\t%0, %2, %3, asr #32\;it\tcc\;movcc\\t%0, %1\";
772 /* The only case that falls through to here is when both ops 1 & 2
775 if (GET_CODE (operands[4]) == CONST_INT
776 && !const_ok_for_arm (INTVAL (operands[4])))
777 output_asm_insn (\"cmn\\t%3, #%n4\", operands);
779 output_asm_insn (\"cmp\\t%3, %4\", operands);
780 switch (which_alternative)
783 output_asm_insn (\"it\\t%D5\", operands);
786 output_asm_insn (\"it\\t%d5\", operands);
789 output_asm_insn (\"ite\\t%d5\", operands);
794 if (which_alternative != 0)
795 output_asm_insn (\"mov%d5\\t%0, %1\", operands);
796 if (which_alternative != 1)
797 output_asm_insn (\"mov%D5\\t%0, %2\", operands);
800 [(set_attr "conds" "clob")
801 (set_attr "length" "10,10,14")]
804 ;; Zero and sign extension instructions.
806 (define_insn_and_split "*thumb2_zero_extendsidi2"
807 [(set (match_operand:DI 0 "s_register_operand" "=r")
808 (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
810 "mov%?\\t%Q0, %1\;mov%?\\t%R0, #0"
811 "&& reload_completed"
812 [(set (match_dup 0) (match_dup 1))]
815 rtx lo_part = gen_lowpart (SImode, operands[0]);
816 if (!REG_P (lo_part) || REGNO (lo_part) != REGNO (operands[1]))
817 emit_move_insn (lo_part, operands[1]);
818 operands[0] = gen_highpart (SImode, operands[0]);
819 operands[1] = const0_rtx;
822 [(set_attr "length" "8")
823 (set_attr "ce_count" "2")
824 (set_attr "predicable" "yes")]
827 (define_insn_and_split "*thumb2_zero_extendhidi2"
828 [(set (match_operand:DI 0 "s_register_operand" "=r,r")
829 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
832 uxth%?\\t%Q0, %1\;mov%?\\t%R0, #0
833 ldr%(h%)\\t%Q0, %1\;mov%?\\t%R0, #0"
834 "&& reload_completed"
835 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
836 (set (match_dup 2) (match_dup 3))]
839 operands[2] = gen_highpart (SImode, operands[0]);
840 operands[0] = gen_lowpart (SImode, operands[0]);
841 operands[3] = const0_rtx;
844 [(set_attr "length" "8")
845 (set_attr "ce_count" "2")
846 (set_attr "predicable" "yes")
847 (set_attr "type" "*,load_byte")
848 (set_attr "pool_range" "*,4092")
849 (set_attr "neg_pool_range" "*,250")]
852 (define_insn_and_split "*thumb2_zero_extendqidi2"
853 [(set (match_operand:DI 0 "s_register_operand" "=r,r")
854 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
857 uxtb%?\\t%Q0, %1\;mov%?\\t%R0, #0
858 ldr%(b%)\\t%Q0, %1\;mov%?\\t%R0, #0"
859 "&& reload_completed"
860 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
861 (set (match_dup 2) (match_dup 3))]
864 operands[2] = gen_highpart (SImode, operands[0]);
865 operands[0] = gen_lowpart (SImode, operands[0]);
866 operands[3] = const0_rtx;
869 [(set_attr "length" "8")
870 (set_attr "ce_count" "2")
871 (set_attr "predicable" "yes")
872 (set_attr "type" "*,load_byte")
873 (set_attr "pool_range" "*,4092")
874 (set_attr "neg_pool_range" "*,250")]
877 (define_insn_and_split "*thumb2_extendsidi2"
878 [(set (match_operand:DI 0 "s_register_operand" "=r")
879 (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
881 "mov%?\\t%Q0, %1\;asr?\\t%R0, %1, #31"
882 "&& reload_completed"
883 [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))]
885 rtx lo_part = gen_lowpart (SImode, operands[0]);
887 if (!REG_P (lo_part) || REGNO (lo_part) != REGNO (operands[1]))
888 emit_move_insn (lo_part, operands[1]);
889 operands[0] = gen_highpart (SImode, operands[0]);
891 [(set_attr "length" "8")
892 (set_attr "ce_count" "2")
893 (set_attr "shift" "1")
894 (set_attr "predicable" "yes")]
897 (define_insn_and_split "*thumb2_extendhidi2"
898 [(set (match_operand:DI 0 "s_register_operand" "=r,r")
899 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
902 sxth%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31
903 ldrsh%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31"
904 "&& reload_completed"
905 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
906 (set (match_dup 2) (ashiftrt:SI (match_dup 0) (const_int 31)))]
909 operands[2] = gen_highpart (SImode, operands[0]);
910 operands[0] = gen_lowpart (SImode, operands[0]);
913 [(set_attr "length" "8")
914 (set_attr "ce_count" "2")
915 (set_attr "predicable" "yes")
916 (set_attr "type" "*,load_byte")
917 (set_attr "pool_range" "*,4092")
918 (set_attr "neg_pool_range" "*,250")]
921 (define_insn_and_split "*thumb2_extendqidi2"
922 [(set (match_operand:DI 0 "s_register_operand" "=r,r")
923 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
926 sxtb%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31
927 ldrsb%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31"
928 "&& reload_completed"
929 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
930 (set (match_dup 2) (ashiftrt:SI (match_dup 0) (const_int 31)))]
933 operands[2] = gen_highpart (SImode, operands[0]);
934 operands[0] = gen_lowpart (SImode, operands[0]);
937 [(set_attr "length" "8")
938 (set_attr "ce_count" "2")
939 (set_attr "predicable" "yes")
940 (set_attr "type" "*,load_byte")
941 (set_attr "pool_range" "*,4092")
942 (set_attr "neg_pool_range" "*,250")]
945 ;; All supported Thumb2 implementations are armv6, so only that case is
947 (define_insn "*thumb2_extendqisi_v6"
948 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
949 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
950 "TARGET_THUMB2 && arm_arch6"
954 [(set_attr "type" "alu_shift,load_byte")
955 (set_attr "predicable" "yes")
956 (set_attr "pool_range" "*,4096")
957 (set_attr "neg_pool_range" "*,250")]
960 (define_insn "*thumb2_zero_extendhisi2_v6"
961 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
962 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
963 "TARGET_THUMB2 && arm_arch6"
967 [(set_attr "type" "alu_shift,load_byte")
968 (set_attr "predicable" "yes")
969 (set_attr "pool_range" "*,4096")
970 (set_attr "neg_pool_range" "*,250")]
973 (define_insn "*thumb2_zero_extendqisi2_v6"
974 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
975 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
976 "TARGET_THUMB2 && arm_arch6"
979 ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
980 [(set_attr "type" "alu_shift,load_byte")
981 (set_attr "predicable" "yes")
982 (set_attr "pool_range" "*,4096")
983 (set_attr "neg_pool_range" "*,250")]
986 (define_insn "thumb2_casesi_internal"
987 [(parallel [(set (pc)
989 (leu (match_operand:SI 0 "s_register_operand" "r")
990 (match_operand:SI 1 "arm_rhs_operand" "rI"))
991 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
992 (label_ref (match_operand 2 "" ""))))
993 (label_ref (match_operand 3 "" ""))))
994 (clobber (reg:CC CC_REGNUM))
995 (clobber (match_scratch:SI 4 "=&r"))
996 (use (label_ref (match_dup 2)))])]
997 "TARGET_THUMB2 && !flag_pic"
998 "* return thumb2_output_casesi(operands);"
999 [(set_attr "conds" "clob")
1000 (set_attr "length" "16")]
1003 (define_insn "thumb2_casesi_internal_pic"
1004 [(parallel [(set (pc)
1006 (leu (match_operand:SI 0 "s_register_operand" "r")
1007 (match_operand:SI 1 "arm_rhs_operand" "rI"))
1008 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
1009 (label_ref (match_operand 2 "" ""))))
1010 (label_ref (match_operand 3 "" ""))))
1011 (clobber (reg:CC CC_REGNUM))
1012 (clobber (match_scratch:SI 4 "=&r"))
1013 (clobber (match_scratch:SI 5 "=r"))
1014 (use (label_ref (match_dup 2)))])]
1015 "TARGET_THUMB2 && flag_pic"
1016 "* return thumb2_output_casesi(operands);"
1017 [(set_attr "conds" "clob")
1018 (set_attr "length" "20")]
1021 ;; Note: this is not predicable, to avoid issues with linker-generated
1022 ;; interworking stubs.
1023 (define_insn "*thumb2_return"
1025 "TARGET_THUMB2 && USE_RETURN_INSN (FALSE)"
1028 return output_return_instruction (const_true_rtx, TRUE, FALSE);
1030 [(set_attr "type" "load1")
1031 (set_attr "length" "12")]
1034 (define_insn_and_split "thumb2_eh_return"
1035 [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
1037 (clobber (match_scratch:SI 1 "=&r"))]
1040 "&& reload_completed"
1044 thumb_set_return_address (operands[0], operands[1]);
1049 (define_insn "*thumb2_alusi3_short"
1050 [(set (match_operand:SI 0 "s_register_operand" "=l")
1051 (match_operator:SI 3 "thumb_16bit_operator"
1052 [(match_operand:SI 1 "s_register_operand" "0")
1053 (match_operand:SI 2 "s_register_operand" "l")]))
1054 (clobber (reg:CC CC_REGNUM))]
1055 "TARGET_THUMB2 && reload_completed
1056 && GET_CODE(operands[3]) != PLUS
1057 && GET_CODE(operands[3]) != MINUS"
1058 "%I3%!\\t%0, %1, %2"
1059 [(set_attr "predicable" "yes")
1060 (set_attr "length" "2")]
1063 ;; Similarly for 16-bit shift instructions
1064 ;; There is no 16-bit rotate by immediate instruction.
1066 [(set (match_operand:SI 0 "low_register_operand" "")
1067 (match_operator:SI 3 "shift_operator"
1068 [(match_operand:SI 1 "low_register_operand" "")
1069 (match_operand:SI 2 "low_reg_or_int_operand" "")]))]
1071 && peep2_regno_dead_p(0, CC_REGNUM)
1072 && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
1073 || REG_P(operands[2]))"
1079 (clobber (reg:CC CC_REGNUM))])]
1083 (define_insn "*thumb2_shiftsi3_short"
1084 [(set (match_operand:SI 0 "low_register_operand" "=l")
1085 (match_operator:SI 3 "shift_operator"
1086 [(match_operand:SI 1 "low_register_operand" "l")
1087 (match_operand:SI 2 "low_reg_or_int_operand" "lM")]))
1088 (clobber (reg:CC CC_REGNUM))]
1089 "TARGET_THUMB2 && reload_completed
1090 && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
1091 || REG_P(operands[2]))"
1092 "* return arm_output_shift(operands, 2);"
1093 [(set_attr "predicable" "yes")
1094 (set_attr "shift" "1")
1095 (set_attr "length" "2")
1096 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
1097 (const_string "alu_shift")
1098 (const_string "alu_shift_reg")))]
1101 ;; 16-bit load immediate
1103 [(set (match_operand:QHSI 0 "low_register_operand" "")
1104 (match_operand:QHSI 1 "const_int_operand" ""))]
1106 && peep2_regno_dead_p(0, CC_REGNUM)
1107 && (unsigned HOST_WIDE_INT) INTVAL(operands[1]) < 256"
1111 (clobber (reg:CC CC_REGNUM))])]
1115 (define_insn "*thumb2_mov<mode>_shortim"
1116 [(set (match_operand:QHSI 0 "low_register_operand" "=l")
1117 (match_operand:QHSI 1 "const_int_operand" "I"))
1118 (clobber (reg:CC CC_REGNUM))]
1119 "TARGET_THUMB2 && reload_completed"
1121 [(set_attr "predicable" "yes")
1122 (set_attr "length" "2")]
1125 ;; 16-bit add/sub immediate
1127 [(set (match_operand:SI 0 "low_register_operand" "")
1128 (plus:SI (match_operand:SI 1 "low_register_operand" "")
1129 (match_operand:SI 2 "const_int_operand" "")))]
1131 && peep2_regno_dead_p(0, CC_REGNUM)
1132 && ((rtx_equal_p(operands[0], operands[1])
1133 && INTVAL(operands[2]) > -256 && INTVAL(operands[2]) < 256)
1134 || (INTVAL(operands[2]) > -8 && INTVAL(operands[2]) < 8))"
1137 (plus:SI (match_dup 1)
1139 (clobber (reg:CC CC_REGNUM))])]
1143 (define_insn "*thumb2_addsi_short"
1144 [(set (match_operand:SI 0 "low_register_operand" "=l,l")
1145 (plus:SI (match_operand:SI 1 "low_register_operand" "l,0")
1146 (match_operand:SI 2 "low_reg_or_int_operand" "lPt,Ps")))
1147 (clobber (reg:CC CC_REGNUM))]
1148 "TARGET_THUMB2 && reload_completed"
1152 if (GET_CODE (operands[2]) == CONST_INT)
1153 val = INTVAL(operands[2]);
1157 /* We prefer eg. subs rn, rn, #1 over adds rn, rn, #0xffffffff. */
1158 if (val < 0 && const_ok_for_arm(ARM_SIGN_EXTEND (-val)))
1159 return \"sub%!\\t%0, %1, #%n2\";
1161 return \"add%!\\t%0, %1, %2\";
1163 [(set_attr "predicable" "yes")
1164 (set_attr "length" "2")]
1167 (define_insn "divsi3"
1168 [(set (match_operand:SI 0 "s_register_operand" "=r")
1169 (div:SI (match_operand:SI 1 "s_register_operand" "r")
1170 (match_operand:SI 2 "s_register_operand" "r")))]
1171 "TARGET_THUMB2 && arm_arch_hwdiv"
1172 "sdiv%?\t%0, %1, %2"
1173 [(set_attr "predicable" "yes")
1174 (set_attr "insn" "sdiv")]
1177 (define_insn "udivsi3"
1178 [(set (match_operand:SI 0 "s_register_operand" "=r")
1179 (udiv:SI (match_operand:SI 1 "s_register_operand" "r")
1180 (match_operand:SI 2 "s_register_operand" "r")))]
1181 "TARGET_THUMB2 && arm_arch_hwdiv"
1182 "udiv%?\t%0, %1, %2"
1183 [(set_attr "predicable" "yes")
1184 (set_attr "insn" "udiv")]
1187 (define_insn "*thumb2_subsi_short"
1188 [(set (match_operand:SI 0 "low_register_operand" "=l")
1189 (minus:SI (match_operand:SI 1 "low_register_operand" "l")
1190 (match_operand:SI 2 "low_register_operand" "l")))
1191 (clobber (reg:CC CC_REGNUM))]
1192 "TARGET_THUMB2 && reload_completed"
1193 "sub%!\\t%0, %1, %2"
1194 [(set_attr "predicable" "yes")
1195 (set_attr "length" "2")]
1199 [(set (match_operand:CC 0 "cc_register" "")
1200 (compare:CC (match_operand:SI 1 "low_register_operand" "")
1201 (match_operand:SI 2 "const_int_operand" "")))]
1203 && peep2_reg_dead_p (1, operands[1])
1204 && satisfies_constraint_Pw (operands[2])"
1206 [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
1207 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 3)))])]
1208 "operands[3] = GEN_INT (- INTVAL (operands[2]));"
1212 [(match_scratch:SI 3 "l")
1213 (set (match_operand:CC 0 "cc_register" "")
1214 (compare:CC (match_operand:SI 1 "low_register_operand" "")
1215 (match_operand:SI 2 "const_int_operand" "")))]
1217 && satisfies_constraint_Px (operands[2])"
1219 [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
1220 (set (match_dup 3) (plus:SI (match_dup 1) (match_dup 4)))])]
1221 "operands[4] = GEN_INT (- INTVAL (operands[2]));"
1224 (define_insn "*thumb2_addsi3_compare0"
1225 [(set (reg:CC_NOOV CC_REGNUM)
1227 (plus:SI (match_operand:SI 1 "s_register_operand" "l, 0, r")
1228 (match_operand:SI 2 "arm_add_operand" "lPt,Ps,rIL"))
1230 (set (match_operand:SI 0 "s_register_operand" "=l,l,r")
1231 (plus:SI (match_dup 1) (match_dup 2)))]
1236 if (GET_CODE (operands[2]) == CONST_INT)
1237 val = INTVAL (operands[2]);
1241 if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
1242 return \"subs\\t%0, %1, #%n2\";
1244 return \"adds\\t%0, %1, %2\";
1246 [(set_attr "conds" "set")
1247 (set_attr "length" "2,2,4")]
1250 (define_insn "*thumb2_addsi3_compare0_scratch"
1251 [(set (reg:CC_NOOV CC_REGNUM)
1253 (plus:SI (match_operand:SI 0 "s_register_operand" "l, r")
1254 (match_operand:SI 1 "arm_add_operand" "lPv,rIL"))
1260 if (GET_CODE (operands[1]) == CONST_INT)
1261 val = INTVAL (operands[1]);
1265 if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
1266 return \"cmp\\t%0, #%n1\";
1268 return \"cmn\\t%0, %1\";
1270 [(set_attr "conds" "set")
1271 (set_attr "length" "2,4")]
1274 ;; 16-bit encodings of "muls" and "mul<c>". We only use these when
1275 ;; optimizing for size since "muls" is slow on all known
1276 ;; implementations and since "mul<c>" will be generated by
1277 ;; "*arm_mulsi3_v6" anyhow. The assembler will use a 16-bit encoding
1278 ;; for "mul<c>" whenever possible anyhow.
1280 [(set (match_operand:SI 0 "low_register_operand" "")
1281 (mult:SI (match_operand:SI 1 "low_register_operand" "")
1283 "TARGET_THUMB2 && optimize_size && peep2_regno_dead_p (0, CC_REGNUM)"
1286 (mult:SI (match_dup 0) (match_dup 1)))
1287 (clobber (reg:CC CC_REGNUM))])]
1292 [(set (match_operand:SI 0 "low_register_operand" "")
1293 (mult:SI (match_dup 0)
1294 (match_operand:SI 1 "low_register_operand" "")))]
1295 "TARGET_THUMB2 && optimize_size && peep2_regno_dead_p (0, CC_REGNUM)"
1298 (mult:SI (match_dup 0) (match_dup 1)))
1299 (clobber (reg:CC CC_REGNUM))])]
1303 (define_insn "*thumb2_mulsi_short"
1304 [(set (match_operand:SI 0 "low_register_operand" "=l")
1305 (mult:SI (match_operand:SI 1 "low_register_operand" "%0")
1306 (match_operand:SI 2 "low_register_operand" "l")))
1307 (clobber (reg:CC CC_REGNUM))]
1308 "TARGET_THUMB2 && optimize_size && reload_completed"
1309 "mul%!\\t%0, %2, %0"
1310 [(set_attr "predicable" "yes")
1311 (set_attr "length" "2")
1312 (set_attr "insn" "muls")])
1314 (define_insn "*thumb2_mulsi_short_compare0"
1315 [(set (reg:CC_NOOV CC_REGNUM)
1317 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1318 (match_operand:SI 2 "register_operand" "l"))
1320 (set (match_operand:SI 0 "register_operand" "=l")
1321 (mult:SI (match_dup 1) (match_dup 2)))]
1322 "TARGET_THUMB2 && optimize_size"
1324 [(set_attr "length" "2")
1325 (set_attr "insn" "muls")])
1327 (define_insn "*thumb2_mulsi_short_compare0_scratch"
1328 [(set (reg:CC_NOOV CC_REGNUM)
1330 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1331 (match_operand:SI 2 "register_operand" "l"))
1333 (clobber (match_scratch:SI 0 "=l"))]
1334 "TARGET_THUMB2 && optimize_size"
1336 [(set_attr "length" "2")
1337 (set_attr "insn" "muls")])
1339 (define_insn "*thumb2_cbz"
1340 [(set (pc) (if_then_else
1341 (eq (match_operand:SI 0 "s_register_operand" "l,?r")
1343 (label_ref (match_operand 1 "" ""))
1345 (clobber (reg:CC CC_REGNUM))]
1348 if (get_attr_length (insn) == 2)
1349 return \"cbz\\t%0, %l1\";
1351 return \"cmp\\t%0, #0\;beq\\t%l1\";
1353 [(set (attr "length")
1355 (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1356 (le (minus (match_dup 1) (pc)) (const_int 128))
1357 (eq (symbol_ref ("which_alternative")) (const_int 0)))
1362 (define_insn "*thumb2_cbnz"
1363 [(set (pc) (if_then_else
1364 (ne (match_operand:SI 0 "s_register_operand" "l,?r")
1366 (label_ref (match_operand 1 "" ""))
1368 (clobber (reg:CC CC_REGNUM))]
1371 if (get_attr_length (insn) == 2)
1372 return \"cbnz\\t%0, %l1\";
1374 return \"cmp\\t%0, #0\;bne\\t%l1\";
1376 [(set (attr "length")
1378 (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1379 (le (minus (match_dup 1) (pc)) (const_int 128))
1380 (eq (symbol_ref ("which_alternative")) (const_int 0)))
1385 ;; 16-bit complement
1387 [(set (match_operand:SI 0 "low_register_operand" "")
1388 (not:SI (match_operand:SI 1 "low_register_operand" "")))]
1390 && peep2_regno_dead_p(0, CC_REGNUM)"
1393 (not:SI (match_dup 1)))
1394 (clobber (reg:CC CC_REGNUM))])]
1398 (define_insn "*thumb2_one_cmplsi2_short"
1399 [(set (match_operand:SI 0 "low_register_operand" "=l")
1400 (not:SI (match_operand:SI 1 "low_register_operand" "l")))
1401 (clobber (reg:CC CC_REGNUM))]
1402 "TARGET_THUMB2 && reload_completed"
1404 [(set_attr "predicable" "yes")
1405 (set_attr "length" "2")]
1410 [(set (match_operand:SI 0 "low_register_operand" "")
1411 (neg:SI (match_operand:SI 1 "low_register_operand" "")))]
1413 && peep2_regno_dead_p(0, CC_REGNUM)"
1416 (neg:SI (match_dup 1)))
1417 (clobber (reg:CC CC_REGNUM))])]
1421 (define_insn "*thumb2_negsi2_short"
1422 [(set (match_operand:SI 0 "low_register_operand" "=l")
1423 (neg:SI (match_operand:SI 1 "low_register_operand" "l")))
1424 (clobber (reg:CC CC_REGNUM))]
1425 "TARGET_THUMB2 && reload_completed"
1427 [(set_attr "predicable" "yes")
1428 (set_attr "length" "2")]
1431 (define_insn "orsi_notsi_si"
1432 [(set (match_operand:SI 0 "s_register_operand" "=r")
1433 (ior:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
1434 (match_operand:SI 1 "s_register_operand" "r")))]
1436 "orn%?\\t%0, %1, %2"
1437 [(set_attr "predicable" "yes")]
1440 (define_insn "*thumb_orsi_not_shiftsi_si"
1441 [(set (match_operand:SI 0 "s_register_operand" "=r")
1442 (ior:SI (not:SI (match_operator:SI 4 "shift_operator"
1443 [(match_operand:SI 2 "s_register_operand" "r")
1444 (match_operand:SI 3 "const_int_operand" "M")]))
1445 (match_operand:SI 1 "s_register_operand" "r")))]
1447 "orn%?\\t%0, %1, %2%S4"
1448 [(set_attr "predicable" "yes")
1449 (set_attr "shift" "2")
1450 (set_attr "type" "alu_shift")]
1453 (define_insn_and_split "*thumb2_iorsi3"
1454 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
1455 (ior:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
1456 (match_operand:SI 2 "reg_or_int_operand" "rI,K,?n")))]
1460 orn%?\\t%0, %1, #%B2
1463 && GET_CODE (operands[2]) == CONST_INT
1464 && !(const_ok_for_arm (INTVAL (operands[2]))
1465 || const_ok_for_arm (~INTVAL (operands[2])))"
1466 [(clobber (const_int 0))]
1468 arm_split_constant (IOR, SImode, curr_insn,
1469 INTVAL (operands[2]), operands[0], operands[1], 0);
1472 [(set_attr "length" "4,4,16")
1473 (set_attr "predicable" "yes")]
1477 [(set (match_operand:CC_NOOV 0 "cc_register" "")
1478 (compare:CC_NOOV (zero_extract:SI
1479 (match_operand:SI 1 "low_register_operand" "")
1481 (match_operand:SI 2 "const_int_operand" ""))
1483 (match_scratch:SI 3 "l")
1485 (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
1486 [(match_dup 0) (const_int 0)])
1487 (match_operand 5 "" "")
1488 (match_operand 6 "" "")))]
1490 && (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32)"
1491 [(parallel [(set (match_dup 0)
1492 (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
1494 (clobber (match_dup 3))])
1496 (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1497 (match_dup 5) (match_dup 6)))]
1499 operands[2] = GEN_INT (31 - INTVAL (operands[2]));
1500 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? LT : GE,
1501 VOIDmode, operands[0], const0_rtx);