gcc/config/arm/thumb2.md

   1 ;; ARM Thumb-2 Machine Description
   2 ;; Copyright (C) 2007, 2008 Free Software Foundation, Inc.
   3 ;; Written by CodeSourcery, LLC.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.  */
  20
  21 ;; Note: Thumb-2 is the variant of the Thumb architecture that adds
  22 ;; 32-bit encodings of [almost all of] the Arm instruction set.
  23 ;; Some old documents refer to the relatively minor interworking
  24 ;; changes made in armv5t as "thumb2".  These are considered part
  25 ;; the 16-bit Thumb-1 instruction set.
  26
  27 (define_insn "*thumb2_incscc"
  28   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
  29         (plus:SI (match_operator:SI 2 "arm_comparison_operator"
  30                     [(match_operand:CC 3 "cc_register" "") (const_int 0)])
  31                  (match_operand:SI 1 "s_register_operand" "0,?r")))]
  32   "TARGET_THUMB2"
  33   "@
  34   it\\t%d2\;add%d2\\t%0, %1, #1
  35   ite\\t%D2\;mov%D2\\t%0, %1\;add%d2\\t%0, %1, #1"
  36   [(set_attr "conds" "use")
  37    (set_attr "length" "6,10")]
  38 )
  39
  40 (define_insn "*thumb2_decscc"
  41   [(set (match_operand:SI            0 "s_register_operand" "=r,r")
  42         (minus:SI (match_operand:SI  1 "s_register_operand" "0,?r")
  43                   (match_operator:SI 2 "arm_comparison_operator"
  44                    [(match_operand   3 "cc_register" "") (const_int 0)])))]
  45   "TARGET_THUMB2"
  46   "@
  47    it\\t%d2\;sub%d2\\t%0, %1, #1
  48    ite\\t%D2\;mov%D2\\t%0, %1\;sub%d2\\t%0, %1, #1"
  49   [(set_attr "conds" "use")
  50    (set_attr "length" "6,10")]
  51 )
  52
  53 ;; Thumb-2 only allows shift by constant on data processing instructions
  54 (define_insn "*thumb_andsi_not_shiftsi_si"
  55   [(set (match_operand:SI 0 "s_register_operand" "=r")
  56         (and:SI (not:SI (match_operator:SI 4 "shift_operator"
  57                          [(match_operand:SI 2 "s_register_operand" "r")
  58                           (match_operand:SI 3 "const_int_operand" "M")]))
  59                 (match_operand:SI 1 "s_register_operand" "r")))]
  60   "TARGET_THUMB2"
  61   "bic%?\\t%0, %1, %2%S4"
  62   [(set_attr "predicable" "yes")
  63    (set_attr "shift" "2")
  64    (set_attr "type" "alu_shift")]
  65 )
  66
  67 (define_insn "*thumb2_smaxsi3"
  68   [(set (match_operand:SI          0 "s_register_operand" "=r,r,r")
  69         (smax:SI (match_operand:SI 1 "s_register_operand"  "0,r,?r")
  70                  (match_operand:SI 2 "arm_rhs_operand"    "rI,0,rI")))
  71    (clobber (reg:CC CC_REGNUM))]
  72   "TARGET_THUMB2"
  73   "@
  74    cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2
  75    cmp\\t%1, %2\;it\\tge\;movge\\t%0, %1
  76    cmp\\t%1, %2\;ite\\tge\;movge\\t%0, %1\;movlt\\t%0, %2"
  77   [(set_attr "conds" "clob")
  78    (set_attr "length" "10,10,14")]
  79 )
  80
  81 (define_insn "*thumb2_sminsi3"
  82   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
  83         (smin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
  84                  (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
  85    (clobber (reg:CC CC_REGNUM))]
  86   "TARGET_THUMB2"
  87   "@
  88    cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2
  89    cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %1
  90    cmp\\t%1, %2\;ite\\tlt\;movlt\\t%0, %1\;movge\\t%0, %2"
  91   [(set_attr "conds" "clob")
  92    (set_attr "length" "10,10,14")]
  93 )
  94
  95 (define_insn "*thumb32_umaxsi3"
  96   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
  97         (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
  98                  (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
  99    (clobber (reg:CC CC_REGNUM))]
 100   "TARGET_THUMB2"
 101   "@
 102    cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2
 103    cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %1
 104    cmp\\t%1, %2\;ite\\tcs\;movcs\\t%0, %1\;movcc\\t%0, %2"
 105   [(set_attr "conds" "clob")
 106    (set_attr "length" "10,10,14")]
 107 )
 108
 109 (define_insn "*thumb2_uminsi3"
 110   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
 111         (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
 112                  (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
 113    (clobber (reg:CC CC_REGNUM))]
 114   "TARGET_THUMB2"
 115   "@
 116    cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2
 117    cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %1
 118    cmp\\t%1, %2\;ite\\tcc\;movcc\\t%0, %1\;movcs\\t%0, %2"
 119   [(set_attr "conds" "clob")
 120    (set_attr "length" "10,10,14")]
 121 )
 122
 123 (define_insn "*thumb2_notsi_shiftsi"
 124   [(set (match_operand:SI 0 "s_register_operand" "=r")
 125         (not:SI (match_operator:SI 3 "shift_operator"
 126                  [(match_operand:SI 1 "s_register_operand" "r")
 127                   (match_operand:SI 2 "const_int_operand"  "M")])))]
 128   "TARGET_THUMB2"
 129   "mvn%?\\t%0, %1%S3"
 130   [(set_attr "predicable" "yes")
 131    (set_attr "shift" "1")
 132    (set_attr "type" "alu_shift")]
 133 )
 134
 135 (define_insn "*thumb2_notsi_shiftsi_compare0"
 136   [(set (reg:CC_NOOV CC_REGNUM)
 137         (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
 138                           [(match_operand:SI 1 "s_register_operand" "r")
 139                            (match_operand:SI 2 "const_int_operand"  "M")]))
 140                          (const_int 0)))
 141    (set (match_operand:SI 0 "s_register_operand" "=r")
 142         (not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))]
 143   "TARGET_THUMB2"
 144   "mvn%.\\t%0, %1%S3"
 145   [(set_attr "conds" "set")
 146    (set_attr "shift" "1")
 147    (set_attr "type" "alu_shift")]
 148 )
 149
 150 (define_insn "*thumb2_not_shiftsi_compare0_scratch"
 151   [(set (reg:CC_NOOV CC_REGNUM)
 152         (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
 153                           [(match_operand:SI 1 "s_register_operand" "r")
 154                            (match_operand:SI 2 "const_int_operand"  "M")]))
 155                          (const_int 0)))
 156    (clobber (match_scratch:SI 0 "=r"))]
 157   "TARGET_THUMB2"
 158   "mvn%.\\t%0, %1%S3"
 159   [(set_attr "conds" "set")
 160    (set_attr "shift" "1")
 161    (set_attr "type" "alu_shift")]
 162 )
 163
 164 ;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
 165 (define_insn "*thumb2_negdi2"
 166   [(set (match_operand:DI         0 "s_register_operand" "=&r,r")
 167         (neg:DI (match_operand:DI 1 "s_register_operand"  "?r,0")))
 168    (clobber (reg:CC CC_REGNUM))]
 169   "TARGET_THUMB2"
 170   "negs\\t%Q0, %Q1\;sbc\\t%R0, %R1, %R1, lsl #1"
 171   [(set_attr "conds" "clob")
 172    (set_attr "length" "8")]
 173 )
 174
 175 (define_insn "*thumb2_abssi2"
 176   [(set (match_operand:SI         0 "s_register_operand" "=r,&r")
 177         (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
 178    (clobber (reg:CC CC_REGNUM))]
 179   "TARGET_THUMB2"
 180   "@
 181    cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
 182    eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31"
 183   [(set_attr "conds" "clob,*")
 184    (set_attr "shift" "1")
 185    ;; predicable can't be set based on the variant, so left as no
 186    (set_attr "length" "10,8")]
 187 )
 188
 189 (define_insn "*thumb2_neg_abssi2"
 190   [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
 191         (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
 192    (clobber (reg:CC CC_REGNUM))]
 193   "TARGET_THUMB2"
 194   "@
 195    cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
 196    eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31"
 197   [(set_attr "conds" "clob,*")
 198    (set_attr "shift" "1")
 199    ;; predicable can't be set based on the variant, so left as no
 200    (set_attr "length" "10,8")]
 201 )
 202
 203 (define_insn "*thumb2_movdi"
 204   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m")
 205         (match_operand:DI 1 "di_operand"              "rDa,Db,Dc,mi,r"))]
 206   "TARGET_THUMB2
 207   && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP))
 208   && !TARGET_IWMMXT"
 209   "*
 210   switch (which_alternative)
 211     {
 212     case 0:
 213     case 1:
 214     case 2:
 215       return \"#\";
 216     default:
 217       return output_move_double (operands);
 218     }
 219   "
 220   [(set_attr "length" "8,12,16,8,8")
 221    (set_attr "type" "*,*,*,load2,store2")
 222    (set_attr "pool_range" "*,*,*,4096,*")
 223    (set_attr "neg_pool_range" "*,*,*,0,*")]
 224 )
 225
 226 (define_insn "*thumb2_movsi_insn"
 227   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m")
 228         (match_operand:SI 1 "general_operand"      "rk ,I,K,j,mi,rk"))]
 229   "TARGET_THUMB2 && ! TARGET_IWMMXT
 230    && !(TARGET_HARD_FLOAT && TARGET_VFP)
 231    && (   register_operand (operands[0], SImode)
 232        || register_operand (operands[1], SImode))"
 233   "@
 234    mov%?\\t%0, %1
 235    mov%?\\t%0, %1
 236    mvn%?\\t%0, #%B1
 237    movw%?\\t%0, %1
 238    ldr%?\\t%0, %1
 239    str%?\\t%1, %0"
 240   [(set_attr "type" "*,*,*,*,load1,store1")
 241    (set_attr "predicable" "yes")
 242    (set_attr "pool_range" "*,*,*,*,4096,*")
 243    (set_attr "neg_pool_range" "*,*,*,*,0,*")]
 244 )
 245
 246 (define_insn "tls_load_dot_plus_four"
 247   [(set (match_operand:SI 0 "register_operand" "=l,r")
 248         (mem:SI (unspec:SI [(match_operand:SI 1 "register_operand" "+l,r")
 249                             (const_int 4)
 250                             (match_operand 2 "" "")]
 251                            UNSPEC_PIC_BASE)))]
 252   "TARGET_THUMB2"
 253   "*
 254   (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
 255                              INTVAL (operands[2]));
 256   return \"add\\t%1, %|pc\;ldr%?\\t%0, [%1]\";
 257   "
 258   [(set_attr "length" "4,6")]
 259 )
 260
 261 ;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
 262 ;; of the messiness associated with the ARM patterns.
 263 (define_insn "*thumb2_movhi_insn"
 264   [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
 265         (match_operand:HI 1 "general_operand"      "rI,n,r,m"))]
 266   "TARGET_THUMB2"
 267   "@
 268    mov%?\\t%0, %1\\t%@ movhi
 269    movw%?\\t%0, %L1\\t%@ movhi
 270    str%(h%)\\t%1, %0\\t%@ movhi
 271    ldr%(h%)\\t%0, %1\\t%@ movhi"
 272   [(set_attr "type" "*,*,store1,load1")
 273    (set_attr "predicable" "yes")
 274    (set_attr "pool_range" "*,*,*,4096")
 275    (set_attr "neg_pool_range" "*,*,*,250")]
 276 )
 277
 278 (define_insn "*thumb2_movsf_soft_insn"
 279   [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
 280         (match_operand:SF 1 "general_operand"  "r,mE,r"))]
 281   "TARGET_THUMB2
 282    && TARGET_SOFT_FLOAT
 283    && (GET_CODE (operands[0]) != MEM
 284        || register_operand (operands[1], SFmode))"
 285   "@
 286    mov%?\\t%0, %1
 287    ldr%?\\t%0, %1\\t%@ float
 288    str%?\\t%1, %0\\t%@ float"
 289   [(set_attr "predicable" "yes")
 290    (set_attr "type" "*,load1,store1")
 291    (set_attr "pool_range" "*,4096,*")
 292    (set_attr "neg_pool_range" "*,0,*")]
 293 )
 294
 295 (define_insn "*thumb2_movdf_soft_insn"
 296   [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,r,r,m")
 297         (match_operand:DF 1 "soft_df_operand" "rDa,Db,Dc,mF,r"))]
 298   "TARGET_THUMB2 && TARGET_SOFT_FLOAT
 299    && (   register_operand (operands[0], DFmode)
 300        || register_operand (operands[1], DFmode))"
 301   "*
 302   switch (which_alternative)
 303     {
 304     case 0:
 305     case 1:
 306     case 2:
 307       return \"#\";
 308     default:
 309       return output_move_double (operands);
 310     }
 311   "
 312   [(set_attr "length" "8,12,16,8,8")
 313    (set_attr "type" "*,*,*,load2,store2")
 314    (set_attr "pool_range" "1020")
 315    (set_attr "neg_pool_range" "0")]
 316 )
 317
 318 (define_insn "*thumb2_cmpsi_shiftsi"
 319   [(set (reg:CC CC_REGNUM)
 320         (compare:CC (match_operand:SI   0 "s_register_operand" "r")
 321                     (match_operator:SI  3 "shift_operator"
 322                      [(match_operand:SI 1 "s_register_operand" "r")
 323                       (match_operand:SI 2 "const_int_operand"  "M")])))]
 324   "TARGET_THUMB2"
 325   "cmp%?\\t%0, %1%S3"
 326   [(set_attr "conds" "set")
 327    (set_attr "shift" "1")
 328    (set_attr "type" "alu_shift")]
 329 )
 330
 331 (define_insn "*thumb2_cmpsi_shiftsi_swp"
 332   [(set (reg:CC_SWP CC_REGNUM)
 333         (compare:CC_SWP (match_operator:SI 3 "shift_operator"
 334                          [(match_operand:SI 1 "s_register_operand" "r")
 335                           (match_operand:SI 2 "const_int_operand" "M")])
 336                         (match_operand:SI 0 "s_register_operand" "r")))]
 337   "TARGET_THUMB2"
 338   "cmp%?\\t%0, %1%S3"
 339   [(set_attr "conds" "set")
 340    (set_attr "shift" "1")
 341    (set_attr "type" "alu_shift")]
 342 )
 343
 344 (define_insn "*thumb2_cmpsi_neg_shiftsi"
 345   [(set (reg:CC CC_REGNUM)
 346         (compare:CC (match_operand:SI 0 "s_register_operand" "r")
 347                     (neg:SI (match_operator:SI 3 "shift_operator"
 348                              [(match_operand:SI 1 "s_register_operand" "r")
 349                               (match_operand:SI 2 "const_int_operand" "M")]))))]
 350   "TARGET_THUMB2"
 351   "cmn%?\\t%0, %1%S3"
 352   [(set_attr "conds" "set")
 353    (set_attr "shift" "1")
 354    (set_attr "type" "alu_shift")]
 355 )
 356
 357 (define_insn "*thumb2_mov_scc"
 358   [(set (match_operand:SI 0 "s_register_operand" "=r")
 359         (match_operator:SI 1 "arm_comparison_operator"
 360          [(match_operand 2 "cc_register" "") (const_int 0)]))]
 361   "TARGET_THUMB2"
 362   "ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
 363   [(set_attr "conds" "use")
 364    (set_attr "length" "10")]
 365 )
 366
 367 (define_insn "*thumb2_mov_negscc"
 368   [(set (match_operand:SI 0 "s_register_operand" "=r")
 369         (neg:SI (match_operator:SI 1 "arm_comparison_operator"
 370                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 371   "TARGET_THUMB2"
 372   "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
 373   [(set_attr "conds" "use")
 374    (set_attr "length" "10")]
 375 )
 376
 377 (define_insn "*thumb2_mov_notscc"
 378   [(set (match_operand:SI 0 "s_register_operand" "=r")
 379         (not:SI (match_operator:SI 1 "arm_comparison_operator"
 380                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 381   "TARGET_THUMB2"
 382   "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #1"
 383   [(set_attr "conds" "use")
 384    (set_attr "length" "10")]
 385 )
 386
 387 (define_insn "*thumb2_movsicc_insn"
 388   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r")
 389         (if_then_else:SI
 390          (match_operator 3 "arm_comparison_operator"
 391           [(match_operand 4 "cc_register" "") (const_int 0)])
 392          (match_operand:SI 1 "arm_not_operand" "0,0,rI,K,rI,rI,K,K")
 393          (match_operand:SI 2 "arm_not_operand" "rI,K,0,0,rI,K,rI,K")))]
 394   "TARGET_THUMB2"
 395   "@
 396    it\\t%D3\;mov%D3\\t%0, %2
 397    it\\t%D3\;mvn%D3\\t%0, #%B2
 398    it\\t%d3\;mov%d3\\t%0, %1
 399    it\\t%d3\;mvn%d3\\t%0, #%B1
 400    ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
 401    ite\\t%d3\;mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2
 402    ite\\t%d3\;mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2
 403    ite\\t%d3\;mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2"
 404   [(set_attr "length" "6,6,6,6,10,10,10,10")
 405    (set_attr "conds" "use")]
 406 )
 407
 408 (define_insn "*thumb2_movsfcc_soft_insn"
 409   [(set (match_operand:SF 0 "s_register_operand" "=r,r")
 410         (if_then_else:SF (match_operator 3 "arm_comparison_operator"
 411                           [(match_operand 4 "cc_register" "") (const_int 0)])
 412                          (match_operand:SF 1 "s_register_operand" "0,r")
 413                          (match_operand:SF 2 "s_register_operand" "r,0")))]
 414   "TARGET_THUMB2 && TARGET_SOFT_FLOAT"
 415   "@
 416    it\\t%D3\;mov%D3\\t%0, %2
 417    it\\t%d3\;mov%d3\\t%0, %1"
 418   [(set_attr "length" "6,6")
 419    (set_attr "conds" "use")]
 420 )
 421
 422 (define_insn "*call_reg_thumb2"
 423   [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
 424          (match_operand 1 "" ""))
 425    (use (match_operand 2 "" ""))
 426    (clobber (reg:SI LR_REGNUM))]
 427   "TARGET_THUMB2"
 428   "blx%?\\t%0"
 429   [(set_attr "type" "call")]
 430 )
 431
 432 (define_insn "*call_value_reg_thumb2"
 433   [(set (match_operand 0 "" "")
 434         (call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
 435               (match_operand 2 "" "")))
 436    (use (match_operand 3 "" ""))
 437    (clobber (reg:SI LR_REGNUM))]
 438   "TARGET_THUMB2"
 439   "blx\\t%1"
 440   [(set_attr "type" "call")]
 441 )
 442
 443 (define_insn "*thumb2_indirect_jump"
 444   [(set (pc)
 445         (match_operand:SI 0 "register_operand" "l*r"))]
 446   "TARGET_THUMB2"
 447   "bx\\t%0"
 448   [(set_attr "conds" "clob")]
 449 )
 450 ;; Don't define thumb2_load_indirect_jump because we can't guarantee label
 451 ;; addresses will have the thumb bit set correctly.
 452
 453
 454 ;; Patterns to allow combination of arithmetic, cond code and shifts
 455
 456 (define_insn "*thumb2_arith_shiftsi"
 457   [(set (match_operand:SI 0 "s_register_operand" "=r")
 458         (match_operator:SI 1 "shiftable_operator"
 459           [(match_operator:SI 3 "shift_operator"
 460              [(match_operand:SI 4 "s_register_operand" "r")
 461               (match_operand:SI 5 "const_int_operand" "M")])
 462            (match_operand:SI 2 "s_register_operand" "r")]))]
 463   "TARGET_THUMB2"
 464   "%i1%?\\t%0, %2, %4%S3"
 465   [(set_attr "predicable" "yes")
 466    (set_attr "shift" "4")
 467    (set_attr "type" "alu_shift")]
 468 )
 469
 470 ;; ??? What does this splitter do?  Copied from the ARM version
 471 (define_split
 472   [(set (match_operand:SI 0 "s_register_operand" "")
 473         (match_operator:SI 1 "shiftable_operator"
 474          [(match_operator:SI 2 "shiftable_operator"
 475            [(match_operator:SI 3 "shift_operator"
 476              [(match_operand:SI 4 "s_register_operand" "")
 477               (match_operand:SI 5 "const_int_operand" "")])
 478             (match_operand:SI 6 "s_register_operand" "")])
 479           (match_operand:SI 7 "arm_rhs_operand" "")]))
 480    (clobber (match_operand:SI 8 "s_register_operand" ""))]
 481   "TARGET_32BIT"
 482   [(set (match_dup 8)
 483         (match_op_dup 2 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
 484                          (match_dup 6)]))
 485    (set (match_dup 0)
 486         (match_op_dup 1 [(match_dup 8) (match_dup 7)]))]
 487   "")
 488
 489 (define_insn "*thumb2_arith_shiftsi_compare0"
 490   [(set (reg:CC_NOOV CC_REGNUM)
 491         (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
 492                           [(match_operator:SI 3 "shift_operator"
 493                             [(match_operand:SI 4 "s_register_operand" "r")
 494                              (match_operand:SI 5 "const_int_operand" "M")])
 495                            (match_operand:SI 2 "s_register_operand" "r")])
 496                          (const_int 0)))
 497    (set (match_operand:SI 0 "s_register_operand" "=r")
 498         (match_op_dup 1 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
 499                          (match_dup 2)]))]
 500   "TARGET_32BIT"
 501   "%i1%.\\t%0, %2, %4%S3"
 502   [(set_attr "conds" "set")
 503    (set_attr "shift" "4")
 504    (set_attr "type" "alu_shift")]
 505 )
 506
 507 (define_insn "*thumb2_arith_shiftsi_compare0_scratch"
 508   [(set (reg:CC_NOOV CC_REGNUM)
 509         (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
 510                           [(match_operator:SI 3 "shift_operator"
 511                             [(match_operand:SI 4 "s_register_operand" "r")
 512                              (match_operand:SI 5 "const_int_operand" "M")])
 513                            (match_operand:SI 2 "s_register_operand" "r")])
 514                          (const_int 0)))
 515    (clobber (match_scratch:SI 0 "=r"))]
 516   "TARGET_THUMB2"
 517   "%i1%.\\t%0, %2, %4%S3"
 518   [(set_attr "conds" "set")
 519    (set_attr "shift" "4")
 520    (set_attr "type" "alu_shift")]
 521 )
 522
 523 (define_insn "*thumb2_sub_shiftsi"
 524   [(set (match_operand:SI 0 "s_register_operand" "=r")
 525         (minus:SI (match_operand:SI 1 "s_register_operand" "r")
 526                   (match_operator:SI 2 "shift_operator"
 527                    [(match_operand:SI 3 "s_register_operand" "r")
 528                     (match_operand:SI 4 "const_int_operand" "M")])))]
 529   "TARGET_THUMB2"
 530   "sub%?\\t%0, %1, %3%S2"
 531   [(set_attr "predicable" "yes")
 532    (set_attr "shift" "3")
 533    (set_attr "type" "alu_shift")]
 534 )
 535
 536 (define_insn "*thumb2_sub_shiftsi_compare0"
 537   [(set (reg:CC_NOOV CC_REGNUM)
 538         (compare:CC_NOOV
 539          (minus:SI (match_operand:SI 1 "s_register_operand" "r")
 540                    (match_operator:SI 2 "shift_operator"
 541                     [(match_operand:SI 3 "s_register_operand" "r")
 542                      (match_operand:SI 4 "const_int_operand" "M")]))
 543          (const_int 0)))
 544    (set (match_operand:SI 0 "s_register_operand" "=r")
 545         (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
 546                                                  (match_dup 4)])))]
 547   "TARGET_THUMB2"
 548   "sub%.\\t%0, %1, %3%S2"
 549   [(set_attr "conds" "set")
 550    (set_attr "shift" "3")
 551    (set_attr "type" "alu_shift")]
 552 )
 553
 554 (define_insn "*thumb2_sub_shiftsi_compare0_scratch"
 555   [(set (reg:CC_NOOV CC_REGNUM)
 556         (compare:CC_NOOV
 557          (minus:SI (match_operand:SI 1 "s_register_operand" "r")
 558                    (match_operator:SI 2 "shift_operator"
 559                     [(match_operand:SI 3 "s_register_operand" "r")
 560                      (match_operand:SI 4 "const_int_operand" "M")]))
 561          (const_int 0)))
 562    (clobber (match_scratch:SI 0 "=r"))]
 563   "TARGET_THUMB2"
 564   "sub%.\\t%0, %1, %3%S2"
 565   [(set_attr "conds" "set")
 566    (set_attr "shift" "3")
 567    (set_attr "type" "alu_shift")]
 568 )
 569
 570 (define_insn "*thumb2_and_scc"
 571   [(set (match_operand:SI 0 "s_register_operand" "=r")
 572         (and:SI (match_operator:SI 1 "arm_comparison_operator"
 573                  [(match_operand 3 "cc_register" "") (const_int 0)])
 574                 (match_operand:SI 2 "s_register_operand" "r")))]
 575   "TARGET_THUMB2"
 576   "ite\\t%D1\;mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1"
 577   [(set_attr "conds" "use")
 578    (set_attr "length" "10")]
 579 )
 580
 581 (define_insn "*thumb2_ior_scc"
 582   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 583         (ior:SI (match_operator:SI 2 "arm_comparison_operator"
 584                  [(match_operand 3 "cc_register" "") (const_int 0)])
 585                 (match_operand:SI 1 "s_register_operand" "0,?r")))]
 586   "TARGET_THUMB2"
 587   "@
 588    it\\t%d2\;orr%d2\\t%0, %1, #1
 589    ite\\t%D2\;mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1"
 590   [(set_attr "conds" "use")
 591    (set_attr "length" "6,10")]
 592 )
 593
 594 (define_insn "*thumb2_compare_scc"
 595   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 596         (match_operator:SI 1 "arm_comparison_operator"
 597          [(match_operand:SI 2 "s_register_operand" "r,r")
 598           (match_operand:SI 3 "arm_add_operand" "rI,L")]))
 599    (clobber (reg:CC CC_REGNUM))]
 600   "TARGET_THUMB2"
 601   "*
 602     if (operands[3] == const0_rtx)
 603       {
 604         if (GET_CODE (operands[1]) == LT)
 605           return \"lsr\\t%0, %2, #31\";
 606
 607         if (GET_CODE (operands[1]) == GE)
 608           return \"mvn\\t%0, %2\;lsr\\t%0, %0, #31\";
 609
 610         if (GET_CODE (operands[1]) == EQ)
 611           return \"rsbs\\t%0, %2, #1\;it\\tcc\;movcc\\t%0, #0\";
 612       }
 613
 614     if (GET_CODE (operands[1]) == NE)
 615       {
 616         if (which_alternative == 1)
 617           return \"adds\\t%0, %2, #%n3\;it\\tne\;movne\\t%0, #1\";
 618         return \"subs\\t%0, %2, %3\;it\\tne\;movne\\t%0, #1\";
 619       }
 620     if (which_alternative == 1)
 621       output_asm_insn (\"cmn\\t%2, #%n3\", operands);
 622     else
 623       output_asm_insn (\"cmp\\t%2, %3\", operands);
 624     return \"ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1\";
 625   "
 626   [(set_attr "conds" "clob")
 627    (set_attr "length" "14")]
 628 )
 629
 630 (define_insn "*thumb2_cond_move"
 631   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
 632         (if_then_else:SI (match_operator 3 "equality_operator"
 633                           [(match_operator 4 "arm_comparison_operator"
 634                             [(match_operand 5 "cc_register" "") (const_int 0)])
 635                            (const_int 0)])
 636                          (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
 637                          (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))]
 638   "TARGET_THUMB2"
 639   "*
 640     if (GET_CODE (operands[3]) == NE)
 641       {
 642         if (which_alternative != 1)
 643           output_asm_insn (\"it\\t%D4\;mov%D4\\t%0, %2\", operands);
 644         if (which_alternative != 0)
 645           output_asm_insn (\"it\\t%d4\;mov%d4\\t%0, %1\", operands);
 646         return \"\";
 647       }
 648     switch (which_alternative)
 649       {
 650       case 0:
 651         output_asm_insn (\"it\\t%d4\", operands);
 652         break;
 653       case 1:
 654         output_asm_insn (\"it\\t%D4\", operands);
 655         break;
 656       case 2:
 657         output_asm_insn (\"ite\\t%D4\", operands);
 658         break;
 659       default:
 660         abort();
 661       }
 662     if (which_alternative != 0)
 663       output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 664     if (which_alternative != 1)
 665       output_asm_insn (\"mov%d4\\t%0, %2\", operands);
 666     return \"\";
 667   "
 668   [(set_attr "conds" "use")
 669    (set_attr "length" "6,6,10")]
 670 )
 671
 672 (define_insn "*thumb2_cond_arith"
 673   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 674         (match_operator:SI 5 "shiftable_operator"
 675          [(match_operator:SI 4 "arm_comparison_operator"
 676            [(match_operand:SI 2 "s_register_operand" "r,r")
 677             (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
 678           (match_operand:SI 1 "s_register_operand" "0,?r")]))
 679    (clobber (reg:CC CC_REGNUM))]
 680   "TARGET_THUMB2"
 681   "*
 682     if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
 683       return \"%i5\\t%0, %1, %2, lsr #31\";
 684
 685     output_asm_insn (\"cmp\\t%2, %3\", operands);
 686     if (GET_CODE (operands[5]) == AND)
 687       {
 688         output_asm_insn (\"ite\\t%D4\", operands);
 689         output_asm_insn (\"mov%D4\\t%0, #0\", operands);
 690       }
 691     else if (GET_CODE (operands[5]) == MINUS)
 692       {
 693         output_asm_insn (\"ite\\t%D4\", operands);
 694         output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands);
 695       }
 696     else if (which_alternative != 0)
 697       {
 698         output_asm_insn (\"ite\\t%D4\", operands);
 699         output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 700       }
 701     else
 702       output_asm_insn (\"it\\t%d4\", operands);
 703     return \"%i5%d4\\t%0, %1, #1\";
 704   "
 705   [(set_attr "conds" "clob")
 706    (set_attr "length" "14")]
 707 )
 708
 709 (define_insn "*thumb2_cond_sub"
 710   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 711         (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r")
 712                   (match_operator:SI 4 "arm_comparison_operator"
 713                    [(match_operand:SI 2 "s_register_operand" "r,r")
 714                     (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
 715    (clobber (reg:CC CC_REGNUM))]
 716   "TARGET_THUMB2"
 717   "*
 718     output_asm_insn (\"cmp\\t%2, %3\", operands);
 719     if (which_alternative != 0)
 720       {
 721         output_asm_insn (\"ite\\t%D4\", operands);
 722         output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 723       }
 724     else
 725       output_asm_insn (\"it\\t%d4\", operands);
 726     return \"sub%d4\\t%0, %1, #1\";
 727   "
 728   [(set_attr "conds" "clob")
 729    (set_attr "length" "10,14")]
 730 )
 731
 732 (define_insn "*thumb2_negscc"
 733   [(set (match_operand:SI 0 "s_register_operand" "=r")
 734         (neg:SI (match_operator 3 "arm_comparison_operator"
 735                  [(match_operand:SI 1 "s_register_operand" "r")
 736                   (match_operand:SI 2 "arm_rhs_operand" "rI")])))
 737    (clobber (reg:CC CC_REGNUM))]
 738   "TARGET_THUMB2"
 739   "*
 740   if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx)
 741     return \"asr\\t%0, %1, #31\";
 742
 743   if (GET_CODE (operands[3]) == NE)
 744     return \"subs\\t%0, %1, %2\;it\\tne\;mvnne\\t%0, #0\";
 745
 746   output_asm_insn (\"cmp\\t%1, %2\", operands);
 747   output_asm_insn (\"ite\\t%D3\", operands);
 748   output_asm_insn (\"mov%D3\\t%0, #0\", operands);
 749   return \"mvn%d3\\t%0, #0\";
 750   "
 751   [(set_attr "conds" "clob")
 752    (set_attr "length" "14")]
 753 )
 754
 755 (define_insn "*thumb2_movcond"
 756   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
 757         (if_then_else:SI
 758          (match_operator 5 "arm_comparison_operator"
 759           [(match_operand:SI 3 "s_register_operand" "r,r,r")
 760            (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
 761          (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
 762          (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
 763    (clobber (reg:CC CC_REGNUM))]
 764   "TARGET_THUMB2"
 765   "*
 766   if (GET_CODE (operands[5]) == LT
 767       && (operands[4] == const0_rtx))
 768     {
 769       if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
 770         {
 771           if (operands[2] == const0_rtx)
 772             return \"and\\t%0, %1, %3, asr #31\";
 773           return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\";
 774         }
 775       else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
 776         {
 777           if (operands[1] == const0_rtx)
 778             return \"bic\\t%0, %2, %3, asr #31\";
 779           return \"bics\\t%0, %2, %3, asr #32\;it\\tcs\;movcs\\t%0, %1\";
 780         }
 781       /* The only case that falls through to here is when both ops 1 & 2
 782          are constants.  */
 783     }
 784
 785   if (GET_CODE (operands[5]) == GE
 786       && (operands[4] == const0_rtx))
 787     {
 788       if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
 789         {
 790           if (operands[2] == const0_rtx)
 791             return \"bic\\t%0, %1, %3, asr #31\";
 792           return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\";
 793         }
 794       else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
 795         {
 796           if (operands[1] == const0_rtx)
 797             return \"and\\t%0, %2, %3, asr #31\";
 798           return \"ands\\t%0, %2, %3, asr #32\;it\tcc\;movcc\\t%0, %1\";
 799         }
 800       /* The only case that falls through to here is when both ops 1 & 2
 801          are constants.  */
 802     }
 803   if (GET_CODE (operands[4]) == CONST_INT
 804       && !const_ok_for_arm (INTVAL (operands[4])))
 805     output_asm_insn (\"cmn\\t%3, #%n4\", operands);
 806   else
 807     output_asm_insn (\"cmp\\t%3, %4\", operands);
 808   switch (which_alternative)
 809     {
 810     case 0:
 811       output_asm_insn (\"it\\t%D5\", operands);
 812       break;
 813     case 1:
 814       output_asm_insn (\"it\\t%d5\", operands);
 815       break;
 816     case 2:
 817       output_asm_insn (\"ite\\t%d5\", operands);
 818       break;
 819     default:
 820       abort();
 821     }
 822   if (which_alternative != 0)
 823     output_asm_insn (\"mov%d5\\t%0, %1\", operands);
 824   if (which_alternative != 1)
 825     output_asm_insn (\"mov%D5\\t%0, %2\", operands);
 826   return \"\";
 827   "
 828   [(set_attr "conds" "clob")
 829    (set_attr "length" "10,10,14")]
 830 )
 831
 832 ;; Zero and sign extension instructions.
 833
 834 (define_insn_and_split "*thumb2_zero_extendsidi2"
 835   [(set (match_operand:DI 0 "s_register_operand" "=r")
 836         (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
 837   "TARGET_THUMB2"
 838   "mov%?\\t%Q0, %1\;mov%?\\t%R0, #0"
 839   "&& reload_completed"
 840   [(set (match_dup 0) (match_dup 1))]
 841   "
 842   {
 843     rtx lo_part = gen_lowpart (SImode, operands[0]);
 844     if (!REG_P (lo_part) || REGNO (lo_part) != REGNO (operands[1]))
 845       emit_move_insn (lo_part, operands[1]);
 846     operands[0] = gen_highpart (SImode, operands[0]);
 847     operands[1] = const0_rtx;
 848   }
 849   "
 850   [(set_attr "length" "8")
 851    (set_attr "ce_count" "2")
 852    (set_attr "predicable" "yes")]
 853 )
 854
 855 (define_insn_and_split "*thumb2_zero_extendhidi2"
 856   [(set (match_operand:DI                 0 "s_register_operand"  "=r,r")
 857         (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
 858   "TARGET_THUMB2"
 859   "@
 860    uxth%?\\t%Q0, %1\;mov%?\\t%R0, #0
 861    ldr%(h%)\\t%Q0, %1\;mov%?\\t%R0, #0"
 862   "&& reload_completed"
 863   [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
 864    (set (match_dup 2) (match_dup 3))]
 865   "
 866   {
 867     operands[2] = gen_highpart (SImode, operands[0]);
 868     operands[0] = gen_lowpart (SImode, operands[0]);
 869     operands[3] = const0_rtx;
 870   }
 871   "
 872   [(set_attr "length" "8")
 873    (set_attr "ce_count" "2")
 874    (set_attr "predicable" "yes")
 875    (set_attr "type" "*,load_byte")
 876    (set_attr "pool_range" "*,4092")
 877    (set_attr "neg_pool_range" "*,250")]
 878 )
 879
 880 (define_insn_and_split "*thumb2_zero_extendqidi2"
 881   [(set (match_operand:DI                 0 "s_register_operand"  "=r,r")
 882         (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
 883   "TARGET_THUMB2"
 884   "@
 885    uxtb%?\\t%Q0, %1\;mov%?\\t%R0, #0
 886    ldr%(b%)\\t%Q0, %1\;mov%?\\t%R0, #0"
 887   "&& reload_completed"
 888   [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
 889    (set (match_dup 2) (match_dup 3))]
 890   "
 891   {
 892     operands[2] = gen_highpart (SImode, operands[0]);
 893     operands[0] = gen_lowpart (SImode, operands[0]);
 894     operands[3] = const0_rtx;
 895   }
 896   "
 897   [(set_attr "length" "8")
 898    (set_attr "ce_count" "2")
 899    (set_attr "predicable" "yes")
 900    (set_attr "type" "*,load_byte")
 901    (set_attr "pool_range" "*,4092")
 902    (set_attr "neg_pool_range" "*,250")]
 903 )
 904
 905 (define_insn_and_split "*thumb2_extendsidi2"
 906   [(set (match_operand:DI 0 "s_register_operand" "=r")
 907         (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
 908   "TARGET_THUMB2"
 909   "mov%?\\t%Q0, %1\;asr?\\t%R0, %1, #31"
 910   "&& reload_completed"
 911   [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))]
 912   {
 913     rtx lo_part = gen_lowpart (SImode, operands[0]);
 914
 915     if (!REG_P (lo_part) || REGNO (lo_part) != REGNO (operands[1]))
 916       emit_move_insn (lo_part, operands[1]);
 917     operands[0] = gen_highpart (SImode, operands[0]);
 918   }
 919   [(set_attr "length" "8")
 920    (set_attr "ce_count" "2")
 921    (set_attr "shift" "1")
 922    (set_attr "predicable" "yes")]
 923 )
 924
 925 (define_insn_and_split "*thumb2_extendhidi2"
 926   [(set (match_operand:DI                 0 "s_register_operand"  "=r,r")
 927         (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
 928   "TARGET_THUMB2"
 929   "@
 930    sxth%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31
 931    ldrsh%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31"
 932   "&& reload_completed"
 933   [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
 934    (set (match_dup 2) (ashiftrt:SI (match_dup 0) (const_int 31)))]
 935   "
 936   {
 937     operands[2] = gen_highpart (SImode, operands[0]);
 938     operands[0] = gen_lowpart (SImode, operands[0]);
 939   }
 940   "
 941   [(set_attr "length" "8")
 942    (set_attr "ce_count" "2")
 943    (set_attr "predicable" "yes")
 944    (set_attr "type" "*,load_byte")
 945    (set_attr "pool_range" "*,4092")
 946    (set_attr "neg_pool_range" "*,250")]
 947 )
 948
 949 (define_insn_and_split "*thumb2_extendqidi2"
 950   [(set (match_operand:DI                 0 "s_register_operand"  "=r,r")
 951         (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
 952   "TARGET_THUMB2"
 953   "@
 954    sxtb%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31
 955    ldrsb%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31"
 956   "&& reload_completed"
 957   [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
 958    (set (match_dup 2) (ashiftrt:SI (match_dup 0) (const_int 31)))]
 959   "
 960   {
 961     operands[2] = gen_highpart (SImode, operands[0]);
 962     operands[0] = gen_lowpart (SImode, operands[0]);
 963   }
 964   "
 965   [(set_attr "length" "8")
 966    (set_attr "ce_count" "2")
 967    (set_attr "predicable" "yes")
 968    (set_attr "type" "*,load_byte")
 969    (set_attr "pool_range" "*,4092")
 970    (set_attr "neg_pool_range" "*,250")]
 971 )
 972
 973 ;; All supported Thumb2 implementations are armv6, so only that case is
 974 ;; provided.
 975 (define_insn "*thumb2_extendqisi_v6"
 976   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 977         (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
 978   "TARGET_THUMB2 && arm_arch6"
 979   "@
 980    sxtb%?\\t%0, %1
 981    ldr%(sb%)\\t%0, %1"
 982   [(set_attr "type" "alu_shift,load_byte")
 983    (set_attr "predicable" "yes")
 984    (set_attr "pool_range" "*,4096")
 985    (set_attr "neg_pool_range" "*,250")]
 986 )
 987
 988 (define_insn "*thumb2_zero_extendhisi2_v6"
 989   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 990         (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
 991   "TARGET_THUMB2 && arm_arch6"
 992   "@
 993    uxth%?\\t%0, %1
 994    ldr%(h%)\\t%0, %1"
 995   [(set_attr "type" "alu_shift,load_byte")
 996    (set_attr "predicable" "yes")
 997    (set_attr "pool_range" "*,4096")
 998    (set_attr "neg_pool_range" "*,250")]
 999 )
1000
1001 (define_insn "*thumb2_zero_extendqisi2_v6"
1002   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1003         (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1004   "TARGET_THUMB2 && arm_arch6"
1005   "@
1006    uxtb%(%)\\t%0, %1
1007    ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
1008   [(set_attr "type" "alu_shift,load_byte")
1009    (set_attr "predicable" "yes")
1010    (set_attr "pool_range" "*,4096")
1011    (set_attr "neg_pool_range" "*,250")]
1012 )
1013
1014 (define_insn "thumb2_casesi_internal"
1015   [(parallel [(set (pc)
1016                (if_then_else
1017                 (leu (match_operand:SI 0 "s_register_operand" "r")
1018                      (match_operand:SI 1 "arm_rhs_operand" "rI"))
1019                 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
1020                                  (label_ref (match_operand 2 "" ""))))
1021                 (label_ref (match_operand 3 "" ""))))
1022               (clobber (reg:CC CC_REGNUM))
1023               (clobber (match_scratch:SI 4 "=&r"))
1024               (use (label_ref (match_dup 2)))])]
1025   "TARGET_THUMB2 && !flag_pic"
1026   "* return thumb2_output_casesi(operands);"
1027   [(set_attr "conds" "clob")
1028    (set_attr "length" "16")]
1029 )
1030
1031 (define_insn "thumb2_casesi_internal_pic"
1032   [(parallel [(set (pc)
1033                (if_then_else
1034                 (leu (match_operand:SI 0 "s_register_operand" "r")
1035                      (match_operand:SI 1 "arm_rhs_operand" "rI"))
1036                 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
1037                                  (label_ref (match_operand 2 "" ""))))
1038                 (label_ref (match_operand 3 "" ""))))
1039               (clobber (reg:CC CC_REGNUM))
1040               (clobber (match_scratch:SI 4 "=&r"))
1041               (clobber (match_scratch:SI 5 "=r"))
1042               (use (label_ref (match_dup 2)))])]
1043   "TARGET_THUMB2 && flag_pic"
1044   "* return thumb2_output_casesi(operands);"
1045   [(set_attr "conds" "clob")
1046    (set_attr "length" "20")]
1047 )
1048
1049 (define_insn_and_split "thumb2_eh_return"
1050   [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
1051                     VUNSPEC_EH_RETURN)
1052    (clobber (match_scratch:SI 1 "=&r"))]
1053   "TARGET_THUMB2"
1054   "#"
1055   "&& reload_completed"
1056   [(const_int 0)]
1057   "
1058   {
1059     thumb_set_return_address (operands[0], operands[1]);
1060     DONE;
1061   }"
1062 )
1063
1064 ;; Peepholes and insns for 16-bit flag clobbering instructions.
1065 ;; The conditional forms of these instructions do not clobber CC.
1066 ;; However by the time peepholes are run it is probably too late to do
1067 ;; anything useful with this information.
1068 (define_peephole2
1069   [(set (match_operand:SI          0 "low_register_operand" "")
1070         (match_operator:SI 3 "thumb_16bit_operator"
1071          [(match_operand:SI 1  "low_register_operand" "")
1072           (match_operand:SI 2 "low_register_operand" "")]))]
1073   "TARGET_THUMB2
1074    && (rtx_equal_p(operands[0], operands[1])
1075        || GET_CODE(operands[3]) == PLUS
1076        || GET_CODE(operands[3]) == MINUS)
1077    && peep2_regno_dead_p(0, CC_REGNUM)"
1078   [(parallel
1079     [(set (match_dup 0)
1080           (match_op_dup 3
1081            [(match_dup 1)
1082             (match_dup 2)]))
1083      (clobber (reg:CC CC_REGNUM))])]
1084   ""
1085 )
1086
1087 (define_insn "*thumb2_alusi3_short"
1088   [(set (match_operand:SI          0 "s_register_operand" "=l")
1089         (match_operator:SI 3 "thumb_16bit_operator"
1090          [(match_operand:SI 1 "s_register_operand" "0")
1091           (match_operand:SI 2 "s_register_operand" "l")]))
1092    (clobber (reg:CC CC_REGNUM))]
1093   "TARGET_THUMB2 && reload_completed
1094    && GET_CODE(operands[3]) != PLUS
1095    && GET_CODE(operands[3]) != MINUS"
1096   "%I3%!\\t%0, %1, %2"
1097   [(set_attr "predicable" "yes")
1098    (set_attr "length" "2")]
1099 )
1100
1101 ;; Similarly for 16-bit shift instructions
1102 ;; There is no 16-bit rotate by immediate instruction.
1103 (define_peephole2
1104   [(set (match_operand:SI   0 "low_register_operand" "")
1105         (match_operator:SI  3 "shift_operator"
1106          [(match_operand:SI 1 "low_register_operand" "")
1107           (match_operand:SI 2 "low_reg_or_int_operand" "")]))]
1108   "TARGET_THUMB2
1109    && peep2_regno_dead_p(0, CC_REGNUM)
1110    && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
1111        || REG_P(operands[2]))"
1112   [(parallel
1113     [(set (match_dup 0)
1114           (match_op_dup 3
1115            [(match_dup 1)
1116             (match_dup 2)]))
1117      (clobber (reg:CC CC_REGNUM))])]
1118   ""
1119 )
1120
1121 (define_insn "*thumb2_shiftsi3_short"
1122   [(set (match_operand:SI   0 "low_register_operand" "=l")
1123         (match_operator:SI  3 "shift_operator"
1124          [(match_operand:SI 1 "low_register_operand"  "l")
1125           (match_operand:SI 2 "low_reg_or_int_operand" "lM")]))
1126    (clobber (reg:CC CC_REGNUM))]
1127   "TARGET_THUMB2 && reload_completed
1128    && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
1129        || REG_P(operands[2]))"
1130   "* return arm_output_shift(operands, 2);"
1131   [(set_attr "predicable" "yes")
1132    (set_attr "shift" "1")
1133    (set_attr "length" "2")
1134    (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
1135                       (const_string "alu_shift")
1136                       (const_string "alu_shift_reg")))]
1137 )
1138
1139 ;; 16-bit load immediate
1140 (define_peephole2
1141   [(set (match_operand:QHSI 0 "low_register_operand" "")
1142         (match_operand:QHSI 1 "const_int_operand" ""))]
1143   "TARGET_THUMB2
1144    && peep2_regno_dead_p(0, CC_REGNUM)
1145    && (unsigned HOST_WIDE_INT) INTVAL(operands[1]) < 256"
1146   [(parallel
1147     [(set (match_dup 0)
1148           (match_dup 1))
1149      (clobber (reg:CC CC_REGNUM))])]
1150   ""
1151 )
1152
1153 (define_insn "*thumb2_mov<mode>_shortim"
1154   [(set (match_operand:QHSI 0 "low_register_operand" "=l")
1155         (match_operand:QHSI 1 "const_int_operand" "I"))
1156    (clobber (reg:CC CC_REGNUM))]
1157   "TARGET_THUMB2 && reload_completed"
1158   "mov%!\t%0, %1"
1159   [(set_attr "predicable" "yes")
1160    (set_attr "length" "2")]
1161 )
1162
1163 ;; 16-bit add/sub immediate
1164 (define_peephole2
1165   [(set (match_operand:SI 0 "low_register_operand" "")
1166         (plus:SI (match_operand:SI 1 "low_register_operand" "")
1167                  (match_operand:SI 2 "const_int_operand" "")))]
1168   "TARGET_THUMB2
1169    && peep2_regno_dead_p(0, CC_REGNUM)
1170    && ((rtx_equal_p(operands[0], operands[1])
1171         && INTVAL(operands[2]) > -256 && INTVAL(operands[2]) < 256)
1172        || (INTVAL(operands[2]) > -8 && INTVAL(operands[2]) < 8))"
1173   [(parallel
1174     [(set (match_dup 0)
1175           (plus:SI (match_dup 1)
1176                    (match_dup 2)))
1177      (clobber (reg:CC CC_REGNUM))])]
1178   ""
1179 )
1180
1181 (define_insn "*thumb2_addsi_short"
1182   [(set (match_operand:SI 0 "low_register_operand" "=l,l")
1183         (plus:SI (match_operand:SI 1 "low_register_operand" "l,0")
1184                  (match_operand:SI 2 "low_reg_or_int_operand" "lPt,Ps")))
1185    (clobber (reg:CC CC_REGNUM))]
1186   "TARGET_THUMB2 && reload_completed"
1187   "*
1188     HOST_WIDE_INT val;
1189
1190     if (GET_CODE (operands[2]) == CONST_INT)
1191       val = INTVAL(operands[2]);
1192     else
1193       val = 0;
1194
1195     /* We prefer eg. subs rn, rn, #1 over adds rn, rn, #0xffffffff.  */
1196     if (val < 0 && const_ok_for_arm(ARM_SIGN_EXTEND (-val)))
1197       return \"sub%!\\t%0, %1, #%n2\";
1198     else
1199       return \"add%!\\t%0, %1, %2\";
1200   "
1201   [(set_attr "predicable" "yes")
1202    (set_attr "length" "2")]
1203 )
1204
1205 (define_insn "divsi3"
1206   [(set (match_operand:SI         0 "s_register_operand" "=r")
1207         (div:SI (match_operand:SI 1 "s_register_operand"  "r")
1208                 (match_operand:SI 2 "s_register_operand"  "r")))]
1209   "TARGET_THUMB2 && arm_arch_hwdiv"
1210   "sdiv%?\t%0, %1, %2"
1211   [(set_attr "predicable" "yes")
1212    (set_attr "insn" "sdiv")]
1213 )
1214
1215 (define_insn "udivsi3"
1216   [(set (match_operand:SI          0 "s_register_operand" "=r")
1217         (udiv:SI (match_operand:SI 1 "s_register_operand"  "r")
1218                  (match_operand:SI 2 "s_register_operand"  "r")))]
1219   "TARGET_THUMB2 && arm_arch_hwdiv"
1220   "udiv%?\t%0, %1, %2"
1221   [(set_attr "predicable" "yes")
1222    (set_attr "insn" "udiv")]
1223 )
1224
1225 (define_insn "*thumb2_subsi_short"
1226   [(set (match_operand:SI 0 "low_register_operand" "=l")
1227         (minus:SI (match_operand:SI 1 "low_register_operand" "l")
1228                   (match_operand:SI 2 "low_register_operand" "l")))
1229    (clobber (reg:CC CC_REGNUM))]
1230   "TARGET_THUMB2 && reload_completed"
1231   "sub%!\\t%0, %1, %2"
1232   [(set_attr "predicable" "yes")
1233    (set_attr "length" "2")]
1234 )
1235
1236 ;; 16-bit encodings of "muls" and "mul<c>".  We only use these when
1237 ;; optimizing for size since "muls" is slow on all known
1238 ;; implementations and since "mul<c>" will be generated by
1239 ;; "*arm_mulsi3_v6" anyhow.  The assembler will use a 16-bit encoding
1240 ;; for "mul<c>" whenever possible anyhow.
1241 (define_peephole2
1242   [(set (match_operand:SI 0 "low_register_operand" "")
1243         (mult:SI (match_operand:SI 1 "low_register_operand" "")
1244                  (match_dup 0)))]
1245   "TARGET_THUMB2 && optimize_size && peep2_regno_dead_p (0, CC_REGNUM)"
1246   [(parallel
1247     [(set (match_dup 0)
1248            (mult:SI (match_dup 0) (match_dup 1)))
1249      (clobber (reg:CC CC_REGNUM))])]
1250   ""
1251 )
1252
1253 (define_peephole2
1254   [(set (match_operand:SI 0 "low_register_operand" "")
1255         (mult:SI (match_dup 0)
1256                  (match_operand:SI 1 "low_register_operand" "")))]
1257   "TARGET_THUMB2 && optimize_size && peep2_regno_dead_p (0, CC_REGNUM)"
1258   [(parallel
1259     [(set (match_dup 0)
1260            (mult:SI (match_dup 0) (match_dup 1)))
1261      (clobber (reg:CC CC_REGNUM))])]
1262   ""
1263 )
1264
1265 (define_insn "*thumb2_mulsi_short"
1266   [(set (match_operand:SI 0 "low_register_operand" "=l")
1267         (mult:SI (match_operand:SI 1 "low_register_operand" "%0")
1268                  (match_operand:SI 2 "low_register_operand" "l")))
1269    (clobber (reg:CC CC_REGNUM))]
1270   "TARGET_THUMB2 && optimize_size && reload_completed"
1271   "mul%!\\t%0, %2, %0"
1272   [(set_attr "predicable" "yes")
1273    (set_attr "length" "2")
1274    (set_attr "insn" "muls")])
1275
1276 (define_insn "*thumb2_mulsi_short_compare0"
1277   [(set (reg:CC_NOOV CC_REGNUM)
1278         (compare:CC_NOOV
1279          (mult:SI (match_operand:SI 1 "register_operand" "%0")
1280                   (match_operand:SI 2 "register_operand" "l"))
1281          (const_int 0)))
1282    (set (match_operand:SI 0 "register_operand" "=l")
1283         (mult:SI (match_dup 1) (match_dup 2)))]
1284   "TARGET_THUMB2 && optimize_size"
1285   "muls\\t%0, %2, %0"
1286   [(set_attr "length" "2")
1287    (set_attr "insn" "muls")])
1288
1289 (define_insn "*thumb2_mulsi_short_compare0_scratch"
1290   [(set (reg:CC_NOOV CC_REGNUM)
1291         (compare:CC_NOOV
1292          (mult:SI (match_operand:SI 1 "register_operand" "%0")
1293                   (match_operand:SI 2 "register_operand" "l"))
1294          (const_int 0)))
1295    (clobber (match_scratch:SI 0 "=l"))]
1296   "TARGET_THUMB2 && optimize_size"
1297   "muls\\t%0, %2, %0"
1298   [(set_attr "length" "2")
1299    (set_attr "insn" "muls")])
1300
1301 (define_insn "*thumb2_cbz"
1302   [(set (pc) (if_then_else
1303               (eq (match_operand:SI 0 "s_register_operand" "l,?r")
1304                   (const_int 0))
1305               (label_ref (match_operand 1 "" ""))
1306               (pc)))
1307    (clobber (reg:CC CC_REGNUM))]
1308   "TARGET_THUMB2"
1309   "*
1310   if (get_attr_length (insn) == 2)
1311     return \"cbz\\t%0, %l1\";
1312   else
1313     return \"cmp\\t%0, #0\;beq\\t%l1\";
1314   "
1315   [(set (attr "length")
1316         (if_then_else
1317             (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1318                  (le (minus (match_dup 1) (pc)) (const_int 128))
1319                  (eq (symbol_ref ("which_alternative")) (const_int 0)))
1320             (const_int 2)
1321             (const_int 8)))]
1322 )
1323
1324 (define_insn "*thumb2_cbnz"
1325   [(set (pc) (if_then_else
1326               (ne (match_operand:SI 0 "s_register_operand" "l,?r")
1327                   (const_int 0))
1328               (label_ref (match_operand 1 "" ""))
1329               (pc)))
1330    (clobber (reg:CC CC_REGNUM))]
1331   "TARGET_THUMB2"
1332   "*
1333   if (get_attr_length (insn) == 2)
1334     return \"cbnz\\t%0, %l1\";
1335   else
1336     return \"cmp\\t%0, #0\;bne\\t%l1\";
1337   "
1338   [(set (attr "length")
1339         (if_then_else
1340             (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1341                  (le (minus (match_dup 1) (pc)) (const_int 128))
1342                  (eq (symbol_ref ("which_alternative")) (const_int 0)))
1343             (const_int 2)
1344             (const_int 8)))]
1345 )
1346
1347 ;; 16-bit complement
1348 (define_peephole2
1349   [(set (match_operand:SI 0 "low_register_operand" "")
1350         (not:SI (match_operand:SI 1 "low_register_operand" "")))]
1351   "TARGET_THUMB2
1352    && peep2_regno_dead_p(0, CC_REGNUM)"
1353   [(parallel
1354     [(set (match_dup 0)
1355           (not:SI (match_dup 1)))
1356      (clobber (reg:CC CC_REGNUM))])]
1357   ""
1358 )
1359
1360 (define_insn "*thumb2_one_cmplsi2_short"
1361   [(set (match_operand:SI 0 "low_register_operand" "=l")
1362         (not:SI (match_operand:SI 1 "low_register_operand" "l")))
1363    (clobber (reg:CC CC_REGNUM))]
1364   "TARGET_THUMB2 && reload_completed"
1365   "mvn%!\t%0, %1"
1366   [(set_attr "predicable" "yes")
1367    (set_attr "length" "2")]
1368 )
1369
1370 ;; 16-bit negate
1371 (define_peephole2
1372   [(set (match_operand:SI 0 "low_register_operand" "")
1373         (neg:SI (match_operand:SI 1 "low_register_operand" "")))]
1374   "TARGET_THUMB2
1375    && peep2_regno_dead_p(0, CC_REGNUM)"
1376   [(parallel
1377     [(set (match_dup 0)
1378           (neg:SI (match_dup 1)))
1379      (clobber (reg:CC CC_REGNUM))])]
1380   ""
1381 )
1382
1383 (define_insn "*thumb2_negsi2_short"
1384   [(set (match_operand:SI 0 "low_register_operand" "=l")
1385         (neg:SI (match_operand:SI 1 "low_register_operand" "l")))
1386    (clobber (reg:CC CC_REGNUM))]
1387   "TARGET_THUMB2 && reload_completed"
1388   "neg%!\t%0, %1"
1389   [(set_attr "predicable" "yes")
1390    (set_attr "length" "2")]
1391 )
1392
1393 (define_insn "orsi_notsi_si"
1394   [(set (match_operand:SI 0 "s_register_operand" "=r")
1395         (ior:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
1396                 (match_operand:SI 1 "s_register_operand" "r")))]
1397   "TARGET_THUMB2"
1398   "orn%?\\t%0, %1, %2"
1399   [(set_attr "predicable" "yes")]
1400 )
1401
1402 (define_insn "*thumb_orsi_not_shiftsi_si"
1403   [(set (match_operand:SI 0 "s_register_operand" "=r")
1404         (ior:SI (not:SI (match_operator:SI 4 "shift_operator"
1405                          [(match_operand:SI 2 "s_register_operand" "r")
1406                           (match_operand:SI 3 "const_int_operand" "M")]))
1407                 (match_operand:SI 1 "s_register_operand" "r")))]
1408   "TARGET_THUMB2"
1409   "orn%?\\t%0, %1, %2%S4"
1410   [(set_attr "predicable" "yes")
1411    (set_attr "shift" "2")
1412    (set_attr "type" "alu_shift")]
1413 )
1414
1415 (define_insn_and_split "*thumb2_iorsi3"
1416   [(set (match_operand:SI         0 "s_register_operand" "=r,r,r")
1417         (ior:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
1418                 (match_operand:SI 2 "reg_or_int_operand" "rI,K,?n")))]
1419   "TARGET_THUMB2"
1420   "@
1421    orr%?\\t%0, %1, %2
1422    orn%?\\t%0, %1, #%B2
1423    #"
1424   "TARGET_THUMB2
1425    && GET_CODE (operands[2]) == CONST_INT
1426    && !(const_ok_for_arm (INTVAL (operands[2]))
1427         || const_ok_for_arm (~INTVAL (operands[2])))"
1428   [(clobber (const_int 0))]
1429   "
1430   arm_split_constant  (IOR, SImode, curr_insn,
1431                        INTVAL (operands[2]), operands[0], operands[1], 0);
1432   DONE;
1433   "
1434   [(set_attr "length" "4,4,16")
1435    (set_attr "predicable" "yes")]
1436 )