gcc/config/arm/thumb2.md

   1 ;; ARM Thumb-2 Machine Description
   2 ;; Copyright (C) 2007, 2008 Free Software Foundation, Inc.
   3 ;; Written by CodeSourcery, LLC.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.  */
  20
  21 ;; Note: Thumb-2 is the variant of the Thumb architecture that adds
  22 ;; 32-bit encodings of [almost all of] the Arm instruction set.
  23 ;; Some old documents refer to the relatively minor interworking
  24 ;; changes made in armv5t as "thumb2".  These are considered part
  25 ;; the 16-bit Thumb-1 instruction set.
  26
  27 (define_insn "*thumb2_incscc"
  28   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
  29         (plus:SI (match_operator:SI 2 "arm_comparison_operator"
  30                     [(match_operand:CC 3 "cc_register" "") (const_int 0)])
  31                  (match_operand:SI 1 "s_register_operand" "0,?r")))]
  32   "TARGET_THUMB2"
  33   "@
  34   it\\t%d2\;add%d2\\t%0, %1, #1
  35   ite\\t%D2\;mov%D2\\t%0, %1\;add%d2\\t%0, %1, #1"
  36   [(set_attr "conds" "use")
  37    (set_attr "length" "6,10")]
  38 )
  39
  40 (define_insn "*thumb2_decscc"
  41   [(set (match_operand:SI            0 "s_register_operand" "=r,r")
  42         (minus:SI (match_operand:SI  1 "s_register_operand" "0,?r")
  43                   (match_operator:SI 2 "arm_comparison_operator"
  44                    [(match_operand   3 "cc_register" "") (const_int 0)])))]
  45   "TARGET_THUMB2"
  46   "@
  47    it\\t%d2\;sub%d2\\t%0, %1, #1
  48    ite\\t%D2\;mov%D2\\t%0, %1\;sub%d2\\t%0, %1, #1"
  49   [(set_attr "conds" "use")
  50    (set_attr "length" "6,10")]
  51 )
  52
  53 ;; Thumb-2 only allows shift by constant on data processing instructions
  54 (define_insn "*thumb_andsi_not_shiftsi_si"
  55   [(set (match_operand:SI 0 "s_register_operand" "=r")
  56         (and:SI (not:SI (match_operator:SI 4 "shift_operator"
  57                          [(match_operand:SI 2 "s_register_operand" "r")
  58                           (match_operand:SI 3 "const_int_operand" "M")]))
  59                 (match_operand:SI 1 "s_register_operand" "r")))]
  60   "TARGET_THUMB2"
  61   "bic%?\\t%0, %1, %2%S4"
  62   [(set_attr "predicable" "yes")
  63    (set_attr "shift" "2")
  64    (set_attr "type" "alu_shift")]
  65 )
  66
  67 (define_insn "*thumb2_smaxsi3"
  68   [(set (match_operand:SI          0 "s_register_operand" "=r,r,r")
  69         (smax:SI (match_operand:SI 1 "s_register_operand"  "0,r,?r")
  70                  (match_operand:SI 2 "arm_rhs_operand"    "rI,0,rI")))
  71    (clobber (reg:CC CC_REGNUM))]
  72   "TARGET_THUMB2"
  73   "@
  74    cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2
  75    cmp\\t%1, %2\;it\\tge\;movge\\t%0, %1
  76    cmp\\t%1, %2\;ite\\tge\;movge\\t%0, %1\;movlt\\t%0, %2"
  77   [(set_attr "conds" "clob")
  78    (set_attr "length" "10,10,14")]
  79 )
  80
  81 (define_insn "*thumb2_sminsi3"
  82   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
  83         (smin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
  84                  (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
  85    (clobber (reg:CC CC_REGNUM))]
  86   "TARGET_THUMB2"
  87   "@
  88    cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2
  89    cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %1
  90    cmp\\t%1, %2\;ite\\tlt\;movlt\\t%0, %1\;movge\\t%0, %2"
  91   [(set_attr "conds" "clob")
  92    (set_attr "length" "10,10,14")]
  93 )
  94
  95 (define_insn "*thumb32_umaxsi3"
  96   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
  97         (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
  98                  (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
  99    (clobber (reg:CC CC_REGNUM))]
 100   "TARGET_THUMB2"
 101   "@
 102    cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2
 103    cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %1
 104    cmp\\t%1, %2\;ite\\tcs\;movcs\\t%0, %1\;movcc\\t%0, %2"
 105   [(set_attr "conds" "clob")
 106    (set_attr "length" "10,10,14")]
 107 )
 108
 109 (define_insn "*thumb2_uminsi3"
 110   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
 111         (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
 112                  (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
 113    (clobber (reg:CC CC_REGNUM))]
 114   "TARGET_THUMB2"
 115   "@
 116    cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2
 117    cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %1
 118    cmp\\t%1, %2\;ite\\tcc\;movcc\\t%0, %1\;movcs\\t%0, %2"
 119   [(set_attr "conds" "clob")
 120    (set_attr "length" "10,10,14")]
 121 )
 122
 123 ;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
 124 (define_insn "*thumb2_negdi2"
 125   [(set (match_operand:DI         0 "s_register_operand" "=&r,r")
 126         (neg:DI (match_operand:DI 1 "s_register_operand"  "?r,0")))
 127    (clobber (reg:CC CC_REGNUM))]
 128   "TARGET_THUMB2"
 129   "negs\\t%Q0, %Q1\;sbc\\t%R0, %R1, %R1, lsl #1"
 130   [(set_attr "conds" "clob")
 131    (set_attr "length" "8")]
 132 )
 133
 134 (define_insn "*thumb2_abssi2"
 135   [(set (match_operand:SI         0 "s_register_operand" "=r,&r")
 136         (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
 137    (clobber (reg:CC CC_REGNUM))]
 138   "TARGET_THUMB2"
 139   "@
 140    cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
 141    eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31"
 142   [(set_attr "conds" "clob,*")
 143    (set_attr "shift" "1")
 144    ;; predicable can't be set based on the variant, so left as no
 145    (set_attr "length" "10,8")]
 146 )
 147
 148 (define_insn "*thumb2_neg_abssi2"
 149   [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
 150         (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
 151    (clobber (reg:CC CC_REGNUM))]
 152   "TARGET_THUMB2"
 153   "@
 154    cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
 155    eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31"
 156   [(set_attr "conds" "clob,*")
 157    (set_attr "shift" "1")
 158    ;; predicable can't be set based on the variant, so left as no
 159    (set_attr "length" "10,8")]
 160 )
 161
 162 ;; We have two alternatives here for memory loads (and similarly for stores)
 163 ;; to reflect the fact that the permissible constant pool ranges differ
 164 ;; between ldr instructions taking low regs and ldr instructions taking high
 165 ;; regs.  The high register alternatives are not taken into account when
 166 ;; choosing register preferences in order to reflect their expense.
 167 (define_insn "*thumb2_movsi_insn"
 168   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l ,*hk,m,*m")
 169         (match_operand:SI 1 "general_operand"      "rk ,I,K,j,mi,*mi,l,*hk"))]
 170   "TARGET_THUMB2 && ! TARGET_IWMMXT
 171    && !(TARGET_HARD_FLOAT && TARGET_VFP)
 172    && (   register_operand (operands[0], SImode)
 173        || register_operand (operands[1], SImode))"
 174   "@
 175    mov%?\\t%0, %1
 176    mov%?\\t%0, %1
 177    mvn%?\\t%0, #%B1
 178    movw%?\\t%0, %1
 179    ldr%?\\t%0, %1
 180    ldr%?\\t%0, %1
 181    str%?\\t%1, %0
 182    str%?\\t%1, %0"
 183   [(set_attr "type" "*,*,*,*,load1,load1,store1,store1")
 184    (set_attr "predicable" "yes")
 185    (set_attr "pool_range" "*,*,*,*,1020,4096,*,*")
 186    (set_attr "neg_pool_range" "*,*,*,*,0,0,*,*")]
 187 )
 188
 189 (define_insn "tls_load_dot_plus_four"
 190   [(set (match_operand:SI 0 "register_operand" "=l,l,r,r")
 191         (mem:SI (unspec:SI [(match_operand:SI 2 "register_operand" "0,1,0,1")
 192                             (const_int 4)
 193                             (match_operand 3 "" "")]
 194                            UNSPEC_PIC_BASE)))
 195    (clobber (match_scratch:SI 1 "=X,l,X,r"))]
 196   "TARGET_THUMB2"
 197   "*
 198   (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
 199                              INTVAL (operands[3]));
 200   return \"add\\t%2, %|pc\;ldr%?\\t%0, [%2]\";
 201   "
 202   [(set_attr "length" "4,4,6,6")]
 203 )
 204
 205 ;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
 206 ;; of the messiness associated with the ARM patterns.
 207 (define_insn "*thumb2_movhi_insn"
 208   [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
 209         (match_operand:HI 1 "general_operand"      "rI,n,r,m"))]
 210   "TARGET_THUMB2"
 211   "@
 212    mov%?\\t%0, %1\\t%@ movhi
 213    movw%?\\t%0, %L1\\t%@ movhi
 214    str%(h%)\\t%1, %0\\t%@ movhi
 215    ldr%(h%)\\t%0, %1\\t%@ movhi"
 216   [(set_attr "type" "*,*,store1,load1")
 217    (set_attr "predicable" "yes")
 218    (set_attr "pool_range" "*,*,*,4096")
 219    (set_attr "neg_pool_range" "*,*,*,250")]
 220 )
 221
 222 (define_insn "*thumb2_cmpsi_neg_shiftsi"
 223   [(set (reg:CC CC_REGNUM)
 224         (compare:CC (match_operand:SI 0 "s_register_operand" "r")
 225                     (neg:SI (match_operator:SI 3 "shift_operator"
 226                              [(match_operand:SI 1 "s_register_operand" "r")
 227                               (match_operand:SI 2 "const_int_operand" "M")]))))]
 228   "TARGET_THUMB2"
 229   "cmn%?\\t%0, %1%S3"
 230   [(set_attr "conds" "set")
 231    (set_attr "shift" "1")
 232    (set_attr "type" "alu_shift")]
 233 )
 234
 235 (define_insn "*thumb2_mov_scc"
 236   [(set (match_operand:SI 0 "s_register_operand" "=r")
 237         (match_operator:SI 1 "arm_comparison_operator"
 238          [(match_operand 2 "cc_register" "") (const_int 0)]))]
 239   "TARGET_THUMB2"
 240   "ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
 241   [(set_attr "conds" "use")
 242    (set_attr "length" "10")]
 243 )
 244
 245 (define_insn "*thumb2_mov_negscc"
 246   [(set (match_operand:SI 0 "s_register_operand" "=r")
 247         (neg:SI (match_operator:SI 1 "arm_comparison_operator"
 248                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 249   "TARGET_THUMB2"
 250   "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
 251   [(set_attr "conds" "use")
 252    (set_attr "length" "10")]
 253 )
 254
 255 (define_insn "*thumb2_mov_notscc"
 256   [(set (match_operand:SI 0 "s_register_operand" "=r")
 257         (not:SI (match_operator:SI 1 "arm_comparison_operator"
 258                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 259   "TARGET_THUMB2"
 260   "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #1"
 261   [(set_attr "conds" "use")
 262    (set_attr "length" "10")]
 263 )
 264
 265 (define_insn "*thumb2_movsicc_insn"
 266   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r")
 267         (if_then_else:SI
 268          (match_operator 3 "arm_comparison_operator"
 269           [(match_operand 4 "cc_register" "") (const_int 0)])
 270          (match_operand:SI 1 "arm_not_operand" "0,0,rI,K,rI,rI,K,K")
 271          (match_operand:SI 2 "arm_not_operand" "rI,K,0,0,rI,K,rI,K")))]
 272   "TARGET_THUMB2"
 273   "@
 274    it\\t%D3\;mov%D3\\t%0, %2
 275    it\\t%D3\;mvn%D3\\t%0, #%B2
 276    it\\t%d3\;mov%d3\\t%0, %1
 277    it\\t%d3\;mvn%d3\\t%0, #%B1
 278    ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
 279    ite\\t%d3\;mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2
 280    ite\\t%d3\;mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2
 281    ite\\t%d3\;mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2"
 282   [(set_attr "length" "6,6,6,6,10,10,10,10")
 283    (set_attr "conds" "use")]
 284 )
 285
 286 (define_insn "*thumb2_movsfcc_soft_insn"
 287   [(set (match_operand:SF 0 "s_register_operand" "=r,r")
 288         (if_then_else:SF (match_operator 3 "arm_comparison_operator"
 289                           [(match_operand 4 "cc_register" "") (const_int 0)])
 290                          (match_operand:SF 1 "s_register_operand" "0,r")
 291                          (match_operand:SF 2 "s_register_operand" "r,0")))]
 292   "TARGET_THUMB2 && TARGET_SOFT_FLOAT"
 293   "@
 294    it\\t%D3\;mov%D3\\t%0, %2
 295    it\\t%d3\;mov%d3\\t%0, %1"
 296   [(set_attr "length" "6,6")
 297    (set_attr "conds" "use")]
 298 )
 299
 300 (define_insn "*call_reg_thumb2"
 301   [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
 302          (match_operand 1 "" ""))
 303    (use (match_operand 2 "" ""))
 304    (clobber (reg:SI LR_REGNUM))]
 305   "TARGET_THUMB2"
 306   "blx%?\\t%0"
 307   [(set_attr "type" "call")]
 308 )
 309
 310 (define_insn "*call_value_reg_thumb2"
 311   [(set (match_operand 0 "" "")
 312         (call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
 313               (match_operand 2 "" "")))
 314    (use (match_operand 3 "" ""))
 315    (clobber (reg:SI LR_REGNUM))]
 316   "TARGET_THUMB2"
 317   "blx\\t%1"
 318   [(set_attr "type" "call")]
 319 )
 320
 321 (define_insn "*thumb2_indirect_jump"
 322   [(set (pc)
 323         (match_operand:SI 0 "register_operand" "l*r"))]
 324   "TARGET_THUMB2"
 325   "bx\\t%0"
 326   [(set_attr "conds" "clob")]
 327 )
 328 ;; Don't define thumb2_load_indirect_jump because we can't guarantee label
 329 ;; addresses will have the thumb bit set correctly.
 330
 331
 332 (define_insn "*thumb2_and_scc"
 333   [(set (match_operand:SI 0 "s_register_operand" "=r")
 334         (and:SI (match_operator:SI 1 "arm_comparison_operator"
 335                  [(match_operand 3 "cc_register" "") (const_int 0)])
 336                 (match_operand:SI 2 "s_register_operand" "r")))]
 337   "TARGET_THUMB2"
 338   "ite\\t%D1\;mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1"
 339   [(set_attr "conds" "use")
 340    (set_attr "length" "10")]
 341 )
 342
 343 (define_insn "*thumb2_ior_scc"
 344   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 345         (ior:SI (match_operator:SI 2 "arm_comparison_operator"
 346                  [(match_operand 3 "cc_register" "") (const_int 0)])
 347                 (match_operand:SI 1 "s_register_operand" "0,?r")))]
 348   "TARGET_THUMB2"
 349   "@
 350    it\\t%d2\;orr%d2\\t%0, %1, #1
 351    ite\\t%D2\;mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1"
 352   [(set_attr "conds" "use")
 353    (set_attr "length" "6,10")]
 354 )
 355
 356 (define_insn "*thumb2_cond_move"
 357   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
 358         (if_then_else:SI (match_operator 3 "equality_operator"
 359                           [(match_operator 4 "arm_comparison_operator"
 360                             [(match_operand 5 "cc_register" "") (const_int 0)])
 361                            (const_int 0)])
 362                          (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
 363                          (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))]
 364   "TARGET_THUMB2"
 365   "*
 366     if (GET_CODE (operands[3]) == NE)
 367       {
 368         if (which_alternative != 1)
 369           output_asm_insn (\"it\\t%D4\;mov%D4\\t%0, %2\", operands);
 370         if (which_alternative != 0)
 371           output_asm_insn (\"it\\t%d4\;mov%d4\\t%0, %1\", operands);
 372         return \"\";
 373       }
 374     switch (which_alternative)
 375       {
 376       case 0:
 377         output_asm_insn (\"it\\t%d4\", operands);
 378         break;
 379       case 1:
 380         output_asm_insn (\"it\\t%D4\", operands);
 381         break;
 382       case 2:
 383         output_asm_insn (\"ite\\t%D4\", operands);
 384         break;
 385       default:
 386         abort();
 387       }
 388     if (which_alternative != 0)
 389       output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 390     if (which_alternative != 1)
 391       output_asm_insn (\"mov%d4\\t%0, %2\", operands);
 392     return \"\";
 393   "
 394   [(set_attr "conds" "use")
 395    (set_attr "length" "6,6,10")]
 396 )
 397
 398 (define_insn "*thumb2_cond_arith"
 399   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 400         (match_operator:SI 5 "shiftable_operator"
 401          [(match_operator:SI 4 "arm_comparison_operator"
 402            [(match_operand:SI 2 "s_register_operand" "r,r")
 403             (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
 404           (match_operand:SI 1 "s_register_operand" "0,?r")]))
 405    (clobber (reg:CC CC_REGNUM))]
 406   "TARGET_THUMB2"
 407   "*
 408     if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
 409       return \"%i5\\t%0, %1, %2, lsr #31\";
 410
 411     output_asm_insn (\"cmp\\t%2, %3\", operands);
 412     if (GET_CODE (operands[5]) == AND)
 413       {
 414         output_asm_insn (\"ite\\t%D4\", operands);
 415         output_asm_insn (\"mov%D4\\t%0, #0\", operands);
 416       }
 417     else if (GET_CODE (operands[5]) == MINUS)
 418       {
 419         output_asm_insn (\"ite\\t%D4\", operands);
 420         output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands);
 421       }
 422     else if (which_alternative != 0)
 423       {
 424         output_asm_insn (\"ite\\t%D4\", operands);
 425         output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 426       }
 427     else
 428       output_asm_insn (\"it\\t%d4\", operands);
 429     return \"%i5%d4\\t%0, %1, #1\";
 430   "
 431   [(set_attr "conds" "clob")
 432    (set_attr "length" "14")]
 433 )
 434
 435 (define_insn "*thumb2_cond_sub"
 436   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 437         (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r")
 438                   (match_operator:SI 4 "arm_comparison_operator"
 439                    [(match_operand:SI 2 "s_register_operand" "r,r")
 440                     (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
 441    (clobber (reg:CC CC_REGNUM))]
 442   "TARGET_THUMB2"
 443   "*
 444     output_asm_insn (\"cmp\\t%2, %3\", operands);
 445     if (which_alternative != 0)
 446       {
 447         output_asm_insn (\"ite\\t%D4\", operands);
 448         output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 449       }
 450     else
 451       output_asm_insn (\"it\\t%d4\", operands);
 452     return \"sub%d4\\t%0, %1, #1\";
 453   "
 454   [(set_attr "conds" "clob")
 455    (set_attr "length" "10,14")]
 456 )
 457
 458 (define_insn "*thumb2_negscc"
 459   [(set (match_operand:SI 0 "s_register_operand" "=r")
 460         (neg:SI (match_operator 3 "arm_comparison_operator"
 461                  [(match_operand:SI 1 "s_register_operand" "r")
 462                   (match_operand:SI 2 "arm_rhs_operand" "rI")])))
 463    (clobber (reg:CC CC_REGNUM))]
 464   "TARGET_THUMB2"
 465   "*
 466   if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx)
 467     return \"asr\\t%0, %1, #31\";
 468
 469   if (GET_CODE (operands[3]) == NE)
 470     return \"subs\\t%0, %1, %2\;it\\tne\;mvnne\\t%0, #0\";
 471
 472   output_asm_insn (\"cmp\\t%1, %2\", operands);
 473   output_asm_insn (\"ite\\t%D3\", operands);
 474   output_asm_insn (\"mov%D3\\t%0, #0\", operands);
 475   return \"mvn%d3\\t%0, #0\";
 476   "
 477   [(set_attr "conds" "clob")
 478    (set_attr "length" "14")]
 479 )
 480
 481 (define_insn "*thumb2_movcond"
 482   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
 483         (if_then_else:SI
 484          (match_operator 5 "arm_comparison_operator"
 485           [(match_operand:SI 3 "s_register_operand" "r,r,r")
 486            (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
 487          (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
 488          (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
 489    (clobber (reg:CC CC_REGNUM))]
 490   "TARGET_THUMB2"
 491   "*
 492   if (GET_CODE (operands[5]) == LT
 493       && (operands[4] == const0_rtx))
 494     {
 495       if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
 496         {
 497           if (operands[2] == const0_rtx)
 498             return \"and\\t%0, %1, %3, asr #31\";
 499           return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\";
 500         }
 501       else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
 502         {
 503           if (operands[1] == const0_rtx)
 504             return \"bic\\t%0, %2, %3, asr #31\";
 505           return \"bics\\t%0, %2, %3, asr #32\;it\\tcs\;movcs\\t%0, %1\";
 506         }
 507       /* The only case that falls through to here is when both ops 1 & 2
 508          are constants.  */
 509     }
 510
 511   if (GET_CODE (operands[5]) == GE
 512       && (operands[4] == const0_rtx))
 513     {
 514       if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
 515         {
 516           if (operands[2] == const0_rtx)
 517             return \"bic\\t%0, %1, %3, asr #31\";
 518           return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\";
 519         }
 520       else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
 521         {
 522           if (operands[1] == const0_rtx)
 523             return \"and\\t%0, %2, %3, asr #31\";
 524           return \"ands\\t%0, %2, %3, asr #32\;it\tcc\;movcc\\t%0, %1\";
 525         }
 526       /* The only case that falls through to here is when both ops 1 & 2
 527          are constants.  */
 528     }
 529   if (GET_CODE (operands[4]) == CONST_INT
 530       && !const_ok_for_arm (INTVAL (operands[4])))
 531     output_asm_insn (\"cmn\\t%3, #%n4\", operands);
 532   else
 533     output_asm_insn (\"cmp\\t%3, %4\", operands);
 534   switch (which_alternative)
 535     {
 536     case 0:
 537       output_asm_insn (\"it\\t%D5\", operands);
 538       break;
 539     case 1:
 540       output_asm_insn (\"it\\t%d5\", operands);
 541       break;
 542     case 2:
 543       output_asm_insn (\"ite\\t%d5\", operands);
 544       break;
 545     default:
 546       abort();
 547     }
 548   if (which_alternative != 0)
 549     output_asm_insn (\"mov%d5\\t%0, %1\", operands);
 550   if (which_alternative != 1)
 551     output_asm_insn (\"mov%D5\\t%0, %2\", operands);
 552   return \"\";
 553   "
 554   [(set_attr "conds" "clob")
 555    (set_attr "length" "10,10,14")]
 556 )
 557
 558 ;; Zero and sign extension instructions.
 559
 560 (define_insn_and_split "*thumb2_zero_extendsidi2"
 561   [(set (match_operand:DI 0 "s_register_operand" "=r")
 562         (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
 563   "TARGET_THUMB2"
 564   "mov%?\\t%Q0, %1\;mov%?\\t%R0, #0"
 565   "&& reload_completed"
 566   [(set (match_dup 0) (match_dup 1))]
 567   "
 568   {
 569     rtx lo_part = gen_lowpart (SImode, operands[0]);
 570     if (!REG_P (lo_part) || REGNO (lo_part) != REGNO (operands[1]))
 571       emit_move_insn (lo_part, operands[1]);
 572     operands[0] = gen_highpart (SImode, operands[0]);
 573     operands[1] = const0_rtx;
 574   }
 575   "
 576   [(set_attr "length" "8")
 577    (set_attr "ce_count" "2")
 578    (set_attr "predicable" "yes")]
 579 )
 580
 581 (define_insn_and_split "*thumb2_zero_extendhidi2"
 582   [(set (match_operand:DI                 0 "s_register_operand"  "=r,r")
 583         (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
 584   "TARGET_THUMB2"
 585   "@
 586    uxth%?\\t%Q0, %1\;mov%?\\t%R0, #0
 587    ldr%(h%)\\t%Q0, %1\;mov%?\\t%R0, #0"
 588   "&& reload_completed"
 589   [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
 590    (set (match_dup 2) (match_dup 3))]
 591   "
 592   {
 593     operands[2] = gen_highpart (SImode, operands[0]);
 594     operands[0] = gen_lowpart (SImode, operands[0]);
 595     operands[3] = const0_rtx;
 596   }
 597   "
 598   [(set_attr "length" "8")
 599    (set_attr "ce_count" "2")
 600    (set_attr "predicable" "yes")
 601    (set_attr "type" "*,load_byte")
 602    (set_attr "pool_range" "*,4092")
 603    (set_attr "neg_pool_range" "*,250")]
 604 )
 605
 606 (define_insn_and_split "*thumb2_zero_extendqidi2"
 607   [(set (match_operand:DI                 0 "s_register_operand"  "=r,r")
 608         (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
 609   "TARGET_THUMB2"
 610   "@
 611    uxtb%?\\t%Q0, %1\;mov%?\\t%R0, #0
 612    ldr%(b%)\\t%Q0, %1\;mov%?\\t%R0, #0"
 613   "&& reload_completed"
 614   [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
 615    (set (match_dup 2) (match_dup 3))]
 616   "
 617   {
 618     operands[2] = gen_highpart (SImode, operands[0]);
 619     operands[0] = gen_lowpart (SImode, operands[0]);
 620     operands[3] = const0_rtx;
 621   }
 622   "
 623   [(set_attr "length" "8")
 624    (set_attr "ce_count" "2")
 625    (set_attr "predicable" "yes")
 626    (set_attr "type" "*,load_byte")
 627    (set_attr "pool_range" "*,4092")
 628    (set_attr "neg_pool_range" "*,250")]
 629 )
 630
 631 (define_insn_and_split "*thumb2_extendsidi2"
 632   [(set (match_operand:DI 0 "s_register_operand" "=r")
 633         (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
 634   "TARGET_THUMB2"
 635   "mov%?\\t%Q0, %1\;asr?\\t%R0, %1, #31"
 636   "&& reload_completed"
 637   [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))]
 638   {
 639     rtx lo_part = gen_lowpart (SImode, operands[0]);
 640
 641     if (!REG_P (lo_part) || REGNO (lo_part) != REGNO (operands[1]))
 642       emit_move_insn (lo_part, operands[1]);
 643     operands[0] = gen_highpart (SImode, operands[0]);
 644   }
 645   [(set_attr "length" "8")
 646    (set_attr "ce_count" "2")
 647    (set_attr "shift" "1")
 648    (set_attr "predicable" "yes")]
 649 )
 650
 651 (define_insn_and_split "*thumb2_extendhidi2"
 652   [(set (match_operand:DI                 0 "s_register_operand"  "=r,r")
 653         (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
 654   "TARGET_THUMB2"
 655   "@
 656    sxth%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31
 657    ldrsh%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31"
 658   "&& reload_completed"
 659   [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
 660    (set (match_dup 2) (ashiftrt:SI (match_dup 0) (const_int 31)))]
 661   "
 662   {
 663     operands[2] = gen_highpart (SImode, operands[0]);
 664     operands[0] = gen_lowpart (SImode, operands[0]);
 665   }
 666   "
 667   [(set_attr "length" "8")
 668    (set_attr "ce_count" "2")
 669    (set_attr "predicable" "yes")
 670    (set_attr "type" "*,load_byte")
 671    (set_attr "pool_range" "*,4092")
 672    (set_attr "neg_pool_range" "*,250")]
 673 )
 674
 675 (define_insn_and_split "*thumb2_extendqidi2"
 676   [(set (match_operand:DI                 0 "s_register_operand"  "=r,r")
 677         (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
 678   "TARGET_THUMB2"
 679   "@
 680    sxtb%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31
 681    ldrsb%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31"
 682   "&& reload_completed"
 683   [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
 684    (set (match_dup 2) (ashiftrt:SI (match_dup 0) (const_int 31)))]
 685   "
 686   {
 687     operands[2] = gen_highpart (SImode, operands[0]);
 688     operands[0] = gen_lowpart (SImode, operands[0]);
 689   }
 690   "
 691   [(set_attr "length" "8")
 692    (set_attr "ce_count" "2")
 693    (set_attr "predicable" "yes")
 694    (set_attr "type" "*,load_byte")
 695    (set_attr "pool_range" "*,4092")
 696    (set_attr "neg_pool_range" "*,250")]
 697 )
 698
 699 ;; All supported Thumb2 implementations are armv6, so only that case is
 700 ;; provided.
 701 (define_insn "*thumb2_extendqisi_v6"
 702   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 703         (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
 704   "TARGET_THUMB2 && arm_arch6"
 705   "@
 706    sxtb%?\\t%0, %1
 707    ldr%(sb%)\\t%0, %1"
 708   [(set_attr "type" "alu_shift,load_byte")
 709    (set_attr "predicable" "yes")
 710    (set_attr "pool_range" "*,4096")
 711    (set_attr "neg_pool_range" "*,250")]
 712 )
 713
 714 (define_insn "*thumb2_zero_extendhisi2_v6"
 715   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 716         (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
 717   "TARGET_THUMB2 && arm_arch6"
 718   "@
 719    uxth%?\\t%0, %1
 720    ldr%(h%)\\t%0, %1"
 721   [(set_attr "type" "alu_shift,load_byte")
 722    (set_attr "predicable" "yes")
 723    (set_attr "pool_range" "*,4096")
 724    (set_attr "neg_pool_range" "*,250")]
 725 )
 726
 727 (define_insn "thumb2_zero_extendqisi2_v6"
 728   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 729         (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
 730   "TARGET_THUMB2 && arm_arch6"
 731   "@
 732    uxtb%(%)\\t%0, %1
 733    ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
 734   [(set_attr "type" "alu_shift,load_byte")
 735    (set_attr "predicable" "yes")
 736    (set_attr "pool_range" "*,4096")
 737    (set_attr "neg_pool_range" "*,250")]
 738 )
 739
 740 (define_insn "thumb2_casesi_internal"
 741   [(parallel [(set (pc)
 742                (if_then_else
 743                 (leu (match_operand:SI 0 "s_register_operand" "r")
 744                      (match_operand:SI 1 "arm_rhs_operand" "rI"))
 745                 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
 746                                  (label_ref (match_operand 2 "" ""))))
 747                 (label_ref (match_operand 3 "" ""))))
 748               (clobber (reg:CC CC_REGNUM))
 749               (clobber (match_scratch:SI 4 "=&r"))
 750               (use (label_ref (match_dup 2)))])]
 751   "TARGET_THUMB2 && !flag_pic"
 752   "* return thumb2_output_casesi(operands);"
 753   [(set_attr "conds" "clob")
 754    (set_attr "length" "16")]
 755 )
 756
 757 (define_insn "thumb2_casesi_internal_pic"
 758   [(parallel [(set (pc)
 759                (if_then_else
 760                 (leu (match_operand:SI 0 "s_register_operand" "r")
 761                      (match_operand:SI 1 "arm_rhs_operand" "rI"))
 762                 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
 763                                  (label_ref (match_operand 2 "" ""))))
 764                 (label_ref (match_operand 3 "" ""))))
 765               (clobber (reg:CC CC_REGNUM))
 766               (clobber (match_scratch:SI 4 "=&r"))
 767               (clobber (match_scratch:SI 5 "=r"))
 768               (use (label_ref (match_dup 2)))])]
 769   "TARGET_THUMB2 && flag_pic"
 770   "* return thumb2_output_casesi(operands);"
 771   [(set_attr "conds" "clob")
 772    (set_attr "length" "20")]
 773 )
 774
 775 ;; Note: this is not predicable, to avoid issues with linker-generated
 776 ;; interworking stubs.
 777 (define_insn "*thumb2_return"
 778   [(return)]
 779   "TARGET_THUMB2 && USE_RETURN_INSN (FALSE)"
 780   "*
 781   {
 782     return output_return_instruction (const_true_rtx, TRUE, FALSE);
 783   }"
 784   [(set_attr "type" "load1")
 785    (set_attr "length" "12")]
 786 )
 787
 788 (define_insn_and_split "thumb2_eh_return"
 789   [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
 790                     VUNSPEC_EH_RETURN)
 791    (clobber (match_scratch:SI 1 "=&r"))]
 792   "TARGET_THUMB2"
 793   "#"
 794   "&& reload_completed"
 795   [(const_int 0)]
 796   "
 797   {
 798     thumb_set_return_address (operands[0], operands[1]);
 799     DONE;
 800   }"
 801 )
 802
 803 (define_insn "*thumb2_alusi3_short"
 804   [(set (match_operand:SI          0 "s_register_operand" "=l")
 805         (match_operator:SI 3 "thumb_16bit_operator"
 806          [(match_operand:SI 1 "s_register_operand" "0")
 807           (match_operand:SI 2 "s_register_operand" "l")]))
 808    (clobber (reg:CC CC_REGNUM))]
 809   "TARGET_THUMB2 && reload_completed
 810    && GET_CODE(operands[3]) != PLUS
 811    && GET_CODE(operands[3]) != MINUS"
 812   "%I3%!\\t%0, %1, %2"
 813   [(set_attr "predicable" "yes")
 814    (set_attr "length" "2")]
 815 )
 816
 817 ;; Similarly for 16-bit shift instructions
 818 ;; There is no 16-bit rotate by immediate instruction.
 819 (define_peephole2
 820   [(set (match_operand:SI   0 "low_register_operand" "")
 821         (match_operator:SI  3 "shift_operator"
 822          [(match_operand:SI 1 "low_register_operand" "")
 823           (match_operand:SI 2 "low_reg_or_int_operand" "")]))]
 824   "TARGET_THUMB2
 825    && peep2_regno_dead_p(0, CC_REGNUM)
 826    && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
 827        || REG_P(operands[2]))"
 828   [(parallel
 829     [(set (match_dup 0)
 830           (match_op_dup 3
 831            [(match_dup 1)
 832             (match_dup 2)]))
 833      (clobber (reg:CC CC_REGNUM))])]
 834   ""
 835 )
 836
 837 (define_insn "*thumb2_shiftsi3_short"
 838   [(set (match_operand:SI   0 "low_register_operand" "=l")
 839         (match_operator:SI  3 "shift_operator"
 840          [(match_operand:SI 1 "low_register_operand"  "l")
 841           (match_operand:SI 2 "low_reg_or_int_operand" "lM")]))
 842    (clobber (reg:CC CC_REGNUM))]
 843   "TARGET_THUMB2 && reload_completed
 844    && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
 845        || REG_P(operands[2]))"
 846   "* return arm_output_shift(operands, 2);"
 847   [(set_attr "predicable" "yes")
 848    (set_attr "shift" "1")
 849    (set_attr "length" "2")
 850    (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
 851                       (const_string "alu_shift")
 852                       (const_string "alu_shift_reg")))]
 853 )
 854
 855 ;; 16-bit load immediate
 856 (define_peephole2
 857   [(set (match_operand:QHSI 0 "low_register_operand" "")
 858         (match_operand:QHSI 1 "const_int_operand" ""))]
 859   "TARGET_THUMB2
 860    && peep2_regno_dead_p(0, CC_REGNUM)
 861    && (unsigned HOST_WIDE_INT) INTVAL(operands[1]) < 256"
 862   [(parallel
 863     [(set (match_dup 0)
 864           (match_dup 1))
 865      (clobber (reg:CC CC_REGNUM))])]
 866   ""
 867 )
 868
 869 (define_insn "*thumb2_mov<mode>_shortim"
 870   [(set (match_operand:QHSI 0 "low_register_operand" "=l")
 871         (match_operand:QHSI 1 "const_int_operand" "I"))
 872    (clobber (reg:CC CC_REGNUM))]
 873   "TARGET_THUMB2 && reload_completed"
 874   "mov%!\t%0, %1"
 875   [(set_attr "predicable" "yes")
 876    (set_attr "length" "2")]
 877 )
 878
 879 ;; 16-bit add/sub immediate
 880 (define_peephole2
 881   [(set (match_operand:SI 0 "low_register_operand" "")
 882         (plus:SI (match_operand:SI 1 "low_register_operand" "")
 883                  (match_operand:SI 2 "const_int_operand" "")))]
 884   "TARGET_THUMB2
 885    && peep2_regno_dead_p(0, CC_REGNUM)
 886    && ((rtx_equal_p(operands[0], operands[1])
 887         && INTVAL(operands[2]) > -256 && INTVAL(operands[2]) < 256)
 888        || (INTVAL(operands[2]) > -8 && INTVAL(operands[2]) < 8))"
 889   [(parallel
 890     [(set (match_dup 0)
 891           (plus:SI (match_dup 1)
 892                    (match_dup 2)))
 893      (clobber (reg:CC CC_REGNUM))])]
 894   ""
 895 )
 896
 897 (define_insn "*thumb2_addsi_short"
 898   [(set (match_operand:SI 0 "low_register_operand" "=l,l")
 899         (plus:SI (match_operand:SI 1 "low_register_operand" "l,0")
 900                  (match_operand:SI 2 "low_reg_or_int_operand" "lPt,Ps")))
 901    (clobber (reg:CC CC_REGNUM))]
 902   "TARGET_THUMB2 && reload_completed"
 903   "*
 904     HOST_WIDE_INT val;
 905
 906     if (GET_CODE (operands[2]) == CONST_INT)
 907       val = INTVAL(operands[2]);
 908     else
 909       val = 0;
 910
 911     /* We prefer eg. subs rn, rn, #1 over adds rn, rn, #0xffffffff.  */
 912     if (val < 0 && const_ok_for_arm(ARM_SIGN_EXTEND (-val)))
 913       return \"sub%!\\t%0, %1, #%n2\";
 914     else
 915       return \"add%!\\t%0, %1, %2\";
 916   "
 917   [(set_attr "predicable" "yes")
 918    (set_attr "length" "2")]
 919 )
 920
 921 (define_insn "divsi3"
 922   [(set (match_operand:SI         0 "s_register_operand" "=r")
 923         (div:SI (match_operand:SI 1 "s_register_operand"  "r")
 924                 (match_operand:SI 2 "s_register_operand"  "r")))]
 925   "TARGET_THUMB2 && arm_arch_hwdiv"
 926   "sdiv%?\t%0, %1, %2"
 927   [(set_attr "predicable" "yes")
 928    (set_attr "insn" "sdiv")]
 929 )
 930
 931 (define_insn "udivsi3"
 932   [(set (match_operand:SI          0 "s_register_operand" "=r")
 933         (udiv:SI (match_operand:SI 1 "s_register_operand"  "r")
 934                  (match_operand:SI 2 "s_register_operand"  "r")))]
 935   "TARGET_THUMB2 && arm_arch_hwdiv"
 936   "udiv%?\t%0, %1, %2"
 937   [(set_attr "predicable" "yes")
 938    (set_attr "insn" "udiv")]
 939 )
 940
 941 (define_insn "*thumb2_subsi_short"
 942   [(set (match_operand:SI 0 "low_register_operand" "=l")
 943         (minus:SI (match_operand:SI 1 "low_register_operand" "l")
 944                   (match_operand:SI 2 "low_register_operand" "l")))
 945    (clobber (reg:CC CC_REGNUM))]
 946   "TARGET_THUMB2 && reload_completed"
 947   "sub%!\\t%0, %1, %2"
 948   [(set_attr "predicable" "yes")
 949    (set_attr "length" "2")]
 950 )
 951
 952 (define_peephole2
 953   [(set (match_operand:CC 0 "cc_register" "")
 954         (compare:CC (match_operand:SI 1 "low_register_operand" "")
 955                     (match_operand:SI 2 "const_int_operand" "")))]
 956   "TARGET_THUMB2
 957    && peep2_reg_dead_p (1, operands[1])
 958    && satisfies_constraint_Pw (operands[2])"
 959   [(parallel
 960     [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
 961      (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 3)))])]
 962   "operands[3] = GEN_INT (- INTVAL (operands[2]));"
 963 )
 964
 965 (define_peephole2
 966   [(match_scratch:SI 3 "l")
 967    (set (match_operand:CC 0 "cc_register" "")
 968         (compare:CC (match_operand:SI 1 "low_register_operand" "")
 969                     (match_operand:SI 2 "const_int_operand" "")))]
 970   "TARGET_THUMB2
 971    && satisfies_constraint_Px (operands[2])"
 972   [(parallel
 973     [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
 974      (set (match_dup 3) (plus:SI (match_dup 1) (match_dup 4)))])]
 975   "operands[4] = GEN_INT (- INTVAL (operands[2]));"
 976 )
 977
 978 (define_insn "*thumb2_addsi3_compare0"
 979   [(set (reg:CC_NOOV CC_REGNUM)
 980         (compare:CC_NOOV
 981           (plus:SI (match_operand:SI 1 "s_register_operand" "l,  0, r")
 982                    (match_operand:SI 2 "arm_add_operand"    "lPt,Ps,rIL"))
 983           (const_int 0)))
 984    (set (match_operand:SI 0 "s_register_operand" "=l,l,r")
 985         (plus:SI (match_dup 1) (match_dup 2)))]
 986   "TARGET_THUMB2"
 987   "*
 988     HOST_WIDE_INT val;
 989
 990     if (GET_CODE (operands[2]) == CONST_INT)
 991       val = INTVAL (operands[2]);
 992     else
 993       val = 0;
 994
 995     if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
 996       return \"subs\\t%0, %1, #%n2\";
 997     else
 998       return \"adds\\t%0, %1, %2\";
 999   "
1000   [(set_attr "conds" "set")
1001    (set_attr "length" "2,2,4")]
1002 )
1003
1004 (define_insn "*thumb2_addsi3_compare0_scratch"
1005   [(set (reg:CC_NOOV CC_REGNUM)
1006         (compare:CC_NOOV
1007           (plus:SI (match_operand:SI 0 "s_register_operand" "l,  r")
1008                    (match_operand:SI 1 "arm_add_operand"    "lPv,rIL"))
1009           (const_int 0)))]
1010   "TARGET_THUMB2"
1011   "*
1012     HOST_WIDE_INT val;
1013
1014     if (GET_CODE (operands[1]) == CONST_INT)
1015       val = INTVAL (operands[1]);
1016     else
1017       val = 0;
1018
1019     if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
1020       return \"cmp\\t%0, #%n1\";
1021     else
1022       return \"cmn\\t%0, %1\";
1023   "
1024   [(set_attr "conds" "set")
1025    (set_attr "length" "2,4")]
1026 )
1027
1028 ;; 16-bit encodings of "muls" and "mul<c>".  We only use these when
1029 ;; optimizing for size since "muls" is slow on all known
1030 ;; implementations and since "mul<c>" will be generated by
1031 ;; "*arm_mulsi3_v6" anyhow.  The assembler will use a 16-bit encoding
1032 ;; for "mul<c>" whenever possible anyhow.
1033 (define_peephole2
1034   [(set (match_operand:SI 0 "low_register_operand" "")
1035         (mult:SI (match_operand:SI 1 "low_register_operand" "")
1036                  (match_dup 0)))]
1037   "TARGET_THUMB2 && optimize_size && peep2_regno_dead_p (0, CC_REGNUM)"
1038   [(parallel
1039     [(set (match_dup 0)
1040            (mult:SI (match_dup 0) (match_dup 1)))
1041      (clobber (reg:CC CC_REGNUM))])]
1042   ""
1043 )
1044
1045 (define_peephole2
1046   [(set (match_operand:SI 0 "low_register_operand" "")
1047         (mult:SI (match_dup 0)
1048                  (match_operand:SI 1 "low_register_operand" "")))]
1049   "TARGET_THUMB2 && optimize_size && peep2_regno_dead_p (0, CC_REGNUM)"
1050   [(parallel
1051     [(set (match_dup 0)
1052            (mult:SI (match_dup 0) (match_dup 1)))
1053      (clobber (reg:CC CC_REGNUM))])]
1054   ""
1055 )
1056
1057 (define_insn "*thumb2_mulsi_short"
1058   [(set (match_operand:SI 0 "low_register_operand" "=l")
1059         (mult:SI (match_operand:SI 1 "low_register_operand" "%0")
1060                  (match_operand:SI 2 "low_register_operand" "l")))
1061    (clobber (reg:CC CC_REGNUM))]
1062   "TARGET_THUMB2 && optimize_size && reload_completed"
1063   "mul%!\\t%0, %2, %0"
1064   [(set_attr "predicable" "yes")
1065    (set_attr "length" "2")
1066    (set_attr "insn" "muls")])
1067
1068 (define_insn "*thumb2_mulsi_short_compare0"
1069   [(set (reg:CC_NOOV CC_REGNUM)
1070         (compare:CC_NOOV
1071          (mult:SI (match_operand:SI 1 "register_operand" "%0")
1072                   (match_operand:SI 2 "register_operand" "l"))
1073          (const_int 0)))
1074    (set (match_operand:SI 0 "register_operand" "=l")
1075         (mult:SI (match_dup 1) (match_dup 2)))]
1076   "TARGET_THUMB2 && optimize_size"
1077   "muls\\t%0, %2, %0"
1078   [(set_attr "length" "2")
1079    (set_attr "insn" "muls")])
1080
1081 (define_insn "*thumb2_mulsi_short_compare0_scratch"
1082   [(set (reg:CC_NOOV CC_REGNUM)
1083         (compare:CC_NOOV
1084          (mult:SI (match_operand:SI 1 "register_operand" "%0")
1085                   (match_operand:SI 2 "register_operand" "l"))
1086          (const_int 0)))
1087    (clobber (match_scratch:SI 0 "=l"))]
1088   "TARGET_THUMB2 && optimize_size"
1089   "muls\\t%0, %2, %0"
1090   [(set_attr "length" "2")
1091    (set_attr "insn" "muls")])
1092
1093 (define_insn "*thumb2_cbz"
1094   [(set (pc) (if_then_else
1095               (eq (match_operand:SI 0 "s_register_operand" "l,?r")
1096                   (const_int 0))
1097               (label_ref (match_operand 1 "" ""))
1098               (pc)))
1099    (clobber (reg:CC CC_REGNUM))]
1100   "TARGET_THUMB2"
1101   "*
1102   if (get_attr_length (insn) == 2)
1103     return \"cbz\\t%0, %l1\";
1104   else
1105     return \"cmp\\t%0, #0\;beq\\t%l1\";
1106   "
1107   [(set (attr "length")
1108         (if_then_else
1109             (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1110                  (le (minus (match_dup 1) (pc)) (const_int 128))
1111                  (eq (symbol_ref ("which_alternative")) (const_int 0)))
1112             (const_int 2)
1113             (const_int 8)))]
1114 )
1115
1116 (define_insn "*thumb2_cbnz"
1117   [(set (pc) (if_then_else
1118               (ne (match_operand:SI 0 "s_register_operand" "l,?r")
1119                   (const_int 0))
1120               (label_ref (match_operand 1 "" ""))
1121               (pc)))
1122    (clobber (reg:CC CC_REGNUM))]
1123   "TARGET_THUMB2"
1124   "*
1125   if (get_attr_length (insn) == 2)
1126     return \"cbnz\\t%0, %l1\";
1127   else
1128     return \"cmp\\t%0, #0\;bne\\t%l1\";
1129   "
1130   [(set (attr "length")
1131         (if_then_else
1132             (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1133                  (le (minus (match_dup 1) (pc)) (const_int 128))
1134                  (eq (symbol_ref ("which_alternative")) (const_int 0)))
1135             (const_int 2)
1136             (const_int 8)))]
1137 )
1138
1139 ;; 16-bit complement
1140 (define_peephole2
1141   [(set (match_operand:SI 0 "low_register_operand" "")
1142         (not:SI (match_operand:SI 1 "low_register_operand" "")))]
1143   "TARGET_THUMB2
1144    && peep2_regno_dead_p(0, CC_REGNUM)"
1145   [(parallel
1146     [(set (match_dup 0)
1147           (not:SI (match_dup 1)))
1148      (clobber (reg:CC CC_REGNUM))])]
1149   ""
1150 )
1151
1152 (define_insn "*thumb2_one_cmplsi2_short"
1153   [(set (match_operand:SI 0 "low_register_operand" "=l")
1154         (not:SI (match_operand:SI 1 "low_register_operand" "l")))
1155    (clobber (reg:CC CC_REGNUM))]
1156   "TARGET_THUMB2 && reload_completed"
1157   "mvn%!\t%0, %1"
1158   [(set_attr "predicable" "yes")
1159    (set_attr "length" "2")]
1160 )
1161
1162 ;; 16-bit negate
1163 (define_peephole2
1164   [(set (match_operand:SI 0 "low_register_operand" "")
1165         (neg:SI (match_operand:SI 1 "low_register_operand" "")))]
1166   "TARGET_THUMB2
1167    && peep2_regno_dead_p(0, CC_REGNUM)"
1168   [(parallel
1169     [(set (match_dup 0)
1170           (neg:SI (match_dup 1)))
1171      (clobber (reg:CC CC_REGNUM))])]
1172   ""
1173 )
1174
1175 (define_insn "*thumb2_negsi2_short"
1176   [(set (match_operand:SI 0 "low_register_operand" "=l")
1177         (neg:SI (match_operand:SI 1 "low_register_operand" "l")))
1178    (clobber (reg:CC CC_REGNUM))]
1179   "TARGET_THUMB2 && reload_completed"
1180   "neg%!\t%0, %1"
1181   [(set_attr "predicable" "yes")
1182    (set_attr "length" "2")]
1183 )
1184
1185 (define_insn "*orsi_notsi_si"
1186   [(set (match_operand:SI 0 "s_register_operand" "=r")
1187         (ior:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
1188                 (match_operand:SI 1 "s_register_operand" "r")))]
1189   "TARGET_THUMB2"
1190   "orn%?\\t%0, %1, %2"
1191   [(set_attr "predicable" "yes")]
1192 )
1193
1194 (define_insn "*orsi_not_shiftsi_si"
1195   [(set (match_operand:SI 0 "s_register_operand" "=r")
1196         (ior:SI (not:SI (match_operator:SI 4 "shift_operator"
1197                          [(match_operand:SI 2 "s_register_operand" "r")
1198                           (match_operand:SI 3 "const_int_operand" "M")]))
1199                 (match_operand:SI 1 "s_register_operand" "r")))]
1200   "TARGET_THUMB2"
1201   "orn%?\\t%0, %1, %2%S4"
1202   [(set_attr "predicable" "yes")
1203    (set_attr "shift" "2")
1204    (set_attr "type" "alu_shift")]
1205 )
1206
1207 (define_peephole2
1208   [(set (match_operand:CC_NOOV 0 "cc_register" "")
1209         (compare:CC_NOOV (zero_extract:SI
1210                           (match_operand:SI 1 "low_register_operand" "")
1211                           (const_int 1)
1212                           (match_operand:SI 2 "const_int_operand" ""))
1213                          (const_int 0)))
1214    (match_scratch:SI 3 "l")
1215    (set (pc)
1216         (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
1217                        [(match_dup 0) (const_int 0)])
1218                       (match_operand 5 "" "")
1219                       (match_operand 6 "" "")))]
1220   "TARGET_THUMB2
1221    && (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32)"
1222   [(parallel [(set (match_dup 0)
1223                    (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
1224                                     (const_int 0)))
1225               (clobber (match_dup 3))])
1226    (set (pc)
1227         (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1228                       (match_dup 5) (match_dup 6)))]
1229   "
1230   operands[2] = GEN_INT (31 - INTVAL (operands[2]));
1231   operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? LT : GE,
1232                                 VOIDmode, operands[0], const0_rtx);
1233   ")
1234
1235 (define_peephole2
1236   [(set (match_operand:CC_NOOV 0 "cc_register" "")
1237         (compare:CC_NOOV (zero_extract:SI
1238                           (match_operand:SI 1 "low_register_operand" "")
1239                           (match_operand:SI 2 "const_int_operand" "")
1240                           (const_int 0))
1241                          (const_int 0)))
1242    (match_scratch:SI 3 "l")
1243    (set (pc)
1244         (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
1245                        [(match_dup 0) (const_int 0)])
1246                       (match_operand 5 "" "")
1247                       (match_operand 6 "" "")))]
1248   "TARGET_THUMB2
1249    && (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 32)"
1250   [(parallel [(set (match_dup 0)
1251                    (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
1252                                     (const_int 0)))
1253               (clobber (match_dup 3))])
1254    (set (pc)
1255         (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1256                       (match_dup 5) (match_dup 6)))]
1257   "
1258   operands[2] = GEN_INT (32 - INTVAL (operands[2]));
1259   ")