1 ;; ARM Thumb-2 Machine Description
2 ;; Copyright (C) 2007, 2008 Free Software Foundation, Inc.
3 ;; Written by CodeSourcery, LLC.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>. */
21 ;; Note: Thumb-2 is the variant of the Thumb architecture that adds
22 ;; 32-bit encodings of [almost all of] the Arm instruction set.
23 ;; Some old documents refer to the relatively minor interworking
24 ;; changes made in armv5t as "thumb2". These are considered part
25 ;; the 16-bit Thumb-1 instruction set.
27 (define_insn "*thumb2_incscc"
28 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
29 (plus:SI (match_operator:SI 2 "arm_comparison_operator"
30 [(match_operand:CC 3 "cc_register" "") (const_int 0)])
31 (match_operand:SI 1 "s_register_operand" "0,?r")))]
34 it\\t%d2\;add%d2\\t%0, %1, #1
35 ite\\t%D2\;mov%D2\\t%0, %1\;add%d2\\t%0, %1, #1"
36 [(set_attr "conds" "use")
37 (set_attr "length" "6,10")]
40 (define_insn "*thumb2_decscc"
41 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
42 (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r")
43 (match_operator:SI 2 "arm_comparison_operator"
44 [(match_operand 3 "cc_register" "") (const_int 0)])))]
47 it\\t%d2\;sub%d2\\t%0, %1, #1
48 ite\\t%D2\;mov%D2\\t%0, %1\;sub%d2\\t%0, %1, #1"
49 [(set_attr "conds" "use")
50 (set_attr "length" "6,10")]
53 ;; Thumb-2 only allows shift by constant on data processing instructions
54 (define_insn "*thumb_andsi_not_shiftsi_si"
55 [(set (match_operand:SI 0 "s_register_operand" "=r")
56 (and:SI (not:SI (match_operator:SI 4 "shift_operator"
57 [(match_operand:SI 2 "s_register_operand" "r")
58 (match_operand:SI 3 "const_int_operand" "M")]))
59 (match_operand:SI 1 "s_register_operand" "r")))]
61 "bic%?\\t%0, %1, %2%S4"
62 [(set_attr "predicable" "yes")
63 (set_attr "shift" "2")
64 (set_attr "type" "alu_shift")]
67 (define_insn "*thumb2_smaxsi3"
68 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
69 (smax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
70 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
71 (clobber (reg:CC CC_REGNUM))]
74 cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2
75 cmp\\t%1, %2\;it\\tge\;movge\\t%0, %1
76 cmp\\t%1, %2\;ite\\tge\;movge\\t%0, %1\;movlt\\t%0, %2"
77 [(set_attr "conds" "clob")
78 (set_attr "length" "10,10,14")]
81 (define_insn "*thumb2_sminsi3"
82 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
83 (smin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
84 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
85 (clobber (reg:CC CC_REGNUM))]
88 cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2
89 cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %1
90 cmp\\t%1, %2\;ite\\tlt\;movlt\\t%0, %1\;movge\\t%0, %2"
91 [(set_attr "conds" "clob")
92 (set_attr "length" "10,10,14")]
95 (define_insn "*thumb32_umaxsi3"
96 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
97 (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
98 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
99 (clobber (reg:CC CC_REGNUM))]
102 cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2
103 cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %1
104 cmp\\t%1, %2\;ite\\tcs\;movcs\\t%0, %1\;movcc\\t%0, %2"
105 [(set_attr "conds" "clob")
106 (set_attr "length" "10,10,14")]
109 (define_insn "*thumb2_uminsi3"
110 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
111 (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
112 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
113 (clobber (reg:CC CC_REGNUM))]
116 cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2
117 cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %1
118 cmp\\t%1, %2\;ite\\tcc\;movcc\\t%0, %1\;movcs\\t%0, %2"
119 [(set_attr "conds" "clob")
120 (set_attr "length" "10,10,14")]
123 (define_insn "*thumb2_notsi_shiftsi"
124 [(set (match_operand:SI 0 "s_register_operand" "=r")
125 (not:SI (match_operator:SI 3 "shift_operator"
126 [(match_operand:SI 1 "s_register_operand" "r")
127 (match_operand:SI 2 "const_int_operand" "M")])))]
130 [(set_attr "predicable" "yes")
131 (set_attr "shift" "1")
132 (set_attr "type" "alu_shift")]
135 (define_insn "*thumb2_notsi_shiftsi_compare0"
136 [(set (reg:CC_NOOV CC_REGNUM)
137 (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
138 [(match_operand:SI 1 "s_register_operand" "r")
139 (match_operand:SI 2 "const_int_operand" "M")]))
141 (set (match_operand:SI 0 "s_register_operand" "=r")
142 (not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))]
145 [(set_attr "conds" "set")
146 (set_attr "shift" "1")
147 (set_attr "type" "alu_shift")]
150 (define_insn "*thumb2_not_shiftsi_compare0_scratch"
151 [(set (reg:CC_NOOV CC_REGNUM)
152 (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
153 [(match_operand:SI 1 "s_register_operand" "r")
154 (match_operand:SI 2 "const_int_operand" "M")]))
156 (clobber (match_scratch:SI 0 "=r"))]
159 [(set_attr "conds" "set")
160 (set_attr "shift" "1")
161 (set_attr "type" "alu_shift")]
164 ;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
165 (define_insn "*thumb2_negdi2"
166 [(set (match_operand:DI 0 "s_register_operand" "=&r,r")
167 (neg:DI (match_operand:DI 1 "s_register_operand" "?r,0")))
168 (clobber (reg:CC CC_REGNUM))]
170 "negs\\t%Q0, %Q1\;sbc\\t%R0, %R1, %R1, lsl #1"
171 [(set_attr "conds" "clob")
172 (set_attr "length" "8")]
175 (define_insn "*thumb2_abssi2"
176 [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
177 (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
178 (clobber (reg:CC CC_REGNUM))]
181 cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
182 eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31"
183 [(set_attr "conds" "clob,*")
184 (set_attr "shift" "1")
185 ;; predicable can't be set based on the variant, so left as no
186 (set_attr "length" "10,8")]
189 (define_insn "*thumb2_neg_abssi2"
190 [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
191 (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
192 (clobber (reg:CC CC_REGNUM))]
195 cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
196 eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31"
197 [(set_attr "conds" "clob,*")
198 (set_attr "shift" "1")
199 ;; predicable can't be set based on the variant, so left as no
200 (set_attr "length" "10,8")]
203 (define_insn "*thumb2_movdi"
204 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m")
205 (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r"))]
207 && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP))
210 switch (which_alternative)
217 return output_move_double (operands);
220 [(set_attr "length" "8,12,16,8,8")
221 (set_attr "type" "*,*,*,load2,store2")
222 (set_attr "pool_range" "*,*,*,4096,*")
223 (set_attr "neg_pool_range" "*,*,*,0,*")]
226 (define_insn "*thumb2_movsi_insn"
227 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m")
228 (match_operand:SI 1 "general_operand" "rk ,I,K,N,mi,rk"))]
229 "TARGET_THUMB2 && ! TARGET_IWMMXT
230 && !(TARGET_HARD_FLOAT && TARGET_VFP)
231 && ( register_operand (operands[0], SImode)
232 || register_operand (operands[1], SImode))"
240 [(set_attr "type" "*,*,*,*,load1,store1")
241 (set_attr "predicable" "yes")
242 (set_attr "pool_range" "*,*,*,*,4096,*")
243 (set_attr "neg_pool_range" "*,*,*,*,0,*")]
246 ;; ??? We can probably do better with thumb2
247 (define_insn "pic_load_addr_thumb2"
248 [(set (match_operand:SI 0 "s_register_operand" "=r")
249 (unspec:SI [(match_operand:SI 1 "" "mX")] UNSPEC_PIC_SYM))]
250 "TARGET_THUMB2 && flag_pic"
252 [(set_attr "type" "load1")
253 (set_attr "pool_range" "4096")
254 (set_attr "neg_pool_range" "0")]
257 ;; Set reg to the address of this instruction plus four. The low two
258 ;; bits of the PC are always read as zero, so ensure the instructions is
260 (define_insn "pic_load_dot_plus_four"
261 [(set (match_operand:SI 0 "register_operand" "=r")
262 (unspec:SI [(const_int 4)
263 (match_operand 1 "" "")]
267 assemble_align(BITS_PER_WORD);
268 (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
269 INTVAL (operands[1]));
270 /* We use adr because some buggy gas assemble add r8, pc, #0
271 to add.w r8, pc, #0, not addw r8, pc, #0. */
272 asm_fprintf (asm_out_file, \"\\tadr\\t%r, %LLPIC%d + 4\\n\",
273 REGNO(operands[0]), (int)INTVAL (operands[1]));
276 [(set_attr "length" "6")]
279 ;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
280 ;; of the messiness associated with the ARM patterns.
281 (define_insn "*thumb2_movhi_insn"
282 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
283 (match_operand:HI 1 "general_operand" "rI,n,r,m"))]
286 mov%?\\t%0, %1\\t%@ movhi
287 movw%?\\t%0, %L1\\t%@ movhi
288 str%(h%)\\t%1, %0\\t%@ movhi
289 ldr%(h%)\\t%0, %1\\t%@ movhi"
290 [(set_attr "type" "*,*,store1,load1")
291 (set_attr "predicable" "yes")
292 (set_attr "pool_range" "*,*,*,4096")
293 (set_attr "neg_pool_range" "*,*,*,250")]
296 (define_insn "*thumb2_movsf_soft_insn"
297 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
298 (match_operand:SF 1 "general_operand" "r,mE,r"))]
301 && (GET_CODE (operands[0]) != MEM
302 || register_operand (operands[1], SFmode))"
305 ldr%?\\t%0, %1\\t%@ float
306 str%?\\t%1, %0\\t%@ float"
307 [(set_attr "predicable" "yes")
308 (set_attr "type" "*,load1,store1")
309 (set_attr "pool_range" "*,4096,*")
310 (set_attr "neg_pool_range" "*,0,*")]
313 (define_insn "*thumb2_movdf_soft_insn"
314 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,r,r,m")
315 (match_operand:DF 1 "soft_df_operand" "rDa,Db,Dc,mF,r"))]
316 "TARGET_THUMB2 && TARGET_SOFT_FLOAT
317 && ( register_operand (operands[0], DFmode)
318 || register_operand (operands[1], DFmode))"
320 switch (which_alternative)
327 return output_move_double (operands);
330 [(set_attr "length" "8,12,16,8,8")
331 (set_attr "type" "*,*,*,load2,store2")
332 (set_attr "pool_range" "1020")
333 (set_attr "neg_pool_range" "0")]
336 (define_insn "*thumb2_cmpsi_shiftsi"
337 [(set (reg:CC CC_REGNUM)
338 (compare:CC (match_operand:SI 0 "s_register_operand" "r")
339 (match_operator:SI 3 "shift_operator"
340 [(match_operand:SI 1 "s_register_operand" "r")
341 (match_operand:SI 2 "const_int_operand" "M")])))]
344 [(set_attr "conds" "set")
345 (set_attr "shift" "1")
346 (set_attr "type" "alu_shift")]
349 (define_insn "*thumb2_cmpsi_shiftsi_swp"
350 [(set (reg:CC_SWP CC_REGNUM)
351 (compare:CC_SWP (match_operator:SI 3 "shift_operator"
352 [(match_operand:SI 1 "s_register_operand" "r")
353 (match_operand:SI 2 "const_int_operand" "M")])
354 (match_operand:SI 0 "s_register_operand" "r")))]
357 [(set_attr "conds" "set")
358 (set_attr "shift" "1")
359 (set_attr "type" "alu_shift")]
362 (define_insn "*thumb2_cmpsi_neg_shiftsi"
363 [(set (reg:CC CC_REGNUM)
364 (compare:CC (match_operand:SI 0 "s_register_operand" "r")
365 (neg:SI (match_operator:SI 3 "shift_operator"
366 [(match_operand:SI 1 "s_register_operand" "r")
367 (match_operand:SI 2 "const_int_operand" "M")]))))]
370 [(set_attr "conds" "set")
371 (set_attr "shift" "1")
372 (set_attr "type" "alu_shift")]
375 (define_insn "*thumb2_mov_scc"
376 [(set (match_operand:SI 0 "s_register_operand" "=r")
377 (match_operator:SI 1 "arm_comparison_operator"
378 [(match_operand 2 "cc_register" "") (const_int 0)]))]
380 "ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
381 [(set_attr "conds" "use")
382 (set_attr "length" "10")]
385 (define_insn "*thumb2_mov_negscc"
386 [(set (match_operand:SI 0 "s_register_operand" "=r")
387 (neg:SI (match_operator:SI 1 "arm_comparison_operator"
388 [(match_operand 2 "cc_register" "") (const_int 0)])))]
390 "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
391 [(set_attr "conds" "use")
392 (set_attr "length" "10")]
395 (define_insn "*thumb2_mov_notscc"
396 [(set (match_operand:SI 0 "s_register_operand" "=r")
397 (not:SI (match_operator:SI 1 "arm_comparison_operator"
398 [(match_operand 2 "cc_register" "") (const_int 0)])))]
400 "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #1"
401 [(set_attr "conds" "use")
402 (set_attr "length" "10")]
405 (define_insn "*thumb2_movsicc_insn"
406 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r")
408 (match_operator 3 "arm_comparison_operator"
409 [(match_operand 4 "cc_register" "") (const_int 0)])
410 (match_operand:SI 1 "arm_not_operand" "0,0,rI,K,rI,rI,K,K")
411 (match_operand:SI 2 "arm_not_operand" "rI,K,0,0,rI,K,rI,K")))]
414 it\\t%D3\;mov%D3\\t%0, %2
415 it\\t%D3\;mvn%D3\\t%0, #%B2
416 it\\t%d3\;mov%d3\\t%0, %1
417 it\\t%d3\;mvn%d3\\t%0, #%B1
418 ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
419 ite\\t%d3\;mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2
420 ite\\t%d3\;mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2
421 ite\\t%d3\;mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2"
422 [(set_attr "length" "6,6,6,6,10,10,10,10")
423 (set_attr "conds" "use")]
426 (define_insn "*thumb2_movsfcc_soft_insn"
427 [(set (match_operand:SF 0 "s_register_operand" "=r,r")
428 (if_then_else:SF (match_operator 3 "arm_comparison_operator"
429 [(match_operand 4 "cc_register" "") (const_int 0)])
430 (match_operand:SF 1 "s_register_operand" "0,r")
431 (match_operand:SF 2 "s_register_operand" "r,0")))]
432 "TARGET_THUMB2 && TARGET_SOFT_FLOAT"
434 it\\t%D3\;mov%D3\\t%0, %2
435 it\\t%d3\;mov%d3\\t%0, %1"
436 [(set_attr "length" "6,6")
437 (set_attr "conds" "use")]
440 (define_insn "*call_reg_thumb2"
441 [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
442 (match_operand 1 "" ""))
443 (use (match_operand 2 "" ""))
444 (clobber (reg:SI LR_REGNUM))]
447 [(set_attr "type" "call")]
450 (define_insn "*call_value_reg_thumb2"
451 [(set (match_operand 0 "" "")
452 (call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
453 (match_operand 2 "" "")))
454 (use (match_operand 3 "" ""))
455 (clobber (reg:SI LR_REGNUM))]
458 [(set_attr "type" "call")]
461 (define_insn "*thumb2_indirect_jump"
463 (match_operand:SI 0 "register_operand" "l*r"))]
466 [(set_attr "conds" "clob")]
468 ;; Don't define thumb2_load_indirect_jump because we can't guarantee label
469 ;; addresses will have the thumb bit set correctly.
472 ;; Patterns to allow combination of arithmetic, cond code and shifts
474 (define_insn "*thumb2_arith_shiftsi"
475 [(set (match_operand:SI 0 "s_register_operand" "=r")
476 (match_operator:SI 1 "shiftable_operator"
477 [(match_operator:SI 3 "shift_operator"
478 [(match_operand:SI 4 "s_register_operand" "r")
479 (match_operand:SI 5 "const_int_operand" "M")])
480 (match_operand:SI 2 "s_register_operand" "r")]))]
482 "%i1%?\\t%0, %2, %4%S3"
483 [(set_attr "predicable" "yes")
484 (set_attr "shift" "4")
485 (set_attr "type" "alu_shift")]
488 ;; ??? What does this splitter do? Copied from the ARM version
490 [(set (match_operand:SI 0 "s_register_operand" "")
491 (match_operator:SI 1 "shiftable_operator"
492 [(match_operator:SI 2 "shiftable_operator"
493 [(match_operator:SI 3 "shift_operator"
494 [(match_operand:SI 4 "s_register_operand" "")
495 (match_operand:SI 5 "const_int_operand" "")])
496 (match_operand:SI 6 "s_register_operand" "")])
497 (match_operand:SI 7 "arm_rhs_operand" "")]))
498 (clobber (match_operand:SI 8 "s_register_operand" ""))]
501 (match_op_dup 2 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
504 (match_op_dup 1 [(match_dup 8) (match_dup 7)]))]
507 (define_insn "*thumb2_arith_shiftsi_compare0"
508 [(set (reg:CC_NOOV CC_REGNUM)
509 (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
510 [(match_operator:SI 3 "shift_operator"
511 [(match_operand:SI 4 "s_register_operand" "r")
512 (match_operand:SI 5 "const_int_operand" "M")])
513 (match_operand:SI 2 "s_register_operand" "r")])
515 (set (match_operand:SI 0 "s_register_operand" "=r")
516 (match_op_dup 1 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
519 "%i1%.\\t%0, %2, %4%S3"
520 [(set_attr "conds" "set")
521 (set_attr "shift" "4")
522 (set_attr "type" "alu_shift")]
525 (define_insn "*thumb2_arith_shiftsi_compare0_scratch"
526 [(set (reg:CC_NOOV CC_REGNUM)
527 (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
528 [(match_operator:SI 3 "shift_operator"
529 [(match_operand:SI 4 "s_register_operand" "r")
530 (match_operand:SI 5 "const_int_operand" "M")])
531 (match_operand:SI 2 "s_register_operand" "r")])
533 (clobber (match_scratch:SI 0 "=r"))]
535 "%i1%.\\t%0, %2, %4%S3"
536 [(set_attr "conds" "set")
537 (set_attr "shift" "4")
538 (set_attr "type" "alu_shift")]
541 (define_insn "*thumb2_sub_shiftsi"
542 [(set (match_operand:SI 0 "s_register_operand" "=r")
543 (minus:SI (match_operand:SI 1 "s_register_operand" "r")
544 (match_operator:SI 2 "shift_operator"
545 [(match_operand:SI 3 "s_register_operand" "r")
546 (match_operand:SI 4 "const_int_operand" "M")])))]
548 "sub%?\\t%0, %1, %3%S2"
549 [(set_attr "predicable" "yes")
550 (set_attr "shift" "3")
551 (set_attr "type" "alu_shift")]
554 (define_insn "*thumb2_sub_shiftsi_compare0"
555 [(set (reg:CC_NOOV CC_REGNUM)
557 (minus:SI (match_operand:SI 1 "s_register_operand" "r")
558 (match_operator:SI 2 "shift_operator"
559 [(match_operand:SI 3 "s_register_operand" "r")
560 (match_operand:SI 4 "const_int_operand" "M")]))
562 (set (match_operand:SI 0 "s_register_operand" "=r")
563 (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
566 "sub%.\\t%0, %1, %3%S2"
567 [(set_attr "conds" "set")
568 (set_attr "shift" "3")
569 (set_attr "type" "alu_shift")]
572 (define_insn "*thumb2_sub_shiftsi_compare0_scratch"
573 [(set (reg:CC_NOOV CC_REGNUM)
575 (minus:SI (match_operand:SI 1 "s_register_operand" "r")
576 (match_operator:SI 2 "shift_operator"
577 [(match_operand:SI 3 "s_register_operand" "r")
578 (match_operand:SI 4 "const_int_operand" "M")]))
580 (clobber (match_scratch:SI 0 "=r"))]
582 "sub%.\\t%0, %1, %3%S2"
583 [(set_attr "conds" "set")
584 (set_attr "shift" "3")
585 (set_attr "type" "alu_shift")]
588 (define_insn "*thumb2_and_scc"
589 [(set (match_operand:SI 0 "s_register_operand" "=r")
590 (and:SI (match_operator:SI 1 "arm_comparison_operator"
591 [(match_operand 3 "cc_register" "") (const_int 0)])
592 (match_operand:SI 2 "s_register_operand" "r")))]
594 "ite\\t%D1\;mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1"
595 [(set_attr "conds" "use")
596 (set_attr "length" "10")]
599 (define_insn "*thumb2_ior_scc"
600 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
601 (ior:SI (match_operator:SI 2 "arm_comparison_operator"
602 [(match_operand 3 "cc_register" "") (const_int 0)])
603 (match_operand:SI 1 "s_register_operand" "0,?r")))]
606 it\\t%d2\;orr%d2\\t%0, %1, #1
607 ite\\t%D2\;mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1"
608 [(set_attr "conds" "use")
609 (set_attr "length" "6,10")]
612 (define_insn "*thumb2_compare_scc"
613 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
614 (match_operator:SI 1 "arm_comparison_operator"
615 [(match_operand:SI 2 "s_register_operand" "r,r")
616 (match_operand:SI 3 "arm_add_operand" "rI,L")]))
617 (clobber (reg:CC CC_REGNUM))]
620 if (operands[3] == const0_rtx)
622 if (GET_CODE (operands[1]) == LT)
623 return \"lsr\\t%0, %2, #31\";
625 if (GET_CODE (operands[1]) == GE)
626 return \"mvn\\t%0, %2\;lsr\\t%0, %0, #31\";
628 if (GET_CODE (operands[1]) == EQ)
629 return \"rsbs\\t%0, %2, #1\;it\\tcc\;movcc\\t%0, #0\";
632 if (GET_CODE (operands[1]) == NE)
634 if (which_alternative == 1)
635 return \"adds\\t%0, %2, #%n3\;it\\tne\;movne\\t%0, #1\";
636 return \"subs\\t%0, %2, %3\;it\\tne\;movne\\t%0, #1\";
638 if (which_alternative == 1)
639 output_asm_insn (\"cmn\\t%2, #%n3\", operands);
641 output_asm_insn (\"cmp\\t%2, %3\", operands);
642 return \"ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1\";
644 [(set_attr "conds" "clob")
645 (set_attr "length" "14")]
648 (define_insn "*thumb2_cond_move"
649 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
650 (if_then_else:SI (match_operator 3 "equality_operator"
651 [(match_operator 4 "arm_comparison_operator"
652 [(match_operand 5 "cc_register" "") (const_int 0)])
654 (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
655 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))]
658 if (GET_CODE (operands[3]) == NE)
660 if (which_alternative != 1)
661 output_asm_insn (\"it\\t%D4\;mov%D4\\t%0, %2\", operands);
662 if (which_alternative != 0)
663 output_asm_insn (\"it\\t%d4\;mov%d4\\t%0, %1\", operands);
666 switch (which_alternative)
669 output_asm_insn (\"it\\t%d4\", operands);
672 output_asm_insn (\"it\\t%D4\", operands);
675 output_asm_insn (\"ite\\t%D4\", operands);
680 if (which_alternative != 0)
681 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
682 if (which_alternative != 1)
683 output_asm_insn (\"mov%d4\\t%0, %2\", operands);
686 [(set_attr "conds" "use")
687 (set_attr "length" "6,6,10")]
690 (define_insn "*thumb2_cond_arith"
691 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
692 (match_operator:SI 5 "shiftable_operator"
693 [(match_operator:SI 4 "arm_comparison_operator"
694 [(match_operand:SI 2 "s_register_operand" "r,r")
695 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
696 (match_operand:SI 1 "s_register_operand" "0,?r")]))
697 (clobber (reg:CC CC_REGNUM))]
700 if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
701 return \"%i5\\t%0, %1, %2, lsr #31\";
703 output_asm_insn (\"cmp\\t%2, %3\", operands);
704 if (GET_CODE (operands[5]) == AND)
706 output_asm_insn (\"ite\\t%D4\", operands);
707 output_asm_insn (\"mov%D4\\t%0, #0\", operands);
709 else if (GET_CODE (operands[5]) == MINUS)
711 output_asm_insn (\"ite\\t%D4\", operands);
712 output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands);
714 else if (which_alternative != 0)
716 output_asm_insn (\"ite\\t%D4\", operands);
717 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
720 output_asm_insn (\"it\\t%d4\", operands);
721 return \"%i5%d4\\t%0, %1, #1\";
723 [(set_attr "conds" "clob")
724 (set_attr "length" "14")]
727 (define_insn "*thumb2_cond_sub"
728 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
729 (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r")
730 (match_operator:SI 4 "arm_comparison_operator"
731 [(match_operand:SI 2 "s_register_operand" "r,r")
732 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
733 (clobber (reg:CC CC_REGNUM))]
736 output_asm_insn (\"cmp\\t%2, %3\", operands);
737 if (which_alternative != 0)
739 output_asm_insn (\"ite\\t%D4\", operands);
740 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
743 output_asm_insn (\"it\\t%d4\", operands);
744 return \"sub%d4\\t%0, %1, #1\";
746 [(set_attr "conds" "clob")
747 (set_attr "length" "10,14")]
750 (define_insn "*thumb2_negscc"
751 [(set (match_operand:SI 0 "s_register_operand" "=r")
752 (neg:SI (match_operator 3 "arm_comparison_operator"
753 [(match_operand:SI 1 "s_register_operand" "r")
754 (match_operand:SI 2 "arm_rhs_operand" "rI")])))
755 (clobber (reg:CC CC_REGNUM))]
758 if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx)
759 return \"asr\\t%0, %1, #31\";
761 if (GET_CODE (operands[3]) == NE)
762 return \"subs\\t%0, %1, %2\;it\\tne\;mvnne\\t%0, #0\";
764 output_asm_insn (\"cmp\\t%1, %2\", operands);
765 output_asm_insn (\"ite\\t%D3\", operands);
766 output_asm_insn (\"mov%D3\\t%0, #0\", operands);
767 return \"mvn%d3\\t%0, #0\";
769 [(set_attr "conds" "clob")
770 (set_attr "length" "14")]
773 (define_insn "*thumb2_movcond"
774 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
776 (match_operator 5 "arm_comparison_operator"
777 [(match_operand:SI 3 "s_register_operand" "r,r,r")
778 (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
779 (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
780 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
781 (clobber (reg:CC CC_REGNUM))]
784 if (GET_CODE (operands[5]) == LT
785 && (operands[4] == const0_rtx))
787 if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
789 if (operands[2] == const0_rtx)
790 return \"and\\t%0, %1, %3, asr #31\";
791 return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\";
793 else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
795 if (operands[1] == const0_rtx)
796 return \"bic\\t%0, %2, %3, asr #31\";
797 return \"bics\\t%0, %2, %3, asr #32\;it\\tcs\;movcs\\t%0, %1\";
799 /* The only case that falls through to here is when both ops 1 & 2
803 if (GET_CODE (operands[5]) == GE
804 && (operands[4] == const0_rtx))
806 if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
808 if (operands[2] == const0_rtx)
809 return \"bic\\t%0, %1, %3, asr #31\";
810 return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\";
812 else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
814 if (operands[1] == const0_rtx)
815 return \"and\\t%0, %2, %3, asr #31\";
816 return \"ands\\t%0, %2, %3, asr #32\;it\tcc\;movcc\\t%0, %1\";
818 /* The only case that falls through to here is when both ops 1 & 2
821 if (GET_CODE (operands[4]) == CONST_INT
822 && !const_ok_for_arm (INTVAL (operands[4])))
823 output_asm_insn (\"cmn\\t%3, #%n4\", operands);
825 output_asm_insn (\"cmp\\t%3, %4\", operands);
826 switch (which_alternative)
829 output_asm_insn (\"it\\t%D5\", operands);
832 output_asm_insn (\"it\\t%d5\", operands);
835 output_asm_insn (\"ite\\t%d5\", operands);
840 if (which_alternative != 0)
841 output_asm_insn (\"mov%d5\\t%0, %1\", operands);
842 if (which_alternative != 1)
843 output_asm_insn (\"mov%D5\\t%0, %2\", operands);
846 [(set_attr "conds" "clob")
847 (set_attr "length" "10,10,14")]
850 ;; Zero and sign extension instructions.
852 (define_insn_and_split "*thumb2_zero_extendsidi2"
853 [(set (match_operand:DI 0 "s_register_operand" "=r")
854 (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
856 "mov%?\\t%Q0, %1\;mov%?\\t%R0, #0"
857 "&& reload_completed"
858 [(set (match_dup 0) (match_dup 1))]
861 rtx lo_part = gen_lowpart (SImode, operands[0]);
862 if (!REG_P (lo_part) || REGNO (lo_part) != REGNO (operands[1]))
863 emit_move_insn (lo_part, operands[1]);
864 operands[0] = gen_highpart (SImode, operands[0]);
865 operands[1] = const0_rtx;
868 [(set_attr "length" "8")
869 (set_attr "ce_count" "2")
870 (set_attr "predicable" "yes")]
873 (define_insn_and_split "*thumb2_zero_extendqidi2"
874 [(set (match_operand:DI 0 "s_register_operand" "=r,r")
875 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
878 uxtb%?\\t%Q0, %1\;mov%?\\t%R0, #0
879 ldr%(b%)\\t%Q0, %1\;mov%?\\t%R0, #0"
880 "&& reload_completed"
881 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
882 (set (match_dup 2) (match_dup 3))]
885 operands[2] = gen_highpart (SImode, operands[0]);
886 operands[0] = gen_lowpart (SImode, operands[0]);
887 operands[3] = const0_rtx;
890 [(set_attr "length" "8")
891 (set_attr "ce_count" "2")
892 (set_attr "predicable" "yes")
893 (set_attr "type" "*,load_byte")
894 (set_attr "pool_range" "*,4092")
895 (set_attr "neg_pool_range" "*,250")]
898 (define_insn "*thumb2_extendsidi2"
899 [(set (match_operand:DI 0 "s_register_operand" "=r")
900 (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
903 /* ??? Output both instructions unconditionally, otherwise the conditional
904 execution insn counter gets confused.
905 if (REGNO (operands[1])
906 != REGNO (operands[0]) + (WORDS_BIG_ENDIAN ? 1 : 0)) */
907 output_asm_insn (\"mov%?\\t%Q0, %1\", operands);
908 return \"asr%?\\t%R0, %Q0, #31\";
910 [(set_attr "length" "8")
911 (set_attr "ce_count" "2")
912 (set_attr "shift" "1")
913 (set_attr "predicable" "yes")]
916 ;; All supported Thumb2 implementations are armv6, so only that case is
918 (define_insn "*thumb2_extendqisi_v6"
919 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
920 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
921 "TARGET_THUMB2 && arm_arch6"
925 [(set_attr "type" "alu_shift,load_byte")
926 (set_attr "predicable" "yes")
927 (set_attr "pool_range" "*,4096")
928 (set_attr "neg_pool_range" "*,250")]
931 (define_insn "*thumb2_zero_extendhisi2_v6"
932 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
933 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
934 "TARGET_THUMB2 && arm_arch6"
938 [(set_attr "type" "alu_shift,load_byte")
939 (set_attr "predicable" "yes")
940 (set_attr "pool_range" "*,4096")
941 (set_attr "neg_pool_range" "*,250")]
944 (define_insn "*thumb2_zero_extendqisi2_v6"
945 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
946 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
947 "TARGET_THUMB2 && arm_arch6"
950 ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
951 [(set_attr "type" "alu_shift,load_byte")
952 (set_attr "predicable" "yes")
953 (set_attr "pool_range" "*,4096")
954 (set_attr "neg_pool_range" "*,250")]
957 (define_insn "thumb2_casesi_internal"
958 [(parallel [(set (pc)
960 (leu (match_operand:SI 0 "s_register_operand" "r")
961 (match_operand:SI 1 "arm_rhs_operand" "rI"))
962 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
963 (label_ref (match_operand 2 "" ""))))
964 (label_ref (match_operand 3 "" ""))))
965 (clobber (reg:CC CC_REGNUM))
966 (clobber (match_scratch:SI 4 "=&r"))
967 (use (label_ref (match_dup 2)))])]
968 "TARGET_THUMB2 && !flag_pic"
969 "* return thumb2_output_casesi(operands);"
970 [(set_attr "conds" "clob")
971 (set_attr "length" "16")]
974 (define_insn "thumb2_casesi_internal_pic"
975 [(parallel [(set (pc)
977 (leu (match_operand:SI 0 "s_register_operand" "r")
978 (match_operand:SI 1 "arm_rhs_operand" "rI"))
979 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
980 (label_ref (match_operand 2 "" ""))))
981 (label_ref (match_operand 3 "" ""))))
982 (clobber (reg:CC CC_REGNUM))
983 (clobber (match_scratch:SI 4 "=&r"))
984 (clobber (match_scratch:SI 5 "=r"))
985 (use (label_ref (match_dup 2)))])]
986 "TARGET_THUMB2 && flag_pic"
987 "* return thumb2_output_casesi(operands);"
988 [(set_attr "conds" "clob")
989 (set_attr "length" "20")]
992 (define_insn_and_split "thumb2_eh_return"
993 [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
995 (clobber (match_scratch:SI 1 "=&r"))]
998 "&& reload_completed"
1002 thumb_set_return_address (operands[0], operands[1]);
1007 ;; Peepholes and insns for 16-bit flag clobbering instructions.
1008 ;; The conditional forms of these instructions do not clobber CC.
1009 ;; However by the time peepholes are run it is probably too late to do
1010 ;; anything useful with this information.
1012 [(set (match_operand:SI 0 "low_register_operand" "")
1013 (match_operator:SI 3 "thumb_16bit_operator"
1014 [(match_operand:SI 1 "low_register_operand" "")
1015 (match_operand:SI 2 "low_register_operand" "")]))]
1017 && (rtx_equal_p(operands[0], operands[1])
1018 || GET_CODE(operands[3]) == PLUS
1019 || GET_CODE(operands[3]) == MINUS)
1020 && peep2_regno_dead_p(0, CC_REGNUM)"
1026 (clobber (reg:CC CC_REGNUM))])]
1030 (define_insn "*thumb2_alusi3_short"
1031 [(set (match_operand:SI 0 "s_register_operand" "=l")
1032 (match_operator:SI 3 "thumb_16bit_operator"
1033 [(match_operand:SI 1 "s_register_operand" "0")
1034 (match_operand:SI 2 "s_register_operand" "l")]))
1035 (clobber (reg:CC CC_REGNUM))]
1036 "TARGET_THUMB2 && reload_completed
1037 && GET_CODE(operands[3]) != PLUS
1038 && GET_CODE(operands[3]) != MINUS"
1039 "%I3%!\\t%0, %1, %2"
1040 [(set_attr "predicable" "yes")
1041 (set_attr "length" "2")]
1044 ;; Similarly for 16-bit shift instructions
1045 ;; There is no 16-bit rotate by immediate instruction.
1047 [(set (match_operand:SI 0 "low_register_operand" "")
1048 (match_operator:SI 3 "shift_operator"
1049 [(match_operand:SI 1 "low_register_operand" "")
1050 (match_operand:SI 2 "low_reg_or_int_operand" "")]))]
1052 && peep2_regno_dead_p(0, CC_REGNUM)
1053 && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
1054 || REG_P(operands[2]))"
1060 (clobber (reg:CC CC_REGNUM))])]
1064 (define_insn "*thumb2_shiftsi3_short"
1065 [(set (match_operand:SI 0 "low_register_operand" "=l")
1066 (match_operator:SI 3 "shift_operator"
1067 [(match_operand:SI 1 "low_register_operand" "l")
1068 (match_operand:SI 2 "low_reg_or_int_operand" "lM")]))
1069 (clobber (reg:CC CC_REGNUM))]
1070 "TARGET_THUMB2 && reload_completed
1071 && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
1072 || REG_P(operands[2]))"
1073 "* return arm_output_shift(operands, 2);"
1074 [(set_attr "predicable" "yes")
1075 (set_attr "shift" "1")
1076 (set_attr "length" "2")
1077 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
1078 (const_string "alu_shift")
1079 (const_string "alu_shift_reg")))]
1082 ;; 16-bit load immediate
1084 [(set (match_operand:SI 0 "low_register_operand" "")
1085 (match_operand:SI 1 "const_int_operand" ""))]
1087 && peep2_regno_dead_p(0, CC_REGNUM)
1088 && (unsigned HOST_WIDE_INT) INTVAL(operands[1]) < 256"
1092 (clobber (reg:CC CC_REGNUM))])]
1096 (define_insn "*thumb2_movsi_shortim"
1097 [(set (match_operand:SI 0 "low_register_operand" "=l")
1098 (match_operand:SI 1 "const_int_operand" "I"))
1099 (clobber (reg:CC CC_REGNUM))]
1100 "TARGET_THUMB2 && reload_completed"
1102 [(set_attr "predicable" "yes")
1103 (set_attr "length" "2")]
1106 ;; 16-bit add/sub immediate
1108 [(set (match_operand:SI 0 "low_register_operand" "")
1109 (plus:SI (match_operand:SI 1 "low_register_operand" "")
1110 (match_operand:SI 2 "const_int_operand" "")))]
1112 && peep2_regno_dead_p(0, CC_REGNUM)
1113 && ((rtx_equal_p(operands[0], operands[1])
1114 && INTVAL(operands[2]) > -256 && INTVAL(operands[2]) < 256)
1115 || (INTVAL(operands[2]) > -8 && INTVAL(operands[2]) < 8))"
1118 (plus:SI (match_dup 1)
1120 (clobber (reg:CC CC_REGNUM))])]
1124 (define_insn "*thumb2_addsi_short"
1125 [(set (match_operand:SI 0 "low_register_operand" "=l")
1126 (plus:SI (match_operand:SI 1 "low_register_operand" "l")
1127 (match_operand:SI 2 "low_reg_or_int_operand" "lIL")))
1128 (clobber (reg:CC CC_REGNUM))]
1129 "TARGET_THUMB2 && reload_completed"
1133 if (GET_CODE (operands[2]) == CONST_INT)
1134 val = INTVAL(operands[2]);
1138 /* We prefer eg. subs rn, rn, #1 over adds rn, rn, #0xffffffff. */
1139 if (val < 0 && const_ok_for_arm(ARM_SIGN_EXTEND (-val)))
1140 return \"sub%!\\t%0, %1, #%n2\";
1142 return \"add%!\\t%0, %1, %2\";
1144 [(set_attr "predicable" "yes")
1145 (set_attr "length" "2")]
1148 (define_insn "divsi3"
1149 [(set (match_operand:SI 0 "s_register_operand" "=r")
1150 (div:SI (match_operand:SI 1 "s_register_operand" "r")
1151 (match_operand:SI 2 "s_register_operand" "r")))]
1152 "TARGET_THUMB2 && arm_arch_hwdiv"
1153 "sdiv%?\t%0, %1, %2"
1154 [(set_attr "predicable" "yes")
1155 (set_attr "insn" "sdiv")]
1158 (define_insn "udivsi3"
1159 [(set (match_operand:SI 0 "s_register_operand" "=r")
1160 (udiv:SI (match_operand:SI 1 "s_register_operand" "r")
1161 (match_operand:SI 2 "s_register_operand" "r")))]
1162 "TARGET_THUMB2 && arm_arch_hwdiv"
1163 "udiv%?\t%0, %1, %2"
1164 [(set_attr "predicable" "yes")
1165 (set_attr "insn" "udiv")]
1168 (define_insn "*thumb2_subsi_short"
1169 [(set (match_operand:SI 0 "low_register_operand" "=l")
1170 (minus:SI (match_operand:SI 1 "low_register_operand" "l")
1171 (match_operand:SI 2 "low_register_operand" "l")))
1172 (clobber (reg:CC CC_REGNUM))]
1173 "TARGET_THUMB2 && reload_completed"
1174 "sub%!\\t%0, %1, %2"
1175 [(set_attr "predicable" "yes")
1176 (set_attr "length" "2")]
1179 ;; 16-bit encodings of "muls" and "mul<c>". We only use these when
1180 ;; optimizing for size since "muls" is slow on all known
1181 ;; implementations and since "mul<c>" will be generated by
1182 ;; "*arm_mulsi3_v6" anyhow. The assembler will use a 16-bit encoding
1183 ;; for "mul<c>" whenever possible anyhow.
1185 [(set (match_operand:SI 0 "low_register_operand" "")
1186 (mult:SI (match_operand:SI 1 "low_register_operand" "")
1188 "TARGET_THUMB2 && optimize_size && peep2_regno_dead_p (0, CC_REGNUM)"
1191 (mult:SI (match_dup 0) (match_dup 1)))
1192 (clobber (reg:CC CC_REGNUM))])]
1197 [(set (match_operand:SI 0 "low_register_operand" "")
1198 (mult:SI (match_dup 0)
1199 (match_operand:SI 1 "low_register_operand" "")))]
1200 "TARGET_THUMB2 && optimize_size && peep2_regno_dead_p (0, CC_REGNUM)"
1203 (mult:SI (match_dup 0) (match_dup 1)))
1204 (clobber (reg:CC CC_REGNUM))])]
1208 (define_insn "*thumb2_mulsi_short"
1209 [(set (match_operand:SI 0 "low_register_operand" "=l")
1210 (mult:SI (match_operand:SI 1 "low_register_operand" "%0")
1211 (match_operand:SI 2 "low_register_operand" "l")))
1212 (clobber (reg:CC CC_REGNUM))]
1213 "TARGET_THUMB2 && optimize_size && reload_completed"
1214 "mul%!\\t%0, %2, %0"
1215 [(set_attr "predicable" "yes")
1216 (set_attr "length" "2")
1217 (set_attr "insn" "muls")])
1219 (define_insn "*thumb2_mulsi_short_compare0"
1220 [(set (reg:CC_NOOV CC_REGNUM)
1222 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1223 (match_operand:SI 2 "register_operand" "l"))
1225 (set (match_operand:SI 0 "register_operand" "=l")
1226 (mult:SI (match_dup 1) (match_dup 2)))]
1227 "TARGET_THUMB2 && optimize_size"
1229 [(set_attr "length" "2")
1230 (set_attr "insn" "muls")])
1232 (define_insn "*thumb2_mulsi_short_compare0_scratch"
1233 [(set (reg:CC_NOOV CC_REGNUM)
1235 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1236 (match_operand:SI 2 "register_operand" "l"))
1238 (clobber (match_scratch:SI 0 "=r"))]
1239 "TARGET_THUMB2 && optimize_size"
1241 [(set_attr "length" "2")
1242 (set_attr "insn" "muls")])
1244 (define_insn "*thumb2_cbz"
1245 [(set (pc) (if_then_else
1246 (eq (match_operand:SI 0 "s_register_operand" "l,?r")
1248 (label_ref (match_operand 1 "" ""))
1250 (clobber (reg:CC CC_REGNUM))]
1253 if (get_attr_length (insn) == 2 && which_alternative == 0)
1254 return \"cbz\\t%0, %l1\";
1256 return \"cmp\\t%0, #0\;beq\\t%l1\";
1258 [(set (attr "length")
1260 (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1261 (le (minus (match_dup 1) (pc)) (const_int 128)))
1266 (define_insn "*thumb2_cbnz"
1267 [(set (pc) (if_then_else
1268 (ne (match_operand:SI 0 "s_register_operand" "l,?r")
1270 (label_ref (match_operand 1 "" ""))
1272 (clobber (reg:CC CC_REGNUM))]
1275 if (get_attr_length (insn) == 2 && which_alternative == 0)
1276 return \"cbnz\\t%0, %l1\";
1278 return \"cmp\\t%0, #0\;bne\\t%l1\";
1280 [(set (attr "length")
1282 (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1283 (le (minus (match_dup 1) (pc)) (const_int 128)))
1288 ;; 16-bit complement
1290 [(set (match_operand:SI 0 "low_register_operand" "")
1291 (not:SI (match_operand:SI 1 "low_register_operand" "")))]
1293 && peep2_regno_dead_p(0, CC_REGNUM)"
1296 (not:SI (match_dup 1)))
1297 (clobber (reg:CC CC_REGNUM))])]
1301 (define_insn "*thumb2_one_cmplsi2_short"
1302 [(set (match_operand:SI 0 "low_register_operand" "=l")
1303 (not:SI (match_operand:SI 1 "low_register_operand" "l")))
1304 (clobber (reg:CC CC_REGNUM))]
1305 "TARGET_THUMB2 && reload_completed"
1307 [(set_attr "predicable" "yes")
1308 (set_attr "length" "2")]
1313 [(set (match_operand:SI 0 "low_register_operand" "")
1314 (neg:SI (match_operand:SI 1 "low_register_operand" "")))]
1316 && peep2_regno_dead_p(0, CC_REGNUM)"
1319 (neg:SI (match_dup 1)))
1320 (clobber (reg:CC CC_REGNUM))])]
1324 (define_insn "*thumb2_negsi2_short"
1325 [(set (match_operand:SI 0 "low_register_operand" "=l")
1326 (neg:SI (match_operand:SI 1 "low_register_operand" "l")))
1327 (clobber (reg:CC CC_REGNUM))]
1328 "TARGET_THUMB2 && reload_completed"
1330 [(set_attr "predicable" "yes")
1331 (set_attr "length" "2")]
1334 (define_insn "orsi_notsi_si"
1335 [(set (match_operand:SI 0 "s_register_operand" "=r")
1336 (ior:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
1337 (match_operand:SI 1 "s_register_operand" "r")))]
1339 "orn%?\\t%0, %1, %2"
1340 [(set_attr "predicable" "yes")]
1343 (define_insn "*thumb_orsi_not_shiftsi_si"
1344 [(set (match_operand:SI 0 "s_register_operand" "=r")
1345 (ior:SI (not:SI (match_operator:SI 4 "shift_operator"
1346 [(match_operand:SI 2 "s_register_operand" "r")
1347 (match_operand:SI 3 "const_int_operand" "M")]))
1348 (match_operand:SI 1 "s_register_operand" "r")))]
1350 "orn%?\\t%0, %1, %2%S4"
1351 [(set_attr "predicable" "yes")
1352 (set_attr "shift" "2")
1353 (set_attr "type" "alu_shift")]
1356 (define_insn_and_split "*thumb2_iorsi3"
1357 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
1358 (ior:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
1359 (match_operand:SI 2 "reg_or_int_operand" "rI,K,?n")))]
1363 orn%?\\t%0, %1, #%B2
1366 && GET_CODE (operands[2]) == CONST_INT
1367 && !(const_ok_for_arm (INTVAL (operands[2]))
1368 || const_ok_for_arm (~INTVAL (operands[2])))"
1369 [(clobber (const_int 0))]
1371 arm_split_constant (IOR, SImode, curr_insn,
1372 INTVAL (operands[2]), operands[0], operands[1], 0);
1375 [(set_attr "length" "4,4,16")
1376 (set_attr "predicable" "yes")]