gcc/config/arm/vfp.md

   1 ;; ARM VFP instruction patterns
   2 ;; Copyright (C) 2003, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
   3 ;; Written by CodeSourcery.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.  */
  20
  21 ;; Additional register numbers
  22 (define_constants
  23   [(VFPCC_REGNUM 127)]
  24 )
  25
  26 ;; The VFP "type" attributes differ from those used in the FPA model.
  27 ;; ffarith      Fast floating point insns, e.g. abs, neg, cpy, cmp.
  28 ;; farith       Most arithmetic insns.
  29 ;; fmul         Double precision multiply.
  30 ;; fdivs        Single precision sqrt or division.
  31 ;; fdivd        Double precision sqrt or division.
  32 ;; f_flag       fmstat operation
  33 ;; f_load[sd]   Floating point load from memory.
  34 ;; f_store[sd]  Floating point store to memory.
  35 ;; f_2_r        Transfer vfp to arm reg.
  36 ;; r_2_f        Transfer arm to vfp reg.
  37 ;; f_cvt        Convert floating<->integral
  38
  39 ;; SImode moves
  40 ;; ??? For now do not allow loading constants into vfp regs.  This causes
  41 ;; problems because small constants get converted into adds.
  42 (define_insn "*arm_movsi_vfp"
  43   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv")
  44       (match_operand:SI 1 "general_operand"        "rk, I,K,N,mi,rk,r,*t,*t,*Uvi,*t"))]
  45   "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT
  46    && (   s_register_operand (operands[0], SImode)
  47        || s_register_operand (operands[1], SImode))"
  48   "*
  49   switch (which_alternative)
  50     {
  51     case 0: case 1:
  52       return \"mov%?\\t%0, %1\";
  53     case 2:
  54       return \"mvn%?\\t%0, #%B1\";
  55     case 3:
  56       return \"movw%?\\t%0, %1\";
  57     case 4:
  58       return \"ldr%?\\t%0, %1\";
  59     case 5:
  60       return \"str%?\\t%1, %0\";
  61     case 6:
  62       return \"fmsr%?\\t%0, %1\\t%@ int\";
  63     case 7:
  64       return \"fmrs%?\\t%0, %1\\t%@ int\";
  65     case 8:
  66       return \"fcpys%?\\t%0, %1\\t%@ int\";
  67     case 9: case 10:
  68       return output_move_vfp (operands);
  69     default:
  70       gcc_unreachable ();
  71     }
  72   "
  73   [(set_attr "predicable" "yes")
  74    (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,ffarith,f_loads,f_stores")
  75    (set_attr "pool_range"     "*,*,*,*,4096,*,*,*,*,1020,*")
  76    (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
  77 )
  78
  79 (define_insn "*thumb2_movsi_vfp"
  80   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m,*t,r, *t,*t, *Uv")
  81       (match_operand:SI 1 "general_operand"        "rk, I,K,N,mi,rk,r,*t,*t,*Uvi,*t"))]
  82   "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT
  83    && (   s_register_operand (operands[0], SImode)
  84        || s_register_operand (operands[1], SImode))"
  85   "*
  86   switch (which_alternative)
  87     {
  88     case 0: case 1:
  89       return \"mov%?\\t%0, %1\";
  90     case 2:
  91       return \"mvn%?\\t%0, #%B1\";
  92     case 3:
  93       return \"movw%?\\t%0, %1\";
  94     case 4:
  95       return \"ldr%?\\t%0, %1\";
  96     case 5:
  97       return \"str%?\\t%1, %0\";
  98     case 6:
  99       return \"fmsr%?\\t%0, %1\\t%@ int\";
 100     case 7:
 101       return \"fmrs%?\\t%0, %1\\t%@ int\";
 102     case 8:
 103       return \"fcpys%?\\t%0, %1\\t%@ int\";
 104     case 9: case 10:
 105       return output_move_vfp (operands);
 106     default:
 107       gcc_unreachable ();
 108     }
 109   "
 110   [(set_attr "predicable" "yes")
 111    (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,ffarith,f_load,f_store")
 112    (set_attr "pool_range"     "*,*,*,*,4096,*,*,*,*,1020,*")
 113    (set_attr "neg_pool_range" "*,*,*,*,   0,*,*,*,*,1008,*")]
 114 )
 115
 116
 117 ;; DImode moves
 118
 119 (define_insn "*arm_movdi_vfp"
 120   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv")
 121         (match_operand:DI 1 "di_operand"              "rIK,mi,r,r,w,w,Uvi,w"))]
 122   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
 123    && (   register_operand (operands[0], DImode)
 124        || register_operand (operands[1], DImode))"
 125   "*
 126   switch (which_alternative)
 127     {
 128     case 0:
 129       return \"#\";
 130     case 1:
 131     case 2:
 132       return output_move_double (operands);
 133     case 3:
 134       return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
 135     case 4:
 136       return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
 137     case 5:
 138       return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
 139     case 6: case 7:
 140       return output_move_vfp (operands);
 141     default:
 142       gcc_unreachable ();
 143     }
 144   "
 145   [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarith,f_loadd,f_stored")
 146    (set_attr "length" "8,8,8,4,4,4,4,4")
 147    (set_attr "pool_range"     "*,1020,*,*,*,*,1020,*")
 148    (set_attr "neg_pool_range" "*,1008,*,*,*,*,1008,*")]
 149 )
 150
 151 (define_insn "*thumb2_movdi_vfp"
 152   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv")
 153         (match_operand:DI 1 "di_operand"              "rIK,mi,r,r,w,w,Uvi,w"))]
 154   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
 155   "*
 156   switch (which_alternative)
 157     {
 158     case 0: case 1: case 2:
 159       return (output_move_double (operands));
 160     case 3:
 161       return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
 162     case 4:
 163       return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
 164     case 5:
 165       return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
 166     case 6: case 7:
 167       return output_move_vfp (operands);
 168     default:
 169       abort ();
 170     }
 171   "
 172   [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarith,f_load,f_store")
 173    (set_attr "length" "8,8,8,4,4,4,4,4")
 174    (set_attr "pool_range"     "*,4096,*,*,*,*,1020,*")
 175    (set_attr "neg_pool_range" "*,   0,*,*,*,*,1008,*")]
 176 )
 177
 178
 179 ;; SFmode moves
 180 ;; Disparage the w<->r cases because reloading an invalid address is
 181 ;; preferable to loading the value via integer registers.
 182
 183 (define_insn "*movsf_vfp"
 184   [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t  ,Uv,r ,m,t,r")
 185         (match_operand:SF 1 "general_operand"      " ?r,t,Dv,UvE,t, mE,r,t,r"))]
 186   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
 187    && (   s_register_operand (operands[0], SFmode)
 188        || s_register_operand (operands[1], SFmode))"
 189   "*
 190   switch (which_alternative)
 191     {
 192     case 0:
 193       return \"fmsr%?\\t%0, %1\";
 194     case 1:
 195       return \"fmrs%?\\t%0, %1\";
 196     case 2:
 197       return \"fconsts%?\\t%0, #%G1\";
 198     case 3: case 4:
 199       return output_move_vfp (operands);
 200     case 5:
 201       return \"ldr%?\\t%0, %1\\t%@ float\";
 202     case 6:
 203       return \"str%?\\t%1, %0\\t%@ float\";
 204     case 7:
 205       return \"fcpys%?\\t%0, %1\";
 206     case 8:
 207       return \"mov%?\\t%0, %1\\t%@ float\";
 208     default:
 209       gcc_unreachable ();
 210     }
 211   "
 212   [(set_attr "predicable" "yes")
 213    (set_attr "type"
 214      "r_2_f,f_2_r,farith,f_loads,f_stores,load1,store1,ffarith,*")
 215    (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
 216    (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
 217 )
 218
 219 (define_insn "*thumb2_movsf_vfp"
 220   [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t  ,Uv,r ,m,t,r")
 221         (match_operand:SF 1 "general_operand"      " ?r,t,Dv,UvE,t, mE,r,t,r"))]
 222   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
 223    && (   s_register_operand (operands[0], SFmode)
 224        || s_register_operand (operands[1], SFmode))"
 225   "*
 226   switch (which_alternative)
 227     {
 228     case 0:
 229       return \"fmsr%?\\t%0, %1\";
 230     case 1:
 231       return \"fmrs%?\\t%0, %1\";
 232     case 2:
 233       return \"fconsts%?\\t%0, #%G1\";
 234     case 3: case 4:
 235       return output_move_vfp (operands);
 236     case 5:
 237       return \"ldr%?\\t%0, %1\\t%@ float\";
 238     case 6:
 239       return \"str%?\\t%1, %0\\t%@ float\";
 240     case 7:
 241       return \"fcpys%?\\t%0, %1\";
 242     case 8:
 243       return \"mov%?\\t%0, %1\\t%@ float\";
 244     default:
 245       gcc_unreachable ();
 246     }
 247   "
 248   [(set_attr "predicable" "yes")
 249    (set_attr "type"
 250      "r_2_f,f_2_r,farith,f_load,f_store,load1,store1,ffarith,*")
 251    (set_attr "pool_range" "*,*,*,1020,*,4092,*,*,*")
 252    (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
 253 )
 254
 255
 256 ;; DFmode moves
 257
 258 (define_insn "*movdf_vfp"
 259   [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w  ,Uv,w,r")
 260         (match_operand:DF 1 "soft_df_operand"              " ?r,w,Dv,mF,r,UvF,w, w,r"))]
 261   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
 262    && (   register_operand (operands[0], DFmode)
 263        || register_operand (operands[1], DFmode))"
 264   "*
 265   {
 266     switch (which_alternative)
 267       {
 268       case 0:
 269         return \"fmdrr%?\\t%P0, %Q1, %R1\";
 270       case 1:
 271         return \"fmrrd%?\\t%Q0, %R0, %P1\";
 272       case 2:
 273         return \"fconstd%?\\t%P0, #%G1\";
 274       case 3: case 4:
 275         return output_move_double (operands);
 276       case 5: case 6:
 277         return output_move_vfp (operands);
 278       case 7:
 279         return \"fcpyd%?\\t%P0, %P1\";
 280       case 8:
 281         return \"#\";
 282       default:
 283         gcc_unreachable ();
 284       }
 285     }
 286   "
 287   [(set_attr "type"
 288      "r_2_f,f_2_r,farith,f_loadd,f_stored,load2,store2,ffarith,*")
 289    (set_attr "length" "4,4,4,8,8,4,4,4,8")
 290    (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*")
 291    (set_attr "neg_pool_range" "*,*,*,1008,*,1008,*,*,*")]
 292 )
 293
 294 (define_insn "*thumb2_movdf_vfp"
 295   [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w  ,Uv,w,r")
 296         (match_operand:DF 1 "soft_df_operand"              " ?r,w,Dv,mF,r,UvF,w, w,r"))]
 297   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
 298   "*
 299   {
 300     switch (which_alternative)
 301       {
 302       case 0:
 303         return \"fmdrr%?\\t%P0, %Q1, %R1\";
 304       case 1:
 305         return \"fmrrd%?\\t%Q0, %R0, %P1\";
 306       case 2:
 307         return \"fconstd%?\\t%P0, #%G1\";
 308       case 3: case 4: case 8:
 309         return output_move_double (operands);
 310       case 5: case 6:
 311         return output_move_vfp (operands);
 312       case 7:
 313         return \"fcpyd%?\\t%P0, %P1\";
 314       default:
 315         abort ();
 316       }
 317     }
 318   "
 319   [(set_attr "type"
 320      "r_2_f,f_2_r,farith,load2,store2,f_load,f_store,ffarith,*")
 321    (set_attr "length" "4,4,4,8,8,4,4,4,8")
 322    (set_attr "pool_range" "*,*,*,4096,*,1020,*,*,*")
 323    (set_attr "neg_pool_range" "*,*,*,0,*,1008,*,*,*")]
 324 )
 325
 326
 327 ;; Conditional move patterns
 328
 329 (define_insn "*movsfcc_vfp"
 330   [(set (match_operand:SF   0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
 331         (if_then_else:SF
 332           (match_operator   3 "arm_comparison_operator"
 333             [(match_operand 4 "cc_register" "") (const_int 0)])
 334           (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
 335           (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
 336   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
 337   "@
 338    fcpys%D3\\t%0, %2
 339    fcpys%d3\\t%0, %1
 340    fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
 341    fmsr%D3\\t%0, %2
 342    fmsr%d3\\t%0, %1
 343    fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
 344    fmrs%D3\\t%0, %2
 345    fmrs%d3\\t%0, %1
 346    fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
 347    [(set_attr "conds" "use")
 348     (set_attr "length" "4,4,8,4,4,8,4,4,8")
 349     (set_attr "type" "ffarith,ffarith,ffarith,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
 350 )
 351
 352 (define_insn "*thumb2_movsfcc_vfp"
 353   [(set (match_operand:SF   0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
 354         (if_then_else:SF
 355           (match_operator   3 "arm_comparison_operator"
 356             [(match_operand 4 "cc_register" "") (const_int 0)])
 357           (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
 358           (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
 359   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
 360   "@
 361    it\\t%D3\;fcpys%D3\\t%0, %2
 362    it\\t%d3\;fcpys%d3\\t%0, %1
 363    ite\\t%D3\;fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
 364    it\\t%D3\;fmsr%D3\\t%0, %2
 365    it\\t%d3\;fmsr%d3\\t%0, %1
 366    ite\\t%D3\;fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
 367    it\\t%D3\;fmrs%D3\\t%0, %2
 368    it\\t%d3\;fmrs%d3\\t%0, %1
 369    ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
 370    [(set_attr "conds" "use")
 371     (set_attr "length" "6,6,10,6,6,10,6,6,10")
 372     (set_attr "type" "ffarith,ffarith,ffarith,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
 373 )
 374
 375 (define_insn "*movdfcc_vfp"
 376   [(set (match_operand:DF   0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
 377         (if_then_else:DF
 378           (match_operator   3 "arm_comparison_operator"
 379             [(match_operand 4 "cc_register" "") (const_int 0)])
 380           (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
 381           (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
 382   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
 383   "@
 384    fcpyd%D3\\t%P0, %P2
 385    fcpyd%d3\\t%P0, %P1
 386    fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
 387    fmdrr%D3\\t%P0, %Q2, %R2
 388    fmdrr%d3\\t%P0, %Q1, %R1
 389    fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
 390    fmrrd%D3\\t%Q0, %R0, %P2
 391    fmrrd%d3\\t%Q0, %R0, %P1
 392    fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
 393    [(set_attr "conds" "use")
 394     (set_attr "length" "4,4,8,4,4,8,4,4,8")
 395     (set_attr "type" "ffarith,ffarith,ffarith,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
 396 )
 397
 398 (define_insn "*thumb2_movdfcc_vfp"
 399   [(set (match_operand:DF   0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
 400         (if_then_else:DF
 401           (match_operator   3 "arm_comparison_operator"
 402             [(match_operand 4 "cc_register" "") (const_int 0)])
 403           (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
 404           (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
 405   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
 406   "@
 407    it\\t%D3\;fcpyd%D3\\t%P0, %P2
 408    it\\t%d3\;fcpyd%d3\\t%P0, %P1
 409    ite\\t%D3\;fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
 410    it\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2
 411    it\t%d3\;fmdrr%d3\\t%P0, %Q1, %R1
 412    ite\\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
 413    it\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2
 414    it\t%d3\;fmrrd%d3\\t%Q0, %R0, %P1
 415    ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
 416    [(set_attr "conds" "use")
 417     (set_attr "length" "6,6,10,6,6,10,6,6,10")
 418     (set_attr "type" "ffarith,ffarith,ffarith,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
 419 )
 420
 421
 422 ;; Sign manipulation functions
 423
 424 (define_insn "*abssf2_vfp"
 425   [(set (match_operand:SF         0 "s_register_operand" "=t")
 426         (abs:SF (match_operand:SF 1 "s_register_operand" "t")))]
 427   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 428   "fabss%?\\t%0, %1"
 429   [(set_attr "predicable" "yes")
 430    (set_attr "type" "ffarith")]
 431 )
 432
 433 (define_insn "*absdf2_vfp"
 434   [(set (match_operand:DF         0 "s_register_operand" "=w")
 435         (abs:DF (match_operand:DF 1 "s_register_operand" "w")))]
 436   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 437   "fabsd%?\\t%P0, %P1"
 438   [(set_attr "predicable" "yes")
 439    (set_attr "type" "ffarith")]
 440 )
 441
 442 (define_insn "*negsf2_vfp"
 443   [(set (match_operand:SF         0 "s_register_operand" "=t,?r")
 444         (neg:SF (match_operand:SF 1 "s_register_operand" "t,r")))]
 445   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 446   "@
 447    fnegs%?\\t%0, %1
 448    eor%?\\t%0, %1, #-2147483648"
 449   [(set_attr "predicable" "yes")
 450    (set_attr "type" "ffarith")]
 451 )
 452
 453 (define_insn_and_split "*negdf2_vfp"
 454   [(set (match_operand:DF         0 "s_register_operand" "=w,?r,?r")
 455         (neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))]
 456   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 457   "@
 458    fnegd%?\\t%P0, %P1
 459    #
 460    #"
 461   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && reload_completed
 462    && arm_general_register_operand (operands[0], DFmode)"
 463   [(set (match_dup 0) (match_dup 1))]
 464   "
 465   if (REGNO (operands[0]) == REGNO (operands[1]))
 466     {
 467       operands[0] = gen_highpart (SImode, operands[0]);
 468       operands[1] = gen_rtx_XOR (SImode, operands[0], GEN_INT (0x80000000));
 469     }
 470   else
 471     {
 472       rtx in_hi, in_lo, out_hi, out_lo;
 473
 474       in_hi = gen_rtx_XOR (SImode, gen_highpart (SImode, operands[1]),
 475                            GEN_INT (0x80000000));
 476       in_lo = gen_lowpart (SImode, operands[1]);
 477       out_hi = gen_highpart (SImode, operands[0]);
 478       out_lo = gen_lowpart (SImode, operands[0]);
 479
 480       if (REGNO (in_lo) == REGNO (out_hi))
 481         {
 482           emit_insn (gen_rtx_SET (SImode, out_lo, in_lo));
 483           operands[0] = out_hi;
 484           operands[1] = in_hi;
 485         }
 486       else
 487         {
 488           emit_insn (gen_rtx_SET (SImode, out_hi, in_hi));
 489           operands[0] = out_lo;
 490           operands[1] = in_lo;
 491         }
 492     }
 493   "
 494   [(set_attr "predicable" "yes")
 495    (set_attr "length" "4,4,8")
 496    (set_attr "type" "ffarith")]
 497 )
 498
 499
 500 ;; Arithmetic insns
 501
 502 (define_insn "*addsf3_vfp"
 503   [(set (match_operand:SF          0 "s_register_operand" "=t")
 504         (plus:SF (match_operand:SF 1 "s_register_operand" "t")
 505                  (match_operand:SF 2 "s_register_operand" "t")))]
 506   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 507   "fadds%?\\t%0, %1, %2"
 508   [(set_attr "predicable" "yes")
 509    (set_attr "type" "farith")]
 510 )
 511
 512 (define_insn "*adddf3_vfp"
 513   [(set (match_operand:DF          0 "s_register_operand" "=w")
 514         (plus:DF (match_operand:DF 1 "s_register_operand" "w")
 515                  (match_operand:DF 2 "s_register_operand" "w")))]
 516   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 517   "faddd%?\\t%P0, %P1, %P2"
 518   [(set_attr "predicable" "yes")
 519    (set_attr "type" "farith")]
 520 )
 521
 522
 523 (define_insn "*subsf3_vfp"
 524   [(set (match_operand:SF           0 "s_register_operand" "=t")
 525         (minus:SF (match_operand:SF 1 "s_register_operand" "t")
 526                   (match_operand:SF 2 "s_register_operand" "t")))]
 527   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 528   "fsubs%?\\t%0, %1, %2"
 529   [(set_attr "predicable" "yes")
 530    (set_attr "type" "farith")]
 531 )
 532
 533 (define_insn "*subdf3_vfp"
 534   [(set (match_operand:DF           0 "s_register_operand" "=w")
 535         (minus:DF (match_operand:DF 1 "s_register_operand" "w")
 536                   (match_operand:DF 2 "s_register_operand" "w")))]
 537   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 538   "fsubd%?\\t%P0, %P1, %P2"
 539   [(set_attr "predicable" "yes")
 540    (set_attr "type" "farith")]
 541 )
 542
 543
 544 ;; Division insns
 545
 546 (define_insn "*divsf3_vfp"
 547   [(set (match_operand:SF         0 "s_register_operand" "+t")
 548         (div:SF (match_operand:SF 1 "s_register_operand" "t")
 549                 (match_operand:SF 2 "s_register_operand" "t")))]
 550   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 551   "fdivs%?\\t%0, %1, %2"
 552   [(set_attr "predicable" "yes")
 553    (set_attr "type" "fdivs")]
 554 )
 555
 556 (define_insn "*divdf3_vfp"
 557   [(set (match_operand:DF         0 "s_register_operand" "+w")
 558         (div:DF (match_operand:DF 1 "s_register_operand" "w")
 559                 (match_operand:DF 2 "s_register_operand" "w")))]
 560   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 561   "fdivd%?\\t%P0, %P1, %P2"
 562   [(set_attr "predicable" "yes")
 563    (set_attr "type" "fdivd")]
 564 )
 565
 566
 567 ;; Multiplication insns
 568
 569 (define_insn "*mulsf3_vfp"
 570   [(set (match_operand:SF          0 "s_register_operand" "+t")
 571         (mult:SF (match_operand:SF 1 "s_register_operand" "t")
 572                  (match_operand:SF 2 "s_register_operand" "t")))]
 573   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 574   "fmuls%?\\t%0, %1, %2"
 575   [(set_attr "predicable" "yes")
 576    (set_attr "type" "farith")]
 577 )
 578
 579 (define_insn "*muldf3_vfp"
 580   [(set (match_operand:DF          0 "s_register_operand" "+w")
 581         (mult:DF (match_operand:DF 1 "s_register_operand" "w")
 582                  (match_operand:DF 2 "s_register_operand" "w")))]
 583   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 584   "fmuld%?\\t%P0, %P1, %P2"
 585   [(set_attr "predicable" "yes")
 586    (set_attr "type" "fmul")]
 587 )
 588
 589
 590 (define_insn "*mulsf3negsf_vfp"
 591   [(set (match_operand:SF                  0 "s_register_operand" "+t")
 592         (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
 593                  (match_operand:SF         2 "s_register_operand" "t")))]
 594   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 595   "fnmuls%?\\t%0, %1, %2"
 596   [(set_attr "predicable" "yes")
 597    (set_attr "type" "farith")]
 598 )
 599
 600 (define_insn "*muldf3negdf_vfp"
 601   [(set (match_operand:DF                  0 "s_register_operand" "+w")
 602         (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
 603                  (match_operand:DF         2 "s_register_operand" "w")))]
 604   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 605   "fnmuld%?\\t%P0, %P1, %P2"
 606   [(set_attr "predicable" "yes")
 607    (set_attr "type" "fmul")]
 608 )
 609
 610
 611 ;; Multiply-accumulate insns
 612
 613 ;; 0 = 1 * 2 + 0
 614 (define_insn "*mulsf3addsf_vfp"
 615   [(set (match_operand:SF                   0 "s_register_operand" "=t")
 616         (plus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
 617                           (match_operand:SF 3 "s_register_operand" "t"))
 618                  (match_operand:SF          1 "s_register_operand" "0")))]
 619   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 620   "fmacs%?\\t%0, %2, %3"
 621   [(set_attr "predicable" "yes")
 622    (set_attr "type" "farith")]
 623 )
 624
 625 (define_insn "*muldf3adddf_vfp"
 626   [(set (match_operand:DF                   0 "s_register_operand" "=w")
 627         (plus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
 628                           (match_operand:DF 3 "s_register_operand" "w"))
 629                  (match_operand:DF          1 "s_register_operand" "0")))]
 630   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 631   "fmacd%?\\t%P0, %P2, %P3"
 632   [(set_attr "predicable" "yes")
 633    (set_attr "type" "fmul")]
 634 )
 635
 636 ;; 0 = 1 * 2 - 0
 637 (define_insn "*mulsf3subsf_vfp"
 638   [(set (match_operand:SF                    0 "s_register_operand" "=t")
 639         (minus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
 640                            (match_operand:SF 3 "s_register_operand" "t"))
 641                   (match_operand:SF          1 "s_register_operand" "0")))]
 642   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 643   "fmscs%?\\t%0, %2, %3"
 644   [(set_attr "predicable" "yes")
 645    (set_attr "type" "farith")]
 646 )
 647
 648 (define_insn "*muldf3subdf_vfp"
 649   [(set (match_operand:DF                    0 "s_register_operand" "=w")
 650         (minus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
 651                            (match_operand:DF 3 "s_register_operand" "w"))
 652                   (match_operand:DF          1 "s_register_operand" "0")))]
 653   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 654   "fmscd%?\\t%P0, %P2, %P3"
 655   [(set_attr "predicable" "yes")
 656    (set_attr "type" "fmul")]
 657 )
 658
 659 ;; 0 = -(1 * 2) + 0
 660 (define_insn "*mulsf3negsfaddsf_vfp"
 661   [(set (match_operand:SF                    0 "s_register_operand" "=t")
 662         (minus:SF (match_operand:SF          1 "s_register_operand" "0")
 663                   (mult:SF (match_operand:SF 2 "s_register_operand" "t")
 664                            (match_operand:SF 3 "s_register_operand" "t"))))]
 665   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 666   "fnmacs%?\\t%0, %2, %3"
 667   [(set_attr "predicable" "yes")
 668    (set_attr "type" "farith")]
 669 )
 670
 671 (define_insn "*fmuldf3negdfadddf_vfp"
 672   [(set (match_operand:DF                    0 "s_register_operand" "=w")
 673         (minus:DF (match_operand:DF          1 "s_register_operand" "0")
 674                   (mult:DF (match_operand:DF 2 "s_register_operand" "w")
 675                            (match_operand:DF 3 "s_register_operand" "w"))))]
 676   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 677   "fnmacd%?\\t%P0, %P2, %P3"
 678   [(set_attr "predicable" "yes")
 679    (set_attr "type" "fmul")]
 680 )
 681
 682
 683 ;; 0 = -(1 * 2) - 0
 684 (define_insn "*mulsf3negsfsubsf_vfp"
 685   [(set (match_operand:SF                     0 "s_register_operand" "=t")
 686         (minus:SF (mult:SF
 687                     (neg:SF (match_operand:SF 2 "s_register_operand" "t"))
 688                     (match_operand:SF         3 "s_register_operand" "t"))
 689                   (match_operand:SF           1 "s_register_operand" "0")))]
 690   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 691   "fnmscs%?\\t%0, %2, %3"
 692   [(set_attr "predicable" "yes")
 693    (set_attr "type" "farith")]
 694 )
 695
 696 (define_insn "*muldf3negdfsubdf_vfp"
 697   [(set (match_operand:DF                     0 "s_register_operand" "=w")
 698         (minus:DF (mult:DF
 699                     (neg:DF (match_operand:DF 2 "s_register_operand" "w"))
 700                     (match_operand:DF         3 "s_register_operand" "w"))
 701                   (match_operand:DF           1 "s_register_operand" "0")))]
 702   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 703   "fnmscd%?\\t%P0, %P2, %P3"
 704   [(set_attr "predicable" "yes")
 705    (set_attr "type" "fmul")]
 706 )
 707
 708
 709 ;; Conversion routines
 710
 711 (define_insn "*extendsfdf2_vfp"
 712   [(set (match_operand:DF                  0 "s_register_operand" "=w")
 713         (float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))]
 714   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 715   "fcvtds%?\\t%P0, %1"
 716   [(set_attr "predicable" "yes")
 717    (set_attr "type" "f_cvt")]
 718 )
 719
 720 (define_insn "*truncdfsf2_vfp"
 721   [(set (match_operand:SF                  0 "s_register_operand" "=t")
 722         (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))]
 723   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 724   "fcvtsd%?\\t%0, %P1"
 725   [(set_attr "predicable" "yes")
 726    (set_attr "type" "f_cvt")]
 727 )
 728
 729 (define_insn "*truncsisf2_vfp"
 730   [(set (match_operand:SI                 0 "s_register_operand" "=t")
 731         (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
 732   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 733   "ftosizs%?\\t%0, %1"
 734   [(set_attr "predicable" "yes")
 735    (set_attr "type" "f_cvt")]
 736 )
 737
 738 (define_insn "*truncsidf2_vfp"
 739   [(set (match_operand:SI                 0 "s_register_operand" "=t")
 740         (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))]
 741   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 742   "ftosizd%?\\t%0, %P1"
 743   [(set_attr "predicable" "yes")
 744    (set_attr "type" "f_cvt")]
 745 )
 746
 747
 748 (define_insn "fixuns_truncsfsi2"
 749   [(set (match_operand:SI                 0 "s_register_operand" "=t")
 750         (unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
 751   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 752   "ftouizs%?\\t%0, %1"
 753   [(set_attr "predicable" "yes")
 754    (set_attr "type" "f_cvt")]
 755 )
 756
 757 (define_insn "fixuns_truncdfsi2"
 758   [(set (match_operand:SI                 0 "s_register_operand" "=t")
 759         (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))]
 760   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 761   "ftouizd%?\\t%0, %P1"
 762   [(set_attr "predicable" "yes")
 763    (set_attr "type" "f_cvt")]
 764 )
 765
 766
 767 (define_insn "*floatsisf2_vfp"
 768   [(set (match_operand:SF           0 "s_register_operand" "=t")
 769         (float:SF (match_operand:SI 1 "s_register_operand" "t")))]
 770   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 771   "fsitos%?\\t%0, %1"
 772   [(set_attr "predicable" "yes")
 773    (set_attr "type" "f_cvt")]
 774 )
 775
 776 (define_insn "*floatsidf2_vfp"
 777   [(set (match_operand:DF           0 "s_register_operand" "=w")
 778         (float:DF (match_operand:SI 1 "s_register_operand" "t")))]
 779   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 780   "fsitod%?\\t%P0, %1"
 781   [(set_attr "predicable" "yes")
 782    (set_attr "type" "f_cvt")]
 783 )
 784
 785
 786 (define_insn "floatunssisf2"
 787   [(set (match_operand:SF           0 "s_register_operand" "=t")
 788         (unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))]
 789   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 790   "fuitos%?\\t%0, %1"
 791   [(set_attr "predicable" "yes")
 792    (set_attr "type" "f_cvt")]
 793 )
 794
 795 (define_insn "floatunssidf2"
 796   [(set (match_operand:DF           0 "s_register_operand" "=w")
 797         (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))]
 798   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 799   "fuitod%?\\t%P0, %1"
 800   [(set_attr "predicable" "yes")
 801    (set_attr "type" "f_cvt")]
 802 )
 803
 804
 805 ;; Sqrt insns.
 806
 807 (define_insn "*sqrtsf2_vfp"
 808   [(set (match_operand:SF          0 "s_register_operand" "=t")
 809         (sqrt:SF (match_operand:SF 1 "s_register_operand" "t")))]
 810   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 811   "fsqrts%?\\t%0, %1"
 812   [(set_attr "predicable" "yes")
 813    (set_attr "type" "fdivs")]
 814 )
 815
 816 (define_insn "*sqrtdf2_vfp"
 817   [(set (match_operand:DF          0 "s_register_operand" "=w")
 818         (sqrt:DF (match_operand:DF 1 "s_register_operand" "w")))]
 819   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 820   "fsqrtd%?\\t%P0, %P1"
 821   [(set_attr "predicable" "yes")
 822    (set_attr "type" "fdivd")]
 823 )
 824
 825
 826 ;; Patterns to split/copy vfp condition flags.
 827
 828 (define_insn "*movcc_vfp"
 829   [(set (reg CC_REGNUM)
 830         (reg VFPCC_REGNUM))]
 831   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 832   "fmstat%?"
 833   [(set_attr "conds" "set")
 834    (set_attr "type" "f_flag")]
 835 )
 836
 837 (define_insn_and_split "*cmpsf_split_vfp"
 838   [(set (reg:CCFP CC_REGNUM)
 839         (compare:CCFP (match_operand:SF 0 "s_register_operand"  "t")
 840                       (match_operand:SF 1 "vfp_compare_operand" "tG")))]
 841   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 842   "#"
 843   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 844   [(set (reg:CCFP VFPCC_REGNUM)
 845         (compare:CCFP (match_dup 0)
 846                       (match_dup 1)))
 847    (set (reg:CCFP CC_REGNUM)
 848         (reg:CCFP VFPCC_REGNUM))]
 849   ""
 850 )
 851
 852 (define_insn_and_split "*cmpsf_trap_split_vfp"
 853   [(set (reg:CCFPE CC_REGNUM)
 854         (compare:CCFPE (match_operand:SF 0 "s_register_operand"  "t")
 855                        (match_operand:SF 1 "vfp_compare_operand" "tG")))]
 856   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 857   "#"
 858   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 859   [(set (reg:CCFPE VFPCC_REGNUM)
 860         (compare:CCFPE (match_dup 0)
 861                        (match_dup 1)))
 862    (set (reg:CCFPE CC_REGNUM)
 863         (reg:CCFPE VFPCC_REGNUM))]
 864   ""
 865 )
 866
 867 (define_insn_and_split "*cmpdf_split_vfp"
 868   [(set (reg:CCFP CC_REGNUM)
 869         (compare:CCFP (match_operand:DF 0 "s_register_operand"  "w")
 870                       (match_operand:DF 1 "vfp_compare_operand" "wG")))]
 871   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 872   "#"
 873   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 874   [(set (reg:CCFP VFPCC_REGNUM)
 875         (compare:CCFP (match_dup 0)
 876                        (match_dup 1)))
 877    (set (reg:CCFP CC_REGNUM)
 878         (reg:CCFPE VFPCC_REGNUM))]
 879   ""
 880 )
 881
 882 (define_insn_and_split "*cmpdf_trap_split_vfp"
 883   [(set (reg:CCFPE CC_REGNUM)
 884         (compare:CCFPE (match_operand:DF 0 "s_register_operand"  "w")
 885                        (match_operand:DF 1 "vfp_compare_operand" "wG")))]
 886   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 887   "#"
 888   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 889   [(set (reg:CCFPE VFPCC_REGNUM)
 890         (compare:CCFPE (match_dup 0)
 891                        (match_dup 1)))
 892    (set (reg:CCFPE CC_REGNUM)
 893         (reg:CCFPE VFPCC_REGNUM))]
 894   ""
 895 )
 896
 897
 898 ;; Comparison patterns
 899
 900 (define_insn "*cmpsf_vfp"
 901   [(set (reg:CCFP VFPCC_REGNUM)
 902         (compare:CCFP (match_operand:SF 0 "s_register_operand"  "t,t")
 903                       (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
 904   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 905   "@
 906    fcmps%?\\t%0, %1
 907    fcmpzs%?\\t%0"
 908   [(set_attr "predicable" "yes")
 909    (set_attr "type" "ffarith")]
 910 )
 911
 912 (define_insn "*cmpsf_trap_vfp"
 913   [(set (reg:CCFPE VFPCC_REGNUM)
 914         (compare:CCFPE (match_operand:SF 0 "s_register_operand"  "t,t")
 915                        (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
 916   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 917   "@
 918    fcmpes%?\\t%0, %1
 919    fcmpezs%?\\t%0"
 920   [(set_attr "predicable" "yes")
 921    (set_attr "type" "ffarith")]
 922 )
 923
 924 (define_insn "*cmpdf_vfp"
 925   [(set (reg:CCFP VFPCC_REGNUM)
 926         (compare:CCFP (match_operand:DF 0 "s_register_operand"  "w,w")
 927                       (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
 928   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 929   "@
 930    fcmpd%?\\t%P0, %P1
 931    fcmpzd%?\\t%P0"
 932   [(set_attr "predicable" "yes")
 933    (set_attr "type" "ffarith")]
 934 )
 935
 936 (define_insn "*cmpdf_trap_vfp"
 937   [(set (reg:CCFPE VFPCC_REGNUM)
 938         (compare:CCFPE (match_operand:DF 0 "s_register_operand"  "w,w")
 939                        (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
 940   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 941   "@
 942    fcmped%?\\t%P0, %P1
 943    fcmpezd%?\\t%P0"
 944   [(set_attr "predicable" "yes")
 945    (set_attr "type" "ffarith")]
 946 )
 947
 948
 949 ;; Store multiple insn used in function prologue.
 950
 951 (define_insn "*push_multi_vfp"
 952   [(match_parallel 2 "multi_register_push"
 953     [(set (match_operand:BLK 0 "memory_operand" "=m")
 954           (unspec:BLK [(match_operand:DF 1 "s_register_operand" "w")]
 955                       UNSPEC_PUSH_MULT))])]
 956   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 957   "* return vfp_output_fstmd (operands);"
 958   [(set_attr "type" "f_stored")]
 959 )
 960
 961
 962 ;; Unimplemented insns:
 963 ;; fldm*
 964 ;; fstm*
 965 ;; fmdhr et al (VFPv1)
 966 ;; Support for xD (single precision only) variants.
 967 ;; fmrrs, fmsrr