gcc/config/arm/vfp.md

   1 ;; ARM VFP instruction patterns
   2 ;; Copyright (C) 2003, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
   3 ;; Written by CodeSourcery.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.  */
  20
  21 ;; Additional register numbers
  22 (define_constants
  23   [(VFPCC_REGNUM 127)]
  24 )
  25
  26 ;; The VFP "type" attributes differ from those used in the FPA model.
  27 ;; fcpys        Single precision cpy.
  28 ;; ffariths     Single precision abs, neg.
  29 ;; ffarithd     Double precision abs, neg, cpy.
  30 ;; fadds        Single precision add/sub.
  31 ;; faddd        Double precision add/sub.
  32 ;; fconsts      Single precision load immediate.
  33 ;; fconstd      Double precision load immediate.
  34 ;; fcmps        Single precision comparison.
  35 ;; fcmpd        Double precision comparison.
  36 ;; fmuls        Single precision multiply.
  37 ;; fmuld        Double precision multiply.
  38 ;; fmacs        Single precision multiply-accumulate.
  39 ;; fmacd        Double precision multiply-accumulate.
  40 ;; fdivs        Single precision sqrt or division.
  41 ;; fdivd        Double precision sqrt or division.
  42 ;; f_flag       fmstat operation
  43 ;; f_load[sd]   Floating point load from memory.
  44 ;; f_store[sd]  Floating point store to memory.
  45 ;; f_2_r        Transfer vfp to arm reg.
  46 ;; r_2_f        Transfer arm to vfp reg.
  47 ;; f_cvt        Convert floating<->integral
  48
  49 ;; SImode moves
  50 ;; ??? For now do not allow loading constants into vfp regs.  This causes
  51 ;; problems because small constants get converted into adds.
  52 (define_insn "*arm_movsi_vfp"
  53   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv")
  54       (match_operand:SI 1 "general_operand"        "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
  55   "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT
  56    && (   s_register_operand (operands[0], SImode)
  57        || s_register_operand (operands[1], SImode))"
  58   "*
  59   switch (which_alternative)
  60     {
  61     case 0: case 1:
  62       return \"mov%?\\t%0, %1\";
  63     case 2:
  64       return \"mvn%?\\t%0, #%B1\";
  65     case 3:
  66       return \"movw%?\\t%0, %1\";
  67     case 4:
  68       return \"ldr%?\\t%0, %1\";
  69     case 5:
  70       return \"str%?\\t%1, %0\";
  71     case 6:
  72       return \"fmsr%?\\t%0, %1\\t%@ int\";
  73     case 7:
  74       return \"fmrs%?\\t%0, %1\\t%@ int\";
  75     case 8:
  76       return \"fcpys%?\\t%0, %1\\t%@ int\";
  77     case 9: case 10:
  78       return output_move_vfp (operands);
  79     default:
  80       gcc_unreachable ();
  81     }
  82   "
  83   [(set_attr "predicable" "yes")
  84    (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
  85    (set_attr "pool_range"     "*,*,*,*,4096,*,*,*,*,1020,*")
  86    (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
  87 )
  88
  89 (define_insn "*thumb2_movsi_vfp"
  90   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m,*t,r, *t,*t, *Uv")
  91       (match_operand:SI 1 "general_operand"        "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
  92   "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT
  93    && (   s_register_operand (operands[0], SImode)
  94        || s_register_operand (operands[1], SImode))"
  95   "*
  96   switch (which_alternative)
  97     {
  98     case 0: case 1:
  99       return \"mov%?\\t%0, %1\";
 100     case 2:
 101       return \"mvn%?\\t%0, #%B1\";
 102     case 3:
 103       return \"movw%?\\t%0, %1\";
 104     case 4:
 105       return \"ldr%?\\t%0, %1\";
 106     case 5:
 107       return \"str%?\\t%1, %0\";
 108     case 6:
 109       return \"fmsr%?\\t%0, %1\\t%@ int\";
 110     case 7:
 111       return \"fmrs%?\\t%0, %1\\t%@ int\";
 112     case 8:
 113       return \"fcpys%?\\t%0, %1\\t%@ int\";
 114     case 9: case 10:
 115       return output_move_vfp (operands);
 116     default:
 117       gcc_unreachable ();
 118     }
 119   "
 120   [(set_attr "predicable" "yes")
 121    (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_load,f_store")
 122    (set_attr "pool_range"     "*,*,*,*,4096,*,*,*,*,1020,*")
 123    (set_attr "neg_pool_range" "*,*,*,*,   0,*,*,*,*,1008,*")]
 124 )
 125
 126
 127 ;; DImode moves
 128
 129 (define_insn "*arm_movdi_vfp"
 130   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv")
 131         (match_operand:DI 1 "di_operand"              "rIK,mi,r,r,w,w,Uvi,w"))]
 132   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
 133    && (   register_operand (operands[0], DImode)
 134        || register_operand (operands[1], DImode))"
 135   "*
 136   switch (which_alternative)
 137     {
 138     case 0:
 139       return \"#\";
 140     case 1:
 141     case 2:
 142       return output_move_double (operands);
 143     case 3:
 144       return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
 145     case 4:
 146       return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
 147     case 5:
 148       return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
 149     case 6: case 7:
 150       return output_move_vfp (operands);
 151     default:
 152       gcc_unreachable ();
 153     }
 154   "
 155   [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
 156    (set_attr "length" "8,8,8,4,4,4,4,4")
 157    (set_attr "pool_range"     "*,1020,*,*,*,*,1020,*")
 158    (set_attr "neg_pool_range" "*,1008,*,*,*,*,1008,*")]
 159 )
 160
 161 (define_insn "*thumb2_movdi_vfp"
 162   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv")
 163         (match_operand:DI 1 "di_operand"              "rIK,mi,r,r,w,w,Uvi,w"))]
 164   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
 165   "*
 166   switch (which_alternative)
 167     {
 168     case 0: case 1: case 2:
 169       return (output_move_double (operands));
 170     case 3:
 171       return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
 172     case 4:
 173       return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
 174     case 5:
 175       return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
 176     case 6: case 7:
 177       return output_move_vfp (operands);
 178     default:
 179       abort ();
 180     }
 181   "
 182   [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_load,f_store")
 183    (set_attr "length" "8,8,8,4,4,4,4,4")
 184    (set_attr "pool_range"     "*,4096,*,*,*,*,1020,*")
 185    (set_attr "neg_pool_range" "*,   0,*,*,*,*,1008,*")]
 186 )
 187
 188 ;; HFmode moves
 189 (define_insn "*movhf_vfp"
 190   [(set (match_operand:HF 0 "nonimmediate_operand" "= t,Um,r,m,t,r,t,r,r")
 191         (match_operand:HF 1 "general_operand"      " Um, t,m,r,t,r,r,t,F"))]
 192   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_NEON_FP16
 193    && (   s_register_operand (operands[0], HFmode)
 194        || s_register_operand (operands[1], HFmode))"
 195   "*
 196   switch (which_alternative)
 197     {
 198     case 0:     /* S register from memory */
 199       return \"vld1.16\\t{%z0}, %A1\";
 200     case 1:     /* memory from S register */
 201       return \"vst1.16\\t{%z1}, %A0\";
 202     case 2:     /* ARM register from memory */
 203       return \"ldrh\\t%0, %1\\t%@ __fp16\";
 204     case 3:     /* memory from ARM register */
 205       return \"strh\\t%1, %0\\t%@ __fp16\";
 206     case 4:     /* S register from S register */
 207       return \"fcpys\\t%0, %1\";
 208     case 5:     /* ARM register from ARM register */
 209       return \"mov\\t%0, %1\\t%@ __fp16\";
 210     case 6:     /* S register from ARM register */
 211       return \"fmsr\\t%0, %1\";
 212     case 7:     /* ARM register from S register */
 213       return \"fmrs\\t%0, %1\";
 214     case 8:     /* ARM register from constant */
 215       {
 216         REAL_VALUE_TYPE r;
 217         long bits;
 218         rtx ops[4];
 219
 220         REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
 221         bits = real_to_target (NULL, &r, HFmode);
 222         ops[0] = operands[0];
 223         ops[1] = GEN_INT (bits);
 224         ops[2] = GEN_INT (bits & 0xff00);
 225         ops[3] = GEN_INT (bits & 0x00ff);
 226
 227         if (arm_arch_thumb2)
 228           output_asm_insn (\"movw\\t%0, %1\", ops);
 229         else
 230           output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
 231         return \"\";
 232        }
 233     default:
 234       gcc_unreachable ();
 235     }
 236   "
 237   [(set_attr "conds" "unconditional")
 238    (set_attr "type" "*,*,load1,store1,fcpys,*,r_2_f,f_2_r,*")
 239    (set_attr "neon_type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,*,*,*,*,*,*,*")
 240    (set_attr "length" "4,4,4,4,4,4,4,4,8")]
 241 )
 242
 243
 244 ;; SFmode moves
 245 ;; Disparage the w<->r cases because reloading an invalid address is
 246 ;; preferable to loading the value via integer registers.
 247
 248 (define_insn "*movsf_vfp"
 249   [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t  ,Uv,r ,m,t,r")
 250         (match_operand:SF 1 "general_operand"      " ?r,t,Dv,UvE,t, mE,r,t,r"))]
 251   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
 252    && (   s_register_operand (operands[0], SFmode)
 253        || s_register_operand (operands[1], SFmode))"
 254   "*
 255   switch (which_alternative)
 256     {
 257     case 0:
 258       return \"fmsr%?\\t%0, %1\";
 259     case 1:
 260       return \"fmrs%?\\t%0, %1\";
 261     case 2:
 262       return \"fconsts%?\\t%0, #%G1\";
 263     case 3: case 4:
 264       return output_move_vfp (operands);
 265     case 5:
 266       return \"ldr%?\\t%0, %1\\t%@ float\";
 267     case 6:
 268       return \"str%?\\t%1, %0\\t%@ float\";
 269     case 7:
 270       return \"fcpys%?\\t%0, %1\";
 271     case 8:
 272       return \"mov%?\\t%0, %1\\t%@ float\";
 273     default:
 274       gcc_unreachable ();
 275     }
 276   "
 277   [(set_attr "predicable" "yes")
 278    (set_attr "type"
 279      "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*")
 280    (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
 281    (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
 282 )
 283
 284 (define_insn "*thumb2_movsf_vfp"
 285   [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t  ,Uv,r ,m,t,r")
 286         (match_operand:SF 1 "general_operand"      " ?r,t,Dv,UvE,t, mE,r,t,r"))]
 287   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
 288    && (   s_register_operand (operands[0], SFmode)
 289        || s_register_operand (operands[1], SFmode))"
 290   "*
 291   switch (which_alternative)
 292     {
 293     case 0:
 294       return \"fmsr%?\\t%0, %1\";
 295     case 1:
 296       return \"fmrs%?\\t%0, %1\";
 297     case 2:
 298       return \"fconsts%?\\t%0, #%G1\";
 299     case 3: case 4:
 300       return output_move_vfp (operands);
 301     case 5:
 302       return \"ldr%?\\t%0, %1\\t%@ float\";
 303     case 6:
 304       return \"str%?\\t%1, %0\\t%@ float\";
 305     case 7:
 306       return \"fcpys%?\\t%0, %1\";
 307     case 8:
 308       return \"mov%?\\t%0, %1\\t%@ float\";
 309     default:
 310       gcc_unreachable ();
 311     }
 312   "
 313   [(set_attr "predicable" "yes")
 314    (set_attr "type"
 315      "r_2_f,f_2_r,fconsts,f_load,f_store,load1,store1,fcpys,*")
 316    (set_attr "pool_range" "*,*,*,1020,*,4092,*,*,*")
 317    (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
 318 )
 319
 320
 321 ;; DFmode moves
 322
 323 (define_insn "*movdf_vfp"
 324   [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w  ,Uv,w,r")
 325         (match_operand:DF 1 "soft_df_operand"              " ?r,w,Dv,mF,r,UvF,w, w,r"))]
 326   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
 327    && (   register_operand (operands[0], DFmode)
 328        || register_operand (operands[1], DFmode))"
 329   "*
 330   {
 331     switch (which_alternative)
 332       {
 333       case 0:
 334         return \"fmdrr%?\\t%P0, %Q1, %R1\";
 335       case 1:
 336         return \"fmrrd%?\\t%Q0, %R0, %P1\";
 337       case 2:
 338         return \"fconstd%?\\t%P0, #%G1\";
 339       case 3: case 4:
 340         return output_move_double (operands);
 341       case 5: case 6:
 342         return output_move_vfp (operands);
 343       case 7:
 344         return \"fcpyd%?\\t%P0, %P1\";
 345       case 8:
 346         return \"#\";
 347       default:
 348         gcc_unreachable ();
 349       }
 350     }
 351   "
 352   [(set_attr "type"
 353      "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
 354    (set_attr "length" "4,4,4,8,8,4,4,4,8")
 355    (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*")
 356    (set_attr "neg_pool_range" "*,*,*,1008,*,1008,*,*,*")]
 357 )
 358
 359 (define_insn "*thumb2_movdf_vfp"
 360   [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w  ,Uv,w,r")
 361         (match_operand:DF 1 "soft_df_operand"              " ?r,w,Dv,mF,r,UvF,w, w,r"))]
 362   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
 363   "*
 364   {
 365     switch (which_alternative)
 366       {
 367       case 0:
 368         return \"fmdrr%?\\t%P0, %Q1, %R1\";
 369       case 1:
 370         return \"fmrrd%?\\t%Q0, %R0, %P1\";
 371       case 2:
 372         return \"fconstd%?\\t%P0, #%G1\";
 373       case 3: case 4: case 8:
 374         return output_move_double (operands);
 375       case 5: case 6:
 376         return output_move_vfp (operands);
 377       case 7:
 378         return \"fcpyd%?\\t%P0, %P1\";
 379       default:
 380         abort ();
 381       }
 382     }
 383   "
 384   [(set_attr "type"
 385      "r_2_f,f_2_r,fconstd,load2,store2,f_load,f_store,ffarithd,*")
 386    (set_attr "length" "4,4,4,8,8,4,4,4,8")
 387    (set_attr "pool_range" "*,*,*,4096,*,1020,*,*,*")
 388    (set_attr "neg_pool_range" "*,*,*,0,*,1008,*,*,*")]
 389 )
 390
 391
 392 ;; Conditional move patterns
 393
 394 (define_insn "*movsfcc_vfp"
 395   [(set (match_operand:SF   0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
 396         (if_then_else:SF
 397           (match_operator   3 "arm_comparison_operator"
 398             [(match_operand 4 "cc_register" "") (const_int 0)])
 399           (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
 400           (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
 401   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
 402   "@
 403    fcpys%D3\\t%0, %2
 404    fcpys%d3\\t%0, %1
 405    fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
 406    fmsr%D3\\t%0, %2
 407    fmsr%d3\\t%0, %1
 408    fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
 409    fmrs%D3\\t%0, %2
 410    fmrs%d3\\t%0, %1
 411    fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
 412    [(set_attr "conds" "use")
 413     (set_attr "length" "4,4,8,4,4,8,4,4,8")
 414     (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
 415 )
 416
 417 (define_insn "*thumb2_movsfcc_vfp"
 418   [(set (match_operand:SF   0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
 419         (if_then_else:SF
 420           (match_operator   3 "arm_comparison_operator"
 421             [(match_operand 4 "cc_register" "") (const_int 0)])
 422           (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
 423           (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
 424   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
 425   "@
 426    it\\t%D3\;fcpys%D3\\t%0, %2
 427    it\\t%d3\;fcpys%d3\\t%0, %1
 428    ite\\t%D3\;fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
 429    it\\t%D3\;fmsr%D3\\t%0, %2
 430    it\\t%d3\;fmsr%d3\\t%0, %1
 431    ite\\t%D3\;fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
 432    it\\t%D3\;fmrs%D3\\t%0, %2
 433    it\\t%d3\;fmrs%d3\\t%0, %1
 434    ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
 435    [(set_attr "conds" "use")
 436     (set_attr "length" "6,6,10,6,6,10,6,6,10")
 437     (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
 438 )
 439
 440 (define_insn "*movdfcc_vfp"
 441   [(set (match_operand:DF   0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
 442         (if_then_else:DF
 443           (match_operator   3 "arm_comparison_operator"
 444             [(match_operand 4 "cc_register" "") (const_int 0)])
 445           (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
 446           (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
 447   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
 448   "@
 449    fcpyd%D3\\t%P0, %P2
 450    fcpyd%d3\\t%P0, %P1
 451    fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
 452    fmdrr%D3\\t%P0, %Q2, %R2
 453    fmdrr%d3\\t%P0, %Q1, %R1
 454    fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
 455    fmrrd%D3\\t%Q0, %R0, %P2
 456    fmrrd%d3\\t%Q0, %R0, %P1
 457    fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
 458    [(set_attr "conds" "use")
 459     (set_attr "length" "4,4,8,4,4,8,4,4,8")
 460     (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
 461 )
 462
 463 (define_insn "*thumb2_movdfcc_vfp"
 464   [(set (match_operand:DF   0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
 465         (if_then_else:DF
 466           (match_operator   3 "arm_comparison_operator"
 467             [(match_operand 4 "cc_register" "") (const_int 0)])
 468           (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
 469           (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
 470   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
 471   "@
 472    it\\t%D3\;fcpyd%D3\\t%P0, %P2
 473    it\\t%d3\;fcpyd%d3\\t%P0, %P1
 474    ite\\t%D3\;fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
 475    it\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2
 476    it\t%d3\;fmdrr%d3\\t%P0, %Q1, %R1
 477    ite\\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
 478    it\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2
 479    it\t%d3\;fmrrd%d3\\t%Q0, %R0, %P1
 480    ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
 481    [(set_attr "conds" "use")
 482     (set_attr "length" "6,6,10,6,6,10,6,6,10")
 483     (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
 484 )
 485
 486
 487 ;; Sign manipulation functions
 488
 489 (define_insn "*abssf2_vfp"
 490   [(set (match_operand:SF         0 "s_register_operand" "=t")
 491         (abs:SF (match_operand:SF 1 "s_register_operand" "t")))]
 492   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 493   "fabss%?\\t%0, %1"
 494   [(set_attr "predicable" "yes")
 495    (set_attr "type" "ffariths")]
 496 )
 497
 498 (define_insn "*absdf2_vfp"
 499   [(set (match_operand:DF         0 "s_register_operand" "=w")
 500         (abs:DF (match_operand:DF 1 "s_register_operand" "w")))]
 501   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 502   "fabsd%?\\t%P0, %P1"
 503   [(set_attr "predicable" "yes")
 504    (set_attr "type" "ffarithd")]
 505 )
 506
 507 (define_insn "*negsf2_vfp"
 508   [(set (match_operand:SF         0 "s_register_operand" "=t,?r")
 509         (neg:SF (match_operand:SF 1 "s_register_operand" "t,r")))]
 510   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 511   "@
 512    fnegs%?\\t%0, %1
 513    eor%?\\t%0, %1, #-2147483648"
 514   [(set_attr "predicable" "yes")
 515    (set_attr "type" "ffariths")]
 516 )
 517
 518 (define_insn_and_split "*negdf2_vfp"
 519   [(set (match_operand:DF         0 "s_register_operand" "=w,?r,?r")
 520         (neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))]
 521   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 522   "@
 523    fnegd%?\\t%P0, %P1
 524    #
 525    #"
 526   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && reload_completed
 527    && arm_general_register_operand (operands[0], DFmode)"
 528   [(set (match_dup 0) (match_dup 1))]
 529   "
 530   if (REGNO (operands[0]) == REGNO (operands[1]))
 531     {
 532       operands[0] = gen_highpart (SImode, operands[0]);
 533       operands[1] = gen_rtx_XOR (SImode, operands[0], GEN_INT (0x80000000));
 534     }
 535   else
 536     {
 537       rtx in_hi, in_lo, out_hi, out_lo;
 538
 539       in_hi = gen_rtx_XOR (SImode, gen_highpart (SImode, operands[1]),
 540                            GEN_INT (0x80000000));
 541       in_lo = gen_lowpart (SImode, operands[1]);
 542       out_hi = gen_highpart (SImode, operands[0]);
 543       out_lo = gen_lowpart (SImode, operands[0]);
 544
 545       if (REGNO (in_lo) == REGNO (out_hi))
 546         {
 547           emit_insn (gen_rtx_SET (SImode, out_lo, in_lo));
 548           operands[0] = out_hi;
 549           operands[1] = in_hi;
 550         }
 551       else
 552         {
 553           emit_insn (gen_rtx_SET (SImode, out_hi, in_hi));
 554           operands[0] = out_lo;
 555           operands[1] = in_lo;
 556         }
 557     }
 558   "
 559   [(set_attr "predicable" "yes")
 560    (set_attr "length" "4,4,8")
 561    (set_attr "type" "ffarithd")]
 562 )
 563
 564
 565 ;; Arithmetic insns
 566
 567 (define_insn "*addsf3_vfp"
 568   [(set (match_operand:SF          0 "s_register_operand" "=t")
 569         (plus:SF (match_operand:SF 1 "s_register_operand" "t")
 570                  (match_operand:SF 2 "s_register_operand" "t")))]
 571   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 572   "fadds%?\\t%0, %1, %2"
 573   [(set_attr "predicable" "yes")
 574    (set_attr "type" "fadds")]
 575 )
 576
 577 (define_insn "*adddf3_vfp"
 578   [(set (match_operand:DF          0 "s_register_operand" "=w")
 579         (plus:DF (match_operand:DF 1 "s_register_operand" "w")
 580                  (match_operand:DF 2 "s_register_operand" "w")))]
 581   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 582   "faddd%?\\t%P0, %P1, %P2"
 583   [(set_attr "predicable" "yes")
 584    (set_attr "type" "faddd")]
 585 )
 586
 587
 588 (define_insn "*subsf3_vfp"
 589   [(set (match_operand:SF           0 "s_register_operand" "=t")
 590         (minus:SF (match_operand:SF 1 "s_register_operand" "t")
 591                   (match_operand:SF 2 "s_register_operand" "t")))]
 592   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 593   "fsubs%?\\t%0, %1, %2"
 594   [(set_attr "predicable" "yes")
 595    (set_attr "type" "fadds")]
 596 )
 597
 598 (define_insn "*subdf3_vfp"
 599   [(set (match_operand:DF           0 "s_register_operand" "=w")
 600         (minus:DF (match_operand:DF 1 "s_register_operand" "w")
 601                   (match_operand:DF 2 "s_register_operand" "w")))]
 602   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 603   "fsubd%?\\t%P0, %P1, %P2"
 604   [(set_attr "predicable" "yes")
 605    (set_attr "type" "faddd")]
 606 )
 607
 608
 609 ;; Division insns
 610
 611 (define_insn "*divsf3_vfp"
 612   [(set (match_operand:SF         0 "s_register_operand" "+t")
 613         (div:SF (match_operand:SF 1 "s_register_operand" "t")
 614                 (match_operand:SF 2 "s_register_operand" "t")))]
 615   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 616   "fdivs%?\\t%0, %1, %2"
 617   [(set_attr "predicable" "yes")
 618    (set_attr "type" "fdivs")]
 619 )
 620
 621 (define_insn "*divdf3_vfp"
 622   [(set (match_operand:DF         0 "s_register_operand" "+w")
 623         (div:DF (match_operand:DF 1 "s_register_operand" "w")
 624                 (match_operand:DF 2 "s_register_operand" "w")))]
 625   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 626   "fdivd%?\\t%P0, %P1, %P2"
 627   [(set_attr "predicable" "yes")
 628    (set_attr "type" "fdivd")]
 629 )
 630
 631
 632 ;; Multiplication insns
 633
 634 (define_insn "*mulsf3_vfp"
 635   [(set (match_operand:SF          0 "s_register_operand" "+t")
 636         (mult:SF (match_operand:SF 1 "s_register_operand" "t")
 637                  (match_operand:SF 2 "s_register_operand" "t")))]
 638   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 639   "fmuls%?\\t%0, %1, %2"
 640   [(set_attr "predicable" "yes")
 641    (set_attr "type" "fmuls")]
 642 )
 643
 644 (define_insn "*muldf3_vfp"
 645   [(set (match_operand:DF          0 "s_register_operand" "+w")
 646         (mult:DF (match_operand:DF 1 "s_register_operand" "w")
 647                  (match_operand:DF 2 "s_register_operand" "w")))]
 648   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 649   "fmuld%?\\t%P0, %P1, %P2"
 650   [(set_attr "predicable" "yes")
 651    (set_attr "type" "fmuld")]
 652 )
 653
 654
 655 (define_insn "*mulsf3negsf_vfp"
 656   [(set (match_operand:SF                  0 "s_register_operand" "+t")
 657         (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
 658                  (match_operand:SF         2 "s_register_operand" "t")))]
 659   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 660   "fnmuls%?\\t%0, %1, %2"
 661   [(set_attr "predicable" "yes")
 662    (set_attr "type" "fmuls")]
 663 )
 664
 665 (define_insn "*muldf3negdf_vfp"
 666   [(set (match_operand:DF                  0 "s_register_operand" "+w")
 667         (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
 668                  (match_operand:DF         2 "s_register_operand" "w")))]
 669   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 670   "fnmuld%?\\t%P0, %P1, %P2"
 671   [(set_attr "predicable" "yes")
 672    (set_attr "type" "fmuld")]
 673 )
 674
 675
 676 ;; Multiply-accumulate insns
 677
 678 ;; 0 = 1 * 2 + 0
 679 (define_insn "*mulsf3addsf_vfp"
 680   [(set (match_operand:SF                   0 "s_register_operand" "=t")
 681         (plus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
 682                           (match_operand:SF 3 "s_register_operand" "t"))
 683                  (match_operand:SF          1 "s_register_operand" "0")))]
 684   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 685   "fmacs%?\\t%0, %2, %3"
 686   [(set_attr "predicable" "yes")
 687    (set_attr "type" "fmacs")]
 688 )
 689
 690 (define_insn "*muldf3adddf_vfp"
 691   [(set (match_operand:DF                   0 "s_register_operand" "=w")
 692         (plus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
 693                           (match_operand:DF 3 "s_register_operand" "w"))
 694                  (match_operand:DF          1 "s_register_operand" "0")))]
 695   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 696   "fmacd%?\\t%P0, %P2, %P3"
 697   [(set_attr "predicable" "yes")
 698    (set_attr "type" "fmacd")]
 699 )
 700
 701 ;; 0 = 1 * 2 - 0
 702 (define_insn "*mulsf3subsf_vfp"
 703   [(set (match_operand:SF                    0 "s_register_operand" "=t")
 704         (minus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
 705                            (match_operand:SF 3 "s_register_operand" "t"))
 706                   (match_operand:SF          1 "s_register_operand" "0")))]
 707   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 708   "fmscs%?\\t%0, %2, %3"
 709   [(set_attr "predicable" "yes")
 710    (set_attr "type" "fmacs")]
 711 )
 712
 713 (define_insn "*muldf3subdf_vfp"
 714   [(set (match_operand:DF                    0 "s_register_operand" "=w")
 715         (minus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
 716                            (match_operand:DF 3 "s_register_operand" "w"))
 717                   (match_operand:DF          1 "s_register_operand" "0")))]
 718   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 719   "fmscd%?\\t%P0, %P2, %P3"
 720   [(set_attr "predicable" "yes")
 721    (set_attr "type" "fmacd")]
 722 )
 723
 724 ;; 0 = -(1 * 2) + 0
 725 (define_insn "*mulsf3negsfaddsf_vfp"
 726   [(set (match_operand:SF                    0 "s_register_operand" "=t")
 727         (minus:SF (match_operand:SF          1 "s_register_operand" "0")
 728                   (mult:SF (match_operand:SF 2 "s_register_operand" "t")
 729                            (match_operand:SF 3 "s_register_operand" "t"))))]
 730   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 731   "fnmacs%?\\t%0, %2, %3"
 732   [(set_attr "predicable" "yes")
 733    (set_attr "type" "fmacs")]
 734 )
 735
 736 (define_insn "*fmuldf3negdfadddf_vfp"
 737   [(set (match_operand:DF                    0 "s_register_operand" "=w")
 738         (minus:DF (match_operand:DF          1 "s_register_operand" "0")
 739                   (mult:DF (match_operand:DF 2 "s_register_operand" "w")
 740                            (match_operand:DF 3 "s_register_operand" "w"))))]
 741   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 742   "fnmacd%?\\t%P0, %P2, %P3"
 743   [(set_attr "predicable" "yes")
 744    (set_attr "type" "fmacd")]
 745 )
 746
 747
 748 ;; 0 = -(1 * 2) - 0
 749 (define_insn "*mulsf3negsfsubsf_vfp"
 750   [(set (match_operand:SF                     0 "s_register_operand" "=t")
 751         (minus:SF (mult:SF
 752                     (neg:SF (match_operand:SF 2 "s_register_operand" "t"))
 753                     (match_operand:SF         3 "s_register_operand" "t"))
 754                   (match_operand:SF           1 "s_register_operand" "0")))]
 755   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 756   "fnmscs%?\\t%0, %2, %3"
 757   [(set_attr "predicable" "yes")
 758    (set_attr "type" "fmacs")]
 759 )
 760
 761 (define_insn "*muldf3negdfsubdf_vfp"
 762   [(set (match_operand:DF                     0 "s_register_operand" "=w")
 763         (minus:DF (mult:DF
 764                     (neg:DF (match_operand:DF 2 "s_register_operand" "w"))
 765                     (match_operand:DF         3 "s_register_operand" "w"))
 766                   (match_operand:DF           1 "s_register_operand" "0")))]
 767   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 768   "fnmscd%?\\t%P0, %P2, %P3"
 769   [(set_attr "predicable" "yes")
 770    (set_attr "type" "fmacd")]
 771 )
 772
 773
 774 ;; Conversion routines
 775
 776 (define_insn "*extendsfdf2_vfp"
 777   [(set (match_operand:DF                  0 "s_register_operand" "=w")
 778         (float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))]
 779   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 780   "fcvtds%?\\t%P0, %1"
 781   [(set_attr "predicable" "yes")
 782    (set_attr "type" "f_cvt")]
 783 )
 784
 785 (define_insn "*truncdfsf2_vfp"
 786   [(set (match_operand:SF                  0 "s_register_operand" "=t")
 787         (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))]
 788   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 789   "fcvtsd%?\\t%0, %P1"
 790   [(set_attr "predicable" "yes")
 791    (set_attr "type" "f_cvt")]
 792 )
 793
 794 (define_insn "extendhfsf2"
 795   [(set (match_operand:SF                  0 "s_register_operand" "=t")
 796         (float_extend:SF (match_operand:HF 1 "s_register_operand" "t")))]
 797   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_NEON_FP16"
 798   "vcvtb%?.f32.f16\\t%0, %1"
 799   [(set_attr "predicable" "yes")
 800    (set_attr "type" "f_cvt")]
 801 )
 802
 803 (define_insn "truncsfhf2"
 804   [(set (match_operand:HF                  0 "s_register_operand" "=t")
 805         (float_truncate:HF (match_operand:SF 1 "s_register_operand" "t")))]
 806   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_NEON_FP16"
 807   "vcvtb%?.f16.f32\\t%0, %1"
 808   [(set_attr "predicable" "yes")
 809    (set_attr "type" "f_cvt")]
 810 )
 811
 812 (define_insn "*truncsisf2_vfp"
 813   [(set (match_operand:SI                 0 "s_register_operand" "=t")
 814         (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
 815   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 816   "ftosizs%?\\t%0, %1"
 817   [(set_attr "predicable" "yes")
 818    (set_attr "type" "f_cvt")]
 819 )
 820
 821 (define_insn "*truncsidf2_vfp"
 822   [(set (match_operand:SI                 0 "s_register_operand" "=t")
 823         (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))]
 824   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 825   "ftosizd%?\\t%0, %P1"
 826   [(set_attr "predicable" "yes")
 827    (set_attr "type" "f_cvt")]
 828 )
 829
 830
 831 (define_insn "fixuns_truncsfsi2"
 832   [(set (match_operand:SI                 0 "s_register_operand" "=t")
 833         (unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
 834   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 835   "ftouizs%?\\t%0, %1"
 836   [(set_attr "predicable" "yes")
 837    (set_attr "type" "f_cvt")]
 838 )
 839
 840 (define_insn "fixuns_truncdfsi2"
 841   [(set (match_operand:SI                 0 "s_register_operand" "=t")
 842         (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))]
 843   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 844   "ftouizd%?\\t%0, %P1"
 845   [(set_attr "predicable" "yes")
 846    (set_attr "type" "f_cvt")]
 847 )
 848
 849
 850 (define_insn "*floatsisf2_vfp"
 851   [(set (match_operand:SF           0 "s_register_operand" "=t")
 852         (float:SF (match_operand:SI 1 "s_register_operand" "t")))]
 853   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 854   "fsitos%?\\t%0, %1"
 855   [(set_attr "predicable" "yes")
 856    (set_attr "type" "f_cvt")]
 857 )
 858
 859 (define_insn "*floatsidf2_vfp"
 860   [(set (match_operand:DF           0 "s_register_operand" "=w")
 861         (float:DF (match_operand:SI 1 "s_register_operand" "t")))]
 862   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 863   "fsitod%?\\t%P0, %1"
 864   [(set_attr "predicable" "yes")
 865    (set_attr "type" "f_cvt")]
 866 )
 867
 868
 869 (define_insn "floatunssisf2"
 870   [(set (match_operand:SF           0 "s_register_operand" "=t")
 871         (unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))]
 872   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 873   "fuitos%?\\t%0, %1"
 874   [(set_attr "predicable" "yes")
 875    (set_attr "type" "f_cvt")]
 876 )
 877
 878 (define_insn "floatunssidf2"
 879   [(set (match_operand:DF           0 "s_register_operand" "=w")
 880         (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))]
 881   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 882   "fuitod%?\\t%P0, %1"
 883   [(set_attr "predicable" "yes")
 884    (set_attr "type" "f_cvt")]
 885 )
 886
 887
 888 ;; Sqrt insns.
 889
 890 (define_insn "*sqrtsf2_vfp"
 891   [(set (match_operand:SF          0 "s_register_operand" "=t")
 892         (sqrt:SF (match_operand:SF 1 "s_register_operand" "t")))]
 893   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 894   "fsqrts%?\\t%0, %1"
 895   [(set_attr "predicable" "yes")
 896    (set_attr "type" "fdivs")]
 897 )
 898
 899 (define_insn "*sqrtdf2_vfp"
 900   [(set (match_operand:DF          0 "s_register_operand" "=w")
 901         (sqrt:DF (match_operand:DF 1 "s_register_operand" "w")))]
 902   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 903   "fsqrtd%?\\t%P0, %P1"
 904   [(set_attr "predicable" "yes")
 905    (set_attr "type" "fdivd")]
 906 )
 907
 908
 909 ;; Patterns to split/copy vfp condition flags.
 910
 911 (define_insn "*movcc_vfp"
 912   [(set (reg CC_REGNUM)
 913         (reg VFPCC_REGNUM))]
 914   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 915   "fmstat%?"
 916   [(set_attr "conds" "set")
 917    (set_attr "type" "f_flag")]
 918 )
 919
 920 (define_insn_and_split "*cmpsf_split_vfp"
 921   [(set (reg:CCFP CC_REGNUM)
 922         (compare:CCFP (match_operand:SF 0 "s_register_operand"  "t")
 923                       (match_operand:SF 1 "vfp_compare_operand" "tG")))]
 924   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 925   "#"
 926   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 927   [(set (reg:CCFP VFPCC_REGNUM)
 928         (compare:CCFP (match_dup 0)
 929                       (match_dup 1)))
 930    (set (reg:CCFP CC_REGNUM)
 931         (reg:CCFP VFPCC_REGNUM))]
 932   ""
 933 )
 934
 935 (define_insn_and_split "*cmpsf_trap_split_vfp"
 936   [(set (reg:CCFPE CC_REGNUM)
 937         (compare:CCFPE (match_operand:SF 0 "s_register_operand"  "t")
 938                        (match_operand:SF 1 "vfp_compare_operand" "tG")))]
 939   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 940   "#"
 941   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 942   [(set (reg:CCFPE VFPCC_REGNUM)
 943         (compare:CCFPE (match_dup 0)
 944                        (match_dup 1)))
 945    (set (reg:CCFPE CC_REGNUM)
 946         (reg:CCFPE VFPCC_REGNUM))]
 947   ""
 948 )
 949
 950 (define_insn_and_split "*cmpdf_split_vfp"
 951   [(set (reg:CCFP CC_REGNUM)
 952         (compare:CCFP (match_operand:DF 0 "s_register_operand"  "w")
 953                       (match_operand:DF 1 "vfp_compare_operand" "wG")))]
 954   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 955   "#"
 956   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 957   [(set (reg:CCFP VFPCC_REGNUM)
 958         (compare:CCFP (match_dup 0)
 959                        (match_dup 1)))
 960    (set (reg:CCFP CC_REGNUM)
 961         (reg:CCFPE VFPCC_REGNUM))]
 962   ""
 963 )
 964
 965 (define_insn_and_split "*cmpdf_trap_split_vfp"
 966   [(set (reg:CCFPE CC_REGNUM)
 967         (compare:CCFPE (match_operand:DF 0 "s_register_operand"  "w")
 968                        (match_operand:DF 1 "vfp_compare_operand" "wG")))]
 969   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 970   "#"
 971   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 972   [(set (reg:CCFPE VFPCC_REGNUM)
 973         (compare:CCFPE (match_dup 0)
 974                        (match_dup 1)))
 975    (set (reg:CCFPE CC_REGNUM)
 976         (reg:CCFPE VFPCC_REGNUM))]
 977   ""
 978 )
 979
 980
 981 ;; Comparison patterns
 982
 983 (define_insn "*cmpsf_vfp"
 984   [(set (reg:CCFP VFPCC_REGNUM)
 985         (compare:CCFP (match_operand:SF 0 "s_register_operand"  "t,t")
 986                       (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
 987   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 988   "@
 989    fcmps%?\\t%0, %1
 990    fcmpzs%?\\t%0"
 991   [(set_attr "predicable" "yes")
 992    (set_attr "type" "fcmps")]
 993 )
 994
 995 (define_insn "*cmpsf_trap_vfp"
 996   [(set (reg:CCFPE VFPCC_REGNUM)
 997         (compare:CCFPE (match_operand:SF 0 "s_register_operand"  "t,t")
 998                        (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
 999   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1000   "@
1001    fcmpes%?\\t%0, %1
1002    fcmpezs%?\\t%0"
1003   [(set_attr "predicable" "yes")
1004    (set_attr "type" "fcmpd")]
1005 )
1006
1007 (define_insn "*cmpdf_vfp"
1008   [(set (reg:CCFP VFPCC_REGNUM)
1009         (compare:CCFP (match_operand:DF 0 "s_register_operand"  "w,w")
1010                       (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
1011   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1012   "@
1013    fcmpd%?\\t%P0, %P1
1014    fcmpzd%?\\t%P0"
1015   [(set_attr "predicable" "yes")
1016    (set_attr "type" "fcmpd")]
1017 )
1018
1019 (define_insn "*cmpdf_trap_vfp"
1020   [(set (reg:CCFPE VFPCC_REGNUM)
1021         (compare:CCFPE (match_operand:DF 0 "s_register_operand"  "w,w")
1022                        (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
1023   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1024   "@
1025    fcmped%?\\t%P0, %P1
1026    fcmpezd%?\\t%P0"
1027   [(set_attr "predicable" "yes")
1028    (set_attr "type" "fcmpd")]
1029 )
1030
1031
1032 ;; Store multiple insn used in function prologue.
1033
1034 (define_insn "*push_multi_vfp"
1035   [(match_parallel 2 "multi_register_push"
1036     [(set (match_operand:BLK 0 "memory_operand" "=m")
1037           (unspec:BLK [(match_operand:DF 1 "s_register_operand" "w")]
1038                       UNSPEC_PUSH_MULT))])]
1039   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1040   "* return vfp_output_fstmd (operands);"
1041   [(set_attr "type" "f_stored")]
1042 )
1043
1044
1045 ;; Unimplemented insns:
1046 ;; fldm*
1047 ;; fstm*
1048 ;; fmdhr et al (VFPv1)
1049 ;; Support for xD (single precision only) variants.
1050 ;; fmrrs, fmsrr