1 /* Subroutines for insn-output.c for ATMEL AVR micro controllers
2 Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
3 Contributed by Denis Chertykov (denisc@overta.ru)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-attr.h"
45 #include "target-def.h"
47 /* Maximal allowed offset for an address in the LD command */
48 #define MAX_LD_OFFSET(MODE) (64 - (signed)GET_MODE_SIZE (MODE))
50 static int avr_naked_function_p (tree
);
51 static int interrupt_function_p (tree
);
52 static int signal_function_p (tree
);
53 static int avr_regs_to_save (HARD_REG_SET
*);
54 static int sequent_regs_live (void);
55 static const char *ptrreg_to_str (int);
56 static const char *cond_string (enum rtx_code
);
57 static int avr_num_arg_regs (enum machine_mode
, tree
);
58 static int out_adj_frame_ptr (FILE *, int);
59 static int out_set_stack_ptr (FILE *, int, int);
60 static RTX_CODE
compare_condition (rtx insn
);
61 static int compare_sign_p (rtx insn
);
62 static tree
avr_handle_progmem_attribute (tree
*, tree
, tree
, int, bool *);
63 static tree
avr_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
64 const struct attribute_spec avr_attribute_table
[];
65 static bool avr_assemble_integer (rtx
, unsigned int, int);
66 static void avr_file_start (void);
67 static void avr_file_end (void);
68 static void avr_output_function_prologue (FILE *, HOST_WIDE_INT
);
69 static void avr_output_function_epilogue (FILE *, HOST_WIDE_INT
);
70 static void avr_unique_section (tree
, int);
71 static void avr_insert_attributes (tree
, tree
*);
72 static unsigned int avr_section_type_flags (tree
, const char *, int);
74 static void avr_reorg (void);
75 static void avr_asm_out_ctor (rtx
, int);
76 static void avr_asm_out_dtor (rtx
, int);
77 static int default_rtx_costs (rtx
, enum rtx_code
, enum rtx_code
);
78 static bool avr_rtx_costs (rtx
, int, int, int *);
79 static int avr_address_cost (rtx
);
81 /* Allocate registers from r25 to r8 for parameters for function calls */
82 #define FIRST_CUM_REG 26
84 /* Temporary register RTX (gen_rtx (REG,QImode,TMP_REGNO)) */
85 static GTY(()) rtx tmp_reg_rtx
;
87 /* Zeroed register RTX (gen_rtx (REG,QImode,ZERO_REGNO)) */
88 static GTY(()) rtx zero_reg_rtx
;
90 /* AVR register names {"r0", "r1", ..., "r31"} */
91 static const char *const avr_regnames
[] = REGISTER_NAMES
;
93 /* This holds the last insn address. */
94 static int last_insn_address
= 0;
96 /* Commands count in the compiled file */
97 static int commands_in_file
;
99 /* Commands in the functions prologues in the compiled file */
100 static int commands_in_prologues
;
102 /* Commands in the functions epilogues in the compiled file */
103 static int commands_in_epilogues
;
105 /* Prologue/Epilogue size in words */
106 static int prologue_size
;
107 static int epilogue_size
;
109 /* Size of all jump tables in the current function, in words. */
110 static int jump_tables_size
;
112 /* Initial stack value specified by the `-minit-stack=' option */
113 const char *avr_init_stack
= "__stack";
115 /* Default MCU name */
116 const char *avr_mcu_name
= "avr2";
118 /* Preprocessor macros to define depending on MCU type. */
119 const char *avr_base_arch_macro
;
120 const char *avr_extra_arch_macro
;
122 /* More than 8K of program memory: use "call" and "jmp". */
125 /* Enhanced core: use "movw", "mul", ... */
126 int avr_enhanced_p
= 0;
128 /* Assembler only. */
129 int avr_asm_only_p
= 0;
135 const char *const macro
;
138 static const struct base_arch_s avr_arch_types
[] = {
139 { 1, 0, 0, NULL
}, /* unknown device specified */
140 { 1, 0, 0, "__AVR_ARCH__=1" },
141 { 0, 0, 0, "__AVR_ARCH__=2" },
142 { 0, 0, 1, "__AVR_ARCH__=3" },
143 { 0, 1, 0, "__AVR_ARCH__=4" },
144 { 0, 1, 1, "__AVR_ARCH__=5" }
148 const char *const name
;
149 int arch
; /* index in avr_arch_types[] */
150 /* Must lie outside user's namespace. NULL == no macro. */
151 const char *const macro
;
154 /* List of all known AVR MCU types - if updated, it has to be kept
155 in sync in several places (FIXME: is there a better way?):
157 - avr.h (CPP_SPEC, LINK_SPEC, CRT_BINUTILS_SPECS)
158 - t-avr (MULTILIB_MATCHES)
159 - gas/config/tc-avr.c
162 static const struct mcu_type_s avr_mcu_types
[] = {
163 /* Classic, <= 8K. */
165 { "at90s2313", 2, "__AVR_AT90S2313__" },
166 { "at90s2323", 2, "__AVR_AT90S2323__" },
167 { "at90s2333", 2, "__AVR_AT90S2333__" },
168 { "at90s2343", 2, "__AVR_AT90S2343__" },
169 { "attiny22", 2, "__AVR_ATtiny22__" },
170 { "attiny26", 2, "__AVR_ATtiny26__" },
171 { "at90s4414", 2, "__AVR_AT90S4414__" },
172 { "at90s4433", 2, "__AVR_AT90S4433__" },
173 { "at90s4434", 2, "__AVR_AT90S4434__" },
174 { "at90s8515", 2, "__AVR_AT90S8515__" },
175 { "at90c8534", 2, "__AVR_AT90C8534__" },
176 { "at90s8535", 2, "__AVR_AT90S8535__" },
177 { "at86rf401", 2, "__AVR_AT86RF401__" },
180 { "atmega103", 3, "__AVR_ATmega103__" },
181 { "atmega603", 3, "__AVR_ATmega603__" },
182 { "at43usb320", 3, "__AVR_AT43USB320__" },
183 { "at43usb355", 3, "__AVR_AT43USB355__" },
184 { "at76c711", 3, "__AVR_AT76C711__" },
185 /* Enhanced, <= 8K. */
187 { "atmega8", 4, "__AVR_ATmega8__" },
188 { "atmega8515", 4, "__AVR_ATmega8515__" },
189 { "atmega8535", 4, "__AVR_ATmega8535__" },
190 /* Enhanced, > 8K. */
192 { "atmega16", 5, "__AVR_ATmega16__" },
193 { "atmega161", 5, "__AVR_ATmega161__" },
194 { "atmega162", 5, "__AVR_ATmega162__" },
195 { "atmega163", 5, "__AVR_ATmega163__" },
196 { "atmega169", 5, "__AVR_ATmega169__" },
197 { "atmega32", 5, "__AVR_ATmega32__" },
198 { "atmega323", 5, "__AVR_ATmega323__" },
199 { "atmega64", 5, "__AVR_ATmega64__" },
200 { "atmega128", 5, "__AVR_ATmega128__" },
201 { "at94k", 5, "__AVR_AT94K__" },
202 /* Assembler only. */
204 { "at90s1200", 1, "__AVR_AT90S1200__" },
205 { "attiny11", 1, "__AVR_ATtiny11__" },
206 { "attiny12", 1, "__AVR_ATtiny12__" },
207 { "attiny15", 1, "__AVR_ATtiny15__" },
208 { "attiny28", 1, "__AVR_ATtiny28__" },
212 int avr_case_values_threshold
= 30000;
214 /* Initialize the GCC target structure. */
215 #undef TARGET_ASM_ALIGNED_HI_OP
216 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
217 #undef TARGET_ASM_INTEGER
218 #define TARGET_ASM_INTEGER avr_assemble_integer
219 #undef TARGET_ASM_FILE_START
220 #define TARGET_ASM_FILE_START avr_file_start
221 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
222 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
223 #undef TARGET_ASM_FILE_END
224 #define TARGET_ASM_FILE_END avr_file_end
226 #undef TARGET_ASM_FUNCTION_PROLOGUE
227 #define TARGET_ASM_FUNCTION_PROLOGUE avr_output_function_prologue
228 #undef TARGET_ASM_FUNCTION_EPILOGUE
229 #define TARGET_ASM_FUNCTION_EPILOGUE avr_output_function_epilogue
230 #undef TARGET_ATTRIBUTE_TABLE
231 #define TARGET_ATTRIBUTE_TABLE avr_attribute_table
232 #undef TARGET_ASM_UNIQUE_SECTION
233 #define TARGET_ASM_UNIQUE_SECTION avr_unique_section
234 #undef TARGET_INSERT_ATTRIBUTES
235 #define TARGET_INSERT_ATTRIBUTES avr_insert_attributes
236 #undef TARGET_SECTION_TYPE_FLAGS
237 #define TARGET_SECTION_TYPE_FLAGS avr_section_type_flags
238 #undef TARGET_RTX_COSTS
239 #define TARGET_RTX_COSTS avr_rtx_costs
240 #undef TARGET_ADDRESS_COST
241 #define TARGET_ADDRESS_COST avr_address_cost
242 #undef TARGET_MACHINE_DEPENDENT_REORG
243 #define TARGET_MACHINE_DEPENDENT_REORG avr_reorg
245 struct gcc_target targetm
= TARGET_INITIALIZER
;
248 avr_override_options (void)
250 const struct mcu_type_s
*t
;
251 const struct base_arch_s
*base
;
253 for (t
= avr_mcu_types
; t
->name
; t
++)
254 if (strcmp (t
->name
, avr_mcu_name
) == 0)
259 fprintf (stderr
, "unknown MCU `%s' specified\nKnown MCU names:\n",
261 for (t
= avr_mcu_types
; t
->name
; t
++)
262 fprintf (stderr
," %s\n", t
->name
);
265 base
= &avr_arch_types
[t
->arch
];
266 avr_asm_only_p
= base
->asm_only
;
267 avr_enhanced_p
= base
->enhanced
;
268 avr_mega_p
= base
->mega
;
269 avr_base_arch_macro
= base
->macro
;
270 avr_extra_arch_macro
= t
->macro
;
272 if (optimize
&& !TARGET_NO_TABLEJUMP
)
273 avr_case_values_threshold
= (!AVR_MEGA
|| TARGET_CALL_PROLOGUES
) ? 8 : 17;
275 tmp_reg_rtx
= gen_rtx_REG (QImode
, TMP_REGNO
);
276 zero_reg_rtx
= gen_rtx_REG (QImode
, ZERO_REGNO
);
279 /* return register class from register number */
281 static const int reg_class_tab
[]={
282 GENERAL_REGS
,GENERAL_REGS
,GENERAL_REGS
,GENERAL_REGS
,GENERAL_REGS
,
283 GENERAL_REGS
,GENERAL_REGS
,GENERAL_REGS
,GENERAL_REGS
,GENERAL_REGS
,
284 GENERAL_REGS
,GENERAL_REGS
,GENERAL_REGS
,GENERAL_REGS
,GENERAL_REGS
,
285 GENERAL_REGS
, /* r0 - r15 */
286 LD_REGS
,LD_REGS
,LD_REGS
,LD_REGS
,LD_REGS
,LD_REGS
,LD_REGS
,
287 LD_REGS
, /* r16 - 23 */
288 ADDW_REGS
,ADDW_REGS
, /* r24,r25 */
289 POINTER_X_REGS
,POINTER_X_REGS
, /* r26,27 */
290 POINTER_Y_REGS
,POINTER_Y_REGS
, /* r28,r29 */
291 POINTER_Z_REGS
,POINTER_Z_REGS
, /* r30,r31 */
292 STACK_REG
,STACK_REG
/* SPL,SPH */
295 /* Return register class for register R */
298 avr_regno_reg_class (int r
)
301 return reg_class_tab
[r
];
306 /* A C expression which defines the machine-dependent operand
307 constraint letters for register classes. If C is such a
308 letter, the value should be the register class corresponding to
309 it. Otherwise, the value should be `NO_REGS'. The register
310 letter `r', corresponding to class `GENERAL_REGS', will not be
311 passed to this macro; you do not need to handle it. */
314 avr_reg_class_from_letter (int c
)
318 case 't' : return R0_REG
;
319 case 'b' : return BASE_POINTER_REGS
;
320 case 'e' : return POINTER_REGS
;
321 case 'w' : return ADDW_REGS
;
322 case 'd' : return LD_REGS
;
323 case 'l' : return NO_LD_REGS
;
324 case 'a' : return SIMPLE_LD_REGS
;
325 case 'x' : return POINTER_X_REGS
;
326 case 'y' : return POINTER_Y_REGS
;
327 case 'z' : return POINTER_Z_REGS
;
328 case 'q' : return STACK_REG
;
334 /* Return nonzero if FUNC is a naked function. */
337 avr_naked_function_p (tree func
)
341 if (TREE_CODE (func
) != FUNCTION_DECL
)
344 a
= lookup_attribute ("naked", DECL_ATTRIBUTES (func
));
345 return a
!= NULL_TREE
;
348 /* Return nonzero if FUNC is an interrupt function as specified
349 by the "interrupt" attribute. */
352 interrupt_function_p (tree func
)
356 if (TREE_CODE (func
) != FUNCTION_DECL
)
359 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
360 return a
!= NULL_TREE
;
363 /* Return nonzero if FUNC is a signal function as specified
364 by the "signal" attribute. */
367 signal_function_p (tree func
)
371 if (TREE_CODE (func
) != FUNCTION_DECL
)
374 a
= lookup_attribute ("signal", DECL_ATTRIBUTES (func
));
375 return a
!= NULL_TREE
;
378 /* Return the number of hard registers to push/pop in the prologue/epilogue
379 of the current function, and optionally store these registers in SET. */
382 avr_regs_to_save (HARD_REG_SET
*set
)
385 int int_or_sig_p
= (interrupt_function_p (current_function_decl
)
386 || signal_function_p (current_function_decl
));
387 int leaf_func_p
= leaf_function_p ();
390 CLEAR_HARD_REG_SET (*set
);
393 /* No need to save any registers if the function never returns. */
394 if (TREE_THIS_VOLATILE (current_function_decl
))
397 for (reg
= 0; reg
< 32; reg
++)
399 /* Do not push/pop __tmp_reg__, __zero_reg__, as well as
400 any global register variables. */
404 if ((int_or_sig_p
&& !leaf_func_p
&& call_used_regs
[reg
])
405 || (regs_ever_live
[reg
]
406 && (int_or_sig_p
|| !call_used_regs
[reg
])
407 && !(frame_pointer_needed
408 && (reg
== REG_Y
|| reg
== (REG_Y
+1)))))
411 SET_HARD_REG_BIT (*set
, reg
);
418 /* Compute offset between arg_pointer and frame_pointer */
421 initial_elimination_offset (int from
, int to
)
423 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
427 int offset
= frame_pointer_needed
? 2 : 0;
429 offset
+= avr_regs_to_save (NULL
);
430 return get_frame_size () + 2 + 1 + offset
;
434 /* Return 1 if the function epilogue is just a single "ret". */
437 avr_simple_epilogue (void)
439 return (! frame_pointer_needed
440 && get_frame_size () == 0
441 && avr_regs_to_save (NULL
) == 0
442 && ! interrupt_function_p (current_function_decl
)
443 && ! signal_function_p (current_function_decl
)
444 && ! avr_naked_function_p (current_function_decl
)
445 && ! MAIN_NAME_P (DECL_NAME (current_function_decl
))
446 && ! TREE_THIS_VOLATILE (current_function_decl
));
449 /* This function checks sequence of live registers */
452 sequent_regs_live (void)
458 for (reg
= 0; reg
< 18; ++reg
)
460 if (!call_used_regs
[reg
])
462 if (regs_ever_live
[reg
])
472 if (!frame_pointer_needed
)
474 if (regs_ever_live
[REG_Y
])
482 if (regs_ever_live
[REG_Y
+1])
495 return (cur_seq
== live_seq
) ? live_seq
: 0;
499 /* Output to FILE the asm instructions to adjust the frame pointer by
500 ADJ (r29:r28 -= ADJ;) which can be positive (prologue) or negative
501 (epilogue). Returns the number of instructions generated. */
504 out_adj_frame_ptr (FILE *file
, int adj
)
510 if (TARGET_TINY_STACK
)
512 if (adj
< -63 || adj
> 63)
513 warning ("large frame pointer change (%d) with -mtiny-stack", adj
);
515 /* The high byte (r29) doesn't change - prefer "subi" (1 cycle)
516 over "sbiw" (2 cycles, same size). */
518 fprintf (file
, (AS2 (subi
, r28
, %d
) CR_TAB
), adj
);
521 else if (adj
< -63 || adj
> 63)
523 fprintf (file
, (AS2 (subi
, r28
, lo8(%d
)) CR_TAB
524 AS2 (sbci
, r29
, hi8(%d
)) CR_TAB
),
530 fprintf (file
, (AS2 (adiw
, r28
, %d
) CR_TAB
), -adj
);
535 fprintf (file
, (AS2 (sbiw
, r28
, %d
) CR_TAB
), adj
);
543 /* Output to FILE the asm instructions to copy r29:r28 to SPH:SPL,
544 handling various cases of interrupt enable flag state BEFORE and AFTER
545 (0=disabled, 1=enabled, -1=unknown/unchanged) and target_flags.
546 Returns the number of instructions generated. */
549 out_set_stack_ptr (FILE *file
, int before
, int after
)
551 int do_sph
, do_cli
, do_save
, do_sei
, lock_sph
, size
;
553 /* The logic here is so that -mno-interrupts actually means
554 "it is safe to write SPH in one instruction, then SPL in the
555 next instruction, without disabling interrupts first".
556 The after != -1 case (interrupt/signal) is not affected. */
558 do_sph
= !TARGET_TINY_STACK
;
559 lock_sph
= do_sph
&& !TARGET_NO_INTERRUPTS
;
560 do_cli
= (before
!= 0 && (after
== 0 || lock_sph
));
561 do_save
= (do_cli
&& before
== -1 && after
== -1);
562 do_sei
= ((do_cli
|| before
!= 1) && after
== 1);
567 fprintf (file
, AS2 (in
, __tmp_reg__
, __SREG__
) CR_TAB
);
573 fprintf (file
, "cli" CR_TAB
);
577 /* Do SPH first - maybe this will disable interrupts for one instruction
578 someday (a suggestion has been sent to avr@atmel.com for consideration
579 in future devices - that would make -mno-interrupts always safe). */
582 fprintf (file
, AS2 (out
, __SP_H__
, r29
) CR_TAB
);
586 /* Set/restore the I flag now - interrupts will be really enabled only
587 after the next instruction. This is not clearly documented, but
588 believed to be true for all AVR devices. */
591 fprintf (file
, AS2 (out
, __SREG__
, __tmp_reg__
) CR_TAB
);
596 fprintf (file
, "sei" CR_TAB
);
600 fprintf (file
, AS2 (out
, __SP_L__
, r28
) "\n");
606 /* Output function prologue */
609 avr_output_function_prologue (FILE *file
, HOST_WIDE_INT size
)
612 int interrupt_func_p
;
618 last_insn_address
= 0;
619 jump_tables_size
= 0;
621 fprintf (file
, "/* prologue: frame size=" HOST_WIDE_INT_PRINT_DEC
" */\n",
624 if (avr_naked_function_p (current_function_decl
))
626 fputs ("/* prologue: naked */\n", file
);
630 interrupt_func_p
= interrupt_function_p (current_function_decl
);
631 signal_func_p
= signal_function_p (current_function_decl
);
632 main_p
= MAIN_NAME_P (DECL_NAME (current_function_decl
));
633 live_seq
= sequent_regs_live ();
634 minimize
= (TARGET_CALL_PROLOGUES
635 && !interrupt_func_p
&& !signal_func_p
&& live_seq
);
637 if (interrupt_func_p
)
639 fprintf (file
,"\tsei\n");
642 if (interrupt_func_p
|| signal_func_p
)
645 AS1 (push
,__zero_reg__
) CR_TAB
646 AS1 (push
,__tmp_reg__
) CR_TAB
647 AS2 (in
,__tmp_reg__
,__SREG__
) CR_TAB
648 AS1 (push
,__tmp_reg__
) CR_TAB
649 AS1 (clr
,__zero_reg__
) "\n");
655 AS1 (ldi
,r28
) ",lo8(%s - " HOST_WIDE_INT_PRINT_DEC
")" CR_TAB
656 AS1 (ldi
,r29
) ",hi8(%s - " HOST_WIDE_INT_PRINT_DEC
")" CR_TAB
657 AS2 (out
,__SP_H__
,r29
) CR_TAB
658 AS2 (out
,__SP_L__
,r28
) "\n"),
659 avr_init_stack
, size
, avr_init_stack
, size
);
663 else if (minimize
&& (frame_pointer_needed
|| live_seq
> 6))
666 AS1 (ldi
, r26
) ",lo8(" HOST_WIDE_INT_PRINT_DEC
")" CR_TAB
667 AS1 (ldi
, r27
) ",hi8(" HOST_WIDE_INT_PRINT_DEC
")" CR_TAB
), size
, size
);
669 fprintf (file
, (AS2 (ldi
, r30
, pm_lo8(.L_
%s_body
)) CR_TAB
670 AS2 (ldi
, r31
, pm_hi8(.L_
%s_body
)) CR_TAB
)
671 ,current_function_name
, current_function_name
);
677 fprintf (file
, AS1 (jmp
,__prologue_saves__
+%d
) "\n",
678 (18 - live_seq
) * 2);
683 fprintf (file
, AS1 (rjmp
,__prologue_saves__
+%d
) "\n",
684 (18 - live_seq
) * 2);
687 fprintf (file
, ".L_%s_body:\n", current_function_name
);
693 prologue_size
+= avr_regs_to_save (&set
);
694 for (reg
= 0; reg
< 32; ++reg
)
696 if (TEST_HARD_REG_BIT (set
, reg
))
698 fprintf (file
, "\t" AS1 (push
,%s
) "\n", avr_regnames
[reg
]);
701 if (frame_pointer_needed
)
705 AS1 (push
,r28
) CR_TAB
706 AS1 (push
,r29
) CR_TAB
707 AS2 (in
,r28
,__SP_L__
) CR_TAB
708 AS2 (in
,r29
,__SP_H__
) "\n");
713 prologue_size
+= out_adj_frame_ptr (file
, size
);
715 if (interrupt_func_p
)
717 prologue_size
+= out_set_stack_ptr (file
, 1, 1);
719 else if (signal_func_p
)
721 prologue_size
+= out_set_stack_ptr (file
, 0, 0);
725 prologue_size
+= out_set_stack_ptr (file
, -1, -1);
733 fprintf (file
, "/* prologue end (size=%d) */\n", prologue_size
);
736 /* Output function epilogue */
739 avr_output_function_epilogue (FILE *file
, HOST_WIDE_INT size
)
742 int interrupt_func_p
;
748 rtx last
= get_last_nonnote_insn ();
750 function_size
= jump_tables_size
;
753 rtx first
= get_first_nonnote_insn ();
754 function_size
+= (INSN_ADDRESSES (INSN_UID (last
)) -
755 INSN_ADDRESSES (INSN_UID (first
)));
756 function_size
+= get_attr_length (last
);
759 fprintf (file
, "/* epilogue: frame size=" HOST_WIDE_INT_PRINT_DEC
" */\n", size
);
762 if (avr_naked_function_p (current_function_decl
))
764 fputs ("/* epilogue: naked */\n", file
);
768 if (last
&& GET_CODE (last
) == BARRIER
)
770 fputs ("/* epilogue: noreturn */\n", file
);
774 interrupt_func_p
= interrupt_function_p (current_function_decl
);
775 signal_func_p
= signal_function_p (current_function_decl
);
776 main_p
= MAIN_NAME_P (DECL_NAME (current_function_decl
));
777 live_seq
= sequent_regs_live ();
778 minimize
= (TARGET_CALL_PROLOGUES
779 && !interrupt_func_p
&& !signal_func_p
&& live_seq
);
783 /* Return value from main() is already in the correct registers
784 (r25:r24) as the exit() argument. */
787 fputs ("\t" AS1 (jmp
,exit
) "\n", file
);
792 fputs ("\t" AS1 (rjmp
,exit
) "\n", file
);
796 else if (minimize
&& (frame_pointer_needed
|| live_seq
> 4))
798 fprintf (file
, ("\t" AS2 (ldi
, r30
, %d
) CR_TAB
), live_seq
);
800 if (frame_pointer_needed
)
802 epilogue_size
+= out_adj_frame_ptr (file
, -size
);
806 fprintf (file
, (AS2 (in
, r28
, __SP_L__
) CR_TAB
807 AS2 (in
, r29
, __SP_H__
) CR_TAB
));
813 fprintf (file
, AS1 (jmp
,__epilogue_restores__
+%d
) "\n",
814 (18 - live_seq
) * 2);
819 fprintf (file
, AS1 (rjmp
,__epilogue_restores__
+%d
) "\n",
820 (18 - live_seq
) * 2);
828 if (frame_pointer_needed
)
833 epilogue_size
+= out_adj_frame_ptr (file
, -size
);
835 if (interrupt_func_p
|| signal_func_p
)
837 epilogue_size
+= out_set_stack_ptr (file
, -1, 0);
841 epilogue_size
+= out_set_stack_ptr (file
, -1, -1);
850 epilogue_size
+= avr_regs_to_save (&set
);
851 for (reg
= 31; reg
>= 0; --reg
)
853 if (TEST_HARD_REG_BIT (set
, reg
))
855 fprintf (file
, "\t" AS1 (pop
,%s
) "\n", avr_regnames
[reg
]);
859 if (interrupt_func_p
|| signal_func_p
)
862 AS1 (pop
,__tmp_reg__
) CR_TAB
863 AS2 (out
,__SREG__
,__tmp_reg__
) CR_TAB
864 AS1 (pop
,__tmp_reg__
) CR_TAB
865 AS1 (pop
,__zero_reg__
) "\n");
867 fprintf (file
, "\treti\n");
870 fprintf (file
, "\tret\n");
875 fprintf (file
, "/* epilogue end (size=%d) */\n", epilogue_size
);
876 fprintf (file
, "/* function %s size %d (%d) */\n", current_function_name
,
877 prologue_size
+ function_size
+ epilogue_size
, function_size
);
878 commands_in_file
+= prologue_size
+ function_size
+ epilogue_size
;
879 commands_in_prologues
+= prologue_size
;
880 commands_in_epilogues
+= epilogue_size
;
884 /* Return nonzero if X (an RTX) is a legitimate memory address on the target
885 machine for a memory operand of mode MODE. */
888 legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
890 enum reg_class r
= NO_REGS
;
892 if (TARGET_ALL_DEBUG
)
894 fprintf (stderr
, "mode: (%s) %s %s %s %s:",
896 strict
? "(strict)": "",
897 reload_completed
? "(reload_completed)": "",
898 reload_in_progress
? "(reload_in_progress)": "",
899 reg_renumber
? "(reg_renumber)" : "");
900 if (GET_CODE (x
) == PLUS
901 && REG_P (XEXP (x
, 0))
902 && GET_CODE (XEXP (x
, 1)) == CONST_INT
903 && INTVAL (XEXP (x
, 1)) >= 0
904 && INTVAL (XEXP (x
, 1)) <= MAX_LD_OFFSET (mode
)
907 fprintf (stderr
, "(r%d ---> r%d)", REGNO (XEXP (x
, 0)),
908 true_regnum (XEXP (x
, 0)));
911 if (REG_P (x
) && (strict
? REG_OK_FOR_BASE_STRICT_P (x
)
912 : REG_OK_FOR_BASE_NOSTRICT_P (x
)))
914 else if (CONSTANT_ADDRESS_P (x
))
916 else if (GET_CODE (x
) == PLUS
917 && REG_P (XEXP (x
, 0))
918 && GET_CODE (XEXP (x
, 1)) == CONST_INT
919 && INTVAL (XEXP (x
, 1)) >= 0)
921 int fit
= INTVAL (XEXP (x
, 1)) <= MAX_LD_OFFSET (mode
);
925 || REGNO (XEXP (x
,0)) == REG_Y
926 || REGNO (XEXP (x
,0)) == REG_Z
)
927 r
= BASE_POINTER_REGS
;
928 if (XEXP (x
,0) == frame_pointer_rtx
929 || XEXP (x
,0) == arg_pointer_rtx
)
930 r
= BASE_POINTER_REGS
;
932 else if (frame_pointer_needed
&& XEXP (x
,0) == frame_pointer_rtx
)
935 else if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
936 && REG_P (XEXP (x
, 0))
937 && (strict
? REG_OK_FOR_BASE_STRICT_P (XEXP (x
, 0))
938 : REG_OK_FOR_BASE_NOSTRICT_P (XEXP (x
, 0))))
942 if (TARGET_ALL_DEBUG
)
944 fprintf (stderr
, " ret = %c\n", r
);
946 return r
== NO_REGS
? 0 : (int)r
;
949 /* Attempts to replace X with a valid
950 memory address for an operand of mode MODE */
953 legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
956 if (TARGET_ALL_DEBUG
)
958 fprintf (stderr
, "legitimize_address mode: %s", GET_MODE_NAME(mode
));
962 if (GET_CODE (oldx
) == PLUS
963 && REG_P (XEXP (oldx
,0)))
965 if (REG_P (XEXP (oldx
,1)))
966 x
= force_reg (GET_MODE (oldx
), oldx
);
967 else if (GET_CODE (XEXP (oldx
, 1)) == CONST_INT
)
969 int offs
= INTVAL (XEXP (oldx
,1));
970 if (frame_pointer_rtx
!= XEXP (oldx
,0))
971 if (offs
> MAX_LD_OFFSET (mode
))
973 if (TARGET_ALL_DEBUG
)
974 fprintf (stderr
, "force_reg (big offset)\n");
975 x
= force_reg (GET_MODE (oldx
), oldx
);
983 /* Return a pointer register name as a string */
986 ptrreg_to_str (int regno
)
990 case REG_X
: return "X";
991 case REG_Y
: return "Y";
992 case REG_Z
: return "Z";
999 /* Return the condition name as a string.
1000 Used in conditional jump constructing */
1003 cond_string (enum rtx_code code
)
1012 if (cc_prev_status
.flags
& CC_OVERFLOW_UNUSABLE
)
1017 if (cc_prev_status
.flags
& CC_OVERFLOW_UNUSABLE
)
1030 /* Output ADDR to FILE as address */
1033 print_operand_address (FILE *file
, rtx addr
)
1035 switch (GET_CODE (addr
))
1038 fprintf (file
, ptrreg_to_str (REGNO (addr
)));
1042 fprintf (file
, "-%s", ptrreg_to_str (REGNO (XEXP (addr
, 0))));
1046 fprintf (file
, "%s+", ptrreg_to_str (REGNO (XEXP (addr
, 0))));
1050 if (CONSTANT_ADDRESS_P (addr
)
1051 && ((GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (addr
))
1052 || GET_CODE (addr
) == LABEL_REF
))
1054 fprintf (file
, "pm(");
1055 output_addr_const (file
,addr
);
1056 fprintf (file
,")");
1059 output_addr_const (file
, addr
);
1064 /* Output X as assembler operand to file FILE */
1067 print_operand (FILE *file
, rtx x
, int code
)
1071 if (code
>= 'A' && code
<= 'D')
1081 if (x
== zero_reg_rtx
)
1082 fprintf (file
, "__zero_reg__");
1084 fprintf (file
, reg_names
[true_regnum (x
) + abcd
]);
1086 else if (GET_CODE (x
) == CONST_INT
)
1087 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) + abcd
);
1088 else if (GET_CODE (x
) == MEM
)
1090 rtx addr
= XEXP (x
,0);
1092 if (CONSTANT_P (addr
) && abcd
)
1095 output_address (addr
);
1096 fprintf (file
, ")+%d", abcd
);
1098 else if (code
== 'o')
1100 if (GET_CODE (addr
) != PLUS
)
1101 fatal_insn ("bad address, not (reg+disp):", addr
);
1103 print_operand (file
, XEXP (addr
, 1), 0);
1105 else if (GET_CODE (addr
) == PLUS
)
1107 print_operand_address (file
, XEXP (addr
,0));
1108 if (REGNO (XEXP (addr
, 0)) == REG_X
)
1109 fatal_insn ("internal compiler error. Bad address:"
1112 print_operand (file
, XEXP (addr
,1), code
);
1115 print_operand_address (file
, addr
);
1117 else if (GET_CODE (x
) == CONST_DOUBLE
)
1121 if (GET_MODE (x
) != SFmode
)
1122 fatal_insn ("internal compiler error. Unknown mode:", x
);
1123 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1124 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1125 fprintf (file
, "0x%lx", val
);
1127 else if (code
== 'j')
1128 fputs (cond_string (GET_CODE (x
)), file
);
1129 else if (code
== 'k')
1130 fputs (cond_string (reverse_condition (GET_CODE (x
))), file
);
1132 print_operand_address (file
, x
);
1135 /* Recognize operand OP of mode MODE used in call instructions */
1138 call_insn_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1140 if (GET_CODE (op
) == MEM
)
1142 rtx inside
= XEXP (op
, 0);
1143 if (register_operand (inside
, Pmode
))
1145 if (CONSTANT_ADDRESS_P (inside
))
1151 /* Update the condition code in the INSN. */
1154 notice_update_cc (rtx body ATTRIBUTE_UNUSED
, rtx insn
)
1158 switch (get_attr_cc (insn
))
1161 /* Insn does not affect CC at all. */
1169 set
= single_set (insn
);
1173 cc_status
.flags
|= CC_NO_OVERFLOW
;
1174 cc_status
.value1
= SET_DEST (set
);
1179 /* Insn sets the Z,N,C flags of CC to recog_operand[0].
1180 The V flag may or may not be known but that's ok because
1181 alter_cond will change tests to use EQ/NE. */
1182 set
= single_set (insn
);
1186 cc_status
.value1
= SET_DEST (set
);
1187 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
;
1192 set
= single_set (insn
);
1195 cc_status
.value1
= SET_SRC (set
);
1199 /* Insn doesn't leave CC in a usable state. */
1202 /* Correct CC for the ashrqi3 with the shift count as CONST_INT != 6 */
1203 set
= single_set (insn
);
1206 rtx src
= SET_SRC (set
);
1208 if (GET_CODE (src
) == ASHIFTRT
1209 && GET_MODE (src
) == QImode
)
1211 rtx x
= XEXP (src
, 1);
1213 if (GET_CODE (x
) == CONST_INT
1216 cc_status
.value1
= SET_DEST (set
);
1217 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
;
1225 /* Return maximum number of consecutive registers of
1226 class CLASS needed to hold a value of mode MODE. */
1229 class_max_nregs (enum reg_class
class ATTRIBUTE_UNUSED
,enum machine_mode mode
)
1231 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
1234 /* Choose mode for jump insn:
1235 1 - relative jump in range -63 <= x <= 62 ;
1236 2 - relative jump in range -2046 <= x <= 2045 ;
1237 3 - absolute jump (only for ATmega[16]03). */
1240 avr_jump_mode (rtx x
, rtx insn
)
1242 int dest_addr
= INSN_ADDRESSES (INSN_UID (GET_MODE (x
) == LABEL_REF
1243 ? XEXP (x
, 0) : x
));
1244 int cur_addr
= INSN_ADDRESSES (INSN_UID (insn
));
1245 int jump_distance
= cur_addr
- dest_addr
;
1247 if (-63 <= jump_distance
&& jump_distance
<= 62)
1249 else if (-2046 <= jump_distance
&& jump_distance
<= 2045)
1257 /* return an AVR condition jump commands.
1258 X is a comparison RTX.
1259 LEN is a number returned by avr_jump_mode function.
1260 if REVERSE nonzero then condition code in X must be reversed. */
1263 ret_cond_branch (rtx x
, int len
, int reverse
)
1265 RTX_CODE cond
= reverse
? reverse_condition (GET_CODE (x
)) : GET_CODE (x
);
1270 if (cc_prev_status
.flags
& CC_OVERFLOW_UNUSABLE
)
1271 return (len
== 1 ? (AS1 (breq
,.+2) CR_TAB
1273 len
== 2 ? (AS1 (breq
,.+4) CR_TAB
1274 AS1 (brmi
,.+2) CR_TAB
1276 (AS1 (breq
,.+6) CR_TAB
1277 AS1 (brmi
,.+4) CR_TAB
1281 return (len
== 1 ? (AS1 (breq
,.+2) CR_TAB
1283 len
== 2 ? (AS1 (breq
,.+4) CR_TAB
1284 AS1 (brlt
,.+2) CR_TAB
1286 (AS1 (breq
,.+6) CR_TAB
1287 AS1 (brlt
,.+4) CR_TAB
1290 return (len
== 1 ? (AS1 (breq
,.+2) CR_TAB
1292 len
== 2 ? (AS1 (breq
,.+4) CR_TAB
1293 AS1 (brlo
,.+2) CR_TAB
1295 (AS1 (breq
,.+6) CR_TAB
1296 AS1 (brlo
,.+4) CR_TAB
1299 if (cc_prev_status
.flags
& CC_OVERFLOW_UNUSABLE
)
1300 return (len
== 1 ? (AS1 (breq
,%0) CR_TAB
1302 len
== 2 ? (AS1 (breq
,.+2) CR_TAB
1303 AS1 (brpl
,.+2) CR_TAB
1305 (AS1 (breq
,.+2) CR_TAB
1306 AS1 (brpl
,.+4) CR_TAB
1309 return (len
== 1 ? (AS1 (breq
,%0) CR_TAB
1311 len
== 2 ? (AS1 (breq
,.+2) CR_TAB
1312 AS1 (brge
,.+2) CR_TAB
1314 (AS1 (breq
,.+2) CR_TAB
1315 AS1 (brge
,.+4) CR_TAB
1318 return (len
== 1 ? (AS1 (breq
,%0) CR_TAB
1320 len
== 2 ? (AS1 (breq
,.+2) CR_TAB
1321 AS1 (brsh
,.+2) CR_TAB
1323 (AS1 (breq
,.+2) CR_TAB
1324 AS1 (brsh
,.+4) CR_TAB
1332 return AS1 (br
%k1
,%0);
1334 return (AS1 (br
%j1
,.+2) CR_TAB
1337 return (AS1 (br
%j1
,.+4) CR_TAB
1346 return AS1 (br
%j1
,%0);
1348 return (AS1 (br
%k1
,.+2) CR_TAB
1351 return (AS1 (br
%k1
,.+4) CR_TAB
1359 /* Predicate function for immediate operand which fits to byte (8bit) */
1362 byte_immediate_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1364 return (GET_CODE (op
) == CONST_INT
1365 && INTVAL (op
) <= 0xff && INTVAL (op
) >= 0);
1368 /* Output all insn addresses and their sizes into the assembly language
1369 output file. This is helpful for debugging whether the length attributes
1370 in the md file are correct.
1371 Output insn cost for next insn. */
1374 final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
1375 int num_operands ATTRIBUTE_UNUSED
)
1377 int uid
= INSN_UID (insn
);
1379 if (TARGET_INSN_SIZE_DUMP
|| TARGET_ALL_DEBUG
)
1381 fprintf (asm_out_file
, "/*DEBUG: 0x%x\t\t%d\t%d */\n",
1382 INSN_ADDRESSES (uid
),
1383 INSN_ADDRESSES (uid
) - last_insn_address
,
1384 rtx_cost (PATTERN (insn
), INSN
));
1386 last_insn_address
= INSN_ADDRESSES (uid
);
1389 /* Return 0 if undefined, 1 if always true or always false. */
1392 avr_simplify_comparison_p (enum machine_mode mode
, RTX_CODE
operator, rtx x
)
1394 unsigned int max
= (mode
== QImode
? 0xff :
1395 mode
== HImode
? 0xffff :
1396 mode
== SImode
? 0xffffffff : 0);
1397 if (max
&& operator && GET_CODE (x
) == CONST_INT
)
1399 if (unsigned_condition (operator) != operator)
1402 if (max
!= (INTVAL (x
) & max
)
1403 && INTVAL (x
) != 0xff)
1410 /* Returns nonzero if REGNO is the number of a hard
1411 register in which function arguments are sometimes passed. */
1414 function_arg_regno_p(int r
)
1416 return (r
>= 8 && r
<= 25);
1419 /* Initializing the variable cum for the state at the beginning
1420 of the argument list. */
1423 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
, rtx libname
,
1424 tree fndecl ATTRIBUTE_UNUSED
)
1427 cum
->regno
= FIRST_CUM_REG
;
1428 if (!libname
&& fntype
)
1430 int stdarg
= (TYPE_ARG_TYPES (fntype
) != 0
1431 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
1432 != void_type_node
));
1438 /* Returns the number of registers to allocate for a function argument. */
1441 avr_num_arg_regs (enum machine_mode mode
, tree type
)
1445 if (mode
== BLKmode
)
1446 size
= int_size_in_bytes (type
);
1448 size
= GET_MODE_SIZE (mode
);
1450 /* Align all function arguments to start in even-numbered registers.
1451 Odd-sized arguments leave holes above them. */
1453 return (size
+ 1) & ~1;
1456 /* Controls whether a function argument is passed
1457 in a register, and which register. */
1460 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
1461 int named ATTRIBUTE_UNUSED
)
1463 int bytes
= avr_num_arg_regs (mode
, type
);
1465 if (cum
->nregs
&& bytes
<= cum
->nregs
)
1466 return gen_rtx (REG
, mode
, cum
->regno
- bytes
);
1471 /* Update the summarizer variable CUM to advance past an argument
1472 in the argument list. */
1475 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
1476 int named ATTRIBUTE_UNUSED
)
1478 int bytes
= avr_num_arg_regs (mode
, type
);
1480 cum
->nregs
-= bytes
;
1481 cum
->regno
-= bytes
;
1483 if (cum
->nregs
<= 0)
1486 cum
->regno
= FIRST_CUM_REG
;
1490 /***********************************************************************
1491 Functions for outputting various mov's for a various modes
1492 ************************************************************************/
1494 output_movqi (rtx insn
, rtx operands
[], int *l
)
1497 rtx dest
= operands
[0];
1498 rtx src
= operands
[1];
1506 if (register_operand (dest
, QImode
))
1508 if (register_operand (src
, QImode
)) /* mov r,r */
1510 if (test_hard_reg_class (STACK_REG
, dest
))
1511 return AS2 (out
,%0,%1);
1512 else if (test_hard_reg_class (STACK_REG
, src
))
1513 return AS2 (in
,%0,%1);
1515 return AS2 (mov
,%0,%1);
1517 else if (CONSTANT_P (src
))
1519 if (test_hard_reg_class (LD_REGS
, dest
)) /* ldi d,i */
1520 return AS2 (ldi
,%0,lo8(%1));
1522 if (GET_CODE (src
) == CONST_INT
)
1524 if (src
== const0_rtx
) /* mov r,L */
1525 return AS1 (clr
,%0);
1526 else if (src
== const1_rtx
)
1529 return (AS1 (clr
,%0) CR_TAB
1532 else if (src
== constm1_rtx
)
1534 /* Immediate constants -1 to any register */
1536 return (AS1 (clr
,%0) CR_TAB
1541 int bit_nr
= exact_log2 (INTVAL (src
));
1547 output_asm_insn ((AS1 (clr
,%0) CR_TAB
1550 avr_output_bld (operands
, bit_nr
);
1557 /* Last resort, larger than loading from memory. */
1559 return (AS2 (mov
,__tmp_reg__
,r31
) CR_TAB
1560 AS2 (ldi
,r31
,lo8(%1)) CR_TAB
1561 AS2 (mov
,%0,r31
) CR_TAB
1562 AS2 (mov
,r31
,__tmp_reg__
));
1564 else if (GET_CODE (src
) == MEM
)
1565 return out_movqi_r_mr (insn
, operands
, real_l
); /* mov r,m */
1567 else if (GET_CODE (dest
) == MEM
)
1569 const char *template;
1571 if (src
== const0_rtx
)
1572 operands
[1] = zero_reg_rtx
;
1574 template = out_movqi_mr_r (insn
, operands
, real_l
);
1577 output_asm_insn (template, operands
);
1586 output_movhi (rtx insn
, rtx operands
[], int *l
)
1589 rtx dest
= operands
[0];
1590 rtx src
= operands
[1];
1596 if (register_operand (dest
, HImode
))
1598 if (register_operand (src
, HImode
)) /* mov r,r */
1600 if (test_hard_reg_class (STACK_REG
, dest
))
1602 if (TARGET_TINY_STACK
)
1605 return AS2 (out
,__SP_L__
,%A1
);
1607 else if (TARGET_NO_INTERRUPTS
)
1610 return (AS2 (out
,__SP_H__
,%B1
) CR_TAB
1611 AS2 (out
,__SP_L__
,%A1
));
1615 return (AS2 (in
,__tmp_reg__
,__SREG__
) CR_TAB
1617 AS2 (out
,__SP_H__
,%B1
) CR_TAB
1618 AS2 (out
,__SREG__
,__tmp_reg__
) CR_TAB
1619 AS2 (out
,__SP_L__
,%A1
));
1621 else if (test_hard_reg_class (STACK_REG
, src
))
1624 return (AS2 (in
,%A0
,__SP_L__
) CR_TAB
1625 AS2 (in
,%B0
,__SP_H__
));
1631 return (AS2 (movw
,%0,%1));
1634 if (true_regnum (dest
) > true_regnum (src
))
1637 return (AS2 (mov
,%B0
,%B1
) CR_TAB
1643 return (AS2 (mov
,%A0
,%A1
) CR_TAB
1647 else if (CONSTANT_P (src
))
1649 if (test_hard_reg_class (LD_REGS
, dest
)) /* ldi d,i */
1652 return (AS2 (ldi
,%A0
,lo8(%1)) CR_TAB
1653 AS2 (ldi
,%B0
,hi8(%1)));
1656 if (GET_CODE (src
) == CONST_INT
)
1658 if (src
== const0_rtx
) /* mov r,L */
1661 return (AS1 (clr
,%A0
) CR_TAB
1664 else if (src
== const1_rtx
)
1667 return (AS1 (clr
,%A0
) CR_TAB
1668 AS1 (clr
,%B0
) CR_TAB
1671 else if (src
== constm1_rtx
)
1673 /* Immediate constants -1 to any register */
1675 return (AS1 (clr
,%0) CR_TAB
1676 AS1 (dec
,%A0
) CR_TAB
1681 int bit_nr
= exact_log2 (INTVAL (src
));
1687 output_asm_insn ((AS1 (clr
,%A0
) CR_TAB
1688 AS1 (clr
,%B0
) CR_TAB
1691 avr_output_bld (operands
, bit_nr
);
1697 if ((INTVAL (src
) & 0xff) == 0)
1700 return (AS2 (mov
,__tmp_reg__
,r31
) CR_TAB
1701 AS1 (clr
,%A0
) CR_TAB
1702 AS2 (ldi
,r31
,hi8(%1)) CR_TAB
1703 AS2 (mov
,%B0
,r31
) CR_TAB
1704 AS2 (mov
,r31
,__tmp_reg__
));
1706 else if ((INTVAL (src
) & 0xff00) == 0)
1709 return (AS2 (mov
,__tmp_reg__
,r31
) CR_TAB
1710 AS2 (ldi
,r31
,lo8(%1)) CR_TAB
1711 AS2 (mov
,%A0
,r31
) CR_TAB
1712 AS1 (clr
,%B0
) CR_TAB
1713 AS2 (mov
,r31
,__tmp_reg__
));
1717 /* Last resort, equal to loading from memory. */
1719 return (AS2 (mov
,__tmp_reg__
,r31
) CR_TAB
1720 AS2 (ldi
,r31
,lo8(%1)) CR_TAB
1721 AS2 (mov
,%A0
,r31
) CR_TAB
1722 AS2 (ldi
,r31
,hi8(%1)) CR_TAB
1723 AS2 (mov
,%B0
,r31
) CR_TAB
1724 AS2 (mov
,r31
,__tmp_reg__
));
1726 else if (GET_CODE (src
) == MEM
)
1727 return out_movhi_r_mr (insn
, operands
, real_l
); /* mov r,m */
1729 else if (GET_CODE (dest
) == MEM
)
1731 const char *template;
1733 if (src
== const0_rtx
)
1734 operands
[1] = zero_reg_rtx
;
1736 template = out_movhi_mr_r (insn
, operands
, real_l
);
1739 output_asm_insn (template, operands
);
1744 fatal_insn ("invalid insn:", insn
);
1749 out_movqi_r_mr (rtx insn
, rtx op
[], int *l
)
1753 rtx x
= XEXP (src
, 0);
1759 if (CONSTANT_ADDRESS_P (x
))
1761 if (avr_io_address_p (x
, 1))
1764 return AS2 (in
,%0,%1-0x20);
1767 return AS2 (lds
,%0,%1);
1769 /* memory access by reg+disp */
1770 else if (GET_CODE (x
) == PLUS
1771 && REG_P (XEXP (x
,0))
1772 && GET_CODE (XEXP (x
,1)) == CONST_INT
)
1774 if ((INTVAL (XEXP (x
,1)) - GET_MODE_SIZE (GET_MODE (src
))) >= 63)
1776 int disp
= INTVAL (XEXP (x
,1));
1777 if (REGNO (XEXP (x
,0)) != REG_Y
)
1778 fatal_insn ("incorrect insn:",insn
);
1780 if (disp
<= 63 + MAX_LD_OFFSET (GET_MODE (src
)))
1781 return *l
= 3, (AS2 (adiw
,r28
,%o1
-63) CR_TAB
1782 AS2 (ldd
,%0,Y
+63) CR_TAB
1783 AS2 (sbiw
,r28
,%o1
-63));
1785 return *l
= 5, (AS2 (subi
,r28
,lo8(-%o1
)) CR_TAB
1786 AS2 (sbci
,r29
,hi8(-%o1
)) CR_TAB
1787 AS2 (ld
,%0,Y
) CR_TAB
1788 AS2 (subi
,r28
,lo8(%o1
)) CR_TAB
1789 AS2 (sbci
,r29
,hi8(%o1
)));
1791 else if (REGNO (XEXP (x
,0)) == REG_X
)
1793 /* This is a paranoid case LEGITIMIZE_RELOAD_ADDRESS must exclude
1794 it but I have this situation with extremal optimizing options. */
1795 if (reg_overlap_mentioned_p (dest
, XEXP (x
,0))
1796 || reg_unused_after (insn
, XEXP (x
,0)))
1797 return *l
= 2, (AS2 (adiw
,r26
,%o1
) CR_TAB
1800 return *l
= 3, (AS2 (adiw
,r26
,%o1
) CR_TAB
1801 AS2 (ld
,%0,X
) CR_TAB
1802 AS2 (sbiw
,r26
,%o1
));
1805 return AS2 (ldd
,%0,%1);
1808 return AS2 (ld
,%0,%1);
1812 out_movhi_r_mr (rtx insn
, rtx op
[], int *l
)
1816 rtx base
= XEXP (src
, 0);
1817 int reg_dest
= true_regnum (dest
);
1818 int reg_base
= true_regnum (base
);
1826 if (reg_dest
== reg_base
) /* R = (R) */
1829 return (AS2 (ld
,__tmp_reg__
,%1+) CR_TAB
1830 AS2 (ld
,%B0
,%1) CR_TAB
1831 AS2 (mov
,%A0
,__tmp_reg__
));
1833 else if (reg_base
== REG_X
) /* (R26) */
1835 if (reg_unused_after (insn
, base
))
1838 return (AS2 (ld
,%A0
,X
+) CR_TAB
1842 return (AS2 (ld
,%A0
,X
+) CR_TAB
1843 AS2 (ld
,%B0
,X
) CR_TAB
1849 return (AS2 (ld
,%A0
,%1) CR_TAB
1850 AS2 (ldd
,%B0
,%1+1));
1853 else if (GET_CODE (base
) == PLUS
) /* (R + i) */
1855 int disp
= INTVAL (XEXP (base
, 1));
1856 int reg_base
= true_regnum (XEXP (base
, 0));
1858 if (disp
> MAX_LD_OFFSET (GET_MODE (src
)))
1860 if (REGNO (XEXP (base
, 0)) != REG_Y
)
1861 fatal_insn ("incorrect insn:",insn
);
1863 if (disp
<= 63 + MAX_LD_OFFSET (GET_MODE (src
)))
1864 return *l
= 4, (AS2 (adiw
,r28
,%o1
-62) CR_TAB
1865 AS2 (ldd
,%A0
,Y
+62) CR_TAB
1866 AS2 (ldd
,%B0
,Y
+63) CR_TAB
1867 AS2 (sbiw
,r28
,%o1
-62));
1869 return *l
= 6, (AS2 (subi
,r28
,lo8(-%o1
)) CR_TAB
1870 AS2 (sbci
,r29
,hi8(-%o1
)) CR_TAB
1871 AS2 (ld
,%A0
,Y
) CR_TAB
1872 AS2 (ldd
,%B0
,Y
+1) CR_TAB
1873 AS2 (subi
,r28
,lo8(%o1
)) CR_TAB
1874 AS2 (sbci
,r29
,hi8(%o1
)));
1876 if (reg_base
== REG_X
)
1878 /* This is a paranoid case. LEGITIMIZE_RELOAD_ADDRESS must exclude
1879 it but I have this situation with extremal
1880 optimization options. */
1883 if (reg_base
== reg_dest
)
1884 return (AS2 (adiw
,r26
,%o1
) CR_TAB
1885 AS2 (ld
,__tmp_reg__
,X
+) CR_TAB
1886 AS2 (ld
,%B0
,X
) CR_TAB
1887 AS2 (mov
,%A0
,__tmp_reg__
));
1889 return (AS2 (adiw
,r26
,%o1
) CR_TAB
1890 AS2 (ld
,%A0
,X
+) CR_TAB
1891 AS2 (ld
,%B0
,X
) CR_TAB
1892 AS2 (sbiw
,r26
,%o1
+1));
1895 if (reg_base
== reg_dest
)
1898 return (AS2 (ldd
,__tmp_reg__
,%A1
) CR_TAB
1899 AS2 (ldd
,%B0
,%B1
) CR_TAB
1900 AS2 (mov
,%A0
,__tmp_reg__
));
1904 return (AS2 (ldd
,%A0
,%A1
) CR_TAB
1907 else if (GET_CODE (base
) == PRE_DEC
) /* (--R) */
1909 if (reg_overlap_mentioned_p (dest
, XEXP (base
, 0)))
1910 fatal_insn ("incorrect insn:", insn
);
1913 return (AS2 (ld
,%B0
,%1) CR_TAB
1916 else if (GET_CODE (base
) == POST_INC
) /* (R++) */
1918 if (reg_overlap_mentioned_p (dest
, XEXP (base
, 0)))
1919 fatal_insn ("incorrect insn:", insn
);
1922 return (AS2 (ld
,%A0
,%1) CR_TAB
1925 else if (CONSTANT_ADDRESS_P (base
))
1927 if (avr_io_address_p (base
, 2))
1930 return (AS2 (in
,%A0
,%A1
-0x20) CR_TAB
1931 AS2 (in
,%B0
,%B1
-0x20));
1934 return (AS2 (lds
,%A0
,%A1
) CR_TAB
1938 fatal_insn ("unknown move insn:",insn
);
1943 out_movsi_r_mr (rtx insn
, rtx op
[], int *l
)
1947 rtx base
= XEXP (src
, 0);
1948 int reg_dest
= true_regnum (dest
);
1949 int reg_base
= true_regnum (base
);
1957 if (reg_base
== REG_X
) /* (R26) */
1959 if (reg_dest
== REG_X
)
1960 /* "ld r26,-X" is undefined */
1961 return *l
=7, (AS2 (adiw
,r26
,3) CR_TAB
1962 AS2 (ld
,r29
,X
) CR_TAB
1963 AS2 (ld
,r28
,-X
) CR_TAB
1964 AS2 (ld
,__tmp_reg__
,-X
) CR_TAB
1965 AS2 (sbiw
,r26
,1) CR_TAB
1966 AS2 (ld
,r26
,X
) CR_TAB
1967 AS2 (mov
,r27
,__tmp_reg__
));
1968 else if (reg_dest
== REG_X
- 2)
1969 return *l
=5, (AS2 (ld
,%A0
,X
+) CR_TAB
1970 AS2 (ld
,%B0
,X
+) CR_TAB
1971 AS2 (ld
,__tmp_reg__
,X
+) CR_TAB
1972 AS2 (ld
,%D0
,X
) CR_TAB
1973 AS2 (mov
,%C0
,__tmp_reg__
));
1974 else if (reg_unused_after (insn
, base
))
1975 return *l
=4, (AS2 (ld
,%A0
,X
+) CR_TAB
1976 AS2 (ld
,%B0
,X
+) CR_TAB
1977 AS2 (ld
,%C0
,X
+) CR_TAB
1980 return *l
=5, (AS2 (ld
,%A0
,X
+) CR_TAB
1981 AS2 (ld
,%B0
,X
+) CR_TAB
1982 AS2 (ld
,%C0
,X
+) CR_TAB
1983 AS2 (ld
,%D0
,X
) CR_TAB
1988 if (reg_dest
== reg_base
)
1989 return *l
=5, (AS2 (ldd
,%D0
,%1+3) CR_TAB
1990 AS2 (ldd
,%C0
,%1+2) CR_TAB
1991 AS2 (ldd
,__tmp_reg__
,%1+1) CR_TAB
1992 AS2 (ld
,%A0
,%1) CR_TAB
1993 AS2 (mov
,%B0
,__tmp_reg__
));
1994 else if (reg_base
== reg_dest
+ 2)
1995 return *l
=5, (AS2 (ld
,%A0
,%1) CR_TAB
1996 AS2 (ldd
,%B0
,%1+1) CR_TAB
1997 AS2 (ldd
,__tmp_reg__
,%1+2) CR_TAB
1998 AS2 (ldd
,%D0
,%1+3) CR_TAB
1999 AS2 (mov
,%C0
,__tmp_reg__
));
2001 return *l
=4, (AS2 (ld
,%A0
,%1) CR_TAB
2002 AS2 (ldd
,%B0
,%1+1) CR_TAB
2003 AS2 (ldd
,%C0
,%1+2) CR_TAB
2004 AS2 (ldd
,%D0
,%1+3));
2007 else if (GET_CODE (base
) == PLUS
) /* (R + i) */
2009 int disp
= INTVAL (XEXP (base
, 1));
2011 if (disp
> MAX_LD_OFFSET (GET_MODE (src
)))
2013 if (REGNO (XEXP (base
, 0)) != REG_Y
)
2014 fatal_insn ("incorrect insn:",insn
);
2016 if (disp
<= 63 + MAX_LD_OFFSET (GET_MODE (src
)))
2017 return *l
= 6, (AS2 (adiw
,r28
,%o1
-60) CR_TAB
2018 AS2 (ldd
,%A0
,Y
+60) CR_TAB
2019 AS2 (ldd
,%B0
,Y
+61) CR_TAB
2020 AS2 (ldd
,%C0
,Y
+62) CR_TAB
2021 AS2 (ldd
,%D0
,Y
+63) CR_TAB
2022 AS2 (sbiw
,r28
,%o1
-60));
2024 return *l
= 8, (AS2 (subi
,r28
,lo8(-%o1
)) CR_TAB
2025 AS2 (sbci
,r29
,hi8(-%o1
)) CR_TAB
2026 AS2 (ld
,%A0
,Y
) CR_TAB
2027 AS2 (ldd
,%B0
,Y
+1) CR_TAB
2028 AS2 (ldd
,%C0
,Y
+2) CR_TAB
2029 AS2 (ldd
,%D0
,Y
+3) CR_TAB
2030 AS2 (subi
,r28
,lo8(%o1
)) CR_TAB
2031 AS2 (sbci
,r29
,hi8(%o1
)));
2034 reg_base
= true_regnum (XEXP (base
, 0));
2035 if (reg_base
== REG_X
)
2038 if (reg_dest
== REG_X
)
2041 /* "ld r26,-X" is undefined */
2042 return (AS2 (adiw
,r26
,%o1
+3) CR_TAB
2043 AS2 (ld
,r29
,X
) CR_TAB
2044 AS2 (ld
,r28
,-X
) CR_TAB
2045 AS2 (ld
,__tmp_reg__
,-X
) CR_TAB
2046 AS2 (sbiw
,r26
,1) CR_TAB
2047 AS2 (ld
,r26
,X
) CR_TAB
2048 AS2 (mov
,r27
,__tmp_reg__
));
2051 if (reg_dest
== REG_X
- 2)
2052 return (AS2 (adiw
,r26
,%o1
) CR_TAB
2053 AS2 (ld
,r24
,X
+) CR_TAB
2054 AS2 (ld
,r25
,X
+) CR_TAB
2055 AS2 (ld
,__tmp_reg__
,X
+) CR_TAB
2056 AS2 (ld
,r27
,X
) CR_TAB
2057 AS2 (mov
,r26
,__tmp_reg__
));
2059 return (AS2 (adiw
,r26
,%o1
) CR_TAB
2060 AS2 (ld
,%A0
,X
+) CR_TAB
2061 AS2 (ld
,%B0
,X
+) CR_TAB
2062 AS2 (ld
,%C0
,X
+) CR_TAB
2063 AS2 (ld
,%D0
,X
) CR_TAB
2064 AS2 (sbiw
,r26
,%o1
+3));
2066 if (reg_dest
== reg_base
)
2067 return *l
=5, (AS2 (ldd
,%D0
,%D1
) CR_TAB
2068 AS2 (ldd
,%C0
,%C1
) CR_TAB
2069 AS2 (ldd
,__tmp_reg__
,%B1
) CR_TAB
2070 AS2 (ldd
,%A0
,%A1
) CR_TAB
2071 AS2 (mov
,%B0
,__tmp_reg__
));
2072 else if (reg_dest
== reg_base
- 2)
2073 return *l
=5, (AS2 (ldd
,%A0
,%A1
) CR_TAB
2074 AS2 (ldd
,%B0
,%B1
) CR_TAB
2075 AS2 (ldd
,__tmp_reg__
,%C1
) CR_TAB
2076 AS2 (ldd
,%D0
,%D1
) CR_TAB
2077 AS2 (mov
,%C0
,__tmp_reg__
));
2078 return *l
=4, (AS2 (ldd
,%A0
,%A1
) CR_TAB
2079 AS2 (ldd
,%B0
,%B1
) CR_TAB
2080 AS2 (ldd
,%C0
,%C1
) CR_TAB
2083 else if (GET_CODE (base
) == PRE_DEC
) /* (--R) */
2084 return *l
=4, (AS2 (ld
,%D0
,%1) CR_TAB
2085 AS2 (ld
,%C0
,%1) CR_TAB
2086 AS2 (ld
,%B0
,%1) CR_TAB
2088 else if (GET_CODE (base
) == POST_INC
) /* (R++) */
2089 return *l
=4, (AS2 (ld
,%A0
,%1) CR_TAB
2090 AS2 (ld
,%B0
,%1) CR_TAB
2091 AS2 (ld
,%C0
,%1) CR_TAB
2093 else if (CONSTANT_ADDRESS_P (base
))
2094 return *l
=8, (AS2 (lds
,%A0
,%A1
) CR_TAB
2095 AS2 (lds
,%B0
,%B1
) CR_TAB
2096 AS2 (lds
,%C0
,%C1
) CR_TAB
2099 fatal_insn ("unknown move insn:",insn
);
2104 out_movsi_mr_r (rtx insn
, rtx op
[], int *l
)
2108 rtx base
= XEXP (dest
, 0);
2109 int reg_base
= true_regnum (base
);
2110 int reg_src
= true_regnum (src
);
2116 if (CONSTANT_ADDRESS_P (base
))
2117 return *l
=8,(AS2 (sts
,%A0
,%A1
) CR_TAB
2118 AS2 (sts
,%B0
,%B1
) CR_TAB
2119 AS2 (sts
,%C0
,%C1
) CR_TAB
2121 if (reg_base
> 0) /* (r) */
2123 if (reg_base
== REG_X
) /* (R26) */
2125 if (reg_src
== REG_X
)
2127 /* "st X+,r26" is undefined */
2128 if (reg_unused_after (insn
, base
))
2129 return *l
=6, (AS2 (mov
,__tmp_reg__
,r27
) CR_TAB
2130 AS2 (st
,X
,r26
) CR_TAB
2131 AS2 (adiw
,r26
,1) CR_TAB
2132 AS2 (st
,X
+,__tmp_reg__
) CR_TAB
2133 AS2 (st
,X
+,r28
) CR_TAB
2136 return *l
=7, (AS2 (mov
,__tmp_reg__
,r27
) CR_TAB
2137 AS2 (st
,X
,r26
) CR_TAB
2138 AS2 (adiw
,r26
,1) CR_TAB
2139 AS2 (st
,X
+,__tmp_reg__
) CR_TAB
2140 AS2 (st
,X
+,r28
) CR_TAB
2141 AS2 (st
,X
,r29
) CR_TAB
2144 else if (reg_base
== reg_src
+ 2)
2146 if (reg_unused_after (insn
, base
))
2147 return *l
=7, (AS2 (mov
,__zero_reg__
,%C1
) CR_TAB
2148 AS2 (mov
,__tmp_reg__
,%D1
) CR_TAB
2149 AS2 (st
,%0+,%A1
) CR_TAB
2150 AS2 (st
,%0+,%B1
) CR_TAB
2151 AS2 (st
,%0+,__zero_reg__
) CR_TAB
2152 AS2 (st
,%0,__tmp_reg__
) CR_TAB
2153 AS1 (clr
,__zero_reg__
));
2155 return *l
=8, (AS2 (mov
,__zero_reg__
,%C1
) CR_TAB
2156 AS2 (mov
,__tmp_reg__
,%D1
) CR_TAB
2157 AS2 (st
,%0+,%A1
) CR_TAB
2158 AS2 (st
,%0+,%B1
) CR_TAB
2159 AS2 (st
,%0+,__zero_reg__
) CR_TAB
2160 AS2 (st
,%0,__tmp_reg__
) CR_TAB
2161 AS1 (clr
,__zero_reg__
) CR_TAB
2164 return *l
=5, (AS2 (st
,%0+,%A1
) CR_TAB
2165 AS2 (st
,%0+,%B1
) CR_TAB
2166 AS2 (st
,%0+,%C1
) CR_TAB
2167 AS2 (st
,%0,%D1
) CR_TAB
2171 return *l
=4, (AS2 (st
,%0,%A1
) CR_TAB
2172 AS2 (std
,%0+1,%B1
) CR_TAB
2173 AS2 (std
,%0+2,%C1
) CR_TAB
2174 AS2 (std
,%0+3,%D1
));
2176 else if (GET_CODE (base
) == PLUS
) /* (R + i) */
2178 int disp
= INTVAL (XEXP (base
, 1));
2179 reg_base
= REGNO (XEXP (base
, 0));
2180 if (disp
> MAX_LD_OFFSET (GET_MODE (dest
)))
2182 if (reg_base
!= REG_Y
)
2183 fatal_insn ("incorrect insn:",insn
);
2185 if (disp
<= 63 + MAX_LD_OFFSET (GET_MODE (dest
)))
2186 return *l
= 6, (AS2 (adiw
,r28
,%o0
-60) CR_TAB
2187 AS2 (std
,Y
+60,%A1
) CR_TAB
2188 AS2 (std
,Y
+61,%B1
) CR_TAB
2189 AS2 (std
,Y
+62,%C1
) CR_TAB
2190 AS2 (std
,Y
+63,%D1
) CR_TAB
2191 AS2 (sbiw
,r28
,%o0
-60));
2193 return *l
= 8, (AS2 (subi
,r28
,lo8(-%o0
)) CR_TAB
2194 AS2 (sbci
,r29
,hi8(-%o0
)) CR_TAB
2195 AS2 (st
,Y
,%A1
) CR_TAB
2196 AS2 (std
,Y
+1,%B1
) CR_TAB
2197 AS2 (std
,Y
+2,%C1
) CR_TAB
2198 AS2 (std
,Y
+3,%D1
) CR_TAB
2199 AS2 (subi
,r28
,lo8(%o0
)) CR_TAB
2200 AS2 (sbci
,r29
,hi8(%o0
)));
2202 if (reg_base
== REG_X
)
2205 if (reg_src
== REG_X
)
2208 return (AS2 (mov
,__tmp_reg__
,r26
) CR_TAB
2209 AS2 (mov
,__zero_reg__
,r27
) CR_TAB
2210 AS2 (adiw
,r26
,%o0
) CR_TAB
2211 AS2 (st
,X
+,__tmp_reg__
) CR_TAB
2212 AS2 (st
,X
+,__zero_reg__
) CR_TAB
2213 AS2 (st
,X
+,r28
) CR_TAB
2214 AS2 (st
,X
,r29
) CR_TAB
2215 AS1 (clr
,__zero_reg__
) CR_TAB
2216 AS2 (sbiw
,r26
,%o0
+3));
2218 else if (reg_src
== REG_X
- 2)
2221 return (AS2 (mov
,__tmp_reg__
,r26
) CR_TAB
2222 AS2 (mov
,__zero_reg__
,r27
) CR_TAB
2223 AS2 (adiw
,r26
,%o0
) CR_TAB
2224 AS2 (st
,X
+,r24
) CR_TAB
2225 AS2 (st
,X
+,r25
) CR_TAB
2226 AS2 (st
,X
+,__tmp_reg__
) CR_TAB
2227 AS2 (st
,X
,__zero_reg__
) CR_TAB
2228 AS1 (clr
,__zero_reg__
) CR_TAB
2229 AS2 (sbiw
,r26
,%o0
+3));
2232 return (AS2 (adiw
,r26
,%o0
) CR_TAB
2233 AS2 (st
,X
+,%A1
) CR_TAB
2234 AS2 (st
,X
+,%B1
) CR_TAB
2235 AS2 (st
,X
+,%C1
) CR_TAB
2236 AS2 (st
,X
,%D1
) CR_TAB
2237 AS2 (sbiw
,r26
,%o0
+3));
2239 return *l
=4, (AS2 (std
,%A0
,%A1
) CR_TAB
2240 AS2 (std
,%B0
,%B1
) CR_TAB
2241 AS2 (std
,%C0
,%C1
) CR_TAB
2244 else if (GET_CODE (base
) == PRE_DEC
) /* (--R) */
2245 return *l
=4, (AS2 (st
,%0,%D1
) CR_TAB
2246 AS2 (st
,%0,%C1
) CR_TAB
2247 AS2 (st
,%0,%B1
) CR_TAB
2249 else if (GET_CODE (base
) == POST_INC
) /* (R++) */
2250 return *l
=4, (AS2 (st
,%0,%A1
) CR_TAB
2251 AS2 (st
,%0,%B1
) CR_TAB
2252 AS2 (st
,%0,%C1
) CR_TAB
2254 fatal_insn ("unknown move insn:",insn
);
2259 output_movsisf(rtx insn
, rtx operands
[], int *l
)
2262 rtx dest
= operands
[0];
2263 rtx src
= operands
[1];
2269 if (register_operand (dest
, VOIDmode
))
2271 if (register_operand (src
, VOIDmode
)) /* mov r,r */
2273 if (true_regnum (dest
) > true_regnum (src
))
2278 return (AS2 (movw
,%C0
,%C1
) CR_TAB
2279 AS2 (movw
,%A0
,%A1
));
2282 return (AS2 (mov
,%D0
,%D1
) CR_TAB
2283 AS2 (mov
,%C0
,%C1
) CR_TAB
2284 AS2 (mov
,%B0
,%B1
) CR_TAB
2292 return (AS2 (movw
,%A0
,%A1
) CR_TAB
2293 AS2 (movw
,%C0
,%C1
));
2296 return (AS2 (mov
,%A0
,%A1
) CR_TAB
2297 AS2 (mov
,%B0
,%B1
) CR_TAB
2298 AS2 (mov
,%C0
,%C1
) CR_TAB
2302 else if (CONSTANT_P (src
))
2304 if (test_hard_reg_class (LD_REGS
, dest
)) /* ldi d,i */
2307 return (AS2 (ldi
,%A0
,lo8(%1)) CR_TAB
2308 AS2 (ldi
,%B0
,hi8(%1)) CR_TAB
2309 AS2 (ldi
,%C0
,hlo8(%1)) CR_TAB
2310 AS2 (ldi
,%D0
,hhi8(%1)));
2313 if (GET_CODE (src
) == CONST_INT
)
2315 const char *const clr_op0
=
2316 AVR_ENHANCED
? (AS1 (clr
,%A0
) CR_TAB
2317 AS1 (clr
,%B0
) CR_TAB
2319 : (AS1 (clr
,%A0
) CR_TAB
2320 AS1 (clr
,%B0
) CR_TAB
2321 AS1 (clr
,%C0
) CR_TAB
2324 if (src
== const0_rtx
) /* mov r,L */
2326 *l
= AVR_ENHANCED
? 3 : 4;
2329 else if (src
== const1_rtx
)
2332 output_asm_insn (clr_op0
, operands
);
2333 *l
= AVR_ENHANCED
? 4 : 5;
2334 return AS1 (inc
,%A0
);
2336 else if (src
== constm1_rtx
)
2338 /* Immediate constants -1 to any register */
2342 return (AS1 (clr
,%A0
) CR_TAB
2343 AS1 (dec
,%A0
) CR_TAB
2344 AS2 (mov
,%B0
,%A0
) CR_TAB
2345 AS2 (movw
,%C0
,%A0
));
2348 return (AS1 (clr
,%A0
) CR_TAB
2349 AS1 (dec
,%A0
) CR_TAB
2350 AS2 (mov
,%B0
,%A0
) CR_TAB
2351 AS2 (mov
,%C0
,%A0
) CR_TAB
2356 int bit_nr
= exact_log2 (INTVAL (src
));
2360 *l
= AVR_ENHANCED
? 5 : 6;
2363 output_asm_insn (clr_op0
, operands
);
2364 output_asm_insn ("set", operands
);
2367 avr_output_bld (operands
, bit_nr
);
2374 /* Last resort, better than loading from memory. */
2376 return (AS2 (mov
,__tmp_reg__
,r31
) CR_TAB
2377 AS2 (ldi
,r31
,lo8(%1)) CR_TAB
2378 AS2 (mov
,%A0
,r31
) CR_TAB
2379 AS2 (ldi
,r31
,hi8(%1)) CR_TAB
2380 AS2 (mov
,%B0
,r31
) CR_TAB
2381 AS2 (ldi
,r31
,hlo8(%1)) CR_TAB
2382 AS2 (mov
,%C0
,r31
) CR_TAB
2383 AS2 (ldi
,r31
,hhi8(%1)) CR_TAB
2384 AS2 (mov
,%D0
,r31
) CR_TAB
2385 AS2 (mov
,r31
,__tmp_reg__
));
2387 else if (GET_CODE (src
) == MEM
)
2388 return out_movsi_r_mr (insn
, operands
, real_l
); /* mov r,m */
2390 else if (GET_CODE (dest
) == MEM
)
2392 const char *template;
2394 if (src
== const0_rtx
)
2395 operands
[1] = zero_reg_rtx
;
2397 template = out_movsi_mr_r (insn
, operands
, real_l
);
2400 output_asm_insn (template, operands
);
2405 fatal_insn ("invalid insn:", insn
);
2410 out_movqi_mr_r (rtx insn
, rtx op
[], int *l
)
2414 rtx x
= XEXP (dest
, 0);
2420 if (CONSTANT_ADDRESS_P (x
))
2422 if (avr_io_address_p (x
, 1))
2425 return AS2 (out
,%0-0x20,%1);
2428 return AS2 (sts
,%0,%1);
2430 /* memory access by reg+disp */
2431 else if (GET_CODE (x
) == PLUS
2432 && REG_P (XEXP (x
,0))
2433 && GET_CODE (XEXP (x
,1)) == CONST_INT
)
2435 if ((INTVAL (XEXP (x
,1)) - GET_MODE_SIZE (GET_MODE (dest
))) >= 63)
2437 int disp
= INTVAL (XEXP (x
,1));
2438 if (REGNO (XEXP (x
,0)) != REG_Y
)
2439 fatal_insn ("incorrect insn:",insn
);
2441 if (disp
<= 63 + MAX_LD_OFFSET (GET_MODE (dest
)))
2442 return *l
= 3, (AS2 (adiw
,r28
,%o0
-63) CR_TAB
2443 AS2 (std
,Y
+63,%1) CR_TAB
2444 AS2 (sbiw
,r28
,%o0
-63));
2446 return *l
= 5, (AS2 (subi
,r28
,lo8(-%o0
)) CR_TAB
2447 AS2 (sbci
,r29
,hi8(-%o0
)) CR_TAB
2448 AS2 (st
,Y
,%1) CR_TAB
2449 AS2 (subi
,r28
,lo8(%o0
)) CR_TAB
2450 AS2 (sbci
,r29
,hi8(%o0
)));
2452 else if (REGNO (XEXP (x
,0)) == REG_X
)
2454 if (reg_overlap_mentioned_p (src
, XEXP (x
, 0)))
2456 if (reg_unused_after (insn
, XEXP (x
,0)))
2457 return *l
= 3, (AS2 (mov
,__tmp_reg__
,%1) CR_TAB
2458 AS2 (adiw
,r26
,%o0
) CR_TAB
2459 AS2 (st
,X
,__tmp_reg__
));
2461 return *l
= 4, (AS2 (mov
,__tmp_reg__
,%1) CR_TAB
2462 AS2 (adiw
,r26
,%o0
) CR_TAB
2463 AS2 (st
,X
,__tmp_reg__
) CR_TAB
2464 AS2 (sbiw
,r26
,%o0
));
2468 if (reg_unused_after (insn
, XEXP (x
,0)))
2469 return *l
= 2, (AS2 (adiw
,r26
,%o0
) CR_TAB
2472 return *l
= 3, (AS2 (adiw
,r26
,%o0
) CR_TAB
2473 AS2 (st
,X
,%1) CR_TAB
2474 AS2 (sbiw
,r26
,%o0
));
2478 return AS2 (std
,%0,%1);
2481 return AS2 (st
,%0,%1);
2485 out_movhi_mr_r (rtx insn
, rtx op
[], int *l
)
2489 rtx base
= XEXP (dest
, 0);
2490 int reg_base
= true_regnum (base
);
2491 int reg_src
= true_regnum (src
);
2495 if (CONSTANT_ADDRESS_P (base
))
2497 if (avr_io_address_p (base
, 2))
2500 return (AS2 (out
,%B0
-0x20,%B1
) CR_TAB
2501 AS2 (out
,%A0
-0x20,%A1
));
2503 return *l
= 4, (AS2 (sts
,%B0
,%B1
) CR_TAB
2508 if (reg_base
== REG_X
)
2510 if (reg_src
== REG_X
)
2512 /* "st X+,r26" is undefined */
2513 if (reg_unused_after (insn
, src
))
2514 return *l
=4, (AS2 (mov
,__tmp_reg__
,r27
) CR_TAB
2515 AS2 (st
,X
,r26
) CR_TAB
2516 AS2 (adiw
,r26
,1) CR_TAB
2517 AS2 (st
,X
,__tmp_reg__
));
2519 return *l
=5, (AS2 (mov
,__tmp_reg__
,r27
) CR_TAB
2520 AS2 (st
,X
,r26
) CR_TAB
2521 AS2 (adiw
,r26
,1) CR_TAB
2522 AS2 (st
,X
,__tmp_reg__
) CR_TAB
2527 if (reg_unused_after (insn
, base
))
2528 return *l
=2, (AS2 (st
,X
+,%A1
) CR_TAB
2531 return *l
=3, (AS2 (st
,X
+,%A1
) CR_TAB
2532 AS2 (st
,X
,%B1
) CR_TAB
2537 return *l
=2, (AS2 (st
,%0,%A1
) CR_TAB
2538 AS2 (std
,%0+1,%B1
));
2540 else if (GET_CODE (base
) == PLUS
)
2542 int disp
= INTVAL (XEXP (base
, 1));
2543 reg_base
= REGNO (XEXP (base
, 0));
2544 if (disp
> MAX_LD_OFFSET (GET_MODE (dest
)))
2546 if (reg_base
!= REG_Y
)
2547 fatal_insn ("incorrect insn:",insn
);
2549 if (disp
<= 63 + MAX_LD_OFFSET (GET_MODE (dest
)))
2550 return *l
= 4, (AS2 (adiw
,r28
,%o0
-62) CR_TAB
2551 AS2 (std
,Y
+62,%A1
) CR_TAB
2552 AS2 (std
,Y
+63,%B1
) CR_TAB
2553 AS2 (sbiw
,r28
,%o0
-62));
2555 return *l
= 6, (AS2 (subi
,r28
,lo8(-%o0
)) CR_TAB
2556 AS2 (sbci
,r29
,hi8(-%o0
)) CR_TAB
2557 AS2 (st
,Y
,%A1
) CR_TAB
2558 AS2 (std
,Y
+1,%B1
) CR_TAB
2559 AS2 (subi
,r28
,lo8(%o0
)) CR_TAB
2560 AS2 (sbci
,r29
,hi8(%o0
)));
2562 if (reg_base
== REG_X
)
2565 if (reg_src
== REG_X
)
2568 return (AS2 (mov
,__tmp_reg__
,r26
) CR_TAB
2569 AS2 (mov
,__zero_reg__
,r27
) CR_TAB
2570 AS2 (adiw
,r26
,%o0
) CR_TAB
2571 AS2 (st
,X
+,__tmp_reg__
) CR_TAB
2572 AS2 (st
,X
,__zero_reg__
) CR_TAB
2573 AS1 (clr
,__zero_reg__
) CR_TAB
2574 AS2 (sbiw
,r26
,%o0
+1));
2577 return (AS2 (adiw
,r26
,%o0
) CR_TAB
2578 AS2 (st
,X
+,%A1
) CR_TAB
2579 AS2 (st
,X
,%B1
) CR_TAB
2580 AS2 (sbiw
,r26
,%o0
+1));
2582 return *l
=2, (AS2 (std
,%A0
,%A1
) CR_TAB
2585 else if (GET_CODE (base
) == PRE_DEC
) /* (--R) */
2586 return *l
=2, (AS2 (st
,%0,%B1
) CR_TAB
2588 else if (GET_CODE (base
) == POST_INC
) /* (R++) */
2589 return *l
=2, (AS2 (st
,%0,%A1
) CR_TAB
2591 fatal_insn ("unknown move insn:",insn
);
2595 /* Return 1 if frame pointer for current function required */
2598 frame_pointer_required_p (void)
2600 return (current_function_calls_alloca
2601 || current_function_args_info
.nregs
== 0
2602 || get_frame_size () > 0);
2605 /* Returns the condition of compare insn INSN, or UNKNOWN. */
2608 compare_condition (rtx insn
)
2610 rtx next
= next_real_insn (insn
);
2611 RTX_CODE cond
= UNKNOWN
;
2612 if (next
&& GET_CODE (next
) == JUMP_INSN
)
2614 rtx pat
= PATTERN (next
);
2615 rtx src
= SET_SRC (pat
);
2616 rtx t
= XEXP (src
, 0);
2617 cond
= GET_CODE (t
);
2622 /* Returns nonzero if INSN is a tst insn that only tests the sign. */
2625 compare_sign_p (rtx insn
)
2627 RTX_CODE cond
= compare_condition (insn
);
2628 return (cond
== GE
|| cond
== LT
);
2631 /* Returns nonzero if the next insn is a JUMP_INSN with a condition
2632 that needs to be swapped (GT, GTU, LE, LEU). */
2635 compare_diff_p (rtx insn
)
2637 RTX_CODE cond
= compare_condition (insn
);
2638 return (cond
== GT
|| cond
== GTU
|| cond
== LE
|| cond
== LEU
) ? cond
: 0;
2641 /* Returns nonzero if INSN is a compare insn with the EQ or NE condition. */
2644 compare_eq_p (rtx insn
)
2646 RTX_CODE cond
= compare_condition (insn
);
2647 return (cond
== EQ
|| cond
== NE
);
2651 /* Output test instruction for HImode */
2654 out_tsthi (rtx insn
, int *l
)
2656 if (compare_sign_p (insn
))
2659 return AS1 (tst
,%B0
);
2661 if (reg_unused_after (insn
, SET_SRC (PATTERN (insn
)))
2662 && compare_eq_p (insn
))
2664 /* faster than sbiw if we can clobber the operand */
2666 return AS2 (or,%A0
,%B0
);
2668 if (test_hard_reg_class (ADDW_REGS
, SET_SRC (PATTERN (insn
))))
2671 return AS2 (sbiw
,%0,0);
2674 return (AS2 (cp
,%A0
,__zero_reg__
) CR_TAB
2675 AS2 (cpc
,%B0
,__zero_reg__
));
2679 /* Output test instruction for SImode */
2682 out_tstsi (rtx insn
, int *l
)
2684 if (compare_sign_p (insn
))
2687 return AS1 (tst
,%D0
);
2689 if (test_hard_reg_class (ADDW_REGS
, SET_SRC (PATTERN (insn
))))
2692 return (AS2 (sbiw
,%A0
,0) CR_TAB
2693 AS2 (cpc
,%C0
,__zero_reg__
) CR_TAB
2694 AS2 (cpc
,%D0
,__zero_reg__
));
2697 return (AS2 (cp
,%A0
,__zero_reg__
) CR_TAB
2698 AS2 (cpc
,%B0
,__zero_reg__
) CR_TAB
2699 AS2 (cpc
,%C0
,__zero_reg__
) CR_TAB
2700 AS2 (cpc
,%D0
,__zero_reg__
));
2704 /* Generate asm equivalent for various shifts.
2705 Shift count is a CONST_INT, MEM or REG.
2706 This only handles cases that are not already
2707 carefully hand-optimized in ?sh??i3_out. */
2710 out_shift_with_cnt (const char *template, rtx insn
, rtx operands
[],
2711 int *len
, int t_len
)
2715 int second_label
= 1;
2716 int saved_in_tmp
= 0;
2717 int use_zero_reg
= 0;
2719 op
[0] = operands
[0];
2720 op
[1] = operands
[1];
2721 op
[2] = operands
[2];
2722 op
[3] = operands
[3];
2728 if (GET_CODE (operands
[2]) == CONST_INT
)
2730 int scratch
= (GET_CODE (PATTERN (insn
)) == PARALLEL
);
2731 int count
= INTVAL (operands
[2]);
2732 int max_len
= 10; /* If larger than this, always use a loop. */
2734 if (count
< 8 && !scratch
)
2738 max_len
= t_len
+ (scratch
? 3 : (use_zero_reg
? 4 : 5));
2740 if (t_len
* count
<= max_len
)
2742 /* Output shifts inline with no loop - faster. */
2744 *len
= t_len
* count
;
2748 output_asm_insn (template, op
);
2757 strcat (str
, AS2 (ldi
,%3,%2));
2759 else if (use_zero_reg
)
2761 /* Hack to save one word: use __zero_reg__ as loop counter.
2762 Set one bit, then shift in a loop until it is 0 again. */
2764 op
[3] = zero_reg_rtx
;
2768 strcat (str
, ("set" CR_TAB
2769 AS2 (bld
,%3,%2-1)));
2773 /* No scratch register available, use one from LD_REGS (saved in
2774 __tmp_reg__) that doesn't overlap with registers to shift. */
2776 op
[3] = gen_rtx (REG
, QImode
,
2777 ((true_regnum (operands
[0]) - 1) & 15) + 16);
2778 op
[4] = tmp_reg_rtx
;
2782 *len
= 3; /* Includes "mov %3,%4" after the loop. */
2784 strcat (str
, (AS2 (mov
,%4,%3) CR_TAB
2790 else if (GET_CODE (operands
[2]) == MEM
)
2794 op
[3] = op_mov
[0] = tmp_reg_rtx
;
2798 out_movqi_r_mr (insn
, op_mov
, len
);
2800 output_asm_insn (out_movqi_r_mr (insn
, op_mov
, NULL
), op_mov
);
2802 else if (register_operand (operands
[2], QImode
))
2804 if (reg_unused_after (insn
, operands
[2]))
2808 op
[3] = tmp_reg_rtx
;
2810 strcat (str
, (AS2 (mov
,%3,%2) CR_TAB
));
2814 fatal_insn ("bad shift insn:", insn
);
2821 strcat (str
, AS1 (rjmp
,2f
));
2825 *len
+= t_len
+ 2; /* template + dec + brXX */
2828 strcat (str
, "\n1:\t");
2829 strcat (str
, template);
2830 strcat (str
, second_label
? "\n2:\t" : "\n\t");
2831 strcat (str
, use_zero_reg
? AS1 (lsr
,%3) : AS1 (dec
,%3));
2832 strcat (str
, CR_TAB
);
2833 strcat (str
, second_label
? AS1 (brpl
,1b
) : AS1 (brne
,1b
));
2835 strcat (str
, (CR_TAB
AS2 (mov
,%3,%4)));
2836 output_asm_insn (str
, op
);
2841 /* 8bit shift left ((char)x << i) */
2844 ashlqi3_out (rtx insn
, rtx operands
[], int *len
)
2846 if (GET_CODE (operands
[2]) == CONST_INT
)
2853 switch (INTVAL (operands
[2]))
2857 return AS1 (clr
,%0);
2861 return AS1 (lsl
,%0);
2865 return (AS1 (lsl
,%0) CR_TAB
2870 return (AS1 (lsl
,%0) CR_TAB
2875 if (test_hard_reg_class (LD_REGS
, operands
[0]))
2878 return (AS1 (swap
,%0) CR_TAB
2879 AS2 (andi
,%0,0xf0));
2882 return (AS1 (lsl
,%0) CR_TAB
2888 if (test_hard_reg_class (LD_REGS
, operands
[0]))
2891 return (AS1 (swap
,%0) CR_TAB
2893 AS2 (andi
,%0,0xe0));
2896 return (AS1 (lsl
,%0) CR_TAB
2903 if (test_hard_reg_class (LD_REGS
, operands
[0]))
2906 return (AS1 (swap
,%0) CR_TAB
2909 AS2 (andi
,%0,0xc0));
2912 return (AS1 (lsl
,%0) CR_TAB
2921 return (AS1 (ror
,%0) CR_TAB
2926 else if (CONSTANT_P (operands
[2]))
2927 fatal_insn ("internal compiler error. Incorrect shift:", insn
);
2929 out_shift_with_cnt (AS1 (lsl
,%0),
2930 insn
, operands
, len
, 1);
2935 /* 16bit shift left ((short)x << i) */
2938 ashlhi3_out (rtx insn
, rtx operands
[], int *len
)
2940 if (GET_CODE (operands
[2]) == CONST_INT
)
2942 int scratch
= (GET_CODE (PATTERN (insn
)) == PARALLEL
);
2943 int ldi_ok
= test_hard_reg_class (LD_REGS
, operands
[0]);
2950 switch (INTVAL (operands
[2]))
2953 if (optimize_size
&& scratch
)
2958 return (AS1 (swap
,%A0
) CR_TAB
2959 AS1 (swap
,%B0
) CR_TAB
2960 AS2 (andi
,%B0
,0xf0) CR_TAB
2961 AS2 (eor
,%B0
,%A0
) CR_TAB
2962 AS2 (andi
,%A0
,0xf0) CR_TAB
2968 return (AS1 (swap
,%A0
) CR_TAB
2969 AS1 (swap
,%B0
) CR_TAB
2970 AS2 (ldi
,%3,0xf0) CR_TAB
2971 AS2 (and,%B0
,%3) CR_TAB
2972 AS2 (eor
,%B0
,%A0
) CR_TAB
2973 AS2 (and,%A0
,%3) CR_TAB
2976 break; /* optimize_size ? 6 : 8 */
2980 break; /* scratch ? 5 : 6 */
2984 return (AS1 (lsl
,%A0
) CR_TAB
2985 AS1 (rol
,%B0
) CR_TAB
2986 AS1 (swap
,%A0
) CR_TAB
2987 AS1 (swap
,%B0
) CR_TAB
2988 AS2 (andi
,%B0
,0xf0) CR_TAB
2989 AS2 (eor
,%B0
,%A0
) CR_TAB
2990 AS2 (andi
,%A0
,0xf0) CR_TAB
2996 return (AS1 (lsl
,%A0
) CR_TAB
2997 AS1 (rol
,%B0
) CR_TAB
2998 AS1 (swap
,%A0
) CR_TAB
2999 AS1 (swap
,%B0
) CR_TAB
3000 AS2 (ldi
,%3,0xf0) CR_TAB
3001 AS2 (and,%B0
,%3) CR_TAB
3002 AS2 (eor
,%B0
,%A0
) CR_TAB
3003 AS2 (and,%A0
,%3) CR_TAB
3010 break; /* scratch ? 5 : 6 */
3012 return (AS1 (clr
,__tmp_reg__
) CR_TAB
3013 AS1 (lsr
,%B0
) CR_TAB
3014 AS1 (ror
,%A0
) CR_TAB
3015 AS1 (ror
,__tmp_reg__
) CR_TAB
3016 AS1 (lsr
,%B0
) CR_TAB
3017 AS1 (ror
,%A0
) CR_TAB
3018 AS1 (ror
,__tmp_reg__
) CR_TAB
3019 AS2 (mov
,%B0
,%A0
) CR_TAB
3020 AS2 (mov
,%A0
,__tmp_reg__
));
3024 return (AS1 (lsr
,%B0
) CR_TAB
3025 AS2 (mov
,%B0
,%A0
) CR_TAB
3026 AS1 (clr
,%A0
) CR_TAB
3027 AS1 (ror
,%B0
) CR_TAB
3031 if (true_regnum (operands
[0]) + 1 == true_regnum (operands
[1]))
3032 return *len
= 1, AS1 (clr
,%A0
);
3034 return *len
= 2, (AS2 (mov
,%B0
,%A1
) CR_TAB
3039 return (AS2 (mov
,%B0
,%A0
) CR_TAB
3040 AS1 (clr
,%A0
) CR_TAB
3045 return (AS2 (mov
,%B0
,%A0
) CR_TAB
3046 AS1 (clr
,%A0
) CR_TAB
3047 AS1 (lsl
,%B0
) CR_TAB
3052 return (AS2 (mov
,%B0
,%A0
) CR_TAB
3053 AS1 (clr
,%A0
) CR_TAB
3054 AS1 (lsl
,%B0
) CR_TAB
3055 AS1 (lsl
,%B0
) CR_TAB
3062 return (AS2 (mov
,%B0
,%A0
) CR_TAB
3063 AS1 (clr
,%A0
) CR_TAB
3064 AS1 (swap
,%B0
) CR_TAB
3065 AS2 (andi
,%B0
,0xf0));
3070 return (AS2 (mov
,%B0
,%A0
) CR_TAB
3071 AS1 (clr
,%A0
) CR_TAB
3072 AS1 (swap
,%B0
) CR_TAB
3073 AS2 (ldi
,%3,0xf0) CR_TAB
3077 return (AS2 (mov
,%B0
,%A0
) CR_TAB
3078 AS1 (clr
,%A0
) CR_TAB
3079 AS1 (lsl
,%B0
) CR_TAB
3080 AS1 (lsl
,%B0
) CR_TAB
3081 AS1 (lsl
,%B0
) CR_TAB
3088 return (AS2 (mov
,%B0
,%A0
) CR_TAB
3089 AS1 (clr
,%A0
) CR_TAB
3090 AS1 (swap
,%B0
) CR_TAB
3091 AS1 (lsl
,%B0
) CR_TAB
3092 AS2 (andi
,%B0
,0xe0));
3094 if (AVR_ENHANCED
&& scratch
)
3097 return (AS2 (ldi
,%3,0x20) CR_TAB
3098 AS2 (mul
,%A0
,%3) CR_TAB
3099 AS2 (mov
,%B0
,r0
) CR_TAB
3100 AS1 (clr
,%A0
) CR_TAB
3101 AS1 (clr
,__zero_reg__
));
3103 if (optimize_size
&& scratch
)
3108 return (AS2 (mov
,%B0
,%A0
) CR_TAB
3109 AS1 (clr
,%A0
) CR_TAB
3110 AS1 (swap
,%B0
) CR_TAB
3111 AS1 (lsl
,%B0
) CR_TAB
3112 AS2 (ldi
,%3,0xe0) CR_TAB
3118 return ("set" CR_TAB
3119 AS2 (bld
,r1
,5) CR_TAB
3120 AS2 (mul
,%A0
,r1
) CR_TAB
3121 AS2 (mov
,%B0
,r0
) CR_TAB
3122 AS1 (clr
,%A0
) CR_TAB
3123 AS1 (clr
,__zero_reg__
));
3126 return (AS2 (mov
,%B0
,%A0
) CR_TAB
3127 AS1 (clr
,%A0
) CR_TAB
3128 AS1 (lsl
,%B0
) CR_TAB
3129 AS1 (lsl
,%B0
) CR_TAB
3130 AS1 (lsl
,%B0
) CR_TAB
3131 AS1 (lsl
,%B0
) CR_TAB
3135 if (AVR_ENHANCED
&& ldi_ok
)
3138 return (AS2 (ldi
,%B0
,0x40) CR_TAB
3139 AS2 (mul
,%A0
,%B0
) CR_TAB
3140 AS2 (mov
,%B0
,r0
) CR_TAB
3141 AS1 (clr
,%A0
) CR_TAB
3142 AS1 (clr
,__zero_reg__
));
3144 if (AVR_ENHANCED
&& scratch
)
3147 return (AS2 (ldi
,%3,0x40) CR_TAB
3148 AS2 (mul
,%A0
,%3) CR_TAB
3149 AS2 (mov
,%B0
,r0
) CR_TAB
3150 AS1 (clr
,%A0
) CR_TAB
3151 AS1 (clr
,__zero_reg__
));
3153 if (optimize_size
&& ldi_ok
)
3156 return (AS2 (mov
,%B0
,%A0
) CR_TAB
3157 AS2 (ldi
,%A0
,6) "\n1:\t"
3158 AS1 (lsl
,%B0
) CR_TAB
3159 AS1 (dec
,%A0
) CR_TAB
3162 if (optimize_size
&& scratch
)
3165 return (AS1 (clr
,%B0
) CR_TAB
3166 AS1 (lsr
,%A0
) CR_TAB
3167 AS1 (ror
,%B0
) CR_TAB
3168 AS1 (lsr
,%A0
) CR_TAB
3169 AS1 (ror
,%B0
) CR_TAB
3174 return (AS1 (clr
,%B0
) CR_TAB
3175 AS1 (lsr
,%A0
) CR_TAB
3176 AS1 (ror
,%B0
) CR_TAB
3181 out_shift_with_cnt ((AS1 (lsl
,%A0
) CR_TAB
3183 insn
, operands
, len
, 2);
3188 /* 32bit shift left ((long)x << i) */
3191 ashlsi3_out (rtx insn
, rtx operands
[], int *len
)
3193 if (GET_CODE (operands
[2]) == CONST_INT
)
3201 switch (INTVAL (operands
[2]))
3205 int reg0
= true_regnum (operands
[0]);
3206 int reg1
= true_regnum (operands
[1]);
3209 return (AS2 (mov
,%D0
,%C1
) CR_TAB
3210 AS2 (mov
,%C0
,%B1
) CR_TAB
3211 AS2 (mov
,%B0
,%A1
) CR_TAB
3213 else if (reg0
+ 1 == reg1
)
3216 return AS1 (clr
,%A0
);
3219 return (AS1 (clr
,%A0
) CR_TAB
3220 AS2 (mov
,%B0
,%A1
) CR_TAB
3221 AS2 (mov
,%C0
,%B1
) CR_TAB
3227 int reg0
= true_regnum (operands
[0]);
3228 int reg1
= true_regnum (operands
[1]);
3230 if (AVR_ENHANCED
&& (reg0
+ 2 != reg1
))
3233 return (AS2 (movw
,%C0
,%A1
) CR_TAB
3234 AS1 (clr
,%B0
) CR_TAB
3237 if (reg0
+ 1 >= reg1
)
3238 return (AS2 (mov
,%D0
,%B1
) CR_TAB
3239 AS2 (mov
,%C0
,%A1
) CR_TAB
3240 AS1 (clr
,%B0
) CR_TAB
3242 if (reg0
+ 2 == reg1
)
3245 return (AS1 (clr
,%B0
) CR_TAB
3249 return (AS2 (mov
,%C0
,%A1
) CR_TAB
3250 AS2 (mov
,%D0
,%B1
) CR_TAB
3251 AS1 (clr
,%B0
) CR_TAB
3257 if (true_regnum (operands
[0]) + 3 != true_regnum (operands
[1]))
3258 return (AS2 (mov
,%D0
,%A1
) CR_TAB
3259 AS1 (clr
,%C0
) CR_TAB
3260 AS1 (clr
,%B0
) CR_TAB
3265 return (AS1 (clr
,%C0
) CR_TAB
3266 AS1 (clr
,%B0
) CR_TAB
3272 return (AS1 (clr
,%D0
) CR_TAB
3273 AS1 (lsr
,%A0
) CR_TAB
3274 AS1 (ror
,%D0
) CR_TAB
3275 AS1 (clr
,%C0
) CR_TAB
3276 AS1 (clr
,%B0
) CR_TAB
3281 out_shift_with_cnt ((AS1 (lsl
,%A0
) CR_TAB
3282 AS1 (rol
,%B0
) CR_TAB
3283 AS1 (rol
,%C0
) CR_TAB
3285 insn
, operands
, len
, 4);
3289 /* 8bit arithmetic shift right ((signed char)x >> i) */
3292 ashrqi3_out (rtx insn
, rtx operands
[], int *len
)
3294 if (GET_CODE (operands
[2]) == CONST_INT
)
3301 switch (INTVAL (operands
[2]))
3305 return AS1 (asr
,%0);
3309 return (AS1 (asr
,%0) CR_TAB
3314 return (AS1 (asr
,%0) CR_TAB
3320 return (AS1 (asr
,%0) CR_TAB
3327 return (AS1 (asr
,%0) CR_TAB
3335 return (AS2 (bst
,%0,6) CR_TAB
3337 AS2 (sbc
,%0,%0) CR_TAB
3343 return (AS1 (lsl
,%0) CR_TAB
3347 else if (CONSTANT_P (operands
[2]))
3348 fatal_insn ("internal compiler error. Incorrect shift:", insn
);
3350 out_shift_with_cnt (AS1 (asr
,%0),
3351 insn
, operands
, len
, 1);
3356 /* 16bit arithmetic shift right ((signed short)x >> i) */
3359 ashrhi3_out (rtx insn
, rtx operands
[], int *len
)
3361 if (GET_CODE (operands
[2]) == CONST_INT
)
3363 int scratch
= (GET_CODE (PATTERN (insn
)) == PARALLEL
);
3364 int ldi_ok
= test_hard_reg_class (LD_REGS
, operands
[0]);
3371 switch (INTVAL (operands
[2]))
3375 /* XXX try to optimize this too? */
3380 break; /* scratch ? 5 : 6 */
3382 return (AS2 (mov
,__tmp_reg__
,%A0
) CR_TAB
3383 AS2 (mov
,%A0
,%B0
) CR_TAB
3384 AS1 (lsl
,__tmp_reg__
) CR_TAB
3385 AS1 (rol
,%A0
) CR_TAB
3386 AS2 (sbc
,%B0
,%B0
) CR_TAB
3387 AS1 (lsl
,__tmp_reg__
) CR_TAB
3388 AS1 (rol
,%A0
) CR_TAB
3393 return (AS1 (lsl
,%A0
) CR_TAB
3394 AS2 (mov
,%A0
,%B0
) CR_TAB
3395 AS1 (rol
,%A0
) CR_TAB
3400 int reg0
= true_regnum (operands
[0]);
3401 int reg1
= true_regnum (operands
[1]);
3404 return *len
= 3, (AS2 (mov
,%A0
,%B0
) CR_TAB
3405 AS1 (lsl
,%B0
) CR_TAB
3407 else if (reg0
== reg1
+ 1)
3408 return *len
= 3, (AS1 (clr
,%B0
) CR_TAB
3409 AS2 (sbrc
,%A0
,7) CR_TAB
3412 return *len
= 4, (AS2 (mov
,%A0
,%B1
) CR_TAB
3413 AS1 (clr
,%B0
) CR_TAB
3414 AS2 (sbrc
,%A0
,7) CR_TAB
3420 return (AS2 (mov
,%A0
,%B0
) CR_TAB
3421 AS1 (lsl
,%B0
) CR_TAB
3422 AS2 (sbc
,%B0
,%B0
) CR_TAB
3427 return (AS2 (mov
,%A0
,%B0
) CR_TAB
3428 AS1 (lsl
,%B0
) CR_TAB
3429 AS2 (sbc
,%B0
,%B0
) CR_TAB
3430 AS1 (asr
,%A0
) CR_TAB
3434 if (AVR_ENHANCED
&& ldi_ok
)
3437 return (AS2 (ldi
,%A0
,0x20) CR_TAB
3438 AS2 (muls
,%B0
,%A0
) CR_TAB
3439 AS2 (mov
,%A0
,r1
) CR_TAB
3440 AS2 (sbc
,%B0
,%B0
) CR_TAB
3441 AS1 (clr
,__zero_reg__
));
3443 if (optimize_size
&& scratch
)
3446 return (AS2 (mov
,%A0
,%B0
) CR_TAB
3447 AS1 (lsl
,%B0
) CR_TAB
3448 AS2 (sbc
,%B0
,%B0
) CR_TAB
3449 AS1 (asr
,%A0
) CR_TAB
3450 AS1 (asr
,%A0
) CR_TAB
3454 if (AVR_ENHANCED
&& ldi_ok
)
3457 return (AS2 (ldi
,%A0
,0x10) CR_TAB
3458 AS2 (muls
,%B0
,%A0
) CR_TAB
3459 AS2 (mov
,%A0
,r1
) CR_TAB
3460 AS2 (sbc
,%B0
,%B0
) CR_TAB
3461 AS1 (clr
,__zero_reg__
));
3463 if (optimize_size
&& scratch
)
3466 return (AS2 (mov
,%A0
,%B0
) CR_TAB
3467 AS1 (lsl
,%B0
) CR_TAB
3468 AS2 (sbc
,%B0
,%B0
) CR_TAB
3469 AS1 (asr
,%A0
) CR_TAB
3470 AS1 (asr
,%A0
) CR_TAB
3471 AS1 (asr
,%A0
) CR_TAB
3475 if (AVR_ENHANCED
&& ldi_ok
)
3478 return (AS2 (ldi
,%A0
,0x08) CR_TAB
3479 AS2 (muls
,%B0
,%A0
) CR_TAB
3480 AS2 (mov
,%A0
,r1
) CR_TAB
3481 AS2 (sbc
,%B0
,%B0
) CR_TAB
3482 AS1 (clr
,__zero_reg__
));
3485 break; /* scratch ? 5 : 7 */
3487 return (AS2 (mov
,%A0
,%B0
) CR_TAB
3488 AS1 (lsl
,%B0
) CR_TAB
3489 AS2 (sbc
,%B0
,%B0
) CR_TAB
3490 AS1 (asr
,%A0
) CR_TAB
3491 AS1 (asr
,%A0
) CR_TAB
3492 AS1 (asr
,%A0
) CR_TAB
3493 AS1 (asr
,%A0
) CR_TAB
3498 return (AS1 (lsl
,%B0
) CR_TAB
3499 AS2 (sbc
,%A0
,%A0
) CR_TAB
3500 AS1 (lsl
,%B0
) CR_TAB
3501 AS2 (mov
,%B0
,%A0
) CR_TAB
3505 return *len
= 3, (AS1 (lsl
,%B0
) CR_TAB
3506 AS2 (sbc
,%A0
,%A0
) CR_TAB
3511 out_shift_with_cnt ((AS1 (asr
,%B0
) CR_TAB
3513 insn
, operands
, len
, 2);
3518 /* 32bit arithmetic shift right ((signed long)x >> i) */
3521 ashrsi3_out (rtx insn
, rtx operands
[], int *len
)
3523 if (GET_CODE (operands
[2]) == CONST_INT
)
3531 switch (INTVAL (operands
[2]))
3535 int reg0
= true_regnum (operands
[0]);
3536 int reg1
= true_regnum (operands
[1]);
3539 return (AS2 (mov
,%A0
,%B1
) CR_TAB
3540 AS2 (mov
,%B0
,%C1
) CR_TAB
3541 AS2 (mov
,%C0
,%D1
) CR_TAB
3542 AS1 (clr
,%D0
) CR_TAB
3543 AS2 (sbrc
,%C0
,7) CR_TAB
3545 else if (reg0
== reg1
+ 1)
3548 return (AS1 (clr
,%D0
) CR_TAB
3549 AS2 (sbrc
,%C0
,7) CR_TAB
3553 return (AS1 (clr
,%D0
) CR_TAB
3554 AS2 (sbrc
,%D1
,7) CR_TAB
3555 AS1 (dec
,%D0
) CR_TAB
3556 AS2 (mov
,%C0
,%D1
) CR_TAB
3557 AS2 (mov
,%B0
,%C1
) CR_TAB
3563 int reg0
= true_regnum (operands
[0]);
3564 int reg1
= true_regnum (operands
[1]);
3566 if (AVR_ENHANCED
&& (reg0
!= reg1
+ 2))
3569 return (AS2 (movw
,%A0
,%C1
) CR_TAB
3570 AS1 (clr
,%D0
) CR_TAB
3571 AS2 (sbrc
,%B0
,7) CR_TAB
3572 AS1 (com
,%D0
) CR_TAB
3575 if (reg0
<= reg1
+ 1)
3576 return (AS2 (mov
,%A0
,%C1
) CR_TAB
3577 AS2 (mov
,%B0
,%D1
) CR_TAB
3578 AS1 (clr
,%D0
) CR_TAB
3579 AS2 (sbrc
,%B0
,7) CR_TAB
3580 AS1 (com
,%D0
) CR_TAB
3582 else if (reg0
== reg1
+ 2)
3583 return *len
= 4, (AS1 (clr
,%D0
) CR_TAB
3584 AS2 (sbrc
,%B0
,7) CR_TAB
3585 AS1 (com
,%D0
) CR_TAB
3588 return (AS2 (mov
,%B0
,%D1
) CR_TAB
3589 AS2 (mov
,%A0
,%C1
) CR_TAB
3590 AS1 (clr
,%D0
) CR_TAB
3591 AS2 (sbrc
,%B0
,7) CR_TAB
3592 AS1 (com
,%D0
) CR_TAB
3597 if (true_regnum (operands
[0]) != true_regnum (operands
[1]) + 3)
3598 return *len
= 6, (AS2 (mov
,%A0
,%D1
) CR_TAB
3599 AS1 (clr
,%D0
) CR_TAB
3600 AS2 (sbrc
,%A0
,7) CR_TAB
3601 AS1 (com
,%D0
) CR_TAB
3602 AS2 (mov
,%B0
,%D0
) CR_TAB
3605 return *len
= 5, (AS1 (clr
,%D0
) CR_TAB
3606 AS2 (sbrc
,%A0
,7) CR_TAB
3607 AS1 (com
,%D0
) CR_TAB
3608 AS2 (mov
,%B0
,%D0
) CR_TAB
3613 return *len
= 4, (AS1 (lsl
,%D0
) CR_TAB
3614 AS2 (sbc
,%A0
,%A0
) CR_TAB
3615 AS2 (mov
,%B0
,%A0
) CR_TAB
3616 AS2 (movw
,%C0
,%A0
));
3618 return *len
= 5, (AS1 (lsl
,%D0
) CR_TAB
3619 AS2 (sbc
,%A0
,%A0
) CR_TAB
3620 AS2 (mov
,%B0
,%A0
) CR_TAB
3621 AS2 (mov
,%C0
,%A0
) CR_TAB
3626 out_shift_with_cnt ((AS1 (asr
,%D0
) CR_TAB
3627 AS1 (ror
,%C0
) CR_TAB
3628 AS1 (ror
,%B0
) CR_TAB
3630 insn
, operands
, len
, 4);
3634 /* 8bit logic shift right ((unsigned char)x >> i) */
3637 lshrqi3_out (rtx insn
, rtx operands
[], int *len
)
3639 if (GET_CODE (operands
[2]) == CONST_INT
)
3646 switch (INTVAL (operands
[2]))
3650 return AS1 (clr
,%0);
3654 return AS1 (lsr
,%0);
3658 return (AS1 (lsr
,%0) CR_TAB
3662 return (AS1 (lsr
,%0) CR_TAB
3667 if (test_hard_reg_class (LD_REGS
, operands
[0]))
3670 return (AS1 (swap
,%0) CR_TAB
3671 AS2 (andi
,%0,0x0f));
3674 return (AS1 (lsr
,%0) CR_TAB
3680 if (test_hard_reg_class (LD_REGS
, operands
[0]))
3683 return (AS1 (swap
,%0) CR_TAB
3688 return (AS1 (lsr
,%0) CR_TAB
3695 if (test_hard_reg_class (LD_REGS
, operands
[0]))
3698 return (AS1 (swap
,%0) CR_TAB
3704 return (AS1 (lsr
,%0) CR_TAB
3713 return (AS1 (rol
,%0) CR_TAB
3718 else if (CONSTANT_P (operands
[2]))
3719 fatal_insn ("internal compiler error. Incorrect shift:", insn
);
3721 out_shift_with_cnt (AS1 (lsr
,%0),
3722 insn
, operands
, len
, 1);
3726 /* 16bit logic shift right ((unsigned short)x >> i) */
3729 lshrhi3_out (rtx insn
, rtx operands
[], int *len
)
3731 if (GET_CODE (operands
[2]) == CONST_INT
)
3733 int scratch
= (GET_CODE (PATTERN (insn
)) == PARALLEL
);
3734 int ldi_ok
= test_hard_reg_class (LD_REGS
, operands
[0]);
3741 switch (INTVAL (operands
[2]))
3744 if (optimize_size
&& scratch
)
3749 return (AS1 (swap
,%B0
) CR_TAB
3750 AS1 (swap
,%A0
) CR_TAB
3751 AS2 (andi
,%A0
,0x0f) CR_TAB
3752 AS2 (eor
,%A0
,%B0
) CR_TAB
3753 AS2 (andi
,%B0
,0x0f) CR_TAB
3759 return (AS1 (swap
,%B0
) CR_TAB
3760 AS1 (swap
,%A0
) CR_TAB
3761 AS2 (ldi
,%3,0x0f) CR_TAB
3762 AS2 (and,%A0
,%3) CR_TAB
3763 AS2 (eor
,%A0
,%B0
) CR_TAB
3764 AS2 (and,%B0
,%3) CR_TAB
3767 break; /* optimize_size ? 6 : 8 */
3771 break; /* scratch ? 5 : 6 */
3775 return (AS1 (lsr
,%B0
) CR_TAB
3776 AS1 (ror
,%A0
) CR_TAB
3777 AS1 (swap
,%B0
) CR_TAB
3778 AS1 (swap
,%A0
) CR_TAB
3779 AS2 (andi
,%A0
,0x0f) CR_TAB
3780 AS2 (eor
,%A0
,%B0
) CR_TAB
3781 AS2 (andi
,%B0
,0x0f) CR_TAB
3787 return (AS1 (lsr
,%B0
) CR_TAB
3788 AS1 (ror
,%A0
) CR_TAB
3789 AS1 (swap
,%B0
) CR_TAB
3790 AS1 (swap
,%A0
) CR_TAB
3791 AS2 (ldi
,%3,0x0f) CR_TAB
3792 AS2 (and,%A0
,%3) CR_TAB
3793 AS2 (eor
,%A0
,%B0
) CR_TAB
3794 AS2 (and,%B0
,%3) CR_TAB
3801 break; /* scratch ? 5 : 6 */
3803 return (AS1 (clr
,__tmp_reg__
) CR_TAB
3804 AS1 (lsl
,%A0
) CR_TAB
3805 AS1 (rol
,%B0
) CR_TAB
3806 AS1 (rol
,__tmp_reg__
) CR_TAB
3807 AS1 (lsl
,%A0
) CR_TAB
3808 AS1 (rol
,%B0
) CR_TAB
3809 AS1 (rol
,__tmp_reg__
) CR_TAB
3810 AS2 (mov
,%A0
,%B0
) CR_TAB
3811 AS2 (mov
,%B0
,__tmp_reg__
));
3815 return (AS1 (lsl
,%A0
) CR_TAB
3816 AS2 (mov
,%A0
,%B0
) CR_TAB
3817 AS1 (rol
,%A0
) CR_TAB
3818 AS2 (sbc
,%B0
,%B0
) CR_TAB
3822 if (true_regnum (operands
[0]) != true_regnum (operands
[1]) + 1)
3823 return *len
= 2, (AS2 (mov
,%A0
,%B1
) CR_TAB
3826 return *len
= 1, AS1 (clr
,%B0
);
3830 return (AS2 (mov
,%A0
,%B0
) CR_TAB
3831 AS1 (clr
,%B0
) CR_TAB
3836 return (AS2 (mov
,%A0
,%B0
) CR_TAB
3837 AS1 (clr
,%B0
) CR_TAB
3838 AS1 (lsr
,%A0
) CR_TAB
3843 return (AS2 (mov
,%A0
,%B0
) CR_TAB
3844 AS1 (clr
,%B0
) CR_TAB
3845 AS1 (lsr
,%A0
) CR_TAB
3846 AS1 (lsr
,%A0
) CR_TAB
3853 return (AS2 (mov
,%A0
,%B0
) CR_TAB
3854 AS1 (clr
,%B0
) CR_TAB
3855 AS1 (swap
,%A0
) CR_TAB
3856 AS2 (andi
,%A0
,0x0f));
3861 return (AS2 (mov
,%A0
,%B0
) CR_TAB
3862 AS1 (clr
,%B0
) CR_TAB
3863 AS1 (swap
,%A0
) CR_TAB
3864 AS2 (ldi
,%3,0x0f) CR_TAB
3868 return (AS2 (mov
,%A0
,%B0
) CR_TAB
3869 AS1 (clr
,%B0
) CR_TAB
3870 AS1 (lsr
,%A0
) CR_TAB
3871 AS1 (lsr
,%A0
) CR_TAB
3872 AS1 (lsr
,%A0
) CR_TAB
3879 return (AS2 (mov
,%A0
,%B0
) CR_TAB
3880 AS1 (clr
,%B0
) CR_TAB
3881 AS1 (swap
,%A0
) CR_TAB
3882 AS1 (lsr
,%A0
) CR_TAB
3883 AS2 (andi
,%A0
,0x07));
3885 if (AVR_ENHANCED
&& scratch
)
3888 return (AS2 (ldi
,%3,0x08) CR_TAB
3889 AS2 (mul
,%B0
,%3) CR_TAB
3890 AS2 (mov
,%A0
,r1
) CR_TAB
3891 AS1 (clr
,%B0
) CR_TAB
3892 AS1 (clr
,__zero_reg__
));
3894 if (optimize_size
&& scratch
)
3899 return (AS2 (mov
,%A0
,%B0
) CR_TAB
3900 AS1 (clr
,%B0
) CR_TAB
3901 AS1 (swap
,%A0
) CR_TAB
3902 AS1 (lsr
,%A0
) CR_TAB
3903 AS2 (ldi
,%3,0x07) CR_TAB
3909 return ("set" CR_TAB
3910 AS2 (bld
,r1
,3) CR_TAB
3911 AS2 (mul
,%B0
,r1
) CR_TAB
3912 AS2 (mov
,%A0
,r1
) CR_TAB
3913 AS1 (clr
,%B0
) CR_TAB
3914 AS1 (clr
,__zero_reg__
));
3917 return (AS2 (mov
,%A0
,%B0
) CR_TAB
3918 AS1 (clr
,%B0
) CR_TAB
3919 AS1 (lsr
,%A0
) CR_TAB
3920 AS1 (lsr
,%A0
) CR_TAB
3921 AS1 (lsr
,%A0
) CR_TAB
3922 AS1 (lsr
,%A0
) CR_TAB
3926 if (AVR_ENHANCED
&& ldi_ok
)
3929 return (AS2 (ldi
,%A0
,0x04) CR_TAB
3930 AS2 (mul
,%B0
,%A0
) CR_TAB
3931 AS2 (mov
,%A0
,r1
) CR_TAB
3932 AS1 (clr
,%B0
) CR_TAB
3933 AS1 (clr
,__zero_reg__
));
3935 if (AVR_ENHANCED
&& scratch
)
3938 return (AS2 (ldi
,%3,0x04) CR_TAB
3939 AS2 (mul
,%B0
,%3) CR_TAB
3940 AS2 (mov
,%A0
,r1
) CR_TAB
3941 AS1 (clr
,%B0
) CR_TAB
3942 AS1 (clr
,__zero_reg__
));
3944 if (optimize_size
&& ldi_ok
)
3947 return (AS2 (mov
,%A0
,%B0
) CR_TAB
3948 AS2 (ldi
,%B0
,6) "\n1:\t"
3949 AS1 (lsr
,%A0
) CR_TAB
3950 AS1 (dec
,%B0
) CR_TAB
3953 if (optimize_size
&& scratch
)
3956 return (AS1 (clr
,%A0
) CR_TAB
3957 AS1 (lsl
,%B0
) CR_TAB
3958 AS1 (rol
,%A0
) CR_TAB
3959 AS1 (lsl
,%B0
) CR_TAB
3960 AS1 (rol
,%A0
) CR_TAB
3965 return (AS1 (clr
,%A0
) CR_TAB
3966 AS1 (lsl
,%B0
) CR_TAB
3967 AS1 (rol
,%A0
) CR_TAB
3972 out_shift_with_cnt ((AS1 (lsr
,%B0
) CR_TAB
3974 insn
, operands
, len
, 2);
3978 /* 32bit logic shift right ((unsigned int)x >> i) */
3981 lshrsi3_out (rtx insn
, rtx operands
[], int *len
)
3983 if (GET_CODE (operands
[2]) == CONST_INT
)
3991 switch (INTVAL (operands
[2]))
3995 int reg0
= true_regnum (operands
[0]);
3996 int reg1
= true_regnum (operands
[1]);
3999 return (AS2 (mov
,%A0
,%B1
) CR_TAB
4000 AS2 (mov
,%B0
,%C1
) CR_TAB
4001 AS2 (mov
,%C0
,%D1
) CR_TAB
4003 else if (reg0
== reg1
+ 1)
4004 return *len
= 1, AS1 (clr
,%D0
);
4006 return (AS1 (clr
,%D0
) CR_TAB
4007 AS2 (mov
,%C0
,%D1
) CR_TAB
4008 AS2 (mov
,%B0
,%C1
) CR_TAB
4014 int reg0
= true_regnum (operands
[0]);
4015 int reg1
= true_regnum (operands
[1]);
4017 if (AVR_ENHANCED
&& (reg0
!= reg1
+ 2))
4020 return (AS2 (movw
,%A0
,%C1
) CR_TAB
4021 AS1 (clr
,%C0
) CR_TAB
4024 if (reg0
<= reg1
+ 1)
4025 return (AS2 (mov
,%A0
,%C1
) CR_TAB
4026 AS2 (mov
,%B0
,%D1
) CR_TAB
4027 AS1 (clr
,%C0
) CR_TAB
4029 else if (reg0
== reg1
+ 2)
4030 return *len
= 2, (AS1 (clr
,%C0
) CR_TAB
4033 return (AS2 (mov
,%B0
,%D1
) CR_TAB
4034 AS2 (mov
,%A0
,%C1
) CR_TAB
4035 AS1 (clr
,%C0
) CR_TAB
4040 if (true_regnum (operands
[0]) != true_regnum (operands
[1]) + 3)
4041 return *len
= 4, (AS2 (mov
,%A0
,%D1
) CR_TAB
4042 AS1 (clr
,%B0
) CR_TAB
4043 AS1 (clr
,%C0
) CR_TAB
4046 return *len
= 3, (AS1 (clr
,%B0
) CR_TAB
4047 AS1 (clr
,%C0
) CR_TAB
4052 return (AS1 (clr
,%A0
) CR_TAB
4053 AS2 (sbrc
,%D0
,7) CR_TAB
4054 AS1 (inc
,%A0
) CR_TAB
4055 AS1 (clr
,%B0
) CR_TAB
4056 AS1 (clr
,%C0
) CR_TAB
4061 out_shift_with_cnt ((AS1 (lsr
,%D0
) CR_TAB
4062 AS1 (ror
,%C0
) CR_TAB
4063 AS1 (ror
,%B0
) CR_TAB
4065 insn
, operands
, len
, 4);
4069 /* Modifies the length assigned to instruction INSN
4070 LEN is the initially computed length of the insn. */
4073 adjust_insn_length (rtx insn
, int len
)
4075 rtx patt
= PATTERN (insn
);
4078 if (GET_CODE (patt
) == SET
)
4081 op
[1] = SET_SRC (patt
);
4082 op
[0] = SET_DEST (patt
);
4083 if (general_operand (op
[1], VOIDmode
)
4084 && general_operand (op
[0], VOIDmode
))
4086 switch (GET_MODE (op
[0]))
4089 output_movqi (insn
, op
, &len
);
4092 output_movhi (insn
, op
, &len
);
4096 output_movsisf (insn
, op
, &len
);
4102 else if (op
[0] == cc0_rtx
&& REG_P (op
[1]))
4104 switch (GET_MODE (op
[1]))
4106 case HImode
: out_tsthi (insn
,&len
); break;
4107 case SImode
: out_tstsi (insn
,&len
); break;
4111 else if (GET_CODE (op
[1]) == AND
)
4113 if (GET_CODE (XEXP (op
[1],1)) == CONST_INT
)
4115 HOST_WIDE_INT mask
= INTVAL (XEXP (op
[1],1));
4116 if (GET_MODE (op
[1]) == SImode
)
4117 len
= (((mask
& 0xff) != 0xff)
4118 + ((mask
& 0xff00) != 0xff00)
4119 + ((mask
& 0xff0000L
) != 0xff0000L
)
4120 + ((mask
& 0xff000000L
) != 0xff000000L
));
4121 else if (GET_MODE (op
[1]) == HImode
)
4122 len
= (((mask
& 0xff) != 0xff)
4123 + ((mask
& 0xff00) != 0xff00));
4126 else if (GET_CODE (op
[1]) == IOR
)
4128 if (GET_CODE (XEXP (op
[1],1)) == CONST_INT
)
4130 HOST_WIDE_INT mask
= INTVAL (XEXP (op
[1],1));
4131 if (GET_MODE (op
[1]) == SImode
)
4132 len
= (((mask
& 0xff) != 0)
4133 + ((mask
& 0xff00) != 0)
4134 + ((mask
& 0xff0000L
) != 0)
4135 + ((mask
& 0xff000000L
) != 0));
4136 else if (GET_MODE (op
[1]) == HImode
)
4137 len
= (((mask
& 0xff) != 0)
4138 + ((mask
& 0xff00) != 0));
4142 set
= single_set (insn
);
4147 op
[1] = SET_SRC (set
);
4148 op
[0] = SET_DEST (set
);
4150 if (GET_CODE (patt
) == PARALLEL
4151 && general_operand (op
[1], VOIDmode
)
4152 && general_operand (op
[0], VOIDmode
))
4154 if (XVECLEN (patt
, 0) == 2)
4155 op
[2] = XVECEXP (patt
, 0, 1);
4157 switch (GET_MODE (op
[0]))
4163 output_reload_inhi (insn
, op
, &len
);
4167 output_reload_insisf (insn
, op
, &len
);
4173 else if (GET_CODE (op
[1]) == ASHIFT
4174 || GET_CODE (op
[1]) == ASHIFTRT
4175 || GET_CODE (op
[1]) == LSHIFTRT
)
4179 ops
[1] = XEXP (op
[1],0);
4180 ops
[2] = XEXP (op
[1],1);
4181 switch (GET_CODE (op
[1]))
4184 switch (GET_MODE (op
[0]))
4186 case QImode
: ashlqi3_out (insn
,ops
,&len
); break;
4187 case HImode
: ashlhi3_out (insn
,ops
,&len
); break;
4188 case SImode
: ashlsi3_out (insn
,ops
,&len
); break;
4193 switch (GET_MODE (op
[0]))
4195 case QImode
: ashrqi3_out (insn
,ops
,&len
); break;
4196 case HImode
: ashrhi3_out (insn
,ops
,&len
); break;
4197 case SImode
: ashrsi3_out (insn
,ops
,&len
); break;
4202 switch (GET_MODE (op
[0]))
4204 case QImode
: lshrqi3_out (insn
,ops
,&len
); break;
4205 case HImode
: lshrhi3_out (insn
,ops
,&len
); break;
4206 case SImode
: lshrsi3_out (insn
,ops
,&len
); break;
4218 /* Return nonzero if register REG dead after INSN */
4221 reg_unused_after (rtx insn
, rtx reg
)
4223 return (dead_or_set_p (insn
, reg
)
4224 || (REG_P(reg
) && _reg_unused_after (insn
, reg
)));
4227 /* Return nonzero if REG is not used after INSN.
4228 We assume REG is a reload reg, and therefore does
4229 not live past labels. It may live past calls or jumps though. */
4232 _reg_unused_after (rtx insn
, rtx reg
)
4237 /* If the reg is set by this instruction, then it is safe for our
4238 case. Disregard the case where this is a store to memory, since
4239 we are checking a register used in the store address. */
4240 set
= single_set (insn
);
4241 if (set
&& GET_CODE (SET_DEST (set
)) != MEM
4242 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
4245 while ((insn
= NEXT_INSN (insn
)))
4247 code
= GET_CODE (insn
);
4250 /* If this is a label that existed before reload, then the register
4251 if dead here. However, if this is a label added by reorg, then
4252 the register may still be live here. We can't tell the difference,
4253 so we just ignore labels completely. */
4254 if (code
== CODE_LABEL
)
4259 if (code
== JUMP_INSN
)
4262 /* If this is a sequence, we must handle them all at once.
4263 We could have for instance a call that sets the target register,
4264 and an insn in a delay slot that uses the register. In this case,
4265 we must return 0. */
4266 else if (code
== INSN
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
)
4271 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
4273 rtx this_insn
= XVECEXP (PATTERN (insn
), 0, i
);
4274 rtx set
= single_set (this_insn
);
4276 if (GET_CODE (this_insn
) == CALL_INSN
)
4278 else if (GET_CODE (this_insn
) == JUMP_INSN
)
4280 if (INSN_ANNULLED_BRANCH_P (this_insn
))
4285 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
4287 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
4289 if (GET_CODE (SET_DEST (set
)) != MEM
)
4295 && reg_overlap_mentioned_p (reg
, PATTERN (this_insn
)))
4300 else if (code
== JUMP_INSN
)
4304 if (code
== CALL_INSN
)
4307 for (tem
= CALL_INSN_FUNCTION_USAGE (insn
); tem
; tem
= XEXP (tem
, 1))
4308 if (GET_CODE (XEXP (tem
, 0)) == USE
4309 && REG_P (XEXP (XEXP (tem
, 0), 0))
4310 && reg_overlap_mentioned_p (reg
, XEXP (XEXP (tem
, 0), 0)))
4312 if (call_used_regs
[REGNO (reg
)])
4316 if (GET_RTX_CLASS (code
) == 'i')
4318 rtx set
= single_set (insn
);
4320 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
4322 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
4323 return GET_CODE (SET_DEST (set
)) != MEM
;
4324 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
4331 /* Target hook for assembling integer objects. The AVR version needs
4332 special handling for references to certain labels. */
4335 avr_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
4337 if (size
== POINTER_SIZE
/ BITS_PER_UNIT
&& aligned_p
4338 && ((GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (x
))
4339 || GET_CODE (x
) == LABEL_REF
))
4341 fputs ("\t.word\tpm(", asm_out_file
);
4342 output_addr_const (asm_out_file
, x
);
4343 fputs (")\n", asm_out_file
);
4346 return default_assemble_integer (x
, size
, aligned_p
);
4349 /* Sets section name for declaration DECL */
4352 avr_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
4355 const char *name
, *prefix
;
4358 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
4359 name
= (* targetm
.strip_name_encoding
) (name
);
4361 if (TREE_CODE (decl
) == FUNCTION_DECL
)
4363 if (flag_function_sections
)
4371 if (flag_function_sections
)
4373 len
= strlen (name
) + strlen (prefix
);
4374 string
= alloca (len
+ 1);
4375 sprintf (string
, "%s%s", prefix
, name
);
4376 DECL_SECTION_NAME (decl
) = build_string (len
, string
);
4381 /* The routine used to output NUL terminated strings. We use a special
4382 version of this for most svr4 targets because doing so makes the
4383 generated assembly code more compact (and thus faster to assemble)
4384 as well as more readable, especially for targets like the i386
4385 (where the only alternative is to output character sequences as
4386 comma separated lists of numbers). */
4389 gas_output_limited_string(FILE *file
, const char *str
)
4391 const unsigned char *_limited_str
= (unsigned char *) str
;
4393 fprintf (file
, "%s\"", STRING_ASM_OP
);
4394 for (; (ch
= *_limited_str
); _limited_str
++)
4397 switch (escape
= ESCAPES
[ch
])
4403 fprintf (file
, "\\%03o", ch
);
4407 putc (escape
, file
);
4411 fprintf (file
, "\"\n");
4414 /* The routine used to output sequences of byte values. We use a special
4415 version of this for most svr4 targets because doing so makes the
4416 generated assembly code more compact (and thus faster to assemble)
4417 as well as more readable. Note that if we find subparts of the
4418 character sequence which end with NUL (and which are shorter than
4419 STRING_LIMIT) we output those using ASM_OUTPUT_LIMITED_STRING. */
4422 gas_output_ascii(FILE *file
, const char *str
, size_t length
)
4424 const unsigned char *_ascii_bytes
= (const unsigned char *) str
;
4425 const unsigned char *limit
= _ascii_bytes
+ length
;
4426 unsigned bytes_in_chunk
= 0;
4427 for (; _ascii_bytes
< limit
; _ascii_bytes
++)
4429 const unsigned char *p
;
4430 if (bytes_in_chunk
>= 60)
4432 fprintf (file
, "\"\n");
4435 for (p
= _ascii_bytes
; p
< limit
&& *p
!= '\0'; p
++)
4437 if (p
< limit
&& (p
- _ascii_bytes
) <= (signed)STRING_LIMIT
)
4439 if (bytes_in_chunk
> 0)
4441 fprintf (file
, "\"\n");
4444 gas_output_limited_string (file
, (char*)_ascii_bytes
);
4451 if (bytes_in_chunk
== 0)
4452 fprintf (file
, "\t.ascii\t\"");
4453 switch (escape
= ESCAPES
[ch
= *_ascii_bytes
])
4460 fprintf (file
, "\\%03o", ch
);
4461 bytes_in_chunk
+= 4;
4465 putc (escape
, file
);
4466 bytes_in_chunk
+= 2;
4471 if (bytes_in_chunk
> 0)
4472 fprintf (file
, "\"\n");
4475 /* Return value is nonzero if pseudos that have been
4476 assigned to registers of class CLASS would likely be spilled
4477 because registers of CLASS are needed for spill registers. */
4480 class_likely_spilled_p (int c
)
4482 return (c
!= ALL_REGS
&& c
!= ADDW_REGS
);
4485 /* Valid attributes:
4486 progmem - put data to program memory;
4487 signal - make a function to be hardware interrupt. After function
4488 prologue interrupts are disabled;
4489 interrupt - make a function to be hardware interrupt. After function
4490 prologue interrupts are enabled;
4491 naked - don't generate function prologue/epilogue and `ret' command.
4493 Only `progmem' attribute valid for type. */
4495 const struct attribute_spec avr_attribute_table
[] =
4497 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4498 { "progmem", 0, 0, false, false, false, avr_handle_progmem_attribute
},
4499 { "signal", 0, 0, true, false, false, avr_handle_fndecl_attribute
},
4500 { "interrupt", 0, 0, true, false, false, avr_handle_fndecl_attribute
},
4501 { "naked", 0, 0, true, false, false, avr_handle_fndecl_attribute
},
4502 { NULL
, 0, 0, false, false, false, NULL
}
4505 /* Handle a "progmem" attribute; arguments as in
4506 struct attribute_spec.handler. */
4508 avr_handle_progmem_attribute (tree
*node
, tree name
,
4509 tree args ATTRIBUTE_UNUSED
,
4510 int flags ATTRIBUTE_UNUSED
,
4515 if (TREE_CODE (*node
) == TYPE_DECL
)
4517 /* This is really a decl attribute, not a type attribute,
4518 but try to handle it for GCC 3.0 backwards compatibility. */
4520 tree type
= TREE_TYPE (*node
);
4521 tree attr
= tree_cons (name
, args
, TYPE_ATTRIBUTES (type
));
4522 tree newtype
= build_type_attribute_variant (type
, attr
);
4524 TYPE_MAIN_VARIANT (newtype
) = TYPE_MAIN_VARIANT (type
);
4525 TREE_TYPE (*node
) = newtype
;
4526 *no_add_attrs
= true;
4528 else if (TREE_STATIC (*node
) || DECL_EXTERNAL (*node
))
4530 if (DECL_INITIAL (*node
) == NULL_TREE
&& !DECL_EXTERNAL (*node
))
4532 warning ("only initialized variables can be placed into "
4533 "program memory area");
4534 *no_add_attrs
= true;
4539 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
4540 *no_add_attrs
= true;
4547 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
4548 struct attribute_spec.handler. */
4551 avr_handle_fndecl_attribute (tree
*node
, tree name
,
4552 tree args ATTRIBUTE_UNUSED
,
4553 int flags ATTRIBUTE_UNUSED
,
4556 if (TREE_CODE (*node
) != FUNCTION_DECL
)
4558 warning ("`%s' attribute only applies to functions",
4559 IDENTIFIER_POINTER (name
));
4560 *no_add_attrs
= true;
4566 /* Look for attribute `progmem' in DECL
4567 if found return 1, otherwise 0. */
4570 avr_progmem_p (tree decl
)
4574 if (TREE_CODE (decl
) != VAR_DECL
)
4578 != lookup_attribute ("progmem", DECL_ATTRIBUTES (decl
)))
4584 while (TREE_CODE (a
) == ARRAY_TYPE
);
4586 if (a
== error_mark_node
)
4589 if (NULL_TREE
!= lookup_attribute ("progmem", TYPE_ATTRIBUTES (a
)))
4595 /* Add the section attribute if the variable is in progmem. */
4598 avr_insert_attributes (tree node
, tree
*attributes
)
4600 if (TREE_CODE (node
) == VAR_DECL
4601 && (TREE_STATIC (node
) || DECL_EXTERNAL (node
))
4602 && avr_progmem_p (node
))
4604 static const char dsec
[] = ".progmem.data";
4605 *attributes
= tree_cons (get_identifier ("section"),
4606 build_tree_list (NULL
, build_string (strlen (dsec
), dsec
)),
4609 /* ??? This seems sketchy. Why can't the user declare the
4610 thing const in the first place? */
4611 TREE_READONLY (node
) = 1;
4616 avr_section_type_flags (tree decl
, const char *name
, int reloc
)
4618 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
4620 if (strncmp (name
, ".noinit", 7) == 0)
4622 if (decl
&& TREE_CODE (decl
) == VAR_DECL
4623 && DECL_INITIAL (decl
) == NULL_TREE
)
4624 flags
|= SECTION_BSS
; /* @nobits */
4626 warning ("only uninitialized variables can be placed in the "
4633 /* Outputs some appropriate text to go at the start of an assembler
4637 avr_file_start (void)
4640 error ("MCU `%s' supported for assembler only", avr_mcu_name
);
4642 default_file_start ();
4644 fprintf (asm_out_file
, "\t.arch %s\n", avr_mcu_name
);
4645 fputs ("__SREG__ = 0x3f\n"
4647 "__SP_L__ = 0x3d\n", asm_out_file
);
4649 fputs ("__tmp_reg__ = 0\n"
4650 "__zero_reg__ = 1\n", asm_out_file
);
4652 /* FIXME: output these only if there is anything in the .data / .bss
4653 sections - some code size could be saved by not linking in the
4654 initialization code from libgcc if one or both sections are empty. */
4655 fputs ("\t.global __do_copy_data\n", asm_out_file
);
4656 fputs ("\t.global __do_clear_bss\n", asm_out_file
);
4658 commands_in_file
= 0;
4659 commands_in_prologues
= 0;
4660 commands_in_epilogues
= 0;
4663 /* Outputs to the stdio stream FILE some
4664 appropriate text to go at the end of an assembler file. */
4669 fputs ("/* File ", asm_out_file
);
4670 output_quoted_string (asm_out_file
, main_input_filename
);
4671 fprintf (asm_out_file
,
4672 ": code %4d = 0x%04x (%4d), prologues %3d, epilogues %3d */\n",
4675 commands_in_file
- commands_in_prologues
- commands_in_epilogues
,
4676 commands_in_prologues
, commands_in_epilogues
);
4679 /* Choose the order in which to allocate hard registers for
4680 pseudo-registers local to a basic block.
4682 Store the desired register order in the array `reg_alloc_order'.
4683 Element 0 should be the register to allocate first; element 1, the
4684 next register; and so on. */
4687 order_regs_for_local_alloc (void)
4690 static const int order_0
[] = {
4698 17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,
4702 static const int order_1
[] = {
4710 17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,
4714 static const int order_2
[] = {
4723 15,14,13,12,11,10,9,8,7,6,5,4,3,2,
4728 const int *order
= (TARGET_ORDER_1
? order_1
:
4729 TARGET_ORDER_2
? order_2
:
4731 for (i
=0; i
< ARRAY_SIZE (order_0
); ++i
)
4732 reg_alloc_order
[i
] = order
[i
];
4735 /* Calculate the cost of X code of the expression in which it is contained,
4736 found in OUTER_CODE */
4739 default_rtx_costs (rtx X
, enum rtx_code code
, enum rtx_code outer_code
)
4746 cost
= 2 * GET_MODE_SIZE (GET_MODE (X
));
4749 if (outer_code
!= SET
)
4751 if (GET_CODE (XEXP (X
,0)) == SYMBOL_REF
)
4752 cost
+= 2 * GET_MODE_SIZE (GET_MODE (X
));
4754 cost
+= GET_MODE_SIZE (GET_MODE (X
));
4760 if (outer_code
== SET
)
4761 cost
= GET_MODE_SIZE (GET_MODE (X
));
4763 cost
= -GET_MODE_SIZE (GET_MODE (X
));
4766 if (outer_code
== SET
)
4767 cost
= GET_MODE_SIZE (GET_MODE (X
));
4773 if (outer_code
== SET
)
4775 if (X
== stack_pointer_rtx
)
4777 else if (GET_CODE (XEXP (X
,1)) == CONST_INT
)
4778 cost
= (INTVAL (XEXP (X
,1)) <= 63 ? 1 :
4779 GET_MODE_SIZE (GET_MODE (X
)));
4781 cost
= GET_MODE_SIZE (GET_MODE (X
));
4785 if (GET_CODE (XEXP (X
,1)) == CONST_INT
)
4786 cost
= GET_MODE_SIZE (GET_MODE (XEXP (X
,0)));
4795 avr_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4802 if (outer_code
== PLUS
4803 || outer_code
== IOR
4804 || outer_code
== AND
4805 || outer_code
== MINUS
4806 || outer_code
== SET
4812 if (outer_code
== COMPARE
4814 && INTVAL (x
) <= 255)
4829 cst
= default_rtx_costs (x
, code
, outer_code
);
4841 /* Calculate the cost of a memory address */
4844 avr_address_cost (rtx x
)
4846 if (GET_CODE (x
) == PLUS
4847 && GET_CODE (XEXP (x
,1)) == CONST_INT
4848 && (REG_P (XEXP (x
,0)) || GET_CODE (XEXP (x
,0)) == SUBREG
)
4849 && INTVAL (XEXP (x
,1)) >= 61)
4851 if (CONSTANT_ADDRESS_P (x
))
4853 if (avr_io_address_p (x
, 1))
4860 /* EXTRA_CONSTRAINT helper */
4863 extra_constraint (rtx x
, int c
)
4866 && GET_CODE (x
) == MEM
4867 && GET_CODE (XEXP (x
,0)) == PLUS
)
4869 if (TARGET_ALL_DEBUG
)
4871 fprintf (stderr
, ("extra_constraint:\n"
4872 "reload_completed: %d\n"
4873 "reload_in_progress: %d\n"),
4874 reload_completed
, reload_in_progress
);
4877 if (GET_CODE (x
) == MEM
4878 && GET_CODE (XEXP (x
,0)) == PLUS
4879 && REG_P (XEXP (XEXP (x
,0), 0))
4880 && GET_CODE (XEXP (XEXP (x
,0), 1)) == CONST_INT
4881 && (INTVAL (XEXP (XEXP (x
,0), 1))
4882 <= MAX_LD_OFFSET (GET_MODE (x
))))
4884 rtx xx
= XEXP (XEXP (x
,0), 0);
4885 int regno
= REGNO (xx
);
4886 if (TARGET_ALL_DEBUG
)
4888 fprintf (stderr
, ("extra_constraint:\n"
4889 "reload_completed: %d\n"
4890 "reload_in_progress: %d\n"),
4891 reload_completed
, reload_in_progress
);
4894 if (regno
>= FIRST_PSEUDO_REGISTER
)
4895 return 1; /* allocate pseudos */
4896 else if (regno
== REG_Z
|| regno
== REG_Y
)
4897 return 1; /* strictly check */
4898 else if (xx
== frame_pointer_rtx
4899 || xx
== arg_pointer_rtx
)
4900 return 1; /* XXX frame & arg pointer checks */
4906 /* Convert condition code CONDITION to the valid AVR condition code */
4909 avr_normalize_condition (RTX_CODE condition
)
4926 /* This function optimizes conditional jumps. */
4933 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
4935 if (! (GET_CODE (insn
) == INSN
4936 || GET_CODE (insn
) == CALL_INSN
4937 || GET_CODE (insn
) == JUMP_INSN
)
4938 || !single_set (insn
))
4941 pattern
= PATTERN (insn
);
4943 if (GET_CODE (pattern
) == PARALLEL
)
4944 pattern
= XVECEXP (pattern
, 0, 0);
4945 if (GET_CODE (pattern
) == SET
4946 && SET_DEST (pattern
) == cc0_rtx
4947 && compare_diff_p (insn
))
4949 if (GET_CODE (SET_SRC (pattern
)) == COMPARE
)
4951 /* Now we work under compare insn */
4953 pattern
= SET_SRC (pattern
);
4954 if (true_regnum (XEXP (pattern
,0)) >= 0
4955 && true_regnum (XEXP (pattern
,1)) >= 0 )
4957 rtx x
= XEXP (pattern
,0);
4958 rtx next
= next_real_insn (insn
);
4959 rtx pat
= PATTERN (next
);
4960 rtx src
= SET_SRC (pat
);
4961 rtx t
= XEXP (src
,0);
4962 PUT_CODE (t
, swap_condition (GET_CODE (t
)));
4963 XEXP (pattern
,0) = XEXP (pattern
,1);
4964 XEXP (pattern
,1) = x
;
4965 INSN_CODE (next
) = -1;
4967 else if (true_regnum (XEXP (pattern
,0)) >= 0
4968 && GET_CODE (XEXP (pattern
,1)) == CONST_INT
)
4970 rtx x
= XEXP (pattern
,1);
4971 rtx next
= next_real_insn (insn
);
4972 rtx pat
= PATTERN (next
);
4973 rtx src
= SET_SRC (pat
);
4974 rtx t
= XEXP (src
,0);
4975 enum machine_mode mode
= GET_MODE (XEXP (pattern
, 0));
4977 if (avr_simplify_comparison_p (mode
, GET_CODE (t
), x
))
4979 XEXP (pattern
, 1) = gen_int_mode (INTVAL (x
) + 1, mode
);
4980 PUT_CODE (t
, avr_normalize_condition (GET_CODE (t
)));
4981 INSN_CODE (next
) = -1;
4982 INSN_CODE (insn
) = -1;
4986 else if (true_regnum (SET_SRC (pattern
)) >= 0)
4988 /* This is a tst insn */
4989 rtx next
= next_real_insn (insn
);
4990 rtx pat
= PATTERN (next
);
4991 rtx src
= SET_SRC (pat
);
4992 rtx t
= XEXP (src
,0);
4994 PUT_CODE (t
, swap_condition (GET_CODE (t
)));
4995 SET_SRC (pattern
) = gen_rtx (NEG
,
4996 GET_MODE (SET_SRC (pattern
)),
4998 INSN_CODE (next
) = -1;
4999 INSN_CODE (insn
) = -1;
5005 /* Returns register number for function return value.*/
5008 avr_ret_register (void)
5013 /* Ceate an RTX representing the place where a
5014 library function returns a value of mode MODE. */
5017 avr_libcall_value (enum machine_mode mode
)
5019 int offs
= GET_MODE_SIZE (mode
);
5022 return gen_rtx (REG
, mode
, RET_REGISTER
+ 2 - offs
);
5025 /* Create an RTX representing the place where a
5026 function returns a value of data type VALTYPE. */
5029 avr_function_value (tree type
, tree func ATTRIBUTE_UNUSED
)
5033 if (TYPE_MODE (type
) != BLKmode
)
5034 return avr_libcall_value (TYPE_MODE (type
));
5036 offs
= int_size_in_bytes (type
);
5039 if (offs
> 2 && offs
< GET_MODE_SIZE (SImode
))
5040 offs
= GET_MODE_SIZE (SImode
);
5041 else if (offs
> GET_MODE_SIZE (SImode
) && offs
< GET_MODE_SIZE (DImode
))
5042 offs
= GET_MODE_SIZE (DImode
);
5044 return gen_rtx (REG
, BLKmode
, RET_REGISTER
+ 2 - offs
);
5047 /* Returns nonzero if the number MASK has only one bit set. */
5050 mask_one_bit_p (HOST_WIDE_INT mask
)
5053 unsigned HOST_WIDE_INT n
=mask
;
5054 for (i
= 0; i
< 32; ++i
)
5056 if (n
& 0x80000000L
)
5058 if (n
& 0x7fffffffL
)
5069 /* Places additional restrictions on the register class to
5070 use when it is necessary to copy value X into a register
5074 preferred_reload_class (rtx x ATTRIBUTE_UNUSED
, enum reg_class
class)
5080 test_hard_reg_class (enum reg_class
class, rtx x
)
5082 int regno
= true_regnum (x
);
5086 if (TEST_HARD_REG_CLASS (class, regno
))
5094 jump_over_one_insn_p (rtx insn
, rtx dest
)
5096 int uid
= INSN_UID (GET_CODE (dest
) == LABEL_REF
5099 int jump_addr
= INSN_ADDRESSES (INSN_UID (insn
));
5100 int dest_addr
= INSN_ADDRESSES (uid
);
5101 return dest_addr
- jump_addr
== get_attr_length (insn
) + 1;
5104 /* Returns 1 if a value of mode MODE can be stored starting with hard
5105 register number REGNO. On the enhanced core, anything larger than
5106 1 byte must start in even numbered register for "movw" to work
5107 (this way we don't have to check for odd registers everywhere). */
5110 avr_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
5112 /* Bug workaround: recog.c (peep2_find_free_register) and probably
5113 a few other places assume that the frame pointer is a single hard
5114 register, so r29 may be allocated and overwrite the high byte of
5115 the frame pointer. Do not allow any value to start in r29. */
5116 if (regno
== REG_Y
+ 1)
5121 /* if (regno < 24 && !AVR_ENHANCED)
5123 return !(regno
& 1);
5126 /* Returns 1 if X is a valid address for an I/O register of size SIZE
5127 (1 or 2). Used for lds/sts -> in/out optimization. Add 0x20 to SIZE
5128 to check for the lower half of I/O space (for cbi/sbi/sbic/sbis). */
5131 avr_io_address_p (rtx x
, int size
)
5133 return (optimize
> 0 && GET_CODE (x
) == CONST_INT
5134 && INTVAL (x
) >= 0x20 && INTVAL (x
) <= 0x60 - size
);
5137 /* Returns nonzero (bit number + 1) if X, or -X, is a constant power of 2. */
5140 const_int_pow2_p (rtx x
)
5142 if (GET_CODE (x
) == CONST_INT
)
5144 HOST_WIDE_INT d
= INTVAL (x
);
5145 HOST_WIDE_INT abs_d
= (d
>= 0) ? d
: -d
;
5146 return exact_log2 (abs_d
) + 1;
5152 output_reload_inhi (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
, int *len
)
5158 if (GET_CODE (operands
[1]) == CONST_INT
)
5160 int val
= INTVAL (operands
[1]);
5161 if ((val
& 0xff) == 0)
5164 return (AS2 (mov
,%A0
,__zero_reg__
) CR_TAB
5165 AS2 (ldi
,%2,hi8(%1)) CR_TAB
5168 else if ((val
& 0xff00) == 0)
5171 return (AS2 (ldi
,%2,lo8(%1)) CR_TAB
5172 AS2 (mov
,%A0
,%2) CR_TAB
5173 AS2 (mov
,%B0
,__zero_reg__
));
5175 else if ((val
& 0xff) == ((val
& 0xff00) >> 8))
5178 return (AS2 (ldi
,%2,lo8(%1)) CR_TAB
5179 AS2 (mov
,%A0
,%2) CR_TAB
5184 return (AS2 (ldi
,%2,lo8(%1)) CR_TAB
5185 AS2 (mov
,%A0
,%2) CR_TAB
5186 AS2 (ldi
,%2,hi8(%1)) CR_TAB
5192 output_reload_insisf (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
, int *len
)
5194 rtx src
= operands
[1];
5195 int cnst
= (GET_CODE (src
) == CONST_INT
);
5200 *len
= 4 + ((INTVAL (src
) & 0xff) != 0)
5201 + ((INTVAL (src
) & 0xff00) != 0)
5202 + ((INTVAL (src
) & 0xff0000) != 0)
5203 + ((INTVAL (src
) & 0xff000000) != 0);
5210 if (cnst
&& ((INTVAL (src
) & 0xff) == 0))
5211 output_asm_insn (AS2 (mov
, %A0
, __zero_reg__
), operands
);
5214 output_asm_insn (AS2 (ldi
, %2, lo8(%1)), operands
);
5215 output_asm_insn (AS2 (mov
, %A0
, %2), operands
);
5217 if (cnst
&& ((INTVAL (src
) & 0xff00) == 0))
5218 output_asm_insn (AS2 (mov
, %B0
, __zero_reg__
), operands
);
5221 output_asm_insn (AS2 (ldi
, %2, hi8(%1)), operands
);
5222 output_asm_insn (AS2 (mov
, %B0
, %2), operands
);
5224 if (cnst
&& ((INTVAL (src
) & 0xff0000) == 0))
5225 output_asm_insn (AS2 (mov
, %C0
, __zero_reg__
), operands
);
5228 output_asm_insn (AS2 (ldi
, %2, hlo8(%1)), operands
);
5229 output_asm_insn (AS2 (mov
, %C0
, %2), operands
);
5231 if (cnst
&& ((INTVAL (src
) & 0xff000000) == 0))
5232 output_asm_insn (AS2 (mov
, %D0
, __zero_reg__
), operands
);
5235 output_asm_insn (AS2 (ldi
, %2, hhi8(%1)), operands
);
5236 output_asm_insn (AS2 (mov
, %D0
, %2), operands
);
5242 avr_output_bld (rtx operands
[], int bit_nr
)
5244 static char s
[] = "bld %A0,0";
5246 s
[5] = 'A' + (bit_nr
>> 3);
5247 s
[8] = '0' + (bit_nr
& 7);
5248 output_asm_insn (s
, operands
);
5252 avr_output_addr_vec_elt (FILE *stream
, int value
)
5255 fprintf (stream
, "\t.word pm(.L%d)\n", value
);
5257 fprintf (stream
, "\trjmp .L%d\n", value
);
5262 /* Returns 1 if SCRATCH are safe to be allocated as a scratch
5263 registers (for a define_peephole2) in the current function. */
5266 avr_peep2_scratch_safe (rtx scratch
)
5268 if ((interrupt_function_p (current_function_decl
)
5269 || signal_function_p (current_function_decl
))
5270 && leaf_function_p ())
5272 int first_reg
= true_regnum (scratch
);
5273 int last_reg
= first_reg
+ GET_MODE_SIZE (GET_MODE (scratch
)) - 1;
5276 for (reg
= first_reg
; reg
<= last_reg
; reg
++)
5278 if (!regs_ever_live
[reg
])
5285 /* Output a branch that tests a single bit of a register (QI, HI or SImode)
5286 or memory location in the I/O space (QImode only).
5288 Operand 0: comparison operator (must be EQ or NE, compare bit to zero).
5289 Operand 1: register operand to test, or CONST_INT memory address.
5290 Operand 2: bit number (for QImode operand) or mask (HImode, SImode).
5291 Operand 3: label to jump to if the test is true. */
5294 avr_out_sbxx_branch (rtx insn
, rtx operands
[])
5296 enum rtx_code comp
= GET_CODE (operands
[0]);
5297 int long_jump
= (get_attr_length (insn
) >= 4);
5298 int reverse
= long_jump
|| jump_over_one_insn_p (insn
, operands
[3]);
5302 else if (comp
== LT
)
5306 comp
= reverse_condition (comp
);
5308 if (GET_CODE (operands
[1]) == CONST_INT
)
5310 if (INTVAL (operands
[1]) < 0x40)
5313 output_asm_insn (AS2 (sbis
,%1-0x20,%2), operands
);
5315 output_asm_insn (AS2 (sbic
,%1-0x20,%2), operands
);
5319 output_asm_insn (AS2 (in
,__tmp_reg__
,%1-0x20), operands
);
5321 output_asm_insn (AS2 (sbrs
,__tmp_reg__
,%2), operands
);
5323 output_asm_insn (AS2 (sbrc
,__tmp_reg__
,%2), operands
);
5326 else /* GET_CODE (operands[1]) == REG */
5328 if (GET_MODE (operands
[1]) == QImode
)
5331 output_asm_insn (AS2 (sbrs
,%1,%2), operands
);
5333 output_asm_insn (AS2 (sbrc
,%1,%2), operands
);
5335 else /* HImode or SImode */
5337 static char buf
[] = "sbrc %A1,0";
5338 int bit_nr
= exact_log2 (INTVAL (operands
[2])
5339 & GET_MODE_MASK (GET_MODE (operands
[1])));
5341 buf
[3] = (comp
== EQ
) ? 's' : 'c';
5342 buf
[6] = 'A' + (bit_nr
>> 3);
5343 buf
[9] = '0' + (bit_nr
& 7);
5344 output_asm_insn (buf
, operands
);
5349 return (AS1 (rjmp
,.+4) CR_TAB
5352 return AS1 (rjmp
,%3);
5357 avr_asm_out_ctor (rtx symbol
, int priority
)
5359 fputs ("\t.global __do_global_ctors\n", asm_out_file
);
5360 default_ctor_section_asm_out_constructor (symbol
, priority
);
5364 avr_asm_out_dtor (rtx symbol
, int priority
)
5366 fputs ("\t.global __do_global_dtors\n", asm_out_file
);
5367 default_dtor_section_asm_out_destructor (symbol
, priority
);