1 /* The Blackfin code generation auxiliary output file.
2 Copyright (C) 2005, 2006 Free Software Foundation, Inc.
3 Contributed by Analog Devices.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "insn-codes.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
42 #include "target-def.h"
48 #include "integrate.h"
50 #include "langhooks.h"
51 #include "bfin-protos.h"
54 #include "basic-block.h"
57 /* A C structure for machine-specific, per-function data.
58 This is added to the cfun structure. */
59 struct machine_function
GTY(())
61 int has_hardware_loops
;
64 /* Test and compare insns in bfin.md store the information needed to
65 generate branch and scc insns here. */
66 rtx bfin_compare_op0
, bfin_compare_op1
;
68 /* RTX for condition code flag register and RETS register */
69 extern GTY(()) rtx bfin_cc_rtx
;
70 extern GTY(()) rtx bfin_rets_rtx
;
71 rtx bfin_cc_rtx
, bfin_rets_rtx
;
73 int max_arg_registers
= 0;
75 /* Arrays used when emitting register names. */
76 const char *short_reg_names
[] = SHORT_REGISTER_NAMES
;
77 const char *high_reg_names
[] = HIGH_REGISTER_NAMES
;
78 const char *dregs_pair_names
[] = DREGS_PAIR_NAMES
;
79 const char *byte_reg_names
[] = BYTE_REGISTER_NAMES
;
81 static int arg_regs
[] = FUNCTION_ARG_REGISTERS
;
83 /* Nonzero if -mshared-library-id was given. */
84 static int bfin_lib_id_given
;
86 /* Nonzero if -fschedule-insns2 was given. We override it and
87 call the scheduler ourselves during reorg. */
88 static int bfin_flag_schedule_insns2
;
90 /* Determines whether we run variable tracking in machine dependent
92 static int bfin_flag_var_tracking
;
94 int splitting_for_sched
;
97 bfin_globalize_label (FILE *stream
, const char *name
)
99 fputs (".global ", stream
);
100 assemble_name (stream
, name
);
106 output_file_start (void)
108 FILE *file
= asm_out_file
;
111 /* Variable tracking should be run after all optimizations which change order
112 of insns. It also needs a valid CFG. This can't be done in
113 override_options, because flag_var_tracking is finalized after
115 bfin_flag_var_tracking
= flag_var_tracking
;
116 flag_var_tracking
= 0;
118 fprintf (file
, ".file \"%s\";\n", input_filename
);
120 for (i
= 0; arg_regs
[i
] >= 0; i
++)
122 max_arg_registers
= i
; /* how many arg reg used */
125 /* Called early in the compilation to conditionally modify
126 fixed_regs/call_used_regs. */
129 conditional_register_usage (void)
131 /* initialize condition code flag register rtx */
132 bfin_cc_rtx
= gen_rtx_REG (BImode
, REG_CC
);
133 bfin_rets_rtx
= gen_rtx_REG (Pmode
, REG_RETS
);
136 /* Examine machine-dependent attributes of function type FUNTYPE and return its
137 type. See the definition of E_FUNKIND. */
139 static e_funkind
funkind (tree funtype
)
141 tree attrs
= TYPE_ATTRIBUTES (funtype
);
142 if (lookup_attribute ("interrupt_handler", attrs
))
143 return INTERRUPT_HANDLER
;
144 else if (lookup_attribute ("exception_handler", attrs
))
145 return EXCPT_HANDLER
;
146 else if (lookup_attribute ("nmi_handler", attrs
))
152 /* Legitimize PIC addresses. If the address is already position-independent,
153 we return ORIG. Newly generated position-independent addresses go into a
154 reg. This is REG if nonzero, otherwise we allocate register(s) as
155 necessary. PICREG is the register holding the pointer to the PIC offset
159 legitimize_pic_address (rtx orig
, rtx reg
, rtx picreg
)
164 if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == LABEL_REF
)
169 if (TARGET_ID_SHARED_LIBRARY
)
170 unspec
= UNSPEC_MOVE_PIC
;
171 else if (GET_CODE (addr
) == SYMBOL_REF
172 && SYMBOL_REF_FUNCTION_P (addr
))
173 unspec
= UNSPEC_FUNCDESC_GOT17M4
;
175 unspec
= UNSPEC_MOVE_FDPIC
;
179 gcc_assert (!no_new_pseudos
);
180 reg
= gen_reg_rtx (Pmode
);
183 tmp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), unspec
);
184 new = gen_const_mem (Pmode
, gen_rtx_PLUS (Pmode
, picreg
, tmp
));
186 emit_move_insn (reg
, new);
187 if (picreg
== pic_offset_table_rtx
)
188 current_function_uses_pic_offset_table
= 1;
192 else if (GET_CODE (addr
) == CONST
|| GET_CODE (addr
) == PLUS
)
196 if (GET_CODE (addr
) == CONST
)
198 addr
= XEXP (addr
, 0);
199 gcc_assert (GET_CODE (addr
) == PLUS
);
202 if (XEXP (addr
, 0) == picreg
)
207 gcc_assert (!no_new_pseudos
);
208 reg
= gen_reg_rtx (Pmode
);
211 base
= legitimize_pic_address (XEXP (addr
, 0), reg
, picreg
);
212 addr
= legitimize_pic_address (XEXP (addr
, 1),
213 base
== reg
? NULL_RTX
: reg
,
216 if (GET_CODE (addr
) == CONST_INT
)
218 gcc_assert (! reload_in_progress
&& ! reload_completed
);
219 addr
= force_reg (Pmode
, addr
);
222 if (GET_CODE (addr
) == PLUS
&& CONSTANT_P (XEXP (addr
, 1)))
224 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (addr
, 0));
225 addr
= XEXP (addr
, 1);
228 return gen_rtx_PLUS (Pmode
, base
, addr
);
234 /* Stack frame layout. */
236 /* Compute the number of DREGS to save with a push_multiple operation.
237 This could include registers that aren't modified in the function,
238 since push_multiple only takes a range of registers.
239 If IS_INTHANDLER, then everything that is live must be saved, even
240 if normally call-clobbered. */
243 n_dregs_to_save (bool is_inthandler
)
247 for (i
= REG_R0
; i
<= REG_R7
; i
++)
249 if (regs_ever_live
[i
] && (is_inthandler
|| ! call_used_regs
[i
]))
250 return REG_R7
- i
+ 1;
252 if (current_function_calls_eh_return
)
257 unsigned test
= EH_RETURN_DATA_REGNO (j
);
258 if (test
== INVALID_REGNUM
)
261 return REG_R7
- i
+ 1;
269 /* Like n_dregs_to_save, but compute number of PREGS to save. */
272 n_pregs_to_save (bool is_inthandler
)
276 for (i
= REG_P0
; i
<= REG_P5
; i
++)
277 if ((regs_ever_live
[i
] && (is_inthandler
|| ! call_used_regs
[i
]))
279 && i
== PIC_OFFSET_TABLE_REGNUM
280 && (current_function_uses_pic_offset_table
281 || (TARGET_ID_SHARED_LIBRARY
&& ! current_function_is_leaf
))))
282 return REG_P5
- i
+ 1;
286 /* Determine if we are going to save the frame pointer in the prologue. */
289 must_save_fp_p (void)
291 return frame_pointer_needed
|| regs_ever_live
[REG_FP
];
295 stack_frame_needed_p (void)
297 /* EH return puts a new return address into the frame using an
298 address relative to the frame pointer. */
299 if (current_function_calls_eh_return
)
301 return frame_pointer_needed
;
304 /* Emit code to save registers in the prologue. SAVEALL is nonzero if we
305 must save all registers; this is used for interrupt handlers.
306 SPREG contains (reg:SI REG_SP). IS_INTHANDLER is true if we're doing
307 this for an interrupt (or exception) handler. */
310 expand_prologue_reg_save (rtx spreg
, int saveall
, bool is_inthandler
)
312 int ndregs
= saveall
? 8 : n_dregs_to_save (is_inthandler
);
313 int npregs
= saveall
? 6 : n_pregs_to_save (is_inthandler
);
314 int dregno
= REG_R7
+ 1 - ndregs
;
315 int pregno
= REG_P5
+ 1 - npregs
;
316 int total
= ndregs
+ npregs
;
323 val
= GEN_INT (-total
* 4);
324 pat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total
+ 2));
325 XVECEXP (pat
, 0, 0) = gen_rtx_UNSPEC (VOIDmode
, gen_rtvec (1, val
),
326 UNSPEC_PUSH_MULTIPLE
);
327 XVECEXP (pat
, 0, total
+ 1) = gen_rtx_SET (VOIDmode
, spreg
,
328 gen_rtx_PLUS (Pmode
, spreg
,
330 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, total
+ 1)) = 1;
331 for (i
= 0; i
< total
; i
++)
333 rtx memref
= gen_rtx_MEM (word_mode
,
334 gen_rtx_PLUS (Pmode
, spreg
,
335 GEN_INT (- i
* 4 - 4)));
339 subpat
= gen_rtx_SET (VOIDmode
, memref
, gen_rtx_REG (word_mode
,
345 subpat
= gen_rtx_SET (VOIDmode
, memref
, gen_rtx_REG (word_mode
,
349 XVECEXP (pat
, 0, i
+ 1) = subpat
;
350 RTX_FRAME_RELATED_P (subpat
) = 1;
352 insn
= emit_insn (pat
);
353 RTX_FRAME_RELATED_P (insn
) = 1;
356 /* Emit code to restore registers in the epilogue. SAVEALL is nonzero if we
357 must save all registers; this is used for interrupt handlers.
358 SPREG contains (reg:SI REG_SP). IS_INTHANDLER is true if we're doing
359 this for an interrupt (or exception) handler. */
362 expand_epilogue_reg_restore (rtx spreg
, bool saveall
, bool is_inthandler
)
364 int ndregs
= saveall
? 8 : n_dregs_to_save (is_inthandler
);
365 int npregs
= saveall
? 6 : n_pregs_to_save (is_inthandler
);
366 int total
= ndregs
+ npregs
;
373 pat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total
+ 1));
374 XVECEXP (pat
, 0, 0) = gen_rtx_SET (VOIDmode
, spreg
,
375 gen_rtx_PLUS (Pmode
, spreg
,
376 GEN_INT (total
* 4)));
383 for (i
= 0; i
< total
; i
++)
386 ? gen_rtx_PLUS (Pmode
, spreg
, GEN_INT (i
* 4))
388 rtx memref
= gen_rtx_MEM (word_mode
, addr
);
391 XVECEXP (pat
, 0, i
+ 1)
392 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (word_mode
, regno
), memref
);
401 insn
= emit_insn (pat
);
402 RTX_FRAME_RELATED_P (insn
) = 1;
405 /* Perform any needed actions needed for a function that is receiving a
406 variable number of arguments.
410 MODE and TYPE are the mode and type of the current parameter.
412 PRETEND_SIZE is a variable that should be set to the amount of stack
413 that must be pushed by the prolog to pretend that our caller pushed
416 Normally, this macro will push all remaining incoming registers on the
417 stack and set PRETEND_SIZE to the length of the registers pushed.
420 - VDSP C compiler manual (our ABI) says that a variable args function
421 should save the R0, R1 and R2 registers in the stack.
422 - The caller will always leave space on the stack for the
423 arguments that are passed in registers, so we dont have
424 to leave any extra space.
425 - now, the vastart pointer can access all arguments from the stack. */
428 setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
429 enum machine_mode mode ATTRIBUTE_UNUSED
,
430 tree type ATTRIBUTE_UNUSED
, int *pretend_size
,
439 /* The move for named arguments will be generated automatically by the
440 compiler. We need to generate the move rtx for the unnamed arguments
441 if they are in the first 3 words. We assume at least 1 named argument
442 exists, so we never generate [ARGP] = R0 here. */
444 for (i
= cum
->words
+ 1; i
< max_arg_registers
; i
++)
446 mem
= gen_rtx_MEM (Pmode
,
447 plus_constant (arg_pointer_rtx
, (i
* UNITS_PER_WORD
)));
448 emit_move_insn (mem
, gen_rtx_REG (Pmode
, i
));
454 /* Value should be nonzero if functions must have frame pointers.
455 Zero means the frame pointer need not be set up (and parms may
456 be accessed via the stack pointer) in functions that seem suitable. */
459 bfin_frame_pointer_required (void)
461 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
463 if (fkind
!= SUBROUTINE
)
466 /* We turn on -fomit-frame-pointer if -momit-leaf-frame-pointer is used,
467 so we have to override it for non-leaf functions. */
468 if (TARGET_OMIT_LEAF_FRAME_POINTER
&& ! current_function_is_leaf
)
474 /* Return the number of registers pushed during the prologue. */
477 n_regs_saved_by_prologue (void)
479 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
480 bool is_inthandler
= fkind
!= SUBROUTINE
;
481 tree attrs
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
482 bool all
= (lookup_attribute ("saveall", attrs
) != NULL_TREE
483 || (is_inthandler
&& !current_function_is_leaf
));
484 int ndregs
= all
? 8 : n_dregs_to_save (is_inthandler
);
485 int npregs
= all
? 6 : n_pregs_to_save (is_inthandler
);
486 int n
= ndregs
+ npregs
;
488 if (all
|| stack_frame_needed_p ())
489 /* We use a LINK instruction in this case. */
493 if (must_save_fp_p ())
495 if (! current_function_is_leaf
)
499 if (fkind
!= SUBROUTINE
)
503 /* Increment once for ASTAT. */
507 if (lookup_attribute ("nesting", attrs
))
510 for (i
= REG_P7
+ 1; i
< REG_CC
; i
++)
513 || (!leaf_function_p () && call_used_regs
[i
]))
514 n
+= i
== REG_A0
|| i
== REG_A1
? 2 : 1;
519 /* Return the offset between two registers, one to be eliminated, and the other
520 its replacement, at the start of a routine. */
523 bfin_initial_elimination_offset (int from
, int to
)
525 HOST_WIDE_INT offset
= 0;
527 if (from
== ARG_POINTER_REGNUM
)
528 offset
= n_regs_saved_by_prologue () * 4;
530 if (to
== STACK_POINTER_REGNUM
)
532 if (current_function_outgoing_args_size
>= FIXED_STACK_AREA
)
533 offset
+= current_function_outgoing_args_size
;
534 else if (current_function_outgoing_args_size
)
535 offset
+= FIXED_STACK_AREA
;
537 offset
+= get_frame_size ();
543 /* Emit code to load a constant CONSTANT into register REG; setting
544 RTX_FRAME_RELATED_P on all insns we generate if RELATED is true.
545 Make sure that the insns we generate need not be split. */
548 frame_related_constant_load (rtx reg
, HOST_WIDE_INT constant
, bool related
)
551 rtx cst
= GEN_INT (constant
);
553 if (constant
>= -32768 && constant
< 65536)
554 insn
= emit_move_insn (reg
, cst
);
557 /* We don't call split_load_immediate here, since dwarf2out.c can get
558 confused about some of the more clever sequences it can generate. */
559 insn
= emit_insn (gen_movsi_high (reg
, cst
));
561 RTX_FRAME_RELATED_P (insn
) = 1;
562 insn
= emit_insn (gen_movsi_low (reg
, reg
, cst
));
565 RTX_FRAME_RELATED_P (insn
) = 1;
568 /* Generate efficient code to add a value to a P register. We can use
569 P1 as a scratch register. Set RTX_FRAME_RELATED_P on the generated
570 insns if FRAME is nonzero. */
573 add_to_reg (rtx reg
, HOST_WIDE_INT value
, int frame
)
578 /* Choose whether to use a sequence using a temporary register, or
579 a sequence with multiple adds. We can add a signed 7 bit value
580 in one instruction. */
581 if (value
> 120 || value
< -120)
583 rtx tmpreg
= gen_rtx_REG (SImode
, REG_P1
);
587 frame_related_constant_load (tmpreg
, value
, TRUE
);
589 insn
= emit_move_insn (tmpreg
, GEN_INT (value
));
591 insn
= emit_insn (gen_addsi3 (reg
, reg
, tmpreg
));
593 RTX_FRAME_RELATED_P (insn
) = 1;
604 /* We could use -62, but that would leave the stack unaligned, so
608 insn
= emit_insn (gen_addsi3 (reg
, reg
, GEN_INT (size
)));
610 RTX_FRAME_RELATED_P (insn
) = 1;
616 /* Generate a LINK insn for a frame sized FRAME_SIZE. If this constant
617 is too large, generate a sequence of insns that has the same effect.
618 SPREG contains (reg:SI REG_SP). */
621 emit_link_insn (rtx spreg
, HOST_WIDE_INT frame_size
)
623 HOST_WIDE_INT link_size
= frame_size
;
627 if (link_size
> 262140)
630 /* Use a LINK insn with as big a constant as possible, then subtract
631 any remaining size from the SP. */
632 insn
= emit_insn (gen_link (GEN_INT (-8 - link_size
)));
633 RTX_FRAME_RELATED_P (insn
) = 1;
635 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
637 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
638 gcc_assert (GET_CODE (set
) == SET
);
639 RTX_FRAME_RELATED_P (set
) = 1;
642 frame_size
-= link_size
;
646 /* Must use a call-clobbered PREG that isn't the static chain. */
647 rtx tmpreg
= gen_rtx_REG (Pmode
, REG_P1
);
649 frame_related_constant_load (tmpreg
, -frame_size
, TRUE
);
650 insn
= emit_insn (gen_addsi3 (spreg
, spreg
, tmpreg
));
651 RTX_FRAME_RELATED_P (insn
) = 1;
655 /* Return the number of bytes we must reserve for outgoing arguments
656 in the current function's stack frame. */
661 if (current_function_outgoing_args_size
)
663 if (current_function_outgoing_args_size
>= FIXED_STACK_AREA
)
664 return current_function_outgoing_args_size
;
666 return FIXED_STACK_AREA
;
671 /* Save RETS and FP, and allocate a stack frame. ALL is true if the
672 function must save all its registers (true only for certain interrupt
676 do_link (rtx spreg
, HOST_WIDE_INT frame_size
, bool all
)
678 frame_size
+= arg_area_size ();
680 if (all
|| stack_frame_needed_p ()
681 || (must_save_fp_p () && ! current_function_is_leaf
))
682 emit_link_insn (spreg
, frame_size
);
685 if (! current_function_is_leaf
)
687 rtx pat
= gen_movsi (gen_rtx_MEM (Pmode
,
688 gen_rtx_PRE_DEC (Pmode
, spreg
)),
690 rtx insn
= emit_insn (pat
);
691 RTX_FRAME_RELATED_P (insn
) = 1;
693 if (must_save_fp_p ())
695 rtx pat
= gen_movsi (gen_rtx_MEM (Pmode
,
696 gen_rtx_PRE_DEC (Pmode
, spreg
)),
697 gen_rtx_REG (Pmode
, REG_FP
));
698 rtx insn
= emit_insn (pat
);
699 RTX_FRAME_RELATED_P (insn
) = 1;
701 add_to_reg (spreg
, -frame_size
, 1);
705 /* Like do_link, but used for epilogues to deallocate the stack frame. */
708 do_unlink (rtx spreg
, HOST_WIDE_INT frame_size
, bool all
)
710 frame_size
+= arg_area_size ();
712 if (all
|| stack_frame_needed_p ())
713 emit_insn (gen_unlink ());
716 rtx postinc
= gen_rtx_MEM (Pmode
, gen_rtx_POST_INC (Pmode
, spreg
));
718 add_to_reg (spreg
, frame_size
, 0);
719 if (must_save_fp_p ())
721 rtx fpreg
= gen_rtx_REG (Pmode
, REG_FP
);
722 emit_move_insn (fpreg
, postinc
);
723 emit_insn (gen_rtx_USE (VOIDmode
, fpreg
));
725 if (! current_function_is_leaf
)
727 emit_move_insn (bfin_rets_rtx
, postinc
);
728 emit_insn (gen_rtx_USE (VOIDmode
, bfin_rets_rtx
));
733 /* Generate a prologue suitable for a function of kind FKIND. This is
734 called for interrupt and exception handler prologues.
735 SPREG contains (reg:SI REG_SP). */
738 expand_interrupt_handler_prologue (rtx spreg
, e_funkind fkind
)
741 HOST_WIDE_INT frame_size
= get_frame_size ();
742 rtx predec1
= gen_rtx_PRE_DEC (SImode
, spreg
);
743 rtx predec
= gen_rtx_MEM (SImode
, predec1
);
745 tree attrs
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
746 bool all
= lookup_attribute ("saveall", attrs
) != NULL_TREE
;
747 tree kspisusp
= lookup_attribute ("kspisusp", attrs
);
751 insn
= emit_move_insn (spreg
, gen_rtx_REG (Pmode
, REG_USP
));
752 RTX_FRAME_RELATED_P (insn
) = 1;
755 /* We need space on the stack in case we need to save the argument
757 if (fkind
== EXCPT_HANDLER
)
759 insn
= emit_insn (gen_addsi3 (spreg
, spreg
, GEN_INT (-12)));
760 RTX_FRAME_RELATED_P (insn
) = 1;
763 insn
= emit_move_insn (predec
, gen_rtx_REG (SImode
, REG_ASTAT
));
764 RTX_FRAME_RELATED_P (insn
) = 1;
766 /* If we're calling other functions, they won't save their call-clobbered
767 registers, so we must save everything here. */
768 if (!current_function_is_leaf
)
770 expand_prologue_reg_save (spreg
, all
, true);
772 for (i
= REG_P7
+ 1; i
< REG_CC
; i
++)
775 || (!leaf_function_p () && call_used_regs
[i
]))
777 if (i
== REG_A0
|| i
== REG_A1
)
778 insn
= emit_move_insn (gen_rtx_MEM (PDImode
, predec1
),
779 gen_rtx_REG (PDImode
, i
));
781 insn
= emit_move_insn (predec
, gen_rtx_REG (SImode
, i
));
782 RTX_FRAME_RELATED_P (insn
) = 1;
785 if (lookup_attribute ("nesting", attrs
))
787 rtx srcreg
= gen_rtx_REG (Pmode
, (fkind
== EXCPT_HANDLER
? REG_RETX
788 : fkind
== NMI_HANDLER
? REG_RETN
790 insn
= emit_move_insn (predec
, srcreg
);
791 RTX_FRAME_RELATED_P (insn
) = 1;
794 do_link (spreg
, frame_size
, all
);
796 if (fkind
== EXCPT_HANDLER
)
798 rtx r0reg
= gen_rtx_REG (SImode
, REG_R0
);
799 rtx r1reg
= gen_rtx_REG (SImode
, REG_R1
);
800 rtx r2reg
= gen_rtx_REG (SImode
, REG_R2
);
803 insn
= emit_move_insn (r0reg
, gen_rtx_REG (SImode
, REG_SEQSTAT
));
804 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
,
806 insn
= emit_insn (gen_ashrsi3 (r0reg
, r0reg
, GEN_INT (26)));
807 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
,
809 insn
= emit_insn (gen_ashlsi3 (r0reg
, r0reg
, GEN_INT (26)));
810 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
,
812 insn
= emit_move_insn (r1reg
, spreg
);
813 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
,
815 insn
= emit_move_insn (r2reg
, gen_rtx_REG (Pmode
, REG_FP
));
816 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
,
818 insn
= emit_insn (gen_addsi3 (r2reg
, r2reg
, GEN_INT (8)));
819 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
,
824 /* Generate an epilogue suitable for a function of kind FKIND. This is
825 called for interrupt and exception handler epilogues.
826 SPREG contains (reg:SI REG_SP). */
829 expand_interrupt_handler_epilogue (rtx spreg
, e_funkind fkind
)
832 rtx postinc1
= gen_rtx_POST_INC (SImode
, spreg
);
833 rtx postinc
= gen_rtx_MEM (SImode
, postinc1
);
834 tree attrs
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
835 bool all
= lookup_attribute ("saveall", attrs
) != NULL_TREE
;
837 /* A slightly crude technique to stop flow from trying to delete "dead"
839 MEM_VOLATILE_P (postinc
) = 1;
841 do_unlink (spreg
, get_frame_size (), all
);
843 if (lookup_attribute ("nesting", attrs
))
845 rtx srcreg
= gen_rtx_REG (Pmode
, (fkind
== EXCPT_HANDLER
? REG_RETX
846 : fkind
== NMI_HANDLER
? REG_RETN
848 emit_move_insn (srcreg
, postinc
);
851 /* If we're calling other functions, they won't save their call-clobbered
852 registers, so we must save (and restore) everything here. */
853 if (!current_function_is_leaf
)
856 for (i
= REG_CC
- 1; i
> REG_P7
; i
--)
859 || (!leaf_function_p () && call_used_regs
[i
]))
861 if (i
== REG_A0
|| i
== REG_A1
)
863 rtx mem
= gen_rtx_MEM (PDImode
, postinc1
);
864 MEM_VOLATILE_P (mem
) = 1;
865 emit_move_insn (gen_rtx_REG (PDImode
, i
), mem
);
868 emit_move_insn (gen_rtx_REG (SImode
, i
), postinc
);
871 expand_epilogue_reg_restore (spreg
, all
, true);
873 emit_move_insn (gen_rtx_REG (SImode
, REG_ASTAT
), postinc
);
875 /* Deallocate any space we left on the stack in case we needed to save the
876 argument registers. */
877 if (fkind
== EXCPT_HANDLER
)
878 emit_insn (gen_addsi3 (spreg
, spreg
, GEN_INT (12)));
880 emit_jump_insn (gen_return_internal (GEN_INT (fkind
)));
883 /* Used while emitting the prologue to generate code to load the correct value
884 into the PIC register, which is passed in DEST. */
887 bfin_load_pic_reg (rtx dest
)
889 struct cgraph_local_info
*i
= NULL
;
892 if (flag_unit_at_a_time
)
893 i
= cgraph_local_info (current_function_decl
);
895 /* Functions local to the translation unit don't need to reload the
896 pic reg, since the caller always passes a usable one. */
898 return pic_offset_table_rtx
;
900 if (bfin_lib_id_given
)
901 addr
= plus_constant (pic_offset_table_rtx
, -4 - bfin_library_id
* 4);
903 addr
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
904 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
905 UNSPEC_LIBRARY_OFFSET
));
906 insn
= emit_insn (gen_movsi (dest
, gen_rtx_MEM (Pmode
, addr
)));
907 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
, NULL
);
911 /* Generate RTL for the prologue of the current function. */
914 bfin_expand_prologue (void)
917 HOST_WIDE_INT frame_size
= get_frame_size ();
918 rtx spreg
= gen_rtx_REG (Pmode
, REG_SP
);
919 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
920 rtx pic_reg_loaded
= NULL_RTX
;
922 if (fkind
!= SUBROUTINE
)
924 expand_interrupt_handler_prologue (spreg
, fkind
);
928 if (current_function_limit_stack
929 || TARGET_STACK_CHECK_L1
)
932 = bfin_initial_elimination_offset (ARG_POINTER_REGNUM
,
933 STACK_POINTER_REGNUM
);
934 rtx lim
= current_function_limit_stack
? stack_limit_rtx
: NULL_RTX
;
935 rtx p2reg
= gen_rtx_REG (Pmode
, REG_P2
);
939 rtx p1reg
= gen_rtx_REG (Pmode
, REG_P1
);
940 emit_move_insn (p2reg
, gen_int_mode (0xFFB00000, SImode
));
941 emit_move_insn (p2reg
, gen_rtx_MEM (Pmode
, p2reg
));
944 if (GET_CODE (lim
) == SYMBOL_REF
)
946 if (TARGET_ID_SHARED_LIBRARY
)
948 rtx p1reg
= gen_rtx_REG (Pmode
, REG_P1
);
950 pic_reg_loaded
= bfin_load_pic_reg (p2reg
);
951 val
= legitimize_pic_address (stack_limit_rtx
, p1reg
,
953 emit_move_insn (p1reg
, val
);
954 frame_related_constant_load (p2reg
, offset
, FALSE
);
955 emit_insn (gen_addsi3 (p2reg
, p2reg
, p1reg
));
960 rtx limit
= plus_constant (lim
, offset
);
961 emit_move_insn (p2reg
, limit
);
968 emit_move_insn (p2reg
, lim
);
969 add_to_reg (p2reg
, offset
, 0);
972 emit_insn (gen_compare_lt (bfin_cc_rtx
, spreg
, lim
));
973 emit_insn (gen_trapifcc ());
975 expand_prologue_reg_save (spreg
, 0, false);
977 do_link (spreg
, frame_size
, false);
979 if (TARGET_ID_SHARED_LIBRARY
981 && (current_function_uses_pic_offset_table
982 || !current_function_is_leaf
))
983 bfin_load_pic_reg (pic_offset_table_rtx
);
986 /* Generate RTL for the epilogue of the current function. NEED_RETURN is zero
987 if this is for a sibcall. EH_RETURN is nonzero if we're expanding an
988 eh_return pattern. */
991 bfin_expand_epilogue (int need_return
, int eh_return
)
993 rtx spreg
= gen_rtx_REG (Pmode
, REG_SP
);
994 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
996 if (fkind
!= SUBROUTINE
)
998 expand_interrupt_handler_epilogue (spreg
, fkind
);
1002 do_unlink (spreg
, get_frame_size (), false);
1004 expand_epilogue_reg_restore (spreg
, false, false);
1006 /* Omit the return insn if this is for a sibcall. */
1011 emit_insn (gen_addsi3 (spreg
, spreg
, gen_rtx_REG (Pmode
, REG_P2
)));
1013 emit_jump_insn (gen_return_internal (GEN_INT (SUBROUTINE
)));
1016 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
1019 bfin_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
1020 unsigned int new_reg
)
1022 /* Interrupt functions can only use registers that have already been
1023 saved by the prologue, even if they would normally be
1026 if (funkind (TREE_TYPE (current_function_decl
)) != SUBROUTINE
1027 && !regs_ever_live
[new_reg
])
1033 /* Return the value of the return address for the frame COUNT steps up
1034 from the current frame, after the prologue.
1035 We punt for everything but the current frame by returning const0_rtx. */
1038 bfin_return_addr_rtx (int count
)
1043 return get_hard_reg_initial_val (Pmode
, REG_RETS
);
1046 /* Try machine-dependent ways of modifying an illegitimate address X
1047 to be legitimate. If we find one, return the new, valid address,
1048 otherwise return NULL_RTX.
1050 OLDX is the address as it was before break_out_memory_refs was called.
1051 In some cases it is useful to look at this to decide what needs to be done.
1053 MODE is the mode of the memory reference. */
1056 legitimize_address (rtx x ATTRIBUTE_UNUSED
, rtx oldx ATTRIBUTE_UNUSED
,
1057 enum machine_mode mode ATTRIBUTE_UNUSED
)
1063 bfin_delegitimize_address (rtx orig_x
)
1067 if (GET_CODE (x
) != MEM
)
1071 if (GET_CODE (x
) == PLUS
1072 && GET_CODE (XEXP (x
, 1)) == UNSPEC
1073 && XINT (XEXP (x
, 1), 1) == UNSPEC_MOVE_PIC
1074 && GET_CODE (XEXP (x
, 0)) == REG
1075 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
1076 return XVECEXP (XEXP (x
, 1), 0, 0);
1081 /* This predicate is used to compute the length of a load/store insn.
1082 OP is a MEM rtx, we return nonzero if its addressing mode requires a
1083 32 bit instruction. */
1086 effective_address_32bit_p (rtx op
, enum machine_mode mode
)
1088 HOST_WIDE_INT offset
;
1090 mode
= GET_MODE (op
);
1093 if (GET_CODE (op
) != PLUS
)
1095 gcc_assert (REG_P (op
) || GET_CODE (op
) == POST_INC
1096 || GET_CODE (op
) == PRE_DEC
|| GET_CODE (op
) == POST_DEC
);
1100 offset
= INTVAL (XEXP (op
, 1));
1102 /* All byte loads use a 16 bit offset. */
1103 if (GET_MODE_SIZE (mode
) == 1)
1106 if (GET_MODE_SIZE (mode
) == 4)
1108 /* Frame pointer relative loads can use a negative offset, all others
1109 are restricted to a small positive one. */
1110 if (XEXP (op
, 0) == frame_pointer_rtx
)
1111 return offset
< -128 || offset
> 60;
1112 return offset
< 0 || offset
> 60;
1115 /* Must be HImode now. */
1116 return offset
< 0 || offset
> 30;
1119 /* Returns true if X is a memory reference using an I register. */
1121 bfin_dsp_memref_p (rtx x
)
1126 if (GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == PRE_INC
1127 || GET_CODE (x
) == POST_DEC
|| GET_CODE (x
) == PRE_DEC
)
1132 /* Return cost of the memory address ADDR.
1133 All addressing modes are equally cheap on the Blackfin. */
1136 bfin_address_cost (rtx addr ATTRIBUTE_UNUSED
)
1141 /* Subroutine of print_operand; used to print a memory reference X to FILE. */
1144 print_address_operand (FILE *file
, rtx x
)
1146 switch (GET_CODE (x
))
1149 output_address (XEXP (x
, 0));
1150 fprintf (file
, "+");
1151 output_address (XEXP (x
, 1));
1155 fprintf (file
, "--");
1156 output_address (XEXP (x
, 0));
1159 output_address (XEXP (x
, 0));
1160 fprintf (file
, "++");
1163 output_address (XEXP (x
, 0));
1164 fprintf (file
, "--");
1168 gcc_assert (GET_CODE (x
) != MEM
);
1169 print_operand (file
, x
, 0);
1174 /* Adding intp DImode support by Tony
1180 print_operand (FILE *file
, rtx x
, char code
)
1182 enum machine_mode mode
;
1186 if (GET_MODE (current_output_insn
) == SImode
)
1187 fprintf (file
, " ||");
1189 fprintf (file
, ";");
1193 mode
= GET_MODE (x
);
1198 switch (GET_CODE (x
))
1201 fprintf (file
, "e");
1204 fprintf (file
, "ne");
1207 fprintf (file
, "g");
1210 fprintf (file
, "l");
1213 fprintf (file
, "ge");
1216 fprintf (file
, "le");
1219 fprintf (file
, "g");
1222 fprintf (file
, "l");
1225 fprintf (file
, "ge");
1228 fprintf (file
, "le");
1231 output_operand_lossage ("invalid %%j value");
1235 case 'J': /* reverse logic */
1236 switch (GET_CODE(x
))
1239 fprintf (file
, "ne");
1242 fprintf (file
, "e");
1245 fprintf (file
, "le");
1248 fprintf (file
, "ge");
1251 fprintf (file
, "l");
1254 fprintf (file
, "g");
1257 fprintf (file
, "le");
1260 fprintf (file
, "ge");
1263 fprintf (file
, "l");
1266 fprintf (file
, "g");
1269 output_operand_lossage ("invalid %%J value");
1274 switch (GET_CODE (x
))
1279 gcc_assert (REGNO (x
) < 32);
1280 fprintf (file
, "%s", short_reg_names
[REGNO (x
)]);
1281 /*fprintf (file, "\n%d\n ", REGNO (x));*/
1284 else if (code
== 'd')
1286 gcc_assert (REGNO (x
) < 32);
1287 fprintf (file
, "%s", high_reg_names
[REGNO (x
)]);
1290 else if (code
== 'w')
1292 gcc_assert (REGNO (x
) == REG_A0
|| REGNO (x
) == REG_A1
);
1293 fprintf (file
, "%s.w", reg_names
[REGNO (x
)]);
1295 else if (code
== 'x')
1297 gcc_assert (REGNO (x
) == REG_A0
|| REGNO (x
) == REG_A1
);
1298 fprintf (file
, "%s.x", reg_names
[REGNO (x
)]);
1300 else if (code
== 'D')
1302 fprintf (file
, "%s", dregs_pair_names
[REGNO (x
)]);
1304 else if (code
== 'H')
1306 gcc_assert (mode
== DImode
|| mode
== DFmode
);
1307 gcc_assert (REG_P (x
));
1308 fprintf (file
, "%s", reg_names
[REGNO (x
) + 1]);
1310 else if (code
== 'T')
1312 gcc_assert (D_REGNO_P (REGNO (x
)));
1313 fprintf (file
, "%s", byte_reg_names
[REGNO (x
)]);
1316 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1322 print_address_operand (file
, x
);
1334 fputs ("(FU)", file
);
1337 fputs ("(T)", file
);
1340 fputs ("(TFU)", file
);
1343 fputs ("(W32)", file
);
1346 fputs ("(IS)", file
);
1349 fputs ("(IU)", file
);
1352 fputs ("(IH)", file
);
1355 fputs ("(M)", file
);
1358 fputs ("(ISS2)", file
);
1361 fputs ("(S2RND)", file
);
1368 else if (code
== 'b')
1370 if (INTVAL (x
) == 0)
1372 else if (INTVAL (x
) == 1)
1378 /* Moves to half registers with d or h modifiers always use unsigned
1380 else if (code
== 'd')
1381 x
= GEN_INT ((INTVAL (x
) >> 16) & 0xffff);
1382 else if (code
== 'h')
1383 x
= GEN_INT (INTVAL (x
) & 0xffff);
1384 else if (code
== 'N')
1385 x
= GEN_INT (-INTVAL (x
));
1386 else if (code
== 'X')
1387 x
= GEN_INT (exact_log2 (0xffffffff & INTVAL (x
)));
1388 else if (code
== 'Y')
1389 x
= GEN_INT (exact_log2 (0xffffffff & ~INTVAL (x
)));
1390 else if (code
== 'Z')
1391 /* Used for LINK insns. */
1392 x
= GEN_INT (-8 - INTVAL (x
));
1397 output_addr_const (file
, x
);
1401 output_operand_lossage ("invalid const_double operand");
1405 switch (XINT (x
, 1))
1407 case UNSPEC_MOVE_PIC
:
1408 output_addr_const (file
, XVECEXP (x
, 0, 0));
1409 fprintf (file
, "@GOT");
1412 case UNSPEC_MOVE_FDPIC
:
1413 output_addr_const (file
, XVECEXP (x
, 0, 0));
1414 fprintf (file
, "@GOT17M4");
1417 case UNSPEC_FUNCDESC_GOT17M4
:
1418 output_addr_const (file
, XVECEXP (x
, 0, 0));
1419 fprintf (file
, "@FUNCDESC_GOT17M4");
1422 case UNSPEC_LIBRARY_OFFSET
:
1423 fprintf (file
, "_current_shared_library_p5_offset_");
1432 output_addr_const (file
, x
);
1437 /* Argument support functions. */
1439 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1440 for a call to a function whose data type is FNTYPE.
1441 For a library call, FNTYPE is 0.
1442 VDSP C Compiler manual, our ABI says that
1443 first 3 words of arguments will use R0, R1 and R2.
1447 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
1448 rtx libname ATTRIBUTE_UNUSED
)
1450 static CUMULATIVE_ARGS zero_cum
;
1454 /* Set up the number of registers to use for passing arguments. */
1456 cum
->nregs
= max_arg_registers
;
1457 cum
->arg_regs
= arg_regs
;
1459 cum
->call_cookie
= CALL_NORMAL
;
1460 /* Check for a longcall attribute. */
1461 if (fntype
&& lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
)))
1462 cum
->call_cookie
|= CALL_SHORT
;
1463 else if (fntype
&& lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
)))
1464 cum
->call_cookie
|= CALL_LONG
;
1469 /* Update the data in CUM to advance over an argument
1470 of mode MODE and data type TYPE.
1471 (TYPE is null for libcalls where that information may not be available.) */
1474 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
1475 int named ATTRIBUTE_UNUSED
)
1477 int count
, bytes
, words
;
1479 bytes
= (mode
== BLKmode
) ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
1480 words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1482 cum
->words
+= words
;
1483 cum
->nregs
-= words
;
1485 if (cum
->nregs
<= 0)
1488 cum
->arg_regs
= NULL
;
1492 for (count
= 1; count
<= words
; count
++)
1499 /* Define where to put the arguments to a function.
1500 Value is zero to push the argument on the stack,
1501 or a hard register in which to store the argument.
1503 MODE is the argument's machine mode.
1504 TYPE is the data type of the argument (as a tree).
1505 This is null for libcalls where that information may
1507 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1508 the preceding args and about the function being called.
1509 NAMED is nonzero if this argument is a named parameter
1510 (otherwise it is an extra parameter matching an ellipsis). */
1513 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
1514 int named ATTRIBUTE_UNUSED
)
1517 = (mode
== BLKmode
) ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
1519 if (mode
== VOIDmode
)
1520 /* Compute operand 2 of the call insn. */
1521 return GEN_INT (cum
->call_cookie
);
1527 return gen_rtx_REG (mode
, *(cum
->arg_regs
));
1532 /* For an arg passed partly in registers and partly in memory,
1533 this is the number of bytes passed in registers.
1534 For args passed entirely in registers or entirely in memory, zero.
1536 Refer VDSP C Compiler manual, our ABI.
1537 First 3 words are in registers. So, if a an argument is larger
1538 than the registers available, it will span the register and
1542 bfin_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1543 tree type ATTRIBUTE_UNUSED
,
1544 bool named ATTRIBUTE_UNUSED
)
1547 = (mode
== BLKmode
) ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
1548 int bytes_left
= cum
->nregs
* UNITS_PER_WORD
;
1553 if (bytes_left
== 0)
1555 if (bytes
> bytes_left
)
1560 /* Variable sized types are passed by reference. */
1563 bfin_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
1564 enum machine_mode mode ATTRIBUTE_UNUSED
,
1565 tree type
, bool named ATTRIBUTE_UNUSED
)
1567 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
1570 /* Decide whether a type should be returned in memory (true)
1571 or in a register (false). This is called by the macro
1572 RETURN_IN_MEMORY. */
1575 bfin_return_in_memory (tree type
)
1577 int size
= int_size_in_bytes (type
);
1578 return size
> 2 * UNITS_PER_WORD
|| size
== -1;
1581 /* Register in which address to store a structure value
1582 is passed to a function. */
1584 bfin_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
1585 int incoming ATTRIBUTE_UNUSED
)
1587 return gen_rtx_REG (Pmode
, REG_P0
);
1590 /* Return true when register may be used to pass function parameters. */
1593 function_arg_regno_p (int n
)
1596 for (i
= 0; arg_regs
[i
] != -1; i
++)
1597 if (n
== arg_regs
[i
])
1602 /* Returns 1 if OP contains a symbol reference */
1605 symbolic_reference_mentioned_p (rtx op
)
1607 register const char *fmt
;
1610 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1613 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
1614 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
1620 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
1621 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
1625 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
1632 /* Decide whether we can make a sibling call to a function. DECL is the
1633 declaration of the function being targeted by the call and EXP is the
1634 CALL_EXPR representing the call. */
1637 bfin_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
1638 tree exp ATTRIBUTE_UNUSED
)
1640 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
1641 if (fkind
!= SUBROUTINE
)
1643 if (!TARGET_ID_SHARED_LIBRARY
|| TARGET_SEP_DATA
)
1646 /* When compiling for ID shared libraries, can't sibcall a local function
1647 from a non-local function, because the local function thinks it does
1648 not need to reload P5 in the prologue, but the sibcall wil pop P5 in the
1649 sibcall epilogue, and we end up with the wrong value in P5. */
1651 if (!flag_unit_at_a_time
|| decl
== NULL
)
1652 /* Not enough information. */
1656 struct cgraph_local_info
*this_func
, *called_func
;
1659 this_func
= cgraph_local_info (current_function_decl
);
1660 called_func
= cgraph_local_info (decl
);
1661 return !called_func
->local
|| this_func
->local
;
1665 /* Emit RTL insns to initialize the variable parts of a trampoline at
1666 TRAMP. FNADDR is an RTX for the address of the function's pure
1667 code. CXT is an RTX for the static chain value for the function. */
1670 initialize_trampoline (tramp
, fnaddr
, cxt
)
1671 rtx tramp
, fnaddr
, cxt
;
1673 rtx t1
= copy_to_reg (fnaddr
);
1674 rtx t2
= copy_to_reg (cxt
);
1680 rtx a
= memory_address (Pmode
, plus_constant (tramp
, 8));
1681 addr
= memory_address (Pmode
, tramp
);
1682 emit_move_insn (gen_rtx_MEM (SImode
, addr
), a
);
1686 addr
= memory_address (Pmode
, plus_constant (tramp
, i
+ 2));
1687 emit_move_insn (gen_rtx_MEM (HImode
, addr
), gen_lowpart (HImode
, t1
));
1688 emit_insn (gen_ashrsi3 (t1
, t1
, GEN_INT (16)));
1689 addr
= memory_address (Pmode
, plus_constant (tramp
, i
+ 6));
1690 emit_move_insn (gen_rtx_MEM (HImode
, addr
), gen_lowpart (HImode
, t1
));
1692 addr
= memory_address (Pmode
, plus_constant (tramp
, i
+ 10));
1693 emit_move_insn (gen_rtx_MEM (HImode
, addr
), gen_lowpart (HImode
, t2
));
1694 emit_insn (gen_ashrsi3 (t2
, t2
, GEN_INT (16)));
1695 addr
= memory_address (Pmode
, plus_constant (tramp
, i
+ 14));
1696 emit_move_insn (gen_rtx_MEM (HImode
, addr
), gen_lowpart (HImode
, t2
));
1699 /* Emit insns to move operands[1] into operands[0]. */
1702 emit_pic_move (rtx
*operands
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1704 rtx temp
= reload_in_progress
? operands
[0] : gen_reg_rtx (Pmode
);
1706 gcc_assert (!TARGET_FDPIC
|| !(reload_in_progress
|| reload_completed
));
1707 if (GET_CODE (operands
[0]) == MEM
&& SYMBOLIC_CONST (operands
[1]))
1708 operands
[1] = force_reg (SImode
, operands
[1]);
1710 operands
[1] = legitimize_pic_address (operands
[1], temp
,
1711 TARGET_FDPIC
? OUR_FDPIC_REG
1712 : pic_offset_table_rtx
);
1715 /* Expand a move operation in mode MODE. The operands are in OPERANDS.
1716 Returns true if no further code must be generated, false if the caller
1717 should generate an insn to move OPERANDS[1] to OPERANDS[0]. */
1720 expand_move (rtx
*operands
, enum machine_mode mode
)
1722 rtx op
= operands
[1];
1723 if ((TARGET_ID_SHARED_LIBRARY
|| TARGET_FDPIC
)
1724 && SYMBOLIC_CONST (op
))
1725 emit_pic_move (operands
, mode
);
1726 else if (mode
== SImode
&& GET_CODE (op
) == CONST
1727 && GET_CODE (XEXP (op
, 0)) == PLUS
1728 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
1729 && !bfin_legitimate_constant_p (op
))
1731 rtx dest
= operands
[0];
1733 gcc_assert (!reload_in_progress
&& !reload_completed
);
1735 op0
= force_reg (mode
, XEXP (op
, 0));
1737 if (!insn_data
[CODE_FOR_addsi3
].operand
[2].predicate (op1
, mode
))
1738 op1
= force_reg (mode
, op1
);
1739 if (GET_CODE (dest
) == MEM
)
1740 dest
= gen_reg_rtx (mode
);
1741 emit_insn (gen_addsi3 (dest
, op0
, op1
));
1742 if (dest
== operands
[0])
1746 /* Don't generate memory->memory or constant->memory moves, go through a
1748 else if ((reload_in_progress
| reload_completed
) == 0
1749 && GET_CODE (operands
[0]) == MEM
1750 && GET_CODE (operands
[1]) != REG
)
1751 operands
[1] = force_reg (mode
, operands
[1]);
1755 /* Split one or more DImode RTL references into pairs of SImode
1756 references. The RTL can be REG, offsettable MEM, integer constant, or
1757 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
1758 split and "num" is its length. lo_half and hi_half are output arrays
1759 that parallel "operands". */
1762 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
1766 rtx op
= operands
[num
];
1768 /* simplify_subreg refuse to split volatile memory addresses,
1769 but we still have to handle it. */
1770 if (GET_CODE (op
) == MEM
)
1772 lo_half
[num
] = adjust_address (op
, SImode
, 0);
1773 hi_half
[num
] = adjust_address (op
, SImode
, 4);
1777 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
1778 GET_MODE (op
) == VOIDmode
1779 ? DImode
: GET_MODE (op
), 0);
1780 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
1781 GET_MODE (op
) == VOIDmode
1782 ? DImode
: GET_MODE (op
), 4);
1788 bfin_longcall_p (rtx op
, int call_cookie
)
1790 gcc_assert (GET_CODE (op
) == SYMBOL_REF
);
1791 if (call_cookie
& CALL_SHORT
)
1793 if (call_cookie
& CALL_LONG
)
1795 if (TARGET_LONG_CALLS
)
1800 /* Expand a call instruction. FNADDR is the call target, RETVAL the return value.
1801 COOKIE is a CONST_INT holding the call_cookie prepared init_cumulative_args.
1802 SIBCALL is nonzero if this is a sibling call. */
1805 bfin_expand_call (rtx retval
, rtx fnaddr
, rtx callarg1
, rtx cookie
, int sibcall
)
1807 rtx use
= NULL
, call
;
1808 rtx callee
= XEXP (fnaddr
, 0);
1809 int nelts
= 2 + !!sibcall
;
1811 rtx picreg
= get_hard_reg_initial_val (SImode
, FDPIC_REGNO
);
1814 /* In an untyped call, we can get NULL for operand 2. */
1815 if (cookie
== NULL_RTX
)
1816 cookie
= const0_rtx
;
1818 /* Static functions and indirect calls don't need the pic register. */
1819 if (!TARGET_FDPIC
&& flag_pic
1820 && GET_CODE (callee
) == SYMBOL_REF
1821 && !SYMBOL_REF_LOCAL_P (callee
))
1822 use_reg (&use
, pic_offset_table_rtx
);
1826 if (GET_CODE (callee
) != SYMBOL_REF
1827 || bfin_longcall_p (callee
, INTVAL (cookie
)))
1830 if (! address_operand (addr
, Pmode
))
1831 addr
= force_reg (Pmode
, addr
);
1833 fnaddr
= gen_reg_rtx (SImode
);
1834 emit_insn (gen_load_funcdescsi (fnaddr
, addr
));
1835 fnaddr
= gen_rtx_MEM (Pmode
, fnaddr
);
1837 picreg
= gen_reg_rtx (SImode
);
1838 emit_insn (gen_load_funcdescsi (picreg
,
1839 plus_constant (addr
, 4)));
1844 else if ((!register_no_elim_operand (callee
, Pmode
)
1845 && GET_CODE (callee
) != SYMBOL_REF
)
1846 || (GET_CODE (callee
) == SYMBOL_REF
1847 && ((TARGET_ID_SHARED_LIBRARY
&& !TARGET_LEAF_ID_SHARED_LIBRARY
)
1848 || bfin_longcall_p (callee
, INTVAL (cookie
)))))
1850 callee
= copy_to_mode_reg (Pmode
, callee
);
1851 fnaddr
= gen_rtx_MEM (Pmode
, callee
);
1853 call
= gen_rtx_CALL (VOIDmode
, fnaddr
, callarg1
);
1856 call
= gen_rtx_SET (VOIDmode
, retval
, call
);
1858 pat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nelts
));
1860 XVECEXP (pat
, 0, n
++) = call
;
1862 XVECEXP (pat
, 0, n
++) = gen_rtx_USE (VOIDmode
, picreg
);
1863 XVECEXP (pat
, 0, n
++) = gen_rtx_USE (VOIDmode
, cookie
);
1865 XVECEXP (pat
, 0, n
++) = gen_rtx_RETURN (VOIDmode
);
1866 call
= emit_call_insn (pat
);
1868 CALL_INSN_FUNCTION_USAGE (call
) = use
;
1871 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
1874 hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1876 /* Allow only dregs to store value of mode HI or QI */
1877 enum reg_class
class = REGNO_REG_CLASS (regno
);
1882 if (mode
== V2HImode
)
1883 return D_REGNO_P (regno
);
1884 if (class == CCREGS
)
1885 return mode
== BImode
;
1886 if (mode
== PDImode
|| mode
== V2PDImode
)
1887 return regno
== REG_A0
|| regno
== REG_A1
;
1889 /* Allow all normal 32 bit regs, except REG_M3, in case regclass ever comes
1890 up with a bad register class (such as ALL_REGS) for DImode. */
1892 return regno
< REG_M3
;
1895 && TEST_HARD_REG_BIT (reg_class_contents
[PROLOGUE_REGS
], regno
))
1898 return TEST_HARD_REG_BIT (reg_class_contents
[MOST_REGS
], regno
);
1901 /* Implements target hook vector_mode_supported_p. */
1904 bfin_vector_mode_supported_p (enum machine_mode mode
)
1906 return mode
== V2HImode
;
1909 /* Return the cost of moving data from a register in class CLASS1 to
1910 one in class CLASS2. A cost of 2 is the default. */
1913 bfin_register_move_cost (enum machine_mode mode
,
1914 enum reg_class class1
, enum reg_class class2
)
1916 /* These need secondary reloads, so they're more expensive. */
1917 if ((class1
== CCREGS
&& class2
!= DREGS
)
1918 || (class1
!= DREGS
&& class2
== CCREGS
))
1921 /* If optimizing for size, always prefer reg-reg over reg-memory moves. */
1925 /* There are some stalls involved when moving from a DREG to a different
1926 class reg, and using the value in one of the following instructions.
1927 Attempt to model this by slightly discouraging such moves. */
1928 if (class1
== DREGS
&& class2
!= DREGS
)
1931 if (GET_MODE_CLASS (mode
) == MODE_INT
)
1933 /* Discourage trying to use the accumulators. */
1934 if (TEST_HARD_REG_BIT (reg_class_contents
[class1
], REG_A0
)
1935 || TEST_HARD_REG_BIT (reg_class_contents
[class1
], REG_A1
)
1936 || TEST_HARD_REG_BIT (reg_class_contents
[class2
], REG_A0
)
1937 || TEST_HARD_REG_BIT (reg_class_contents
[class2
], REG_A1
))
1943 /* Return the cost of moving data of mode M between a
1944 register and memory. A value of 2 is the default; this cost is
1945 relative to those in `REGISTER_MOVE_COST'.
1947 ??? In theory L1 memory has single-cycle latency. We should add a switch
1948 that tells the compiler whether we expect to use only L1 memory for the
1949 program; it'll make the costs more accurate. */
1952 bfin_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
1953 enum reg_class
class,
1954 int in ATTRIBUTE_UNUSED
)
1956 /* Make memory accesses slightly more expensive than any register-register
1957 move. Also, penalize non-DP registers, since they need secondary
1958 reloads to load and store. */
1959 if (! reg_class_subset_p (class, DPREGS
))
1965 /* Inform reload about cases where moving X with a mode MODE to a register in
1966 CLASS requires an extra scratch register. Return the class needed for the
1967 scratch register. */
1969 static enum reg_class
1970 bfin_secondary_reload (bool in_p
, rtx x
, enum reg_class
class,
1971 enum machine_mode mode
, secondary_reload_info
*sri
)
1973 /* If we have HImode or QImode, we can only use DREGS as secondary registers;
1974 in most other cases we can also use PREGS. */
1975 enum reg_class default_class
= GET_MODE_SIZE (mode
) >= 4 ? DPREGS
: DREGS
;
1976 enum reg_class x_class
= NO_REGS
;
1977 enum rtx_code code
= GET_CODE (x
);
1980 x
= SUBREG_REG (x
), code
= GET_CODE (x
);
1983 int regno
= REGNO (x
);
1984 if (regno
>= FIRST_PSEUDO_REGISTER
)
1985 regno
= reg_renumber
[regno
];
1990 x_class
= REGNO_REG_CLASS (regno
);
1993 /* We can be asked to reload (plus (FP) (large_constant)) into a DREG.
1994 This happens as a side effect of register elimination, and we need
1995 a scratch register to do it. */
1996 if (fp_plus_const_operand (x
, mode
))
1998 rtx op2
= XEXP (x
, 1);
1999 int large_constant_p
= ! CONST_7BIT_IMM_P (INTVAL (op2
));
2001 if (class == PREGS
|| class == PREGS_CLOBBERED
)
2003 /* If destination is a DREG, we can do this without a scratch register
2004 if the constant is valid for an add instruction. */
2005 if ((class == DREGS
|| class == DPREGS
)
2006 && ! large_constant_p
)
2008 /* Reloading to anything other than a DREG? Use a PREG scratch
2010 sri
->icode
= CODE_FOR_reload_insi
;
2014 /* Data can usually be moved freely between registers of most classes.
2015 AREGS are an exception; they can only move to or from another register
2016 in AREGS or one in DREGS. They can also be assigned the constant 0. */
2017 if (x_class
== AREGS
)
2018 return class == DREGS
|| class == AREGS
? NO_REGS
: DREGS
;
2022 if (x
!= const0_rtx
&& x_class
!= DREGS
)
2028 /* CCREGS can only be moved from/to DREGS. */
2029 if (class == CCREGS
&& x_class
!= DREGS
)
2031 if (x_class
== CCREGS
&& class != DREGS
)
2034 /* All registers other than AREGS can load arbitrary constants. The only
2035 case that remains is MEM. */
2037 if (! reg_class_subset_p (class, default_class
))
2038 return default_class
;
2042 /* Implement TARGET_HANDLE_OPTION. */
2045 bfin_handle_option (size_t code
, const char *arg
, int value
)
2049 case OPT_mshared_library_id_
:
2050 if (value
> MAX_LIBRARY_ID
)
2051 error ("-mshared-library-id=%s is not between 0 and %d",
2052 arg
, MAX_LIBRARY_ID
);
2053 bfin_lib_id_given
= 1;
2061 static struct machine_function
*
2062 bfin_init_machine_status (void)
2064 struct machine_function
*f
;
2066 f
= ggc_alloc_cleared (sizeof (struct machine_function
));
2071 /* Implement the macro OVERRIDE_OPTIONS. */
2074 override_options (void)
2076 if (TARGET_OMIT_LEAF_FRAME_POINTER
)
2077 flag_omit_frame_pointer
= 1;
2079 /* Library identification */
2080 if (bfin_lib_id_given
&& ! TARGET_ID_SHARED_LIBRARY
)
2081 error ("-mshared-library-id= specified without -mid-shared-library");
2083 if (TARGET_ID_SHARED_LIBRARY
&& flag_pic
== 0)
2086 if (stack_limit_rtx
&& TARGET_STACK_CHECK_L1
)
2087 error ("Can't use multiple stack checking methods together.");
2089 if (TARGET_ID_SHARED_LIBRARY
&& TARGET_FDPIC
)
2090 error ("ID shared libraries and FD-PIC mode can't be used together.");
2092 /* Don't allow the user to specify -mid-shared-library and -msep-data
2093 together, as it makes little sense from a user's point of view... */
2094 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
2095 error ("cannot specify both -msep-data and -mid-shared-library");
2096 /* ... internally, however, it's nearly the same. */
2097 if (TARGET_SEP_DATA
)
2098 target_flags
|= MASK_ID_SHARED_LIBRARY
| MASK_LEAF_ID_SHARED_LIBRARY
;
2100 /* There is no single unaligned SI op for PIC code. Sometimes we
2101 need to use ".4byte" and sometimes we need to use ".picptr".
2102 See bfin_assemble_integer for details. */
2104 targetm
.asm_out
.unaligned_op
.si
= 0;
2106 /* Silently turn off flag_pic if not doing FDPIC or ID shared libraries,
2107 since we don't support it and it'll just break. */
2108 if (flag_pic
&& !TARGET_FDPIC
&& !TARGET_ID_SHARED_LIBRARY
)
2111 flag_schedule_insns
= 0;
2113 /* Passes after sched2 can break the helpful TImode annotations that
2114 haifa-sched puts on every insn. Just do scheduling in reorg. */
2115 bfin_flag_schedule_insns2
= flag_schedule_insns_after_reload
;
2116 flag_schedule_insns_after_reload
= 0;
2118 init_machine_status
= bfin_init_machine_status
;
2121 /* Return the destination address of BRANCH.
2122 We need to use this instead of get_attr_length, because the
2123 cbranch_with_nops pattern conservatively sets its length to 6, and
2124 we still prefer to use shorter sequences. */
2127 branch_dest (rtx branch
)
2131 rtx pat
= PATTERN (branch
);
2132 if (GET_CODE (pat
) == PARALLEL
)
2133 pat
= XVECEXP (pat
, 0, 0);
2134 dest
= SET_SRC (pat
);
2135 if (GET_CODE (dest
) == IF_THEN_ELSE
)
2136 dest
= XEXP (dest
, 1);
2137 dest
= XEXP (dest
, 0);
2138 dest_uid
= INSN_UID (dest
);
2139 return INSN_ADDRESSES (dest_uid
);
2142 /* Return nonzero if INSN is annotated with a REG_BR_PROB note that indicates
2143 it's a branch that's predicted taken. */
2146 cbranch_predicted_taken_p (rtx insn
)
2148 rtx x
= find_reg_note (insn
, REG_BR_PROB
, 0);
2152 int pred_val
= INTVAL (XEXP (x
, 0));
2154 return pred_val
>= REG_BR_PROB_BASE
/ 2;
2160 /* Templates for use by asm_conditional_branch. */
2162 static const char *ccbranch_templates
[][3] = {
2163 { "if !cc jump %3;", "if cc jump 4 (bp); jump.s %3;", "if cc jump 6 (bp); jump.l %3;" },
2164 { "if cc jump %3;", "if !cc jump 4 (bp); jump.s %3;", "if !cc jump 6 (bp); jump.l %3;" },
2165 { "if !cc jump %3 (bp);", "if cc jump 4; jump.s %3;", "if cc jump 6; jump.l %3;" },
2166 { "if cc jump %3 (bp);", "if !cc jump 4; jump.s %3;", "if !cc jump 6; jump.l %3;" },
2169 /* Output INSN, which is a conditional branch instruction with operands
2172 We deal with the various forms of conditional branches that can be generated
2173 by bfin_reorg to prevent the hardware from doing speculative loads, by
2174 - emitting a sufficient number of nops, if N_NOPS is nonzero, or
2175 - always emitting the branch as predicted taken, if PREDICT_TAKEN is true.
2176 Either of these is only necessary if the branch is short, otherwise the
2177 template we use ends in an unconditional jump which flushes the pipeline
2181 asm_conditional_branch (rtx insn
, rtx
*operands
, int n_nops
, int predict_taken
)
2183 int offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
2184 /* Note : offset for instructions like if cc jmp; jump.[sl] offset
2185 is to be taken from start of if cc rather than jump.
2186 Range for jump.s is (-4094, 4096) instead of (-4096, 4094)
2188 int len
= (offset
>= -1024 && offset
<= 1022 ? 0
2189 : offset
>= -4094 && offset
<= 4096 ? 1
2191 int bp
= predict_taken
&& len
== 0 ? 1 : cbranch_predicted_taken_p (insn
);
2192 int idx
= (bp
<< 1) | (GET_CODE (operands
[0]) == EQ
? BRF
: BRT
);
2193 output_asm_insn (ccbranch_templates
[idx
][len
], operands
);
2194 gcc_assert (n_nops
== 0 || !bp
);
2196 while (n_nops
-- > 0)
2197 output_asm_insn ("nop;", NULL
);
2200 /* Emit rtl for a comparison operation CMP in mode MODE. Operands have been
2201 stored in bfin_compare_op0 and bfin_compare_op1 already. */
2204 bfin_gen_compare (rtx cmp
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2206 enum rtx_code code1
, code2
;
2207 rtx op0
= bfin_compare_op0
, op1
= bfin_compare_op1
;
2208 rtx tem
= bfin_cc_rtx
;
2209 enum rtx_code code
= GET_CODE (cmp
);
2211 /* If we have a BImode input, then we already have a compare result, and
2212 do not need to emit another comparison. */
2213 if (GET_MODE (op0
) == BImode
)
2215 gcc_assert ((code
== NE
|| code
== EQ
) && op1
== const0_rtx
);
2216 tem
= op0
, code2
= code
;
2221 /* bfin has these conditions */
2231 code1
= reverse_condition (code
);
2235 emit_insn (gen_rtx_SET (BImode
, tem
,
2236 gen_rtx_fmt_ee (code1
, BImode
, op0
, op1
)));
2239 return gen_rtx_fmt_ee (code2
, BImode
, tem
, CONST0_RTX (BImode
));
2242 /* Return nonzero iff C has exactly one bit set if it is interpreted
2243 as a 32 bit constant. */
2246 log2constp (unsigned HOST_WIDE_INT c
)
2249 return c
!= 0 && (c
& (c
-1)) == 0;
2252 /* Returns the number of consecutive least significant zeros in the binary
2253 representation of *V.
2254 We modify *V to contain the original value arithmetically shifted right by
2255 the number of zeroes. */
2258 shiftr_zero (HOST_WIDE_INT
*v
)
2260 unsigned HOST_WIDE_INT tmp
= *v
;
2261 unsigned HOST_WIDE_INT sgn
;
2267 sgn
= tmp
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1));
2268 while ((tmp
& 0x1) == 0 && n
<= 32)
2270 tmp
= (tmp
>> 1) | sgn
;
2277 /* After reload, split the load of an immediate constant. OPERANDS are the
2278 operands of the movsi_insn pattern which we are splitting. We return
2279 nonzero if we emitted a sequence to load the constant, zero if we emitted
2280 nothing because we want to use the splitter's default sequence. */
2283 split_load_immediate (rtx operands
[])
2285 HOST_WIDE_INT val
= INTVAL (operands
[1]);
2287 HOST_WIDE_INT shifted
= val
;
2288 HOST_WIDE_INT shifted_compl
= ~val
;
2289 int num_zero
= shiftr_zero (&shifted
);
2290 int num_compl_zero
= shiftr_zero (&shifted_compl
);
2291 unsigned int regno
= REGNO (operands
[0]);
2292 enum reg_class class1
= REGNO_REG_CLASS (regno
);
2294 /* This case takes care of single-bit set/clear constants, which we could
2295 also implement with BITSET/BITCLR. */
2297 && shifted
>= -32768 && shifted
< 65536
2298 && (D_REGNO_P (regno
)
2299 || (regno
>= REG_P0
&& regno
<= REG_P7
&& num_zero
<= 2)))
2301 emit_insn (gen_movsi (operands
[0], GEN_INT (shifted
)));
2302 emit_insn (gen_ashlsi3 (operands
[0], operands
[0], GEN_INT (num_zero
)));
2307 tmp
|= -(tmp
& 0x8000);
2309 /* If high word has one bit set or clear, try to use a bit operation. */
2310 if (D_REGNO_P (regno
))
2312 if (log2constp (val
& 0xFFFF0000))
2314 emit_insn (gen_movsi (operands
[0], GEN_INT (val
& 0xFFFF)));
2315 emit_insn (gen_iorsi3 (operands
[0], operands
[0], GEN_INT (val
& 0xFFFF0000)));
2318 else if (log2constp (val
| 0xFFFF) && (val
& 0x8000) != 0)
2320 emit_insn (gen_movsi (operands
[0], GEN_INT (tmp
)));
2321 emit_insn (gen_andsi3 (operands
[0], operands
[0], GEN_INT (val
| 0xFFFF)));
2325 if (D_REGNO_P (regno
))
2327 if (CONST_7BIT_IMM_P (tmp
))
2329 emit_insn (gen_movsi (operands
[0], GEN_INT (tmp
)));
2330 emit_insn (gen_movstricthi_high (operands
[0], GEN_INT (val
& -65536)));
2334 if ((val
& 0xFFFF0000) == 0)
2336 emit_insn (gen_movsi (operands
[0], const0_rtx
));
2337 emit_insn (gen_movsi_low (operands
[0], operands
[0], operands
[1]));
2341 if ((val
& 0xFFFF0000) == 0xFFFF0000)
2343 emit_insn (gen_movsi (operands
[0], constm1_rtx
));
2344 emit_insn (gen_movsi_low (operands
[0], operands
[0], operands
[1]));
2349 /* Need DREGs for the remaining case. */
2354 && num_compl_zero
&& CONST_7BIT_IMM_P (shifted_compl
))
2356 /* If optimizing for size, generate a sequence that has more instructions
2358 emit_insn (gen_movsi (operands
[0], GEN_INT (shifted_compl
)));
2359 emit_insn (gen_ashlsi3 (operands
[0], operands
[0],
2360 GEN_INT (num_compl_zero
)));
2361 emit_insn (gen_one_cmplsi2 (operands
[0], operands
[0]));
2367 /* Return true if the legitimate memory address for a memory operand of mode
2368 MODE. Return false if not. */
2371 bfin_valid_add (enum machine_mode mode
, HOST_WIDE_INT value
)
2373 unsigned HOST_WIDE_INT v
= value
> 0 ? value
: -value
;
2374 int sz
= GET_MODE_SIZE (mode
);
2375 int shift
= sz
== 1 ? 0 : sz
== 2 ? 1 : 2;
2376 /* The usual offsettable_memref machinery doesn't work so well for this
2377 port, so we deal with the problem here. */
2378 if (value
> 0 && sz
== 8)
2380 return (v
& ~(0x7fff << shift
)) == 0;
2384 bfin_valid_reg_p (unsigned int regno
, int strict
, enum machine_mode mode
,
2385 enum rtx_code outer_code
)
2388 return REGNO_OK_FOR_BASE_STRICT_P (regno
, mode
, outer_code
, SCRATCH
);
2390 return REGNO_OK_FOR_BASE_NONSTRICT_P (regno
, mode
, outer_code
, SCRATCH
);
2394 bfin_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
2396 switch (GET_CODE (x
)) {
2398 if (bfin_valid_reg_p (REGNO (x
), strict
, mode
, MEM
))
2402 if (REG_P (XEXP (x
, 0))
2403 && bfin_valid_reg_p (REGNO (XEXP (x
, 0)), strict
, mode
, PLUS
)
2404 && ((GET_CODE (XEXP (x
, 1)) == UNSPEC
&& mode
== SImode
)
2405 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
2406 && bfin_valid_add (mode
, INTVAL (XEXP (x
, 1))))))
2411 if (LEGITIMATE_MODE_FOR_AUTOINC_P (mode
)
2412 && REG_P (XEXP (x
, 0))
2413 && bfin_valid_reg_p (REGNO (XEXP (x
, 0)), strict
, mode
, POST_INC
))
2416 if (LEGITIMATE_MODE_FOR_AUTOINC_P (mode
)
2417 && XEXP (x
, 0) == stack_pointer_rtx
2418 && REG_P (XEXP (x
, 0))
2419 && bfin_valid_reg_p (REGNO (XEXP (x
, 0)), strict
, mode
, PRE_DEC
))
2428 /* Decide whether we can force certain constants to memory. If we
2429 decide we can't, the caller should be able to cope with it in
2433 bfin_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED
)
2435 /* We have only one class of non-legitimate constants, and our movsi
2436 expander knows how to handle them. Dropping these constants into the
2437 data section would only shift the problem - we'd still get relocs
2438 outside the object, in the data section rather than the text section. */
2442 /* Ensure that for any constant of the form symbol + offset, the offset
2443 remains within the object. Any other constants are ok.
2444 This ensures that flat binaries never have to deal with relocations
2445 crossing section boundaries. */
2448 bfin_legitimate_constant_p (rtx x
)
2451 HOST_WIDE_INT offset
;
2453 if (GET_CODE (x
) != CONST
)
2457 gcc_assert (GET_CODE (x
) == PLUS
);
2461 if (GET_CODE (sym
) != SYMBOL_REF
2462 || GET_CODE (x
) != CONST_INT
)
2464 offset
= INTVAL (x
);
2466 if (SYMBOL_REF_DECL (sym
) == 0)
2469 || offset
>= int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (sym
))))
2476 bfin_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2478 int cost2
= COSTS_N_INSNS (1);
2484 if (outer_code
== SET
|| outer_code
== PLUS
)
2485 *total
= CONST_7BIT_IMM_P (INTVAL (x
)) ? 0 : cost2
;
2486 else if (outer_code
== AND
)
2487 *total
= log2constp (~INTVAL (x
)) ? 0 : cost2
;
2488 else if (outer_code
== LE
|| outer_code
== LT
|| outer_code
== EQ
)
2489 *total
= (INTVAL (x
) >= -4 && INTVAL (x
) <= 3) ? 0 : cost2
;
2490 else if (outer_code
== LEU
|| outer_code
== LTU
)
2491 *total
= (INTVAL (x
) >= 0 && INTVAL (x
) <= 7) ? 0 : cost2
;
2492 else if (outer_code
== MULT
)
2493 *total
= (INTVAL (x
) == 2 || INTVAL (x
) == 4) ? 0 : cost2
;
2494 else if (outer_code
== ASHIFT
&& (INTVAL (x
) == 1 || INTVAL (x
) == 2))
2496 else if (outer_code
== ASHIFT
|| outer_code
== ASHIFTRT
2497 || outer_code
== LSHIFTRT
)
2498 *total
= (INTVAL (x
) >= 0 && INTVAL (x
) <= 31) ? 0 : cost2
;
2499 else if (outer_code
== IOR
|| outer_code
== XOR
)
2500 *total
= (INTVAL (x
) & (INTVAL (x
) - 1)) == 0 ? 0 : cost2
;
2509 *total
= COSTS_N_INSNS (2);
2515 if (GET_MODE (x
) == SImode
)
2517 if (GET_CODE (op0
) == MULT
2518 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
2520 HOST_WIDE_INT val
= INTVAL (XEXP (op0
, 1));
2521 if (val
== 2 || val
== 4)
2524 *total
+= rtx_cost (XEXP (op0
, 0), outer_code
);
2525 *total
+= rtx_cost (op1
, outer_code
);
2530 if (GET_CODE (op0
) != REG
2531 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2532 *total
+= rtx_cost (op0
, SET
);
2533 #if 0 /* We'd like to do this for accuracy, but it biases the loop optimizer
2534 towards creating too many induction variables. */
2535 if (!reg_or_7bit_operand (op1
, SImode
))
2536 *total
+= rtx_cost (op1
, SET
);
2539 else if (GET_MODE (x
) == DImode
)
2542 if (GET_CODE (op1
) != CONST_INT
2543 || !CONST_7BIT_IMM_P (INTVAL (op1
)))
2544 *total
+= rtx_cost (op1
, PLUS
);
2545 if (GET_CODE (op0
) != REG
2546 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2547 *total
+= rtx_cost (op0
, PLUS
);
2552 if (GET_MODE (x
) == DImode
)
2561 if (GET_MODE (x
) == DImode
)
2568 if (GET_CODE (op0
) != REG
2569 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2570 *total
+= rtx_cost (op0
, code
);
2580 /* Handle special cases of IOR: rotates, ALIGN insns, movstricthi_high. */
2583 if ((GET_CODE (op0
) == LSHIFTRT
&& GET_CODE (op1
) == ASHIFT
)
2584 || (GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == ZERO_EXTEND
)
2585 || (GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
2586 || (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == CONST_INT
))
2593 if (GET_CODE (op0
) != REG
2594 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2595 *total
+= rtx_cost (op0
, code
);
2597 if (GET_MODE (x
) == DImode
)
2603 if (GET_MODE (x
) != SImode
)
2608 if (! rhs_andsi3_operand (XEXP (x
, 1), SImode
))
2609 *total
+= rtx_cost (XEXP (x
, 1), code
);
2613 if (! regorlog2_operand (XEXP (x
, 1), SImode
))
2614 *total
+= rtx_cost (XEXP (x
, 1), code
);
2621 if (outer_code
== SET
2622 && XEXP (x
, 1) == const1_rtx
2623 && GET_CODE (XEXP (x
, 2)) == CONST_INT
)
2639 if (GET_CODE (op0
) == GET_CODE (op1
)
2640 && (GET_CODE (op0
) == ZERO_EXTEND
2641 || GET_CODE (op0
) == SIGN_EXTEND
))
2643 *total
= COSTS_N_INSNS (1);
2644 op0
= XEXP (op0
, 0);
2645 op1
= XEXP (op1
, 0);
2647 else if (optimize_size
)
2648 *total
= COSTS_N_INSNS (1);
2650 *total
= COSTS_N_INSNS (3);
2652 if (GET_CODE (op0
) != REG
2653 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2654 *total
+= rtx_cost (op0
, MULT
);
2655 if (GET_CODE (op1
) != REG
2656 && (GET_CODE (op1
) != SUBREG
|| GET_CODE (SUBREG_REG (op1
)) != REG
))
2657 *total
+= rtx_cost (op1
, MULT
);
2663 *total
= COSTS_N_INSNS (32);
2668 if (outer_code
== SET
)
2678 bfin_internal_label (FILE *stream
, const char *prefix
, unsigned long num
)
2680 fprintf (stream
, "%s%s$%ld:\n", LOCAL_LABEL_PREFIX
, prefix
, num
);
2683 /* Used for communication between {push,pop}_multiple_operation (which
2684 we use not only as a predicate) and the corresponding output functions. */
2685 static int first_preg_to_save
, first_dreg_to_save
;
2688 push_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2690 int lastdreg
= 8, lastpreg
= 6;
2693 first_preg_to_save
= lastpreg
;
2694 first_dreg_to_save
= lastdreg
;
2695 for (i
= 1, group
= 0; i
< XVECLEN (op
, 0) - 1; i
++)
2697 rtx t
= XVECEXP (op
, 0, i
);
2701 if (GET_CODE (t
) != SET
)
2705 dest
= SET_DEST (t
);
2706 if (GET_CODE (dest
) != MEM
|| ! REG_P (src
))
2708 dest
= XEXP (dest
, 0);
2709 if (GET_CODE (dest
) != PLUS
2710 || ! REG_P (XEXP (dest
, 0))
2711 || REGNO (XEXP (dest
, 0)) != REG_SP
2712 || GET_CODE (XEXP (dest
, 1)) != CONST_INT
2713 || INTVAL (XEXP (dest
, 1)) != -i
* 4)
2716 regno
= REGNO (src
);
2719 if (D_REGNO_P (regno
))
2722 first_dreg_to_save
= lastdreg
= regno
- REG_R0
;
2724 else if (regno
>= REG_P0
&& regno
<= REG_P7
)
2727 first_preg_to_save
= lastpreg
= regno
- REG_P0
;
2737 if (regno
>= REG_P0
&& regno
<= REG_P7
)
2740 first_preg_to_save
= lastpreg
= regno
- REG_P0
;
2742 else if (regno
!= REG_R0
+ lastdreg
+ 1)
2747 else if (group
== 2)
2749 if (regno
!= REG_P0
+ lastpreg
+ 1)
2758 pop_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2760 int lastdreg
= 8, lastpreg
= 6;
2763 for (i
= 1, group
= 0; i
< XVECLEN (op
, 0); i
++)
2765 rtx t
= XVECEXP (op
, 0, i
);
2769 if (GET_CODE (t
) != SET
)
2773 dest
= SET_DEST (t
);
2774 if (GET_CODE (src
) != MEM
|| ! REG_P (dest
))
2776 src
= XEXP (src
, 0);
2780 if (! REG_P (src
) || REGNO (src
) != REG_SP
)
2783 else if (GET_CODE (src
) != PLUS
2784 || ! REG_P (XEXP (src
, 0))
2785 || REGNO (XEXP (src
, 0)) != REG_SP
2786 || GET_CODE (XEXP (src
, 1)) != CONST_INT
2787 || INTVAL (XEXP (src
, 1)) != (i
- 1) * 4)
2790 regno
= REGNO (dest
);
2793 if (regno
== REG_R7
)
2798 else if (regno
!= REG_P0
+ lastpreg
- 1)
2803 else if (group
== 1)
2805 if (regno
!= REG_R0
+ lastdreg
- 1)
2811 first_dreg_to_save
= lastdreg
;
2812 first_preg_to_save
= lastpreg
;
2816 /* Emit assembly code for one multi-register push described by INSN, with
2817 operands in OPERANDS. */
2820 output_push_multiple (rtx insn
, rtx
*operands
)
2825 /* Validate the insn again, and compute first_[dp]reg_to_save. */
2826 ok
= push_multiple_operation (PATTERN (insn
), VOIDmode
);
2829 if (first_dreg_to_save
== 8)
2830 sprintf (buf
, "[--sp] = ( p5:%d );\n", first_preg_to_save
);
2831 else if (first_preg_to_save
== 6)
2832 sprintf (buf
, "[--sp] = ( r7:%d );\n", first_dreg_to_save
);
2834 sprintf (buf
, "[--sp] = ( r7:%d, p5:%d );\n",
2835 first_dreg_to_save
, first_preg_to_save
);
2837 output_asm_insn (buf
, operands
);
2840 /* Emit assembly code for one multi-register pop described by INSN, with
2841 operands in OPERANDS. */
2844 output_pop_multiple (rtx insn
, rtx
*operands
)
2849 /* Validate the insn again, and compute first_[dp]reg_to_save. */
2850 ok
= pop_multiple_operation (PATTERN (insn
), VOIDmode
);
2853 if (first_dreg_to_save
== 8)
2854 sprintf (buf
, "( p5:%d ) = [sp++];\n", first_preg_to_save
);
2855 else if (first_preg_to_save
== 6)
2856 sprintf (buf
, "( r7:%d ) = [sp++];\n", first_dreg_to_save
);
2858 sprintf (buf
, "( r7:%d, p5:%d ) = [sp++];\n",
2859 first_dreg_to_save
, first_preg_to_save
);
2861 output_asm_insn (buf
, operands
);
2864 /* Adjust DST and SRC by OFFSET bytes, and generate one move in mode MODE. */
2867 single_move_for_movmem (rtx dst
, rtx src
, enum machine_mode mode
, HOST_WIDE_INT offset
)
2869 rtx scratch
= gen_reg_rtx (mode
);
2872 srcmem
= adjust_address_nv (src
, mode
, offset
);
2873 dstmem
= adjust_address_nv (dst
, mode
, offset
);
2874 emit_move_insn (scratch
, srcmem
);
2875 emit_move_insn (dstmem
, scratch
);
2878 /* Expand a string move operation of COUNT_EXP bytes from SRC to DST, with
2879 alignment ALIGN_EXP. Return true if successful, false if we should fall
2880 back on a different method. */
2883 bfin_expand_movmem (rtx dst
, rtx src
, rtx count_exp
, rtx align_exp
)
2885 rtx srcreg
, destreg
, countreg
;
2886 HOST_WIDE_INT align
= 0;
2887 unsigned HOST_WIDE_INT count
= 0;
2889 if (GET_CODE (align_exp
) == CONST_INT
)
2890 align
= INTVAL (align_exp
);
2891 if (GET_CODE (count_exp
) == CONST_INT
)
2893 count
= INTVAL (count_exp
);
2895 if (!TARGET_INLINE_ALL_STRINGOPS
&& count
> 64)
2900 /* If optimizing for size, only do single copies inline. */
2903 if (count
== 2 && align
< 2)
2905 if (count
== 4 && align
< 4)
2907 if (count
!= 1 && count
!= 2 && count
!= 4)
2910 if (align
< 2 && count
!= 1)
2913 destreg
= copy_to_mode_reg (Pmode
, XEXP (dst
, 0));
2914 if (destreg
!= XEXP (dst
, 0))
2915 dst
= replace_equiv_address_nv (dst
, destreg
);
2916 srcreg
= copy_to_mode_reg (Pmode
, XEXP (src
, 0));
2917 if (srcreg
!= XEXP (src
, 0))
2918 src
= replace_equiv_address_nv (src
, srcreg
);
2920 if (count
!= 0 && align
>= 2)
2922 unsigned HOST_WIDE_INT offset
= 0;
2926 if ((count
& ~3) == 4)
2928 single_move_for_movmem (dst
, src
, SImode
, offset
);
2931 else if (count
& ~3)
2933 HOST_WIDE_INT new_count
= ((count
>> 2) & 0x3fffffff) - 1;
2934 countreg
= copy_to_mode_reg (Pmode
, GEN_INT (new_count
));
2936 emit_insn (gen_rep_movsi (destreg
, srcreg
, countreg
, destreg
, srcreg
));
2940 single_move_for_movmem (dst
, src
, HImode
, offset
);
2946 if ((count
& ~1) == 2)
2948 single_move_for_movmem (dst
, src
, HImode
, offset
);
2951 else if (count
& ~1)
2953 HOST_WIDE_INT new_count
= ((count
>> 1) & 0x7fffffff) - 1;
2954 countreg
= copy_to_mode_reg (Pmode
, GEN_INT (new_count
));
2956 emit_insn (gen_rep_movhi (destreg
, srcreg
, countreg
, destreg
, srcreg
));
2961 single_move_for_movmem (dst
, src
, QImode
, offset
);
2968 /* Implement TARGET_SCHED_ISSUE_RATE. */
2971 bfin_issue_rate (void)
2977 bfin_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
2979 enum attr_type insn_type
, dep_insn_type
;
2980 int dep_insn_code_number
;
2982 /* Anti and output dependencies have zero cost. */
2983 if (REG_NOTE_KIND (link
) != 0)
2986 dep_insn_code_number
= recog_memoized (dep_insn
);
2988 /* If we can't recognize the insns, we can't really do anything. */
2989 if (dep_insn_code_number
< 0 || recog_memoized (insn
) < 0)
2992 insn_type
= get_attr_type (insn
);
2993 dep_insn_type
= get_attr_type (dep_insn
);
2995 if (dep_insn_type
== TYPE_MOVE
|| dep_insn_type
== TYPE_MCLD
)
2997 rtx pat
= PATTERN (dep_insn
);
2998 rtx dest
= SET_DEST (pat
);
2999 rtx src
= SET_SRC (pat
);
3000 if (! ADDRESS_REGNO_P (REGNO (dest
)) || ! D_REGNO_P (REGNO (src
)))
3002 return cost
+ (dep_insn_type
== TYPE_MOVE
? 4 : 3);
3009 /* Increment the counter for the number of loop instructions in the
3010 current function. */
3013 bfin_hardware_loop (void)
3015 cfun
->machine
->has_hardware_loops
++;
3018 /* Maximum loop nesting depth. */
3019 #define MAX_LOOP_DEPTH 2
3021 /* Maximum size of a loop. */
3022 #define MAX_LOOP_LENGTH 2042
3024 /* We need to keep a vector of loops */
3025 typedef struct loop_info
*loop_info
;
3026 DEF_VEC_P (loop_info
);
3027 DEF_VEC_ALLOC_P (loop_info
,heap
);
3029 /* Information about a loop we have found (or are in the process of
3031 struct loop_info
GTY (())
3033 /* loop number, for dumps */
3036 /* Predecessor block of the loop. This is the one that falls into
3037 the loop and contains the initialization instruction. */
3038 basic_block predecessor
;
3040 /* First block in the loop. This is the one branched to by the loop_end
3044 /* Last block in the loop (the one with the loop_end insn). */
3047 /* The successor block of the loop. This is the one the loop_end insn
3049 basic_block successor
;
3051 /* The last instruction in the tail. */
3054 /* The loop_end insn. */
3057 /* The iteration register. */
3060 /* The new initialization insn. */
3063 /* The new initialization instruction. */
3066 /* The new label placed at the beginning of the loop. */
3069 /* The new label placed at the end of the loop. */
3072 /* The length of the loop. */
3075 /* The nesting depth of the loop. */
3078 /* Nonzero if we can't optimize this loop. */
3081 /* True if we have visited this loop. */
3084 /* True if this loop body clobbers any of LC0, LT0, or LB0. */
3087 /* True if this loop body clobbers any of LC1, LT1, or LB1. */
3090 /* Next loop in the graph. */
3091 struct loop_info
*next
;
3093 /* Immediate outer loop of this loop. */
3094 struct loop_info
*outer
;
3096 /* Vector of blocks only within the loop, including those within
3098 VEC (basic_block
,heap
) *blocks
;
3100 /* Same information in a bitmap. */
3101 bitmap block_bitmap
;
3103 /* Vector of inner loops within this loop */
3104 VEC (loop_info
,heap
) *loops
;
3108 bfin_dump_loops (loop_info loops
)
3112 for (loop
= loops
; loop
; loop
= loop
->next
)
3118 fprintf (dump_file
, ";; loop %d: ", loop
->loop_no
);
3120 fprintf (dump_file
, "(bad) ");
3121 fprintf (dump_file
, "{head:%d, depth:%d}", loop
->head
->index
, loop
->depth
);
3123 fprintf (dump_file
, " blocks: [ ");
3124 for (ix
= 0; VEC_iterate (basic_block
, loop
->blocks
, ix
, b
); ix
++)
3125 fprintf (dump_file
, "%d ", b
->index
);
3126 fprintf (dump_file
, "] ");
3128 fprintf (dump_file
, " inner loops: [ ");
3129 for (ix
= 0; VEC_iterate (loop_info
, loop
->loops
, ix
, i
); ix
++)
3130 fprintf (dump_file
, "%d ", i
->loop_no
);
3131 fprintf (dump_file
, "]\n");
3133 fprintf (dump_file
, "\n");
3136 /* Scan the blocks of LOOP (and its inferiors) looking for basic block
3137 BB. Return true, if we find it. */
3140 bfin_bb_in_loop (loop_info loop
, basic_block bb
)
3142 return bitmap_bit_p (loop
->block_bitmap
, bb
->index
);
3145 /* Scan the blocks of LOOP (and its inferiors) looking for uses of
3146 REG. Return true, if we find any. Don't count the loop's loop_end
3147 insn if it matches LOOP_END. */
3150 bfin_scan_loop (loop_info loop
, rtx reg
, rtx loop_end
)
3155 for (ix
= 0; VEC_iterate (basic_block
, loop
->blocks
, ix
, bb
); ix
++)
3159 for (insn
= BB_HEAD (bb
);
3160 insn
!= NEXT_INSN (BB_END (bb
));
3161 insn
= NEXT_INSN (insn
))
3165 if (insn
== loop_end
)
3167 if (reg_mentioned_p (reg
, PATTERN (insn
)))
3174 /* Optimize LOOP. */
3177 bfin_optimize_loop (loop_info loop
)
3181 rtx insn
, init_insn
, last_insn
, nop_insn
;
3182 rtx loop_init
, start_label
, end_label
;
3183 rtx reg_lc0
, reg_lc1
, reg_lt0
, reg_lt1
, reg_lb0
, reg_lb1
;
3185 rtx lc_reg
, lt_reg
, lb_reg
;
3189 int inner_depth
= 0;
3199 fprintf (dump_file
, ";; loop %d bad when found\n", loop
->loop_no
);
3203 /* Every loop contains in its list of inner loops every loop nested inside
3204 it, even if there are intermediate loops. This works because we're doing
3205 a depth-first search here and never visit a loop more than once. */
3206 for (ix
= 0; VEC_iterate (loop_info
, loop
->loops
, ix
, inner
); ix
++)
3208 bfin_optimize_loop (inner
);
3210 if (!inner
->bad
&& inner_depth
< inner
->depth
)
3212 inner_depth
= inner
->depth
;
3214 loop
->clobber_loop0
|= inner
->clobber_loop0
;
3215 loop
->clobber_loop1
|= inner
->clobber_loop1
;
3219 loop
->depth
= inner_depth
+ 1;
3220 if (loop
->depth
> MAX_LOOP_DEPTH
)
3223 fprintf (dump_file
, ";; loop %d too deep\n", loop
->loop_no
);
3227 /* Get the loop iteration register. */
3228 iter_reg
= loop
->iter_reg
;
3230 if (!DPREG_P (iter_reg
))
3233 fprintf (dump_file
, ";; loop %d iteration count NOT in PREG or DREG\n",
3238 /* Check if start_label appears before loop_end and calculate the
3239 offset between them. We calculate the length of instructions
3242 for (insn
= loop
->start_label
;
3243 insn
&& insn
!= loop
->loop_end
;
3244 insn
= NEXT_INSN (insn
))
3246 if (JUMP_P (insn
) && any_condjump_p (insn
) && !optimize_size
)
3248 if (TARGET_CSYNC_ANOMALY
)
3250 else if (TARGET_SPECLD_ANOMALY
)
3253 else if (LABEL_P (insn
))
3255 if (TARGET_CSYNC_ANOMALY
)
3260 length
+= get_attr_length (insn
);
3266 fprintf (dump_file
, ";; loop %d start_label not before loop_end\n",
3271 loop
->length
= length
;
3272 if (loop
->length
> MAX_LOOP_LENGTH
)
3275 fprintf (dump_file
, ";; loop %d too long\n", loop
->loop_no
);
3279 /* Scan all the blocks to make sure they don't use iter_reg. */
3280 if (bfin_scan_loop (loop
, iter_reg
, loop
->loop_end
))
3283 fprintf (dump_file
, ";; loop %d uses iterator\n", loop
->loop_no
);
3287 /* Scan all the insns to see if the loop body clobber
3288 any hardware loop registers. */
3290 reg_lc0
= gen_rtx_REG (SImode
, REG_LC0
);
3291 reg_lc1
= gen_rtx_REG (SImode
, REG_LC1
);
3292 reg_lt0
= gen_rtx_REG (SImode
, REG_LT0
);
3293 reg_lt1
= gen_rtx_REG (SImode
, REG_LT1
);
3294 reg_lb0
= gen_rtx_REG (SImode
, REG_LB0
);
3295 reg_lb1
= gen_rtx_REG (SImode
, REG_LB1
);
3297 for (ix
= 0; VEC_iterate (basic_block
, loop
->blocks
, ix
, bb
); ix
++)
3301 for (insn
= BB_HEAD (bb
);
3302 insn
!= NEXT_INSN (BB_END (bb
));
3303 insn
= NEXT_INSN (insn
))
3308 if (reg_set_p (reg_lc0
, insn
)
3309 || reg_set_p (reg_lt0
, insn
)
3310 || reg_set_p (reg_lb0
, insn
))
3311 loop
->clobber_loop0
= 1;
3313 if (reg_set_p (reg_lc1
, insn
)
3314 || reg_set_p (reg_lt1
, insn
)
3315 || reg_set_p (reg_lb1
, insn
))
3316 loop
->clobber_loop1
|= 1;
3320 if ((loop
->clobber_loop0
&& loop
->clobber_loop1
)
3321 || (loop
->depth
== MAX_LOOP_DEPTH
&& loop
->clobber_loop0
))
3323 loop
->depth
= MAX_LOOP_DEPTH
+ 1;
3325 fprintf (dump_file
, ";; loop %d no loop reg available\n",
3330 /* There should be an instruction before the loop_end instruction
3331 in the same basic block. And the instruction must not be
3333 - CONDITIONAL BRANCH
3337 - Returns (RTS, RTN, etc.) */
3340 last_insn
= PREV_INSN (loop
->loop_end
);
3344 for (; last_insn
!= PREV_INSN (BB_HEAD (bb
));
3345 last_insn
= PREV_INSN (last_insn
))
3346 if (INSN_P (last_insn
))
3349 if (last_insn
!= PREV_INSN (BB_HEAD (bb
)))
3352 if (single_pred_p (bb
)
3353 && single_pred (bb
) != ENTRY_BLOCK_PTR
)
3355 bb
= single_pred (bb
);
3356 last_insn
= BB_END (bb
);
3361 last_insn
= NULL_RTX
;
3369 fprintf (dump_file
, ";; loop %d has no last instruction\n",
3374 if (JUMP_P (last_insn
))
3376 loop_info inner
= bb
->aux
;
3378 && inner
->outer
== loop
3379 && inner
->loop_end
== last_insn
3380 && inner
->depth
== 1)
3381 /* This jump_insn is the exact loop_end of an inner loop
3382 and to be optimized away. So use the inner's last_insn. */
3383 last_insn
= inner
->last_insn
;
3387 fprintf (dump_file
, ";; loop %d has bad last instruction\n",
3392 else if (CALL_P (last_insn
)
3393 || (GET_CODE (PATTERN (last_insn
)) != SEQUENCE
3394 && get_attr_type (last_insn
) == TYPE_SYNC
)
3395 || recog_memoized (last_insn
) == CODE_FOR_return_internal
)
3398 fprintf (dump_file
, ";; loop %d has bad last instruction\n",
3403 if (GET_CODE (PATTERN (last_insn
)) == ASM_INPUT
3404 || asm_noperands (PATTERN (last_insn
)) >= 0
3405 || (GET_CODE (PATTERN (last_insn
)) != SEQUENCE
3406 && get_attr_seq_insns (last_insn
) == SEQ_INSNS_MULTI
))
3408 nop_insn
= emit_insn_after (gen_nop (), last_insn
);
3409 last_insn
= nop_insn
;
3412 loop
->last_insn
= last_insn
;
3414 /* The loop is good for replacement. */
3415 start_label
= loop
->start_label
;
3416 end_label
= gen_label_rtx ();
3417 iter_reg
= loop
->iter_reg
;
3419 if (loop
->depth
== 1 && !loop
->clobber_loop1
)
3424 loop
->clobber_loop1
= 1;
3431 loop
->clobber_loop0
= 1;
3434 /* If iter_reg is a DREG, we need generate an instruction to load
3435 the loop count into LC register. */
3436 if (D_REGNO_P (REGNO (iter_reg
)))
3438 init_insn
= gen_movsi (lc_reg
, iter_reg
);
3439 loop_init
= gen_lsetup_without_autoinit (lt_reg
, start_label
,
3443 else if (P_REGNO_P (REGNO (iter_reg
)))
3445 init_insn
= NULL_RTX
;
3446 loop_init
= gen_lsetup_with_autoinit (lt_reg
, start_label
,
3453 loop
->init
= init_insn
;
3454 loop
->end_label
= end_label
;
3455 loop
->loop_init
= loop_init
;
3459 fprintf (dump_file
, ";; replacing loop %d initializer with\n",
3461 print_rtl_single (dump_file
, loop
->loop_init
);
3462 fprintf (dump_file
, ";; replacing loop %d terminator with\n",
3464 print_rtl_single (dump_file
, loop
->loop_end
);
3469 if (loop
->init
!= NULL_RTX
)
3470 emit_insn (loop
->init
);
3471 emit_insn(loop
->loop_init
);
3472 emit_label (loop
->start_label
);
3477 emit_insn_after (seq
, BB_END (loop
->predecessor
));
3478 delete_insn (loop
->loop_end
);
3480 /* Insert the loop end label before the last instruction of the loop. */
3481 emit_label_before (loop
->end_label
, loop
->last_insn
);
3488 fprintf (dump_file
, ";; loop %d is bad\n", loop
->loop_no
);
3492 if (DPREG_P (loop
->iter_reg
))
3494 /* If loop->iter_reg is a DREG or PREG, we can split it here
3495 without scratch register. */
3498 emit_insn_before (gen_addsi3 (loop
->iter_reg
,
3503 emit_insn_before (gen_cmpsi (loop
->iter_reg
, const0_rtx
),
3506 insn
= emit_jump_insn_before (gen_bne (loop
->start_label
),
3509 JUMP_LABEL (insn
) = loop
->start_label
;
3510 LABEL_NUSES (loop
->start_label
)++;
3511 delete_insn (loop
->loop_end
);
3515 /* Called from bfin_reorg_loops when a potential loop end is found. LOOP is
3516 a newly set up structure describing the loop, it is this function's
3517 responsibility to fill most of it. TAIL_BB and TAIL_INSN point to the
3518 loop_end insn and its enclosing basic block. */
3521 bfin_discover_loop (loop_info loop
, basic_block tail_bb
, rtx tail_insn
)
3525 VEC (basic_block
,heap
) *works
= VEC_alloc (basic_block
,heap
,20);
3527 loop
->tail
= tail_bb
;
3528 loop
->head
= BRANCH_EDGE (tail_bb
)->dest
;
3529 loop
->successor
= FALLTHRU_EDGE (tail_bb
)->dest
;
3530 loop
->predecessor
= NULL
;
3531 loop
->loop_end
= tail_insn
;
3532 loop
->last_insn
= NULL_RTX
;
3533 loop
->iter_reg
= SET_DEST (XVECEXP (PATTERN (tail_insn
), 0, 1));
3534 loop
->depth
= loop
->length
= 0;
3536 loop
->clobber_loop0
= loop
->clobber_loop1
= 0;
3540 loop
->init
= loop
->loop_init
= NULL_RTX
;
3541 loop
->start_label
= XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (tail_insn
), 0, 0)), 1), 0);
3542 loop
->end_label
= NULL_RTX
;
3545 VEC_safe_push (basic_block
, heap
, works
, loop
->head
);
3547 while (VEC_iterate (basic_block
, works
, dwork
++, bb
))
3551 if (bb
== EXIT_BLOCK_PTR
)
3553 /* We've reached the exit block. The loop must be bad. */
3556 ";; Loop is bad - reached exit block while scanning\n");
3561 if (bitmap_bit_p (loop
->block_bitmap
, bb
->index
))
3564 /* We've not seen this block before. Add it to the loop's
3565 list and then add each successor to the work list. */
3567 VEC_safe_push (basic_block
, heap
, loop
->blocks
, bb
);
3568 bitmap_set_bit (loop
->block_bitmap
, bb
->index
);
3572 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
3574 basic_block succ
= EDGE_SUCC (bb
, ei
.index
)->dest
;
3575 if (!REGNO_REG_SET_P (succ
->il
.rtl
->global_live_at_start
,
3576 REGNO (loop
->iter_reg
)))
3578 if (!VEC_space (basic_block
, works
, 1))
3582 VEC_block_remove (basic_block
, works
, 0, dwork
);
3586 VEC_reserve (basic_block
, heap
, works
, 1);
3588 VEC_quick_push (basic_block
, works
, succ
);
3595 /* Make sure we only have one entry point. */
3596 if (EDGE_COUNT (loop
->head
->preds
) == 2)
3598 loop
->predecessor
= EDGE_PRED (loop
->head
, 0)->src
;
3599 if (loop
->predecessor
== loop
->tail
)
3600 /* We wanted the other predecessor. */
3601 loop
->predecessor
= EDGE_PRED (loop
->head
, 1)->src
;
3603 /* We can only place a loop insn on a fall through edge of a
3604 single exit block. */
3605 if (EDGE_COUNT (loop
->predecessor
->succs
) != 1
3606 || !(EDGE_SUCC (loop
->predecessor
, 0)->flags
& EDGE_FALLTHRU
)
3607 /* If loop->predecessor is in loop, loop->head is not really
3608 the head of the loop. */
3609 || bfin_bb_in_loop (loop
, loop
->predecessor
))
3610 loop
->predecessor
= NULL
;
3613 if (loop
->predecessor
== NULL
)
3616 fprintf (dump_file
, ";; loop has bad predecessor\n");
3621 #ifdef ENABLE_CHECKING
3622 /* Make sure nothing jumps into this loop. This shouldn't happen as we
3623 wouldn't have generated the counted loop patterns in such a case.
3624 However, this test must be done after the test above to detect loops
3625 with invalid headers. */
3627 for (dwork
= 0; VEC_iterate (basic_block
, loop
->blocks
, dwork
, bb
); dwork
++)
3631 if (bb
== loop
->head
)
3633 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
3635 basic_block pred
= EDGE_PRED (bb
, ei
.index
)->src
;
3636 if (!bfin_bb_in_loop (loop
, pred
))
3641 VEC_free (basic_block
, heap
, works
);
3645 bfin_reorg_loops (FILE *dump_file
)
3647 bitmap_obstack stack
;
3650 loop_info loops
= NULL
;
3654 bitmap_obstack_initialize (&stack
);
3656 /* Find all the possible loop tails. This means searching for every
3657 loop_end instruction. For each one found, create a loop_info
3658 structure and add the head block to the work list. */
3661 rtx tail
= BB_END (bb
);
3663 while (GET_CODE (tail
) == NOTE
)
3664 tail
= PREV_INSN (tail
);
3668 if (INSN_P (tail
) && recog_memoized (tail
) == CODE_FOR_loop_end
)
3670 /* A possible loop end */
3672 loop
= XNEW (struct loop_info
);
3675 loop
->loop_no
= nloops
++;
3676 loop
->blocks
= VEC_alloc (basic_block
, heap
, 20);
3677 loop
->block_bitmap
= BITMAP_ALLOC (&stack
);
3682 fprintf (dump_file
, ";; potential loop %d ending at\n",
3684 print_rtl_single (dump_file
, tail
);
3687 bfin_discover_loop (loop
, bb
, tail
);
3691 tmp_bitmap
= BITMAP_ALLOC (&stack
);
3692 /* Compute loop nestings. */
3693 for (loop
= loops
; loop
; loop
= loop
->next
)
3699 for (other
= loop
->next
; other
; other
= other
->next
)
3704 bitmap_and (tmp_bitmap
, other
->block_bitmap
, loop
->block_bitmap
);
3705 if (bitmap_empty_p (tmp_bitmap
))
3707 if (bitmap_equal_p (tmp_bitmap
, other
->block_bitmap
))
3709 other
->outer
= loop
;
3710 VEC_safe_push (loop_info
, heap
, loop
->loops
, other
);
3712 else if (bitmap_equal_p (tmp_bitmap
, loop
->block_bitmap
))
3714 loop
->outer
= other
;
3715 VEC_safe_push (loop_info
, heap
, other
->loops
, loop
);
3719 loop
->bad
= other
->bad
= 1;
3723 BITMAP_FREE (tmp_bitmap
);
3727 fprintf (dump_file
, ";; All loops found:\n\n");
3728 bfin_dump_loops (loops
);
3731 /* Now apply the optimizations. */
3732 for (loop
= loops
; loop
; loop
= loop
->next
)
3733 bfin_optimize_loop (loop
);
3737 fprintf (dump_file
, ";; After hardware loops optimization:\n\n");
3738 bfin_dump_loops (loops
);
3741 /* Free up the loop structures */
3746 VEC_free (loop_info
, heap
, loop
->loops
);
3747 VEC_free (basic_block
, heap
, loop
->blocks
);
3748 BITMAP_FREE (loop
->block_bitmap
);
3753 print_rtl (dump_file
, get_insns ());
3759 /* Possibly generate a SEQUENCE out of three insns found in SLOT.
3760 Returns true if we modified the insn chain, false otherwise. */
3762 gen_one_bundle (rtx slot
[3])
3766 gcc_assert (slot
[1] != NULL_RTX
);
3768 /* Verify that we really can do the multi-issue. */
3771 rtx t
= NEXT_INSN (slot
[0]);
3772 while (t
!= slot
[1])
3774 if (GET_CODE (t
) != NOTE
3775 || NOTE_LINE_NUMBER (t
) != NOTE_INSN_DELETED
)
3782 rtx t
= NEXT_INSN (slot
[1]);
3783 while (t
!= slot
[2])
3785 if (GET_CODE (t
) != NOTE
3786 || NOTE_LINE_NUMBER (t
) != NOTE_INSN_DELETED
)
3792 if (slot
[0] == NULL_RTX
)
3793 slot
[0] = emit_insn_before (gen_mnop (), slot
[1]);
3794 if (slot
[2] == NULL_RTX
)
3795 slot
[2] = emit_insn_after (gen_nop (), slot
[1]);
3797 /* Avoid line number information being printed inside one bundle. */
3798 if (INSN_LOCATOR (slot
[1])
3799 && INSN_LOCATOR (slot
[1]) != INSN_LOCATOR (slot
[0]))
3800 INSN_LOCATOR (slot
[1]) = INSN_LOCATOR (slot
[0]);
3801 if (INSN_LOCATOR (slot
[2])
3802 && INSN_LOCATOR (slot
[2]) != INSN_LOCATOR (slot
[0]))
3803 INSN_LOCATOR (slot
[2]) = INSN_LOCATOR (slot
[0]);
3805 /* Terminate them with "|| " instead of ";" in the output. */
3806 PUT_MODE (slot
[0], SImode
);
3807 PUT_MODE (slot
[1], SImode
);
3809 /* This is a cheat to avoid emit_insn's special handling of SEQUENCEs.
3810 Generating a PARALLEL first and changing its code later is the
3811 easiest way to emit a SEQUENCE insn. */
3812 bundle
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (3, slot
[0], slot
[1], slot
[2]));
3813 emit_insn_before (bundle
, slot
[0]);
3814 remove_insn (slot
[0]);
3815 remove_insn (slot
[1]);
3816 remove_insn (slot
[2]);
3817 PUT_CODE (bundle
, SEQUENCE
);
3822 /* Go through all insns, and use the information generated during scheduling
3823 to generate SEQUENCEs to represent bundles of instructions issued
3827 bfin_gen_bundles (void)
3836 slot
[0] = slot
[1] = slot
[2] = NULL_RTX
;
3837 for (insn
= BB_HEAD (bb
);; insn
= next
)
3842 if (get_attr_type (insn
) == TYPE_DSP32
)
3844 else if (slot
[1] == NULL_RTX
)
3851 next
= NEXT_INSN (insn
);
3852 while (next
&& insn
!= BB_END (bb
)
3854 && GET_CODE (PATTERN (next
)) != USE
3855 && GET_CODE (PATTERN (next
)) != CLOBBER
))
3858 next
= NEXT_INSN (insn
);
3861 /* BB_END can change due to emitting extra NOPs, so check here. */
3862 at_end
= insn
== BB_END (bb
);
3863 if (at_end
|| GET_MODE (next
) == TImode
)
3866 || !gen_one_bundle (slot
))
3867 && slot
[0] != NULL_RTX
)
3869 rtx pat
= PATTERN (slot
[0]);
3870 if (GET_CODE (pat
) == SET
3871 && GET_CODE (SET_SRC (pat
)) == UNSPEC
3872 && XINT (SET_SRC (pat
), 1) == UNSPEC_32BIT
)
3874 SET_SRC (pat
) = XVECEXP (SET_SRC (pat
), 0, 0);
3875 INSN_CODE (slot
[0]) = -1;
3879 slot
[0] = slot
[1] = slot
[2] = NULL_RTX
;
3887 /* Return an insn type for INSN that can be used by the caller for anomaly
3888 workarounds. This differs from plain get_attr_type in that it handles
3891 static enum attr_type
3892 type_for_anomaly (rtx insn
)
3894 rtx pat
= PATTERN (insn
);
3895 if (GET_CODE (pat
) == SEQUENCE
)
3898 t
= get_attr_type (XVECEXP (pat
, 0, 1));
3901 t
= get_attr_type (XVECEXP (pat
, 0, 2));
3907 return get_attr_type (insn
);
3910 /* Return nonzero if INSN contains any loads that may trap. It handles
3911 SEQUENCEs correctly. */
3914 trapping_loads_p (rtx insn
)
3916 rtx pat
= PATTERN (insn
);
3917 if (GET_CODE (pat
) == SEQUENCE
)
3920 t
= get_attr_type (XVECEXP (pat
, 0, 1));
3921 if (t
== TYPE_MCLD
&& may_trap_p (SET_SRC (XVECEXP (pat
, 0, 1))))
3923 t
= get_attr_type (XVECEXP (pat
, 0, 2));
3924 if (t
== TYPE_MCLD
&& may_trap_p (SET_SRC (XVECEXP (pat
, 0, 2))))
3929 return may_trap_p (SET_SRC (single_set (insn
)));
3932 /* We use the machine specific reorg pass for emitting CSYNC instructions
3933 after conditional branches as needed.
3935 The Blackfin is unusual in that a code sequence like
3938 may speculatively perform the load even if the condition isn't true. This
3939 happens for a branch that is predicted not taken, because the pipeline
3940 isn't flushed or stalled, so the early stages of the following instructions,
3941 which perform the memory reference, are allowed to execute before the
3942 jump condition is evaluated.
3943 Therefore, we must insert additional instructions in all places where this
3944 could lead to incorrect behavior. The manual recommends CSYNC, while
3945 VDSP seems to use NOPs (even though its corresponding compiler option is
3948 When optimizing for speed, we emit NOPs, which seems faster than a CSYNC.
3949 When optimizing for size, we turn the branch into a predicted taken one.
3950 This may be slower due to mispredicts, but saves code size. */
3955 rtx insn
, last_condjump
= NULL_RTX
;
3956 int cycles_since_jump
= INT_MAX
;
3958 /* We are freeing block_for_insn in the toplev to keep compatibility
3959 with old MDEP_REORGS that are not CFG based. Recompute it now. */
3960 compute_bb_for_insn ();
3962 if (bfin_flag_schedule_insns2
)
3964 splitting_for_sched
= 1;
3965 split_all_insns (0);
3966 splitting_for_sched
= 0;
3968 update_life_info (NULL
, UPDATE_LIFE_GLOBAL_RM_NOTES
, PROP_DEATH_NOTES
);
3970 timevar_push (TV_SCHED2
);
3972 timevar_pop (TV_SCHED2
);
3974 /* Examine the schedule and insert nops as necessary for 64 bit parallel
3976 bfin_gen_bundles ();
3979 /* Doloop optimization */
3980 if (cfun
->machine
->has_hardware_loops
)
3981 bfin_reorg_loops (dump_file
);
3983 if (! TARGET_SPECLD_ANOMALY
&& ! TARGET_CSYNC_ANOMALY
)
3986 /* First pass: find predicted-false branches; if something after them
3987 needs nops, insert them or change the branch to predict true. */
3988 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
3992 if (NOTE_P (insn
) || BARRIER_P (insn
) || LABEL_P (insn
))
3995 pat
= PATTERN (insn
);
3996 if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
3997 || GET_CODE (pat
) == ASM_INPUT
|| GET_CODE (pat
) == ADDR_VEC
3998 || GET_CODE (pat
) == ADDR_DIFF_VEC
|| asm_noperands (pat
) >= 0)
4003 if (any_condjump_p (insn
)
4004 && ! cbranch_predicted_taken_p (insn
))
4006 last_condjump
= insn
;
4007 cycles_since_jump
= 0;
4010 cycles_since_jump
= INT_MAX
;
4012 else if (INSN_P (insn
))
4014 enum attr_type type
= type_for_anomaly (insn
);
4015 int delay_needed
= 0;
4016 if (cycles_since_jump
< INT_MAX
)
4017 cycles_since_jump
++;
4019 if (type
== TYPE_MCLD
&& TARGET_SPECLD_ANOMALY
)
4021 if (trapping_loads_p (insn
))
4024 else if (type
== TYPE_SYNC
&& TARGET_CSYNC_ANOMALY
)
4027 if (delay_needed
> cycles_since_jump
)
4031 rtx
*op
= recog_data
.operand
;
4033 delay_needed
-= cycles_since_jump
;
4035 extract_insn (last_condjump
);
4038 pat
= gen_cbranch_predicted_taken (op
[0], op
[1], op
[2],
4040 cycles_since_jump
= INT_MAX
;
4043 /* Do not adjust cycles_since_jump in this case, so that
4044 we'll increase the number of NOPs for a subsequent insn
4046 pat
= gen_cbranch_with_nops (op
[0], op
[1], op
[2], op
[3],
4047 GEN_INT (delay_needed
));
4048 PATTERN (last_condjump
) = pat
;
4049 INSN_CODE (last_condjump
) = recog (pat
, insn
, &num_clobbers
);
4053 /* Second pass: for predicted-true branches, see if anything at the
4054 branch destination needs extra nops. */
4055 if (! TARGET_CSYNC_ANOMALY
)
4058 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
4061 && any_condjump_p (insn
)
4062 && (INSN_CODE (insn
) == CODE_FOR_cbranch_predicted_taken
4063 || cbranch_predicted_taken_p (insn
)))
4065 rtx target
= JUMP_LABEL (insn
);
4067 cycles_since_jump
= 0;
4068 for (; target
&& cycles_since_jump
< 3; target
= NEXT_INSN (target
))
4072 if (NOTE_P (target
) || BARRIER_P (target
) || LABEL_P (target
))
4075 pat
= PATTERN (target
);
4076 if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
4077 || GET_CODE (pat
) == ASM_INPUT
|| GET_CODE (pat
) == ADDR_VEC
4078 || GET_CODE (pat
) == ADDR_DIFF_VEC
|| asm_noperands (pat
) >= 0)
4081 if (INSN_P (target
))
4083 enum attr_type type
= type_for_anomaly (target
);
4084 int delay_needed
= 0;
4085 if (cycles_since_jump
< INT_MAX
)
4086 cycles_since_jump
++;
4088 if (type
== TYPE_SYNC
&& TARGET_CSYNC_ANOMALY
)
4091 if (delay_needed
> cycles_since_jump
)
4093 rtx prev
= prev_real_insn (label
);
4094 delay_needed
-= cycles_since_jump
;
4096 fprintf (dump_file
, "Adding %d nops after %d\n",
4097 delay_needed
, INSN_UID (label
));
4099 && INSN_CODE (prev
) == CODE_FOR_cbranch_with_nops
)
4106 "Reducing nops on insn %d.\n",
4109 x
= XVECEXP (x
, 0, 1);
4110 v
= INTVAL (XVECEXP (x
, 0, 0)) - delay_needed
;
4111 XVECEXP (x
, 0, 0) = GEN_INT (v
);
4113 while (delay_needed
-- > 0)
4114 emit_insn_after (gen_nop (), label
);
4122 if (bfin_flag_var_tracking
)
4124 timevar_push (TV_VAR_TRACKING
);
4125 variable_tracking_main ();
4126 timevar_pop (TV_VAR_TRACKING
);
4130 /* Handle interrupt_handler, exception_handler and nmi_handler function
4131 attributes; arguments as in struct attribute_spec.handler. */
4134 handle_int_attribute (tree
*node
, tree name
,
4135 tree args ATTRIBUTE_UNUSED
,
4136 int flags ATTRIBUTE_UNUSED
,
4140 if (TREE_CODE (x
) == FUNCTION_DECL
)
4143 if (TREE_CODE (x
) != FUNCTION_TYPE
)
4145 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
4146 IDENTIFIER_POINTER (name
));
4147 *no_add_attrs
= true;
4149 else if (funkind (x
) != SUBROUTINE
)
4150 error ("multiple function type attributes specified");
4155 /* Return 0 if the attributes for two types are incompatible, 1 if they
4156 are compatible, and 2 if they are nearly compatible (which causes a
4157 warning to be generated). */
4160 bfin_comp_type_attributes (tree type1
, tree type2
)
4162 e_funkind kind1
, kind2
;
4164 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
4167 kind1
= funkind (type1
);
4168 kind2
= funkind (type2
);
4173 /* Check for mismatched modifiers */
4174 if (!lookup_attribute ("nesting", TYPE_ATTRIBUTES (type1
))
4175 != !lookup_attribute ("nesting", TYPE_ATTRIBUTES (type2
)))
4178 if (!lookup_attribute ("saveall", TYPE_ATTRIBUTES (type1
))
4179 != !lookup_attribute ("saveall", TYPE_ATTRIBUTES (type2
)))
4182 if (!lookup_attribute ("kspisusp", TYPE_ATTRIBUTES (type1
))
4183 != !lookup_attribute ("kspisusp", TYPE_ATTRIBUTES (type2
)))
4186 if (!lookup_attribute ("longcall", TYPE_ATTRIBUTES (type1
))
4187 != !lookup_attribute ("longcall", TYPE_ATTRIBUTES (type2
)))
4193 /* Handle a "longcall" or "shortcall" attribute; arguments as in
4194 struct attribute_spec.handler. */
4197 bfin_handle_longcall_attribute (tree
*node
, tree name
,
4198 tree args ATTRIBUTE_UNUSED
,
4199 int flags ATTRIBUTE_UNUSED
,
4202 if (TREE_CODE (*node
) != FUNCTION_TYPE
4203 && TREE_CODE (*node
) != FIELD_DECL
4204 && TREE_CODE (*node
) != TYPE_DECL
)
4206 warning (OPT_Wattributes
, "`%s' attribute only applies to functions",
4207 IDENTIFIER_POINTER (name
));
4208 *no_add_attrs
= true;
4211 if ((strcmp (IDENTIFIER_POINTER (name
), "longcall") == 0
4212 && lookup_attribute ("shortcall", TYPE_ATTRIBUTES (*node
)))
4213 || (strcmp (IDENTIFIER_POINTER (name
), "shortcall") == 0
4214 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (*node
))))
4216 warning (OPT_Wattributes
,
4217 "can't apply both longcall and shortcall attributes to the same function");
4218 *no_add_attrs
= true;
4224 /* Table of valid machine attributes. */
4225 const struct attribute_spec bfin_attribute_table
[] =
4227 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4228 { "interrupt_handler", 0, 0, false, true, true, handle_int_attribute
},
4229 { "exception_handler", 0, 0, false, true, true, handle_int_attribute
},
4230 { "nmi_handler", 0, 0, false, true, true, handle_int_attribute
},
4231 { "nesting", 0, 0, false, true, true, NULL
},
4232 { "kspisusp", 0, 0, false, true, true, NULL
},
4233 { "saveall", 0, 0, false, true, true, NULL
},
4234 { "longcall", 0, 0, false, true, true, bfin_handle_longcall_attribute
},
4235 { "shortcall", 0, 0, false, true, true, bfin_handle_longcall_attribute
},
4236 { NULL
, 0, 0, false, false, false, NULL
}
4239 /* Implementation of TARGET_ASM_INTEGER. When using FD-PIC, we need to
4240 tell the assembler to generate pointers to function descriptors in
4244 bfin_assemble_integer (rtx value
, unsigned int size
, int aligned_p
)
4246 if (TARGET_FDPIC
&& size
== UNITS_PER_WORD
)
4248 if (GET_CODE (value
) == SYMBOL_REF
4249 && SYMBOL_REF_FUNCTION_P (value
))
4251 fputs ("\t.picptr\tfuncdesc(", asm_out_file
);
4252 output_addr_const (asm_out_file
, value
);
4253 fputs (")\n", asm_out_file
);
4258 /* We've set the unaligned SI op to NULL, so we always have to
4259 handle the unaligned case here. */
4260 assemble_integer_with_op ("\t.4byte\t", value
);
4264 return default_assemble_integer (value
, size
, aligned_p
);
4267 /* Output the assembler code for a thunk function. THUNK_DECL is the
4268 declaration for the thunk function itself, FUNCTION is the decl for
4269 the target function. DELTA is an immediate constant offset to be
4270 added to THIS. If VCALL_OFFSET is nonzero, the word at
4271 *(*this + vcall_offset) should be added to THIS. */
4274 bfin_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED
,
4275 tree thunk ATTRIBUTE_UNUSED
, HOST_WIDE_INT delta
,
4276 HOST_WIDE_INT vcall_offset
, tree function
)
4279 /* The this parameter is passed as the first argument. */
4280 rtx
this = gen_rtx_REG (Pmode
, REG_R0
);
4282 /* Adjust the this parameter by a fixed constant. */
4286 if (delta
>= -64 && delta
<= 63)
4288 xops
[0] = GEN_INT (delta
);
4289 output_asm_insn ("%1 += %0;", xops
);
4291 else if (delta
>= -128 && delta
< -64)
4293 xops
[0] = GEN_INT (delta
+ 64);
4294 output_asm_insn ("%1 += -64; %1 += %0;", xops
);
4296 else if (delta
> 63 && delta
<= 126)
4298 xops
[0] = GEN_INT (delta
- 63);
4299 output_asm_insn ("%1 += 63; %1 += %0;", xops
);
4303 xops
[0] = GEN_INT (delta
);
4304 output_asm_insn ("r3.l = %h0; r3.h = %d0; %1 = %1 + r3;", xops
);
4308 /* Adjust the this parameter by a value stored in the vtable. */
4311 rtx p2tmp
= gen_rtx_REG (Pmode
, REG_P2
);
4312 rtx tmp
= gen_rtx_REG (Pmode
, REG_R2
);
4316 output_asm_insn ("%2 = r0; %2 = [%2];", xops
);
4318 /* Adjust the this parameter. */
4319 xops
[0] = gen_rtx_MEM (Pmode
, plus_constant (p2tmp
, vcall_offset
));
4320 if (!memory_operand (xops
[0], Pmode
))
4322 rtx tmp2
= gen_rtx_REG (Pmode
, REG_P1
);
4323 xops
[0] = GEN_INT (vcall_offset
);
4325 output_asm_insn ("%h1 = %h0; %d1 = %d0; %2 = %2 + %1", xops
);
4326 xops
[0] = gen_rtx_MEM (Pmode
, p2tmp
);
4329 output_asm_insn ("%1 = %0; %2 = %2 + %1;", xops
);
4332 xops
[0] = XEXP (DECL_RTL (function
), 0);
4333 if (1 || !flag_pic
|| (*targetm
.binds_local_p
) (function
))
4334 output_asm_insn ("jump.l\t%P0", xops
);
4337 /* Codes for all the Blackfin builtins. */
4342 BFIN_BUILTIN_COMPOSE_2X16
,
4343 BFIN_BUILTIN_EXTRACTLO
,
4344 BFIN_BUILTIN_EXTRACTHI
,
4346 BFIN_BUILTIN_SSADD_2X16
,
4347 BFIN_BUILTIN_SSSUB_2X16
,
4348 BFIN_BUILTIN_SSADDSUB_2X16
,
4349 BFIN_BUILTIN_SSSUBADD_2X16
,
4350 BFIN_BUILTIN_MULT_2X16
,
4351 BFIN_BUILTIN_MULTR_2X16
,
4352 BFIN_BUILTIN_NEG_2X16
,
4353 BFIN_BUILTIN_ABS_2X16
,
4354 BFIN_BUILTIN_MIN_2X16
,
4355 BFIN_BUILTIN_MAX_2X16
,
4357 BFIN_BUILTIN_SSADD_1X16
,
4358 BFIN_BUILTIN_SSSUB_1X16
,
4359 BFIN_BUILTIN_MULT_1X16
,
4360 BFIN_BUILTIN_MULTR_1X16
,
4361 BFIN_BUILTIN_NORM_1X16
,
4362 BFIN_BUILTIN_NEG_1X16
,
4363 BFIN_BUILTIN_ABS_1X16
,
4364 BFIN_BUILTIN_MIN_1X16
,
4365 BFIN_BUILTIN_MAX_1X16
,
4367 BFIN_BUILTIN_DIFFHL_2X16
,
4368 BFIN_BUILTIN_DIFFLH_2X16
,
4370 BFIN_BUILTIN_SSADD_1X32
,
4371 BFIN_BUILTIN_SSSUB_1X32
,
4372 BFIN_BUILTIN_NORM_1X32
,
4373 BFIN_BUILTIN_NEG_1X32
,
4374 BFIN_BUILTIN_MIN_1X32
,
4375 BFIN_BUILTIN_MAX_1X32
,
4376 BFIN_BUILTIN_MULT_1X32
,
4378 BFIN_BUILTIN_MULHISILL
,
4379 BFIN_BUILTIN_MULHISILH
,
4380 BFIN_BUILTIN_MULHISIHL
,
4381 BFIN_BUILTIN_MULHISIHH
,
4383 BFIN_BUILTIN_LSHIFT_1X16
,
4384 BFIN_BUILTIN_LSHIFT_2X16
,
4385 BFIN_BUILTIN_SSASHIFT_1X16
,
4386 BFIN_BUILTIN_SSASHIFT_2X16
,
4388 BFIN_BUILTIN_CPLX_MUL_16
,
4389 BFIN_BUILTIN_CPLX_MAC_16
,
4390 BFIN_BUILTIN_CPLX_MSU_16
,
4395 #define def_builtin(NAME, TYPE, CODE) \
4397 add_builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
4401 /* Set up all builtin functions for this target. */
4403 bfin_init_builtins (void)
4405 tree V2HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V2HImode
);
4406 tree void_ftype_void
4407 = build_function_type (void_type_node
, void_list_node
);
4408 tree short_ftype_short
4409 = build_function_type_list (short_integer_type_node
, short_integer_type_node
,
4411 tree short_ftype_int_int
4412 = build_function_type_list (short_integer_type_node
, integer_type_node
,
4413 integer_type_node
, NULL_TREE
);
4414 tree int_ftype_int_int
4415 = build_function_type_list (integer_type_node
, integer_type_node
,
4416 integer_type_node
, NULL_TREE
);
4418 = build_function_type_list (integer_type_node
, integer_type_node
,
4420 tree short_ftype_int
4421 = build_function_type_list (short_integer_type_node
, integer_type_node
,
4423 tree int_ftype_v2hi_v2hi
4424 = build_function_type_list (integer_type_node
, V2HI_type_node
,
4425 V2HI_type_node
, NULL_TREE
);
4426 tree v2hi_ftype_v2hi_v2hi
4427 = build_function_type_list (V2HI_type_node
, V2HI_type_node
,
4428 V2HI_type_node
, NULL_TREE
);
4429 tree v2hi_ftype_v2hi_v2hi_v2hi
4430 = build_function_type_list (V2HI_type_node
, V2HI_type_node
,
4431 V2HI_type_node
, V2HI_type_node
, NULL_TREE
);
4432 tree v2hi_ftype_int_int
4433 = build_function_type_list (V2HI_type_node
, integer_type_node
,
4434 integer_type_node
, NULL_TREE
);
4435 tree v2hi_ftype_v2hi_int
4436 = build_function_type_list (V2HI_type_node
, V2HI_type_node
,
4437 integer_type_node
, NULL_TREE
);
4438 tree int_ftype_short_short
4439 = build_function_type_list (integer_type_node
, short_integer_type_node
,
4440 short_integer_type_node
, NULL_TREE
);
4441 tree v2hi_ftype_v2hi
4442 = build_function_type_list (V2HI_type_node
, V2HI_type_node
, NULL_TREE
);
4443 tree short_ftype_v2hi
4444 = build_function_type_list (short_integer_type_node
, V2HI_type_node
,
4447 /* Add the remaining MMX insns with somewhat more complicated types. */
4448 def_builtin ("__builtin_bfin_csync", void_ftype_void
, BFIN_BUILTIN_CSYNC
);
4449 def_builtin ("__builtin_bfin_ssync", void_ftype_void
, BFIN_BUILTIN_SSYNC
);
4451 def_builtin ("__builtin_bfin_compose_2x16", v2hi_ftype_int_int
,
4452 BFIN_BUILTIN_COMPOSE_2X16
);
4453 def_builtin ("__builtin_bfin_extract_hi", short_ftype_v2hi
,
4454 BFIN_BUILTIN_EXTRACTHI
);
4455 def_builtin ("__builtin_bfin_extract_lo", short_ftype_v2hi
,
4456 BFIN_BUILTIN_EXTRACTLO
);
4458 def_builtin ("__builtin_bfin_min_fr2x16", v2hi_ftype_v2hi_v2hi
,
4459 BFIN_BUILTIN_MIN_2X16
);
4460 def_builtin ("__builtin_bfin_max_fr2x16", v2hi_ftype_v2hi_v2hi
,
4461 BFIN_BUILTIN_MAX_2X16
);
4463 def_builtin ("__builtin_bfin_add_fr2x16", v2hi_ftype_v2hi_v2hi
,
4464 BFIN_BUILTIN_SSADD_2X16
);
4465 def_builtin ("__builtin_bfin_sub_fr2x16", v2hi_ftype_v2hi_v2hi
,
4466 BFIN_BUILTIN_SSSUB_2X16
);
4467 def_builtin ("__builtin_bfin_dspaddsubsat", v2hi_ftype_v2hi_v2hi
,
4468 BFIN_BUILTIN_SSADDSUB_2X16
);
4469 def_builtin ("__builtin_bfin_dspsubaddsat", v2hi_ftype_v2hi_v2hi
,
4470 BFIN_BUILTIN_SSSUBADD_2X16
);
4471 def_builtin ("__builtin_bfin_mult_fr2x16", v2hi_ftype_v2hi_v2hi
,
4472 BFIN_BUILTIN_MULT_2X16
);
4473 def_builtin ("__builtin_bfin_multr_fr2x16", v2hi_ftype_v2hi_v2hi
,
4474 BFIN_BUILTIN_MULTR_2X16
);
4475 def_builtin ("__builtin_bfin_negate_fr2x16", v2hi_ftype_v2hi
,
4476 BFIN_BUILTIN_NEG_2X16
);
4477 def_builtin ("__builtin_bfin_abs_fr2x16", v2hi_ftype_v2hi
,
4478 BFIN_BUILTIN_ABS_2X16
);
4480 def_builtin ("__builtin_bfin_add_fr1x16", short_ftype_int_int
,
4481 BFIN_BUILTIN_SSADD_1X16
);
4482 def_builtin ("__builtin_bfin_sub_fr1x16", short_ftype_int_int
,
4483 BFIN_BUILTIN_SSSUB_1X16
);
4484 def_builtin ("__builtin_bfin_mult_fr1x16", short_ftype_int_int
,
4485 BFIN_BUILTIN_MULT_1X16
);
4486 def_builtin ("__builtin_bfin_multr_fr1x16", short_ftype_int_int
,
4487 BFIN_BUILTIN_MULTR_1X16
);
4488 def_builtin ("__builtin_bfin_negate_fr1x16", short_ftype_short
,
4489 BFIN_BUILTIN_NEG_1X16
);
4490 def_builtin ("__builtin_bfin_abs_fr1x16", short_ftype_short
,
4491 BFIN_BUILTIN_ABS_1X16
);
4492 def_builtin ("__builtin_bfin_norm_fr1x16", short_ftype_int
,
4493 BFIN_BUILTIN_NORM_1X16
);
4495 def_builtin ("__builtin_bfin_diff_hl_fr2x16", short_ftype_v2hi
,
4496 BFIN_BUILTIN_DIFFHL_2X16
);
4497 def_builtin ("__builtin_bfin_diff_lh_fr2x16", short_ftype_v2hi
,
4498 BFIN_BUILTIN_DIFFLH_2X16
);
4500 def_builtin ("__builtin_bfin_mulhisill", int_ftype_v2hi_v2hi
,
4501 BFIN_BUILTIN_MULHISILL
);
4502 def_builtin ("__builtin_bfin_mulhisihl", int_ftype_v2hi_v2hi
,
4503 BFIN_BUILTIN_MULHISIHL
);
4504 def_builtin ("__builtin_bfin_mulhisilh", int_ftype_v2hi_v2hi
,
4505 BFIN_BUILTIN_MULHISILH
);
4506 def_builtin ("__builtin_bfin_mulhisihh", int_ftype_v2hi_v2hi
,
4507 BFIN_BUILTIN_MULHISIHH
);
4509 def_builtin ("__builtin_bfin_add_fr1x32", int_ftype_int_int
,
4510 BFIN_BUILTIN_SSADD_1X32
);
4511 def_builtin ("__builtin_bfin_sub_fr1x32", int_ftype_int_int
,
4512 BFIN_BUILTIN_SSSUB_1X32
);
4513 def_builtin ("__builtin_bfin_negate_fr1x32", int_ftype_int
,
4514 BFIN_BUILTIN_NEG_1X32
);
4515 def_builtin ("__builtin_bfin_norm_fr1x32", short_ftype_int
,
4516 BFIN_BUILTIN_NORM_1X32
);
4517 def_builtin ("__builtin_bfin_mult_fr1x32", int_ftype_short_short
,
4518 BFIN_BUILTIN_MULT_1X32
);
4521 def_builtin ("__builtin_bfin_shl_fr1x16", short_ftype_int_int
,
4522 BFIN_BUILTIN_SSASHIFT_1X16
);
4523 def_builtin ("__builtin_bfin_shl_fr2x16", v2hi_ftype_v2hi_int
,
4524 BFIN_BUILTIN_SSASHIFT_2X16
);
4525 def_builtin ("__builtin_bfin_lshl_fr1x16", short_ftype_int_int
,
4526 BFIN_BUILTIN_LSHIFT_1X16
);
4527 def_builtin ("__builtin_bfin_lshl_fr2x16", v2hi_ftype_v2hi_int
,
4528 BFIN_BUILTIN_LSHIFT_2X16
);
4530 /* Complex numbers. */
4531 def_builtin ("__builtin_bfin_cmplx_mul", v2hi_ftype_v2hi_v2hi
,
4532 BFIN_BUILTIN_CPLX_MUL_16
);
4533 def_builtin ("__builtin_bfin_cmplx_mac", v2hi_ftype_v2hi_v2hi_v2hi
,
4534 BFIN_BUILTIN_CPLX_MAC_16
);
4535 def_builtin ("__builtin_bfin_cmplx_msu", v2hi_ftype_v2hi_v2hi_v2hi
,
4536 BFIN_BUILTIN_CPLX_MSU_16
);
4540 struct builtin_description
4542 const enum insn_code icode
;
4543 const char *const name
;
4544 const enum bfin_builtins code
;
4548 static const struct builtin_description bdesc_2arg
[] =
4550 { CODE_FOR_composev2hi
, "__builtin_bfin_compose_2x16", BFIN_BUILTIN_COMPOSE_2X16
, -1 },
4552 { CODE_FOR_ssashiftv2hi3
, "__builtin_bfin_shl_fr2x16", BFIN_BUILTIN_SSASHIFT_2X16
, -1 },
4553 { CODE_FOR_ssashifthi3
, "__builtin_bfin_shl_fr1x16", BFIN_BUILTIN_SSASHIFT_1X16
, -1 },
4554 { CODE_FOR_lshiftv2hi3
, "__builtin_bfin_lshl_fr2x16", BFIN_BUILTIN_LSHIFT_2X16
, -1 },
4555 { CODE_FOR_lshifthi3
, "__builtin_bfin_lshl_fr1x16", BFIN_BUILTIN_LSHIFT_1X16
, -1 },
4557 { CODE_FOR_sminhi3
, "__builtin_bfin_min_fr1x16", BFIN_BUILTIN_MIN_1X16
, -1 },
4558 { CODE_FOR_smaxhi3
, "__builtin_bfin_max_fr1x16", BFIN_BUILTIN_MAX_1X16
, -1 },
4559 { CODE_FOR_ssaddhi3
, "__builtin_bfin_add_fr1x16", BFIN_BUILTIN_SSADD_1X16
, -1 },
4560 { CODE_FOR_sssubhi3
, "__builtin_bfin_sub_fr1x16", BFIN_BUILTIN_SSSUB_1X16
, -1 },
4562 { CODE_FOR_sminsi3
, "__builtin_bfin_min_fr1x32", BFIN_BUILTIN_MIN_1X32
, -1 },
4563 { CODE_FOR_smaxsi3
, "__builtin_bfin_max_fr1x32", BFIN_BUILTIN_MAX_1X32
, -1 },
4564 { CODE_FOR_ssaddsi3
, "__builtin_bfin_add_fr1x32", BFIN_BUILTIN_SSADD_1X32
, -1 },
4565 { CODE_FOR_sssubsi3
, "__builtin_bfin_sub_fr1x32", BFIN_BUILTIN_SSSUB_1X32
, -1 },
4567 { CODE_FOR_sminv2hi3
, "__builtin_bfin_min_fr2x16", BFIN_BUILTIN_MIN_2X16
, -1 },
4568 { CODE_FOR_smaxv2hi3
, "__builtin_bfin_max_fr2x16", BFIN_BUILTIN_MAX_2X16
, -1 },
4569 { CODE_FOR_ssaddv2hi3
, "__builtin_bfin_add_fr2x16", BFIN_BUILTIN_SSADD_2X16
, -1 },
4570 { CODE_FOR_sssubv2hi3
, "__builtin_bfin_sub_fr2x16", BFIN_BUILTIN_SSSUB_2X16
, -1 },
4571 { CODE_FOR_ssaddsubv2hi3
, "__builtin_bfin_dspaddsubsat", BFIN_BUILTIN_SSADDSUB_2X16
, -1 },
4572 { CODE_FOR_sssubaddv2hi3
, "__builtin_bfin_dspsubaddsat", BFIN_BUILTIN_SSSUBADD_2X16
, -1 },
4574 { CODE_FOR_flag_mulhisi
, "__builtin_bfin_mult_fr1x32", BFIN_BUILTIN_MULT_1X32
, MACFLAG_NONE
},
4575 { CODE_FOR_flag_mulhi
, "__builtin_bfin_mult_fr1x16", BFIN_BUILTIN_MULT_1X16
, MACFLAG_T
},
4576 { CODE_FOR_flag_mulhi
, "__builtin_bfin_multr_fr1x16", BFIN_BUILTIN_MULTR_1X16
, MACFLAG_NONE
},
4577 { CODE_FOR_flag_mulv2hi
, "__builtin_bfin_mult_fr2x16", BFIN_BUILTIN_MULT_2X16
, MACFLAG_T
},
4578 { CODE_FOR_flag_mulv2hi
, "__builtin_bfin_multr_fr2x16", BFIN_BUILTIN_MULTR_2X16
, MACFLAG_NONE
}
4581 static const struct builtin_description bdesc_1arg
[] =
4583 { CODE_FOR_signbitshi2
, "__builtin_bfin_norm_fr1x16", BFIN_BUILTIN_NORM_1X16
, 0 },
4584 { CODE_FOR_ssneghi2
, "__builtin_bfin_negate_fr1x16", BFIN_BUILTIN_NEG_1X16
, 0 },
4585 { CODE_FOR_abshi2
, "__builtin_bfin_abs_fr1x16", BFIN_BUILTIN_ABS_1X16
, 0 },
4587 { CODE_FOR_signbitssi2
, "__builtin_bfin_norm_fr1x32", BFIN_BUILTIN_NORM_1X32
, 0 },
4588 { CODE_FOR_ssnegsi2
, "__builtin_bfin_negate_fr1x32", BFIN_BUILTIN_NEG_1X32
, 0 },
4590 { CODE_FOR_movv2hi_hi_low
, "__builtin_bfin_extract_lo", BFIN_BUILTIN_EXTRACTLO
, 0 },
4591 { CODE_FOR_movv2hi_hi_high
, "__builtin_bfin_extract_hi", BFIN_BUILTIN_EXTRACTHI
, 0 },
4592 { CODE_FOR_ssnegv2hi2
, "__builtin_bfin_negate_fr2x16", BFIN_BUILTIN_NEG_2X16
, 0 },
4593 { CODE_FOR_absv2hi2
, "__builtin_bfin_abs_fr2x16", BFIN_BUILTIN_ABS_2X16
, 0 }
4596 /* Errors in the source file can cause expand_expr to return const0_rtx
4597 where we expect a vector. To avoid crashing, use one of the vector
4598 clear instructions. */
4600 safe_vector_operand (rtx x
, enum machine_mode mode
)
4602 if (x
!= const0_rtx
)
4604 x
= gen_reg_rtx (SImode
);
4606 emit_insn (gen_movsi (x
, CONST0_RTX (SImode
)));
4607 return gen_lowpart (mode
, x
);
4610 /* Subroutine of bfin_expand_builtin to take care of binop insns. MACFLAG is -1
4611 if this is a normal binary op, or one of the MACFLAG_xxx constants. */
4614 bfin_expand_binop_builtin (enum insn_code icode
, tree arglist
, rtx target
,
4618 tree arg0
= TREE_VALUE (arglist
);
4619 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
4620 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
4621 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
4622 enum machine_mode op0mode
= GET_MODE (op0
);
4623 enum machine_mode op1mode
= GET_MODE (op1
);
4624 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
4625 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
4626 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
4628 if (VECTOR_MODE_P (mode0
))
4629 op0
= safe_vector_operand (op0
, mode0
);
4630 if (VECTOR_MODE_P (mode1
))
4631 op1
= safe_vector_operand (op1
, mode1
);
4634 || GET_MODE (target
) != tmode
4635 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
4636 target
= gen_reg_rtx (tmode
);
4638 if ((op0mode
== SImode
|| op0mode
== VOIDmode
) && mode0
== HImode
)
4641 op0
= gen_lowpart (HImode
, op0
);
4643 if ((op1mode
== SImode
|| op1mode
== VOIDmode
) && mode1
== HImode
)
4646 op1
= gen_lowpart (HImode
, op1
);
4648 /* In case the insn wants input operands in modes different from
4649 the result, abort. */
4650 gcc_assert ((op0mode
== mode0
|| op0mode
== VOIDmode
)
4651 && (op1mode
== mode1
|| op1mode
== VOIDmode
));
4653 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
4654 op0
= copy_to_mode_reg (mode0
, op0
);
4655 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
4656 op1
= copy_to_mode_reg (mode1
, op1
);
4659 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
4661 pat
= GEN_FCN (icode
) (target
, op0
, op1
, GEN_INT (macflag
));
4669 /* Subroutine of bfin_expand_builtin to take care of unop insns. */
4672 bfin_expand_unop_builtin (enum insn_code icode
, tree arglist
,
4676 tree arg0
= TREE_VALUE (arglist
);
4677 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
4678 enum machine_mode op0mode
= GET_MODE (op0
);
4679 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
4680 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
4683 || GET_MODE (target
) != tmode
4684 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
4685 target
= gen_reg_rtx (tmode
);
4687 if (VECTOR_MODE_P (mode0
))
4688 op0
= safe_vector_operand (op0
, mode0
);
4690 if (op0mode
== SImode
&& mode0
== HImode
)
4693 op0
= gen_lowpart (HImode
, op0
);
4695 gcc_assert (op0mode
== mode0
|| op0mode
== VOIDmode
);
4697 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
4698 op0
= copy_to_mode_reg (mode0
, op0
);
4700 pat
= GEN_FCN (icode
) (target
, op0
);
4707 /* Expand an expression EXP that calls a built-in function,
4708 with result going to TARGET if that's convenient
4709 (and in mode MODE if that's convenient).
4710 SUBTARGET may be used as the target for computing one of EXP's operands.
4711 IGNORE is nonzero if the value is to be ignored. */
4714 bfin_expand_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
4715 rtx subtarget ATTRIBUTE_UNUSED
,
4716 enum machine_mode mode ATTRIBUTE_UNUSED
,
4717 int ignore ATTRIBUTE_UNUSED
)
4720 enum insn_code icode
;
4721 const struct builtin_description
*d
;
4722 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
4723 tree arglist
= TREE_OPERAND (exp
, 1);
4724 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
4725 tree arg0
, arg1
, arg2
;
4726 rtx op0
, op1
, op2
, accvec
, pat
, tmp1
, tmp2
;
4727 enum machine_mode tmode
, mode0
;
4731 case BFIN_BUILTIN_CSYNC
:
4732 emit_insn (gen_csync ());
4734 case BFIN_BUILTIN_SSYNC
:
4735 emit_insn (gen_ssync ());
4738 case BFIN_BUILTIN_DIFFHL_2X16
:
4739 case BFIN_BUILTIN_DIFFLH_2X16
:
4740 arg0
= TREE_VALUE (arglist
);
4741 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
4742 icode
= (fcode
== BFIN_BUILTIN_DIFFHL_2X16
4743 ? CODE_FOR_subhilov2hi3
: CODE_FOR_sublohiv2hi3
);
4744 tmode
= insn_data
[icode
].operand
[0].mode
;
4745 mode0
= insn_data
[icode
].operand
[1].mode
;
4748 || GET_MODE (target
) != tmode
4749 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
4750 target
= gen_reg_rtx (tmode
);
4752 if (VECTOR_MODE_P (mode0
))
4753 op0
= safe_vector_operand (op0
, mode0
);
4755 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
4756 op0
= copy_to_mode_reg (mode0
, op0
);
4758 pat
= GEN_FCN (icode
) (target
, op0
, op0
);
4764 case BFIN_BUILTIN_CPLX_MUL_16
:
4765 arg0
= TREE_VALUE (arglist
);
4766 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
4767 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
4768 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
4769 accvec
= gen_reg_rtx (V2PDImode
);
4772 || GET_MODE (target
) != V2HImode
4773 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, V2HImode
))
4774 target
= gen_reg_rtx (tmode
);
4775 if (! register_operand (op0
, GET_MODE (op0
)))
4776 op0
= copy_to_mode_reg (GET_MODE (op0
), op0
);
4777 if (! register_operand (op1
, GET_MODE (op1
)))
4778 op1
= copy_to_mode_reg (GET_MODE (op1
), op1
);
4780 emit_insn (gen_flag_macinit1v2hi_parts (accvec
, op0
, op1
, const0_rtx
,
4781 const0_rtx
, const0_rtx
,
4782 const1_rtx
, GEN_INT (MACFLAG_NONE
)));
4783 emit_insn (gen_flag_macv2hi_parts (target
, op0
, op1
, const1_rtx
,
4784 const1_rtx
, const1_rtx
,
4785 const0_rtx
, accvec
, const1_rtx
, const0_rtx
,
4786 GEN_INT (MACFLAG_NONE
), accvec
));
4790 case BFIN_BUILTIN_CPLX_MAC_16
:
4791 case BFIN_BUILTIN_CPLX_MSU_16
:
4792 arg0
= TREE_VALUE (arglist
);
4793 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
4794 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
4795 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
4796 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
4797 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
4798 accvec
= gen_reg_rtx (V2PDImode
);
4801 || GET_MODE (target
) != V2HImode
4802 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, V2HImode
))
4803 target
= gen_reg_rtx (tmode
);
4804 if (! register_operand (op0
, GET_MODE (op0
)))
4805 op0
= copy_to_mode_reg (GET_MODE (op0
), op0
);
4806 if (! register_operand (op1
, GET_MODE (op1
)))
4807 op1
= copy_to_mode_reg (GET_MODE (op1
), op1
);
4809 tmp1
= gen_reg_rtx (SImode
);
4810 tmp2
= gen_reg_rtx (SImode
);
4811 emit_insn (gen_ashlsi3 (tmp1
, gen_lowpart (SImode
, op2
), GEN_INT (16)));
4812 emit_move_insn (tmp2
, gen_lowpart (SImode
, op2
));
4813 emit_insn (gen_movstricthi_1 (gen_lowpart (HImode
, tmp2
), const0_rtx
));
4814 emit_insn (gen_load_accumulator_pair (accvec
, tmp1
, tmp2
));
4815 emit_insn (gen_flag_macv2hi_parts_acconly (accvec
, op0
, op1
, const0_rtx
,
4816 const0_rtx
, const0_rtx
,
4817 const1_rtx
, accvec
, const0_rtx
,
4819 GEN_INT (MACFLAG_W32
)));
4820 tmp1
= (fcode
== BFIN_BUILTIN_CPLX_MAC_16
? const1_rtx
: const0_rtx
);
4821 tmp2
= (fcode
== BFIN_BUILTIN_CPLX_MAC_16
? const0_rtx
: const1_rtx
);
4822 emit_insn (gen_flag_macv2hi_parts (target
, op0
, op1
, const1_rtx
,
4823 const1_rtx
, const1_rtx
,
4824 const0_rtx
, accvec
, tmp1
, tmp2
,
4825 GEN_INT (MACFLAG_NONE
), accvec
));
4833 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
4834 if (d
->code
== fcode
)
4835 return bfin_expand_binop_builtin (d
->icode
, arglist
, target
,
4838 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
4839 if (d
->code
== fcode
)
4840 return bfin_expand_unop_builtin (d
->icode
, arglist
, target
);
4845 #undef TARGET_INIT_BUILTINS
4846 #define TARGET_INIT_BUILTINS bfin_init_builtins
4848 #undef TARGET_EXPAND_BUILTIN
4849 #define TARGET_EXPAND_BUILTIN bfin_expand_builtin
4851 #undef TARGET_ASM_GLOBALIZE_LABEL
4852 #define TARGET_ASM_GLOBALIZE_LABEL bfin_globalize_label
4854 #undef TARGET_ASM_FILE_START
4855 #define TARGET_ASM_FILE_START output_file_start
4857 #undef TARGET_ATTRIBUTE_TABLE
4858 #define TARGET_ATTRIBUTE_TABLE bfin_attribute_table
4860 #undef TARGET_COMP_TYPE_ATTRIBUTES
4861 #define TARGET_COMP_TYPE_ATTRIBUTES bfin_comp_type_attributes
4863 #undef TARGET_RTX_COSTS
4864 #define TARGET_RTX_COSTS bfin_rtx_costs
4866 #undef TARGET_ADDRESS_COST
4867 #define TARGET_ADDRESS_COST bfin_address_cost
4869 #undef TARGET_ASM_INTERNAL_LABEL
4870 #define TARGET_ASM_INTERNAL_LABEL bfin_internal_label
4872 #undef TARGET_ASM_INTEGER
4873 #define TARGET_ASM_INTEGER bfin_assemble_integer
4875 #undef TARGET_MACHINE_DEPENDENT_REORG
4876 #define TARGET_MACHINE_DEPENDENT_REORG bfin_reorg
4878 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
4879 #define TARGET_FUNCTION_OK_FOR_SIBCALL bfin_function_ok_for_sibcall
4881 #undef TARGET_ASM_OUTPUT_MI_THUNK
4882 #define TARGET_ASM_OUTPUT_MI_THUNK bfin_output_mi_thunk
4883 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
4884 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
4886 #undef TARGET_SCHED_ADJUST_COST
4887 #define TARGET_SCHED_ADJUST_COST bfin_adjust_cost
4889 #undef TARGET_SCHED_ISSUE_RATE
4890 #define TARGET_SCHED_ISSUE_RATE bfin_issue_rate
4892 #undef TARGET_PROMOTE_PROTOTYPES
4893 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
4894 #undef TARGET_PROMOTE_FUNCTION_ARGS
4895 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
4896 #undef TARGET_PROMOTE_FUNCTION_RETURN
4897 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
4899 #undef TARGET_ARG_PARTIAL_BYTES
4900 #define TARGET_ARG_PARTIAL_BYTES bfin_arg_partial_bytes
4902 #undef TARGET_PASS_BY_REFERENCE
4903 #define TARGET_PASS_BY_REFERENCE bfin_pass_by_reference
4905 #undef TARGET_SETUP_INCOMING_VARARGS
4906 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
4908 #undef TARGET_STRUCT_VALUE_RTX
4909 #define TARGET_STRUCT_VALUE_RTX bfin_struct_value_rtx
4911 #undef TARGET_VECTOR_MODE_SUPPORTED_P
4912 #define TARGET_VECTOR_MODE_SUPPORTED_P bfin_vector_mode_supported_p
4914 #undef TARGET_HANDLE_OPTION
4915 #define TARGET_HANDLE_OPTION bfin_handle_option
4917 #undef TARGET_DEFAULT_TARGET_FLAGS
4918 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
4920 #undef TARGET_SECONDARY_RELOAD
4921 #define TARGET_SECONDARY_RELOAD bfin_secondary_reload
4923 #undef TARGET_DELEGITIMIZE_ADDRESS
4924 #define TARGET_DELEGITIMIZE_ADDRESS bfin_delegitimize_address
4926 #undef TARGET_CANNOT_FORCE_CONST_MEM
4927 #define TARGET_CANNOT_FORCE_CONST_MEM bfin_cannot_force_const_mem
4929 struct gcc_target targetm
= TARGET_INITIALIZER
;