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crti.s (__init, __fini): Use appropriate prologue if __PIC__ is defined.
[gcc.git] / gcc / config / bfin / bfin.h
1 /* Definitions for the Blackfin port.
2 Copyright (C) 2005 Free Software Foundation, Inc.
3 Contributed by Analog Devices.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
21
22 #ifndef _BFIN_CONFIG
23 #define _BFIN_CONFIG
24
25 #define OBJECT_FORMAT_ELF
26
27 #define BRT 1
28 #define BRF 0
29
30 /* Print subsidiary information on the compiler version in use. */
31 #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)")
32
33 /* Run-time compilation parameters selecting different hardware subsets. */
34
35 extern int target_flags;
36
37 /* Predefinition in the preprocessor for this target machine */
38 #ifndef TARGET_CPU_CPP_BUILTINS
39 #define TARGET_CPU_CPP_BUILTINS() \
40 do \
41 { \
42 builtin_define ("bfin"); \
43 builtin_define ("BFIN"); \
44 if (flag_pic) \
45 { \
46 builtin_define ("__PIC__"); \
47 builtin_define ("__pic__"); \
48 } \
49 } \
50 while (0)
51 #endif
52
53 /* Generate DSP instructions, like DSP halfword loads */
54 #define TARGET_DSP (1)
55
56 #define TARGET_DEFAULT (MASK_SPECLD_ANOMALY | MASK_CSYNC_ANOMALY)
57
58 /* Maximum number of library ids we permit */
59 #define MAX_LIBRARY_ID 255
60
61 extern const char *bfin_library_id_string;
62
63 /* Sometimes certain combinations of command options do not make
64 sense on a particular target machine. You can define a macro
65 `OVERRIDE_OPTIONS' to take account of this. This macro, if
66 defined, is executed once just after all the command options have
67 been parsed.
68
69 Don't use this macro to turn on various extra optimizations for
70 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
71
72 #define OVERRIDE_OPTIONS override_options ()
73
74 #define FUNCTION_MODE SImode
75 #define Pmode SImode
76
77 /* store-condition-codes instructions store 0 for false
78 This is the value stored for true. */
79 #define STORE_FLAG_VALUE 1
80
81 /* Define this if pushing a word on the stack
82 makes the stack pointer a smaller address. */
83 #define STACK_GROWS_DOWNWARD
84
85 #define STACK_PUSH_CODE PRE_DEC
86
87 /* Define this to nonzero if the nominal address of the stack frame
88 is at the high-address end of the local variables;
89 that is, each additional local variable allocated
90 goes at a more negative offset in the frame. */
91 #define FRAME_GROWS_DOWNWARD 1
92
93 /* We define a dummy ARGP register; the parameters start at offset 0 from
94 it. */
95 #define FIRST_PARM_OFFSET(DECL) 0
96
97 /* Offset within stack frame to start allocating local variables at.
98 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
99 first local allocated. Otherwise, it is the offset to the BEGINNING
100 of the first local allocated. */
101 #define STARTING_FRAME_OFFSET 0
102
103 /* Register to use for pushing function arguments. */
104 #define STACK_POINTER_REGNUM REG_P6
105
106 /* Base register for access to local variables of the function. */
107 #define FRAME_POINTER_REGNUM REG_P7
108
109 /* A dummy register that will be eliminated to either FP or SP. */
110 #define ARG_POINTER_REGNUM REG_ARGP
111
112 /* `PIC_OFFSET_TABLE_REGNUM'
113 The register number of the register used to address a table of
114 static data addresses in memory. In some cases this register is
115 defined by a processor's "application binary interface" (ABI).
116 When this macro is defined, RTL is generated for this register
117 once, as with the stack pointer and frame pointer registers. If
118 this macro is not defined, it is up to the machine-dependent files
119 to allocate such a register (if necessary). */
120 #define PIC_OFFSET_TABLE_REGNUM (REG_P5)
121
122 /* A static chain register for nested functions. We need to use a
123 call-clobbered register for this. */
124 #define STATIC_CHAIN_REGNUM REG_P2
125
126 /* Define this if functions should assume that stack space has been
127 allocated for arguments even when their values are passed in
128 registers.
129
130 The value of this macro is the size, in bytes, of the area reserved for
131 arguments passed in registers.
132
133 This space can either be allocated by the caller or be a part of the
134 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
135 says which. */
136 #define FIXED_STACK_AREA 12
137 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA
138
139 /* Define this if the above stack space is to be considered part of the
140 * space allocated by the caller. */
141 #define OUTGOING_REG_PARM_STACK_SPACE
142
143 /* Define this if the maximum size of all the outgoing args is to be
144 accumulated and pushed during the prologue. The amount can be
145 found in the variable current_function_outgoing_args_size. */
146 #define ACCUMULATE_OUTGOING_ARGS 1
147
148 /* Value should be nonzero if functions must have frame pointers.
149 Zero means the frame pointer need not be set up (and parms
150 may be accessed via the stack pointer) in functions that seem suitable.
151 This is computed in `reload', in reload1.c.
152 */
153 #define FRAME_POINTER_REQUIRED (bfin_frame_pointer_required ())
154
155 #define PARM_BOUNDRY 32
156
157 #define STACK_BOUNDRY 32
158
159 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */
160
161 /* Make strings word-aligned so strcpy from constants will be faster. */
162 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
163 (TREE_CODE (EXP) == STRING_CST \
164 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
165
166 #define TRAMPOLINE_SIZE 18
167 #define TRAMPOLINE_TEMPLATE(FILE) \
168 fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \
169 fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */; \
170 fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */; \
171 fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */; \
172 fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/
173
174 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
175 initialize_trampoline (TRAMP, FNADDR, CXT)
176 \f
177 /* Definitions for register eliminations.
178
179 This is an array of structures. Each structure initializes one pair
180 of eliminable registers. The "from" register number is given first,
181 followed by "to". Eliminations of the same "from" register are listed
182 in order of preference.
183
184 There are two registers that can always be eliminated on the i386.
185 The frame pointer and the arg pointer can be replaced by either the
186 hard frame pointer or to the stack pointer, depending upon the
187 circumstances. The hard frame pointer is not used before reload and
188 so it is not eligible for elimination. */
189
190 #define ELIMINABLE_REGS \
191 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
192 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
193 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \
194
195 /* Given FROM and TO register numbers, say whether this elimination is
196 allowed. Frame pointer elimination is automatically handled.
197
198 All other eliminations are valid. */
199
200 #define CAN_ELIMINATE(FROM, TO) \
201 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
202
203 /* Define the offset between two registers, one to be eliminated, and the other
204 its replacement, at the start of a routine. */
205
206 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
207 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO)))
208 \f
209 /* This processor has
210 8 data register for doing arithmetic
211 8 pointer register for doing addressing, including
212 1 stack pointer P6
213 1 frame pointer P7
214 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3)
215 1 condition code flag register CC
216 5 return address registers RETS/I/X/N/E
217 1 arithmetic status register (ASTAT). */
218
219 #define FIRST_PSEUDO_REGISTER 44
220
221 #define PREG_P(X) (REG_P (X) && REGNO (X) >= REG_P0 && REGNO (X) <= REG_P7)
222 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3)
223 #define D_REGNO_P(X) ((X) <= REG_R7)
224
225 #define REGISTER_NAMES { \
226 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
227 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \
228 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \
229 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \
230 "A0", "A1", \
231 "CC", \
232 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \
233 "ARGP" \
234 }
235
236 #define SHORT_REGISTER_NAMES { \
237 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \
238 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \
239 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \
240 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", }
241
242 #define HIGH_REGISTER_NAMES { \
243 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \
244 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \
245 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \
246 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", }
247
248 #define DREGS_PAIR_NAMES { \
249 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, }
250
251 #define BYTE_REGISTER_NAMES { \
252 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", }
253
254
255 /* 1 for registers that have pervasive standard uses
256 and are not available for the register allocator. */
257
258 #define FIXED_REGISTERS \
259 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
260 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
261 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
262 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
263 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp */ \
264 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
265 }
266
267 /* 1 for registers not available across function calls.
268 These must include the FIXED_REGISTERS and also any
269 registers that can be used without being saved.
270 The latter must include the registers where values are returned
271 and the register where structure-value addresses are passed.
272 Aside from that, you can include as many other registers as you like. */
273
274 #define CALL_USED_REGISTERS \
275 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
276 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \
277 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
278 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
279 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp */ \
280 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
281 }
282
283 /* Order in which to allocate registers. Each register must be
284 listed once, even those in FIXED_REGISTERS. List frame pointer
285 late and fixed registers last. Note that, in general, we prefer
286 registers listed in CALL_USED_REGISTERS, keeping the others
287 available for storage of persistent values. */
288
289 #define REG_ALLOC_ORDER \
290 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \
291 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \
292 REG_A0, REG_A1, \
293 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \
294 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \
295 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \
296 REG_ASTAT, REG_SEQSTAT, REG_USP, \
297 REG_CC, REG_ARGP \
298 }
299
300 /* Macro to conditionally modify fixed_regs/call_used_regs. */
301 #define CONDITIONAL_REGISTER_USAGE \
302 { \
303 conditional_register_usage(); \
304 if (flag_pic) \
305 { \
306 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
307 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
308 } \
309 }
310
311 /* Define the classes of registers for register constraints in the
312 machine description. Also define ranges of constants.
313
314 One of the classes must always be named ALL_REGS and include all hard regs.
315 If there is more than one class, another class must be named NO_REGS
316 and contain no registers.
317
318 The name GENERAL_REGS must be the name of a class (or an alias for
319 another name such as ALL_REGS). This is the class of registers
320 that is allowed by "g" or "r" in a register constraint.
321 Also, registers outside this class are allocated only when
322 instructions express preferences for them.
323
324 The classes must be numbered in nondecreasing order; that is,
325 a larger-numbered class must never be contained completely
326 in a smaller-numbered class.
327
328 For any two classes, it is very desirable that there be another
329 class that represents their union. */
330
331
332 enum reg_class
333 {
334 NO_REGS,
335 IREGS,
336 BREGS,
337 LREGS,
338 MREGS,
339 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */
340 DAGREGS,
341 EVEN_AREGS,
342 ODD_AREGS,
343 AREGS,
344 CCREGS,
345 EVEN_DREGS,
346 ODD_DREGS,
347 DREGS,
348 PREGS_CLOBBERED,
349 PREGS,
350 DPREGS,
351 MOST_REGS,
352 PROLOGUE_REGS,
353 NON_A_CC_REGS,
354 ALL_REGS, LIM_REG_CLASSES
355 };
356
357 #define N_REG_CLASSES ((int)LIM_REG_CLASSES)
358
359 #define GENERAL_REGS DPREGS
360
361 /* Give names of register classes as strings for dump file. */
362
363 #define REG_CLASS_NAMES \
364 { "NO_REGS", \
365 "IREGS", \
366 "BREGS", \
367 "LREGS", \
368 "MREGS", \
369 "CIRCREGS", \
370 "DAGREGS", \
371 "EVEN_AREGS", \
372 "ODD_AREGS", \
373 "AREGS", \
374 "CCREGS", \
375 "EVEN_DREGS", \
376 "ODD_DREGS", \
377 "DREGS", \
378 "PREGS_CLOBBERED", \
379 "PREGS", \
380 "DPREGS", \
381 "MOST_REGS", \
382 "PROLOGUE_REGS", \
383 "NON_A_CC_REGS", \
384 "ALL_REGS" }
385
386 /* An initializer containing the contents of the register classes, as integers
387 which are bit masks. The Nth integer specifies the contents of class N.
388 The way the integer MASK is interpreted is that register R is in the class
389 if `MASK & (1 << R)' is 1.
390
391 When the machine has more than 32 registers, an integer does not suffice.
392 Then the integers are replaced by sub-initializers, braced groupings
393 containing several integers. Each sub-initializer must be suitable as an
394 initializer for the type `HARD_REG_SET' which is defined in
395 `hard-reg-set.h'. */
396
397 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use
398 MOST_REGS as the union of DPREGS and DAGREGS. */
399
400 #define REG_CLASS_CONTENTS \
401 /* 31 - 0 63-32 */ \
402 { { 0x00000000, 0 }, /* NO_REGS */ \
403 { 0x000f0000, 0 }, /* IREGS */ \
404 { 0x00f00000, 0 }, /* BREGS */ \
405 { 0x0f000000, 0 }, /* LREGS */ \
406 { 0xf0000000, 0 }, /* MREGS */ \
407 { 0x0fff0000, 0 }, /* CIRCREGS */ \
408 { 0xffff0000, 0 }, /* DAGREGS */ \
409 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \
410 { 0x00000000, 0x2 }, /* ODD_AREGS */ \
411 { 0x00000000, 0x3 }, /* AREGS */ \
412 { 0x00000000, 0x4 }, /* CCREGS */ \
413 { 0x00000055, 0 }, /* EVEN_DREGS */ \
414 { 0x000000aa, 0 }, /* ODD_DREGS */ \
415 { 0x000000ff, 0 }, /* DREGS */ \
416 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \
417 { 0x0000ff00, 0x800 }, /* PREGS */ \
418 { 0x0000ffff, 0x800 }, /* DPREGS */ \
419 { 0xffffffff, 0x800 }, /* MOST_REGS */\
420 { 0x00000000, 0x7f8 }, /* PROLOGUE_REGS */\
421 { 0xffffffff, 0xff8 }, /* NON_A_CC_REGS */\
422 { 0xffffffff, 0xfff }} /* ALL_REGS */
423
424 #define BASE_REG_CLASS PREGS
425 #define INDEX_REG_CLASS PREGS
426
427 #define REGNO_OK_FOR_BASE_STRICT_P(X) (REGNO_REG_CLASS (X) == BASE_REG_CLASS)
428 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X) \
429 (((X) >= FIRST_PSEUDO_REGISTER) || REGNO_REG_CLASS (X) == BASE_REG_CLASS)
430
431 #ifdef REG_OK_STRICT
432 #define REGNO_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_STRICT_P (X)
433 #else
434 #define REGNO_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_NONSTRICT_P (X)
435 #endif
436
437 #define REG_OK_FOR_BASE_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
438 #define REG_OK_FOR_INDEX_P(X) 0
439 #define REGNO_OK_FOR_INDEX_P(X) 0
440
441 /* Get reg_class from a letter such as appears in the machine description. */
442
443 #define REG_CLASS_FROM_LETTER(LETTER) \
444 ((LETTER) == 'a' ? PREGS : \
445 (LETTER) == 'd' ? DREGS : \
446 (LETTER) == 'z' ? PREGS_CLOBBERED : \
447 (LETTER) == 'D' ? EVEN_DREGS : \
448 (LETTER) == 'W' ? ODD_DREGS : \
449 (LETTER) == 'e' ? AREGS : \
450 (LETTER) == 'A' ? EVEN_AREGS : \
451 (LETTER) == 'B' ? ODD_AREGS : \
452 (LETTER) == 'b' ? IREGS : \
453 (LETTER) == 'B' ? BREGS : \
454 (LETTER) == 'f' ? MREGS : \
455 (LETTER) == 'c' ? CIRCREGS : \
456 (LETTER) == 'C' ? CCREGS : \
457 (LETTER) == 'x' ? MOST_REGS : \
458 (LETTER) == 'y' ? PROLOGUE_REGS : \
459 (LETTER) == 'w' ? NON_A_CC_REGS : \
460 NO_REGS)
461
462 /* The same information, inverted:
463 Return the class number of the smallest class containing
464 reg number REGNO. This could be a conditional expression
465 or could index an array. */
466
467 #define REGNO_REG_CLASS(REGNO) \
468 ((REGNO) < REG_P0 ? DREGS \
469 : (REGNO) < REG_I0 ? PREGS \
470 : (REGNO) == REG_ARGP ? BASE_REG_CLASS \
471 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \
472 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \
473 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \
474 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \
475 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \
476 : (REGNO) == REG_CC ? CCREGS \
477 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \
478 : NO_REGS)
479
480 /* When defined, the compiler allows registers explicitly used in the
481 rtl to be used as spill registers but prevents the compiler from
482 extending the lifetime of these registers. */
483 #define SMALL_REGISTER_CLASSES 1
484
485 #define CLASS_LIKELY_SPILLED_P(CLASS) \
486 ((CLASS) == PREGS_CLOBBERED \
487 || (CLASS) == PROLOGUE_REGS \
488 || (CLASS) == CCREGS)
489
490 /* Do not allow to store a value in REG_CC for any mode */
491 /* Do not allow to store value in pregs if mode is not SI*/
492 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
493
494 /* Return the maximum number of consecutive registers
495 needed to represent mode MODE in a register of class CLASS. */
496 #define CLASS_MAX_NREGS(CLASS, MODE) \
497 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
498
499 #define HARD_REGNO_NREGS(REGNO, MODE) \
500 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) \
501 ? 1 : CLASS_MAX_NREGS (GENERAL_REGS, MODE))
502
503 /* A C expression that is nonzero if hard register TO can be
504 considered for use as a rename register for FROM register */
505 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO)
506
507 /* A C expression that is nonzero if it is desirable to choose
508 register allocation so as to avoid move instructions between a
509 value of mode MODE1 and a value of mode MODE2.
510
511 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
512 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
513 MODE2)' must be zero. */
514 #define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2))
515
516 /* `PREFERRED_RELOAD_CLASS (X, CLASS)'
517 A C expression that places additional restrictions on the register
518 class to use when it is necessary to copy value X into a register
519 in class CLASS. The value is a register class; perhaps CLASS, or
520 perhaps another, smaller class. */
521 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
522
523 #define SECONDARY_OUTPUT_RELOAD_CLASS(class,mode,x) \
524 secondary_output_reload_class(class,mode,x)
525 #define SECONDARY_INPUT_RELOAD_CLASS(class,mode,x) \
526 secondary_input_reload_class(class,mode,x)
527
528 /* Function Calling Conventions. */
529
530 /* The type of the current function; normal functions are of type
531 SUBROUTINE. */
532 typedef enum {
533 SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER
534 } e_funkind;
535
536 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 }
537
538 /* Flags for the call/call_value rtl operations set up by function_arg */
539 #define CALL_NORMAL 0x00000000 /* no special processing */
540 #define CALL_LONG 0x00000001 /* always call indirect */
541 #define CALL_SHORT 0x00000002 /* always call by symbol */
542
543 typedef struct {
544 int words; /* # words passed so far */
545 int nregs; /* # registers available for passing */
546 int *arg_regs; /* array of register -1 terminated */
547 int call_cookie; /* Do special things for this call */
548 } CUMULATIVE_ARGS;
549
550 /* Define where to put the arguments to a function.
551 Value is zero to push the argument on the stack,
552 or a hard register in which to store the argument.
553
554 MODE is the argument's machine mode.
555 TYPE is the data type of the argument (as a tree).
556 This is null for libcalls where that information may
557 not be available.
558 CUM is a variable of type CUMULATIVE_ARGS which gives info about
559 the preceding args and about the function being called.
560 NAMED is nonzero if this argument is a named parameter
561 (otherwise it is an extra parameter matching an ellipsis). */
562
563 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
564 (function_arg (&CUM, MODE, TYPE, NAMED))
565
566 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO)
567
568
569 /* Initialize a variable CUM of type CUMULATIVE_ARGS
570 for a call to a function whose data type is FNTYPE.
571 For a library call, FNTYPE is 0. */
572 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \
573 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
574
575 /* Update the data in CUM to advance over an argument
576 of mode MODE and data type TYPE.
577 (TYPE is null for libcalls where that information may not be available.) */
578 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
579 (function_arg_advance (&CUM, MODE, TYPE, NAMED))
580
581 #define RETURN_POPS_ARGS(FDECL, FUNTYPE, STKSIZE) 0
582
583 /* Define how to find the value returned by a function.
584 VALTYPE is the data type of the value (as a tree).
585 If the precise function being called is known, FUNC is its FUNCTION_DECL;
586 otherwise, FUNC is 0.
587 */
588
589 #define VALUE_REGNO(MODE) (REG_R0)
590
591 #define FUNCTION_VALUE(VALTYPE, FUNC) \
592 gen_rtx_REG (TYPE_MODE (VALTYPE), \
593 VALUE_REGNO(TYPE_MODE(VALTYPE)))
594
595 /* Define how to find the value returned by a library function
596 assuming the value has mode MODE. */
597
598 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE))
599
600 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0)
601
602 #define DEFAULT_PCC_STRUCT_RETURN 0
603 #define RETURN_IN_MEMORY(TYPE) bfin_return_in_memory(TYPE)
604
605 /* Before the prologue, the return address is in the RETS register. */
606 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS)
607
608 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT)
609
610 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS)
611
612 /* Call instructions don't modify the stack pointer on the Blackfin. */
613 #define INCOMING_FRAME_SP_OFFSET 0
614
615 /* Describe how we implement __builtin_eh_return. */
616 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
617 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2)
618 #define EH_RETURN_HANDLER_RTX \
619 gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD))
620
621 /* Addressing Modes */
622
623 /* Recognize any constant value that is a valid address. */
624 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
625
626 /* Nonzero if the constant value X is a legitimate general operand.
627 symbol_ref are not legitimate and will be put into constant pool.
628 See force_const_mem().
629 If -mno-pool, all constants are legitimate.
630 */
631 #define LEGITIMATE_CONSTANT_P(x) 1
632
633 /* A number, the maximum number of registers that can appear in a
634 valid memory address. Note that it is up to you to specify a
635 value equal to the maximum number that `GO_IF_LEGITIMATE_ADDRESS'
636 would ever accept. */
637 #define MAX_REGS_PER_ADDRESS 1
638
639 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
640 that is a valid memory address for an instruction.
641 The MODE argument is the machine mode for the MEM expression
642 that wants to use this address.
643
644 Blackfin addressing modes are as follows:
645
646 [preg]
647 [preg + imm16]
648
649 B [ Preg + uimm15 ]
650 W [ Preg + uimm16m2 ]
651 [ Preg + uimm17m4 ]
652
653 [preg++]
654 [preg--]
655 [--sp]
656 */
657
658 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \
659 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode)
660
661 #ifdef REG_OK_STRICT
662 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
663 do { \
664 if (bfin_legitimate_address_p (MODE, X, 1)) \
665 goto WIN; \
666 } while (0);
667 #else
668 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
669 do { \
670 if (bfin_legitimate_address_p (MODE, X, 0)) \
671 goto WIN; \
672 } while (0);
673 #endif
674
675 /* Try machine-dependent ways of modifying an illegitimate address
676 to be legitimate. If we find one, return the new, valid address.
677 This macro is used in only one place: `memory_address' in explow.c.
678
679 OLDX is the address as it was before break_out_memory_refs was called.
680 In some cases it is useful to look at this to decide what needs to be done.
681
682 MODE and WIN are passed so that this macro can use
683 GO_IF_LEGITIMATE_ADDRESS.
684
685 It is always safe for this macro to do nothing. It exists to recognize
686 opportunities to optimize the output.
687 */
688 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
689 do { \
690 rtx _q = legitimize_address(X, OLDX, MODE); \
691 if (_q) { X = _q; goto WIN; } \
692 } while (0)
693
694 #define HAVE_POST_INCREMENT 1
695 #define HAVE_POST_DECREMENT 1
696 #define HAVE_PRE_DECREMENT 1
697
698 /* `LEGITIMATE_PIC_OPERAND_P (X)'
699 A C expression that is nonzero if X is a legitimate immediate
700 operand on the target machine when generating position independent
701 code. You can assume that X satisfies `CONSTANT_P', so you need
702 not check this. You can also assume FLAG_PIC is true, so you need
703 not check it either. You need not define this macro if all
704 constants (including `SYMBOL_REF') can be immediate operands when
705 generating position independent code. */
706 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X)
707
708 #define SYMBOLIC_CONST(X) \
709 (GET_CODE (X) == SYMBOL_REF \
710 || GET_CODE (X) == LABEL_REF \
711 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
712
713 /*
714 A C statement or compound statement with a conditional `goto
715 LABEL;' executed if memory address X (an RTX) can have different
716 meanings depending on the machine mode of the memory reference it
717 is used for or if the address is valid for some modes but not
718 others.
719
720 Autoincrement and autodecrement addresses typically have
721 mode-dependent effects because the amount of the increment or
722 decrement is the size of the operand being addressed. Some
723 machines have other mode-dependent addresses. Many RISC machines
724 have no mode-dependent addresses.
725
726 You may assume that ADDR is a valid address for the machine.
727 */
728 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
729 do { \
730 if (GET_CODE (ADDR) == POST_INC \
731 || GET_CODE (ADDR) == POST_DEC \
732 || GET_CODE (ADDR) == PRE_DEC) \
733 goto LABEL; \
734 } while (0)
735
736 #define NOTICE_UPDATE_CC(EXPR, INSN) 0
737
738 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
739 is done just by pretending it is already truncated. */
740 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
741
742 /* Max number of bytes we can move from memory to memory
743 in one reasonably fast instruction. */
744 #define MOVE_MAX UNITS_PER_WORD
745
746
747 /* STORAGE LAYOUT: target machine storage layout
748 Define this macro as a C expression which is nonzero if accessing
749 less than a word of memory (i.e. a `char' or a `short') is no
750 faster than accessing a word of memory, i.e., if such access
751 require more than one instruction or if there is no difference in
752 cost between byte and (aligned) word loads.
753
754 When this macro is not defined, the compiler will access a field by
755 finding the smallest containing object; when it is defined, a
756 fullword load will be used if alignment permits. Unless bytes
757 accesses are faster than word accesses, using word accesses is
758 preferable since it may eliminate subsequent memory access if
759 subsequent accesses occur to other fields in the same word of the
760 structure, but to different bytes. */
761 #define SLOW_BYTE_ACCESS 0
762 #define SLOW_SHORT_ACCESS 0
763
764 /* Define this if most significant bit is lowest numbered
765 in instructions that operate on numbered bit-fields. */
766 #define BITS_BIG_ENDIAN 0
767
768 /* Define this if most significant byte of a word is the lowest numbered.
769 We can't access bytes but if we could we would in the Big Endian order. */
770 #define BYTES_BIG_ENDIAN 0
771
772 /* Define this if most significant word of a multiword number is numbered. */
773 #define WORDS_BIG_ENDIAN 0
774
775 /* number of bits in an addressable storage unit */
776 #define BITS_PER_UNIT 8
777
778 /* Width in bits of a "word", which is the contents of a machine register.
779 Note that this is not necessarily the width of data type `int';
780 if using 16-bit ints on a 68000, this would still be 32.
781 But on a machine with 16-bit registers, this would be 16. */
782 #define BITS_PER_WORD 32
783
784 /* Width of a word, in units (bytes). */
785 #define UNITS_PER_WORD 4
786
787 /* Width in bits of a pointer.
788 See also the macro `Pmode1' defined below. */
789 #define POINTER_SIZE 32
790
791 /* Allocation boundary (in *bits*) for storing pointers in memory. */
792 #define POINTER_BOUNDARY 32
793
794 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
795 #define PARM_BOUNDARY 32
796
797 /* Boundary (in *bits*) on which stack pointer should be aligned. */
798 #define STACK_BOUNDARY 32
799
800 /* Allocation boundary (in *bits*) for the code of a function. */
801 #define FUNCTION_BOUNDARY 32
802
803 /* Alignment of field after `int : 0' in a structure. */
804 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
805
806 /* No data type wants to be aligned rounder than this. */
807 #define BIGGEST_ALIGNMENT 32
808
809 /* Define this if move instructions will actually fail to work
810 when given unaligned data. */
811 #define STRICT_ALIGNMENT 1
812
813 /* (shell-command "rm c-decl.o stor-layout.o")
814 * never define PCC_BITFIELD_TYPE_MATTERS
815 * really cause some alignment problem
816 */
817
818 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \
819 BITS_PER_UNIT)
820
821 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \
822 BITS_PER_UNIT)
823
824
825 /* what is the 'type' of size_t */
826 #define SIZE_TYPE "long unsigned int"
827
828 /* Define this as 1 if `char' should by default be signed; else as 0. */
829 #define DEFAULT_SIGNED_CHAR 1
830 #define FLOAT_TYPE_SIZE BITS_PER_WORD
831 #define SHORT_TYPE_SIZE 16
832 #define CHAR_TYPE_SIZE 8
833 #define INT_TYPE_SIZE 32
834 #define LONG_TYPE_SIZE 32
835 #define LONG_LONG_TYPE_SIZE 64
836
837 /* Note: Fix this to depend on target switch. -- lev */
838
839 /* Note: Try to implement double and force long double. -- tonyko
840 * #define __DOUBLES_ARE_FLOATS__
841 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE
842 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
843 * #define DOUBLES_ARE_FLOATS 1
844 */
845
846 #define DOUBLE_TYPE_SIZE 64
847 #define LONG_DOUBLE_TYPE_SIZE 64
848
849 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)'
850 A macro to update M and UNSIGNEDP when an object whose type is
851 TYPE and which has the specified mode and signedness is to be
852 stored in a register. This macro is only called when TYPE is a
853 scalar type.
854
855 On most RISC machines, which only have operations that operate on
856 a full register, define this macro to set M to `word_mode' if M is
857 an integer mode narrower than `BITS_PER_WORD'. In most cases,
858 only integer modes should be widened because wider-precision
859 floating-point operations are usually more expensive than their
860 narrower counterparts.
861
862 For most machines, the macro definition does not change UNSIGNEDP.
863 However, some machines, have instructions that preferentially
864 handle either signed or unsigned quantities of certain modes. For
865 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add
866 instructions sign-extend the result to 64 bits. On such machines,
867 set UNSIGNEDP according to which kind of extension is more
868 efficient.
869
870 Do not define this macro if it would never modify M.*/
871
872 #define BFIN_PROMOTE_MODE_P(MODE) \
873 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \
874 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)
875
876 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
877 if (BFIN_PROMOTE_MODE_P(MODE)) \
878 { \
879 if (MODE == QImode) \
880 UNSIGNEDP = 1; \
881 else if (MODE == HImode) \
882 UNSIGNEDP = 0; \
883 (MODE) = SImode; \
884 }
885
886 /* Describing Relative Costs of Operations */
887
888 /* Do not put function addr into constant pool */
889 #define NO_FUNCTION_CSE 1
890
891 /* A C expression for the cost of moving data from a register in class FROM to
892 one in class TO. The classes are expressed using the enumeration values
893 such as `GENERAL_REGS'. A value of 2 is the default; other values are
894 interpreted relative to that.
895
896 It is not required that the cost always equal 2 when FROM is the same as TO;
897 on some machines it is expensive to move between registers if they are not
898 general registers. */
899
900 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
901 bfin_register_move_cost ((MODE), (CLASS1), (CLASS2))
902
903 /* A C expression for the cost of moving data of mode M between a
904 register and memory. A value of 2 is the default; this cost is
905 relative to those in `REGISTER_MOVE_COST'.
906
907 If moving between registers and memory is more expensive than
908 between two registers, you should define this macro to express the
909 relative cost. */
910
911 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
912 bfin_memory_move_cost ((MODE), (CLASS), (IN))
913
914 /* Specify the machine mode that this machine uses
915 for the index in the tablejump instruction. */
916 #define CASE_VECTOR_MODE SImode
917
918 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
919
920 /* Define if operations between registers always perform the operation
921 on the full register even if a narrower mode is specified.
922 #define WORD_REGISTER_OPERATIONS
923 */
924
925 #define CONST_18UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 262140)
926 #define CONST_16BIT_IMM_P(VALUE) ((VALUE) >= -32768 && (VALUE) <= 32767)
927 #define CONST_16UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 65535)
928 #define CONST_7BIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 63)
929 #define CONST_7NBIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 0)
930 #define CONST_5UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 31)
931 #define CONST_4BIT_IMM_P(VALUE) ((VALUE) >= -8 && (VALUE) <= 7)
932 #define CONST_4UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 15)
933 #define CONST_3BIT_IMM_P(VALUE) ((VALUE) >= -4 && (VALUE) <= 3)
934 #define CONST_3UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 7)
935
936 #define CONSTRAINT_LEN(C, STR) \
937 ((C) == 'P' || (C) == 'M' || (C) == 'N' ? 2 \
938 : (C) == 'K' ? 3 \
939 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
940
941 #define CONST_OK_FOR_P(VALUE, STR) \
942 ((STR)[1] == '0' ? (VALUE) == 0 \
943 : (STR)[1] == '1' ? (VALUE) == 1 \
944 : (STR)[1] == '2' ? (VALUE) == 2 \
945 : (STR)[1] == '3' ? (VALUE) == 3 \
946 : (STR)[1] == '4' ? (VALUE) == 4 \
947 : 0)
948
949 #define CONST_OK_FOR_K(VALUE, STR) \
950 ((STR)[1] == 'u' \
951 ? ((STR)[2] == '3' ? CONST_3UBIT_IMM_P (VALUE) \
952 : (STR)[2] == '4' ? CONST_4UBIT_IMM_P (VALUE) \
953 : (STR)[2] == '5' ? CONST_5UBIT_IMM_P (VALUE) \
954 : (STR)[2] == 'h' ? CONST_16UBIT_IMM_P (VALUE) \
955 : 0) \
956 : (STR)[1] == 's' \
957 ? ((STR)[2] == '3' ? CONST_3BIT_IMM_P (VALUE) \
958 : (STR)[2] == '4' ? CONST_4BIT_IMM_P (VALUE) \
959 : (STR)[2] == '7' ? CONST_7BIT_IMM_P (VALUE) \
960 : (STR)[2] == 'h' ? CONST_16BIT_IMM_P (VALUE) \
961 : 0) \
962 : (STR)[1] == 'n' \
963 ? ((STR)[2] == '7' ? CONST_7NBIT_IMM_P (VALUE) \
964 : 0) \
965 : 0)
966
967 #define CONST_OK_FOR_M(VALUE, STR) \
968 ((STR)[1] == '1' ? (VALUE) == 255 \
969 : (STR)[1] == '2' ? (VALUE) == 65535 \
970 : 0)
971
972 /* The letters I, J, K, L and M in a register constraint string
973 can be used to stand for particular ranges of immediate operands.
974 This macro defines what the ranges are.
975 C is the letter, and VALUE is a constant value.
976 Return 1 if VALUE is in the range specified by C.
977
978 bfin constant operands are as follows
979
980 J 2**N 5bit imm scaled
981 Ks7 -64 .. 63 signed 7bit imm
982 Ku5 0..31 unsigned 5bit imm
983 Ks4 -8 .. 7 signed 4bit imm
984 Ks3 -4 .. 3 signed 3bit imm
985 Ku3 0 .. 7 unsigned 3bit imm
986 Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n
987 */
988 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
989 ((C) == 'J' ? (log2constp (VALUE)) \
990 : (C) == 'K' ? CONST_OK_FOR_K (VALUE, STR) \
991 : (C) == 'L' ? log2constp (~(VALUE)) \
992 : (C) == 'M' ? CONST_OK_FOR_M (VALUE, STR) \
993 : (C) == 'P' ? CONST_OK_FOR_P (VALUE, STR) \
994 : 0)
995
996 /*Constant Output Formats */
997 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
998 ((C) == 'H' ? 1 : 0)
999
1000 #define EXTRA_CONSTRAINT(VALUE, D) \
1001 ((D) == 'Q' ? GET_CODE (VALUE) == SYMBOL_REF : 0)
1002
1003 /* Switch into a generic section. */
1004 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
1005
1006 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE)
1007 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX)
1008
1009 typedef enum sections {
1010 CODE_DIR,
1011 DATA_DIR,
1012 LAST_SECT_NM
1013 } SECT_ENUM_T;
1014
1015 typedef enum directives {
1016 LONG_CONST_DIR,
1017 SHORT_CONST_DIR,
1018 BYTE_CONST_DIR,
1019 SPACE_DIR,
1020 INIT_DIR,
1021 LAST_DIR_NM
1022 } DIR_ENUM_T;
1023
1024 #define TEXT_SECTION_ASM_OP ".text;"
1025 #define DATA_SECTION_ASM_OP ".data;"
1026
1027 #define ASM_APP_ON ""
1028 #define ASM_APP_OFF ""
1029
1030 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \
1031 do { fputs (".global ", FILE); \
1032 assemble_name (FILE, NAME); \
1033 fputc (';',FILE); \
1034 fputc ('\n',FILE); \
1035 } while (0)
1036
1037 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1038 do { \
1039 fputs (".type ", FILE); \
1040 assemble_name (FILE, NAME); \
1041 fputs (", STT_FUNC", FILE); \
1042 fputc (';',FILE); \
1043 fputc ('\n',FILE); \
1044 ASM_OUTPUT_LABEL(FILE, NAME); \
1045 } while (0)
1046
1047 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1048 do { assemble_name (FILE, NAME); \
1049 fputs (":\n",FILE); \
1050 } while (0)
1051
1052 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1053 do { fprintf (FILE, "_%s", NAME); \
1054 } while (0)
1055
1056 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1057 do { \
1058 int len = strlen (NAME); \
1059 char *temp = (char *) alloca (len + 4); \
1060 temp[0] = 'L'; \
1061 temp[1] = '_'; \
1062 strcpy (&temp[2], (NAME)); \
1063 temp[len + 2] = '_'; \
1064 temp[len + 3] = 0; \
1065 (OUTPUT) = (char *) alloca (strlen (NAME) + 13); \
1066 sprintf (OUTPUT, "_%s$%d", temp, LABELNO); \
1067 } while (0)
1068
1069 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1070 do { char __buf[256]; \
1071 fprintf (FILE, "\t.dd\t"); \
1072 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1073 assemble_name (FILE, __buf); \
1074 fputc (';', FILE); \
1075 fputc ('\n', FILE); \
1076 } while (0)
1077
1078 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1079 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)
1080
1081 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1082 do { \
1083 char __buf[256]; \
1084 fprintf (FILE, "\t.dd\t"); \
1085 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1086 assemble_name (FILE, __buf); \
1087 fputs (" - ", FILE); \
1088 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \
1089 assemble_name (FILE, __buf); \
1090 fputc (';', FILE); \
1091 fputc ('\n', FILE); \
1092 } while (0)
1093
1094 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1095 do { \
1096 if ((LOG) != 0) \
1097 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
1098 } while (0)
1099
1100 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1101 do { \
1102 asm_output_skip (FILE, SIZE); \
1103 } while (0)
1104
1105 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1106 do { \
1107 data_section(); \
1108 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \
1109 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
1110 ASM_OUTPUT_LABEL (FILE, NAME); \
1111 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \
1112 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \
1113 } while (0)
1114
1115 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1116 do { \
1117 ASM_GLOBALIZE_LABEL1(FILE,NAME); \
1118 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0)
1119
1120 #define ASM_COMMENT_START "//"
1121
1122 #define FUNCTION_PROFILER(FILE, LABELNO) \
1123 do {\
1124 fprintf (FILE, "\tP1.l =LP$%d; P1.h =LP$%d; call mcount;\n", \
1125 LABELNO, LABELNO);\
1126 } while(0)
1127
1128 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO])
1129 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO])
1130
1131 extern struct rtx_def *bfin_compare_op0, *bfin_compare_op1;
1132 extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx;
1133
1134 /* This works for GAS and some other assemblers. */
1135 #define SET_ASM_OP ".set "
1136
1137 /* Don't know how to order these. UNALIGNED_WORD_ASM_OP is in
1138 dwarf2.out. */
1139 #define UNALIGNED_WORD_ASM_OP ".4byte"
1140
1141 /* DBX register number for a given compiler register number */
1142 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1143
1144 #define SIZE_ASM_OP "\t.size\t"
1145
1146 #endif /* _BFIN_CONFIG */