gcc/config/bfin/bfin.h

   1 /* Definitions for the Blackfin port.
   2    Copyright (C) 2005, 2006  Free Software Foundation, Inc.
   3    Contributed by Analog Devices.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 2, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING.  If not, write to
  19    the Free Software Foundation, 51 Franklin Street, Fifth Floor,
  20    Boston, MA 02110-1301, USA.  */
  21
  22 #ifndef _BFIN_CONFIG
  23 #define _BFIN_CONFIG
  24
  25 #define OBJECT_FORMAT_ELF
  26
  27 #define BRT 1
  28 #define BRF 0
  29
  30 /* Print subsidiary information on the compiler version in use.  */
  31 #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)")
  32
  33 /* Run-time compilation parameters selecting different hardware subsets.  */
  34
  35 extern int target_flags;
  36
  37 /* Predefinition in the preprocessor for this target machine */
  38 #ifndef TARGET_CPU_CPP_BUILTINS
  39 #define TARGET_CPU_CPP_BUILTINS()               \
  40   do                                            \
  41     {                                           \
  42       builtin_define ("bfin");                  \
  43       builtin_define ("BFIN");                  \
  44       builtin_define ("__ADSPBLACKFIN__");      \
  45       if (TARGET_ID_SHARED_LIBRARY)             \
  46         builtin_define ("__ID_SHARED_LIB__");   \
  47     }                                           \
  48   while (0)
  49 #endif
  50
  51 /* Generate DSP instructions, like DSP halfword loads */
  52 #define TARGET_DSP                      (1)
  53
  54 #define TARGET_DEFAULT (MASK_SPECLD_ANOMALY | MASK_CSYNC_ANOMALY)
  55
  56 /* Maximum number of library ids we permit */
  57 #define MAX_LIBRARY_ID 255
  58
  59 extern const char *bfin_library_id_string;
  60
  61 /* Sometimes certain combinations of command options do not make
  62    sense on a particular target machine.  You can define a macro
  63    `OVERRIDE_OPTIONS' to take account of this.  This macro, if
  64    defined, is executed once just after all the command options have
  65    been parsed.
  66
  67    Don't use this macro to turn on various extra optimizations for
  68    `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
  69
  70 #define OVERRIDE_OPTIONS override_options ()
  71
  72 #define FUNCTION_MODE    SImode
  73 #define Pmode            SImode
  74
  75 /* store-condition-codes instructions store 0 for false
  76    This is the value stored for true.  */
  77 #define STORE_FLAG_VALUE 1
  78
  79 /* Define this if pushing a word on the stack
  80    makes the stack pointer a smaller address.  */
  81 #define STACK_GROWS_DOWNWARD
  82
  83 #define STACK_PUSH_CODE PRE_DEC
  84
  85 /* Define this to nonzero if the nominal address of the stack frame
  86    is at the high-address end of the local variables;
  87    that is, each additional local variable allocated
  88    goes at a more negative offset in the frame.  */
  89 #define FRAME_GROWS_DOWNWARD 1
  90
  91 /* We define a dummy ARGP register; the parameters start at offset 0 from
  92    it. */
  93 #define FIRST_PARM_OFFSET(DECL) 0
  94
  95 /* Offset within stack frame to start allocating local variables at.
  96    If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
  97    first local allocated.  Otherwise, it is the offset to the BEGINNING
  98    of the first local allocated.  */
  99 #define STARTING_FRAME_OFFSET 0
 100
 101 /* Register to use for pushing function arguments.  */
 102 #define STACK_POINTER_REGNUM REG_P6
 103
 104 /* Base register for access to local variables of the function.  */
 105 #define FRAME_POINTER_REGNUM REG_P7
 106
 107 /* A dummy register that will be eliminated to either FP or SP.  */
 108 #define ARG_POINTER_REGNUM REG_ARGP
 109
 110 /* `PIC_OFFSET_TABLE_REGNUM'
 111      The register number of the register used to address a table of
 112      static data addresses in memory.  In some cases this register is
 113      defined by a processor's "application binary interface" (ABI).
 114      When this macro is defined, RTL is generated for this register
 115      once, as with the stack pointer and frame pointer registers.  If
 116      this macro is not defined, it is up to the machine-dependent files
 117      to allocate such a register (if necessary). */
 118 #define PIC_OFFSET_TABLE_REGNUM (REG_P5)
 119
 120 /* A static chain register for nested functions.  We need to use a
 121    call-clobbered register for this.  */
 122 #define STATIC_CHAIN_REGNUM REG_P2
 123
 124 /* Define this if functions should assume that stack space has been
 125    allocated for arguments even when their values are passed in
 126    registers.
 127
 128    The value of this macro is the size, in bytes, of the area reserved for
 129    arguments passed in registers.
 130
 131    This space can either be allocated by the caller or be a part of the
 132    machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
 133    says which.  */
 134 #define FIXED_STACK_AREA 12
 135 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA
 136
 137 /* Define this if the above stack space is to be considered part of the
 138  * space allocated by the caller.  */
 139 #define OUTGOING_REG_PARM_STACK_SPACE
 140
 141 /* Define this if the maximum size of all the outgoing args is to be
 142    accumulated and pushed during the prologue.  The amount can be
 143    found in the variable current_function_outgoing_args_size. */
 144 #define ACCUMULATE_OUTGOING_ARGS 1
 145
 146 /* Value should be nonzero if functions must have frame pointers.
 147    Zero means the frame pointer need not be set up (and parms
 148    may be accessed via the stack pointer) in functions that seem suitable.
 149    This is computed in `reload', in reload1.c.
 150 */
 151 #define FRAME_POINTER_REQUIRED (bfin_frame_pointer_required ())
 152
 153 #define PARM_BOUNDRY            32
 154
 155 #define STACK_BOUNDRY           32
 156
 157 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */
 158
 159 /* Make strings word-aligned so strcpy from constants will be faster.  */
 160 #define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
 161   (TREE_CODE (EXP) == STRING_CST        \
 162    && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
 163
 164 #define TRAMPOLINE_SIZE 18
 165 #define TRAMPOLINE_TEMPLATE(FILE)                                       \
 166   fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */             \
 167   fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */;           \
 168   fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */;            \
 169   fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */;           \
 170   fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/
 171
 172 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
 173   initialize_trampoline (TRAMP, FNADDR, CXT)
 174 \f
 175 /* Definitions for register eliminations.
 176
 177    This is an array of structures.  Each structure initializes one pair
 178    of eliminable registers.  The "from" register number is given first,
 179    followed by "to".  Eliminations of the same "from" register are listed
 180    in order of preference.
 181
 182    There are two registers that can always be eliminated on the i386.
 183    The frame pointer and the arg pointer can be replaced by either the
 184    hard frame pointer or to the stack pointer, depending upon the
 185    circumstances.  The hard frame pointer is not used before reload and
 186    so it is not eligible for elimination.  */
 187
 188 #define ELIMINABLE_REGS                         \
 189 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},   \
 190  { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},   \
 191  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \
 192
 193 /* Given FROM and TO register numbers, say whether this elimination is
 194    allowed.  Frame pointer elimination is automatically handled.
 195
 196    All other eliminations are valid.  */
 197
 198 #define CAN_ELIMINATE(FROM, TO) \
 199   ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
 200
 201 /* Define the offset between two registers, one to be eliminated, and the other
 202    its replacement, at the start of a routine.  */
 203
 204 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 205   ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO)))
 206 \f
 207 /* This processor has
 208    8 data register for doing arithmetic
 209    8  pointer register for doing addressing, including
 210       1  stack pointer P6
 211       1  frame pointer P7
 212    4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3)
 213    1  condition code flag register CC
 214    5  return address registers RETS/I/X/N/E
 215    1  arithmetic status register (ASTAT).  */
 216
 217 #define FIRST_PSEUDO_REGISTER 44
 218
 219 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X)))
 220 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
 221 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3)
 222 #define D_REGNO_P(X) ((X) <= REG_R7)
 223 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7)
 224 #define I_REGNO_P(X) \
 225   ((X) == REG_I0 || (X) == REG_I1 || (X) == REG_I2 || (X) == REG_I3)
 226
 227 #define REGISTER_NAMES { \
 228   "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
 229   "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \
 230   "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \
 231   "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \
 232   "A0", "A1", \
 233   "CC", \
 234   "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \
 235   "ARGP" \
 236 }
 237
 238 #define SHORT_REGISTER_NAMES { \
 239         "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \
 240         "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \
 241         "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \
 242         "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", }
 243
 244 #define HIGH_REGISTER_NAMES { \
 245         "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \
 246         "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \
 247         "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \
 248         "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", }
 249
 250 #define DREGS_PAIR_NAMES { \
 251   "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0,  }
 252
 253 #define BYTE_REGISTER_NAMES { \
 254   "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",  }
 255
 256
 257 /* 1 for registers that have pervasive standard uses
 258    and are not available for the register allocator.  */
 259
 260 #define FIXED_REGISTERS \
 261 /*r0 r1 r2 r3 r4 r5 r6 r7   p0 p1 p2 p3 p4 p5 p6 p7 */ \
 262 { 0, 0, 0, 0, 0, 0, 0, 0,   0, 0, 0, 0, 0, 0, 1, 0,    \
 263 /*i0 i1 i2 i3 b0 b1 b2 b3   l0 l1 l2 l3 m0 m1 m2 m3 */ \
 264   0, 0, 0, 0, 0, 0, 0, 0,   1, 1, 1, 1, 0, 0, 0, 0,    \
 265 /*a0 a1 cc rets/i/x/n/e     astat seqstat usp argp */ \
 266   0, 0, 0, 1, 1, 1, 1, 1,   1, 1, 1, 1   \
 267 }
 268
 269 /* 1 for registers not available across function calls.
 270    These must include the FIXED_REGISTERS and also any
 271    registers that can be used without being saved.
 272    The latter must include the registers where values are returned
 273    and the register where structure-value addresses are passed.
 274    Aside from that, you can include as many other registers as you like.  */
 275
 276 #define CALL_USED_REGISTERS \
 277 /*r0 r1 r2 r3 r4 r5 r6 r7   p0 p1 p2 p3 p4 p5 p6 p7 */ \
 278 { 1, 1, 1, 1, 0, 0, 0, 0,   1, 1, 1, 0, 0, 0, 1, 0, \
 279 /*i0 i1 i2 i3 b0 b1 b2 b3   l0 l1 l2 l3 m0 m1 m2 m3 */ \
 280   1, 1, 1, 1, 1, 1, 1, 1,   1, 1, 1, 1, 1, 1, 1, 1,   \
 281 /*a0 a1 cc rets/i/x/n/e     astat seqstat usp argp */ \
 282   1, 1, 1, 1, 1, 1, 1, 1,   1, 1, 1, 1   \
 283 }
 284
 285 /* Order in which to allocate registers.  Each register must be
 286    listed once, even those in FIXED_REGISTERS.  List frame pointer
 287    late and fixed registers last.  Note that, in general, we prefer
 288    registers listed in CALL_USED_REGISTERS, keeping the others
 289    available for storage of persistent values. */
 290
 291 #define REG_ALLOC_ORDER \
 292 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \
 293   REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \
 294   REG_A0, REG_A1, \
 295   REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \
 296   REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \
 297   REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE,               \
 298   REG_ASTAT, REG_SEQSTAT, REG_USP,                                \
 299   REG_CC, REG_ARGP                                                \
 300 }
 301
 302 /* Macro to conditionally modify fixed_regs/call_used_regs.  */
 303 #define CONDITIONAL_REGISTER_USAGE                      \
 304   {                                                     \
 305     conditional_register_usage();                       \
 306     if (flag_pic)                                       \
 307       {                                                 \
 308         fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;        \
 309         call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;    \
 310       }                                                 \
 311   }
 312
 313 /* Define the classes of registers for register constraints in the
 314    machine description.  Also define ranges of constants.
 315
 316    One of the classes must always be named ALL_REGS and include all hard regs.
 317    If there is more than one class, another class must be named NO_REGS
 318    and contain no registers.
 319
 320    The name GENERAL_REGS must be the name of a class (or an alias for
 321    another name such as ALL_REGS).  This is the class of registers
 322    that is allowed by "g" or "r" in a register constraint.
 323    Also, registers outside this class are allocated only when
 324    instructions express preferences for them.
 325
 326    The classes must be numbered in nondecreasing order; that is,
 327    a larger-numbered class must never be contained completely
 328    in a smaller-numbered class.
 329
 330    For any two classes, it is very desirable that there be another
 331    class that represents their union. */
 332
 333
 334 enum reg_class
 335 {
 336   NO_REGS,
 337   IREGS,
 338   BREGS,
 339   LREGS,
 340   MREGS,
 341   CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form.  See Automatic Circular Buffering.  */
 342   DAGREGS,
 343   EVEN_AREGS,
 344   ODD_AREGS,
 345   AREGS,
 346   CCREGS,
 347   EVEN_DREGS,
 348   ODD_DREGS,
 349   DREGS,
 350   PREGS_CLOBBERED,
 351   PREGS,
 352   IPREGS,
 353   DPREGS,
 354   MOST_REGS,
 355   PROLOGUE_REGS,
 356   NON_A_CC_REGS,
 357   ALL_REGS, LIM_REG_CLASSES
 358 };
 359
 360 #define N_REG_CLASSES ((int)LIM_REG_CLASSES)
 361
 362 #define GENERAL_REGS DPREGS
 363
 364 /* Give names of register classes as strings for dump file.   */
 365
 366 #define REG_CLASS_NAMES \
 367 {  "NO_REGS",           \
 368    "IREGS",             \
 369    "BREGS",             \
 370    "LREGS",             \
 371    "MREGS",             \
 372    "CIRCREGS",          \
 373    "DAGREGS",           \
 374    "EVEN_AREGS",        \
 375    "ODD_AREGS",         \
 376    "AREGS",             \
 377    "CCREGS",            \
 378    "EVEN_DREGS",        \
 379    "ODD_DREGS",         \
 380    "DREGS",             \
 381    "PREGS_CLOBBERED",   \
 382    "PREGS",             \
 383    "IPREGS",            \
 384    "DPREGS",            \
 385    "MOST_REGS",         \
 386    "PROLOGUE_REGS",     \
 387    "NON_A_CC_REGS",     \
 388    "ALL_REGS" }
 389
 390 /* An initializer containing the contents of the register classes, as integers
 391    which are bit masks.  The Nth integer specifies the contents of class N.
 392    The way the integer MASK is interpreted is that register R is in the class
 393    if `MASK & (1 << R)' is 1.
 394
 395    When the machine has more than 32 registers, an integer does not suffice.
 396    Then the integers are replaced by sub-initializers, braced groupings
 397    containing several integers.  Each sub-initializer must be suitable as an
 398    initializer for the type `HARD_REG_SET' which is defined in
 399    `hard-reg-set.h'.  */
 400
 401 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS.  We use
 402    MOST_REGS as the union of DPREGS and DAGREGS.  */
 403
 404 #define REG_CLASS_CONTENTS \
 405     /* 31 - 0       63-32   */ \
 406 {   { 0x00000000,    0 },               /* NO_REGS */   \
 407     { 0x000f0000,    0 },               /* IREGS */     \
 408     { 0x00f00000,    0 },               /* BREGS */             \
 409     { 0x0f000000,    0 },               /* LREGS */     \
 410     { 0xf0000000,    0 },               /* MREGS */   \
 411     { 0x0fff0000,    0 },               /* CIRCREGS */   \
 412     { 0xffff0000,    0 },               /* DAGREGS */   \
 413     { 0x00000000,    0x1 },             /* EVEN_AREGS */   \
 414     { 0x00000000,    0x2 },             /* ODD_AREGS */   \
 415     { 0x00000000,    0x3 },             /* AREGS */   \
 416     { 0x00000000,    0x4 },             /* CCREGS */  \
 417     { 0x00000055,    0 },               /* EVEN_DREGS */   \
 418     { 0x000000aa,    0 },               /* ODD_DREGS */   \
 419     { 0x000000ff,    0 },               /* DREGS */   \
 420     { 0x00004700,    0x800 },           /* PREGS_CLOBBERED */   \
 421     { 0x0000ff00,    0x800 },           /* PREGS */   \
 422     { 0x000fff00,    0x800 },           /* IPREGS */    \
 423     { 0x0000ffff,    0x800 },           /* DPREGS */   \
 424     { 0xffffffff,    0x800 },           /* MOST_REGS */\
 425     { 0x00000000,    0x7f8 },           /* PROLOGUE_REGS */\
 426     { 0xffffffff,    0xff8 },           /* NON_A_CC_REGS */\
 427     { 0xffffffff,    0xfff }}           /* ALL_REGS */
 428
 429 #define IREG_POSSIBLE_P(OUTER)                               \
 430   ((OUTER) == POST_INC || (OUTER) == PRE_INC                 \
 431    || (OUTER) == POST_DEC || (OUTER) == PRE_DEC              \
 432    || (OUTER) == MEM || (OUTER) == ADDRESS)
 433
 434 #define MODE_CODE_BASE_REG_CLASS(MODE, OUTER, INDEX)                    \
 435   ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS)
 436
 437 #define INDEX_REG_CLASS         PREGS
 438
 439 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX)       \
 440   (P_REGNO_P (X) || (X) == REG_ARGP                             \
 441    || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode              \
 442        && I_REGNO_P (X)))
 443
 444 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX)    \
 445   ((X) >= FIRST_PSEUDO_REGISTER                                 \
 446    || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX))
 447
 448 #ifdef REG_OK_STRICT
 449 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
 450   REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)
 451 #else
 452 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
 453   REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX)
 454 #endif
 455
 456 #define REGNO_OK_FOR_INDEX_P(X)   0
 457
 458 /* Get reg_class from a letter such as appears in the machine description.  */
 459
 460 #define REG_CLASS_FROM_LETTER(LETTER)   \
 461   ((LETTER) == 'a' ? PREGS :            \
 462    (LETTER) == 'd' ? DREGS :            \
 463    (LETTER) == 'z' ? PREGS_CLOBBERED :  \
 464    (LETTER) == 'D' ? EVEN_DREGS :       \
 465    (LETTER) == 'W' ? ODD_DREGS :        \
 466    (LETTER) == 'e' ? AREGS :            \
 467    (LETTER) == 'A' ? EVEN_AREGS :       \
 468    (LETTER) == 'B' ? ODD_AREGS :        \
 469    (LETTER) == 'b' ? IREGS :            \
 470    (LETTER) == 'B' ? BREGS :            \
 471    (LETTER) == 'f' ? MREGS :            \
 472    (LETTER) == 'c' ? CIRCREGS :         \
 473    (LETTER) == 'C' ? CCREGS :           \
 474    (LETTER) == 'x' ? MOST_REGS :        \
 475    (LETTER) == 'y' ? PROLOGUE_REGS :    \
 476    (LETTER) == 'w' ? NON_A_CC_REGS :    \
 477    NO_REGS)
 478
 479 /* The same information, inverted:
 480    Return the class number of the smallest class containing
 481    reg number REGNO.  This could be a conditional expression
 482    or could index an array.  */
 483
 484 #define REGNO_REG_CLASS(REGNO) \
 485  ((REGNO) < REG_P0 ? DREGS                              \
 486  : (REGNO) < REG_I0 ? PREGS                             \
 487  : (REGNO) == REG_ARGP ? PREGS                          \
 488  : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS       \
 489  : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS       \
 490  : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS       \
 491  : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS       \
 492  : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS       \
 493  : (REGNO) == REG_CC ? CCREGS                           \
 494  : (REGNO) >= REG_RETS ? PROLOGUE_REGS                  \
 495  : NO_REGS)
 496
 497 /* When defined, the compiler allows registers explicitly used in the
 498    rtl to be used as spill registers but prevents the compiler from
 499    extending the lifetime of these registers. */
 500 #define SMALL_REGISTER_CLASSES 1
 501
 502 #define CLASS_LIKELY_SPILLED_P(CLASS) \
 503     ((CLASS) == PREGS_CLOBBERED \
 504      || (CLASS) == PROLOGUE_REGS \
 505      || (CLASS) == CCREGS)
 506
 507 /* Do not allow to store a value in REG_CC for any mode */
 508 /* Do not allow to store value in pregs if mode is not SI*/
 509 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
 510
 511 /* Return the maximum number of consecutive registers
 512    needed to represent mode MODE in a register of class CLASS.  */
 513 #define CLASS_MAX_NREGS(CLASS, MODE)                                    \
 514   ((MODE) == V2PDImode && (CLASS) == AREGS ? 2                          \
 515    : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
 516
 517 #define HARD_REGNO_NREGS(REGNO, MODE) \
 518   ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1    \
 519    : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \
 520    : CLASS_MAX_NREGS (GENERAL_REGS, MODE))
 521
 522 /* A C expression that is nonzero if hard register TO can be
 523    considered for use as a rename register for FROM register */
 524 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO)
 525
 526 /* A C expression that is nonzero if it is desirable to choose
 527    register allocation so as to avoid move instructions between a
 528    value of mode MODE1 and a value of mode MODE2.
 529
 530    If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
 531    MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
 532    MODE2)' must be zero. */
 533 #define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2))
 534
 535 /* `PREFERRED_RELOAD_CLASS (X, CLASS)'
 536    A C expression that places additional restrictions on the register
 537    class to use when it is necessary to copy value X into a register
 538    in class CLASS.  The value is a register class; perhaps CLASS, or
 539    perhaps another, smaller class.  */
 540 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
 541
 542 /* Function Calling Conventions. */
 543
 544 /* The type of the current function; normal functions are of type
 545    SUBROUTINE.  */
 546 typedef enum {
 547   SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER
 548 } e_funkind;
 549
 550 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 }
 551
 552 /* Flags for the call/call_value rtl operations set up by function_arg */
 553 #define CALL_NORMAL             0x00000000      /* no special processing */
 554 #define CALL_LONG               0x00000001      /* always call indirect */
 555 #define CALL_SHORT              0x00000002      /* always call by symbol */
 556
 557 typedef struct {
 558   int words;                    /* # words passed so far */
 559   int nregs;                    /* # registers available for passing */
 560   int *arg_regs;                /* array of register -1 terminated */
 561   int call_cookie;              /* Do special things for this call */
 562 } CUMULATIVE_ARGS;
 563
 564 /* Define where to put the arguments to a function.
 565    Value is zero to push the argument on the stack,
 566    or a hard register in which to store the argument.
 567
 568    MODE is the argument's machine mode.
 569    TYPE is the data type of the argument (as a tree).
 570     This is null for libcalls where that information may
 571     not be available.
 572    CUM is a variable of type CUMULATIVE_ARGS which gives info about
 573     the preceding args and about the function being called.
 574    NAMED is nonzero if this argument is a named parameter
 575     (otherwise it is an extra parameter matching an ellipsis).  */
 576
 577 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
 578   (function_arg (&CUM, MODE, TYPE, NAMED))
 579
 580 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO)
 581
 582
 583 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 584    for a call to a function whose data type is FNTYPE.
 585    For a library call, FNTYPE is 0.  */
 586 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \
 587   (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
 588
 589 /* Update the data in CUM to advance over an argument
 590    of mode MODE and data type TYPE.
 591    (TYPE is null for libcalls where that information may not be available.)  */
 592 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)    \
 593   (function_arg_advance (&CUM, MODE, TYPE, NAMED))
 594
 595 #define RETURN_POPS_ARGS(FDECL, FUNTYPE, STKSIZE) 0
 596
 597 /* Define how to find the value returned by a function.
 598    VALTYPE is the data type of the value (as a tree).
 599    If the precise function being called is known, FUNC is its FUNCTION_DECL;
 600    otherwise, FUNC is 0.
 601 */
 602
 603 #define VALUE_REGNO(MODE) (REG_R0)
 604
 605 #define FUNCTION_VALUE(VALTYPE, FUNC)           \
 606   gen_rtx_REG (TYPE_MODE (VALTYPE),             \
 607                VALUE_REGNO(TYPE_MODE(VALTYPE)))
 608
 609 /* Define how to find the value returned by a library function
 610    assuming the value has mode MODE.  */
 611
 612 #define LIBCALL_VALUE(MODE)  gen_rtx_REG (MODE, VALUE_REGNO(MODE))
 613
 614 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0)
 615
 616 #define DEFAULT_PCC_STRUCT_RETURN 0
 617 #define RETURN_IN_MEMORY(TYPE) bfin_return_in_memory(TYPE)
 618
 619 /* Before the prologue, the return address is in the RETS register.  */
 620 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS)
 621
 622 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT)
 623
 624 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS)
 625
 626 /* Call instructions don't modify the stack pointer on the Blackfin.  */
 627 #define INCOMING_FRAME_SP_OFFSET 0
 628
 629 /* Describe how we implement __builtin_eh_return.  */
 630 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
 631 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, REG_P2)
 632 #define EH_RETURN_HANDLER_RTX \
 633     gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD))
 634
 635 /* Addressing Modes */
 636
 637 /* Recognize any constant value that is a valid address.  */
 638 #define CONSTANT_ADDRESS_P(X)   (CONSTANT_P (X))
 639
 640 /* Nonzero if the constant value X is a legitimate general operand.
 641    symbol_ref are not legitimate and will be put into constant pool.
 642    See force_const_mem().
 643    If -mno-pool, all constants are legitimate.
 644  */
 645 #define LEGITIMATE_CONSTANT_P(x) 1
 646
 647 /*   A number, the maximum number of registers that can appear in a
 648      valid memory address.  Note that it is up to you to specify a
 649      value equal to the maximum number that `GO_IF_LEGITIMATE_ADDRESS'
 650      would ever accept. */
 651 #define MAX_REGS_PER_ADDRESS 1
 652
 653 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
 654    that is a valid memory address for an instruction.
 655    The MODE argument is the machine mode for the MEM expression
 656    that wants to use this address.
 657
 658    Blackfin addressing modes are as follows:
 659
 660       [preg]
 661       [preg + imm16]
 662
 663       B [ Preg + uimm15 ]
 664       W [ Preg + uimm16m2 ]
 665       [ Preg + uimm17m4 ]
 666
 667       [preg++]
 668       [preg--]
 669       [--sp]
 670 */
 671
 672 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \
 673       (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode)
 674
 675 #ifdef REG_OK_STRICT
 676 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN)          \
 677   do {                                                  \
 678     if (bfin_legitimate_address_p (MODE, X, 1))         \
 679       goto WIN;                                         \
 680   } while (0);
 681 #else
 682 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN)          \
 683   do {                                                  \
 684     if (bfin_legitimate_address_p (MODE, X, 0))         \
 685       goto WIN;                                         \
 686   } while (0);
 687 #endif
 688
 689 /* Try machine-dependent ways of modifying an illegitimate address
 690    to be legitimate.  If we find one, return the new, valid address.
 691    This macro is used in only one place: `memory_address' in explow.c.
 692
 693    OLDX is the address as it was before break_out_memory_refs was called.
 694    In some cases it is useful to look at this to decide what needs to be done.
 695
 696    MODE and WIN are passed so that this macro can use
 697    GO_IF_LEGITIMATE_ADDRESS.
 698
 699    It is always safe for this macro to do nothing.  It exists to recognize
 700    opportunities to optimize the output.
 701  */
 702 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)    \
 703 do {                                           \
 704    rtx _q = legitimize_address(X, OLDX, MODE); \
 705    if (_q) { X = _q; goto WIN; }               \
 706 } while (0)
 707
 708 #define HAVE_POST_INCREMENT 1
 709 #define HAVE_POST_DECREMENT 1
 710 #define HAVE_PRE_DECREMENT  1
 711
 712 /* `LEGITIMATE_PIC_OPERAND_P (X)'
 713      A C expression that is nonzero if X is a legitimate immediate
 714      operand on the target machine when generating position independent
 715      code.  You can assume that X satisfies `CONSTANT_P', so you need
 716      not check this.  You can also assume FLAG_PIC is true, so you need
 717      not check it either.  You need not define this macro if all
 718      constants (including `SYMBOL_REF') can be immediate operands when
 719      generating position independent code. */
 720 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X)
 721
 722 #define SYMBOLIC_CONST(X)       \
 723 (GET_CODE (X) == SYMBOL_REF                                             \
 724  || GET_CODE (X) == LABEL_REF                                           \
 725  || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
 726
 727 /*
 728      A C statement or compound statement with a conditional `goto
 729      LABEL;' executed if memory address X (an RTX) can have different
 730      meanings depending on the machine mode of the memory reference it
 731      is used for or if the address is valid for some modes but not
 732      others.
 733
 734      Autoincrement and autodecrement addresses typically have
 735      mode-dependent effects because the amount of the increment or
 736      decrement is the size of the operand being addressed.  Some
 737      machines have other mode-dependent addresses.  Many RISC machines
 738      have no mode-dependent addresses.
 739
 740      You may assume that ADDR is a valid address for the machine.
 741 */
 742 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)  \
 743 do {                                              \
 744  if (GET_CODE (ADDR) == POST_INC                  \
 745      || GET_CODE (ADDR) == POST_DEC               \
 746      || GET_CODE (ADDR) == PRE_DEC)               \
 747    goto LABEL;                                    \
 748 } while (0)
 749
 750 #define NOTICE_UPDATE_CC(EXPR, INSN) 0
 751
 752 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
 753    is done just by pretending it is already truncated.  */
 754 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 755
 756 /* Max number of bytes we can move from memory to memory
 757    in one reasonably fast instruction.  */
 758 #define MOVE_MAX UNITS_PER_WORD
 759
 760
 761 /* STORAGE LAYOUT: target machine storage layout
 762    Define this macro as a C expression which is nonzero if accessing
 763    less than a word of memory (i.e. a `char' or a `short') is no
 764    faster than accessing a word of memory, i.e., if such access
 765    require more than one instruction or if there is no difference in
 766    cost between byte and (aligned) word loads.
 767
 768    When this macro is not defined, the compiler will access a field by
 769    finding the smallest containing object; when it is defined, a
 770    fullword load will be used if alignment permits.  Unless bytes
 771    accesses are faster than word accesses, using word accesses is
 772    preferable since it may eliminate subsequent memory access if
 773    subsequent accesses occur to other fields in the same word of the
 774    structure, but to different bytes.  */
 775 #define SLOW_BYTE_ACCESS  0
 776 #define SLOW_SHORT_ACCESS 0
 777
 778 /* Define this if most significant bit is lowest numbered
 779    in instructions that operate on numbered bit-fields. */
 780 #define BITS_BIG_ENDIAN  0
 781
 782 /* Define this if most significant byte of a word is the lowest numbered.
 783    We can't access bytes but if we could we would in the Big Endian order. */
 784 #define BYTES_BIG_ENDIAN 0
 785
 786 /* Define this if most significant word of a multiword number is numbered. */
 787 #define WORDS_BIG_ENDIAN 0
 788
 789 /* number of bits in an addressable storage unit */
 790 #define BITS_PER_UNIT 8
 791
 792 /* Width in bits of a "word", which is the contents of a machine register.
 793    Note that this is not necessarily the width of data type `int';
 794    if using 16-bit ints on a 68000, this would still be 32.
 795    But on a machine with 16-bit registers, this would be 16.  */
 796 #define BITS_PER_WORD 32
 797
 798 /* Width of a word, in units (bytes).  */
 799 #define UNITS_PER_WORD 4
 800
 801 /* Width in bits of a pointer.
 802    See also the macro `Pmode1' defined below.  */
 803 #define POINTER_SIZE 32
 804
 805 /* Allocation boundary (in *bits*) for storing pointers in memory.  */
 806 #define POINTER_BOUNDARY 32
 807
 808 /* Allocation boundary (in *bits*) for storing arguments in argument list.  */
 809 #define PARM_BOUNDARY 32
 810
 811 /* Boundary (in *bits*) on which stack pointer should be aligned.  */
 812 #define STACK_BOUNDARY 32
 813
 814 /* Allocation boundary (in *bits*) for the code of a function.  */
 815 #define FUNCTION_BOUNDARY 32
 816
 817 /* Alignment of field after `int : 0' in a structure.  */
 818 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
 819
 820 /* No data type wants to be aligned rounder than this.  */
 821 #define BIGGEST_ALIGNMENT 32
 822
 823 /* Define this if move instructions will actually fail to work
 824    when given unaligned data.  */
 825 #define STRICT_ALIGNMENT 1
 826
 827 /* (shell-command "rm c-decl.o stor-layout.o")
 828  *  never define PCC_BITFIELD_TYPE_MATTERS
 829  *  really cause some alignment problem
 830  */
 831
 832 #define UNITS_PER_FLOAT  ((FLOAT_TYPE_SIZE  + BITS_PER_UNIT - 1) / \
 833                            BITS_PER_UNIT)
 834
 835 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \
 836                            BITS_PER_UNIT)
 837
 838
 839 /* what is the 'type' of size_t */
 840 #define SIZE_TYPE "long unsigned int"
 841
 842 /* Define this as 1 if `char' should by default be signed; else as 0.  */
 843 #define DEFAULT_SIGNED_CHAR 1
 844 #define FLOAT_TYPE_SIZE BITS_PER_WORD
 845 #define SHORT_TYPE_SIZE 16
 846 #define CHAR_TYPE_SIZE  8
 847 #define INT_TYPE_SIZE   32
 848 #define LONG_TYPE_SIZE  32
 849 #define LONG_LONG_TYPE_SIZE 64
 850
 851 /* Note: Fix this to depend on target switch. -- lev */
 852
 853 /* Note: Try to implement double and force long double. -- tonyko
 854  * #define __DOUBLES_ARE_FLOATS__
 855  * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE
 856  * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
 857  * #define DOUBLES_ARE_FLOATS 1
 858  */
 859
 860 #define DOUBLE_TYPE_SIZE        64
 861 #define LONG_DOUBLE_TYPE_SIZE   64
 862
 863 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)'
 864      A macro to update M and UNSIGNEDP when an object whose type is
 865      TYPE and which has the specified mode and signedness is to be
 866      stored in a register.  This macro is only called when TYPE is a
 867      scalar type.
 868
 869      On most RISC machines, which only have operations that operate on
 870      a full register, define this macro to set M to `word_mode' if M is
 871      an integer mode narrower than `BITS_PER_WORD'.  In most cases,
 872      only integer modes should be widened because wider-precision
 873      floating-point operations are usually more expensive than their
 874      narrower counterparts.
 875
 876      For most machines, the macro definition does not change UNSIGNEDP.
 877      However, some machines, have instructions that preferentially
 878      handle either signed or unsigned quantities of certain modes.  For
 879      example, on the DEC Alpha, 32-bit loads from memory and 32-bit add
 880      instructions sign-extend the result to 64 bits.  On such machines,
 881      set UNSIGNEDP according to which kind of extension is more
 882      efficient.
 883
 884      Do not define this macro if it would never modify M.*/
 885
 886 #define BFIN_PROMOTE_MODE_P(MODE) \
 887     (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT   \
 888       && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)
 889
 890 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
 891   if (BFIN_PROMOTE_MODE_P(MODE))                \
 892     {                                           \
 893       if (MODE == QImode)                       \
 894         UNSIGNEDP = 1;                          \
 895       else if (MODE == HImode)                  \
 896         UNSIGNEDP = 0;                          \
 897       (MODE) = SImode;                          \
 898     }
 899
 900 /* Describing Relative Costs of Operations */
 901
 902 /* Do not put function addr into constant pool */
 903 #define NO_FUNCTION_CSE 1
 904
 905 /* A C expression for the cost of moving data from a register in class FROM to
 906    one in class TO.  The classes are expressed using the enumeration values
 907    such as `GENERAL_REGS'.  A value of 2 is the default; other values are
 908    interpreted relative to that.
 909
 910    It is not required that the cost always equal 2 when FROM is the same as TO;
 911    on some machines it is expensive to move between registers if they are not
 912    general registers.  */
 913
 914 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
 915    bfin_register_move_cost ((MODE), (CLASS1), (CLASS2))
 916
 917 /* A C expression for the cost of moving data of mode M between a
 918    register and memory.  A value of 2 is the default; this cost is
 919    relative to those in `REGISTER_MOVE_COST'.
 920
 921    If moving between registers and memory is more expensive than
 922    between two registers, you should define this macro to express the
 923    relative cost.  */
 924
 925 #define MEMORY_MOVE_COST(MODE, CLASS, IN)       \
 926   bfin_memory_move_cost ((MODE), (CLASS), (IN))
 927
 928 /* Specify the machine mode that this machine uses
 929    for the index in the tablejump instruction.  */
 930 #define CASE_VECTOR_MODE SImode
 931
 932 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
 933
 934 /* Define if operations between registers always perform the operation
 935    on the full register even if a narrower mode is specified.
 936 #define WORD_REGISTER_OPERATIONS
 937 */
 938
 939 #define CONST_18UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 262140)
 940 #define CONST_16BIT_IMM_P(VALUE) ((VALUE) >= -32768 && (VALUE) <= 32767)
 941 #define CONST_16UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 65535)
 942 #define CONST_7BIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 63)
 943 #define CONST_7NBIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 0)
 944 #define CONST_5UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 31)
 945 #define CONST_4BIT_IMM_P(VALUE) ((VALUE) >= -8 && (VALUE) <= 7)
 946 #define CONST_4UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 15)
 947 #define CONST_3BIT_IMM_P(VALUE) ((VALUE) >= -4 && (VALUE) <= 3)
 948 #define CONST_3UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 7)
 949
 950 #define CONSTRAINT_LEN(C, STR)                  \
 951     ((C) == 'P' || (C) == 'M' || (C) == 'N' ? 2 \
 952      : (C) == 'K' ? 3                           \
 953      : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
 954
 955 #define CONST_OK_FOR_P(VALUE, STR)    \
 956     ((STR)[1] == '0' ? (VALUE) == 0   \
 957      : (STR)[1] == '1' ? (VALUE) == 1 \
 958      : (STR)[1] == '2' ? (VALUE) == 2 \
 959      : (STR)[1] == '3' ? (VALUE) == 3 \
 960      : (STR)[1] == '4' ? (VALUE) == 4 \
 961      : 0)
 962
 963 #define CONST_OK_FOR_K(VALUE, STR)                      \
 964     ((STR)[1] == 'u'                                    \
 965      ? ((STR)[2] == '3' ? CONST_3UBIT_IMM_P (VALUE)     \
 966         : (STR)[2] == '4' ? CONST_4UBIT_IMM_P (VALUE)   \
 967         : (STR)[2] == '5' ? CONST_5UBIT_IMM_P (VALUE)   \
 968         : (STR)[2] == 'h' ? CONST_16UBIT_IMM_P (VALUE)  \
 969         : 0)                                            \
 970      : (STR)[1] == 's'                                  \
 971      ? ((STR)[2] == '3' ? CONST_3BIT_IMM_P (VALUE)      \
 972         : (STR)[2] == '4' ? CONST_4BIT_IMM_P (VALUE)    \
 973         : (STR)[2] == '7' ? CONST_7BIT_IMM_P (VALUE)    \
 974         : (STR)[2] == 'h' ? CONST_16BIT_IMM_P (VALUE)   \
 975         : 0)                                            \
 976      : (STR)[1] == 'n'                                  \
 977      ? ((STR)[2] == '7' ? CONST_7NBIT_IMM_P (VALUE)     \
 978         : 0)                                            \
 979      : 0)
 980
 981 #define CONST_OK_FOR_M(VALUE, STR)                      \
 982     ((STR)[1] == '1' ? (VALUE) == 255                   \
 983      : (STR)[1] == '2' ? (VALUE) == 65535               \
 984      : 0)
 985
 986 /* The letters I, J, K, L and M in a register constraint string
 987    can be used to stand for particular ranges of immediate operands.
 988    This macro defines what the ranges are.
 989    C is the letter, and VALUE is a constant value.
 990    Return 1 if VALUE is in the range specified by C.
 991
 992    bfin constant operands are as follows
 993
 994      J   2**N       5bit imm scaled
 995      Ks7 -64 .. 63  signed 7bit imm
 996      Ku5 0..31      unsigned 5bit imm
 997      Ks4 -8 .. 7    signed 4bit imm
 998      Ks3 -4 .. 3    signed 3bit imm
 999      Ku3 0 .. 7     unsigned 3bit imm
1000      Pn  0, 1, 2    constants 0, 1 or 2, corresponding to n
1001 */
1002 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR)                \
1003   ((C) == 'J' ? (log2constp (VALUE))                            \
1004    : (C) == 'K' ? CONST_OK_FOR_K (VALUE, STR)                   \
1005    : (C) == 'L' ? log2constp (~(VALUE))                         \
1006    : (C) == 'M' ? CONST_OK_FOR_M (VALUE, STR)                   \
1007    : (C) == 'P' ? CONST_OK_FOR_P (VALUE, STR)                   \
1008    : 0)
1009
1010      /*Constant Output Formats */
1011 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  \
1012   ((C) == 'H' ? 1 : 0)
1013
1014 #define EXTRA_CONSTRAINT(VALUE, D) \
1015     ((D) == 'Q' ? GET_CODE (VALUE) == SYMBOL_REF : 0)
1016
1017 /* Switch into a generic section.  */
1018 #define TARGET_ASM_NAMED_SECTION  default_elf_asm_named_section
1019
1020 #define PRINT_OPERAND(FILE, RTX, CODE)   print_operand (FILE, RTX, CODE)
1021 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX)
1022
1023 typedef enum sections {
1024     CODE_DIR,
1025     DATA_DIR,
1026     LAST_SECT_NM
1027 } SECT_ENUM_T;
1028
1029 typedef enum directives {
1030     LONG_CONST_DIR,
1031     SHORT_CONST_DIR,
1032     BYTE_CONST_DIR,
1033     SPACE_DIR,
1034     INIT_DIR,
1035     LAST_DIR_NM
1036 } DIR_ENUM_T;
1037
1038 #define TEXT_SECTION_ASM_OP ".text;"
1039 #define DATA_SECTION_ASM_OP ".data;"
1040
1041 #define ASM_APP_ON  ""
1042 #define ASM_APP_OFF ""
1043
1044 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \
1045   do {  fputs (".global ", FILE);               \
1046         assemble_name (FILE, NAME);             \
1047         fputc (';',FILE);                       \
1048         fputc ('\n',FILE);                      \
1049       } while (0)
1050
1051 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1052   do {                                  \
1053     fputs (".type ", FILE);             \
1054     assemble_name (FILE, NAME);         \
1055     fputs (", STT_FUNC", FILE);         \
1056     fputc (';',FILE);                   \
1057     fputc ('\n',FILE);                  \
1058     ASM_OUTPUT_LABEL(FILE, NAME);       \
1059   } while (0)
1060
1061 #define ASM_OUTPUT_LABEL(FILE, NAME)    \
1062   do {  assemble_name (FILE, NAME);             \
1063         fputs (":\n",FILE);                     \
1064       } while (0)
1065
1066 #define ASM_OUTPUT_LABELREF(FILE,NAME)  \
1067     do {  fprintf (FILE, "_%s", NAME); \
1068         } while (0)
1069
1070 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)            \
1071 do { char __buf[256];                                   \
1072      fprintf (FILE, "\t.dd\t");                         \
1073      ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE);   \
1074      assemble_name (FILE, __buf);                       \
1075      fputc (';', FILE);                                 \
1076      fputc ('\n', FILE);                                \
1077    } while (0)
1078
1079 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1080     MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)
1081
1082 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)           \
1083     do {                                                        \
1084         char __buf[256];                                        \
1085         fprintf (FILE, "\t.dd\t");                              \
1086         ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE);        \
1087         assemble_name (FILE, __buf);                            \
1088         fputs (" - ", FILE);                                    \
1089         ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL);          \
1090         assemble_name (FILE, __buf);                            \
1091         fputc (';', FILE);                                      \
1092         fputc ('\n', FILE);                                     \
1093     } while (0)
1094
1095 #define ASM_OUTPUT_ALIGN(FILE,LOG)                              \
1096     do {                                                        \
1097       if ((LOG) != 0)                                           \
1098         fprintf (FILE, "\t.align %d\n", 1 << (LOG));            \
1099     } while (0)
1100
1101 #define ASM_OUTPUT_SKIP(FILE,SIZE)              \
1102     do {                                        \
1103         asm_output_skip (FILE, SIZE);           \
1104     } while (0)
1105
1106 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)     \
1107 do {                                            \
1108     switch_to_section (data_section);                           \
1109     if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2);  \
1110     ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE);               \
1111     ASM_OUTPUT_LABEL (FILE, NAME);                              \
1112     fprintf (FILE, "%s %ld;\n", ASM_SPACE,                      \
1113              (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1);     \
1114 } while (0)
1115
1116 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)    \
1117      do {                                               \
1118         ASM_GLOBALIZE_LABEL1(FILE,NAME);                \
1119         ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0)
1120
1121 #define ASM_COMMENT_START "//"
1122
1123 #define FUNCTION_PROFILER(FILE, LABELNO) \
1124   do {\
1125     fprintf (FILE, "\tP1.l =LP$%d; P1.h =LP$%d; call mcount;\n", \
1126        LABELNO, LABELNO);\
1127   } while(0)
1128
1129 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO])
1130 #define ASM_OUTPUT_REG_POP(FILE, REGNO)  fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO])
1131
1132 extern struct rtx_def *bfin_compare_op0, *bfin_compare_op1;
1133 extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx;
1134
1135 /* This works for GAS and some other assemblers.  */
1136 #define SET_ASM_OP              ".set "
1137
1138 /* DBX register number for a given compiler register number */
1139 #define DBX_REGISTER_NUMBER(REGNO)  (REGNO)
1140
1141 #define SIZE_ASM_OP     "\t.size\t"
1142
1143 #endif /*  _BFIN_CONFIG */