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bfin.opt (mfdpic): New option.
[gcc.git] / gcc / config / bfin / bfin.h
1 /* Definitions for the Blackfin port.
2 Copyright (C) 2005 Free Software Foundation, Inc.
3 Contributed by Analog Devices.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
21
22 #ifndef _BFIN_CONFIG
23 #define _BFIN_CONFIG
24
25 #define OBJECT_FORMAT_ELF
26
27 #define BRT 1
28 #define BRF 0
29
30 /* Print subsidiary information on the compiler version in use. */
31 #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)")
32
33 /* Run-time compilation parameters selecting different hardware subsets. */
34
35 extern int target_flags;
36
37 /* Predefinition in the preprocessor for this target machine */
38 #ifndef TARGET_CPU_CPP_BUILTINS
39 #define TARGET_CPU_CPP_BUILTINS() \
40 do \
41 { \
42 builtin_define ("bfin"); \
43 builtin_define ("BFIN"); \
44 builtin_define ("__ADSPBLACKFIN__"); \
45 if (TARGET_FDPIC) \
46 builtin_define ("__BFIN_FDPIC__"); \
47 if (TARGET_ID_SHARED_LIBRARY) \
48 builtin_define ("__ID_SHARED_LIB__"); \
49 } \
50 while (0)
51 #endif
52
53 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\
54 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
55 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \
56 "
57 #ifndef SUBTARGET_DRIVER_SELF_SPECS
58 # define SUBTARGET_DRIVER_SELF_SPECS
59 #endif
60
61 #define LINK_GCC_C_SEQUENCE_SPEC \
62 "%{mfdpic:%{!static: %L} %{static: %G %L %G}} \
63 %{!mfdpic:%G %L %G}"
64
65 /* A C string constant that tells the GCC driver program options to pass to
66 the assembler. It can also specify how to translate options you give to GNU
67 CC into options for GCC to pass to the assembler. See the file `sun3.h'
68 for an example of this.
69
70 Do not define this macro if it does not need to do anything.
71
72 Defined in svr4.h. */
73 #undef ASM_SPEC
74 #define ASM_SPEC "\
75 %{G*} %{v} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \
76 %{mno-fdpic:-mnopic} %{mfdpic}"
77
78 #define LINK_SPEC "\
79 %{h*} %{v:-V} \
80 %{b} \
81 %{mfdpic:-melf32bfinfd -z text} \
82 %{static:-dn -Bstatic} \
83 %{shared:-G -Bdynamic} \
84 %{symbolic:-Bsymbolic} \
85 %{G*} \
86 %{YP,*} \
87 %{Qy:} %{!Qn:-Qy} \
88 -init __init -fini __fini "
89
90 /* Generate DSP instructions, like DSP halfword loads */
91 #define TARGET_DSP (1)
92
93 #define TARGET_DEFAULT (MASK_SPECLD_ANOMALY | MASK_CSYNC_ANOMALY)
94
95 /* Maximum number of library ids we permit */
96 #define MAX_LIBRARY_ID 255
97
98 extern const char *bfin_library_id_string;
99
100 /* Sometimes certain combinations of command options do not make
101 sense on a particular target machine. You can define a macro
102 `OVERRIDE_OPTIONS' to take account of this. This macro, if
103 defined, is executed once just after all the command options have
104 been parsed.
105
106 Don't use this macro to turn on various extra optimizations for
107 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
108
109 #define OVERRIDE_OPTIONS override_options ()
110
111 #define FUNCTION_MODE SImode
112 #define Pmode SImode
113
114 /* store-condition-codes instructions store 0 for false
115 This is the value stored for true. */
116 #define STORE_FLAG_VALUE 1
117
118 /* Define this if pushing a word on the stack
119 makes the stack pointer a smaller address. */
120 #define STACK_GROWS_DOWNWARD
121
122 #define STACK_PUSH_CODE PRE_DEC
123
124 /* Define this to nonzero if the nominal address of the stack frame
125 is at the high-address end of the local variables;
126 that is, each additional local variable allocated
127 goes at a more negative offset in the frame. */
128 #define FRAME_GROWS_DOWNWARD 1
129
130 /* We define a dummy ARGP register; the parameters start at offset 0 from
131 it. */
132 #define FIRST_PARM_OFFSET(DECL) 0
133
134 /* Offset within stack frame to start allocating local variables at.
135 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
136 first local allocated. Otherwise, it is the offset to the BEGINNING
137 of the first local allocated. */
138 #define STARTING_FRAME_OFFSET 0
139
140 /* Register to use for pushing function arguments. */
141 #define STACK_POINTER_REGNUM REG_P6
142
143 /* Base register for access to local variables of the function. */
144 #define FRAME_POINTER_REGNUM REG_P7
145
146 /* A dummy register that will be eliminated to either FP or SP. */
147 #define ARG_POINTER_REGNUM REG_ARGP
148
149 /* `PIC_OFFSET_TABLE_REGNUM'
150 The register number of the register used to address a table of
151 static data addresses in memory. In some cases this register is
152 defined by a processor's "application binary interface" (ABI).
153 When this macro is defined, RTL is generated for this register
154 once, as with the stack pointer and frame pointer registers. If
155 this macro is not defined, it is up to the machine-dependent files
156 to allocate such a register (if necessary). */
157 #define PIC_OFFSET_TABLE_REGNUM (REG_P5)
158
159 #define FDPIC_FPTR_REGNO REG_P1
160 #define FDPIC_REGNO REG_P3
161 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
162
163 /* A static chain register for nested functions. We need to use a
164 call-clobbered register for this. */
165 #define STATIC_CHAIN_REGNUM REG_P2
166
167 /* Define this if functions should assume that stack space has been
168 allocated for arguments even when their values are passed in
169 registers.
170
171 The value of this macro is the size, in bytes, of the area reserved for
172 arguments passed in registers.
173
174 This space can either be allocated by the caller or be a part of the
175 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
176 says which. */
177 #define FIXED_STACK_AREA 12
178 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA
179
180 /* Define this if the above stack space is to be considered part of the
181 * space allocated by the caller. */
182 #define OUTGOING_REG_PARM_STACK_SPACE
183
184 /* Define this if the maximum size of all the outgoing args is to be
185 accumulated and pushed during the prologue. The amount can be
186 found in the variable current_function_outgoing_args_size. */
187 #define ACCUMULATE_OUTGOING_ARGS 1
188
189 /* Value should be nonzero if functions must have frame pointers.
190 Zero means the frame pointer need not be set up (and parms
191 may be accessed via the stack pointer) in functions that seem suitable.
192 This is computed in `reload', in reload1.c.
193 */
194 #define FRAME_POINTER_REQUIRED (bfin_frame_pointer_required ())
195
196 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */
197
198 /* Make strings word-aligned so strcpy from constants will be faster. */
199 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
200 (TREE_CODE (EXP) == STRING_CST \
201 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
202
203 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18)
204 #define TRAMPOLINE_TEMPLATE(FILE) \
205 if (TARGET_FDPIC) \
206 { \
207 fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \
208 fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \
209 fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \
210 fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \
211 fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \
212 fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \
213 fprintf(FILE, "\t.dw\t0xac4b\n"); /* p3 = [p1 + 4] */ \
214 fprintf(FILE, "\t.dw\t0x9149\n"); /* p1 = [p1] */ \
215 fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \
216 } \
217 else \
218 { \
219 fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \
220 fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \
221 fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \
222 fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \
223 fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \
224 }
225
226 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
227 initialize_trampoline (TRAMP, FNADDR, CXT)
228 \f
229 /* Definitions for register eliminations.
230
231 This is an array of structures. Each structure initializes one pair
232 of eliminable registers. The "from" register number is given first,
233 followed by "to". Eliminations of the same "from" register are listed
234 in order of preference.
235
236 There are two registers that can always be eliminated on the i386.
237 The frame pointer and the arg pointer can be replaced by either the
238 hard frame pointer or to the stack pointer, depending upon the
239 circumstances. The hard frame pointer is not used before reload and
240 so it is not eligible for elimination. */
241
242 #define ELIMINABLE_REGS \
243 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
244 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
245 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \
246
247 /* Given FROM and TO register numbers, say whether this elimination is
248 allowed. Frame pointer elimination is automatically handled.
249
250 All other eliminations are valid. */
251
252 #define CAN_ELIMINATE(FROM, TO) \
253 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
254
255 /* Define the offset between two registers, one to be eliminated, and the other
256 its replacement, at the start of a routine. */
257
258 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
259 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO)))
260 \f
261 /* This processor has
262 8 data register for doing arithmetic
263 8 pointer register for doing addressing, including
264 1 stack pointer P6
265 1 frame pointer P7
266 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3)
267 1 condition code flag register CC
268 5 return address registers RETS/I/X/N/E
269 1 arithmetic status register (ASTAT). */
270
271 #define FIRST_PSEUDO_REGISTER 44
272
273 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X)))
274 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
275 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3)
276 #define D_REGNO_P(X) ((X) <= REG_R7)
277 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7)
278 #define I_REGNO_P(X) \
279 ((X) == REG_I0 || (X) == REG_I1 || (X) == REG_I2 || (X) == REG_I3)
280
281 #define REGISTER_NAMES { \
282 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
283 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \
284 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \
285 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \
286 "A0", "A1", \
287 "CC", \
288 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \
289 "ARGP" \
290 }
291
292 #define SHORT_REGISTER_NAMES { \
293 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \
294 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \
295 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \
296 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", }
297
298 #define HIGH_REGISTER_NAMES { \
299 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \
300 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \
301 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \
302 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", }
303
304 #define DREGS_PAIR_NAMES { \
305 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, }
306
307 #define BYTE_REGISTER_NAMES { \
308 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", }
309
310
311 /* 1 for registers that have pervasive standard uses
312 and are not available for the register allocator. */
313
314 #define FIXED_REGISTERS \
315 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
316 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
317 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
318 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
319 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp */ \
320 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
321 }
322
323 /* 1 for registers not available across function calls.
324 These must include the FIXED_REGISTERS and also any
325 registers that can be used without being saved.
326 The latter must include the registers where values are returned
327 and the register where structure-value addresses are passed.
328 Aside from that, you can include as many other registers as you like. */
329
330 #define CALL_USED_REGISTERS \
331 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
332 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \
333 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
334 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
335 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp */ \
336 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
337 }
338
339 /* Order in which to allocate registers. Each register must be
340 listed once, even those in FIXED_REGISTERS. List frame pointer
341 late and fixed registers last. Note that, in general, we prefer
342 registers listed in CALL_USED_REGISTERS, keeping the others
343 available for storage of persistent values. */
344
345 #define REG_ALLOC_ORDER \
346 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \
347 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \
348 REG_A0, REG_A1, \
349 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \
350 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \
351 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \
352 REG_ASTAT, REG_SEQSTAT, REG_USP, \
353 REG_CC, REG_ARGP \
354 }
355
356 /* Macro to conditionally modify fixed_regs/call_used_regs. */
357 #define CONDITIONAL_REGISTER_USAGE \
358 { \
359 conditional_register_usage(); \
360 if (TARGET_FDPIC) \
361 call_used_regs[FDPIC_REGNO] = 1; \
362 if (!TARGET_FDPIC && flag_pic) \
363 { \
364 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
365 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
366 } \
367 }
368
369 /* Define the classes of registers for register constraints in the
370 machine description. Also define ranges of constants.
371
372 One of the classes must always be named ALL_REGS and include all hard regs.
373 If there is more than one class, another class must be named NO_REGS
374 and contain no registers.
375
376 The name GENERAL_REGS must be the name of a class (or an alias for
377 another name such as ALL_REGS). This is the class of registers
378 that is allowed by "g" or "r" in a register constraint.
379 Also, registers outside this class are allocated only when
380 instructions express preferences for them.
381
382 The classes must be numbered in nondecreasing order; that is,
383 a larger-numbered class must never be contained completely
384 in a smaller-numbered class.
385
386 For any two classes, it is very desirable that there be another
387 class that represents their union. */
388
389
390 enum reg_class
391 {
392 NO_REGS,
393 IREGS,
394 BREGS,
395 LREGS,
396 MREGS,
397 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */
398 DAGREGS,
399 EVEN_AREGS,
400 ODD_AREGS,
401 AREGS,
402 CCREGS,
403 EVEN_DREGS,
404 ODD_DREGS,
405 DREGS,
406 FDPIC_REGS,
407 FDPIC_FPTR_REGS,
408 PREGS_CLOBBERED,
409 PREGS,
410 IPREGS,
411 DPREGS,
412 MOST_REGS,
413 PROLOGUE_REGS,
414 NON_A_CC_REGS,
415 ALL_REGS, LIM_REG_CLASSES
416 };
417
418 #define N_REG_CLASSES ((int)LIM_REG_CLASSES)
419
420 #define GENERAL_REGS DPREGS
421
422 /* Give names of register classes as strings for dump file. */
423
424 #define REG_CLASS_NAMES \
425 { "NO_REGS", \
426 "IREGS", \
427 "BREGS", \
428 "LREGS", \
429 "MREGS", \
430 "CIRCREGS", \
431 "DAGREGS", \
432 "EVEN_AREGS", \
433 "ODD_AREGS", \
434 "AREGS", \
435 "CCREGS", \
436 "EVEN_DREGS", \
437 "ODD_DREGS", \
438 "DREGS", \
439 "FDPIC_REGS", \
440 "FDPIC_FPTR_REGS", \
441 "PREGS_CLOBBERED", \
442 "PREGS", \
443 "IPREGS", \
444 "DPREGS", \
445 "MOST_REGS", \
446 "PROLOGUE_REGS", \
447 "NON_A_CC_REGS", \
448 "ALL_REGS" }
449
450 /* An initializer containing the contents of the register classes, as integers
451 which are bit masks. The Nth integer specifies the contents of class N.
452 The way the integer MASK is interpreted is that register R is in the class
453 if `MASK & (1 << R)' is 1.
454
455 When the machine has more than 32 registers, an integer does not suffice.
456 Then the integers are replaced by sub-initializers, braced groupings
457 containing several integers. Each sub-initializer must be suitable as an
458 initializer for the type `HARD_REG_SET' which is defined in
459 `hard-reg-set.h'. */
460
461 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use
462 MOST_REGS as the union of DPREGS and DAGREGS. */
463
464 #define REG_CLASS_CONTENTS \
465 /* 31 - 0 63-32 */ \
466 { { 0x00000000, 0 }, /* NO_REGS */ \
467 { 0x000f0000, 0 }, /* IREGS */ \
468 { 0x00f00000, 0 }, /* BREGS */ \
469 { 0x0f000000, 0 }, /* LREGS */ \
470 { 0xf0000000, 0 }, /* MREGS */ \
471 { 0x0fff0000, 0 }, /* CIRCREGS */ \
472 { 0xffff0000, 0 }, /* DAGREGS */ \
473 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \
474 { 0x00000000, 0x2 }, /* ODD_AREGS */ \
475 { 0x00000000, 0x3 }, /* AREGS */ \
476 { 0x00000000, 0x4 }, /* CCREGS */ \
477 { 0x00000055, 0 }, /* EVEN_DREGS */ \
478 { 0x000000aa, 0 }, /* ODD_DREGS */ \
479 { 0x000000ff, 0 }, /* DREGS */ \
480 { 0x00000800, 0x000 }, /* FDPIC_REGS */ \
481 { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \
482 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \
483 { 0x0000ff00, 0x800 }, /* PREGS */ \
484 { 0x000fff00, 0x800 }, /* IPREGS */ \
485 { 0x0000ffff, 0x800 }, /* DPREGS */ \
486 { 0xffffffff, 0x800 }, /* MOST_REGS */\
487 { 0x00000000, 0x7f8 }, /* PROLOGUE_REGS */\
488 { 0xffffffff, 0xff8 }, /* NON_A_CC_REGS */\
489 { 0xffffffff, 0xfff }} /* ALL_REGS */
490
491 #define IREG_POSSIBLE_P(OUTER) \
492 ((OUTER) == POST_INC || (OUTER) == PRE_INC \
493 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \
494 || (OUTER) == MEM || (OUTER) == ADDRESS)
495
496 #define MODE_CODE_BASE_REG_CLASS(MODE, OUTER, INDEX) \
497 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS)
498
499 #define INDEX_REG_CLASS PREGS
500
501 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \
502 (P_REGNO_P (X) || (X) == REG_ARGP \
503 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \
504 && I_REGNO_P (X)))
505
506 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \
507 ((X) >= FIRST_PSEUDO_REGISTER \
508 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX))
509
510 #ifdef REG_OK_STRICT
511 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
512 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)
513 #else
514 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
515 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX)
516 #endif
517
518 #define REGNO_OK_FOR_INDEX_P(X) 0
519
520 /* Get reg_class from a letter such as appears in the machine description. */
521
522 #define REG_CLASS_FROM_LETTER(LETTER) \
523 ((LETTER) == 'a' ? PREGS : \
524 (LETTER) == 'Z' ? FDPIC_REGS : \
525 (LETTER) == 'Y' ? FDPIC_FPTR_REGS : \
526 (LETTER) == 'd' ? DREGS : \
527 (LETTER) == 'z' ? PREGS_CLOBBERED : \
528 (LETTER) == 'D' ? EVEN_DREGS : \
529 (LETTER) == 'W' ? ODD_DREGS : \
530 (LETTER) == 'e' ? AREGS : \
531 (LETTER) == 'A' ? EVEN_AREGS : \
532 (LETTER) == 'B' ? ODD_AREGS : \
533 (LETTER) == 'b' ? IREGS : \
534 (LETTER) == 'B' ? BREGS : \
535 (LETTER) == 'f' ? MREGS : \
536 (LETTER) == 'c' ? CIRCREGS : \
537 (LETTER) == 'C' ? CCREGS : \
538 (LETTER) == 'x' ? MOST_REGS : \
539 (LETTER) == 'y' ? PROLOGUE_REGS : \
540 (LETTER) == 'w' ? NON_A_CC_REGS : \
541 NO_REGS)
542
543 /* The same information, inverted:
544 Return the class number of the smallest class containing
545 reg number REGNO. This could be a conditional expression
546 or could index an array. */
547
548 #define REGNO_REG_CLASS(REGNO) \
549 ((REGNO) < REG_P0 ? DREGS \
550 : (REGNO) < REG_I0 ? PREGS \
551 : (REGNO) == REG_ARGP ? PREGS \
552 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \
553 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \
554 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \
555 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \
556 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \
557 : (REGNO) == REG_CC ? CCREGS \
558 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \
559 : NO_REGS)
560
561 /* When defined, the compiler allows registers explicitly used in the
562 rtl to be used as spill registers but prevents the compiler from
563 extending the lifetime of these registers. */
564 #define SMALL_REGISTER_CLASSES 1
565
566 #define CLASS_LIKELY_SPILLED_P(CLASS) \
567 ((CLASS) == PREGS_CLOBBERED \
568 || (CLASS) == PROLOGUE_REGS \
569 || (CLASS) == CCREGS)
570
571 /* Do not allow to store a value in REG_CC for any mode */
572 /* Do not allow to store value in pregs if mode is not SI*/
573 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
574
575 /* Return the maximum number of consecutive registers
576 needed to represent mode MODE in a register of class CLASS. */
577 #define CLASS_MAX_NREGS(CLASS, MODE) \
578 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \
579 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
580
581 #define HARD_REGNO_NREGS(REGNO, MODE) \
582 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \
583 : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \
584 : CLASS_MAX_NREGS (GENERAL_REGS, MODE))
585
586 /* A C expression that is nonzero if hard register TO can be
587 considered for use as a rename register for FROM register */
588 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO)
589
590 /* A C expression that is nonzero if it is desirable to choose
591 register allocation so as to avoid move instructions between a
592 value of mode MODE1 and a value of mode MODE2.
593
594 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
595 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
596 MODE2)' must be zero. */
597 #define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2))
598
599 /* `PREFERRED_RELOAD_CLASS (X, CLASS)'
600 A C expression that places additional restrictions on the register
601 class to use when it is necessary to copy value X into a register
602 in class CLASS. The value is a register class; perhaps CLASS, or
603 perhaps another, smaller class. */
604 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
605
606 /* Function Calling Conventions. */
607
608 /* The type of the current function; normal functions are of type
609 SUBROUTINE. */
610 typedef enum {
611 SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER
612 } e_funkind;
613
614 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 }
615
616 /* Flags for the call/call_value rtl operations set up by function_arg */
617 #define CALL_NORMAL 0x00000000 /* no special processing */
618 #define CALL_LONG 0x00000001 /* always call indirect */
619 #define CALL_SHORT 0x00000002 /* always call by symbol */
620
621 typedef struct {
622 int words; /* # words passed so far */
623 int nregs; /* # registers available for passing */
624 int *arg_regs; /* array of register -1 terminated */
625 int call_cookie; /* Do special things for this call */
626 } CUMULATIVE_ARGS;
627
628 /* Define where to put the arguments to a function.
629 Value is zero to push the argument on the stack,
630 or a hard register in which to store the argument.
631
632 MODE is the argument's machine mode.
633 TYPE is the data type of the argument (as a tree).
634 This is null for libcalls where that information may
635 not be available.
636 CUM is a variable of type CUMULATIVE_ARGS which gives info about
637 the preceding args and about the function being called.
638 NAMED is nonzero if this argument is a named parameter
639 (otherwise it is an extra parameter matching an ellipsis). */
640
641 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
642 (function_arg (&CUM, MODE, TYPE, NAMED))
643
644 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO)
645
646
647 /* Initialize a variable CUM of type CUMULATIVE_ARGS
648 for a call to a function whose data type is FNTYPE.
649 For a library call, FNTYPE is 0. */
650 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \
651 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
652
653 /* Update the data in CUM to advance over an argument
654 of mode MODE and data type TYPE.
655 (TYPE is null for libcalls where that information may not be available.) */
656 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
657 (function_arg_advance (&CUM, MODE, TYPE, NAMED))
658
659 #define RETURN_POPS_ARGS(FDECL, FUNTYPE, STKSIZE) 0
660
661 /* Define how to find the value returned by a function.
662 VALTYPE is the data type of the value (as a tree).
663 If the precise function being called is known, FUNC is its FUNCTION_DECL;
664 otherwise, FUNC is 0.
665 */
666
667 #define VALUE_REGNO(MODE) (REG_R0)
668
669 #define FUNCTION_VALUE(VALTYPE, FUNC) \
670 gen_rtx_REG (TYPE_MODE (VALTYPE), \
671 VALUE_REGNO(TYPE_MODE(VALTYPE)))
672
673 /* Define how to find the value returned by a library function
674 assuming the value has mode MODE. */
675
676 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE))
677
678 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0)
679
680 #define DEFAULT_PCC_STRUCT_RETURN 0
681 #define RETURN_IN_MEMORY(TYPE) bfin_return_in_memory(TYPE)
682
683 /* Before the prologue, the return address is in the RETS register. */
684 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS)
685
686 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT)
687
688 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS)
689
690 /* Call instructions don't modify the stack pointer on the Blackfin. */
691 #define INCOMING_FRAME_SP_OFFSET 0
692
693 /* Describe how we implement __builtin_eh_return. */
694 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
695 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2)
696 #define EH_RETURN_HANDLER_RTX \
697 gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD))
698
699 /* Addressing Modes */
700
701 /* Recognize any constant value that is a valid address. */
702 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
703
704 /* Nonzero if the constant value X is a legitimate general operand.
705 symbol_ref are not legitimate and will be put into constant pool.
706 See force_const_mem().
707 If -mno-pool, all constants are legitimate.
708 */
709 #define LEGITIMATE_CONSTANT_P(x) 1
710
711 /* A number, the maximum number of registers that can appear in a
712 valid memory address. Note that it is up to you to specify a
713 value equal to the maximum number that `GO_IF_LEGITIMATE_ADDRESS'
714 would ever accept. */
715 #define MAX_REGS_PER_ADDRESS 1
716
717 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
718 that is a valid memory address for an instruction.
719 The MODE argument is the machine mode for the MEM expression
720 that wants to use this address.
721
722 Blackfin addressing modes are as follows:
723
724 [preg]
725 [preg + imm16]
726
727 B [ Preg + uimm15 ]
728 W [ Preg + uimm16m2 ]
729 [ Preg + uimm17m4 ]
730
731 [preg++]
732 [preg--]
733 [--sp]
734 */
735
736 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \
737 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode)
738
739 #ifdef REG_OK_STRICT
740 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
741 do { \
742 if (bfin_legitimate_address_p (MODE, X, 1)) \
743 goto WIN; \
744 } while (0);
745 #else
746 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
747 do { \
748 if (bfin_legitimate_address_p (MODE, X, 0)) \
749 goto WIN; \
750 } while (0);
751 #endif
752
753 /* Try machine-dependent ways of modifying an illegitimate address
754 to be legitimate. If we find one, return the new, valid address.
755 This macro is used in only one place: `memory_address' in explow.c.
756
757 OLDX is the address as it was before break_out_memory_refs was called.
758 In some cases it is useful to look at this to decide what needs to be done.
759
760 MODE and WIN are passed so that this macro can use
761 GO_IF_LEGITIMATE_ADDRESS.
762
763 It is always safe for this macro to do nothing. It exists to recognize
764 opportunities to optimize the output.
765 */
766 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
767 do { \
768 rtx _q = legitimize_address(X, OLDX, MODE); \
769 if (_q) { X = _q; goto WIN; } \
770 } while (0)
771
772 #define HAVE_POST_INCREMENT 1
773 #define HAVE_POST_DECREMENT 1
774 #define HAVE_PRE_DECREMENT 1
775
776 /* `LEGITIMATE_PIC_OPERAND_P (X)'
777 A C expression that is nonzero if X is a legitimate immediate
778 operand on the target machine when generating position independent
779 code. You can assume that X satisfies `CONSTANT_P', so you need
780 not check this. You can also assume FLAG_PIC is true, so you need
781 not check it either. You need not define this macro if all
782 constants (including `SYMBOL_REF') can be immediate operands when
783 generating position independent code. */
784 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X)
785
786 #define SYMBOLIC_CONST(X) \
787 (GET_CODE (X) == SYMBOL_REF \
788 || GET_CODE (X) == LABEL_REF \
789 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
790
791 /*
792 A C statement or compound statement with a conditional `goto
793 LABEL;' executed if memory address X (an RTX) can have different
794 meanings depending on the machine mode of the memory reference it
795 is used for or if the address is valid for some modes but not
796 others.
797
798 Autoincrement and autodecrement addresses typically have
799 mode-dependent effects because the amount of the increment or
800 decrement is the size of the operand being addressed. Some
801 machines have other mode-dependent addresses. Many RISC machines
802 have no mode-dependent addresses.
803
804 You may assume that ADDR is a valid address for the machine.
805 */
806 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
807 do { \
808 if (GET_CODE (ADDR) == POST_INC \
809 || GET_CODE (ADDR) == POST_DEC \
810 || GET_CODE (ADDR) == PRE_DEC) \
811 goto LABEL; \
812 } while (0)
813
814 #define NOTICE_UPDATE_CC(EXPR, INSN) 0
815
816 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
817 is done just by pretending it is already truncated. */
818 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
819
820 /* Max number of bytes we can move from memory to memory
821 in one reasonably fast instruction. */
822 #define MOVE_MAX UNITS_PER_WORD
823
824
825 /* STORAGE LAYOUT: target machine storage layout
826 Define this macro as a C expression which is nonzero if accessing
827 less than a word of memory (i.e. a `char' or a `short') is no
828 faster than accessing a word of memory, i.e., if such access
829 require more than one instruction or if there is no difference in
830 cost between byte and (aligned) word loads.
831
832 When this macro is not defined, the compiler will access a field by
833 finding the smallest containing object; when it is defined, a
834 fullword load will be used if alignment permits. Unless bytes
835 accesses are faster than word accesses, using word accesses is
836 preferable since it may eliminate subsequent memory access if
837 subsequent accesses occur to other fields in the same word of the
838 structure, but to different bytes. */
839 #define SLOW_BYTE_ACCESS 0
840 #define SLOW_SHORT_ACCESS 0
841
842 /* Define this if most significant bit is lowest numbered
843 in instructions that operate on numbered bit-fields. */
844 #define BITS_BIG_ENDIAN 0
845
846 /* Define this if most significant byte of a word is the lowest numbered.
847 We can't access bytes but if we could we would in the Big Endian order. */
848 #define BYTES_BIG_ENDIAN 0
849
850 /* Define this if most significant word of a multiword number is numbered. */
851 #define WORDS_BIG_ENDIAN 0
852
853 /* number of bits in an addressable storage unit */
854 #define BITS_PER_UNIT 8
855
856 /* Width in bits of a "word", which is the contents of a machine register.
857 Note that this is not necessarily the width of data type `int';
858 if using 16-bit ints on a 68000, this would still be 32.
859 But on a machine with 16-bit registers, this would be 16. */
860 #define BITS_PER_WORD 32
861
862 /* Width of a word, in units (bytes). */
863 #define UNITS_PER_WORD 4
864
865 /* Width in bits of a pointer.
866 See also the macro `Pmode1' defined below. */
867 #define POINTER_SIZE 32
868
869 /* Allocation boundary (in *bits*) for storing pointers in memory. */
870 #define POINTER_BOUNDARY 32
871
872 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
873 #define PARM_BOUNDARY 32
874
875 /* Boundary (in *bits*) on which stack pointer should be aligned. */
876 #define STACK_BOUNDARY 32
877
878 /* Allocation boundary (in *bits*) for the code of a function. */
879 #define FUNCTION_BOUNDARY 32
880
881 /* Alignment of field after `int : 0' in a structure. */
882 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
883
884 /* No data type wants to be aligned rounder than this. */
885 #define BIGGEST_ALIGNMENT 32
886
887 /* Define this if move instructions will actually fail to work
888 when given unaligned data. */
889 #define STRICT_ALIGNMENT 1
890
891 /* (shell-command "rm c-decl.o stor-layout.o")
892 * never define PCC_BITFIELD_TYPE_MATTERS
893 * really cause some alignment problem
894 */
895
896 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \
897 BITS_PER_UNIT)
898
899 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \
900 BITS_PER_UNIT)
901
902
903 /* what is the 'type' of size_t */
904 #define SIZE_TYPE "long unsigned int"
905
906 /* Define this as 1 if `char' should by default be signed; else as 0. */
907 #define DEFAULT_SIGNED_CHAR 1
908 #define FLOAT_TYPE_SIZE BITS_PER_WORD
909 #define SHORT_TYPE_SIZE 16
910 #define CHAR_TYPE_SIZE 8
911 #define INT_TYPE_SIZE 32
912 #define LONG_TYPE_SIZE 32
913 #define LONG_LONG_TYPE_SIZE 64
914
915 /* Note: Fix this to depend on target switch. -- lev */
916
917 /* Note: Try to implement double and force long double. -- tonyko
918 * #define __DOUBLES_ARE_FLOATS__
919 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE
920 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
921 * #define DOUBLES_ARE_FLOATS 1
922 */
923
924 #define DOUBLE_TYPE_SIZE 64
925 #define LONG_DOUBLE_TYPE_SIZE 64
926
927 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)'
928 A macro to update M and UNSIGNEDP when an object whose type is
929 TYPE and which has the specified mode and signedness is to be
930 stored in a register. This macro is only called when TYPE is a
931 scalar type.
932
933 On most RISC machines, which only have operations that operate on
934 a full register, define this macro to set M to `word_mode' if M is
935 an integer mode narrower than `BITS_PER_WORD'. In most cases,
936 only integer modes should be widened because wider-precision
937 floating-point operations are usually more expensive than their
938 narrower counterparts.
939
940 For most machines, the macro definition does not change UNSIGNEDP.
941 However, some machines, have instructions that preferentially
942 handle either signed or unsigned quantities of certain modes. For
943 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add
944 instructions sign-extend the result to 64 bits. On such machines,
945 set UNSIGNEDP according to which kind of extension is more
946 efficient.
947
948 Do not define this macro if it would never modify M.*/
949
950 #define BFIN_PROMOTE_MODE_P(MODE) \
951 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \
952 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)
953
954 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
955 if (BFIN_PROMOTE_MODE_P(MODE)) \
956 { \
957 if (MODE == QImode) \
958 UNSIGNEDP = 1; \
959 else if (MODE == HImode) \
960 UNSIGNEDP = 0; \
961 (MODE) = SImode; \
962 }
963
964 /* Describing Relative Costs of Operations */
965
966 /* Do not put function addr into constant pool */
967 #define NO_FUNCTION_CSE 1
968
969 /* A C expression for the cost of moving data from a register in class FROM to
970 one in class TO. The classes are expressed using the enumeration values
971 such as `GENERAL_REGS'. A value of 2 is the default; other values are
972 interpreted relative to that.
973
974 It is not required that the cost always equal 2 when FROM is the same as TO;
975 on some machines it is expensive to move between registers if they are not
976 general registers. */
977
978 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
979 bfin_register_move_cost ((MODE), (CLASS1), (CLASS2))
980
981 /* A C expression for the cost of moving data of mode M between a
982 register and memory. A value of 2 is the default; this cost is
983 relative to those in `REGISTER_MOVE_COST'.
984
985 If moving between registers and memory is more expensive than
986 between two registers, you should define this macro to express the
987 relative cost. */
988
989 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
990 bfin_memory_move_cost ((MODE), (CLASS), (IN))
991
992 /* Specify the machine mode that this machine uses
993 for the index in the tablejump instruction. */
994 #define CASE_VECTOR_MODE SImode
995
996 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
997
998 /* Define if operations between registers always perform the operation
999 on the full register even if a narrower mode is specified.
1000 #define WORD_REGISTER_OPERATIONS
1001 */
1002
1003 #define CONST_18UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 262140)
1004 #define CONST_16BIT_IMM_P(VALUE) ((VALUE) >= -32768 && (VALUE) <= 32767)
1005 #define CONST_16UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 65535)
1006 #define CONST_7BIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 63)
1007 #define CONST_7NBIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 0)
1008 #define CONST_5UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 31)
1009 #define CONST_4BIT_IMM_P(VALUE) ((VALUE) >= -8 && (VALUE) <= 7)
1010 #define CONST_4UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 15)
1011 #define CONST_3BIT_IMM_P(VALUE) ((VALUE) >= -4 && (VALUE) <= 3)
1012 #define CONST_3UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 7)
1013
1014 #define CONSTRAINT_LEN(C, STR) \
1015 ((C) == 'P' || (C) == 'M' || (C) == 'N' ? 2 \
1016 : (C) == 'K' ? 3 \
1017 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1018
1019 #define CONST_OK_FOR_P(VALUE, STR) \
1020 ((STR)[1] == '0' ? (VALUE) == 0 \
1021 : (STR)[1] == '1' ? (VALUE) == 1 \
1022 : (STR)[1] == '2' ? (VALUE) == 2 \
1023 : (STR)[1] == '3' ? (VALUE) == 3 \
1024 : (STR)[1] == '4' ? (VALUE) == 4 \
1025 : 0)
1026
1027 #define CONST_OK_FOR_K(VALUE, STR) \
1028 ((STR)[1] == 'u' \
1029 ? ((STR)[2] == '3' ? CONST_3UBIT_IMM_P (VALUE) \
1030 : (STR)[2] == '4' ? CONST_4UBIT_IMM_P (VALUE) \
1031 : (STR)[2] == '5' ? CONST_5UBIT_IMM_P (VALUE) \
1032 : (STR)[2] == 'h' ? CONST_16UBIT_IMM_P (VALUE) \
1033 : 0) \
1034 : (STR)[1] == 's' \
1035 ? ((STR)[2] == '3' ? CONST_3BIT_IMM_P (VALUE) \
1036 : (STR)[2] == '4' ? CONST_4BIT_IMM_P (VALUE) \
1037 : (STR)[2] == '7' ? CONST_7BIT_IMM_P (VALUE) \
1038 : (STR)[2] == 'h' ? CONST_16BIT_IMM_P (VALUE) \
1039 : 0) \
1040 : (STR)[1] == 'n' \
1041 ? ((STR)[2] == '7' ? CONST_7NBIT_IMM_P (VALUE) \
1042 : 0) \
1043 : 0)
1044
1045 #define CONST_OK_FOR_M(VALUE, STR) \
1046 ((STR)[1] == '1' ? (VALUE) == 255 \
1047 : (STR)[1] == '2' ? (VALUE) == 65535 \
1048 : 0)
1049
1050 /* The letters I, J, K, L and M in a register constraint string
1051 can be used to stand for particular ranges of immediate operands.
1052 This macro defines what the ranges are.
1053 C is the letter, and VALUE is a constant value.
1054 Return 1 if VALUE is in the range specified by C.
1055
1056 bfin constant operands are as follows
1057
1058 J 2**N 5bit imm scaled
1059 Ks7 -64 .. 63 signed 7bit imm
1060 Ku5 0..31 unsigned 5bit imm
1061 Ks4 -8 .. 7 signed 4bit imm
1062 Ks3 -4 .. 3 signed 3bit imm
1063 Ku3 0 .. 7 unsigned 3bit imm
1064 Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n
1065 */
1066 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
1067 ((C) == 'J' ? (log2constp (VALUE)) \
1068 : (C) == 'K' ? CONST_OK_FOR_K (VALUE, STR) \
1069 : (C) == 'L' ? log2constp (~(VALUE)) \
1070 : (C) == 'M' ? CONST_OK_FOR_M (VALUE, STR) \
1071 : (C) == 'P' ? CONST_OK_FOR_P (VALUE, STR) \
1072 : 0)
1073
1074 /*Constant Output Formats */
1075 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1076 ((C) == 'H' ? 1 : 0)
1077
1078 #define EXTRA_CONSTRAINT(VALUE, D) \
1079 ((D) == 'Q' ? GET_CODE (VALUE) == SYMBOL_REF : 0)
1080
1081 /* Switch into a generic section. */
1082 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
1083
1084 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE)
1085 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX)
1086
1087 typedef enum sections {
1088 CODE_DIR,
1089 DATA_DIR,
1090 LAST_SECT_NM
1091 } SECT_ENUM_T;
1092
1093 typedef enum directives {
1094 LONG_CONST_DIR,
1095 SHORT_CONST_DIR,
1096 BYTE_CONST_DIR,
1097 SPACE_DIR,
1098 INIT_DIR,
1099 LAST_DIR_NM
1100 } DIR_ENUM_T;
1101
1102 #define TEXT_SECTION_ASM_OP ".text;"
1103 #define DATA_SECTION_ASM_OP ".data;"
1104
1105 #define ASM_APP_ON ""
1106 #define ASM_APP_OFF ""
1107
1108 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \
1109 do { fputs (".global ", FILE); \
1110 assemble_name (FILE, NAME); \
1111 fputc (';',FILE); \
1112 fputc ('\n',FILE); \
1113 } while (0)
1114
1115 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1116 do { \
1117 fputs (".type ", FILE); \
1118 assemble_name (FILE, NAME); \
1119 fputs (", STT_FUNC", FILE); \
1120 fputc (';',FILE); \
1121 fputc ('\n',FILE); \
1122 ASM_OUTPUT_LABEL(FILE, NAME); \
1123 } while (0)
1124
1125 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1126 do { assemble_name (FILE, NAME); \
1127 fputs (":\n",FILE); \
1128 } while (0)
1129
1130 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1131 do { fprintf (FILE, "_%s", NAME); \
1132 } while (0)
1133
1134 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1135 do { char __buf[256]; \
1136 fprintf (FILE, "\t.dd\t"); \
1137 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1138 assemble_name (FILE, __buf); \
1139 fputc (';', FILE); \
1140 fputc ('\n', FILE); \
1141 } while (0)
1142
1143 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1144 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)
1145
1146 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1147 do { \
1148 char __buf[256]; \
1149 fprintf (FILE, "\t.dd\t"); \
1150 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1151 assemble_name (FILE, __buf); \
1152 fputs (" - ", FILE); \
1153 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \
1154 assemble_name (FILE, __buf); \
1155 fputc (';', FILE); \
1156 fputc ('\n', FILE); \
1157 } while (0)
1158
1159 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1160 do { \
1161 if ((LOG) != 0) \
1162 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
1163 } while (0)
1164
1165 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1166 do { \
1167 asm_output_skip (FILE, SIZE); \
1168 } while (0)
1169
1170 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1171 do { \
1172 switch_to_section (data_section); \
1173 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \
1174 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
1175 ASM_OUTPUT_LABEL (FILE, NAME); \
1176 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \
1177 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \
1178 } while (0)
1179
1180 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1181 do { \
1182 ASM_GLOBALIZE_LABEL1(FILE,NAME); \
1183 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0)
1184
1185 #define ASM_COMMENT_START "//"
1186
1187 #define FUNCTION_PROFILER(FILE, LABELNO) \
1188 do {\
1189 fprintf (FILE, "\tP1.l =LP$%d; P1.h =LP$%d; call mcount;\n", \
1190 LABELNO, LABELNO);\
1191 } while(0)
1192
1193 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO])
1194 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO])
1195
1196 extern struct rtx_def *bfin_compare_op0, *bfin_compare_op1;
1197 extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx;
1198
1199 /* This works for GAS and some other assemblers. */
1200 #define SET_ASM_OP ".set "
1201
1202 /* DBX register number for a given compiler register number */
1203 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1204
1205 #define SIZE_ASM_OP "\t.size\t"
1206
1207 #endif /* _BFIN_CONFIG */