projects / gcc.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
c4x.md: Use GEN_INT instead of gen_rtx (CONST_INT, ...).
[gcc.git] / gcc / config / c4x / c4x.md
1 ;; Machine description for the TMS320C[34]x for GCC
2 ;; Copyright (C) 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2002, 2004 Free Software Foundation, Inc.
4
5 ;; Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
6 ;; and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl)
7
8 ;; This file is part of GCC.
9
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; any later version.
14
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
19
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
24
25 ;
26 ; TODO :
27 ; Try using PQImode again for addresses since C30 only uses
28 ; 24-bit addresses. Ideally GCC would emit different insns
29 ; for QImode and Pmode, whether Pmode was QImode or PQImode.
30 ; For addresses we wouldn't have to have a clobber of the CC
31 ; associated with each insn and we could use MPYI in address
32 ; calculations without having to synthesize a proper 32 bit multiply.
33
34 ; Additional C30/C40 instructions not coded:
35 ; CALLcond, IACK, IDLE, LDE, LDFI, LDII, LDM, NORM, RETIcond
36 ; ROLC, RORC, SIGI, STFI, STII, SUBC, SWI
37
38 ; Additional C40 instructions not coded:
39 ; LDEP, LDPE, LWRct, LAJcond, RETIcondD
40
41 ;
42 ; C4x MODES
43 ;
44 ; QImode char, short, int, long (32-bits)
45 ; HImode long long (64-bits)
46 ; QFmode float, double (32-bits)
47 ; HFmode long double (40-bits)
48 ; CCmode
49 ; CC_NOOVmode
50
51 ;
52 ; C4x PREDICATES:
53 ;
54 ; comparison_operator LT, GT, LE, GE, LTU, GTU, LEU, GEU, EQ, NE
55 ; memory_operand memory [m]
56 ; immediate_operand immediate constant [IKN]
57 ; register_operand register [rf]
58 ; general_operand register, memory, constant [rfmI]
59
60 ; addr_reg_operand AR0-AR7, pseudo reg [a]
61 ; sp_reg_operand SP [b]
62 ; std_reg_operand AR0-AR7, IR0-IR1, RC, RS, RE, SP, pseudo [c]
63 ; ext_reg_operand R0-R11, pseudo reg [f]
64 ; ext_low_reg_operand R0-R7, pseudo reg [q]
65 ; index_reg_operand IR0-IR1, pseudo reg [x]
66 ; st_reg_operand ST [y]
67 ; dp_reg_operand DP [z]
68 ; stik_const_operand 5-bit const [K]
69 ; src_operand general operand [rfHmI]
70 ; par_ind_operand indirect S mode (ARx + 0, 1, IRx) [S<>]
71 ; parallel_operand par_ind_operand or ext_low_reg_operand
72 ; symbolic_address_operand
73 ; call_address_operand
74
75 ; ADDI src2, src1, dst three operand op
76 ; ADDI src, dst two operand op
77
78 ; Note that the predicates are only used when selecting a pattern
79 ; to determine if an operand is valid.
80
81 ; The constraints then select which of the possible valid operands
82 ; is present (and guide register selection). The actual assembly
83 ; instruction is then selected on the basis of the constraints.
84
85 ; The extra constraint (valid_operands) is used to determine if
86 ; the combination of operands is legitimate for the pattern.
87
88 ;
89 ; C4x CONSTRAINTS:
90 ;
91 ; a address reg AR0-AR7
92 ; b stack pointer SP
93 ; c other int reg AR0-AR7, IR0-IR1, RC, RS, RE
94 ; d fp reg R0-R11 (sets CC when dst)
95 ; e
96 ; f fp reg R0-R11 (sets CC when dst)
97 ; g general reg, memory, constant
98 ; h fp reg (HFmode) R0-R11 (sets CC when dst)
99 ; i immediate int constant
100 ; j
101 ; k block count BK
102 ; l
103 ; m memory
104 ; n immediate int constant with known numeric value
105 ; o offsettable memory
106 ; p memory address
107 ; q low fp reg R0-R7 (sets CC when dst)
108 ; r general reg R0-R11, AR0-AR7, IR0-IR1, RC, RS, RE
109 ; s immediate int constant (value not explicit)
110 ; t R0-R1
111 ; u R2-R3
112 ; v repeat count reg RC
113 ; w
114 ; x index reg IR0-IR1
115 ; y status (CC) reg ST
116 ; z data pointer DP
117
118 ; G fp zero
119 ; H fp 16-bit constant
120 ; I signed 16-bit
121 ; J signed 8-bit (C4x only)
122 ; K signed 5-bit (C4x only)
123 ; L unsigned 16-bit
124 ; M unsigned 8-bit (C4x only)
125 ; N ones complement of unsigned 16-bit
126 ; O 16 bit high constant
127 ; Q ARx + 9-bit signed disp
128 ; R ARx + 5-bit unsigned disp (C4x only)
129 ; S ARx + 0, 1, IRx disp
130 ; T direct memory operand
131 ; V non offsettable memory
132 ; X any operand
133 ; < memory operand with autodecrement addressing
134 ; > memory operand with autoincrement addressing
135 ; { memory operand with pre-modify addressing
136 ; } memory operand with post-modify addressing
137
138 ; Note that the 'd', 'f', and 'h' constraints are equivalent.
139 ; The m constraint is equivalent to 'QT<>{}'
140
141 ; Note we cannot use the 'g' constraint with Pmode (i.e, QImode)
142 ; operations since LEGITIMATE_CONSTANT_P accepts SYMBOL_REF.
143 ; So instead we use 'rIm' for signed operands or 'rLm' for unsigned operands.
144
145 ; Note that the constraints are used to select the operands
146 ; for a chosen pattern. The constraint that requires the fewest
147 ; instructions to load an operand is chosen.
148
149 ; Note that the 'r' constraint is mostly only used for src integer register
150 ; operands, while 'c' and 'd' constraints are generally only used for dst
151 ; integer register operands (the 'r' constraint is the union of the 'c' and
152 ; 'd' constraints). When a register satisfying the 'd' constraint
153 ; is used as a dst operand, the CC gets clobbered (except for LDIcond)---but
154 ; not for 'c'.
155
156 ; The 'f' constraint is only for float register operands---when
157 ; a register satisying the 'f' constraint is used as a dst operand,
158 ; the CC gets clobbered (except for LDFcond).
159
160 ; The ! in front of the 'b' constraint says to GCC to disparage the
161 ; use of this constraint. The 'b' constraint applies only to the SP.
162
163 ; Note that we deal with the condition code CC like some of the RISC
164 ; architectures (arm, sh, sparc) where it is stored in a general register,
165 ; in this case the hard register ST (21). Unlike these other architectures
166 ; that do not set the CC with many instructions, the C[34]x architectures
167 ; sets the CC for many instructions when the destination register is
168 ; an extended precision register. While it would have been easier
169 ; to use the generic cc0 register to store the CC, as with most of
170 ; the other ported architectures, this constrains the setting and testing
171 ; of the CC to be consecutive insns. Thus we would reduce the benefit
172 ; of scheduling instructions to avoid pipeline conflicts and filling of
173 ; delayed branch slots.
174
175 ; Since the C[34]x has many instructions that set the CC, we pay the
176 ; price of having to explicitly define which insns clobber the CC
177 ; (rather than using the macro NOTICE_UPDATE_CC).
178
179 ; Note that many patterns say that the CC is clobbered when in fact
180 ; that it may not be (depending on the destination register).
181 ; We have to cover ourselves if an extended precision register
182 ; is allocated to the destination register.
183 ; Unfortunately, it is not easy to tell GCC that the clobbering of CC
184 ; is register dependent. If we could tolerate the ST register being
185 ; copied about, then we could store the CC in a pseudo register and
186 ; use constructs such as (clobber (match_scratch:CC N "&y,X")) to
187 ; indicate that the 'y' class (ST register) is clobbered for the
188 ; first combination of operands but not with the second.
189 ; I tried this approach for a while but reload got unhappy since I
190 ; didn't allow it to move the CC around.
191
192 ; Note that fundamental operations, such as moves, must not clobber the
193 ; CC. Thus movqi choses a move instruction that doesn't clobber the CC.
194 ; If GCC wants to combine a move with a compare, it is smart enough to
195 ; chose the move instruction that sets the CC.
196
197 ; Unfortunately, the C[34]x instruction set does not have arithmetic or
198 ; logical operations that never touch the CC. We thus have to assume
199 ; that the CC may be clobbered at all times. If we define patterns
200 ; such as addqi without the clobber of CC, then GCC will be forced
201 ; to use registers such as the auxiliary registers which can cause
202 ; horrible pipeline conflicts. The tradeoff is that GCC can't now
203 ; sneak in an add instruction between setting and testing of the CC.
204
205 ; Most of the C[34]x instructions require operands of the following formats,
206 ; where imm represents an immediate constant, dir a direct memory reference,
207 ; ind an indirect memory reference, and reg a register:
208
209 ; src2 (op2) src1 (op1) dst (op0)
210 ; imm dir ind reg | imm dir ind reg | reg Notes
211 ;---------------------+----------------------+------
212 ; ILH T Q<> r | - - - 0 | r 2 operand
213 ; - - S<> r | - - S<> r | r
214 ; J - R - | - - R r | r C4x
215
216 ; Arithmetic operations use the I, J constraints for immediate constants,
217 ; while logical operations use the L, J constraints. Floating point
218 ; operations use the H constraint for immediate constants.
219
220 ; With most instructions the src2 and src1 operands are commutative
221 ; (except for SUB, SUBR, ANDN). The assembler considers
222 ; ADDI 10, R0, R1 and ADDI R0, 10, R1 to be equivalent.
223 ; We thus match src2 and src1 with the src_operand predicate and
224 ; use valid_operands as the extra constraint to reject invalid
225 ; operand combinations. For example, ADDI @foo, @bar, R0.
226
227 ; Note that we use the ? modifier so that reload doesn't preferentially
228 ; try the alternative where three registers are acceptable as
229 ; operands (whenever an operand requires reloading). Instead it will try
230 ; the 2 operand form which will produce better code since it won't require
231 ; a new spill register.
232
233 ; Note that the floating point representation of 0.0 on the C4x
234 ; is 0x80000000 (-2147483648). This value produces a warning
235 ; message on 32-bit machines about the decimal constant being so large
236 ; that it is unsigned.
237
238 ; With two operand instructions patterns having two sets,
239 ; the compare set must come first to keep the combiner happy.
240 ; While the combiner seems to cope most of the time with the
241 ; compare set coming second, it's best to have it first.
242
243 ;
244 ; C4x CONSTANT attributes
245 ;
246 (define_attr "cpu" "c4x,c3x"
247 (const
248 (cond [(symbol_ref "TARGET_C3X") (const_string "c3x")]
249 (const_string "c4x"))))
250
251 ;
252 ; C4x INSN ATTRIBUTES:
253 ;
254 ; lda load address, non-clobber CC
255 ; store memory store, non-clobber CC
256 ; load_load parallel memory loads, non-clobber CC
257 ; load_store parallel memory load and store, non-clobber CC
258 ; store_load parallel memory store and load, non-clobber CC
259 ; store_store parallel memory stores, non-clobber CC
260 ; unary two operand arithmetic, non-clobber CC
261 ; unarycc two operand arithmetic, clobber CC
262 ; binary three operand arithmetic, non-clobber CC
263 ; binarycc three operand arithmetic, clobber CC
264 ; compare compare, clobber CC
265 ; call function call
266 ; rets return from subroutine
267 ; jump unconditional branch
268 ; jmpc conditional branch
269 ; db decrement and branch (unconditional)
270 ; dbc decrement and branch (conditional)
271 ; ldp load DP
272 ; push stack push
273 ; pop stack pop
274 ; repeat block repeat
275 ; repeat_top block repeat top
276 ; laj link and jump
277 ; multi multiple instruction
278 ; misc nop (default)
279
280 ; The only real instructions that affect things are the ones that modify
281 ; address registers and ones that call or jump. Note that the number
282 ; of operands refers to the RTL insn pattern, not the number of explicit
283 ; operands in the machine instruction.
284 ;
285 (define_attr "type" "lda,store,unary,unarycc,binary,binarycc,compare,call,rets,jump,jmpc,db,dbc,misc,ldp,repeat,repeat_top,laj,load_load,load_store,store_load,store_store,push,pop,multi"
286 (const_string "misc"))
287
288
289 ; Some instructions operate on unsigned data constants, some on signed data
290 ; constants, or the ones complement of unsigned constants.
291 ; This differentiates them. Default to signed. This attribute
292 ; is used by the macro SMALL_CONST () (defined in c4x.h) to determine
293 ; whether an immediate integer constant will fit within the instruction,
294 ; or will have to be loaded using direct addressing from memory.
295 ; Note that logical operations assume unsigned integers whereas
296 ; arithmetic operations assume signed integers. Note that the C4x
297 ; small immediate constant (J) used as src2 in three operand instructions
298 ; is always signed. not_uint16 refers to a number that fits into 16-bits
299 ; when one's complemented.
300 ;
301 (define_attr "data" "int16,uint16,high_16,not_uint16" (const_string "int16"))
302
303 (define_asm_attributes
304 [(set_attr "type" "multi")])
305
306 ;
307 ; C4x DELAY SLOTS
308 ;
309 ; Define delay slot scheduling for branch and call instructions.
310 ; The C[34]x has three delay slots. Note that none of the three instructions
311 ; that follow a delayed branch can be a Bcond, BcondD, BR, BRD, DBcond,
312 ; DBcondD, CALL, CALLcond, TRAPcond, RETIcond, RETScond, RPTB, RPTS, or IDLE.
313 ;
314 ; Annulled branches are a bit difficult because the next instructions
315 ; are preprocessed.
316 ; The table below shows what phase of the c4x is executed.
317 ; BccA[TF] label
318 ; op1 fetch, decode and read executed
319 ; op2 fetch and decode executed
320 ; op3 fetch executed
321 ; This means that we can allow any instruction in the last delay slot
322 ; and only instructions which modify registers in the first two.
323 ; lda can not be executed in the first delay slot
324 ; and ldpk can not be executed in the first two delay slots.
325
326 (define_attr "onlyreg" "false,true"
327 (cond [(eq_attr "type" "unary,unarycc")
328 (if_then_else (and (match_operand 0 "reg_imm_operand" "")
329 (match_operand 1 "reg_imm_operand" ""))
330 (const_string "true") (const_string "false"))
331 (eq_attr "type" "binary,binarycc")
332 (if_then_else (and (match_operand 0 "reg_imm_operand" "")
333 (and (match_operand 1 "reg_imm_operand" "")
334 (match_operand 2 "reg_imm_operand" "")))
335 (const_string "true") (const_string "false"))]
336 (const_string "false")))
337
338 (define_attr "onlyreg_nomod" "false,true"
339 (cond [(eq_attr "type" "unary,unarycc,compare,lda,store")
340 (if_then_else (and (match_operand 0 "not_modify_reg" "")
341 (match_operand 1 "not_modify_reg" ""))
342 (const_string "true") (const_string "false"))
343 (eq_attr "type" "binary,binarycc")
344 (if_then_else (and (match_operand 0 "not_modify_reg" "")
345 (and (match_operand 1 "not_modify_reg" "")
346 (match_operand 2 "not_modify_reg" "")))
347 (const_string "true") (const_string "false"))]
348 (const_string "false")))
349
350 (define_attr "not_repeat_reg" "false,true"
351 (cond [(eq_attr "type" "unary,unarycc,compare,lda,ldp,store")
352 (if_then_else (and (match_operand 0 "not_rc_reg" "")
353 (match_operand 1 "not_rc_reg" ""))
354 (const_string "true") (const_string "false"))
355 (eq_attr "type" "binary,binarycc")
356 (if_then_else (and (match_operand 0 "not_rc_reg" "")
357 (and (match_operand 1 "not_rc_reg" "")
358 (match_operand 2 "not_rc_reg" "")))
359 (const_string "true") (const_string "false"))]
360 (const_string "false")))
361
362 /* Disable compare because the c4x contains a bug. The cmpi insn sets the CC
363 in the read phase of the pipeline instead of the execution phase when
364 two registers are compared. */
365 (define_attr "in_annul_slot_1" "false,true"
366 (if_then_else (and (and (eq_attr "cpu" "c4x")
367 (eq_attr "type" "!jump,call,rets,jmpc,compare,db,dbc,repeat,repeat_top,laj,push,pop,lda,ldp,multi"))
368 (eq_attr "onlyreg" "true"))
369 (const_string "true")
370 (const_string "false")))
371
372 (define_attr "in_annul_slot_2" "false,true"
373 (if_then_else (and (and (eq_attr "cpu" "c4x")
374 (eq_attr "type" "!jump,call,rets,jmpc,db,dbc,repeat,repeat_top,laj,push,pop,ldp,multi"))
375 (eq_attr "onlyreg_nomod" "true"))
376 (const_string "true")
377 (const_string "false")))
378
379 /* Disable ldp because the c4x contains a bug. The ldp insn modifies
380 the dp register when the insn is anulled or not.
381 Also disable autoincrement insns because of a silicon bug. */
382 (define_attr "in_annul_slot_3" "false,true"
383 (if_then_else (and (and (eq_attr "cpu" "c4x")
384 (eq_attr "type" "!jump,call,rets,jmpc,db,dbc,repeat,repeat_top,laj,push,pop,ldp,multi"))
385 (eq_attr "onlyreg_nomod" "true"))
386 (const_string "true")
387 (const_string "false")))
388
389 (define_attr "in_delay_slot" "false,true"
390 (if_then_else (eq_attr "type" "!jump,call,rets,jmpc,db,dbc,repeat,repeat_top,laj,multi")
391 (const_string "true")
392 (const_string "false")))
393
394 (define_attr "in_repeat_slot" "false,true"
395 (if_then_else (and (eq_attr "cpu" "c4x")
396 (and (eq_attr "type" "!jump,call,rets,jmpc,db,dbc,repeat,repeat_top,laj,multi")
397 (eq_attr "not_repeat_reg" "true")))
398 (const_string "true")
399 (const_string "false")))
400
401 (define_attr "in_dbc_slot" "false,true"
402 (if_then_else (eq_attr "type" "!jump,call,rets,jmpc,unarycc,binarycc,compare,db,dbc,repeat,repeat_top,laj,multi")
403 (const_string "true")
404 (const_string "false")))
405
406 (define_delay (eq_attr "type" "jmpc")
407 [(eq_attr "in_delay_slot" "true")
408 (eq_attr "in_annul_slot_1" "true")
409 (eq_attr "in_annul_slot_1" "true")
410
411 (eq_attr "in_delay_slot" "true")
412 (eq_attr "in_annul_slot_2" "true")
413 (eq_attr "in_annul_slot_2" "true")
414
415 (eq_attr "in_delay_slot" "true")
416 (eq_attr "in_annul_slot_3" "true")
417 (eq_attr "in_annul_slot_3" "true") ])
418
419
420 (define_delay (eq_attr "type" "repeat_top")
421 [(eq_attr "in_repeat_slot" "true") (nil) (nil)
422 (eq_attr "in_repeat_slot" "true") (nil) (nil)
423 (eq_attr "in_repeat_slot" "true") (nil) (nil)])
424
425 (define_delay (eq_attr "type" "jump,db")
426 [(eq_attr "in_delay_slot" "true") (nil) (nil)
427 (eq_attr "in_delay_slot" "true") (nil) (nil)
428 (eq_attr "in_delay_slot" "true") (nil) (nil)])
429
430
431 ; Decrement and branch conditional instructions cannot modify the
432 ; condition codes for the cycles in the delay slots.
433 ;
434 (define_delay (eq_attr "type" "dbc")
435 [(eq_attr "in_dbc_slot" "true") (nil) (nil)
436 (eq_attr "in_dbc_slot" "true") (nil) (nil)
437 (eq_attr "in_dbc_slot" "true") (nil) (nil)])
438
439 ; The LAJ instruction has three delay slots but the last slot is
440 ; used for pushing the return address. Thus we can only use two slots.
441 ;
442 (define_delay (eq_attr "type" "laj")
443 [(eq_attr "in_delay_slot" "true") (nil) (nil)
444 (eq_attr "in_delay_slot" "true") (nil) (nil)])
445
446 ;
447 ; C4x UNSPEC NUMBERS
448 ;
449 (define_constants
450 [
451 (UNSPEC_BU 1)
452 (UNSPEC_RPTS 2)
453 (UNSPEC_LSH 3)
454 (UNSPEC_CMPHI 4)
455 (UNSPEC_RCPF 5)
456 (UNSPEC_RND 6)
457 (UNSPEC_RPTB_FILL 7)
458 (UNSPEC_LOADHF_INT 8)
459 (UNSPEC_STOREHF_INT 9)
460 (UNSPEC_RSQRF 10)
461 (UNSPEC_LOADQF_INT 11)
462 (UNSPEC_STOREQF_INT 12)
463 (UNSPEC_LDIV 13)
464 (UNSPEC_PUSH_ST 14)
465 (UNSPEC_POP_ST 15)
466 (UNSPEC_PUSH_DP 16)
467 (UNSPEC_POP_DP 17)
468 (UNSPEC_POPQI 18)
469 (UNSPEC_POPQF 19)
470 (UNSPEC_ANDN_ST 20)
471 (UNSPEC_RPTB_INIT 22)
472 (UNSPEC_TOIEEE 23)
473 (UNSPEC_FRIEEE 24)
474 ])
475
476 ;
477 ; C4x FUNCTIONAL UNITS
478 ;
479 ; Define functional units for instruction scheduling to minimize
480 ; pipeline conflicts.
481 ;
482 ; With the C3x, an external memory write (with no wait states) takes
483 ; two cycles and an external memory read (with no wait states) takes
484 ; one cycle. However, an external read following an external write
485 ; takes two cycles. With internal memory, reads and writes take
486 ; half a cycle.
487 ;
488 ; When a C4x address register is loaded it will not be available for
489 ; an extra machine cycle. Calculating with a C4x address register
490 ; makes it unavailable for 2 machine cycles. To notify GCC of these
491 ; pipeline delays, each of the auxiliary and index registers are declared
492 ; as separate functional units.
493 ;
494 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
495 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
496 ;
497 ; MULTIPLICITY 1 (C4x has no independent identical function units)
498 ; SIMULTANEITY 0 (C4x is pipelined)
499 ; READY_DELAY 1 (Results usually ready after every cyle)
500 ; ISSUE_DELAY 1 (Can issue insns every cycle)
501
502 ; Just some dummy definitions. The real work is done in c4x_adjust_cost.
503 ; These are needed so the min/max READY_DELAY is known.
504
505 (define_function_unit "dummy" 1 0 (const_int 0) 1 1)
506 (define_function_unit "dummy" 1 0 (const_int 0) 2 1)
507 (define_function_unit "dummy" 1 0 (const_int 0) 3 1)
508
509 ; The attribute setar0 is set to 1 for insns where ar0 is a dst operand.
510 ; Note that the attributes unarycc and binarycc do not apply
511 ; if ar0 is a dst operand (only loading an ext. prec. reg. sets CC)
512 (define_attr "setar0" ""
513 (cond [(eq_attr "type" "unary,binary")
514 (if_then_else (match_operand 0 "ar0_reg_operand" "")
515 (const_int 1) (const_int 0))]
516 (const_int 0)))
517
518 (define_attr "setlda_ar0" ""
519 (cond [(eq_attr "type" "lda")
520 (if_then_else (match_operand 0 "ar0_reg_operand" "")
521 (const_int 1) (const_int 0))]
522 (const_int 0)))
523
524 ; The attribute usear0 is set to 1 for insns where ar0 is used
525 ; for addressing, as a src operand, or as a dst operand.
526 (define_attr "usear0" ""
527 (cond [(eq_attr "type" "compare,store")
528 (if_then_else (match_operand 0 "ar0_mem_operand" "")
529 (const_int 1) (const_int 0))
530 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
531 (if_then_else (match_operand 1 "ar0_mem_operand" "")
532 (const_int 1) (const_int 0))
533 (eq_attr "type" "binary,binarycc")
534 (if_then_else (match_operand 2 "ar0_mem_operand" "")
535 (const_int 1) (const_int 0))
536 (eq_attr "type" "db,dbc")
537 (if_then_else (match_operand 0 "ar0_reg_operand" "")
538 (const_int 1) (const_int 0))]
539 (const_int 0)))
540
541 ; The attribute readar0 is set to 1 for insns where ar0 is a src operand.
542 (define_attr "readar0" ""
543 (cond [(eq_attr "type" "compare")
544 (if_then_else (match_operand 0 "ar0_reg_operand" "")
545 (const_int 1) (const_int 0))
546 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
547 (if_then_else (match_operand 1 "ar0_reg_operand" "")
548 (const_int 1) (const_int 0))
549 (eq_attr "type" "binary,binarycc")
550 (if_then_else (match_operand 2 "ar0_reg_operand" "")
551 (const_int 1) (const_int 0))]
552 (const_int 0)))
553
554 (define_attr "setar1" ""
555 (cond [(eq_attr "type" "unary,binary")
556 (if_then_else (match_operand 0 "ar1_reg_operand" "")
557 (const_int 1) (const_int 0))]
558 (const_int 0)))
559
560 (define_attr "setlda_ar1" ""
561 (cond [(eq_attr "type" "lda")
562 (if_then_else (match_operand 0 "ar1_reg_operand" "")
563 (const_int 1) (const_int 0))]
564 (const_int 0)))
565
566 (define_attr "usear1" ""
567 (cond [(eq_attr "type" "compare,store")
568 (if_then_else (match_operand 0 "ar1_mem_operand" "")
569 (const_int 1) (const_int 0))
570 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
571 (if_then_else (match_operand 1 "ar1_mem_operand" "")
572 (const_int 1) (const_int 0))
573 (eq_attr "type" "binary,binarycc")
574 (if_then_else (match_operand 2 "ar1_mem_operand" "")
575 (const_int 1) (const_int 0))
576 (eq_attr "type" "db,dbc")
577 (if_then_else (match_operand 0 "ar1_reg_operand" "")
578 (const_int 1) (const_int 0))]
579 (const_int 0)))
580
581 (define_attr "readar1" ""
582 (cond [(eq_attr "type" "compare")
583 (if_then_else (match_operand 0 "ar1_reg_operand" "")
584 (const_int 1) (const_int 0))
585 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
586 (if_then_else (match_operand 1 "ar1_reg_operand" "")
587 (const_int 1) (const_int 0))
588 (eq_attr "type" "binary,binarycc")
589 (if_then_else (match_operand 2 "ar1_reg_operand" "")
590 (const_int 1) (const_int 0))]
591 (const_int 0)))
592
593 (define_attr "setar2" ""
594 (cond [(eq_attr "type" "unary,binary")
595 (if_then_else (match_operand 0 "ar2_reg_operand" "")
596 (const_int 1) (const_int 0))]
597 (const_int 0)))
598
599 (define_attr "setlda_ar2" ""
600 (cond [(eq_attr "type" "lda")
601 (if_then_else (match_operand 0 "ar2_reg_operand" "")
602 (const_int 1) (const_int 0))]
603 (const_int 0)))
604
605 (define_attr "usear2" ""
606 (cond [(eq_attr "type" "compare,store")
607 (if_then_else (match_operand 0 "ar2_mem_operand" "")
608 (const_int 1) (const_int 0))
609 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
610 (if_then_else (match_operand 1 "ar2_mem_operand" "")
611 (const_int 1) (const_int 0))
612 (eq_attr "type" "binary,binarycc")
613 (if_then_else (match_operand 2 "ar2_mem_operand" "")
614 (const_int 1) (const_int 0))
615 (eq_attr "type" "db,dbc")
616 (if_then_else (match_operand 0 "ar2_reg_operand" "")
617 (const_int 1) (const_int 0))]
618 (const_int 0)))
619
620 (define_attr "readar2" ""
621 (cond [(eq_attr "type" "compare")
622 (if_then_else (match_operand 0 "ar2_reg_operand" "")
623 (const_int 1) (const_int 0))
624 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
625 (if_then_else (match_operand 1 "ar2_reg_operand" "")
626 (const_int 1) (const_int 0))
627 (eq_attr "type" "binary,binarycc")
628 (if_then_else (match_operand 2 "ar2_reg_operand" "")
629 (const_int 1) (const_int 0))]
630 (const_int 0)))
631
632 (define_attr "setar3" ""
633 (cond [(eq_attr "type" "unary,binary")
634 (if_then_else (match_operand 0 "ar3_reg_operand" "")
635 (const_int 1) (const_int 0))]
636 (const_int 0)))
637
638 (define_attr "setlda_ar3" ""
639 (cond [(eq_attr "type" "lda")
640 (if_then_else (match_operand 0 "ar3_reg_operand" "")
641 (const_int 1) (const_int 0))]
642 (const_int 0)))
643
644 (define_attr "usear3" ""
645 (cond [(eq_attr "type" "compare,store")
646 (if_then_else (match_operand 0 "ar3_mem_operand" "")
647 (const_int 1) (const_int 0))
648 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
649 (if_then_else (match_operand 1 "ar3_mem_operand" "")
650 (const_int 1) (const_int 0))
651 (eq_attr "type" "binary,binarycc")
652 (if_then_else (match_operand 2 "ar3_mem_operand" "")
653 (const_int 1) (const_int 0))
654 (eq_attr "type" "db,dbc")
655 (if_then_else (match_operand 0 "ar3_reg_operand" "")
656 (const_int 1) (const_int 0))]
657 (const_int 0)))
658
659 (define_attr "readar3" ""
660 (cond [(eq_attr "type" "compare")
661 (if_then_else (match_operand 0 "ar3_reg_operand" "")
662 (const_int 1) (const_int 0))
663 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
664 (if_then_else (match_operand 1 "ar3_reg_operand" "")
665 (const_int 1) (const_int 0))
666 (eq_attr "type" "binary,binarycc")
667 (if_then_else (match_operand 2 "ar3_reg_operand" "")
668 (const_int 1) (const_int 0))]
669 (const_int 0)))
670
671 (define_attr "setar4" ""
672 (cond [(eq_attr "type" "unary,binary")
673 (if_then_else (match_operand 0 "ar4_reg_operand" "")
674 (const_int 1) (const_int 0))]
675 (const_int 0)))
676
677 (define_attr "setlda_ar4" ""
678 (cond [(eq_attr "type" "lda")
679 (if_then_else (match_operand 0 "ar4_reg_operand" "")
680 (const_int 1) (const_int 0))]
681 (const_int 0)))
682
683 (define_attr "usear4" ""
684 (cond [(eq_attr "type" "compare,store")
685 (if_then_else (match_operand 0 "ar4_mem_operand" "")
686 (const_int 1) (const_int 0))
687 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
688 (if_then_else (match_operand 1 "ar4_mem_operand" "")
689 (const_int 1) (const_int 0))
690 (eq_attr "type" "binary,binarycc")
691 (if_then_else (match_operand 2 "ar4_mem_operand" "")
692 (const_int 1) (const_int 0))
693 (eq_attr "type" "db,dbc")
694 (if_then_else (match_operand 0 "ar4_reg_operand" "")
695 (const_int 1) (const_int 0))]
696 (const_int 0)))
697
698 (define_attr "readar4" ""
699 (cond [(eq_attr "type" "compare")
700 (if_then_else (match_operand 0 "ar4_reg_operand" "")
701 (const_int 1) (const_int 0))
702 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
703 (if_then_else (match_operand 1 "ar4_reg_operand" "")
704 (const_int 1) (const_int 0))
705 (eq_attr "type" "binary,binarycc")
706 (if_then_else (match_operand 2 "ar4_reg_operand" "")
707 (const_int 1) (const_int 0))]
708 (const_int 0)))
709
710 (define_attr "setar5" ""
711 (cond [(eq_attr "type" "unary,binary")
712 (if_then_else (match_operand 0 "ar5_reg_operand" "")
713 (const_int 1) (const_int 0))]
714 (const_int 0)))
715
716 (define_attr "setlda_ar5" ""
717 (cond [(eq_attr "type" "lda")
718 (if_then_else (match_operand 0 "ar5_reg_operand" "")
719 (const_int 1) (const_int 0))]
720 (const_int 0)))
721
722 (define_attr "usear5" ""
723 (cond [(eq_attr "type" "compare,store")
724 (if_then_else (match_operand 0 "ar5_mem_operand" "")
725 (const_int 1) (const_int 0))
726 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
727 (if_then_else (match_operand 1 "ar5_mem_operand" "")
728 (const_int 1) (const_int 0))
729 (eq_attr "type" "binary,binarycc")
730 (if_then_else (match_operand 2 "ar5_mem_operand" "")
731 (const_int 1) (const_int 0))
732 (eq_attr "type" "db,dbc")
733 (if_then_else (match_operand 0 "ar5_reg_operand" "")
734 (const_int 1) (const_int 0))]
735 (const_int 0)))
736
737 (define_attr "readar5" ""
738 (cond [(eq_attr "type" "compare")
739 (if_then_else (match_operand 0 "ar5_reg_operand" "")
740 (const_int 1) (const_int 0))
741 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
742 (if_then_else (match_operand 1 "ar5_reg_operand" "")
743 (const_int 1) (const_int 0))
744 (eq_attr "type" "binary,binarycc")
745 (if_then_else (match_operand 2 "ar5_reg_operand" "")
746 (const_int 1) (const_int 0))]
747 (const_int 0)))
748
749 (define_attr "setar6" ""
750 (cond [(eq_attr "type" "unary,binary")
751 (if_then_else (match_operand 0 "ar6_reg_operand" "")
752 (const_int 1) (const_int 0))]
753 (const_int 0)))
754
755 (define_attr "setlda_ar6" ""
756 (cond [(eq_attr "type" "lda")
757 (if_then_else (match_operand 0 "ar6_reg_operand" "")
758 (const_int 1) (const_int 0))]
759 (const_int 0)))
760
761 (define_attr "usear6" ""
762 (cond [(eq_attr "type" "compare,store")
763 (if_then_else (match_operand 0 "ar6_mem_operand" "")
764 (const_int 1) (const_int 0))
765 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
766 (if_then_else (match_operand 1 "ar6_mem_operand" "")
767 (const_int 1) (const_int 0))
768 (eq_attr "type" "binary,binarycc")
769 (if_then_else (match_operand 2 "ar6_mem_operand" "")
770 (const_int 1) (const_int 0))
771 (eq_attr "type" "db,dbc")
772 (if_then_else (match_operand 0 "ar6_reg_operand" "")
773 (const_int 1) (const_int 0))]
774 (const_int 0)))
775
776 (define_attr "readar6" ""
777 (cond [(eq_attr "type" "compare")
778 (if_then_else (match_operand 0 "ar6_reg_operand" "")
779 (const_int 1) (const_int 0))
780 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
781 (if_then_else (match_operand 1 "ar6_reg_operand" "")
782 (const_int 1) (const_int 0))
783 (eq_attr "type" "binary,binarycc")
784 (if_then_else (match_operand 2 "ar6_reg_operand" "")
785 (const_int 1) (const_int 0))]
786 (const_int 0)))
787
788 (define_attr "setar7" ""
789 (cond [(eq_attr "type" "unary,binary")
790 (if_then_else (match_operand 0 "ar7_reg_operand" "")
791 (const_int 1) (const_int 0))]
792 (const_int 0)))
793
794 (define_attr "setlda_ar7" ""
795 (cond [(eq_attr "type" "lda")
796 (if_then_else (match_operand 0 "ar7_reg_operand" "")
797 (const_int 1) (const_int 0))]
798 (const_int 0)))
799
800 (define_attr "usear7" ""
801 (cond [(eq_attr "type" "compare,store")
802 (if_then_else (match_operand 0 "ar7_mem_operand" "")
803 (const_int 1) (const_int 0))
804 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
805 (if_then_else (match_operand 1 "ar7_mem_operand" "")
806 (const_int 1) (const_int 0))
807 (eq_attr "type" "binary,binarycc")
808 (if_then_else (match_operand 2 "ar7_mem_operand" "")
809 (const_int 1) (const_int 0))
810 (eq_attr "type" "db,dbc")
811 (if_then_else (match_operand 0 "ar7_reg_operand" "")
812 (const_int 1) (const_int 0))]
813 (const_int 0)))
814
815 (define_attr "readar7" ""
816 (cond [(eq_attr "type" "compare")
817 (if_then_else (match_operand 0 "ar7_reg_operand" "")
818 (const_int 1) (const_int 0))
819 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
820 (if_then_else (match_operand 1 "ar7_reg_operand" "")
821 (const_int 1) (const_int 0))
822 (eq_attr "type" "binary,binarycc")
823 (if_then_else (match_operand 2 "ar7_reg_operand" "")
824 (const_int 1) (const_int 0))]
825 (const_int 0)))
826
827 (define_attr "setir0" ""
828 (cond [(eq_attr "type" "unary,binary")
829 (if_then_else (match_operand 0 "ir0_reg_operand" "")
830 (const_int 1) (const_int 0))]
831 (const_int 0)))
832
833 (define_attr "setlda_ir0" ""
834 (cond [(eq_attr "type" "lda")
835 (if_then_else (match_operand 0 "ir0_reg_operand" "")
836 (const_int 1) (const_int 0))]
837 (const_int 0)))
838
839 (define_attr "useir0" ""
840 (cond [(eq_attr "type" "compare,store")
841 (if_then_else (match_operand 0 "ir0_mem_operand" "")
842 (const_int 1) (const_int 0))
843 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
844 (if_then_else (match_operand 1 "ir0_mem_operand" "")
845 (const_int 1) (const_int 0))
846 (eq_attr "type" "binary,binarycc")
847 (if_then_else (match_operand 2 "ir0_mem_operand" "")
848 (const_int 1) (const_int 0))]
849 (const_int 0)))
850
851 (define_attr "setir1" ""
852 (cond [(eq_attr "type" "unary,binary")
853 (if_then_else (match_operand 0 "ir1_reg_operand" "")
854 (const_int 1) (const_int 0))]
855 (const_int 0)))
856
857 (define_attr "setlda_ir1" ""
858 (cond [(eq_attr "type" "lda")
859 (if_then_else (match_operand 0 "ir1_reg_operand" "")
860 (const_int 1) (const_int 0))]
861 (const_int 0)))
862
863 (define_attr "useir1" ""
864 (cond [(eq_attr "type" "compare,store")
865 (if_then_else (match_operand 0 "ir1_mem_operand" "")
866 (const_int 1) (const_int 0))
867 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
868 (if_then_else (match_operand 1 "ir1_mem_operand" "")
869 (const_int 1) (const_int 0))
870 (eq_attr "type" "binary,binarycc")
871 (if_then_else (match_operand 2 "ir1_mem_operand" "")
872 (const_int 1) (const_int 0))]
873 (const_int 0)))
874
875 ; With the C3x, things are simpler but slower, i.e. more pipeline conflicts :(
876 ; There are three functional groups:
877 ; (1) AR0-AR7, IR0-IR1, BK
878 ; (2) DP
879 ; (3) SP
880 ;
881 ; When a register in one of these functional groups is loaded,
882 ; the contents of that or any other register in its group
883 ; will not be available to the next instruction for 2 machine cycles.
884 ; Similarly, when a register in one of the functional groups is read
885 ; excepting (IR0-IR1, BK, DP) the contents of that or any other register
886 ; in its group will not be available to the next instruction for
887 ; 1 machine cycle.
888 ;
889 ; Let's ignore functional groups 2 and 3 for now, since they are not
890 ; so important.
891
892 (define_attr "setgroup1" ""
893 (cond [(eq_attr "type" "lda,unary,binary")
894 (if_then_else (match_operand 0 "group1_reg_operand" "")
895 (const_int 1) (const_int 0))]
896 (const_int 0)))
897
898 (define_attr "usegroup1" ""
899 (cond [(eq_attr "type" "compare,store,store_store,store_load")
900 (if_then_else (match_operand 0 "group1_mem_operand" "")
901 (const_int 1) (const_int 0))
902 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc,load_load,load_store")
903 (if_then_else (match_operand 1 "group1_mem_operand" "")
904 (const_int 1) (const_int 0))
905 (eq_attr "type" "store_store,load_store")
906 (if_then_else (match_operand 2 "group1_mem_operand" "")
907 (const_int 1) (const_int 0))
908 (eq_attr "type" "load_load,store_load")
909 (if_then_else (match_operand 3 "group1_mem_operand" "")
910 (const_int 1) (const_int 0))]
911 (const_int 0)))
912
913 (define_attr "readarx" ""
914 (cond [(eq_attr "type" "compare")
915 (if_then_else (match_operand 0 "arx_reg_operand" "")
916 (const_int 1) (const_int 0))
917 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
918 (if_then_else (match_operand 1 "arx_reg_operand" "")
919 (const_int 1) (const_int 0))
920 (eq_attr "type" "binary,binarycc")
921 (if_then_else (match_operand 2 "arx_reg_operand" "")
922 (const_int 1) (const_int 0))]
923 (const_int 0)))
924
925
926 ;
927 ; C4x INSN PATTERNS:
928 ;
929 ; Note that the movMM and addP patterns can be called during reload
930 ; so we need to take special care with theses patterns since
931 ; we cannot blindly clobber CC or generate new pseudo registers.
932
933 ;
934 ; TWO OPERAND INTEGER INSTRUCTIONS
935 ;
936
937 ;
938 ; LDP/LDPK
939 ;
940 (define_insn "set_ldp"
941 [(set (match_operand:QI 0 "dp_reg_operand" "=z")
942 (high:QI (match_operand:QI 1 "" "")))]
943 "! TARGET_SMALL"
944 "* return (TARGET_C3X) ? \"ldp\\t%A1\" : \"ldpk\\t%A1\";"
945 [(set_attr "type" "ldp")])
946
947 (define_insn "set_ldp_prologue"
948 [(set (match_operand:QI 0 "dp_reg_operand" "=z")
949 (high:QI (match_operand:QI 1 "" "")))]
950 "TARGET_SMALL && TARGET_PARANOID"
951 "* return (TARGET_C3X) ? \"ldp\\t@data_sec\" : \"ldpk\\t@data_sec\";"
952 [(set_attr "type" "ldp")])
953
954 (define_insn "set_high"
955 [(set (match_operand:QI 0 "std_reg_operand" "=c")
956 (high:QI (match_operand:QI 1 "symbolic_address_operand" "")))]
957 "! TARGET_C3X && ! TARGET_TI"
958 "ldhi\\t^%H1,%0"
959 [(set_attr "type" "unary")])
960
961 (define_insn "set_lo_sum"
962 [(set (match_operand:QI 0 "std_reg_operand" "+c")
963 (lo_sum:QI (match_dup 0)
964 (match_operand:QI 1 "symbolic_address_operand" "")))]
965 "! TARGET_TI"
966 "or\\t#%H1,%0"
967 [(set_attr "type" "unary")])
968
969 (define_split
970 [(set (match_operand:QI 0 "std_reg_operand" "")
971 (match_operand:QI 1 "symbolic_address_operand" ""))]
972 "reload_completed && ! TARGET_C3X && ! TARGET_TI"
973 [(set (match_dup 0) (high:QI (match_dup 1)))
974 (set (match_dup 0) (lo_sum:QI (match_dup 0) (match_dup 1)))]
975 "")
976
977 (define_split
978 [(set (match_operand:QI 0 "reg_operand" "")
979 (match_operand:QI 1 "const_int_operand" ""))
980 (clobber (reg:QI 16))]
981 "! TARGET_C3X
982 && ! IS_INT16_CONST (INTVAL (operands[1]))
983 && ! IS_HIGH_CONST (INTVAL (operands[1]))
984 && reload_completed
985 && std_reg_operand (operands[0], QImode)"
986 [(set (match_dup 0) (match_dup 2))
987 (set (match_dup 0) (ior:QI (match_dup 0) (match_dup 3)))]
988 "
989 {
990 operands[2] = GEN_INT (INTVAL (operands[1]) & ~0xffff);
991 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
992 }")
993
994 (define_split
995 [(set (match_operand:QI 0 "reg_operand" "")
996 (match_operand:QI 1 "const_int_operand" ""))]
997 "! TARGET_C3X
998 && ! IS_INT16_CONST (INTVAL (operands[1]))
999 && ! IS_HIGH_CONST (INTVAL (operands[1]))
1000 && reload_completed
1001 && std_reg_operand (operands[0], QImode)"
1002 [(set (match_dup 0) (match_dup 2))
1003 (set (match_dup 0) (ior:QI (match_dup 0) (match_dup 3)))]
1004 "
1005 {
1006 operands[2] = GEN_INT (INTVAL (operands[1]) & ~0xffff);
1007 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
1008 }")
1009
1010 (define_split
1011 [(set (match_operand:QI 0 "reg_operand" "")
1012 (match_operand:QI 1 "const_int_operand" ""))
1013 (clobber (reg:QI 16))]
1014 "TARGET_C3X && ! TARGET_SMALL
1015 && ! IS_INT16_CONST (INTVAL (operands[1]))
1016 && reload_completed
1017 && std_reg_operand (operands[0], QImode)
1018 && c4x_shiftable_constant (operands[1]) < 0"
1019 [(set (match_dup 0) (match_dup 2))
1020 (set (match_dup 0) (ashift:QI (match_dup 0) (match_dup 4)))
1021 (set (match_dup 0) (ior:QI (match_dup 0) (match_dup 3)))]
1022 "
1023 {
1024 /* Generate two's complement value of 16 MSBs. */
1025 operands[2] = GEN_INT ((((INTVAL (operands[1]) >> 16) & 0xffff)
1026 - 0x8000) ^ ~0x7fff);
1027 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
1028 operands[4] = GEN_INT (16);
1029 }")
1030
1031 (define_split
1032 [(set (match_operand:QI 0 "reg_operand" "")
1033 (match_operand:QI 1 "const_int_operand" ""))]
1034 "TARGET_C3X && ! TARGET_SMALL
1035 && ! IS_INT16_CONST (INTVAL (operands[1]))
1036 && reload_completed
1037 && std_reg_operand (operands[0], QImode)
1038 && c4x_shiftable_constant (operands[1]) < 0"
1039 [(set (match_dup 0) (match_dup 2))
1040 (set (match_dup 0) (ashift:QI (match_dup 0) (match_dup 4)))
1041 (set (match_dup 0) (ior:QI (match_dup 0) (match_dup 3)))]
1042 "
1043 {
1044 /* Generate two's complement value of 16 MSBs. */
1045 operands[2] = GEN_INT ((((INTVAL (operands[1]) >> 16) & 0xffff)
1046 - 0x8000) ^ ~0x7fff);
1047 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
1048 operands[4] = GEN_INT (16);
1049 }")
1050
1051 (define_split
1052 [(set (match_operand:QI 0 "reg_operand" "")
1053 (match_operand:QI 1 "const_int_operand" ""))
1054 (clobber (reg:QI 16))]
1055 "TARGET_C3X
1056 && ! IS_INT16_CONST (INTVAL (operands[1]))
1057 && reload_completed
1058 && std_reg_operand (operands[0], QImode)
1059 && c4x_shiftable_constant (operands[1]) >= 0"
1060 [(set (match_dup 0) (match_dup 2))
1061 (set (match_dup 0) (ashift:QI (match_dup 0) (match_dup 3)))]
1062 "
1063 {
1064 /* Generate two's complement value of MSBs. */
1065 int shift = c4x_shiftable_constant (operands[1]);
1066
1067 operands[2] = GEN_INT ((((INTVAL (operands[1]) >> shift) & 0xffff)
1068 - 0x8000) ^ ~0x7fff);
1069 operands[3] = GEN_INT (shift);
1070 }")
1071
1072 (define_split
1073 [(set (match_operand:QI 0 "reg_operand" "")
1074 (match_operand:QI 1 "const_int_operand" ""))]
1075 "TARGET_C3X
1076 && ! IS_INT16_CONST (INTVAL (operands[1]))
1077 && reload_completed
1078 && std_reg_operand (operands[0], QImode)
1079 && c4x_shiftable_constant (operands[1]) >= 0"
1080 [(set (match_dup 0) (match_dup 2))
1081 (set (match_dup 0) (ashift:QI (match_dup 0) (match_dup 3)))]
1082 "
1083 {
1084 /* Generate two's complement value of MSBs. */
1085 int shift = c4x_shiftable_constant (operands[1]);
1086
1087 operands[2] = GEN_INT ((((INTVAL (operands[1]) >> shift) & 0xffff)
1088 - 0x8000) ^ ~0x7fff);
1089 operands[3] = GEN_INT (shift);
1090 }")
1091
1092 (define_split
1093 [(set (match_operand:QI 0 "reg_operand" "")
1094 (match_operand:QI 1 "const_int_operand" ""))
1095 (clobber (reg:QI 16))]
1096 "! TARGET_SMALL
1097 && ! IS_INT16_CONST (INTVAL (operands[1]))
1098 && ! IS_HIGH_CONST (INTVAL (operands[1]))
1099 && reload_completed
1100 && ! std_reg_operand (operands[0], QImode)"
1101 [(set (match_dup 2) (high:QI (match_dup 3)))
1102 (set (match_dup 0) (match_dup 4))
1103 (use (match_dup 1))]
1104 "
1105 {
1106 rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
1107 operands[2] = dp_reg;
1108 operands[3] = force_const_mem (Pmode, operands[1]);
1109 operands[4] = change_address (operands[3], QImode,
1110 gen_rtx_LO_SUM (Pmode, dp_reg,
1111 XEXP (operands[3], 0)));
1112 operands[3] = XEXP (operands[3], 0);
1113 }")
1114
1115 (define_split
1116 [(set (match_operand:QI 0 "reg_operand" "")
1117 (match_operand:QI 1 "const_int_operand" ""))]
1118 "! TARGET_SMALL
1119 && ! IS_INT16_CONST (INTVAL (operands[1]))
1120 && ! IS_HIGH_CONST (INTVAL (operands[1]))
1121 && reload_completed
1122 && ! std_reg_operand (operands[0], QImode)"
1123 [(set (match_dup 2) (high:QI (match_dup 3)))
1124 (set (match_dup 0) (match_dup 4))
1125 (use (match_dup 1))]
1126 "
1127 {
1128 rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
1129 operands[2] = dp_reg;
1130 operands[3] = force_const_mem (Pmode, operands[1]);
1131 operands[4] = change_address (operands[3], QImode,
1132 gen_rtx_LO_SUM (Pmode, dp_reg,
1133 XEXP (operands[3], 0)));
1134 operands[3] = XEXP (operands[3], 0);
1135 }")
1136
1137 (define_split
1138 [(set (match_operand:QI 0 "reg_operand" "")
1139 (match_operand:QI 1 "const_int_operand" ""))
1140 (clobber (reg:QI 16))]
1141 "TARGET_SMALL
1142 && ! IS_INT16_CONST (INTVAL (operands[1]))
1143 && ! IS_HIGH_CONST (INTVAL (operands[1]))
1144 && reload_completed
1145 && ((TARGET_C3X && c4x_shiftable_constant (operands[1]) < 0)
1146 || ! std_reg_operand (operands[0], QImode))"
1147 [(set (match_dup 0) (match_dup 2))
1148 (use (match_dup 1))]
1149 "
1150 {
1151 rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
1152 operands[2] = force_const_mem (Pmode, operands[1]);
1153 operands[2] = change_address (operands[2], QImode,
1154 gen_rtx_LO_SUM (Pmode, dp_reg,
1155 XEXP (operands[2], 0)));
1156 }")
1157
1158 (define_split
1159 [(set (match_operand:QI 0 "reg_operand" "")
1160 (match_operand:QI 1 "const_int_operand" ""))]
1161 "TARGET_SMALL
1162 && ! IS_INT16_CONST (INTVAL (operands[1]))
1163 && ! IS_HIGH_CONST (INTVAL (operands[1]))
1164 && reload_completed
1165 && ((TARGET_C3X && c4x_shiftable_constant (operands[1]) < 0)
1166 || ! std_reg_operand (operands[0], QImode))"
1167 [(set (match_dup 0) (match_dup 2))
1168 (use (match_dup 1))]
1169 "
1170 {
1171 rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
1172 operands[2] = force_const_mem (Pmode, operands[1]);
1173 operands[2] = change_address (operands[2], QImode,
1174 gen_rtx_LO_SUM (Pmode, dp_reg,
1175 XEXP (operands[2], 0)));
1176 }")
1177
1178 (define_split
1179 [(set (match_operand:HI 0 "reg_operand" "")
1180 (match_operand:HI 1 "const_int_operand" ""))
1181 (clobber (reg:QI 16))]
1182 "reload_completed"
1183 [(set (match_dup 2) (match_dup 4))
1184 (set (match_dup 3) (match_dup 5))]
1185 "
1186 {
1187 operands[2] = c4x_operand_subword (operands[0], 0, 1, HImode);
1188 operands[3] = c4x_operand_subword (operands[0], 1, 1, HImode);
1189 operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
1190 operands[5] = c4x_operand_subword (operands[1], 1, 1, HImode);
1191 }")
1192
1193
1194 ; We need to clobber the DP reg to be safe in case we
1195 ; need to load this address from memory
1196 (define_insn "load_immed_address"
1197 [(set (match_operand:QI 0 "reg_operand" "=a?x?c*r")
1198 (match_operand:QI 1 "symbolic_address_operand" ""))
1199 (clobber (reg:QI 16))]
1200 "TARGET_LOAD_ADDRESS"
1201 "#"
1202 [(set_attr "type" "multi")])
1203
1204
1205 (define_split
1206 [(set (match_operand:QI 0 "std_reg_operand" "")
1207 (match_operand:QI 1 "symbolic_address_operand" ""))
1208 (clobber (reg:QI 16))]
1209 "reload_completed && ! TARGET_C3X && ! TARGET_TI"
1210 [(set (match_dup 0) (high:QI (match_dup 1)))
1211 (set (match_dup 0) (lo_sum:QI (match_dup 0) (match_dup 1)))]
1212 "")
1213
1214 ; CC has been selected to load a symbolic address. We force the address
1215 ; into memory and then generate LDP and LDIU insns.
1216 ; This is also required for the C30 if we pretend that we can
1217 ; easily load symbolic addresses into a register.
1218 (define_split
1219 [(set (match_operand:QI 0 "reg_operand" "")
1220 (match_operand:QI 1 "symbolic_address_operand" ""))
1221 (clobber (reg:QI 16))]
1222 "reload_completed
1223 && ! TARGET_SMALL
1224 && (TARGET_C3X || TARGET_TI || ! std_reg_operand (operands[0], QImode))"
1225 [(set (match_dup 2) (high:QI (match_dup 3)))
1226 (set (match_dup 0) (match_dup 4))
1227 (use (match_dup 1))]
1228 "
1229 {
1230 rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
1231 operands[2] = dp_reg;
1232 operands[3] = force_const_mem (Pmode, operands[1]);
1233 operands[4] = change_address (operands[3], QImode,
1234 gen_rtx_LO_SUM (Pmode, dp_reg,
1235 XEXP (operands[3], 0)));
1236 operands[3] = XEXP (operands[3], 0);
1237 }")
1238
1239 ; This pattern is similar to the above but does not emit a LDP
1240 ; for the small memory model.
1241 (define_split
1242 [(set (match_operand:QI 0 "reg_operand" "")
1243 (match_operand:QI 1 "symbolic_address_operand" ""))
1244 (clobber (reg:QI 16))]
1245 "reload_completed
1246 && TARGET_SMALL
1247 && (TARGET_C3X || TARGET_TI || ! std_reg_operand (operands[0], QImode))"
1248 [(set (match_dup 0) (match_dup 2))
1249 (use (match_dup 1))]
1250 "
1251 {
1252 rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
1253 operands[2] = force_const_mem (Pmode, operands[1]);
1254 operands[2] = change_address (operands[2], QImode,
1255 gen_rtx_LO_SUM (Pmode, dp_reg,
1256 XEXP (operands[2], 0)));
1257 }")
1258
1259 (define_insn "loadhi_big_constant"
1260 [(set (match_operand:HI 0 "reg_operand" "=c*d")
1261 (match_operand:HI 1 "const_int_operand" ""))
1262 (clobber (reg:QI 16))]
1263 ""
1264 "#"
1265 [(set_attr "type" "multi")])
1266
1267 ;
1268 ; LDIU/LDA/STI/STIK
1269 ;
1270 ; The following moves will not set the condition codes register.
1271 ;
1272
1273 ; This must come before the general case
1274 (define_insn "*movqi_stik"
1275 [(set (match_operand:QI 0 "memory_operand" "=m")
1276 (match_operand:QI 1 "stik_const_operand" "K"))]
1277 "! TARGET_C3X"
1278 "stik\\t%1,%0"
1279 [(set_attr "type" "store")])
1280
1281 (define_insn "loadqi_big_constant"
1282 [(set (match_operand:QI 0 "reg_operand" "=c*d")
1283 (match_operand:QI 1 "const_int_operand" ""))
1284 (clobber (reg:QI 16))]
1285 "! IS_INT16_CONST (INTVAL (operands[1]))
1286 && ! IS_HIGH_CONST (INTVAL (operands[1]))"
1287 "#"
1288 [(set_attr "type" "multi")])
1289
1290 ; We must provide an alternative to store to memory in case we have to
1291 ; spill a register.
1292 (define_insn "movqi_noclobber"
1293 [(set (match_operand:QI 0 "dst_operand" "=d,*c,m,r")
1294 (match_operand:QI 1 "src_hi_operand" "rIm,rIm,r,O"))]
1295 "(REG_P (operands[0]) || REG_P (operands[1])
1296 || GET_CODE (operands[0]) == SUBREG
1297 || GET_CODE (operands[1]) == SUBREG)
1298 && ! symbolic_address_operand (operands[1], QImode)"
1299 "*
1300 if (which_alternative == 2)
1301 return \"sti\\t%1,%0\";
1302
1303 if (! TARGET_C3X && which_alternative == 3)
1304 {
1305 operands[1] = GEN_INT ((INTVAL (operands[1]) >> 16) & 0xffff);
1306 return \"ldhi\\t%1,%0\";
1307 }
1308
1309 /* The lda instruction cannot use the same register as source
1310 and destination. */
1311 if (! TARGET_C3X && which_alternative == 1
1312 && ( IS_ADDR_REG (operands[0])
1313 || IS_INDEX_REG (operands[0])
1314 || IS_SP_REG (operands[0]))
1315 && (REGNO (operands[0]) != REGNO (operands[1])))
1316 return \"lda\\t%1,%0\";
1317 return \"ldiu\\t%1,%0\";
1318 "
1319 [(set_attr "type" "unary,lda,store,unary")
1320 (set_attr "data" "int16,int16,int16,high_16")])
1321
1322 ;
1323 ; LDI
1324 ;
1325
1326 ; We shouldn't need these peepholes, but the combiner seems to miss them...
1327 (define_peephole
1328 [(set (match_operand:QI 0 "ext_reg_operand" "=d")
1329 (match_operand:QI 1 "src_operand" "rIm"))
1330 (set (reg:CC 21)
1331 (compare:CC (match_dup 0) (const_int 0)))]
1332 ""
1333 "ldi\\t%1,%0"
1334 [(set_attr "type" "unarycc")
1335 (set_attr "data" "int16")])
1336
1337 (define_insn "*movqi_set"
1338 [(set (reg:CC 21)
1339 (compare:CC (match_operand:QI 1 "src_operand" "rIm")
1340 (const_int 0)))
1341 (set (match_operand:QI 0 "ext_reg_operand" "=d")
1342 (match_dup 1))]
1343 ""
1344 "ldi\\t%1,%0"
1345 [(set_attr "type" "unarycc")
1346 (set_attr "data" "int16")])
1347
1348 ; This pattern probably gets in the way and requires a scratch register
1349 ; when a simple compare with zero will suffice.
1350 ;(define_insn "*movqi_test"
1351 ; [(set (reg:CC 21)
1352 ; (compare:CC (match_operand:QI 1 "src_operand" "rIm")
1353 ; (const_int 0)))
1354 ; (clobber (match_scratch:QI 0 "=d"))]
1355 ; ""
1356 ; "@
1357 ; ldi\\t%1,%0"
1358 ; [(set_attr "type" "unarycc")
1359 ; (set_attr "data" "int16")])
1360
1361 ; If one of the operands is not a register, then we should
1362 ; emit two insns, using a scratch register. This will produce
1363 ; better code in loops if the source operand is invariant, since
1364 ; the source reload can be optimized out. During reload we cannot
1365 ; use change_address or force_reg which will allocate new pseudo regs.
1366
1367 ; Unlike most other insns, the move insns can't be split with
1368 ; different predicates, because register spilling and other parts of
1369 ; the compiler, have memoized the insn number already.
1370
1371 (define_expand "movqi"
1372 [(set (match_operand:QI 0 "general_operand" "")
1373 (match_operand:QI 1 "general_operand" ""))]
1374 ""
1375 "
1376 {
1377 if (c4x_emit_move_sequence (operands, QImode))
1378 DONE;
1379 }")
1380
1381
1382 ; As far as GCC is concerned, the moves are performed in parallel
1383 ; thus it must be convinced that there is no aliasing.
1384 ; It also assumes that the input operands are simultaneously loaded
1385 ; and then the output operands are simultaneously stored.
1386 ; With the C4x, if there are parallel stores to the same address
1387 ; both stores are executed.
1388 ; If there is a parallel load and store to the same address,
1389 ; the load is performed first.
1390 ; The problem with this pattern is that reload can spoil
1391 ; the show when it eliminates a reference to the frame pointer.
1392 ; This can invalidate the memory addressing mode, i.e., when
1393 ; the displacement is greater than 1.
1394 (define_insn "movqi_parallel"
1395 [(set (match_operand:QI 0 "parallel_operand" "=q,S<>!V,q,S<>!V")
1396 (match_operand:QI 1 "parallel_operand" "S<>!V,q,S<>!V,q"))
1397 (set (match_operand:QI 2 "parallel_operand" "=q,S<>!V,S<>!V,q")
1398 (match_operand:QI 3 "parallel_operand" "S<>!V,q,q,S<>!V"))]
1399 "TARGET_PARALLEL && valid_parallel_load_store (operands, QImode)"
1400 "@
1401 ldi1\\t%1,%0\\n||\\tldi2\\t%3,%2
1402 sti1\\t%1,%0\\n||\\tsti2\\t%3,%2
1403 ldi\\t%1,%0\\n||\\tsti\\t%3,%2
1404 ldi\\t%3,%2\\n||\\tsti\\t%1,%0"
1405 [(set_attr "type" "load_load,store_store,load_store,store_load")])
1406
1407 ;
1408 ; PUSH/POP
1409 ;
1410 (define_insn "pushqi"
1411 [(set (mem:QI (pre_inc:QI (reg:QI 20)))
1412 (match_operand:QI 0 "reg_operand" "r"))]
1413 ""
1414 "push\\t%0"
1415 [(set_attr "type" "push")])
1416
1417 (define_insn "push_st"
1418 [(set (mem:QI (pre_inc:QI (reg:QI 20)))
1419 (unspec:QI [(reg:QI 21)] UNSPEC_PUSH_ST))
1420 (use (reg:QI 21))]
1421 ""
1422 "push\\tst"
1423 [(set_attr "type" "push")])
1424
1425 (define_insn "push_dp"
1426 [(set (mem:QI (pre_inc:QI (reg:QI 20)))
1427 (unspec:QI [(reg:QI 16)] UNSPEC_PUSH_DP))
1428 (use (reg:QI 16))]
1429 ""
1430 "push\\tdp"
1431 [(set_attr "type" "push")])
1432
1433 (define_insn "popqi"
1434 [(set (match_operand:QI 0 "reg_operand" "=r")
1435 (mem:QI (post_dec:QI (reg:QI 20))))
1436 (clobber (reg:CC 21))]
1437 ""
1438 "pop\\t%0"
1439 [(set_attr "type" "pop")])
1440
1441 (define_insn "pop_st"
1442 [(set (unspec:QI [(reg:QI 21)] UNSPEC_POP_ST)
1443 (mem:QI (post_dec:QI (reg:QI 20))))
1444 (clobber (reg:CC 21))]
1445 ""
1446 "pop\\tst"
1447 [(set_attr "type" "pop")])
1448
1449 (define_insn "pop_dp"
1450 [(set (unspec:QI [(reg:QI 16)] UNSPEC_POP_DP)
1451 (mem:QI (post_dec:QI (reg:QI 20))))
1452 (clobber (reg:CC 16))]
1453 ""
1454 "pop\\tdp"
1455 [(set_attr "type" "pop")])
1456
1457 (define_insn "popqi_unspec"
1458 [(set (unspec:QI [(match_operand:QI 0 "reg_operand" "=r")] UNSPEC_POPQI)
1459 (mem:QI (post_dec:QI (reg:QI 20))))
1460 (clobber (match_dup 0))
1461 (clobber (reg:CC 21))]
1462 ""
1463 "pop\\t%0"
1464 [(set_attr "type" "pop")])
1465
1466 ;
1467 ; ABSI
1468 ;
1469 (define_expand "absqi2"
1470 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
1471 (abs:QI (match_operand:QI 1 "src_operand" "")))
1472 (clobber (reg:CC_NOOV 21))])]
1473 ""
1474 "")
1475
1476 (define_insn "*absqi2_clobber"
1477 [(set (match_operand:QI 0 "reg_operand" "=d,c")
1478 (abs:QI (match_operand:QI 1 "src_operand" "rIm,rIm")))
1479 (clobber (reg:CC_NOOV 21))]
1480 ""
1481 "absi\\t%1,%0"
1482 [(set_attr "type" "unarycc,unary")
1483 (set_attr "data" "int16,int16")])
1484
1485 (define_insn "*absqi2_noclobber"
1486 [(set (match_operand:QI 0 "std_reg_operand" "=c")
1487 (abs:QI (match_operand:QI 1 "src_operand" "rIm")))]
1488 ""
1489 "absi\\t%1,%0"
1490 [(set_attr "type" "unary")
1491 (set_attr "data" "int16")])
1492
1493 (define_split
1494 [(set (match_operand:QI 0 "std_reg_operand" "")
1495 (abs:QI (match_operand:QI 1 "src_operand" "")))
1496 (clobber (reg:CC_NOOV 21))]
1497 "reload_completed"
1498 [(set (match_dup 0)
1499 (abs:QI (match_dup 1)))]
1500 "")
1501
1502 (define_insn "*absqi2_test"
1503 [(set (reg:CC_NOOV 21)
1504 (compare:CC_NOOV (abs:QI (match_operand:QI 1 "src_operand" "rIm"))
1505 (const_int 0)))
1506 (clobber (match_scratch:QI 0 "=d"))]
1507 ""
1508 "absi\\t%1,%0"
1509 [(set_attr "type" "unarycc")
1510 (set_attr "data" "int16")])
1511
1512 (define_insn "*absqi2_set"
1513 [(set (reg:CC_NOOV 21)
1514 (compare:CC_NOOV (abs:QI (match_operand:QI 1 "src_operand" "rIm"))
1515 (const_int 0)))
1516 (set (match_operand:QI 0 "ext_reg_operand" "=d")
1517 (abs:QI (match_dup 1)))]
1518 ""
1519 "absi\\t%1,%0"
1520 [(set_attr "type" "unarycc")
1521 (set_attr "data" "int16")])
1522
1523 ;
1524 ; NEGI
1525 ;
1526 (define_expand "negqi2"
1527 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
1528 (neg:QI (match_operand:QI 1 "src_operand" "")))
1529 (clobber (reg:CC_NOOV 21))])]
1530 ""
1531 "")
1532
1533 (define_insn "*negqi2_clobber"
1534 [(set (match_operand:QI 0 "reg_operand" "=d,c")
1535 (neg:QI (match_operand:QI 1 "src_operand" "rIm,rIm")))
1536 (clobber (reg:CC_NOOV 21))]
1537 ""
1538 "negi\\t%1,%0"
1539 [(set_attr "type" "unarycc,unary")
1540 (set_attr "data" "int16,int16")])
1541
1542 (define_insn "*negqi2_noclobber"
1543 [(set (match_operand:QI 0 "std_reg_operand" "=c")
1544 (neg:QI (match_operand:QI 1 "src_operand" "rIm")))]
1545 ""
1546 "negi\\t%1,%0"
1547 [(set_attr "type" "unary")
1548 (set_attr "data" "int16")])
1549
1550 (define_split
1551 [(set (match_operand:QI 0 "std_reg_operand" "")
1552 (neg:QI (match_operand:QI 1 "src_operand" "")))
1553 (clobber (reg:CC_NOOV 21))]
1554 "reload_completed"
1555 [(set (match_dup 0)
1556 (neg:QI (match_dup 1)))]
1557 "")
1558
1559 (define_insn "*negqi2_test"
1560 [(set (reg:CC_NOOV 21)
1561 (compare:CC_NOOV (neg:QI (match_operand:QI 1 "src_operand" "rIm"))
1562 (const_int 0)))
1563 (clobber (match_scratch:QI 0 "=d"))]
1564 ""
1565 "negi\\t%1,%0"
1566 [(set_attr "type" "unarycc")
1567 (set_attr "data" "int16")])
1568
1569 (define_insn "*negqi2_set"
1570 [(set (reg:CC_NOOV 21)
1571 (compare:CC_NOOV (neg:QI (match_operand:QI 1 "src_operand" "rIm"))
1572 (const_int 0)))
1573 (set (match_operand:QI 0 "ext_reg_operand" "=d")
1574 (neg:QI (match_dup 1)))]
1575 ""
1576 "negi\\t%1,%0"
1577 [(set_attr "type" "unarycc")
1578 (set_attr "data" "int16")])
1579
1580 (define_insn "*negbqi2_clobber"
1581 [(set (match_operand:QI 0 "ext_reg_operand" "=d")
1582 (neg:QI (match_operand:QI 1 "src_operand" "rIm")))
1583 (use (reg:CC_NOOV 21))
1584 (clobber (reg:CC_NOOV 21))]
1585 ""
1586 "negb\\t%1,%0"
1587 [(set_attr "type" "unarycc")
1588 (set_attr "data" "int16")])
1589
1590 ;
1591 ; NOT
1592 ;
1593 (define_expand "one_cmplqi2"
1594 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
1595 (not:QI (match_operand:QI 1 "lsrc_operand" "")))
1596 (clobber (reg:CC 21))])]
1597 ""
1598 "")
1599
1600 (define_insn "*one_cmplqi2_clobber"
1601 [(set (match_operand:QI 0 "reg_operand" "=d,c")
1602 (not:QI (match_operand:QI 1 "lsrc_operand" "rLm,rLm")))
1603 (clobber (reg:CC 21))]
1604 ""
1605 "not\\t%1,%0"
1606 [(set_attr "type" "unarycc,unary")
1607 (set_attr "data" "uint16,uint16")])
1608
1609 (define_insn "*one_cmplqi2_noclobber"
1610 [(set (match_operand:QI 0 "std_reg_operand" "=c")
1611 (not:QI (match_operand:QI 1 "lsrc_operand" "rLm")))]
1612 ""
1613 "not\\t%1,%0"
1614 [(set_attr "type" "unary")
1615 (set_attr "data" "uint16")])
1616
1617 (define_split
1618 [(set (match_operand:QI 0 "std_reg_operand" "")
1619 (not:QI (match_operand:QI 1 "lsrc_operand" "")))
1620 (clobber (reg:CC 21))]
1621 "reload_completed"
1622 [(set (match_dup 0)
1623 (not:QI (match_dup 1)))]
1624 "")
1625
1626 (define_insn "*one_cmplqi2_test"
1627 [(set (reg:CC 21)
1628 (compare:CC (not:QI (match_operand:QI 1 "lsrc_operand" "rLm"))
1629 (const_int 0)))
1630 (clobber (match_scratch:QI 0 "=d"))]
1631 ""
1632 "not\\t%1,%0"
1633 [(set_attr "type" "unarycc")
1634 (set_attr "data" "uint16")])
1635
1636 (define_insn "*one_cmplqi2_set"
1637 [(set (reg:CC 21)
1638 (compare:CC (not:QI (match_operand:QI 1 "lsrc_operand" "rLm"))
1639 (const_int 0)))
1640 (set (match_operand:QI 0 "ext_reg_operand" "=d")
1641 (not:QI (match_dup 1)))]
1642 ""
1643 "not\\t%1,%0"
1644 [(set_attr "type" "unarycc")
1645 (set_attr "data" "uint16")])
1646
1647 (define_insn "*one_cmplqi2_const_clobber"
1648 [(set (match_operand:QI 0 "reg_operand" "=d,c")
1649 (match_operand:QI 1 "not_const_operand" "N,N"))
1650 (clobber (reg:CC 21))]
1651 ""
1652 "@
1653 not\\t%N1,%0
1654 not\\t%N1,%0"
1655 [(set_attr "type" "unarycc,unary")
1656 (set_attr "data" "not_uint16,not_uint16")])
1657
1658 ; movqi can use this for loading an integer that can't normally
1659 ; fit into a 16-bit signed integer. The drawback is that it cannot
1660 ; go into R0-R11 since that will clobber the CC and movqi shouldn't
1661 ; do that. This can cause additional reloading but in most cases
1662 ; this will cause only an additional register move. With the large
1663 ; memory model we require an extra instruction to load DP anyway,
1664 ; if we're loading the constant from memory. The big advantage of
1665 ; allowing constants that satisfy not_const_operand in movqi, is that
1666 ; it allows andn to be generated more often.
1667 ; However, there is a problem if GCC has decided that it wants
1668 ; to use R0-R11, since we won't have a matching pattern...
1669 ; In interim, we prevent immed_const allowing `N' constants.
1670 (define_insn "*one_cmplqi2_const_noclobber"
1671 [(set (match_operand:QI 0 "std_reg_operand" "=c")
1672 (match_operand:QI 1 "not_const_operand" "N"))]
1673 ""
1674 "not\\t%N1,%0"
1675 [(set_attr "type" "unary")
1676 (set_attr "data" "not_uint16")])
1677
1678 ;
1679 ; ROL
1680 ;
1681 (define_expand "rotlqi3"
1682 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
1683 (rotate:QI (match_operand:QI 1 "reg_operand" "")
1684 (match_operand:QI 2 "const_int_operand" "")))
1685 (clobber (reg:CC 21))])]
1686 ""
1687 "if (INTVAL (operands[2]) > 4)
1688 FAIL; /* Open code as two shifts and an or */
1689 if (INTVAL (operands[2]) > 1)
1690 {
1691 int i;
1692 rtx tmp;
1693
1694 /* If we have 4 or fewer shifts, then it is probably faster
1695 to emit separate ROL instructions. A C3x requires
1696 at least 4 instructions (a C4x requires at least 3), to
1697 perform a rotation by shifts. */
1698
1699 tmp = operands[1];
1700 for (i = 0; i < INTVAL (operands[2]) - 1; i++)
1701 {
1702 tmp = gen_reg_rtx (QImode);
1703 emit_insn (gen_rotl_1_clobber (tmp, operands[1]));
1704 operands[1] = tmp;
1705 }
1706 emit_insn (gen_rotl_1_clobber (operands[0], tmp));
1707 DONE;
1708 }")
1709
1710 (define_insn "rotl_1_clobber"
1711 [(set (match_operand:QI 0 "reg_operand" "=d,c")
1712 (rotate:QI (match_operand:QI 1 "reg_operand" "0,0")
1713 (const_int 1)))
1714 (clobber (reg:CC 21))]
1715 ""
1716 "rol\\t%0"
1717 [(set_attr "type" "unarycc,unary")])
1718 ; Default to int16 data attr.
1719
1720 ;
1721 ; ROR
1722 ;
1723 (define_expand "rotrqi3"
1724 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
1725 (rotatert:QI (match_operand:QI 1 "reg_operand" "")
1726 (match_operand:QI 2 "const_int_operand" "")))
1727 (clobber (reg:CC 21))])]
1728 ""
1729 "if (INTVAL (operands[2]) > 4)
1730 FAIL; /* Open code as two shifts and an or */
1731 if (INTVAL (operands[2]) > 1)
1732 {
1733 int i;
1734 rtx tmp;
1735
1736 /* If we have 4 or fewer shifts, then it is probably faster
1737 to emit separate ROL instructions. A C3x requires
1738 at least 4 instructions (a C4x requires at least 3), to
1739 perform a rotation by shifts. */
1740
1741 tmp = operands[1];
1742 for (i = 0; i < INTVAL (operands[2]) - 1; i++)
1743 {
1744 tmp = gen_reg_rtx (QImode);
1745 emit_insn (gen_rotr_1_clobber (tmp, operands[1]));
1746 operands[1] = tmp;
1747 }
1748 emit_insn (gen_rotr_1_clobber (operands[0], tmp));
1749 DONE;
1750 }")
1751
1752 (define_insn "rotr_1_clobber"
1753 [(set (match_operand:QI 0 "reg_operand" "=d,c")
1754 (rotatert:QI (match_operand:QI 1 "reg_operand" "0,0")
1755 (const_int 1)))
1756 (clobber (reg:CC 21))]
1757 ""
1758 "ror\\t%0"
1759 [(set_attr "type" "unarycc,unary")])
1760 ; Default to int16 data attr.
1761
1762
1763 ;
1764 ; THREE OPERAND INTEGER INSTRUCTIONS
1765 ;
1766
1767 ;
1768 ; ADDI
1769 ;
1770 ; This is used by reload when it calls gen_add2_insn for address arithmetic
1771 ; so we must emit the pattern that doesn't clobber CC.
1772 ;
1773 (define_expand "addqi3"
1774 [(parallel [(set (match_operand:QI 0 "std_or_reg_operand" "")
1775 (plus:QI (match_operand:QI 1 "src_operand" "")
1776 (match_operand:QI 2 "src_operand" "")))
1777 (clobber (reg:CC_NOOV 21))])]
1778 ""
1779 "legitimize_operands (PLUS, operands, QImode);
1780 if (reload_in_progress
1781 || (! IS_PSEUDO_REG (operands[0])
1782 && ! IS_EXT_REG (operands[0])))
1783 {
1784 emit_insn (gen_addqi3_noclobber (operands[0], operands[1], operands[2]));
1785 DONE;
1786 }")
1787
1788 ; This pattern is required primarily for manipulating the stack pointer
1789 ; where GCC doesn't expect CC to be clobbered or for calculating
1790 ; addresses during reload. Since this is a more specific pattern
1791 ; it needs to go first (otherwise we get into problems trying to decide
1792 ; to add clobbers).
1793 (define_insn "addqi3_noclobber"
1794 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,c")
1795 (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
1796 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>")))]
1797 "valid_operands (PLUS, operands, QImode)"
1798 "@
1799 addi\\t%2,%0
1800 addi3\\t%2,%1,%0
1801 addi3\\t%2,%1,%0"
1802 [(set_attr "type" "binary,binary,binary")])
1803 ; Default to int16 data attr.
1804
1805 (define_insn "*addqi3_clobber"
1806 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
1807 (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>,0,rR,rS<>")
1808 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>,rIm,JR,rS<>")))
1809 (clobber (reg:CC_NOOV 21))]
1810 "valid_operands (PLUS, operands, QImode)"
1811 "@
1812 addi\\t%2,%0
1813 addi3\\t%2,%1,%0
1814 addi3\\t%2,%1,%0
1815 addi\\t%2,%0
1816 addi3\\t%2,%1,%0
1817 addi3\\t%2,%1,%0"
1818 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
1819 ; Default to int16 data attr.
1820
1821 (define_split
1822 [(set (match_operand:QI 0 "std_reg_operand" "")
1823 (plus:QI (match_operand:QI 1 "src_operand" "")
1824 (match_operand:QI 2 "src_operand" "")))
1825 (clobber (reg:CC_NOOV 21))]
1826 "reload_completed"
1827 [(set (match_dup 0)
1828 (plus:QI (match_dup 1)
1829 (match_dup 2)))]
1830 "")
1831
1832 (define_insn "*addqi3_test"
1833 [(set (reg:CC_NOOV 21)
1834 (compare:CC_NOOV (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
1835 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>"))
1836 (const_int 0)))
1837 (clobber (match_scratch:QI 0 "=d,d,d"))]
1838 "valid_operands (PLUS, operands, QImode)"
1839 "@
1840 addi\\t%2,%0
1841 addi3\\t%2,%1,%0
1842 addi3\\t%2,%1,%0"
1843 [(set_attr "type" "binarycc,binarycc,binarycc")])
1844 ; Default to int16 data attr.
1845
1846 ; gcc does this in combine.c we just reverse it here
1847 (define_insn "*cmp_neg"
1848 [(set (reg:CC_NOOV 21)
1849 (compare:CC_NOOV (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
1850 (neg: QI (match_operand:QI 2 "src_operand" "g,JR,rS<>"))))
1851 (clobber (match_scratch:QI 0 "=d,d,d"))]
1852 "valid_operands (PLUS, operands, QImode)"
1853 "@
1854 addi\\t%2,%0
1855 addi3\\t%2,%1,%0
1856 addi3\\t%2,%1,%0"
1857 [(set_attr "type" "binarycc,binarycc,binarycc")])
1858
1859 (define_peephole
1860 [(parallel [(set (match_operand:QI 0 "ext_reg_operand" "=d,d,d")
1861 (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
1862 (match_operand:QI 2 "src_operand" "g,JR,rS<>")))
1863 (clobber (reg:CC_NOOV 21))])
1864 (set (reg:CC_NOOV 21)
1865 (compare:CC_NOOV (match_dup 0) (const_int 0)))]
1866 "valid_operands (PLUS, operands, QImode)"
1867 "@
1868 addi\\t%2,%0
1869 addi3\\t%2,%1,%0
1870 addi3\\t%2,%1,%0"
1871 [(set_attr "type" "binarycc,binarycc,binarycc")])
1872
1873 (define_insn "*addqi3_set"
1874 [(set (reg:CC_NOOV 21)
1875 (compare:CC_NOOV (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
1876 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>"))
1877 (const_int 0)))
1878 (set (match_operand:QI 0 "ext_reg_operand" "=d,d,d")
1879 (plus:QI (match_dup 1) (match_dup 2)))]
1880 "valid_operands (PLUS, operands, QImode)"
1881 "@
1882 addi\\t%2,%0
1883 addi3\\t%2,%1,%0
1884 addi3\\t%2,%1,%0"
1885 [(set_attr "type" "binarycc,binarycc,binarycc")])
1886 ; Default to int16 data attr.
1887
1888
1889 ; This pattern is required during reload when eliminate_regs_in_insn
1890 ; effectively converts a move insn into an add insn when the src
1891 ; operand is the frame pointer plus a constant. Without this
1892 ; pattern, gen_addqi3 can be called with a register for operand0
1893 ; that can clobber CC.
1894 ; For example, we may have (set (mem (reg ar0)) (reg 99))
1895 ; with (set (reg 99) (plus (reg ar3) (const_int 8)))
1896 ; Now since ar3, the frame pointer, is unchanging within the function,
1897 ; (plus (reg ar3) (const_int 8)) is considered a constant.
1898 ; eliminate_regs_in_insn substitutes this constant to give
1899 ; (set (mem (reg ar0)) (plus (reg ar3) (const_int 8))).
1900 ; This is an invalid C4x insn but if we don't provide a pattern
1901 ; for it, it will be considered to be a move insn for reloading.
1902 (define_insn "*addqi3_noclobber_reload"
1903 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,c")
1904 (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
1905 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>")))]
1906 "reload_in_progress"
1907 "@
1908 addi\\t%2,%0
1909 addi3\\t%2,%1,%0
1910 addi3\\t%2,%1,%0"
1911 [(set_attr "type" "binary,binary,binary")])
1912 ; Default to int16 data attr.
1913
1914
1915 (define_insn "*addqi3_carry_clobber"
1916 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
1917 (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>,0,rR,rS<>")
1918 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>,rIm,JR,rS<>")))
1919 (use (reg:CC_NOOV 21))
1920 (clobber (reg:CC_NOOV 21))]
1921 "valid_operands (PLUS, operands, QImode)"
1922 "@
1923 addc\\t%2,%0
1924 addc3\\t%2,%1,%0
1925 addc3\\t%2,%1,%0
1926 addc\\t%2,%0
1927 addc3\\t%2,%1,%0
1928 addc3\\t%2,%1,%0"
1929 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
1930 ; Default to int16 data attr.
1931
1932
1933 ;
1934 ; SUBI/SUBRI
1935 ;
1936 (define_expand "subqi3"
1937 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
1938 (minus:QI (match_operand:QI 1 "src_operand" "")
1939 (match_operand:QI 2 "src_operand" "")))
1940 (clobber (reg:CC_NOOV 21))])]
1941 ""
1942 "legitimize_operands (MINUS, operands, QImode);")
1943
1944 (define_insn "*subqi3_clobber"
1945 [(set (match_operand:QI 0 "reg_operand" "=d,d,d,?d,c,c,c,?c")
1946 (minus:QI (match_operand:QI 1 "src_operand" "0,rIm,rR,rS<>,0,rIm,rR,rS<>")
1947 (match_operand:QI 2 "src_operand" "rIm,0,JR,rS<>,rIm,0,JR,rS<>")))
1948 (clobber (reg:CC_NOOV 21))]
1949 "valid_operands (MINUS, operands, QImode)"
1950 "@
1951 subi\\t%2,%0
1952 subri\\t%1,%0
1953 subi3\\t%2,%1,%0
1954 subi3\\t%2,%1,%0
1955 subi\\t%2,%0
1956 subri\\t%1,%0
1957 subi3\\t%2,%1,%0
1958 subi3\\t%2,%1,%0"
1959 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc,binary,binary,binary,binary")])
1960 ; Default to int16 data attr.
1961
1962 (define_split
1963 [(set (match_operand:QI 0 "std_reg_operand" "")
1964 (minus:QI (match_operand:QI 1 "src_operand" "")
1965 (match_operand:QI 2 "src_operand" "")))
1966 (clobber (reg:CC_NOOV 21))]
1967 "reload_completed"
1968 [(set (match_dup 0)
1969 (minus:QI (match_dup 1)
1970 (match_dup 2)))]
1971 "")
1972
1973 (define_insn "*subqi3_test"
1974 [(set (reg:CC_NOOV 21)
1975 (compare:CC_NOOV (minus:QI (match_operand:QI 1 "src_operand" "0,rIm,rR,rS<>")
1976 (match_operand:QI 2 "src_operand" "rIm,0,JR,rS<>"))
1977 (const_int 0)))
1978 (clobber (match_scratch:QI 0 "=d,d,d,?d"))]
1979 "valid_operands (MINUS, operands, QImode)"
1980 "@
1981 subi\\t%2,%0
1982 subri\\t%1,%0
1983 subi3\\t%2,%1,%0
1984 subi3\\t%2,%1,%0"
1985 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
1986 ; Default to int16 data attr.
1987
1988 (define_peephole
1989 [(parallel [(set (match_operand:QI 0 "ext_reg_operand" "=d,d,d,?d")
1990 (minus:QI (match_operand:QI 1 "src_operand" "0,rIm,rR,rS<>")
1991 (match_operand:QI 2 "src_operand" "rIm,0,JR,rS<>")))
1992 (clobber (reg:CC_NOOV 21))])
1993 (set (reg:CC_NOOV 21)
1994 (compare:CC_NOOV (match_dup 0) (const_int 0)))]
1995 "valid_operands (MINUS, operands, QImode)"
1996 "@
1997 subi\\t%2,%0
1998 subri\\t%1,%0
1999 subi3\\t%2,%1,%0
2000 subi3\\t%2,%1,%0"
2001 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
2002
2003 (define_insn "*subqi3_set"
2004 [(set (reg:CC_NOOV 21)
2005 (compare:CC_NOOV (minus:QI (match_operand:QI 1 "src_operand" "0,rIm,rR,rS<>")
2006 (match_operand:QI 2 "src_operand" "rIm,0,JR,rS<>"))
2007 (const_int 0)))
2008 (set (match_operand:QI 0 "ext_reg_operand" "=d,d,d,?d")
2009 (minus:QI (match_dup 1)
2010 (match_dup 2)))]
2011 "valid_operands (MINUS, operands, QImode)"
2012 "@
2013 subi\\t%2,%0
2014 subri\\t%1,%0
2015 subi3\\t%2,%1,%0
2016 subi3\\t%2,%1,%0"
2017 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
2018 ; Default to int16 data attr.
2019
2020 (define_insn "*subqi3_noclobber"
2021 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,c,?c")
2022 (minus:QI (match_operand:QI 1 "src_operand" "0,rIm,rR,rS<>")
2023 (match_operand:QI 2 "src_operand" "rIm,0,JR,rS<>")))]
2024 "valid_operands (MINUS, operands, QImode)"
2025 "@
2026 subi\\t%2,%0
2027 subri\\t%1,%0
2028 subi3\\t%2,%1,%0
2029 subi3\\t%2,%1,%0"
2030 [(set_attr "type" "binary,binary,binary,binary")])
2031 ; Default to int16 data attr.
2032
2033 (define_insn "*subqi3_carry_clobber"
2034 [(set (match_operand:QI 0 "reg_operand" "=d,d,d,?d,c,c,c,?c")
2035 (minus:QI (match_operand:QI 1 "src_operand" "0,rIm,rR,rS<>,0,rIm,rR,rS<>")
2036 (match_operand:QI 2 "src_operand" "rIm,0,JR,rS<>,rIm,0,JR,rS<>")))
2037 (use (reg:CC_NOOV 21))
2038 (clobber (reg:CC_NOOV 21))]
2039 "valid_operands (MINUS, operands, QImode)"
2040 "@
2041 subb\\t%2,%0
2042 subrb\\t%1,%0
2043 subb3\\t%2,%1,%0
2044 subb3\\t%2,%1,%0
2045 subb\\t%2,%0
2046 subrb\\t%1,%0
2047 subb3\\t%2,%1,%0
2048 subb3\\t%2,%1,%0"
2049 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc,binary,binary,binary,binary")])
2050 ; Default to int16 data attr.
2051
2052 (define_insn "*subqi3_carry_set"
2053 [(set (reg:CC_NOOV 21)
2054 (compare:CC_NOOV (minus:QI (match_operand:QI 1 "src_operand" "0,rIm,rR,rS<>")
2055 (match_operand:QI 2 "src_operand" "rIm,0,JR,rS<>"))
2056 (const_int 0)))
2057 (set (match_operand:QI 0 "ext_reg_operand" "=d,d,d,?d")
2058 (minus:QI (match_dup 1)
2059 (match_dup 2)))
2060 (use (reg:CC_NOOV 21))]
2061 "valid_operands (MINUS, operands, QImode)"
2062 "@
2063 subb\\t%2,%0
2064 subrb\\t%1,%0
2065 subb3\\t%2,%1,%0
2066 subb3\\t%2,%1,%0"
2067 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
2068 ; Default to int16 data attr.
2069
2070 ;
2071 ; MPYI
2072 ;
2073 (define_expand "mulqi3"
2074 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2075 (mult:QI (match_operand:QI 1 "src_operand" "")
2076 (match_operand:QI 2 "src_operand" "")))
2077 (clobber (reg:CC_NOOV 21))])]
2078 ""
2079 "if (TARGET_MPYI || (GET_CODE (operands[2]) == CONST_INT
2080 && exact_log2 (INTVAL (operands[2])) >= 0))
2081 legitimize_operands (MULT, operands, QImode);
2082 else
2083 {
2084 if (GET_CODE (operands[2]) == CONST_INT)
2085 {
2086 /* Let GCC try to synthesize the multiplication using shifts
2087 and adds. In most cases this will be more profitable than
2088 using the C3x MPYI. */
2089 FAIL;
2090 }
2091 if (operands[1] == operands[2])
2092 {
2093 /* Do the squaring operation in-line. */
2094 emit_insn (gen_sqrqi2_inline (operands[0], operands[1]));
2095 DONE;
2096 }
2097 if (TARGET_INLINE)
2098 {
2099 emit_insn (gen_mulqi3_inline (operands[0], operands[1],
2100 operands[2]));
2101 DONE;
2102 }
2103 c4x_emit_libcall3 (smul_optab->handlers[(int) QImode].libfunc,
2104 MULT, QImode, operands);
2105 DONE;
2106 }
2107 ")
2108
2109 (define_insn "*mulqi3_clobber"
2110 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
2111 (mult:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>,0,rR,rS<>")
2112 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>,rIm,JR,rS<>")))
2113 (clobber (reg:CC_NOOV 21))]
2114 "valid_operands (MULT, operands, QImode)"
2115 "*
2116 if (which_alternative == 0 || which_alternative == 3)
2117 {
2118 if (TARGET_C3X
2119 && GET_CODE (operands[2]) == CONST_INT
2120 && exact_log2 (INTVAL (operands[2])) >= 0)
2121 return \"ash\\t%L2,%0\";
2122 else
2123 return \"mpyi\\t%2,%0\";
2124 }
2125 else
2126 return \"mpyi3\\t%2,%1,%0\";"
2127 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
2128 ; Default to int16 data attr.
2129
2130 (define_insn "*mulqi3_test"
2131 [(set (reg:CC_NOOV 21)
2132 (compare:CC_NOOV (mult:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
2133 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>"))
2134 (const_int 0)))
2135 (clobber (match_scratch:QI 0 "=d,d,d"))]
2136 "valid_operands (MULT, operands, QImode)"
2137 "*
2138 if (which_alternative == 0)
2139 {
2140 if (TARGET_C3X
2141 && GET_CODE (operands[2]) == CONST_INT
2142 && exact_log2 (INTVAL (operands[2])) >= 0)
2143 return \"ash\\t%L2,%0\";
2144 else
2145 return \"mpyi\\t%2,%0\";
2146 }
2147 else
2148 return \"mpyi3\\t%2,%1,%0\";"
2149 [(set_attr "type" "binarycc,binarycc,binarycc")])
2150 ; Default to int16 data attr.
2151
2152 (define_insn "*mulqi3_set"
2153 [(set (reg:CC_NOOV 21)
2154 (compare:CC_NOOV (mult:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
2155 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>"))
2156 (const_int 0)))
2157 (set (match_operand:QI 0 "ext_reg_operand" "=d,d,d")
2158 (mult:QI (match_dup 1)
2159 (match_dup 2)))]
2160 "valid_operands (MULT, operands, QImode)"
2161 "*
2162 if (which_alternative == 0)
2163 {
2164 if (TARGET_C3X
2165 && GET_CODE (operands[2]) == CONST_INT
2166 && exact_log2 (INTVAL (operands[2])) >= 0)
2167 return \"ash\\t%L2,%0\";
2168 else
2169 return \"mpyi\\t%2,%0\";
2170 }
2171 else
2172 return \"mpyi3\\t%2,%1,%0\";"
2173 [(set_attr "type" "binarycc,binarycc,binarycc")])
2174 ; Default to int16 data attr.
2175
2176 ; The C3x multiply instruction assumes 24-bit signed integer operands
2177 ; and the 48-bit result is truncated to 32-bits.
2178 (define_insn "mulqi3_24_clobber"
2179 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
2180 (mult:QI
2181 (sign_extend:QI
2182 (and:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>,0,rR,rS<>")
2183 (const_int 16777215)))
2184 (sign_extend:QI
2185 (and:QI (match_operand:QI 2 "src_operand" "rIm,JR,rS<>,rIm,JR,rS<>")
2186 (const_int 16777215)))))
2187 (clobber (reg:CC_NOOV 21))]
2188 "TARGET_C3X && valid_operands (MULT, operands, QImode)"
2189 "@
2190 mpyi\\t%2,%0
2191 mpyi3\\t%2,%1,%0
2192 mpyi3\\t%2,%1,%0
2193 mpyi\\t%2,%0
2194 mpyi3\\t%2,%1,%0
2195 mpyi3\\t%2,%1,%0"
2196 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
2197 ; Default to int16 data attr.
2198
2199
2200 ; Fast square function for C3x where TARGET_MPYI not asserted
2201 (define_expand "sqrqi2_inline"
2202 [(set (match_dup 7) (match_operand:QI 1 "src_operand" ""))
2203 (parallel [(set (match_dup 3)
2204 (lshiftrt:QI (match_dup 7) (const_int 16)))
2205 (clobber (reg:CC 21))])
2206 (parallel [(set (match_dup 2)
2207 (and:QI (match_dup 7) (const_int 65535)))
2208 (clobber (reg:CC 21))])
2209 (parallel [(set (match_dup 4)
2210 (mult:QI (sign_extend:QI (and:QI (match_dup 2)
2211 (const_int 16777215)))
2212 (sign_extend:QI (and:QI (match_dup 2)
2213 (const_int 16777215)))))
2214 (clobber (reg:CC_NOOV 21))])
2215 (parallel [(set (match_dup 5)
2216 (mult:QI (sign_extend:QI (and:QI (match_dup 2)
2217 (const_int 16777215)))
2218 (sign_extend:QI (and:QI (match_dup 3)
2219 (const_int 16777215)))))
2220 (clobber (reg:CC_NOOV 21))])
2221 (parallel [(set (match_dup 6)
2222 (ashift:QI (match_dup 5) (const_int 17)))
2223 (clobber (reg:CC 21))])
2224 (parallel [(set (match_operand:QI 0 "reg_operand" "")
2225 (plus:QI (match_dup 4) (match_dup 6)))
2226 (clobber (reg:CC_NOOV 21))])]
2227 ""
2228 "
2229 operands[2] = gen_reg_rtx (QImode); /* a = val & 0xffff */
2230 operands[3] = gen_reg_rtx (QImode); /* b = val >> 16 */
2231 operands[4] = gen_reg_rtx (QImode); /* a * a */
2232 operands[5] = gen_reg_rtx (QImode); /* a * b */
2233 operands[6] = gen_reg_rtx (QImode); /* (a * b) << 17 */
2234 operands[7] = gen_reg_rtx (QImode); /* val */
2235 ")
2236
2237 ; Inlined integer multiply for C3x
2238 (define_expand "mulqi3_inline"
2239 [(set (match_dup 12) (const_int -16))
2240 (set (match_dup 13) (match_operand:QI 1 "src_operand" ""))
2241 (set (match_dup 14) (match_operand:QI 2 "src_operand" ""))
2242 (parallel [(set (match_dup 4)
2243 (lshiftrt:QI (match_dup 13) (neg:QI (match_dup 12))))
2244 (clobber (reg:CC 21))])
2245 (parallel [(set (match_dup 6)
2246 (lshiftrt:QI (match_dup 14) (neg:QI (match_dup 12))))
2247 (clobber (reg:CC 21))])
2248 (parallel [(set (match_dup 3)
2249 (and:QI (match_dup 13)
2250 (const_int 65535)))
2251 (clobber (reg:CC 21))])
2252 (parallel [(set (match_dup 5)
2253 (and:QI (match_dup 14)
2254 (const_int 65535)))
2255 (clobber (reg:CC 21))])
2256 (parallel [(set (match_dup 7)
2257 (mult:QI (sign_extend:QI (and:QI (match_dup 4)
2258 (const_int 16777215)))
2259 (sign_extend:QI (and:QI (match_dup 5)
2260 (const_int 16777215)))))
2261 (clobber (reg:CC_NOOV 21))])
2262 (parallel [(set (match_dup 8)
2263 (mult:QI (sign_extend:QI (and:QI (match_dup 3)
2264 (const_int 16777215)))
2265 (sign_extend:QI (and:QI (match_dup 5)
2266 (const_int 16777215)))))
2267 (clobber (reg:CC_NOOV 21))])
2268 (parallel [(set (match_dup 9)
2269 (mult:QI (sign_extend:QI (and:QI (match_dup 3)
2270 (const_int 16777215)))
2271 (sign_extend:QI (and:QI (match_dup 6)
2272 (const_int 16777215)))))
2273 (clobber (reg:CC_NOOV 21))])
2274 (parallel [(set (match_dup 10)
2275 (plus:QI (match_dup 7) (match_dup 9)))
2276 (clobber (reg:CC_NOOV 21))])
2277 (parallel [(set (match_dup 11)
2278 (ashift:QI (match_dup 10) (const_int 16)))
2279 (clobber (reg:CC 21))])
2280 (parallel [(set (match_operand:QI 0 "reg_operand" "")
2281 (plus:QI (match_dup 8) (match_dup 11)))
2282 (clobber (reg:CC_NOOV 21))])]
2283 "TARGET_C3X"
2284 "
2285 operands[3] = gen_reg_rtx (QImode); /* a = arg1 & 0xffff */
2286 operands[4] = gen_reg_rtx (QImode); /* b = arg1 >> 16 */
2287 operands[5] = gen_reg_rtx (QImode); /* a = arg2 & 0xffff */
2288 operands[6] = gen_reg_rtx (QImode); /* b = arg2 >> 16 */
2289 operands[7] = gen_reg_rtx (QImode); /* b * c */
2290 operands[8] = gen_reg_rtx (QImode); /* a * c */
2291 operands[9] = gen_reg_rtx (QImode); /* a * d */
2292 operands[10] = gen_reg_rtx (QImode); /* b * c + a * d */
2293 operands[11] = gen_reg_rtx (QImode); /* (b *c + a * d) << 16 */
2294 operands[12] = gen_reg_rtx (QImode); /* -16 */
2295 operands[13] = gen_reg_rtx (QImode); /* arg1 */
2296 operands[14] = gen_reg_rtx (QImode); /* arg2 */
2297 ")
2298
2299 ;
2300 ; MPYSHI (C4x only)
2301 ;
2302 (define_expand "smulqi3_highpart"
2303 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2304 (truncate:QI
2305 (lshiftrt:HI
2306 (mult:HI
2307 (sign_extend:HI (match_operand:QI 1 "src_operand" ""))
2308 (sign_extend:HI (match_operand:QI 2 "src_operand" "")))
2309 (const_int 32))))
2310 (clobber (reg:CC_NOOV 21))])]
2311 ""
2312 "legitimize_operands (MULT, operands, QImode);
2313 if (TARGET_C3X)
2314 {
2315 c4x_emit_libcall_mulhi (smulhi3_libfunc, SIGN_EXTEND, QImode, operands);
2316 DONE;
2317 }
2318 ")
2319
2320 (define_insn "*smulqi3_highpart_clobber"
2321 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
2322 (truncate:QI
2323 (lshiftrt:HI
2324 (mult:HI
2325 (sign_extend:HI (match_operand:QI 1 "src_operand" "%0,rR,rS<>,0,rR,rS<>"))
2326 (sign_extend:HI (match_operand:QI 2 "src_operand" "rIm,JR,rS<>,rIm,JR,rS<>")))
2327 (const_int 32))))
2328 (clobber (reg:CC_NOOV 21))]
2329 "! TARGET_C3X && valid_operands (MULT, operands, QImode)"
2330 "@
2331 mpyshi\\t%2,%0
2332 mpyshi3\\t%2,%1,%0
2333 mpyshi3\\t%2,%1,%0
2334 mpyshi\\t%2,%0
2335 mpyshi3\\t%2,%1,%0
2336 mpyshi3\\t%2,%1,%0"
2337 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")
2338 (set_attr "data" "int16,int16,int16,int16,int16,int16")])
2339
2340 (define_insn "*smulqi3_highpart_noclobber"
2341 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,?c")
2342 (truncate:QI
2343 (lshiftrt:HI
2344 (mult:HI
2345 (sign_extend:HI (match_operand:QI 1 "src_operand" "0,rR,rS<>"))
2346 (sign_extend:HI (match_operand:QI 2 "src_operand" "rIm,JR,rS<>")))
2347 (const_int 32))))]
2348 "! TARGET_C3X && valid_operands (MULT, operands, QImode)"
2349 "@
2350 mpyshi\\t%2,%0
2351 mpyshi3\\t%2,%1,%0
2352 mpyshi3\\t%2,%1,%0"
2353 [(set_attr "type" "binary,binary,binary")
2354 (set_attr "data" "int16,int16,int16")])
2355
2356 ;
2357 ; MPYUHI (C4x only)
2358 ;
2359 (define_expand "umulqi3_highpart"
2360 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2361 (truncate:QI
2362 (lshiftrt:HI
2363 (mult:HI
2364 (zero_extend:HI (match_operand:QI 1
2365 "nonimmediate_src_operand" ""))
2366 (zero_extend:HI (match_operand:QI 2
2367 "nonimmediate_lsrc_operand" "")))
2368 (const_int 32))))
2369 (clobber (reg:CC_NOOV 21))])]
2370 ""
2371 "legitimize_operands (MULT, operands, QImode);
2372 if (TARGET_C3X)
2373 {
2374 c4x_emit_libcall_mulhi (umulhi3_libfunc, ZERO_EXTEND, QImode, operands);
2375 DONE;
2376 }
2377 ")
2378
2379 (define_insn "*umulqi3_highpart_clobber"
2380 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
2381 (truncate:QI
2382 (lshiftrt:HI
2383 (mult:HI
2384 (zero_extend:HI (match_operand:QI 1
2385 "nonimmediate_src_operand" "%0,rR,rS<>,0,rR,rS<>"))
2386 (zero_extend:HI (match_operand:QI 2
2387 "nonimmediate_lsrc_operand" "rm,R,rS<>,rm,R,rS<>")))
2388 (const_int 32))))
2389 (clobber (reg:CC_NOOV 21))]
2390 "! TARGET_C3X && valid_operands (MULT, operands, QImode)"
2391 "@
2392 mpyuhi\\t%2,%0
2393 mpyuhi3\\t%2,%1,%0
2394 mpyuhi3\\t%2,%1,%0
2395 mpyuhi\\t%2,%0
2396 mpyuhi3\\t%2,%1,%0
2397 mpyuhi3\\t%2,%1,%0"
2398 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")
2399 (set_attr "data" "uint16,uint16,uint16,uint16,uint16,uint16")])
2400
2401 (define_insn "*umulqi3_highpart_noclobber"
2402 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,?c")
2403 (truncate:QI
2404 (lshiftrt:HI
2405 (mult:HI
2406 (zero_extend:HI (match_operand:QI 1
2407 "nonimmediate_src_operand" "0,rR,rS<>"))
2408 (zero_extend:HI (match_operand:QI 2
2409 "nonimmediate_lsrc_operand" "rm,R,rS<>")))
2410 (const_int 32))))]
2411 "! TARGET_C3X && valid_operands (MULT, operands, QImode)"
2412 "@
2413 mpyuhi\\t%2,%0
2414 mpyuhi3\\t%2,%1,%0
2415 mpyuhi3\\t%2,%1,%0"
2416 [(set_attr "type" "binary,binary,binary")
2417 (set_attr "data" "uint16,uint16,uint16")])
2418
2419 ;
2420 ; AND
2421 ;
2422 (define_expand "andqi3"
2423 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2424 (and:QI (match_operand:QI 1 "src_operand" "")
2425 (match_operand:QI 2 "tsrc_operand" "")))
2426 (clobber (reg:CC 21))])]
2427 ""
2428 "legitimize_operands (AND, operands, QImode);")
2429
2430
2431 (define_insn "*andqi3_255_clobber"
2432 [(set (match_operand:QI 0 "reg_operand" "=d,c")
2433 (and:QI (match_operand:QI 1 "src_operand" "mr,mr")
2434 (const_int 255)))
2435 (clobber (reg:CC 21))]
2436 "! TARGET_C3X"
2437 "lbu0\\t%1,%0"
2438 [(set_attr "type" "unarycc,unary")])
2439
2440 (define_insn "*andqi3_255_noclobber"
2441 [(set (match_operand:QI 0 "reg_operand" "=c")
2442 (and:QI (match_operand:QI 1 "src_operand" "mr")
2443 (const_int 255)))]
2444 "! TARGET_C3X"
2445 "lbu0\\t%1,%0"
2446 [(set_attr "type" "unary")])
2447
2448
2449 (define_insn "*andqi3_65535_clobber"
2450 [(set (match_operand:QI 0 "reg_operand" "=d,c")
2451 (and:QI (match_operand:QI 1 "src_operand" "mr,mr")
2452 (const_int 65535)))
2453 (clobber (reg:CC 21))]
2454 "! TARGET_C3X"
2455 "lhu0\\t%1,%0"
2456 [(set_attr "type" "unarycc,unary")])
2457
2458 (define_insn "*andqi3_65535_noclobber"
2459 [(set (match_operand:QI 0 "reg_operand" "=c")
2460 (and:QI (match_operand:QI 1 "src_operand" "mr")
2461 (const_int 65535)))]
2462 "! TARGET_C3X"
2463 "lhu0\\t%1,%0"
2464 [(set_attr "type" "unary")])
2465
2466 (define_insn "*andqi3_clobber"
2467 [(set (match_operand:QI 0 "reg_operand" "=d,d,d,?d,c,c,c,?c")
2468 (and:QI (match_operand:QI 1 "src_operand" "%0,0,rR,rS<>,0,0,rR,rS<>")
2469 (match_operand:QI 2 "tsrc_operand" "N,rLm,JR,rS<>,N,rLm,JR,rS<>")))
2470 (clobber (reg:CC 21))]
2471 "valid_operands (AND, operands, QImode)"
2472 "@
2473 andn\\t%N2,%0
2474 and\\t%2,%0
2475 and3\\t%2,%1,%0
2476 and3\\t%2,%1,%0
2477 andn\\t%N2,%0
2478 and\\t%2,%0
2479 and3\\t%2,%1,%0
2480 and3\\t%2,%1,%0"
2481 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc,binary,binary,binary,binary")
2482 (set_attr "data" "not_uint16,uint16,int16,uint16,not_uint16,uint16,int16,uint16")])
2483
2484 (define_insn "*andqi3_noclobber"
2485 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,c,?c")
2486 (and:QI (match_operand:QI 1 "src_operand" "%0,0,rR,rS<>")
2487 (match_operand:QI 2 "tsrc_operand" "N,rLm,JR,rS<>")))]
2488 "valid_operands (AND, operands, QImode)"
2489 "@
2490 andn\\t%N2,%0
2491 and\\t%2,%0
2492 and3\\t%2,%1,%0
2493 and3\\t%2,%1,%0"
2494 [(set_attr "type" "binary,binary,binary,binary")
2495 (set_attr "data" "not_uint16,uint16,int16,uint16")])
2496
2497 (define_insn "andn_st"
2498 [(set (unspec:QI [(reg:QI 21)] 20)
2499 (and:QI (unspec:QI [(reg:QI 21)] UNSPEC_ANDN_ST)
2500 (match_operand:QI 0 "" "N")))
2501 (use (match_dup 0))
2502 (use (reg:CC 21))
2503 (clobber (reg:CC 21))]
2504 ""
2505 "andn\\t%N0,st"
2506 [(set_attr "type" "misc")
2507 (set_attr "data" "not_uint16")])
2508
2509 (define_split
2510 [(set (match_operand:QI 0 "std_reg_operand" "")
2511 (and:QI (match_operand:QI 1 "src_operand" "")
2512 (match_operand:QI 2 "tsrc_operand" "")))
2513 (clobber (reg:CC 21))]
2514 "reload_completed"
2515 [(set (match_dup 0)
2516 (and:QI (match_dup 1)
2517 (match_dup 2)))]
2518 "")
2519
2520 (define_insn "*andqi3_test"
2521 [(set (reg:CC 21)
2522 (compare:CC (and:QI (match_operand:QI 1 "src_operand" "%0,r,rR,rS<>")
2523 (match_operand:QI 2 "tsrc_operand" "N,rLm,JR,rS<>"))
2524 (const_int 0)))
2525 (clobber (match_scratch:QI 0 "=d,X,X,?X"))]
2526 "valid_operands (AND, operands, QImode)"
2527 "@
2528 andn\\t%N2,%0
2529 tstb\\t%2,%1
2530 tstb3\\t%2,%1
2531 tstb3\\t%2,%1"
2532 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")
2533 (set_attr "data" "not_uint16,uint16,int16,uint16")])
2534
2535 (define_peephole
2536 [(parallel [(set (match_operand:QI 0 "ext_reg_operand" "=d,d,d,?d")
2537 (and:QI (match_operand:QI 1 "src_operand" "%0,0,rR,rS<>")
2538 (match_operand:QI 2 "tsrc_operand" "N,rLm,JR,rS<>")))
2539 (clobber (reg:CC 21))])
2540 (set (reg:CC 21)
2541 (compare:CC (match_dup 0) (const_int 0)))]
2542 "valid_operands (AND, operands, QImode)"
2543 "@
2544 andn\\t%N2,%0
2545 and\\t%2,%0
2546 and3\\t%2,%1,%0
2547 and3\\t%2,%1,%0"
2548 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")
2549 (set_attr "data" "not_uint16,uint16,int16,uint16")])
2550
2551 (define_insn "*andqi3_set"
2552 [(set (reg:CC 21)
2553 (compare:CC (and:QI (match_operand:QI 1 "src_operand" "%0,0,rR,rS<>")
2554 (match_operand:QI 2 "tsrc_operand" "N,rLm,JR,rS<>"))
2555 (const_int 0)))
2556 (set (match_operand:QI 0 "ext_reg_operand" "=d,d,d,?d")
2557 (and:QI (match_dup 1)
2558 (match_dup 2)))]
2559 "valid_operands (AND, operands, QImode)"
2560 "@
2561 andn\\t%N2,%0
2562 and\\t%2,%0
2563 and3\\t%2,%1,%0
2564 and3\\t%2,%1,%0"
2565 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")
2566 (set_attr "data" "not_uint16,uint16,int16,uint16")])
2567
2568 ;
2569 ; ANDN
2570 ;
2571 ; NB, this insn doesn't have commutative operands, but valid_operands
2572 ; assumes that the code AND does. We might have to kludge this if
2573 ; we make valid_operands stricter.
2574 (define_insn "*andnqi3_clobber"
2575 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
2576 (and:QI (not:QI (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>,rLm,JR,rS<>"))
2577 (match_operand:QI 1 "src_operand" "0,rR,rS<>,0,rR,rS<>")))
2578 (clobber (reg:CC 21))]
2579 "valid_operands (AND, operands, QImode)"
2580 "@
2581 andn\\t%2,%0
2582 andn3\\t%2,%1,%0
2583 andn3\\t%2,%1,%0
2584 andn\\t%2,%0
2585 andn3\\t%2,%1,%0
2586 andn3\\t%2,%1,%0"
2587 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")
2588 (set_attr "data" "uint16,int16,uint16,uint16,int16,uint16")])
2589
2590 (define_insn "*andnqi3_noclobber"
2591 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,?c")
2592 (and:QI (not:QI (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>"))
2593 (match_operand:QI 1 "src_operand" "0,rR,rS<>")))]
2594 "valid_operands (AND, operands, QImode)"
2595 "@
2596 andn\\t%2,%0
2597 andn3\\t%2,%1,%0
2598 andn3\\t%2,%1,%0"
2599 [(set_attr "type" "binary,binary,binary")
2600 (set_attr "data" "uint16,int16,uint16")])
2601
2602 (define_split
2603 [(set (match_operand:QI 0 "std_reg_operand" "")
2604 (and:QI (not:QI (match_operand:QI 2 "lsrc_operand" ""))
2605 (match_operand:QI 1 "src_operand" "")))
2606 (clobber (reg:CC 21))]
2607 "reload_completed"
2608 [(set (match_dup 0)
2609 (and:QI (not:QI (match_dup 2))
2610 (match_dup 1)))]
2611 "")
2612
2613 (define_insn "*andnqi3_test"
2614 [(set (reg:CC 21)
2615 (compare:CC (and:QI (not:QI (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>"))
2616 (match_operand:QI 1 "src_operand" "0,rR,rS<>"))
2617 (const_int 0)))
2618 (clobber (match_scratch:QI 0 "=d,d,d"))]
2619 "valid_operands (AND, operands, QImode)"
2620 "@
2621 andn\\t%2,%0
2622 andn3\\t%2,%1,%0
2623 andn3\\t%2,%1,%0"
2624 [(set_attr "type" "binarycc,binarycc,binarycc")
2625 (set_attr "data" "uint16,int16,uint16")])
2626
2627 (define_insn "*andnqi3_set"
2628 [(set (reg:CC 21)
2629 (compare:CC (and:QI (not:QI (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>"))
2630 (match_operand:QI 1 "src_operand" "0,rR,rS<>"))
2631 (const_int 0)))
2632 (set (match_operand:QI 0 "ext_reg_operand" "=d,d,d")
2633 (and:QI (not:QI (match_dup 2))
2634 (match_dup 1)))]
2635 "valid_operands (AND, operands, QImode)"
2636 "@
2637 andn\\t%2,%0
2638 andn3\\t%2,%1,%0
2639 andn3\\t%2,%1,%0"
2640 [(set_attr "type" "binarycc,binarycc,binarycc")
2641 (set_attr "data" "uint16,int16,uint16")])
2642
2643 ;
2644 ; OR
2645 ;
2646 (define_expand "iorqi3"
2647 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2648 (ior:QI (match_operand:QI 1 "src_operand" "")
2649 (match_operand:QI 2 "lsrc_operand" "")))
2650 (clobber (reg:CC 21))])]
2651 ""
2652 "legitimize_operands (IOR, operands, QImode);")
2653
2654 (define_insn "*iorqi3_clobber"
2655 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
2656 (ior:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>,0,rR,rS<>")
2657 (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>,rLm,JR,rS<>")))
2658 (clobber (reg:CC 21))]
2659 "valid_operands (IOR, operands, QImode)"
2660 "@
2661 or\\t%2,%0
2662 or3\\t%2,%1,%0
2663 or3\\t%2,%1,%0
2664 or\\t%2,%0
2665 or3\\t%2,%1,%0
2666 or3\\t%2,%1,%0"
2667 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")
2668 (set_attr "data" "uint16,int16,uint16,uint16,int16,uint16")])
2669
2670 (define_split
2671 [(set (match_operand:QI 0 "std_reg_operand" "")
2672 (ior:QI (match_operand:QI 1 "src_operand" "")
2673 (match_operand:QI 2 "lsrc_operand" "")))
2674 (clobber (reg:CC 21))]
2675 "reload_completed"
2676 [(set (match_dup 0)
2677 (ior:QI (match_dup 1)
2678 (match_dup 2)))]
2679 "")
2680
2681 (define_insn "*iorqi3_test"
2682 [(set (reg:CC 21)
2683 (compare:CC (ior:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
2684 (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>"))
2685 (const_int 0)))
2686 (clobber (match_scratch:QI 0 "=d,d,d"))]
2687 "valid_operands (IOR, operands, QImode)"
2688 "@
2689 or\\t%2,%0
2690 or3\\t%2,%1,%0
2691 or3\\t%2,%1,%0"
2692 [(set_attr "type" "binarycc,binarycc,binarycc")
2693 (set_attr "data" "uint16,int16,uint16")])
2694
2695 (define_peephole
2696 [(parallel [(set (match_operand:QI 0 "ext_reg_operand" "=d,d,d")
2697 (ior:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
2698 (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>")))
2699 (clobber (reg:CC 21))])
2700 (set (reg:CC 21)
2701 (compare:CC (match_dup 0) (const_int 0)))]
2702 "valid_operands (IOR, operands, QImode)"
2703 "@
2704 or\\t%2,%0
2705 or3\\t%2,%1,%0
2706 or3\\t%2,%1,%0"
2707 [(set_attr "type" "binarycc,binarycc,binarycc")
2708 (set_attr "data" "uint16,int16,uint16")])
2709
2710 (define_insn "*iorqi3_set"
2711 [(set (reg:CC 21)
2712 (compare:CC (ior:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
2713 (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>"))
2714 (const_int 0)))
2715 (set (match_operand:QI 0 "ext_reg_operand" "=d,d,d")
2716 (ior:QI (match_dup 1)
2717 (match_dup 2)))]
2718 "valid_operands (IOR, operands, QImode)"
2719 "@
2720 or\\t%2,%0
2721 or3\\t%2,%1,%0
2722 or3\\t%2,%1,%0"
2723 [(set_attr "type" "binarycc,binarycc,binarycc")
2724 (set_attr "data" "uint16,int16,uint16")])
2725
2726 ; This pattern is used for loading symbol references in several parts.
2727 (define_insn "iorqi3_noclobber"
2728 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,c")
2729 (ior:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
2730 (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>")))]
2731 "valid_operands (IOR, operands, QImode)"
2732 "@
2733 or\\t%2,%0
2734 or3\\t%2,%1,%0
2735 or3\\t%2,%1,%0"
2736 [(set_attr "type" "binary,binary,binary")
2737 (set_attr "data" "uint16,int16,uint16")])
2738
2739 ;
2740 ; XOR
2741 ;
2742 (define_expand "xorqi3"
2743 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2744 (xor:QI (match_operand:QI 1 "src_operand" "")
2745 (match_operand:QI 2 "lsrc_operand" "")))
2746 (clobber (reg:CC 21))])]
2747 ""
2748 "legitimize_operands (XOR, operands, QImode);")
2749
2750 (define_insn "*xorqi3_clobber"
2751 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
2752 (xor:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>,0,rR,rS<>")
2753 (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>,rLm,JR,rS<>")))
2754 (clobber (reg:CC 21))]
2755 "valid_operands (XOR, operands, QImode)"
2756 "@
2757 xor\\t%2,%0
2758 xor3\\t%2,%1,%0
2759 xor3\\t%2,%1,%0
2760 xor\\t%2,%0
2761 xor3\\t%2,%1,%0
2762 xor3\\t%2,%1,%0"
2763 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")
2764 (set_attr "data" "uint16,int16,uint16,uint16,int16,uint16")])
2765
2766 (define_insn "*xorqi3_noclobber"
2767 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,?c")
2768 (xor:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
2769 (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>")))]
2770 "valid_operands (XOR, operands, QImode)"
2771 "@
2772 xor\\t%2,%0
2773 xor3\\t%2,%1,%0
2774 xor3\\t%2,%1,%0"
2775 [(set_attr "type" "binary,binary,binary")
2776 (set_attr "data" "uint16,int16,uint16")])
2777
2778 (define_split
2779 [(set (match_operand:QI 0 "std_reg_operand" "")
2780 (xor:QI (match_operand:QI 1 "src_operand" "")
2781 (match_operand:QI 2 "lsrc_operand" "")))
2782 (clobber (reg:CC 21))]
2783 "reload_completed"
2784 [(set (match_dup 0)
2785 (xor:QI (match_dup 1)
2786 (match_dup 2)))]
2787 "")
2788
2789 (define_insn "*xorqi3_test"
2790 [(set (reg:CC 21)
2791 (compare:CC (xor:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
2792 (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>"))
2793 (const_int 0)))
2794 (clobber (match_scratch:QI 0 "=d,d,d"))]
2795 "valid_operands (XOR, operands, QImode)"
2796 "@
2797 xor\\t%2,%0
2798 xor3\\t%2,%1,%0
2799 xor3\\t%2,%1,%0"
2800 [(set_attr "type" "binarycc,binarycc,binarycc")
2801 (set_attr "data" "uint16,int16,uint16")])
2802
2803 (define_insn "*xorqi3_set"
2804 [(set (reg:CC 21)
2805 (compare:CC (xor:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
2806 (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>"))
2807 (const_int 0)))
2808 (set (match_operand:QI 0 "ext_reg_operand" "=d,d,d")
2809 (xor:QI (match_dup 1)
2810 (match_dup 2)))]
2811 "valid_operands (XOR, operands, QImode)"
2812 "@
2813 xor\\t%2,%0
2814 xor3\\t%2,%1,%0
2815 xor3\\t%2,%1,%0"
2816 [(set_attr "type" "binarycc,binarycc,binarycc")
2817 (set_attr "data" "uint16,int16,uint16")])
2818
2819 ;
2820 ; LSH/ASH (left)
2821 ;
2822 ; The C3x and C4x have two shift instructions ASH and LSH
2823 ; If the shift count is positive, a left shift is performed
2824 ; otherwise a right shift is performed. The number of bits
2825 ; shifted is determined by the seven LSBs of the shift count.
2826 ; If the absolute value of the count is 32 or greater, the result
2827 ; using the LSH instruction is zero; with the ASH insn the result
2828 ; is zero or negative 1. Note that the ISO C standard allows
2829 ; the result to be machine dependent whenever the shift count
2830 ; exceeds the size of the object.
2831 (define_expand "ashlqi3"
2832 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2833 (ashift:QI (match_operand:QI 1 "src_operand" "")
2834 (match_operand:QI 2 "src_operand" "")))
2835 (clobber (reg:CC 21))])]
2836 ""
2837 "legitimize_operands (ASHIFT, operands, QImode);")
2838
2839 (define_insn "*ashlqi3_clobber"
2840 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
2841 (ashift:QI (match_operand:QI 1 "src_operand" "0,rR,rS<>,0,rR,rS<>")
2842 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>,rIm,JR,rS<>")))
2843 (clobber (reg:CC 21))]
2844 "valid_operands (ASHIFT, operands, QImode)"
2845 "@
2846 ash\\t%2,%0
2847 ash3\\t%2,%1,%0
2848 ash3\\t%2,%1,%0
2849 ash\\t%2,%0
2850 ash3\\t%2,%1,%0
2851 ash3\\t%2,%1,%0"
2852 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
2853 ; Default to int16 data attr.
2854
2855 (define_insn "*ashlqi3_set"
2856 [(set (reg:CC 21)
2857 (compare:CC
2858 (ashift:QI (match_operand:QI 1 "src_operand" "0,rR,rS<>")
2859 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>"))
2860 (const_int 0)))
2861 (set (match_operand:QI 0 "reg_operand" "=d,d,d")
2862 (ashift:QI (match_dup 1)
2863 (match_dup 2)))]
2864 "valid_operands (ASHIFT, operands, QImode)"
2865 "@
2866 ash\\t%2,%0
2867 ash3\\t%2,%1,%0
2868 ash3\\t%2,%1,%0"
2869 [(set_attr "type" "binarycc,binarycc,binarycc")])
2870 ; Default to int16 data attr.
2871
2872 (define_insn "ashlqi3_noclobber"
2873 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,?c")
2874 (ashift:QI (match_operand:QI 1 "src_operand" "0,rR,rS<>")
2875 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>")))]
2876 "valid_operands (ASHIFT, operands, QImode)"
2877 "@
2878 ash\\t%2,%0
2879 ash3\\t%2,%1,%0
2880 ash3\\t%2,%1,%0"
2881 [(set_attr "type" "binary,binary,binary")])
2882 ; Default to int16 data attr.
2883
2884 (define_split
2885 [(set (match_operand:QI 0 "std_reg_operand" "")
2886 (ashift:QI (match_operand:QI 1 "src_operand" "")
2887 (match_operand:QI 2 "src_operand" "")))
2888 (clobber (reg:CC 21))]
2889 "reload_completed"
2890 [(set (match_dup 0)
2891 (ashift:QI (match_dup 1)
2892 (match_dup 2)))]
2893 "")
2894
2895 ; This is only used by lshrhi3_reg where we need a LSH insn that will
2896 ; shift both ways.
2897 (define_insn "*lshlqi3_clobber"
2898 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
2899 (ashift:QI (match_operand:QI 1 "src_operand" "0,rR,rS<>,0,rR,rS<>")
2900 (unspec:QI [(match_operand:QI 2 "src_operand" "rIm,JR,rS<>,rIm,JR,rS<>")] UNSPEC_LSH)))
2901 (clobber (reg:CC 21))]
2902 "valid_operands (ASHIFT, operands, QImode)"
2903 "@
2904 lsh\\t%2,%0
2905 lsh3\\t%2,%1,%0
2906 lsh3\\t%2,%1,%0
2907 lsh\\t%2,%0
2908 lsh3\\t%2,%1,%0
2909 lsh3\\t%2,%1,%0"
2910 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
2911 ; Default to int16 data attr.
2912
2913 ;
2914 ; LSH (right)
2915 ;
2916 ; Logical right shift on the C[34]x works by negating the shift count,
2917 ; then emitting a right shift with the shift count negated. This means
2918 ; that all actual shift counts in the RTL will be positive.
2919 ;
2920 (define_expand "lshrqi3"
2921 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2922 (lshiftrt:QI (match_operand:QI 1 "src_operand" "")
2923 (match_operand:QI 2 "src_operand" "")))
2924 (clobber (reg:CC 21))])]
2925 ""
2926 "legitimize_operands (LSHIFTRT, operands, QImode);")
2927
2928
2929 (define_insn "*lshrqi3_24_clobber"
2930 [(set (match_operand:QI 0 "reg_operand" "=d,c")
2931 (lshiftrt:QI (match_operand:QI 1 "src_operand" "mr,mr")
2932 (const_int 24)))
2933 (clobber (reg:CC 21))]
2934 "! TARGET_C3X"
2935 "lbu3\\t%1,%0"
2936 [(set_attr "type" "unarycc")])
2937
2938
2939 (define_insn "*ashrqi3_24_clobber"
2940 [(set (match_operand:QI 0 "reg_operand" "=d,c")
2941 (ashiftrt:QI (match_operand:QI 1 "src_operand" "mr,mr")
2942 (const_int 24)))
2943 (clobber (reg:CC 21))]
2944 "! TARGET_C3X"
2945 "lb3\\t%1,%0"
2946 [(set_attr "type" "unarycc")])
2947
2948
2949 (define_insn "lshrqi3_16_clobber"
2950 [(set (match_operand:QI 0 "reg_operand" "=d,c")
2951 (lshiftrt:QI (match_operand:QI 1 "src_operand" "mr,mr")
2952 (const_int 16)))
2953 (clobber (reg:CC 21))]
2954 "! TARGET_C3X"
2955 "lhu1\\t%1,%0"
2956 [(set_attr "type" "unarycc")])
2957
2958
2959 (define_insn "*ashrqi3_16_clobber"
2960 [(set (match_operand:QI 0 "reg_operand" "=d,c")
2961 (ashiftrt:QI (match_operand:QI 1 "src_operand" "mr,mr")
2962 (const_int 16)))
2963 (clobber (reg:CC 21))]
2964 "! TARGET_C3X"
2965 "lh1\\t%1,%0"
2966 [(set_attr "type" "unarycc")])
2967
2968
2969 ; When the shift count is greater than the size of the word
2970 ; the result can be implementation specific
2971 (define_insn "*lshrqi3_const_clobber"
2972 [(set (match_operand:QI 0 "reg_operand" "=d,c,?d,?c")
2973 (lshiftrt:QI (match_operand:QI 1 "src_operand" "0,0,r,r")
2974 (match_operand:QI 2 "const_int_operand" "n,n,J,J")))
2975 (clobber (reg:CC 21))]
2976 "valid_operands (LSHIFTRT, operands, QImode)"
2977 "@
2978 lsh\\t%n2,%0
2979 lsh\\t%n2,%0
2980 lsh3\\t%n2,%1,%0
2981 lsh3\\t%n2,%1,%0"
2982 [(set_attr "type" "binarycc,binary,binarycc,binary")])
2983
2984 (define_insn "*lshrqi3_const_noclobber"
2985 [(set (match_operand:QI 0 "std_reg_operand" "=c,?c")
2986 (lshiftrt:QI (match_operand:QI 1 "src_operand" "0,r")
2987 (match_operand:QI 2 "const_int_operand" "n,J")))]
2988 "valid_operands (LSHIFTRT, operands, QImode)"
2989 "@
2990 lsh\\t%n2,%0
2991 lsh3\\t%n2,%1,%0"
2992 [(set_attr "type" "binary,binary")])
2993
2994 ; When the shift count is greater than the size of the word
2995 ; the result can be implementation specific
2996 (define_insn "*lshrqi3_const_set"
2997 [(set (reg:CC 21)
2998 (compare:CC
2999 (lshiftrt:QI (match_operand:QI 1 "src_operand" "0,r")
3000 (match_operand:QI 2 "const_int_operand" "n,J"))
3001 (const_int 0)))
3002 (set (match_operand:QI 0 "reg_operand" "=?d,d")
3003 (lshiftrt:QI (match_dup 1)
3004 (match_dup 2)))]
3005 "valid_operands (LSHIFTRT, operands, QImode)"
3006 "@
3007 lsh\\t%n2,%0
3008 lsh3\\t%n2,%1,%0"
3009 [(set_attr "type" "binarycc,binarycc")])
3010
3011 (define_insn "*lshrqi3_nonconst_clobber"
3012 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
3013 (lshiftrt:QI (match_operand:QI 1 "src_operand" "0,rR,rS<>,0,rR,rS<>")
3014 (neg:QI (match_operand:QI 2 "src_operand" "rm,R,rS<>,rm,R,rS<>"))))
3015 (clobber (reg:CC 21))]
3016 "valid_operands (LSHIFTRT, operands, QImode)"
3017 "@
3018 lsh\\t%2,%0
3019 lsh3\\t%2,%1,%0
3020 lsh3\\t%2,%1,%0
3021 lsh\\t%2,%0
3022 lsh3\\t%2,%1,%0
3023 lsh3\\t%2,%1,%0"
3024 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
3025 ; Default to int16 data attr.
3026
3027 (define_insn "*lshrqi3_nonconst_noclobber"
3028 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,?c")
3029 (lshiftrt:QI (match_operand:QI 1 "src_operand" "0,rR,rS<>")
3030 (neg:QI (match_operand:QI 2 "src_operand" "rm,R,rS<>"))))]
3031 "valid_operands (LSHIFTRT, operands, QImode)"
3032 "@
3033 lsh\\t%2,%0
3034 lsh3\\t%2,%1,%0
3035 lsh3\\t%2,%1,%0"
3036 [(set_attr "type" "binary,binary,binary")])
3037 ; Default to int16 data attr.
3038
3039 ;
3040 ; ASH (right)
3041 ;
3042 ; Arithmetic right shift on the C[34]x works by negating the shift count,
3043 ; then emitting a right shift with the shift count negated. This means
3044 ; that all actual shift counts in the RTL will be positive.
3045
3046 (define_expand "ashrqi3"
3047 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
3048 (ashiftrt:QI (match_operand:QI 1 "src_operand" "")
3049 (match_operand:QI 2 "src_operand" "")))
3050 (clobber (reg:CC 21))])]
3051 ""
3052 "legitimize_operands (ASHIFTRT, operands, QImode);")
3053
3054 ; When the shift count is greater than the size of the word
3055 ; the result can be implementation specific
3056 (define_insn "*ashrqi3_const_clobber"
3057 [(set (match_operand:QI 0 "reg_operand" "=d,c,?d,?c")
3058 (ashiftrt:QI (match_operand:QI 1 "src_operand" "0,0,r,r")
3059 (match_operand:QI 2 "const_int_operand" "n,n,J,J")))
3060 (clobber (reg:CC 21))]
3061 "valid_operands (ASHIFTRT, operands, QImode)"
3062 "@
3063 ash\\t%n2,%0
3064 ash\\t%n2,%0
3065 ash3\\t%n2,%1,%0
3066 ash3\\t%n2,%1,%0"
3067 [(set_attr "type" "binarycc,binary,binarycc,binary")])
3068
3069 (define_insn "*ashrqi3_const_noclobber"
3070 [(set (match_operand:QI 0 "std_reg_operand" "=c,?c")
3071 (ashiftrt:QI (match_operand:QI 1 "src_operand" "0,r")
3072 (match_operand:QI 2 "const_int_operand" "n,J")))]
3073 "valid_operands (ASHIFTRT, operands, QImode)"
3074 "@
3075 ash\\t%n2,%0
3076 ash3\\t%n2,%1,%0"
3077 [(set_attr "type" "binarycc,binarycc")])
3078
3079 ; When the shift count is greater than the size of the word
3080 ; the result can be implementation specific
3081 (define_insn "*ashrqi3_const_set"
3082 [(set (reg:CC 21)
3083 (compare:CC
3084 (ashiftrt:QI (match_operand:QI 1 "src_operand" "0,r")
3085 (match_operand:QI 2 "const_int_operand" "n,J"))
3086 (const_int 0)))
3087 (set (match_operand:QI 0 "reg_operand" "=?d,d")
3088 (ashiftrt:QI (match_dup 1)
3089 (match_dup 2)))]
3090 "valid_operands (ASHIFTRT, operands, QImode)"
3091 "@
3092 ash\\t%n2,%0
3093 ash3\\t%n2,%1,%0"
3094 [(set_attr "type" "binarycc,binarycc")])
3095
3096 (define_insn "*ashrqi3_nonconst_clobber"
3097 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
3098 (ashiftrt:QI (match_operand:QI 1 "src_operand" "0,rR,rS<>,0,rR,rS<>")
3099 (neg:QI (match_operand:QI 2 "src_operand" "rm,R,rS<>,rm,R,rS<>"))))
3100 (clobber (reg:CC 21))]
3101 "valid_operands (ASHIFTRT, operands, QImode)"
3102 "@
3103 ash\\t%2,%0
3104 ash3\\t%2,%1,%0
3105 ash3\\t%2,%1,%0
3106 ash\\t%2,%0
3107 ash3\\t%2,%1,%0
3108 ash3\\t%2,%1,%0"
3109 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
3110 ; Default to int16 data attr.
3111
3112 (define_insn "*ashrqi3_nonconst_noclobber"
3113 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,?c")
3114 (ashiftrt:QI (match_operand:QI 1 "src_operand" "0,rR,rS<>")
3115 (neg:QI (match_operand:QI 2 "src_operand" "rm,R,rS<>"))))]
3116 "valid_operands (ASHIFTRT, operands, QImode)"
3117 "@
3118 ash\\t%2,%0
3119 ash3\\t%2,%1,%0
3120 ash3\\t%2,%1,%0"
3121 [(set_attr "type" "binary,binary,binary")])
3122 ; Default to int16 data attr.
3123
3124 ;
3125 ; CMPI
3126 ;
3127 ; Unfortunately the C40 doesn't allow cmpi3 7, *ar0++ so the next best
3128 ; thing would be to get the small constant loaded into a register (say r0)
3129 ; so that it could be hoisted out of the loop so that we only
3130 ; would need to do cmpi3 *ar0++, r0. Now the loop optimization pass
3131 ; comes before the flow pass (which finds autoincrements) so we're stuck.
3132 ; Ideally, GCC requires another loop optimization pass (preferably after
3133 ; reload) so that it can hoist invariants out of loops.
3134 ; The current solution modifies legitimize_operands () so that small
3135 ; constants are forced into a pseudo register.
3136 ;
3137 (define_expand "cmpqi"
3138 [(set (reg:CC 21)
3139 (compare:CC (match_operand:QI 0 "src_operand" "")
3140 (match_operand:QI 1 "src_operand" "")))]
3141 ""
3142 "legitimize_operands (COMPARE, operands, QImode);
3143 c4x_compare_op0 = operands[0];
3144 c4x_compare_op1 = operands[1];
3145 DONE;")
3146
3147 (define_insn "*cmpqi_test"
3148 [(set (reg:CC 21)
3149 (compare:CC (match_operand:QI 0 "src_operand" "r,rR,rS<>")
3150 (match_operand:QI 1 "src_operand" "rIm,JR,rS<>")))]
3151 "valid_operands (COMPARE, operands, QImode)"
3152 "@
3153 cmpi\\t%1,%0
3154 cmpi3\\t%1,%0
3155 cmpi3\\t%1,%0"
3156 [(set_attr "type" "compare,compare,compare")])
3157
3158 (define_insn "*cmpqi_test_noov"
3159 [(set (reg:CC_NOOV 21)
3160 (compare:CC_NOOV (match_operand:QI 0 "src_operand" "r,rR,rS<>")
3161 (match_operand:QI 1 "src_operand" "rIm,JR,rS<>")))]
3162 "valid_operands (COMPARE, operands, QImode)"
3163 "@
3164 cmpi\\t%1,%0
3165 cmpi3\\t%1,%0
3166 cmpi3\\t%1,%0"
3167 [(set_attr "type" "compare,compare,compare")])
3168
3169
3170 ;
3171 ; BIT-FIELD INSTRUCTIONS
3172 ;
3173
3174 ;
3175 ; LBx/LHw (C4x only)
3176 ;
3177 (define_expand "extv"
3178 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
3179 (sign_extract:QI (match_operand:QI 1 "src_operand" "")
3180 (match_operand:QI 2 "const_int_operand" "")
3181 (match_operand:QI 3 "const_int_operand" "")))
3182 (clobber (reg:CC 21))])]
3183 "! TARGET_C3X"
3184 "if ((INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
3185 || (INTVAL (operands[3]) % INTVAL (operands[2]) != 0))
3186 FAIL;
3187 ")
3188
3189 (define_insn "*extv_clobber"
3190 [(set (match_operand:QI 0 "reg_operand" "=d,c")
3191 (sign_extract:QI (match_operand:QI 1 "src_operand" "rLm,rLm")
3192 (match_operand:QI 2 "const_int_operand" "n,n")
3193 (match_operand:QI 3 "const_int_operand" "n,n")))
3194 (clobber (reg:CC 21))]
3195 "! TARGET_C3X
3196 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
3197 && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
3198 "*
3199 if (INTVAL (operands[2]) == 8)
3200 {
3201 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
3202 return \"lb%3\\t%1,%0\";
3203 }
3204 operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
3205 return \"lh%3\\t%1,%0\";
3206 "
3207 [(set_attr "type" "binarycc,binary")
3208 (set_attr "data" "int16,int16")])
3209
3210 (define_insn "*extv_clobber_test"
3211 [(set (reg:CC 21)
3212 (compare:CC (sign_extract:QI (match_operand:QI 1 "src_operand" "rLm")
3213 (match_operand:QI 2 "const_int_operand" "n")
3214 (match_operand:QI 3 "const_int_operand" "n"))
3215 (const_int 0)))
3216 (clobber (match_scratch:QI 0 "=d"))]
3217 "! TARGET_C3X
3218 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
3219 && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
3220 "*
3221 if (INTVAL (operands[2]) == 8)
3222 {
3223 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
3224 return \"lb%3\\t%1,%0\";
3225 }
3226 operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
3227 return \"lh%3\\t%1,%0\";
3228 "
3229 [(set_attr "type" "binarycc")
3230 (set_attr "data" "int16")])
3231
3232 (define_insn "*extv_clobber_set"
3233 [(set (reg:CC 21)
3234 (compare:CC (sign_extract:QI (match_operand:QI 1 "src_operand" "rLm")
3235 (match_operand:QI 2 "const_int_operand" "n")
3236 (match_operand:QI 3 "const_int_operand" "n"))
3237 (const_int 0)))
3238 (set (match_operand:QI 0 "reg_operand" "=d")
3239 (sign_extract:QI (match_dup 1)
3240 (match_dup 2)
3241 (match_dup 3)))]
3242 "! TARGET_C3X
3243 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
3244 && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
3245 "*
3246 if (INTVAL (operands[2]) == 8)
3247 {
3248 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
3249 return \"lb%3\\t%1,%0\";
3250 }
3251 operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
3252 return \"lh%3\\t%1,%0\";
3253 "
3254 [(set_attr "type" "binarycc")
3255 (set_attr "data" "int16")])
3256
3257 ;
3258 ; LBUx/LHUw (C4x only)
3259 ;
3260 (define_expand "extzv"
3261 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
3262 (zero_extract:QI (match_operand:QI 1 "src_operand" "")
3263 (match_operand:QI 2 "const_int_operand" "")
3264 (match_operand:QI 3 "const_int_operand" "")))
3265 (clobber (reg:CC 21))])]
3266 "! TARGET_C3X"
3267 "if ((INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
3268 || (INTVAL (operands[3]) % INTVAL (operands[2]) != 0))
3269 FAIL;
3270 ")
3271
3272 (define_insn "*extzv_clobber"
3273 [(set (match_operand:QI 0 "reg_operand" "=d,c")
3274 (zero_extract:QI (match_operand:QI 1 "src_operand" "rLm,rLm")
3275 (match_operand:QI 2 "const_int_operand" "n,n")
3276 (match_operand:QI 3 "const_int_operand" "n,n")))
3277 (clobber (reg:CC 21))]
3278 "! TARGET_C3X
3279 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
3280 && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
3281 "*
3282 if (INTVAL (operands[2]) == 8)
3283 {
3284 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
3285 return \"lbu%3\\t%1,%0\";
3286 }
3287 operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
3288 return \"lhu%3\\t%1,%0\";
3289 "
3290 [(set_attr "type" "binarycc,binary")
3291 (set_attr "data" "uint16,uint16")])
3292
3293 (define_insn "*extzv_test"
3294 [(set (reg:CC 21)
3295 (compare:CC (zero_extract:QI (match_operand:QI 1 "src_operand" "rLm")
3296 (match_operand:QI 2 "const_int_operand" "n")
3297 (match_operand:QI 3 "const_int_operand" "n"))
3298 (const_int 0)))
3299 (clobber (match_scratch:QI 0 "=d"))]
3300 "! TARGET_C3X
3301 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
3302 && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
3303 "*
3304 if (INTVAL (operands[2]) == 8)
3305 {
3306 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
3307 return \"lbu%3\\t%1,%0\";
3308 }
3309 operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
3310 return \"lhu%3\\t%1,%0\";
3311 "
3312 [(set_attr "type" "binarycc")
3313 (set_attr "data" "uint16")])
3314
3315 (define_insn "*extzv_set"
3316 [(set (reg:CC 21)
3317 (compare:CC (zero_extract:QI (match_operand:QI 1 "src_operand" "rLm")
3318 (match_operand:QI 2 "const_int_operand" "n")
3319 (match_operand:QI 3 "const_int_operand" "n"))
3320 (const_int 0)))
3321 (set (match_operand:QI 0 "ext_reg_operand" "=d")
3322 (zero_extract:QI (match_dup 1)
3323 (match_dup 2)
3324 (match_dup 3)))]
3325 "! TARGET_C3X
3326 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
3327 && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
3328 "*
3329 if (INTVAL (operands[2]) == 8)
3330 {
3331 /* 8 bit extract. */
3332 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
3333 return \"lbu%3\\t%1,%0\";
3334 }
3335 /* 16 bit extract. */
3336 operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
3337 return \"lhu%3\\t%1,%0\";
3338 "
3339 [(set_attr "type" "binarycc")
3340 (set_attr "data" "uint16")])
3341
3342 ;
3343 ; MBx/MHw (C4x only)
3344 ;
3345 (define_expand "insv"
3346 [(parallel [(set (zero_extract:QI (match_operand:QI 0 "reg_operand" "")
3347 (match_operand:QI 1 "const_int_operand" "")
3348 (match_operand:QI 2 "const_int_operand" ""))
3349 (match_operand:QI 3 "src_operand" ""))
3350 (clobber (reg:CC 21))])]
3351 "! TARGET_C3X"
3352 "if (! (((INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
3353 && (INTVAL (operands[2]) % INTVAL (operands[1]) == 0))
3354 || (INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)))
3355 FAIL;
3356 ")
3357
3358 (define_insn "*insv_clobber"
3359 [(set (zero_extract:QI (match_operand:QI 0 "reg_operand" "+d,c")
3360 (match_operand:QI 1 "const_int_operand" "n,n")
3361 (match_operand:QI 2 "const_int_operand" "n,n"))
3362 (match_operand:QI 3 "src_operand" "rLm,rLm"))
3363 (clobber (reg:CC 21))]
3364 "! TARGET_C3X
3365 && (((INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
3366 && (INTVAL (operands[2]) % INTVAL (operands[1]) == 0))
3367 || (INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8))"
3368 "*
3369 if (INTVAL (operands[1]) == 8)
3370 {
3371 /* 8 bit insert. */
3372 operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
3373 return \"mb%2\\t%3,%0\";
3374 }
3375 else if (INTVAL (operands[1]) == 16)
3376 {
3377 /* 16 bit insert. */
3378 operands[2] = GEN_INT (INTVAL (operands[2]) / 16);
3379 return \"mh%2\\t%3,%0\";
3380 }
3381 /* 24 bit insert. */
3382 return \"lwl1\\t%3,%0\";
3383 "
3384 [(set_attr "type" "binarycc,binary")
3385 (set_attr "data" "uint16,uint16")])
3386
3387 (define_peephole
3388 [(parallel [(set (zero_extract:QI (match_operand:QI 0 "ext_reg_operand" "+d")
3389 (match_operand:QI 1 "const_int_operand" "n")
3390 (match_operand:QI 2 "const_int_operand" "n"))
3391 (match_operand:QI 3 "src_operand" "rLm"))
3392 (clobber (reg:CC 21))])
3393 (set (reg:CC 21)
3394 (compare:CC (match_dup 0) (const_int 0)))]
3395 "! TARGET_C3X
3396 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
3397 && (INTVAL (operands[2]) % INTVAL (operands[1]) == 0)"
3398 "*
3399 if (INTVAL (operands[1]) == 8)
3400 {
3401 operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
3402 return \"mb%2\\t%3,%0\";
3403 }
3404 operands[2] = GEN_INT (INTVAL (operands[2]) / 16);
3405 return \"mh%2\\t%3,%0\";
3406 "
3407 [(set_attr "type" "binarycc")
3408 (set_attr "data" "uint16")])
3409
3410
3411 ; TWO OPERAND FLOAT INSTRUCTIONS
3412 ;
3413
3414 ;
3415 ; LDF/STF
3416 ;
3417 ; If one of the operands is not a register, then we should
3418 ; emit two insns, using a scratch register. This will produce
3419 ; better code in loops if the source operand is invariant, since
3420 ; the source reload can be optimized out. During reload we cannot
3421 ; use change_address or force_reg.
3422 (define_expand "movqf"
3423 [(set (match_operand:QF 0 "src_operand" "")
3424 (match_operand:QF 1 "src_operand" ""))]
3425 ""
3426 "
3427 {
3428 if (c4x_emit_move_sequence (operands, QFmode))
3429 DONE;
3430 }")
3431
3432 ; This can generate invalid stack slot displacements
3433 (define_split
3434 [(set (match_operand:QI 0 "reg_operand" "")
3435 (unspec:QI [(match_operand:QF 1 "reg_operand" "")] UNSPEC_STOREQF_INT))]
3436 "reload_completed"
3437 [(set (match_dup 3) (match_dup 1))
3438 (set (match_dup 0) (match_dup 2))]
3439 "operands[2] = assign_stack_temp (QImode, GET_MODE_SIZE (QImode), 0);
3440 operands[3] = copy_rtx (operands[2]);
3441 PUT_MODE (operands[3], QFmode);")
3442
3443
3444 (define_insn "storeqf_int"
3445 [(set (match_operand:QI 0 "reg_operand" "=r")
3446 (unspec:QI [(match_operand:QF 1 "reg_operand" "f")] UNSPEC_STOREQF_INT))]
3447 ""
3448 "#"
3449 [(set_attr "type" "multi")])
3450
3451 (define_split
3452 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
3453 (unspec:QI [(match_operand:QF 1 "reg_operand" "")] UNSPEC_STOREQF_INT))
3454 (clobber (reg:CC 21))])]
3455 "reload_completed"
3456 [(set (mem:QF (pre_inc:QI (reg:QI 20)))
3457 (match_dup 1))
3458 (parallel [(set (match_dup 0)
3459 (mem:QI (post_dec:QI (reg:QI 20))))
3460 (clobber (reg:CC 21))])]
3461 "")
3462
3463
3464 ; We need accurate death notes for this...
3465 ;(define_peephole
3466 ; [(set (match_operand:QF 0 "reg_operand" "=f")
3467 ; (match_operand:QF 1 "memory_operand" "m"))
3468 ; (set (mem:QF (pre_inc:QI (reg:QI 20)))
3469 ; (match_dup 0))
3470 ; (parallel [(set (match_operand:QI 2 "reg_operand" "r")
3471 ; (mem:QI (post_dec:QI (reg:QI 20))))
3472 ; (clobber (reg:CC 21))])]
3473 ; ""
3474 ; "ldiu\\t%1,%0")
3475
3476 (define_insn "storeqf_int_clobber"
3477 [(parallel [(set (match_operand:QI 0 "reg_operand" "=r")
3478 (unspec:QI [(match_operand:QF 1 "reg_operand" "f")] UNSPEC_STOREQF_INT))
3479 (clobber (reg:CC 21))])]
3480 ""
3481 "#"
3482 [(set_attr "type" "multi")])
3483
3484
3485 ; This can generate invalid stack slot displacements
3486 (define_split
3487 [(set (match_operand:QF 0 "reg_operand" "")
3488 (unspec:QF [(match_operand:QI 1 "reg_operand" "")] UNSPEC_LOADQF_INT))]
3489 "reload_completed"
3490 [(set (match_dup 2) (match_dup 1))
3491 (set (match_dup 0) (match_dup 3))]
3492 "operands[2] = assign_stack_temp (QImode, GET_MODE_SIZE (QImode), 0);
3493 operands[3] = copy_rtx (operands[2]);
3494 PUT_MODE (operands[3], QFmode);")
3495
3496
3497 (define_insn "loadqf_int"
3498 [(set (match_operand:QF 0 "reg_operand" "=f")
3499 (unspec:QF [(match_operand:QI 1 "reg_operand" "r")] UNSPEC_LOADQF_INT))]
3500 ""
3501 "#"
3502 [(set_attr "type" "multi")])
3503
3504 (define_split
3505 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
3506 (unspec:QF [(match_operand:QI 1 "reg_operand" "")] UNSPEC_LOADQF_INT))
3507 (clobber (reg:CC 21))])]
3508 "reload_completed"
3509 [(set (mem:QI (pre_inc:QI (reg:QI 20)))
3510 (match_dup 1))
3511 (parallel [(set (match_dup 0)
3512 (mem:QF (post_dec:QI (reg:QI 20))))
3513 (clobber (reg:CC 21))])]
3514 "")
3515
3516 (define_insn "loadqf_int_clobber"
3517 [(parallel [(set (match_operand:QF 0 "reg_operand" "=f")
3518 (unspec:QF [(match_operand:QI 1 "reg_operand" "r")] UNSPEC_LOADQF_INT))
3519 (clobber (reg:CC 21))])]
3520 ""
3521 "#"
3522 [(set_attr "type" "multi")])
3523
3524 ; We must provide an alternative to store to memory in case we have to
3525 ; spill a register.
3526 (define_insn "movqf_noclobber"
3527 [(set (match_operand:QF 0 "dst_operand" "=f,m")
3528 (match_operand:QF 1 "src_operand" "fHm,f"))]
3529 "REG_P (operands[0]) || REG_P (operands[1])"
3530 "@
3531 ldfu\\t%1,%0
3532 stf\\t%1,%0"
3533 [(set_attr "type" "unary,store")])
3534
3535 ;(define_insn "*movqf_clobber"
3536 ; [(set (match_operand:QF 0 "reg_operand" "=f")
3537 ; (match_operand:QF 1 "src_operand" "fHm"))
3538 ; (clobber (reg:CC 21))]
3539 ; "0"
3540 ; "ldf\\t%1,%0"
3541 ; [(set_attr "type" "unarycc")])
3542
3543 (define_insn "*movqf_test"
3544 [(set (reg:CC 21)
3545 (compare:CC (match_operand:QF 1 "src_operand" "fHm")
3546 (const_int 0)))
3547 (clobber (match_scratch:QF 0 "=f"))]
3548 ""
3549 "ldf\\t%1,%0"
3550 [(set_attr "type" "unarycc")])
3551
3552 (define_insn "*movqf_set"
3553 [(set (reg:CC 21)
3554 (compare:CC (match_operand:QF 1 "src_operand" "fHm")
3555 (match_operand:QF 2 "fp_zero_operand" "G")))
3556 (set (match_operand:QF 0 "reg_operand" "=f")
3557 (match_dup 1))]
3558 ""
3559 "ldf\\t%1,%0"
3560 [(set_attr "type" "unarycc")])
3561
3562
3563 (define_insn "*movqf_parallel"
3564 [(set (match_operand:QF 0 "parallel_operand" "=q,S<>!V,q,S<>!V")
3565 (match_operand:QF 1 "parallel_operand" "S<>!V,q,S<>!V,q"))
3566 (set (match_operand:QF 2 "parallel_operand" "=q,S<>!V,S<>!V,q")
3567 (match_operand:QF 3 "parallel_operand" "S<>!V,q,q,S<>!V"))]
3568 "TARGET_PARALLEL && valid_parallel_load_store (operands, QFmode)"
3569 "@
3570 ldf1\\t%1,%0\\n||\\tldf2\\t%3,%2
3571 stf1\\t%1,%0\\n||\\tstf2\\t%3,%2
3572 ldf\\t%1,%0\\n||\\tstf\\t%3,%2
3573 ldf\\t%3,%2\\n||\\tstf\\t%1,%0"
3574 [(set_attr "type" "load_load,store_store,load_store,store_load")])
3575
3576
3577 ;
3578 ; PUSH/POP
3579 ;
3580 (define_insn "pushqf"
3581 [(set (mem:QF (pre_inc:QI (reg:QI 20)))
3582 (match_operand:QF 0 "reg_operand" "f"))]
3583 ""
3584 "pushf\\t%0"
3585 [(set_attr "type" "push")])
3586
3587 (define_insn "popqf"
3588 [(set (match_operand:QF 0 "reg_operand" "=f")
3589 (mem:QF (post_dec:QI (reg:QI 20))))
3590 (clobber (reg:CC 21))]
3591 ""
3592 "popf\\t%0"
3593 [(set_attr "type" "pop")])
3594
3595 (define_insn "popqf_unspec"
3596 [(set (unspec:QF [(match_operand:QF 0 "reg_operand" "=f")] UNSPEC_POPQF)
3597 (mem:QF (post_dec:QI (reg:QI 20))))
3598 (clobber (match_dup 0))
3599 (clobber (reg:CC 21))]
3600 ""
3601 "popf\\t%0"
3602 [(set_attr "type" "pop")])
3603
3604 ;
3605 ; ABSF
3606 ;
3607 (define_expand "absqf2"
3608 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
3609 (abs:QF (match_operand:QF 1 "src_operand" "")))
3610 (clobber (reg:CC_NOOV 21))])]
3611 ""
3612 "")
3613
3614 (define_insn "*absqf2_clobber"
3615 [(set (match_operand:QF 0 "reg_operand" "=f")
3616 (abs:QF (match_operand:QF 1 "src_operand" "fHm")))
3617 (clobber (reg:CC_NOOV 21))]
3618 ""
3619 "absf\\t%1,%0"
3620 [(set_attr "type" "unarycc")])
3621
3622 (define_insn "*absqf2_test"
3623 [(set (reg:CC_NOOV 21)
3624 (compare:CC_NOOV (abs:QF (match_operand:QF 1 "src_operand" "fHm"))
3625 (match_operand:QF 2 "fp_zero_operand" "G")))
3626 (clobber (match_scratch:QF 0 "=f"))]
3627 ""
3628 "absf\\t%1,%0"
3629 [(set_attr "type" "unarycc")])
3630
3631 (define_insn "*absqf2_set"
3632 [(set (reg:CC_NOOV 21)
3633 (compare:CC_NOOV (abs:QF (match_operand:QF 1 "src_operand" "fHm"))
3634 (match_operand:QF 2 "fp_zero_operand" "G")))
3635 (set (match_operand:QF 0 "reg_operand" "=f")
3636 (abs:QF (match_dup 1)))]
3637
3638 ""
3639 "absf\\t%1,%0"
3640 [(set_attr "type" "unarycc")])
3641
3642 ;
3643 ; NEGF
3644 ;
3645 (define_expand "negqf2"
3646 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
3647 (neg:QF (match_operand:QF 1 "src_operand" "")))
3648 (clobber (reg:CC_NOOV 21))])]
3649 ""
3650 "")
3651
3652 (define_insn "*negqf2_clobber"
3653 [(set (match_operand:QF 0 "reg_operand" "=f")
3654 (neg:QF (match_operand:QF 1 "src_operand" "fHm")))
3655 (clobber (reg:CC_NOOV 21))]
3656 ""
3657 "negf\\t%1,%0"
3658 [(set_attr "type" "unarycc")])
3659
3660 (define_insn "*negqf2_test"
3661 [(set (reg:CC_NOOV 21)
3662 (compare:CC_NOOV (neg:QF (match_operand:QF 1 "src_operand" "fHm"))
3663 (match_operand:QF 2 "fp_zero_operand" "G")))
3664 (clobber (match_scratch:QF 0 "=f"))]
3665 ""
3666 "negf\\t%1,%0"
3667 [(set_attr "type" "unarycc")])
3668
3669 (define_insn "*negqf2_set"
3670 [(set (reg:CC_NOOV 21)
3671 (compare:CC_NOOV (neg:QF (match_operand:QF 1 "src_operand" "fHm"))
3672 (match_operand:QF 2 "fp_zero_operand" "G")))
3673 (set (match_operand:QF 0 "reg_operand" "=f")
3674 (neg:QF (match_dup 1)))]
3675 ""
3676 "negf\\t%1,%0"
3677 [(set_attr "type" "unarycc")])
3678
3679 ;
3680 ; FLOAT
3681 ;
3682 (define_insn "floatqiqf2"
3683 [(set (match_operand:QF 0 "reg_operand" "=f")
3684 (float:QF (match_operand:QI 1 "src_operand" "rIm")))
3685 (clobber (reg:CC 21))]
3686 ""
3687 "float\\t%1,%0"
3688 [(set_attr "type" "unarycc")])
3689
3690 (define_insn "*floatqiqf2_set"
3691 [(set (reg:CC 21)
3692 (compare:CC (float:QF (match_operand:QI 1 "src_operand" "rIm"))
3693 (match_operand:QF 2 "fp_zero_operand" "G")))
3694 (set (match_operand:QF 0 "reg_operand" "=f")
3695 (float:QF (match_dup 1)))]
3696 ""
3697 "float\\t%1,%0"
3698 [(set_attr "type" "unarycc")])
3699
3700 ; Unsigned conversions are a little tricky because we need to
3701 ; add the value for the high bit if necessary.
3702 ;
3703 ;
3704 (define_expand "floatunsqiqf2"
3705 [(set (match_dup 2) (match_dup 3))
3706 (parallel [(set (reg:CC 21)
3707 (compare:CC (float:QF (match_operand:QI 1 "src_operand" ""))
3708 (match_dup 3)))
3709 (set (match_dup 4)
3710 (float:QF (match_dup 1)))])
3711 (set (match_dup 2)
3712 (if_then_else:QF (lt (reg:CC 21) (const_int 0))
3713 (match_dup 5)
3714 (match_dup 2)))
3715 (parallel [(set (match_operand:QF 0 "reg_operand" "")
3716 (plus:QF (match_dup 2) (match_dup 4)))
3717 (clobber (reg:CC_NOOV 21))])]
3718 ""
3719 "operands[2] = gen_reg_rtx (QFmode);
3720 operands[3] = CONST0_RTX (QFmode);
3721 operands[4] = gen_reg_rtx (QFmode);
3722 operands[5] = gen_reg_rtx (QFmode);
3723 emit_move_insn (operands[5], CONST_DOUBLE_ATOF (\"4294967296.0\", QFmode));")
3724
3725 (define_expand "floatunsqihf2"
3726 [(set (match_dup 2) (match_dup 3))
3727 (parallel [(set (reg:CC 21)
3728 (compare:CC (float:HF (match_operand:QI 1 "src_operand" ""))
3729 (match_dup 3)))
3730 (set (match_dup 4)
3731 (float:HF (match_dup 1)))])
3732 (set (match_dup 2)
3733 (if_then_else:HF (lt (reg:CC 21) (const_int 0))
3734 (match_dup 5)
3735 (match_dup 2)))
3736 (parallel [(set (match_operand:HF 0 "reg_operand" "")
3737 (plus:HF (match_dup 2) (match_dup 4)))
3738 (clobber (reg:CC_NOOV 21))])]
3739 ""
3740 "operands[2] = gen_reg_rtx (HFmode);
3741 operands[3] = CONST0_RTX (HFmode);
3742 operands[4] = gen_reg_rtx (HFmode);
3743 operands[5] = gen_reg_rtx (HFmode);
3744 emit_move_insn (operands[5], CONST_DOUBLE_ATOF (\"4294967296.0\", HFmode));")
3745
3746 (define_insn "floatqihf2"
3747 [(set (match_operand:HF 0 "reg_operand" "=h")
3748 (float:HF (match_operand:QI 1 "src_operand" "rIm")))
3749 (clobber (reg:CC 21))]
3750 ""
3751 "float\\t%1,%0"
3752 [(set_attr "type" "unarycc")])
3753
3754 (define_insn "*floatqihf2_set"
3755 [(set (reg:CC 21)
3756 (compare:CC (float:HF (match_operand:QI 1 "src_operand" "rIm"))
3757 (match_operand:QF 2 "fp_zero_operand" "G")))
3758 (set (match_operand:HF 0 "reg_operand" "=h")
3759 (float:HF (match_dup 1)))]
3760 ""
3761 "float\\t%1,%0"
3762 [(set_attr "type" "unarycc")])
3763
3764 ;
3765 ; FIX
3766 ;
3767 (define_insn "fixqfqi_clobber"
3768 [(set (match_operand:QI 0 "reg_operand" "=d,c")
3769 (fix:QI (match_operand:QF 1 "src_operand" "fHm,fHm")))
3770 (clobber (reg:CC 21))]
3771 ""
3772 "fix\\t%1,%0"
3773 [(set_attr "type" "unarycc")])
3774
3775 (define_insn "*fixqfqi_set"
3776 [(set (reg:CC 21)
3777 (compare:CC (fix:QI (match_operand:QF 1 "src_operand" "fHm"))
3778 (const_int 0)))
3779 (set (match_operand:QI 0 "ext_reg_operand" "=d")
3780 (fix:QI (match_dup 1)))]
3781 ""
3782 "fix\\t%1,%0"
3783 [(set_attr "type" "unarycc")])
3784
3785 ;
3786 ; The C[34]x fix instruction implements a floor, not a straight trunc,
3787 ; so we have to invert the number, fix it, and reinvert it if negative
3788 ;
3789 (define_expand "fix_truncqfqi2"
3790 [(parallel [(set (match_dup 2)
3791 (fix:QI (match_operand:QF 1 "src_operand" "")))
3792 (clobber (reg:CC 21))])
3793 (parallel [(set (match_dup 3) (neg:QF (match_dup 1)))
3794 (clobber (reg:CC_NOOV 21))])
3795 (parallel [(set (match_dup 4) (fix:QI (match_dup 3)))
3796 (clobber (reg:CC 21))])
3797 (parallel [(set (reg:CC_NOOV 21)
3798 (compare:CC_NOOV (neg:QI (match_dup 4)) (const_int 0)))
3799 (set (match_dup 5) (neg:QI (match_dup 4)))])
3800 (set (match_dup 2)
3801 (if_then_else:QI (le (reg:CC 21) (const_int 0))
3802 (match_dup 5)
3803 (match_dup 2)))
3804 (set (match_operand:QI 0 "reg_operand" "=r") (match_dup 2))]
3805 ""
3806 "if (TARGET_FAST_FIX)
3807 {
3808 emit_insn (gen_fixqfqi_clobber (operands[0], operands[1]));
3809 DONE;
3810 }
3811 operands[2] = gen_reg_rtx (QImode);
3812 operands[3] = gen_reg_rtx (QFmode);
3813 operands[4] = gen_reg_rtx (QImode);
3814 operands[5] = gen_reg_rtx (QImode);
3815 ")
3816
3817 (define_expand "fix_truncqfhi2"
3818 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
3819 (fix:HI (match_operand:QF 1 "src_operand" "")))
3820 (clobber (reg:CC 21))])]
3821 ""
3822 "c4x_emit_libcall (fix_truncqfhi2_libfunc, FIX, HImode, QFmode, 2, operands);
3823 DONE;")
3824
3825 (define_expand "fixuns_truncqfqi2"
3826 [(parallel [(set (match_dup 2)
3827 (fix:QI (match_operand:QF 1 "src_operand" "fHm")))
3828 (clobber (reg:CC 21))])
3829 (parallel [(set (match_dup 3)
3830 (minus:QF (match_dup 1) (match_dup 5)))
3831 (clobber (reg:CC_NOOV 21))])
3832 (parallel [(set (reg:CC 21)
3833 (compare:CC (fix:QI (match_dup 3))
3834 (const_int 0)))
3835 (set (match_dup 4)
3836 (fix:QI (match_dup 3)))])
3837 (parallel [(set (match_dup 4) (unspec:QI [(match_dup 2)] UNSPEC_LDIV))
3838 (use (reg:CC 21))])
3839 (set (match_operand:QI 0 "reg_operand" "=r") (match_dup 4))]
3840 ""
3841 "operands[2] = gen_reg_rtx (QImode);
3842 operands[3] = gen_reg_rtx (QFmode);
3843 operands[4] = gen_reg_rtx (QImode);
3844 operands[5] = gen_reg_rtx (QFmode);
3845 emit_move_insn (operands[5], CONST_DOUBLE_ATOF (\"4294967296.0\", QFmode));")
3846
3847 (define_expand "fixuns_truncqfhi2"
3848 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
3849 (unsigned_fix:HI (match_operand:QF 1 "src_operand" "")))
3850 (clobber (reg:CC 21))])]
3851 ""
3852 "c4x_emit_libcall (fixuns_truncqfhi2_libfunc, UNSIGNED_FIX,
3853 HImode, QFmode, 2, operands);
3854 DONE;")
3855
3856 ;
3857 ; RCPF
3858 ;
3859 (define_insn "rcpfqf_clobber"
3860 [(set (match_operand:QF 0 "reg_operand" "=f")
3861 (unspec:QF [(match_operand:QF 1 "src_operand" "fHm")] UNSPEC_RCPF))
3862 (clobber (reg:CC_NOOV 21))]
3863 "! TARGET_C3X"
3864 "rcpf\\t%1,%0"
3865 [(set_attr "type" "unarycc")])
3866
3867 ;
3868 ; RSQRF
3869 ;
3870 (define_insn "*rsqrfqf_clobber"
3871 [(set (match_operand:QF 0 "reg_operand" "=f")
3872 (unspec:QF [(match_operand:QF 1 "src_operand" "fHm")] UNSPEC_RSQRF))
3873 (clobber (reg:CC_NOOV 21))]
3874 "! TARGET_C3X"
3875 "rsqrf\\t%1,%0"
3876 [(set_attr "type" "unarycc")])
3877
3878 ;
3879 ; RNDF
3880 ;
3881 (define_insn "*rndqf_clobber"
3882 [(set (match_operand:QF 0 "reg_operand" "=f")
3883 (unspec:QF [(match_operand:QF 1 "src_operand" "fHm")] UNSPEC_RND))
3884 (clobber (reg:CC_NOOV 21))]
3885 "! TARGET_C3X"
3886 "rnd\\t%1,%0"
3887 [(set_attr "type" "unarycc")])
3888
3889
3890 ; Inlined float square root for C4x
3891 (define_expand "sqrtqf2_inline"
3892 [(parallel [(set (match_dup 2)
3893 (unspec:QF [(match_operand:QF 1 "src_operand" "")] UNSPEC_RSQRF))
3894 (clobber (reg:CC_NOOV 21))])
3895 (parallel [(set (match_dup 3) (mult:QF (match_dup 5) (match_dup 1)))
3896 (clobber (reg:CC_NOOV 21))])
3897 (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 3)))
3898 (clobber (reg:CC_NOOV 21))])
3899 (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 4)))
3900 (clobber (reg:CC_NOOV 21))])
3901 (parallel [(set (match_dup 4) (minus:QF (match_dup 6) (match_dup 4)))
3902 (clobber (reg:CC_NOOV 21))])
3903 (parallel [(set (match_dup 2) (mult:QF (match_dup 2) (match_dup 4)))
3904 (clobber (reg:CC_NOOV 21))])
3905 (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 3)))
3906 (clobber (reg:CC_NOOV 21))])
3907 (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 4)))
3908 (clobber (reg:CC_NOOV 21))])
3909 (parallel [(set (match_dup 4) (minus:QF (match_dup 6) (match_dup 4)))
3910 (clobber (reg:CC_NOOV 21))])
3911 (parallel [(set (match_dup 2) (mult:QF (match_dup 2) (match_dup 4)))
3912 (clobber (reg:CC_NOOV 21))])
3913 (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 1)))
3914 (clobber (reg:CC_NOOV 21))])
3915 (parallel [(set (match_operand:QF 0 "reg_operand" "")
3916 (unspec:QF [(match_dup 4)] UNSPEC_RND))
3917 (clobber (reg:CC_NOOV 21))])]
3918 "! TARGET_C3X"
3919 "if (! reload_in_progress
3920 && ! reg_operand (operands[1], QFmode))
3921 operands[1] = force_reg (QFmode, operands[1]);
3922 operands[2] = gen_reg_rtx (QFmode);
3923 operands[3] = gen_reg_rtx (QFmode);
3924 operands[4] = gen_reg_rtx (QFmode);
3925 operands[5] = CONST_DOUBLE_ATOF (\"0.5\", QFmode);
3926 operands[6] = CONST_DOUBLE_ATOF (\"1.5\", QFmode);")
3927
3928 (define_expand "sqrtqf2"
3929 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
3930 (sqrt:QF (match_operand:QF 1 "src_operand" "")))
3931 (clobber (reg:CC 21))])]
3932 "! TARGET_C3X && TARGET_INLINE"
3933 "emit_insn (gen_sqrtqf2_inline (operands[0], operands[1]));
3934 DONE;")
3935
3936 ;
3937 ; TOIEEE / FRIEEE
3938 ;
3939 (define_insn "toieee"
3940 [(set (match_operand:QF 0 "reg_operand" "=f")
3941 (unspec:QF [(match_operand:QF 1 "src_operand" "fHm")] UNSPEC_TOIEEE))
3942 (clobber (reg:CC 21))]
3943 ""
3944 "toieee\\t%1,%0")
3945
3946 (define_insn "frieee"
3947 [(set (match_operand:QF 0 "reg_operand" "=f")
3948 (unspec:QF [(match_operand:QF 1 "memory_operand" "m")] UNSPEC_FRIEEE))
3949 (clobber (reg:CC 21))]
3950 ""
3951 "frieee\\t%1,%0")
3952
3953 ;
3954 ; THREE OPERAND FLOAT INSTRUCTIONS
3955 ;
3956
3957 ;
3958 ; ADDF
3959 ;
3960 (define_expand "addqf3"
3961 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
3962 (plus:QF (match_operand:QF 1 "src_operand" "")
3963 (match_operand:QF 2 "src_operand" "")))
3964 (clobber (reg:CC_NOOV 21))])]
3965 ""
3966 "legitimize_operands (PLUS, operands, QFmode);")
3967
3968 (define_insn "*addqf3_clobber"
3969 [(set (match_operand:QF 0 "reg_operand" "=f,f,?f")
3970 (plus:QF (match_operand:QF 1 "src_operand" "%0,fR,fS<>")
3971 (match_operand:QF 2 "src_operand" "fHm,R,fS<>")))
3972 (clobber (reg:CC_NOOV 21))]
3973 "valid_operands (PLUS, operands, QFmode)"
3974 "@
3975 addf\\t%2,%0
3976 addf3\\t%2,%1,%0
3977 addf3\\t%2,%1,%0"
3978 [(set_attr "type" "binarycc,binarycc,binarycc")])
3979
3980 (define_insn "*addqf3_test"
3981 [(set (reg:CC_NOOV 21)
3982 (compare:CC_NOOV (plus:QF (match_operand:QF 1 "src_operand" "%0,fR,fS<>")
3983 (match_operand:QF 2 "src_operand" "fHm,R,fS<>"))
3984 (match_operand:QF 3 "fp_zero_operand" "G,G,G")))
3985 (clobber (match_scratch:QF 0 "=f,f,?f"))]
3986 "valid_operands (PLUS, operands, QFmode)"
3987 "@
3988 addf\\t%2,%0
3989 addf3\\t%2,%1,%0
3990 addf3\\t%2,%1,%0"
3991 [(set_attr "type" "binarycc,binarycc,binarycc")])
3992
3993 (define_insn "*addqf3_set"
3994 [(set (reg:CC_NOOV 21)
3995 (compare:CC_NOOV (plus:QF (match_operand:QF 1 "src_operand" "%0,fR,fS<>")
3996 (match_operand:QF 2 "src_operand" "fHm,R,fS<>"))
3997 (match_operand:QF 3 "fp_zero_operand" "G,G,G")))
3998 (set (match_operand:QF 0 "reg_operand" "=f,f,?f")
3999 (plus:QF (match_dup 1)
4000 (match_dup 2)))]
4001 "valid_operands (PLUS, operands, QFmode)"
4002 "@
4003 addf\\t%2,%0
4004 addf3\\t%2,%1,%0
4005 addf3\\t%2,%1,%0"
4006 [(set_attr "type" "binarycc,binarycc,binarycc")])
4007
4008 ;
4009 ; SUBF/SUBRF
4010 ;
4011 (define_expand "subqf3"
4012 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
4013 (minus:QF (match_operand:QF 1 "src_operand" "")
4014 (match_operand:QF 2 "src_operand" "")))
4015 (clobber (reg:CC_NOOV 21))])]
4016 ""
4017 "legitimize_operands (MINUS, operands, QFmode);")
4018
4019 (define_insn "*subqf3_clobber"
4020 [(set (match_operand:QF 0 "reg_operand" "=f,f,f,?f")
4021 (minus:QF (match_operand:QF 1 "src_operand" "0,fHm,fR,fS<>")
4022 (match_operand:QF 2 "src_operand" "fHm,0,R,fS<>")))
4023 (clobber (reg:CC_NOOV 21))]
4024 "valid_operands (MINUS, operands, QFmode)"
4025 "@
4026 subf\\t%2,%0
4027 subrf\\t%1,%0
4028 subf3\\t%2,%1,%0
4029 subf3\\t%2,%1,%0"
4030 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
4031
4032 (define_insn "*subqf3_test"
4033 [(set (reg:CC_NOOV 21)
4034 (compare:CC_NOOV (minus:QF (match_operand:QF 1 "src_operand" "0,fHm,fR,fS<>")
4035 (match_operand:QF 2 "src_operand" "fHm,0,R,fS<>"))
4036 (match_operand:QF 3 "fp_zero_operand" "G,G,G,G")))
4037 (clobber (match_scratch:QF 0 "=f,f,f,?f"))]
4038 "valid_operands (MINUS, operands, QFmode)"
4039 "@
4040 subf\\t%2,%0
4041 subrf\\t%1,%0
4042 subf3\\t%2,%1,%0
4043 subf3\\t%2,%1,%0"
4044 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
4045
4046 (define_insn "*subqf3_set"
4047 [(set (reg:CC_NOOV 21)
4048 (compare:CC_NOOV (minus:QF (match_operand:QF 1 "src_operand" "0,fHm,fR,fS<>")
4049 (match_operand:QF 2 "src_operand" "fHm,0,R,fS<>"))
4050 (match_operand:QF 3 "fp_zero_operand" "G,G,G,G")))
4051 (set (match_operand:QF 0 "reg_operand" "=f,f,f,?f")
4052 (minus:QF (match_dup 1)
4053 (match_dup 2)))]
4054 "valid_operands (MINUS, operands, QFmode)"
4055 "@
4056 subf\\t%2,%0
4057 subrf\\t%1,%0
4058 subf3\\t%2,%1,%0
4059 subf3\\t%2,%1,%0"
4060 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
4061
4062 ;
4063 ; MPYF
4064 ;
4065 (define_expand "mulqf3"
4066 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
4067 (mult:QF (match_operand:QF 1 "src_operand" "")
4068 (match_operand:QF 2 "src_operand" "")))
4069 (clobber (reg:CC_NOOV 21))])]
4070 ""
4071 "legitimize_operands (MULT, operands, QFmode);")
4072
4073 (define_insn "*mulqf3_clobber"
4074 [(set (match_operand:QF 0 "reg_operand" "=f,f,?f")
4075 (mult:QF (match_operand:QF 1 "src_operand" "%0,fR,fS<>")
4076 (match_operand:QF 2 "src_operand" "fHm,R,fS<>")))
4077 (clobber (reg:CC_NOOV 21))]
4078 "valid_operands (MULT, operands, QFmode)"
4079 "@
4080 mpyf\\t%2,%0
4081 mpyf3\\t%2,%1,%0
4082 mpyf3\\t%2,%1,%0"
4083 [(set_attr "type" "binarycc,binarycc,binarycc")])
4084
4085 (define_insn "*mulqf3_test"
4086 [(set (reg:CC_NOOV 21)
4087 (compare:CC_NOOV (mult:QF (match_operand:QF 1 "src_operand" "%0,fR,fS<>")
4088 (match_operand:QF 2 "src_operand" "fHm,R,fS<>"))
4089 (match_operand:QF 3 "fp_zero_operand" "G,G,G")))
4090 (clobber (match_scratch:QF 0 "=f,f,?f"))]
4091 "valid_operands (MULT, operands, QFmode)"
4092 "@
4093 mpyf\\t%2,%0
4094 mpyf3\\t%2,%1,%0
4095 mpyf3\\t%2,%1,%0"
4096 [(set_attr "type" "binarycc,binarycc,binarycc")])
4097
4098 (define_insn "*mulqf3_set"
4099 [(set (reg:CC_NOOV 21)
4100 (compare:CC_NOOV (mult:QF (match_operand:QF 1 "src_operand" "%0,fR,fS<>")
4101 (match_operand:QF 2 "src_operand" "fHm,R,fS<>"))
4102 (match_operand:QF 3 "fp_zero_operand" "G,G,G")))
4103 (set (match_operand:QF 0 "reg_operand" "=f,f,?f")
4104 (mult:QF (match_dup 1)
4105 (match_dup 2)))]
4106 "valid_operands (MULT, operands, QFmode)"
4107 "@
4108 mpyf\\t%2,%0
4109 mpyf3\\t%2,%1,%0
4110 mpyf3\\t%2,%1,%0"
4111 [(set_attr "type" "binarycc,binarycc,binarycc")])
4112
4113 ;
4114 ; CMPF
4115 ;
4116 (define_expand "cmpqf"
4117 [(set (reg:CC 21)
4118 (compare:CC (match_operand:QF 0 "src_operand" "")
4119 (match_operand:QF 1 "src_operand" "")))]
4120 ""
4121 "legitimize_operands (COMPARE, operands, QFmode);
4122 c4x_compare_op0 = operands[0];
4123 c4x_compare_op1 = operands[1];
4124 DONE;")
4125
4126 (define_insn "*cmpqf"
4127 [(set (reg:CC 21)
4128 (compare:CC (match_operand:QF 0 "src_operand" "f,fR,fS<>")
4129 (match_operand:QF 1 "src_operand" "fHm,R,fS<>")))]
4130 "valid_operands (COMPARE, operands, QFmode)"
4131 "@
4132 cmpf\\t%1,%0
4133 cmpf3\\t%1,%0
4134 cmpf3\\t%1,%0"
4135 [(set_attr "type" "compare,compare,compare")])
4136
4137 (define_insn "*cmpqf_noov"
4138 [(set (reg:CC_NOOV 21)
4139 (compare:CC_NOOV (match_operand:QF 0 "src_operand" "f,fR,fS<>")
4140 (match_operand:QF 1 "src_operand" "fHm,R,fS<>")))]
4141 "valid_operands (COMPARE, operands, QFmode)"
4142 "@
4143 cmpf\\t%1,%0
4144 cmpf3\\t%1,%0
4145 cmpf3\\t%1,%0"
4146 [(set_attr "type" "compare,compare,compare")])
4147
4148 ; Inlined float divide for C4x
4149 (define_expand "divqf3_inline"
4150 [(parallel [(set (match_dup 3)
4151 (unspec:QF [(match_operand:QF 2 "src_operand" "")] UNSPEC_RCPF))
4152 (clobber (reg:CC_NOOV 21))])
4153 (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 3)))
4154 (clobber (reg:CC_NOOV 21))])
4155 (parallel [(set (match_dup 4) (minus:QF (match_dup 5) (match_dup 4)))
4156 (clobber (reg:CC_NOOV 21))])
4157 (parallel [(set (match_dup 3) (mult:QF (match_dup 3) (match_dup 4)))
4158 (clobber (reg:CC_NOOV 21))])
4159 (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 3)))
4160 (clobber (reg:CC_NOOV 21))])
4161 (parallel [(set (match_dup 4) (minus:QF (match_dup 5) (match_dup 4)))
4162 (clobber (reg:CC_NOOV 21))])
4163 (parallel [(set (match_dup 3) (mult:QF (match_dup 3) (match_dup 4)))
4164 (clobber (reg:CC_NOOV 21))])
4165 (parallel [(set (match_dup 3)
4166 (mult:QF (match_operand:QF 1 "src_operand" "")
4167 (match_dup 3)))
4168 (clobber (reg:CC_NOOV 21))])
4169 (parallel [(set (match_operand:QF 0 "reg_operand" "")
4170 (unspec:QF [(match_dup 3)] UNSPEC_RND))
4171 (clobber (reg:CC_NOOV 21))])]
4172 "! TARGET_C3X"
4173 "if (! reload_in_progress
4174 && ! reg_operand (operands[2], QFmode))
4175 operands[2] = force_reg (QFmode, operands[2]);
4176 operands[3] = gen_reg_rtx (QFmode);
4177 operands[4] = gen_reg_rtx (QFmode);
4178 operands[5] = CONST2_RTX (QFmode);")
4179
4180 (define_expand "divqf3"
4181 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
4182 (div:QF (match_operand:QF 1 "src_operand" "")
4183 (match_operand:QF 2 "src_operand" "")))
4184 (clobber (reg:CC 21))])]
4185 "! TARGET_C3X && TARGET_INLINE"
4186 "emit_insn (gen_divqf3_inline (operands[0], operands[1], operands[2]));
4187 DONE;")
4188
4189 ;
4190 ; CONDITIONAL MOVES
4191 ;
4192
4193 ; ??? We should make these pattern fail if the src operand combination
4194 ; is not valid. Although reload will fix things up, it will introduce
4195 ; extra load instructions that won't be hoisted out of a loop.
4196
4197 (define_insn "*ldi_conditional"
4198 [(set (match_operand:QI 0 "reg_operand" "=r,r")
4199 (if_then_else:QI (match_operator 1 "comparison_operator"
4200 [(reg:CC 21) (const_int 0)])
4201 (match_operand:QI 2 "src_operand" "rIm,0")
4202 (match_operand:QI 3 "src_operand" "0,rIm")))]
4203 "valid_operands (IF_THEN_ELSE, operands, QImode)"
4204 "@
4205 ldi%1\\t%2,%0
4206 ldi%I1\\t%3,%0"
4207 [(set_attr "type" "binary")])
4208
4209 (define_insn "*ldi_conditional_noov"
4210 [(set (match_operand:QI 0 "reg_operand" "=r,r")
4211 (if_then_else:QI (match_operator 1 "comparison_operator"
4212 [(reg:CC_NOOV 21) (const_int 0)])
4213 (match_operand:QI 2 "src_operand" "rIm,0")
4214 (match_operand:QI 3 "src_operand" "0,rIm")))]
4215 "GET_CODE (operands[1]) != LE
4216 && GET_CODE (operands[1]) != GE
4217 && GET_CODE (operands[1]) != LT
4218 && GET_CODE (operands[1]) != GT
4219 && valid_operands (IF_THEN_ELSE, operands, QImode)"
4220 "@
4221 ldi%1\\t%2,%0
4222 ldi%I1\\t%3,%0"
4223 [(set_attr "type" "binary")])
4224
4225 (define_insn "*ldi_on_overflow"
4226 [(set (match_operand:QI 0 "reg_operand" "=r")
4227 (unspec:QI [(match_operand:QI 1 "src_operand" "rIm")] UNSPEC_LDIV))
4228 (use (reg:CC 21))]
4229 ""
4230 "ldiv\\t%1,%0"
4231 [(set_attr "type" "unary")])
4232
4233 ; Move operand 2 to operand 0 if condition (operand 1) is true
4234 ; else move operand 3 to operand 0.
4235 ; The temporary register is required below because some of the operands
4236 ; might be identical (namely 0 and 2).
4237 ;
4238 (define_expand "movqicc"
4239 [(set (match_operand:QI 0 "reg_operand" "")
4240 (if_then_else:QI (match_operand 1 "comparison_operator" "")
4241 (match_operand:QI 2 "src_operand" "")
4242 (match_operand:QI 3 "src_operand" "")))]
4243 ""
4244 "{
4245 enum rtx_code code = GET_CODE (operands[1]);
4246 rtx ccreg = c4x_gen_compare_reg (code, c4x_compare_op0, c4x_compare_op1);
4247 if (ccreg == NULL_RTX) FAIL;
4248 emit_insn (gen_rtx_SET (QImode, operands[0],
4249 gen_rtx_IF_THEN_ELSE (QImode,
4250 gen_rtx (code, VOIDmode, ccreg, const0_rtx),
4251 operands[2], operands[3])));
4252 DONE;}")
4253
4254 (define_insn "*ldf_conditional"
4255 [(set (match_operand:QF 0 "reg_operand" "=f,f")
4256 (if_then_else:QF (match_operator 1 "comparison_operator"
4257 [(reg:CC 21) (const_int 0)])
4258 (match_operand:QF 2 "src_operand" "fHm,0")
4259 (match_operand:QF 3 "src_operand" "0,fHm")))]
4260 "valid_operands (IF_THEN_ELSE, operands, QFmode)"
4261 "@
4262 ldf%1\\t%2,%0
4263 ldf%I1\\t%3,%0"
4264 [(set_attr "type" "binary")])
4265
4266 (define_insn "*ldf_conditional_noov"
4267 [(set (match_operand:QF 0 "reg_operand" "=f,f")
4268 (if_then_else:QF (match_operator 1 "comparison_operator"
4269 [(reg:CC_NOOV 21) (const_int 0)])
4270 (match_operand:QF 2 "src_operand" "fHm,0")
4271 (match_operand:QF 3 "src_operand" "0,fHm")))]
4272 "GET_CODE (operands[1]) != LE
4273 && GET_CODE (operands[1]) != GE
4274 && GET_CODE (operands[1]) != LT
4275 && GET_CODE (operands[1]) != GT
4276 && valid_operands (IF_THEN_ELSE, operands, QFmode)"
4277 "@
4278 ldf%1\\t%2,%0
4279 ldf%I1\\t%3,%0"
4280 [(set_attr "type" "binary")])
4281
4282 (define_expand "movqfcc"
4283 [(set (match_operand:QF 0 "reg_operand" "")
4284 (if_then_else:QF (match_operand 1 "comparison_operator" "")
4285 (match_operand:QF 2 "src_operand" "")
4286 (match_operand:QF 3 "src_operand" "")))]
4287 ""
4288 "{
4289 enum rtx_code code = GET_CODE (operands[1]);
4290 rtx ccreg = c4x_gen_compare_reg (code, c4x_compare_op0, c4x_compare_op1);
4291 if (ccreg == NULL_RTX) FAIL;
4292 emit_insn (gen_rtx_SET (QFmode, operands[0],
4293 gen_rtx_IF_THEN_ELSE (QFmode,
4294 gen_rtx (code, VOIDmode, ccreg, const0_rtx),
4295 operands[2], operands[3])));
4296 DONE;}")
4297
4298 (define_insn "*ldhf_conditional"
4299 [(set (match_operand:HF 0 "reg_operand" "=h,h")
4300 (if_then_else:HF (match_operator 1 "comparison_operator"
4301 [(reg:CC 21) (const_int 0)])
4302 (match_operand:HF 2 "src_operand" "hH,0")
4303 (match_operand:HF 3 "src_operand" "0,hH")))]
4304 ""
4305 "@
4306 ldf%1\\t%2,%0
4307 ldf%I1\\t%3,%0"
4308 [(set_attr "type" "binary")])
4309
4310 (define_insn "*ldhf_conditional_noov"
4311 [(set (match_operand:HF 0 "reg_operand" "=h,h")
4312 (if_then_else:HF (match_operator 1 "comparison_operator"
4313 [(reg:CC_NOOV 21) (const_int 0)])
4314 (match_operand:HF 2 "src_operand" "hH,0")
4315 (match_operand:HF 3 "src_operand" "0,hH")))]
4316 "GET_CODE (operands[1]) != LE
4317 && GET_CODE (operands[1]) != GE
4318 && GET_CODE (operands[1]) != LT
4319 && GET_CODE (operands[1]) != GT"
4320 "@
4321 ldf%1\\t%2,%0
4322 ldf%I1\\t%3,%0"
4323 [(set_attr "type" "binary")])
4324
4325 (define_expand "movhfcc"
4326 [(set (match_operand:HF 0 "reg_operand" "")
4327 (if_then_else:HF (match_operand 1 "comparison_operator" "")
4328 (match_operand:HF 2 "src_operand" "")
4329 (match_operand:HF 3 "src_operand" "")))]
4330 ""
4331 "{
4332 enum rtx_code code = GET_CODE (operands[1]);
4333 rtx ccreg = c4x_gen_compare_reg (code, c4x_compare_op0, c4x_compare_op1);
4334 if (ccreg == NULL_RTX) FAIL;
4335 emit_insn (gen_rtx_SET (HFmode, operands[0],
4336 gen_rtx_IF_THEN_ELSE (HFmode,
4337 gen_rtx (code, VOIDmode, ccreg, const0_rtx),
4338 operands[2], operands[3])));
4339 DONE;}")
4340
4341 (define_expand "seq"
4342 [(set (match_operand:QI 0 "reg_operand" "")
4343 (const_int 0))
4344 (set (match_dup 0)
4345 (if_then_else:QI (eq (match_dup 1) (const_int 0))
4346 (const_int 1)
4347 (match_dup 0)))]
4348 ""
4349 "operands[1] = c4x_gen_compare_reg (EQ, c4x_compare_op0, c4x_compare_op1);")
4350
4351 (define_expand "sne"
4352 [(set (match_operand:QI 0 "reg_operand" "")
4353 (const_int 0))
4354 (set (match_dup 0)
4355 (if_then_else:QI (ne (match_dup 1) (const_int 0))
4356 (const_int 1)
4357 (match_dup 0)))]
4358 ""
4359 "operands[1] = c4x_gen_compare_reg (NE, c4x_compare_op0, c4x_compare_op1);")
4360
4361 (define_expand "slt"
4362 [(set (match_operand:QI 0 "reg_operand" "")
4363 (const_int 0))
4364 (set (match_dup 0)
4365 (if_then_else:QI (lt (match_dup 1) (const_int 0))
4366 (const_int 1)
4367 (match_dup 0)))]
4368 ""
4369 "operands[1] = c4x_gen_compare_reg (LT, c4x_compare_op0, c4x_compare_op1);
4370 if (operands[1] == NULL_RTX) FAIL;")
4371
4372 (define_expand "sltu"
4373 [(set (match_operand:QI 0 "reg_operand" "")
4374 (const_int 0))
4375 (set (match_dup 0)
4376 (if_then_else:QI (ltu (match_dup 1) (const_int 0))
4377 (const_int 1)
4378 (match_dup 0)))]
4379 ""
4380 "operands[1] = c4x_gen_compare_reg (LTU, c4x_compare_op0, c4x_compare_op1);")
4381
4382 (define_expand "sgt"
4383 [(set (match_operand:QI 0 "reg_operand" "")
4384 (const_int 0))
4385 (set (match_dup 0)
4386 (if_then_else:QI (gt (match_dup 1) (const_int 0))
4387 (const_int 1)
4388 (match_dup 0)))]
4389 ""
4390 "operands[1] = c4x_gen_compare_reg (GT, c4x_compare_op0, c4x_compare_op1);
4391 if (operands[1] == NULL_RTX) FAIL;")
4392
4393 (define_expand "sgtu"
4394 [(set (match_operand:QI 0 "reg_operand" "")
4395 (const_int 0))
4396 (set (match_dup 0)
4397 (if_then_else:QI (gtu (match_dup 1) (const_int 0))
4398 (const_int 1)
4399 (match_dup 0)))]
4400 ""
4401 "operands[1] = c4x_gen_compare_reg (GTU, c4x_compare_op0, c4x_compare_op1);")
4402
4403 (define_expand "sle"
4404 [(set (match_operand:QI 0 "reg_operand" "")
4405 (const_int 0))
4406 (set (match_dup 0)
4407 (if_then_else:QI (le (match_dup 1) (const_int 0))
4408 (const_int 1)
4409 (match_dup 0)))]
4410 ""
4411 "operands[1] = c4x_gen_compare_reg (LE, c4x_compare_op0, c4x_compare_op1);
4412 if (operands[1] == NULL_RTX) FAIL;")
4413
4414 (define_expand "sleu"
4415 [(set (match_operand:QI 0 "reg_operand" "")
4416 (const_int 0))
4417 (set (match_dup 0)
4418 (if_then_else:QI (leu (match_dup 1) (const_int 0))
4419 (const_int 1)
4420 (match_dup 0)))]
4421 ""
4422 "operands[1] = c4x_gen_compare_reg (LEU, c4x_compare_op0, c4x_compare_op1);")
4423
4424 (define_expand "sge"
4425 [(set (match_operand:QI 0 "reg_operand" "")
4426 (const_int 0))
4427 (set (match_dup 0)
4428 (if_then_else:QI (ge (match_dup 1) (const_int 0))
4429 (const_int 1)
4430 (match_dup 0)))]
4431 ""
4432 "operands[1] = c4x_gen_compare_reg (GE, c4x_compare_op0, c4x_compare_op1);
4433 if (operands[1] == NULL_RTX) FAIL;")
4434
4435 (define_expand "sgeu"
4436 [(set (match_operand:QI 0 "reg_operand" "")
4437 (const_int 0))
4438 (set (match_dup 0)
4439 (if_then_else:QI (geu (match_dup 1) (const_int 0))
4440 (const_int 1)
4441 (match_dup 0)))]
4442 ""
4443 "operands[1] = c4x_gen_compare_reg (GEU, c4x_compare_op0, c4x_compare_op1);")
4444
4445 (define_split
4446 [(set (match_operand:QI 0 "reg_operand" "")
4447 (match_operator:QI 1 "comparison_operator" [(reg:CC 21) (const_int 0)]))]
4448 "reload_completed"
4449 [(set (match_dup 0) (const_int 0))
4450 (set (match_dup 0)
4451 (if_then_else:QI (match_op_dup 1 [(reg:CC 21) (const_int 0)])
4452 (const_int 1)
4453 (match_dup 0)))]
4454 "")
4455
4456 (define_split
4457 [(set (match_operand:QI 0 "reg_operand" "")
4458 (match_operator:QI 1 "comparison_operator" [(reg:CC_NOOV 21) (const_int 0)]))]
4459 "reload_completed"
4460 [(set (match_dup 0) (const_int 0))
4461 (set (match_dup 0)
4462 (if_then_else:QI (match_op_dup 1 [(reg:CC_NOOV 21) (const_int 0)])
4463 (const_int 1)
4464 (match_dup 0)))]
4465 "")
4466
4467 (define_insn "*bu"
4468 [(set (pc)
4469 (unspec [(match_operand:QI 0 "reg_operand" "r")] UNSPEC_BU))]
4470 ""
4471 "bu%#\\t%0"
4472 [(set_attr "type" "jump")])
4473
4474 (define_expand "caseqi"
4475 [(parallel [(set (match_dup 5)
4476 (minus:QI (match_operand:QI 0 "reg_operand" "")
4477 (match_operand:QI 1 "src_operand" "")))
4478 (clobber (reg:CC_NOOV 21))])
4479 (set (reg:CC 21)
4480 (compare:CC (match_dup 5)
4481 (match_operand:QI 2 "src_operand" "")))
4482 (set (pc)
4483 (if_then_else (gtu (reg:CC 21)
4484 (const_int 0))
4485 (label_ref (match_operand 4 "" ""))
4486 (pc)))
4487 (parallel [(set (match_dup 6)
4488 (plus:QI (match_dup 5)
4489 (label_ref:QI (match_operand 3 "" ""))))
4490 (clobber (reg:CC_NOOV 21))])
4491 (set (match_dup 7)
4492 (mem:QI (match_dup 6)))
4493 (set (pc) (match_dup 7))]
4494 ""
4495 "operands[5] = gen_reg_rtx (QImode);
4496 operands[6] = gen_reg_rtx (QImode);
4497 operands[7] = gen_reg_rtx (QImode);")
4498
4499 ;
4500 ; PARALLEL FLOAT INSTRUCTIONS
4501 ;
4502 ; This patterns are under development
4503
4504 ;
4505 ; ABSF/STF
4506 ;
4507
4508 (define_insn "*absqf2_movqf_clobber"
4509 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
4510 (abs:QF (match_operand:QF 1 "par_ind_operand" "S<>")))
4511 (set (match_operand:QF 2 "par_ind_operand" "=S<>")
4512 (match_operand:QF 3 "ext_low_reg_operand" "q"))
4513 (clobber (reg:CC_NOOV 21))]
4514 "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QFmode)"
4515 "absf\\t%1,%0\\n||\\tstf\\t%3,%2"
4516 [(set_attr "type" "binarycc")])
4517
4518 ;
4519 ; ADDF/STF
4520 ;
4521
4522 (define_insn "*addqf3_movqf_clobber"
4523 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q,q")
4524 (plus:QF (match_operand:QF 1 "parallel_operand" "%q,S<>")
4525 (match_operand:QF 2 "parallel_operand" "S<>,q")))
4526 (set (match_operand:QF 3 "par_ind_operand" "=S<>,S<>")
4527 (match_operand:QF 4 "ext_low_reg_operand" "q,q"))
4528 (clobber (reg:CC 21))]
4529 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QFmode)"
4530 "addf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3"
4531 [(set_attr "type" "binarycc,binarycc")])
4532
4533 ;
4534 ; FLOAT/STF
4535 ;
4536
4537 (define_insn "*floatqiqf2_movqf_clobber"
4538 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
4539 (float:QF (match_operand:QI 1 "par_ind_operand" "S<>")))
4540 (set (match_operand:QF 2 "par_ind_operand" "=S<>")
4541 (match_operand:QF 3 "ext_low_reg_operand" "q"))
4542 (clobber (reg:CC 21))]
4543 "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QFmode)"
4544 "float\\t%1,%0\\n||\\tstf\\t%3,%2"
4545 [(set_attr "type" "binarycc")])
4546
4547 ;
4548 ; MPYF/ADDF
4549 ;
4550
4551 (define_insn "*mulqf3_addqf3_clobber"
4552 [(set (match_operand:QF 0 "r0r1_reg_operand" "=t,t,t,t")
4553 (mult:QF (match_operand:QF 1 "parallel_operand" "%S<>!V,q,S<>!V,q")
4554 (match_operand:QF 2 "parallel_operand" "q,S<>!V,S<>!V,q")))
4555 (set (match_operand:QF 3 "r2r3_reg_operand" "=u,u,u,u")
4556 (plus:QF (match_operand:QF 4 "parallel_operand" "%S<>!V,q,q,S<>!V")
4557 (match_operand:QF 5 "parallel_operand" "q,S<>!V,q,S<>!V")))
4558 (clobber (reg:CC_NOOV 21))]
4559 "TARGET_PARALLEL_MPY && valid_parallel_operands_6 (operands, QFmode)"
4560 "mpyf3\\t%2,%1,%0\\n||\\taddf3\\t%5,%4,%3"
4561 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
4562
4563
4564 ;
4565 ; MPYF/STF
4566 ;
4567
4568 (define_insn "*mulqf3_movqf_clobber"
4569 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q,q")
4570 (mult:QF (match_operand:QF 1 "parallel_operand" "%q,S<>")
4571 (match_operand:QF 2 "parallel_operand" "S<>,q")))
4572 (set (match_operand:QF 3 "par_ind_operand" "=S<>,S<>")
4573 (match_operand:QF 4 "ext_low_reg_operand" "q,q"))
4574 (clobber (reg:CC 21))]
4575 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QFmode)"
4576 "mpyf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3"
4577 [(set_attr "type" "binarycc,binarycc")])
4578
4579 ;
4580 ; MPYF/SUBF
4581 ;
4582
4583 (define_insn "*mulqf3_subqf3_clobber"
4584 [(set (match_operand:QF 0 "r0r1_reg_operand" "=t,t")
4585 (mult:QF (match_operand:QF 1 "parallel_operand" "S<>,q")
4586 (match_operand:QF 2 "parallel_operand" "q,S<>")))
4587 (set (match_operand:QF 3 "r2r3_reg_operand" "=u,u")
4588 (minus:QF (match_operand:QF 4 "parallel_operand" "S<>,q")
4589 (match_operand:QF 5 "parallel_operand" "q,S<>")))
4590 (clobber (reg:CC 21))]
4591 "TARGET_PARALLEL_MPY && valid_parallel_operands_6 (operands, QFmode)"
4592 "mpyf3\\t%2,%1,%0\\n||\\tsubf3\\t%5,%4,%3"
4593 [(set_attr "type" "binarycc,binarycc")])
4594
4595 ;
4596 ; MPYF/LDF 0
4597 ;
4598
4599 (define_insn "*mulqf3_clrqf_clobber"
4600 [(set (match_operand:QF 0 "r0r1_reg_operand" "=t")
4601 (mult:QF (match_operand:QF 1 "par_ind_operand" "%S<>")
4602 (match_operand:QF 2 "par_ind_operand" "S<>")))
4603 (set (match_operand:QF 3 "r2r3_reg_operand" "=u")
4604 (match_operand:QF 4 "fp_zero_operand" "G"))
4605 (clobber (reg:CC 21))]
4606 "TARGET_PARALLEL_MPY"
4607 "mpyf3\\t%2,%1,%0\\n||\\tsubf3\\t%3,%3,%3"
4608 [(set_attr "type" "binarycc")])
4609
4610 ;
4611 ; NEGF/STF
4612 ;
4613
4614 (define_insn "*negqf2_movqf_clobber"
4615 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
4616 (neg:QF (match_operand:QF 1 "par_ind_operand" "S<>")))
4617 (set (match_operand:QF 2 "par_ind_operand" "=S<>")
4618 (match_operand:QF 3 "ext_low_reg_operand" "q"))
4619 (clobber (reg:CC 21))]
4620 "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QFmode)"
4621 "negf\\t%1,%0\\n||\\tstf\\t%3,%2"
4622 [(set_attr "type" "binarycc")])
4623
4624 ;
4625 ; SUBF/STF
4626 ;
4627
4628 (define_insn "*subqf3_movqf_clobber"
4629 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
4630 (minus:QF (match_operand:QF 1 "ext_low_reg_operand" "q")
4631 (match_operand:QF 2 "par_ind_operand" "S<>")))
4632 (set (match_operand:QF 3 "par_ind_operand" "=S<>")
4633 (match_operand:QF 4 "ext_low_reg_operand" "q"))
4634 (clobber (reg:CC 21))]
4635 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QFmode)"
4636 "subf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3"
4637 [(set_attr "type" "binarycc")])
4638
4639 ;
4640 ; TOIEEE/STF
4641 ;
4642
4643 (define_insn "*toieee_movqf_clobber"
4644 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
4645 (unspec:QF [(match_operand:QF 1 "par_ind_operand" "S<>")] UNSPEC_TOIEEE))
4646 (set (match_operand:QF 2 "par_ind_operand" "=S<>")
4647 (match_operand:QF 3 "ext_low_reg_operand" "q"))
4648 (clobber (reg:CC 21))]
4649 "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QFmode)"
4650 "toieee\\t%1,%0\\n||\\tstf\\t%3,%2"
4651 [(set_attr "type" "binarycc")])
4652
4653 ;
4654 ; FRIEEE/STF
4655 ;
4656
4657 (define_insn "*frieee_movqf_clobber"
4658 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
4659 (unspec:QF [(match_operand:QF 1 "par_ind_operand" "S<>")] UNSPEC_FRIEEE))
4660 (set (match_operand:QF 2 "par_ind_operand" "=S<>")
4661 (match_operand:QF 3 "ext_low_reg_operand" "q"))
4662 (clobber (reg:CC 21))]
4663 "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QFmode)"
4664 "frieee\\t%1,%0\\n||\\tstf\\t%3,%2"
4665 [(set_attr "type" "binarycc")])
4666
4667 ;
4668 ; PARALLEL INTEGER INSTRUCTIONS
4669 ;
4670
4671 ;
4672 ; ABSI/STI
4673 ;
4674
4675 (define_insn "*absqi2_movqi_clobber"
4676 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4677 (abs:QI (match_operand:QI 1 "par_ind_operand" "S<>")))
4678 (set (match_operand:QI 2 "par_ind_operand" "=S<>")
4679 (match_operand:QI 3 "ext_low_reg_operand" "q"))
4680 (clobber (reg:CC_NOOV 21))]
4681 "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QImode)"
4682 "absi\\t%1,%0\\n||\\tsti\\t%3,%2"
4683 [(set_attr "type" "binarycc")])
4684
4685 ;
4686 ; ADDI/STI
4687 ;
4688
4689 (define_insn "*addqi3_movqi_clobber"
4690 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q,q")
4691 (plus:QI (match_operand:QI 1 "parallel_operand" "%q,S<>")
4692 (match_operand:QI 2 "parallel_operand" "S<>,q")))
4693 (set (match_operand:QI 3 "par_ind_operand" "=S<>,S<>")
4694 (match_operand:QI 4 "ext_low_reg_operand" "q,q"))
4695 (clobber (reg:CC 21))]
4696 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
4697 "addi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4698 [(set_attr "type" "binarycc,binarycc")])
4699
4700 ;
4701 ; AND/STI
4702 ;
4703
4704 (define_insn "*andqi3_movqi_clobber"
4705 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q,q")
4706 (and:QI (match_operand:QI 1 "parallel_operand" "%q,S<>")
4707 (match_operand:QI 2 "parallel_operand" "S<>,q")))
4708 (set (match_operand:QI 3 "par_ind_operand" "=S<>,S<>")
4709 (match_operand:QI 4 "ext_low_reg_operand" "q,q"))
4710 (clobber (reg:CC 21))]
4711 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
4712 "and3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4713 [(set_attr "type" "binarycc,binarycc")])
4714
4715 ;
4716 ; ASH(left)/STI
4717 ;
4718
4719 (define_insn "*ashlqi3_movqi_clobber"
4720 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4721 (ashift:QI (match_operand:QI 1 "par_ind_operand" "S<>")
4722 (match_operand:QI 2 "ext_low_reg_operand" "q")))
4723 (set (match_operand:QI 3 "par_ind_operand" "=S<>")
4724 (match_operand:QI 4 "ext_low_reg_operand" "q"))
4725 (clobber (reg:CC 21))]
4726 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
4727 "ash3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4728 [(set_attr "type" "binarycc")])
4729
4730 ;
4731 ; ASH(right)/STI
4732 ;
4733
4734 (define_insn "*ashrqi3_movqi_clobber"
4735 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4736 (ashiftrt:QI (match_operand:QI 1 "par_ind_operand" "S<>")
4737 (neg:QI (match_operand:QI 2 "ext_low_reg_operand" "q"))))
4738 (set (match_operand:QI 3 "par_ind_operand" "=S<>")
4739 (match_operand:QI 4 "ext_low_reg_operand" "q"))
4740 (clobber (reg:CC 21))]
4741 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
4742 "ash3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4743 [(set_attr "type" "binarycc")])
4744
4745 ;
4746 ; FIX/STI
4747 ;
4748
4749 (define_insn "*fixqfqi2_movqi_clobber"
4750 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4751 (fix:QI (match_operand:QF 1 "par_ind_operand" "S<>")))
4752 (set (match_operand:QI 2 "par_ind_operand" "=S<>")
4753 (match_operand:QI 3 "ext_low_reg_operand" "q"))
4754 (clobber (reg:CC 21))]
4755 "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QImode)"
4756 "fix\\t%1,%0\\n||\\tsti\\t%3,%2"
4757 [(set_attr "type" "binarycc")])
4758
4759 ;
4760 ; LSH(right)/STI
4761 ;
4762
4763 (define_insn "*lshrqi3_movqi_clobber"
4764 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4765 (lshiftrt:QI (match_operand:QI 1 "par_ind_operand" "S<>")
4766 (neg:QI (match_operand:QI 2 "ext_low_reg_operand" "q"))))
4767 (set (match_operand:QI 3 "par_ind_operand" "=S<>")
4768 (match_operand:QI 4 "ext_low_reg_operand" "q"))
4769 (clobber (reg:CC 21))]
4770 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
4771 "lsh3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4772 [(set_attr "type" "binarycc")])
4773
4774 ;
4775 ; MPYI/ADDI
4776 ;
4777
4778 (define_insn "*mulqi3_addqi3_clobber"
4779 [(set (match_operand:QI 0 "r0r1_reg_operand" "=t,t,t,t")
4780 (mult:QI (match_operand:QI 1 "parallel_operand" "%S<>!V,q,S<>!V,q")
4781 (match_operand:QI 2 "parallel_operand" "q,S<>!V,S<>!V,q")))
4782 (set (match_operand:QI 3 "r2r3_reg_operand" "=u,u,u,u")
4783 (plus:QI (match_operand:QI 4 "parallel_operand" "%S<>!V,q,q,S<>!V")
4784 (match_operand:QI 5 "parallel_operand" "q,S<>!V,q,S<>!V")))
4785 (clobber (reg:CC 21))]
4786 "TARGET_PARALLEL_MPY && TARGET_MPYI
4787 && valid_parallel_operands_6 (operands, QImode)"
4788 "mpyi3\\t%2,%1,%0\\n||\\taddi3\\t%5,%4,%3"
4789 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
4790
4791
4792 ;
4793 ; MPYI/STI
4794 ;
4795
4796 (define_insn "*mulqi3_movqi_clobber"
4797 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q,q")
4798 (mult:QI (match_operand:QI 1 "parallel_operand" "%q,S<>")
4799 (match_operand:QI 2 "parallel_operand" "S<>,q")))
4800 (set (match_operand:QI 3 "par_ind_operand" "=S<>,S<>")
4801 (match_operand:QI 4 "ext_low_reg_operand" "q,q"))
4802 (clobber (reg:CC 21))]
4803 "TARGET_PARALLEL && TARGET_MPYI
4804 && valid_parallel_operands_5 (operands, QImode)"
4805 "mpyi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4806 [(set_attr "type" "binarycc,binarycc")])
4807
4808 ;
4809 ; MPYI/SUBI
4810 ;
4811
4812 (define_insn "*mulqi3_subqi3_clobber"
4813 [(set (match_operand:QI 0 "r0r1_reg_operand" "=t,t")
4814 (mult:QI (match_operand:QI 1 "parallel_operand" "S<>,q")
4815 (match_operand:QI 2 "parallel_operand" "q,S<>")))
4816 (set (match_operand:QI 3 "r2r3_reg_operand" "=u,u")
4817 (minus:QI (match_operand:QI 4 "parallel_operand" "S<>,q")
4818 (match_operand:QI 5 "parallel_operand" "q,S<>")))
4819 (clobber (reg:CC 21))]
4820 "TARGET_PARALLEL_MPY && TARGET_MPYI
4821 && valid_parallel_operands_6 (operands, QImode)"
4822 "mpyi3\\t%2,%1,%0\\n||\\tsubi3\\t%5,%4,%3"
4823 [(set_attr "type" "binarycc,binarycc")])
4824
4825 ;
4826 ; MPYI/LDI 0
4827 ;
4828
4829 (define_insn "*mulqi3_clrqi_clobber"
4830 [(set (match_operand:QI 0 "r0r1_reg_operand" "=t")
4831 (mult:QI (match_operand:QI 1 "par_ind_operand" "%S<>")
4832 (match_operand:QI 2 "par_ind_operand" "S<>")))
4833 (set (match_operand:QI 3 "r2r3_reg_operand" "=u")
4834 (const_int 0))
4835 (clobber (reg:CC 21))]
4836 "TARGET_PARALLEL_MPY && TARGET_MPYI"
4837 "mpyi3\\t%2,%1,%0\\n||\\tsubi3\\t%3,%3,%3"
4838 [(set_attr "type" "binarycc")])
4839
4840 ;
4841 ; NEGI/STI
4842 ;
4843
4844 (define_insn "*negqi2_movqi_clobber"
4845 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4846 (neg:QI (match_operand:QI 1 "par_ind_operand" "S<>")))
4847 (set (match_operand:QI 2 "par_ind_operand" "=S<>")
4848 (match_operand:QI 3 "ext_low_reg_operand" "q"))
4849 (clobber (reg:CC 21))]
4850 "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QImode)"
4851 "negi\\t%1,%0\\n||\\tsti\\t%3,%2"
4852 [(set_attr "type" "binarycc")])
4853
4854 ;
4855 ; NOT/STI
4856 ;
4857
4858 (define_insn "*notqi2_movqi_clobber"
4859 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4860 (not:QI (match_operand:QI 1 "par_ind_operand" "S<>")))
4861 (set (match_operand:QI 2 "par_ind_operand" "=S<>")
4862 (match_operand:QI 3 "ext_low_reg_operand" "q"))
4863 (clobber (reg:CC 21))]
4864 "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QImode)"
4865 "not\\t%1,%0\\n||\\tsti\\t%3,%2"
4866 [(set_attr "type" "binarycc")])
4867
4868 ;
4869 ; OR/STI
4870 ;
4871
4872 (define_insn "*iorqi3_movqi_clobber"
4873 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q,q")
4874 (ior:QI (match_operand:QI 1 "parallel_operand" "%q,S<>")
4875 (match_operand:QI 2 "parallel_operand" "S<>,q")))
4876 (set (match_operand:QI 3 "par_ind_operand" "=S<>,S<>")
4877 (match_operand:QI 4 "ext_low_reg_operand" "q,q"))
4878 (clobber (reg:CC 21))]
4879 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
4880 "or3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4881 [(set_attr "type" "binarycc,binarycc")])
4882
4883 ;
4884 ; SUBI/STI
4885 ;
4886
4887 (define_insn "*subqi3_movqi_clobber"
4888 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4889 (minus:QI (match_operand:QI 1 "par_ind_operand" "S<>")
4890 (match_operand:QI 2 "ext_low_reg_operand" "q")))
4891 (set (match_operand:QI 3 "par_ind_operand" "=S<>")
4892 (match_operand:QI 4 "ext_low_reg_operand" "q"))
4893 (clobber (reg:CC 21))]
4894 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
4895 "subi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4896 [(set_attr "type" "binarycc")])
4897
4898 ;
4899 ; XOR/STI
4900 ;
4901
4902 (define_insn "*xorqi3_movqi_clobber"
4903 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q,q")
4904 (xor:QI (match_operand:QI 1 "parallel_operand" "%q,S<>")
4905 (match_operand:QI 2 "parallel_operand" "S<>,q")))
4906 (set (match_operand:QI 3 "par_ind_operand" "=S<>,S<>")
4907 (match_operand:QI 4 "ext_low_reg_operand" "q,q"))
4908 (clobber (reg:CC 21))]
4909 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
4910 "xor3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4911 [(set_attr "type" "binarycc,binarycc")])
4912
4913 ;
4914 ; BRANCH/CALL INSTRUCTIONS
4915 ;
4916
4917 ;
4918 ; Branch instructions
4919 ;
4920 (define_insn "*b"
4921 [(set (pc) (if_then_else (match_operator 0 "comparison_operator"
4922 [(reg:CC 21) (const_int 0)])
4923 (label_ref (match_operand 1 "" ""))
4924 (pc)))]
4925 ""
4926 "*
4927 return c4x_output_cbranch (\"b%0\", insn);"
4928 [(set_attr "type" "jmpc")])
4929
4930 (define_insn "*b_rev"
4931 [(set (pc) (if_then_else (match_operator 0 "comparison_operator"
4932 [(reg:CC 21) (const_int 0)])
4933 (pc)
4934 (label_ref (match_operand 1 "" ""))))]
4935 ""
4936 "*
4937 return c4x_output_cbranch (\"b%I0\", insn);"
4938 [(set_attr "type" "jmpc")])
4939
4940 (define_insn "*b_noov"
4941 [(set (pc) (if_then_else (match_operator 0 "comparison_operator"
4942 [(reg:CC_NOOV 21) (const_int 0)])
4943 (label_ref (match_operand 1 "" ""))
4944 (pc)))]
4945 "GET_CODE (operands[0]) != LE
4946 && GET_CODE (operands[0]) != GE
4947 && GET_CODE (operands[0]) != LT
4948 && GET_CODE (operands[0]) != GT"
4949 "*
4950 return c4x_output_cbranch (\"b%0\", insn);"
4951 [(set_attr "type" "jmpc")])
4952
4953 (define_insn "*b_noov_rev"
4954 [(set (pc) (if_then_else (match_operator 0 "comparison_operator"
4955 [(reg:CC_NOOV 21) (const_int 0)])
4956 (pc)
4957 (label_ref (match_operand 1 "" ""))))]
4958 "GET_CODE (operands[0]) != LE
4959 && GET_CODE (operands[0]) != GE
4960 && GET_CODE (operands[0]) != LT
4961 && GET_CODE (operands[0]) != GT"
4962 "*
4963 return c4x_output_cbranch (\"b%I0\", insn);"
4964 [(set_attr "type" "jmpc")])
4965
4966 (define_expand "beq"
4967 [(set (pc) (if_then_else (eq (match_dup 1) (const_int 0))
4968 (label_ref (match_operand 0 "" ""))
4969 (pc)))]
4970 ""
4971 "operands[1] = c4x_gen_compare_reg (EQ, c4x_compare_op0, c4x_compare_op1);")
4972
4973 (define_expand "bne"
4974 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
4975 (label_ref (match_operand 0 "" ""))
4976 (pc)))]
4977 ""
4978 "operands[1] = c4x_gen_compare_reg (NE, c4x_compare_op0, c4x_compare_op1);")
4979
4980 (define_expand "blt"
4981 [(set (pc) (if_then_else (lt (match_dup 1) (const_int 0))
4982 (label_ref (match_operand 0 "" ""))
4983 (pc)))]
4984 ""
4985 "operands[1] = c4x_gen_compare_reg (LT, c4x_compare_op0, c4x_compare_op1);
4986 if (operands[1] == NULL_RTX) FAIL;")
4987
4988 (define_expand "bltu"
4989 [(set (pc) (if_then_else (ltu (match_dup 1) (const_int 0))
4990 (label_ref (match_operand 0 "" ""))
4991 (pc)))]
4992 ""
4993 "operands[1] = c4x_gen_compare_reg (LTU, c4x_compare_op0, c4x_compare_op1);")
4994
4995 (define_expand "bgt"
4996 [(set (pc) (if_then_else (gt (match_dup 1) (const_int 0))
4997 (label_ref (match_operand 0 "" ""))
4998 (pc)))]
4999 ""
5000 "operands[1] = c4x_gen_compare_reg (GT, c4x_compare_op0, c4x_compare_op1);
5001 if (operands[1] == NULL_RTX) FAIL;")
5002
5003 (define_expand "bgtu"
5004 [(set (pc) (if_then_else (gtu (match_dup 1) (const_int 0))
5005 (label_ref (match_operand 0 "" ""))
5006 (pc)))]
5007 ""
5008 "operands[1] = c4x_gen_compare_reg (GTU, c4x_compare_op0, c4x_compare_op1);")
5009
5010 (define_expand "ble"
5011 [(set (pc) (if_then_else (le (match_dup 1) (const_int 0))
5012 (label_ref (match_operand 0 "" ""))
5013 (pc)))]
5014 ""
5015 "operands[1] = c4x_gen_compare_reg (LE, c4x_compare_op0, c4x_compare_op1);
5016 if (operands[1] == NULL_RTX) FAIL;")
5017
5018 (define_expand "bleu"
5019 [(set (pc) (if_then_else (leu (match_dup 1) (const_int 0))
5020 (label_ref (match_operand 0 "" ""))
5021 (pc)))]
5022 ""
5023 "operands[1] = c4x_gen_compare_reg (LEU, c4x_compare_op0, c4x_compare_op1);")
5024
5025 (define_expand "bge"
5026 [(set (pc) (if_then_else (ge (match_dup 1) (const_int 0))
5027 (label_ref (match_operand 0 "" ""))
5028 (pc)))]
5029 ""
5030 "operands[1] = c4x_gen_compare_reg (GE, c4x_compare_op0, c4x_compare_op1);
5031 if (operands[1] == NULL_RTX) FAIL;")
5032
5033 (define_expand "bgeu"
5034 [(set (pc) (if_then_else (geu (match_dup 1) (const_int 0))
5035 (label_ref (match_operand 0 "" ""))
5036 (pc)))]
5037 ""
5038 "operands[1] = c4x_gen_compare_reg (GEU, c4x_compare_op0, c4x_compare_op1);")
5039
5040 (define_insn "*b_reg"
5041 [(set (pc) (match_operand:QI 0 "reg_operand" "r"))]
5042 ""
5043 "bu%#\\t%0"
5044 [(set_attr "type" "jump")])
5045
5046 (define_expand "indirect_jump"
5047 [(set (pc) (match_operand:QI 0 "reg_operand" ""))]
5048 ""
5049 "")
5050
5051 (define_insn "tablejump"
5052 [(set (pc) (match_operand:QI 0 "src_operand" "r"))
5053 (use (label_ref (match_operand 1 "" "")))]
5054 ""
5055 "bu%#\\t%0"
5056 [(set_attr "type" "jump")])
5057
5058 ;
5059 ; CALL
5060 ;
5061 (define_insn "*call_c3x"
5062 [(call (mem:QI (match_operand:QI 0 "call_address_operand" "Ur"))
5063 (match_operand:QI 1 "general_operand" ""))
5064 (clobber (reg:QI 31))]
5065 ;; Operand 1 not really used on the C4x. The C30 doesn't have reg 31.
5066
5067 "TARGET_C3X"
5068 "call%U0\\t%C0"
5069 [(set_attr "type" "call")])
5070
5071 ; LAJ requires R11 (31) for the return address
5072 (define_insn "*laj"
5073 [(call (mem:QI (match_operand:QI 0 "call_address_operand" "Ur"))
5074 (match_operand:QI 1 "general_operand" ""))
5075 (clobber (reg:QI 31))]
5076 ;; Operand 1 not really used on the C4x.
5077
5078 "! TARGET_C3X"
5079 "*
5080 if (final_sequence)
5081 return c4x_check_laj_p (insn)
5082 ? \"nop\\n\\tlaj%U0\\t%C0\" : \"laj%U0\\t%C0\";
5083 else
5084 return \"call%U0\\t%C0\";"
5085 [(set_attr "type" "laj")])
5086
5087 (define_expand "call"
5088 [(parallel [(call (match_operand:QI 0 "" "")
5089 (match_operand:QI 1 "general_operand" ""))
5090 (clobber (reg:QI 31))])]
5091 ""
5092 "
5093 {
5094 if (GET_CODE (operands[0]) == MEM
5095 && ! call_address_operand (XEXP (operands[0], 0), Pmode))
5096 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
5097 force_reg (Pmode, XEXP (operands[0], 0)));
5098 }")
5099
5100 (define_insn "nodb_call"
5101 [(call (mem:QI (match_operand:QI 0 "call_address_operand" "Ur"))
5102 (const_int 0))]
5103 ""
5104 "call%U0\\t%C0"
5105 [(set_attr "type" "call")])
5106
5107 (define_insn "*callv_c3x"
5108 [(set (match_operand 0 "" "=r")
5109 (call (mem:QI (match_operand:QI 1 "call_address_operand" "Ur"))
5110 (match_operand:QI 2 "general_operand" "")))
5111 (clobber (reg:QI 31))]
5112 ;; Operand 0 and 2 not really used for the C4x.
5113 ;; The C30 doesn't have reg 31.
5114
5115 "TARGET_C3X"
5116 "call%U1\\t%C1"
5117 [(set_attr "type" "call")])
5118
5119 ; LAJ requires R11 (31) for the return address
5120 (define_insn "*lajv"
5121 [(set (match_operand 0 "" "=r")
5122 (call (mem:QI (match_operand:QI 1 "call_address_operand" "Ur"))
5123 (match_operand:QI 2 "general_operand" "")))
5124 (clobber (reg:QI 31))]
5125 ;; Operand 0 and 2 not really used in the C30 instruction.
5126
5127 "! TARGET_C3X"
5128 "*
5129 if (final_sequence)
5130 return c4x_check_laj_p (insn)
5131 ? \"nop\\n\\tlaj%U1\\t%C1\" : \"laj%U1\\t%C1\";
5132 else
5133 return \"call%U1\\t%C1\";"
5134 [(set_attr "type" "laj")])
5135
5136 (define_expand "call_value"
5137 [(parallel [(set (match_operand 0 "" "")
5138 (call (match_operand:QI 1 "" "")
5139 (match_operand:QI 2 "general_operand" "")))
5140 (clobber (reg:QI 31))])]
5141 ""
5142 "
5143 {
5144 if (GET_CODE (operands[0]) == MEM
5145 && ! call_address_operand (XEXP (operands[1], 0), Pmode))
5146 operands[0] = gen_rtx_MEM (GET_MODE (operands[1]),
5147 force_reg (Pmode, XEXP (operands[1], 0)));
5148 }")
5149
5150 (define_insn "return"
5151 [(return)]
5152 "! c4x_null_epilogue_p ()"
5153 "rets"
5154 [(set_attr "type" "rets")])
5155
5156 (define_insn "return_from_epilogue"
5157 [(return)]
5158 "reload_completed && ! c4x_interrupt_function_p ()"
5159 "rets"
5160 [(set_attr "type" "rets")])
5161
5162 (define_insn "return_from_interrupt_epilogue"
5163 [(return)]
5164 "reload_completed && c4x_interrupt_function_p ()"
5165 "reti"
5166 [(set_attr "type" "rets")])
5167
5168 (define_insn "*return_cc"
5169 [(set (pc)
5170 (if_then_else (match_operator 0 "comparison_operator"
5171 [(reg:CC 21) (const_int 0)])
5172 (return)
5173 (pc)))]
5174 "! c4x_null_epilogue_p ()"
5175 "rets%0"
5176 [(set_attr "type" "rets")])
5177
5178 (define_insn "*return_cc_noov"
5179 [(set (pc)
5180 (if_then_else (match_operator 0 "comparison_operator"
5181 [(reg:CC_NOOV 21) (const_int 0)])
5182 (return)
5183 (pc)))]
5184 "GET_CODE (operands[0]) != LE
5185 && GET_CODE (operands[0]) != GE
5186 && GET_CODE (operands[0]) != LT
5187 && GET_CODE (operands[0]) != GT
5188 && ! c4x_null_epilogue_p ()"
5189 "rets%0"
5190 [(set_attr "type" "rets")])
5191
5192 (define_insn "*return_cc_inverse"
5193 [(set (pc)
5194 (if_then_else (match_operator 0 "comparison_operator"
5195 [(reg:CC 21) (const_int 0)])
5196 (pc)
5197 (return)))]
5198 "! c4x_null_epilogue_p ()"
5199 "rets%I0"
5200 [(set_attr "type" "rets")])
5201
5202 (define_insn "*return_cc_noov_inverse"
5203 [(set (pc)
5204 (if_then_else (match_operator 0 "comparison_operator"
5205 [(reg:CC_NOOV 21) (const_int 0)])
5206 (pc)
5207 (return)))]
5208 "GET_CODE (operands[0]) != LE
5209 && GET_CODE (operands[0]) != GE
5210 && GET_CODE (operands[0]) != LT
5211 && GET_CODE (operands[0]) != GT
5212 && ! c4x_null_epilogue_p ()"
5213 "rets%I0"
5214 [(set_attr "type" "rets")])
5215
5216 (define_insn "jump"
5217 [(set (pc) (label_ref (match_operand 0 "" "")))]
5218 ""
5219 "br%#\\t%l0"
5220 [(set_attr "type" "jump")])
5221
5222 (define_insn "trap"
5223 [(trap_if (const_int 1) (const_int 31))]
5224 ""
5225 "trapu\\t31"
5226 [(set_attr "type" "call")])
5227
5228 (define_expand "conditional_trap"
5229 [(trap_if (match_operand 0 "comparison_operator" "")
5230 (match_operand 1 "const_int_operand" ""))]
5231 ""
5232 "{
5233 enum rtx_code code = GET_CODE (operands[1]);
5234 rtx ccreg = c4x_gen_compare_reg (code, c4x_compare_op0, c4x_compare_op1);
5235 if (ccreg == NULL_RTX) FAIL;
5236 if (GET_MODE (ccreg) == CCmode)
5237 emit_insn (gen_cond_trap_cc (operands[0], operands[1]));
5238 else
5239 emit_insn (gen_cond_trap_cc_noov (operands[0], operands[1]));
5240 DONE;}")
5241
5242 (define_insn "cond_trap_cc"
5243 [(trap_if (match_operator 0 "comparison_operator"
5244 [(reg:CC 21) (const_int 0)])
5245 (match_operand 1 "const_int_operand" ""))]
5246 ""
5247 "trap%0\\t31"
5248 [(set_attr "type" "call")])
5249
5250 (define_insn "cond_trap_cc_noov"
5251 [(trap_if (match_operator 0 "comparison_operator"
5252 [(reg:CC_NOOV 21) (const_int 0)])
5253 (match_operand 1 "const_int_operand" ""))]
5254 "GET_CODE (operands[0]) != LE
5255 && GET_CODE (operands[0]) != GE
5256 && GET_CODE (operands[0]) != LT
5257 && GET_CODE (operands[0]) != GT"
5258 "trap%0\\t31"
5259 [(set_attr "type" "call")])
5260
5261 ;
5262 ; DBcond
5263 ;
5264 ; Note we have to emit a dbu instruction if there are no delay slots
5265 ; to fill.
5266 ; Also note that GCC will try to reverse a loop to see if it can
5267 ; utilize this instruction. However, if there are more than one
5268 ; memory reference in the loop, it cannot guarantee that reversing
5269 ; the loop will work :( (see check_dbra_loop() in loop.c)
5270 ; Note that the C3x only decrements the 24 LSBs of the address register
5271 ; and the 8 MSBs are untouched. The C4x uses all 32-bits. We thus
5272 ; have an option to disable this instruction.
5273 (define_insn "*db"
5274 [(set (pc)
5275 (if_then_else (ne (match_operand:QI 0 "addr_reg_operand" "+a,?*d,??*r,!m")
5276 (const_int 0))
5277 (label_ref (match_operand 1 "" ""))
5278 (pc)))
5279 (set (match_dup 0)
5280 (plus:QI (match_dup 0)
5281 (const_int -1)))
5282 (use (reg:QI 20))
5283 (clobber (reg:CC_NOOV 21))]
5284 "TARGET_DB && TARGET_LOOP_UNSIGNED"
5285 "*
5286 if (which_alternative == 0)
5287 return \"dbu%#\\t%0,%l1\";
5288 else if (which_alternative == 1)
5289 return c4x_output_cbranch (\"subi\\t1,%0\\n\\tbge\", insn);
5290 else if (which_alternative == 2)
5291 return c4x_output_cbranch (\"subi\\t1,%0\\n\\tcmpi\\t0,%0\\n\\tbge\", insn);
5292 else
5293 return c4x_output_cbranch (\"push\\tr0\\n\\tldi\\t%0,r0\\n\\tsubi\\t1,r0\\n\\tsti\\tr0,%0\\n\\tpop\\tr0\\n\\tbhs\", insn);
5294 "
5295 [(set_attr "type" "db,jmpc,jmpc,jmpc")])
5296
5297 (define_insn "*db_noclobber"
5298 [(set (pc)
5299 (if_then_else (ne (match_operand:QI 0 "addr_reg_operand" "+a")
5300 (const_int 0))
5301 (label_ref (match_operand 1 "" ""))
5302 (pc)))
5303 (set (match_dup 0)
5304 (plus:QI (match_dup 0)
5305 (const_int -1)))]
5306 "reload_completed && TARGET_DB && TARGET_LOOP_UNSIGNED"
5307 "dbu%#\\t%0,%l1"
5308 [(set_attr "type" "db")])
5309
5310 (define_split
5311 [(set (pc)
5312 (if_then_else (ne (match_operand:QI 0 "addr_reg_operand" "")
5313 (const_int 0))
5314 (label_ref (match_operand 1 "" ""))
5315 (pc)))
5316 (set (match_dup 0)
5317 (plus:QI (match_dup 0)
5318 (const_int -1)))
5319 (use (reg:QI 20))
5320 (clobber (reg:CC_NOOV 21))]
5321 "reload_completed && TARGET_DB && TARGET_LOOP_UNSIGNED"
5322 [(parallel [(set (pc)
5323 (if_then_else (ne (match_dup 0)
5324 (const_int 0))
5325 (label_ref (match_dup 1))
5326 (pc)))
5327 (set (match_dup 0)
5328 (plus:QI (match_dup 0)
5329 (const_int -1)))])]
5330 "")
5331
5332
5333 ; This insn is used for some loop tests, typically loops reversed when
5334 ; strength reduction is used. It is actually created when the instruction
5335 ; combination phase combines the special loop test. Since this insn
5336 ; is both a jump insn and has an output, it must deal with its own
5337 ; reloads, hence the `m' constraints.
5338
5339 ; The C4x does the decrement and then compares the result against zero.
5340 ; It branches if the result was greater than or equal to zero.
5341 ; In the RTL the comparison and decrement are assumed to happen
5342 ; at the same time so we bias the iteration counter with by -1
5343 ; when we make the test.
5344 (define_insn "decrement_and_branch_until_zero"
5345 [(set (pc)
5346 (if_then_else (ge (plus:QI (match_operand:QI 0 "addr_reg_operand" "+a,?*d,??*r,!m")
5347 (const_int -1))
5348 (const_int 0))
5349 (label_ref (match_operand 1 "" ""))
5350 (pc)))
5351 (set (match_dup 0)
5352 (plus:QI (match_dup 0)
5353 (const_int -1)))
5354 (use (reg:QI 20))
5355 (clobber (reg:CC_NOOV 21))]
5356 "TARGET_DB && (find_reg_note (insn, REG_NONNEG, 0) || TARGET_LOOP_UNSIGNED)"
5357 "*
5358 if (which_alternative == 0)
5359 return \"dbu%#\\t%0,%l1\";
5360 else if (which_alternative == 1)
5361 return c4x_output_cbranch (\"subi\\t1,%0\\n\\tbge\", insn);
5362 else if (which_alternative == 2)
5363 return c4x_output_cbranch (\"subi\\t1,%0\\n\\tcmpi\\t0,%0\\n\\tbge\", insn);
5364 else
5365 return c4x_output_cbranch (\"push\\tr0\\n\\tldi\\t%0,r0\\n\\tsubi\\t1,r0\\n\\tsti\\tr0,%0\\n\\tpop\\tr0\\n\\tbhs\", insn);
5366 "
5367 [(set_attr "type" "db,jmpc,jmpc,jmpc")])
5368
5369 (define_insn "*decrement_and_branch_until_zero_noclobber"
5370 [(set (pc)
5371 (if_then_else (ge (plus:QI (match_operand:QI 0 "addr_reg_operand" "+a")
5372 (const_int -1))
5373 (const_int 0))
5374 (label_ref (match_operand 1 "" ""))
5375 (pc)))
5376 (set (match_dup 0)
5377 (plus:QI (match_dup 0)
5378 (const_int -1)))]
5379 "reload_completed && TARGET_DB && TARGET_LOOP_UNSIGNED"
5380 "dbu%#\\t%0,%l1"
5381 [(set_attr "type" "db")])
5382
5383 (define_split
5384 [(set (pc)
5385 (if_then_else (ge (plus:QI (match_operand:QI 0 "addr_reg_operand" "")
5386 (const_int -1))
5387 (const_int 0))
5388 (label_ref (match_operand 1 "" ""))
5389 (pc)))
5390 (set (match_dup 0)
5391 (plus:QI (match_dup 0)
5392 (const_int -1)))
5393 (use (reg:QI 20))
5394 (clobber (reg:CC_NOOV 21))]
5395 "reload_completed && TARGET_DB && TARGET_LOOP_UNSIGNED"
5396 [(parallel [(set (pc)
5397 (if_then_else (ge (plus:QI (match_dup 0)
5398 (const_int -1))
5399 (const_int 0))
5400 (label_ref (match_dup 1))
5401 (pc)))
5402 (set (match_dup 0)
5403 (plus:QI (match_dup 0)
5404 (const_int -1)))])]
5405 "")
5406
5407 ;
5408 ; MISC INSTRUCTIONS
5409 ;
5410
5411 ;
5412 ; NOP
5413 ;
5414 (define_insn "nop"
5415 [(const_int 0)]
5416 ""
5417 "nop")
5418 ; Default to misc type attr.
5419
5420 (define_insn "return_indirect_internal"
5421 [(return)
5422 (use (match_operand:QI 0 "reg_operand" ""))]
5423 "reload_completed"
5424 "bu%#\\t%0"
5425 [(set_attr "type" "jump")])
5426
5427 (define_expand "prologue"
5428 [(const_int 1)]
5429 ""
5430 "c4x_expand_prologue (); DONE;")
5431
5432 (define_expand "epilogue"
5433 [(const_int 1)]
5434 ""
5435 "c4x_expand_epilogue (); DONE;")
5436
5437 ;
5438 ; RPTB
5439 ;
5440 (define_insn "rptb_top"
5441 [(use (label_ref (match_operand 0 "" "")))
5442 (use (label_ref (match_operand 1 "" "")))
5443 (clobber (reg:QI 25))
5444 (clobber (reg:QI 26))]
5445 ""
5446 "*
5447 return ! final_sequence && c4x_rptb_rpts_p (insn, operands[0])
5448 ? \"rpts\\trc\" : \"rptb%#\\t%l1-1\";
5449 "
5450 [(set_attr "type" "repeat_top")])
5451
5452 (define_insn "rpts_top"
5453 [(unspec [(use (label_ref (match_operand 0 "" "")))
5454 (use (label_ref (match_operand 1 "" "")))] UNSPEC_RPTS)
5455 (clobber (reg:QI 25))
5456 (clobber (reg:QI 26))]
5457 ""
5458 "*
5459 return ! final_sequence && c4x_rptb_rpts_p (insn, operands[0])
5460 ? \"rpts\\trc\" : \"rptb%#\\t%l1-1\";
5461 "
5462 [(set_attr "type" "repeat")])
5463
5464 ; This pattern needs to be emitted at the start of the loop to
5465 ; say that RS and RE are loaded.
5466 (define_insn "rptb_init"
5467 [(unspec [(match_operand:QI 0 "register_operand" "va")] UNSPEC_RPTB_INIT)
5468 (clobber (reg:QI 25))
5469 (clobber (reg:QI 26))]
5470 ""
5471 ""
5472 [(set_attr "type" "repeat")])
5473
5474
5475 ; operand 0 is the loop count pseudo register
5476 ; operand 1 is the number of loop iterations or 0 if it is unknown
5477 ; operand 2 is the maximum number of loop iterations
5478 ; operand 3 is the number of levels of enclosed loops
5479 (define_expand "doloop_begin"
5480 [(use (match_operand 0 "register_operand" ""))
5481 (use (match_operand:QI 1 "const_int_operand" ""))
5482 (use (match_operand:QI 2 "const_int_operand" ""))
5483 (use (match_operand:QI 3 "const_int_operand" ""))]
5484 ""
5485 "if (INTVAL (operands[3]) > 1 || ! TARGET_RPTB)
5486 FAIL;
5487 emit_insn (gen_rptb_init (operands[0]));
5488 DONE;
5489 ")
5490
5491
5492 ; The RS (25) and RE (26) registers must be unviolate from the top of the loop
5493 ; to here.
5494 (define_insn "rptb_end"
5495 [(set (pc)
5496 (if_then_else (ge (match_operand:QI 0 "register_operand" "+v,?a,!*d,!*x*k,!m")
5497 (const_int 0))
5498 (label_ref (match_operand 1 "" ""))
5499 (pc)))
5500 (set (match_dup 0)
5501 (plus:QI (match_dup 0)
5502 (const_int -1)))
5503 (use (reg:QI 25))
5504 (use (reg:QI 26))
5505 (use (reg:QI 20))
5506 (clobber (reg:CC_NOOV 21))]
5507 ""
5508 "*
5509 if (which_alternative == 0)
5510 return c4x_rptb_nop_p (insn) ? \"nop\" : \"\";
5511 else if (which_alternative == 1 && TARGET_DB)
5512 return \"dbu%#\\t%0,%l1\";
5513 else if (which_alternative == 2)
5514 return c4x_output_cbranch (\"subi\\t1,%0\\n\\tbge\", insn);
5515 else if (which_alternative == 3 || (which_alternative == 1 && ! TARGET_DB))
5516 return c4x_output_cbranch (\"subi\\t1,%0\\n\\tcmpi\\t0,%0\\n\\tbge\", insn);
5517 else
5518 return c4x_output_cbranch (\"push\\tr0\\n\\tldi\\t%0,r0\\n\\tsubi\\t1,r0\\n\\tsti\\tr0,%0\\n\\tpop\\tr0\\n\\tbhs\", insn);
5519 "
5520 [(set_attr "type" "repeat,db,jmpc,jmpc,jmpc")])
5521
5522 (define_split
5523 [(set (pc)
5524 (if_then_else (ge (match_operand:QI 0 "addr_reg_operand" "")
5525 (const_int 0))
5526 (label_ref (match_operand 1 "" ""))
5527 (pc)))
5528 (set (match_dup 0)
5529 (plus:QI (match_dup 0)
5530 (const_int -1)))
5531 (use (match_operand:QI 2 "const_int_operand" ""))
5532 (use (match_operand:QI 3 "const_int_operand" ""))
5533 (use (match_operand:QI 4 "const_int_operand" ""))
5534 (use (reg:QI 25))
5535 (use (reg:QI 26))
5536 (use (reg:QI 20))
5537 (clobber (reg:CC_NOOV 21))]
5538 "reload_completed"
5539 [(parallel [(set (pc)
5540 (if_then_else (ge (match_dup 0)
5541 (const_int 0))
5542 (label_ref (match_dup 1))
5543 (pc)))
5544 (set (match_dup 0)
5545 (plus:QI (match_dup 0)
5546 (const_int -1)))])]
5547 "")
5548
5549 ; operand 0 is the loop count pseudo register
5550 ; operand 1 is the number of loop iterations or 0 if it is unknown
5551 ; operand 2 is the maximum number of loop iterations
5552 ; operand 3 is the number of levels of enclosed loops
5553 ; operand 4 is the label to jump to at the top of the loop
5554 (define_expand "doloop_end"
5555 [(use (match_operand 0 "register_operand" ""))
5556 (use (match_operand:QI 1 "const_int_operand" ""))
5557 (use (match_operand:QI 2 "const_int_operand" ""))
5558 (use (match_operand:QI 3 "const_int_operand" ""))
5559 (use (label_ref (match_operand 4 "" "")))]
5560 ""
5561 "if (! TARGET_LOOP_UNSIGNED
5562 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > ((unsigned) 1 << 31))
5563 FAIL;
5564 if (INTVAL (operands[3]) > 1 || ! TARGET_RPTB)
5565 {
5566 /* The C30 maximum iteration count for DB is 2^24. */
5567 if (! TARGET_DB)
5568 FAIL;
5569 emit_jump_insn (gen_decrement_and_branch_until_zero (operands[0],
5570 operands[4]));
5571 DONE;
5572 }
5573 emit_jump_insn (gen_rptb_end (operands[0], operands[4]));
5574 DONE;
5575 ")
5576
5577 (define_expand "decrement_and_branch_on_count"
5578 [(parallel [(set (pc)
5579 (if_then_else (ge (match_operand:QI 0 "register_operand" "")
5580 (const_int 0))
5581 (label_ref (match_operand 1 "" ""))
5582 (pc)))
5583 (set (match_dup 0)
5584 (plus:QI (match_dup 0)
5585 (const_int -1)))
5586 (use (reg:QI 25))
5587 (use (reg:QI 26))
5588 (clobber (reg:CC_NOOV 21))])]
5589 "0"
5590 "")
5591
5592 (define_expand "movstrqi_small"
5593 [(parallel [(set (mem:BLK (match_operand:BLK 0 "src_operand" ""))
5594 (mem:BLK (match_operand:BLK 1 "src_operand" "")))
5595 (use (match_operand:QI 2 "immediate_operand" ""))
5596 (use (match_operand:QI 3 "immediate_operand" ""))
5597 (clobber (match_operand:QI 4 "ext_low_reg_operand" ""))])]
5598 ""
5599 "
5600 {
5601 rtx src, dst, tmp;
5602 rtx src_mem, dst_mem;
5603 int len;
5604 int i;
5605
5606 dst = operands[0];
5607 src = operands[1];
5608 len = INTVAL (operands[2]);
5609 tmp = operands[4];
5610
5611 src_mem = gen_rtx_MEM (QImode, src);
5612 dst_mem = gen_rtx_MEM (QImode, dst);
5613
5614 if (TARGET_PARALLEL)
5615 {
5616 emit_insn (gen_movqi (tmp, src_mem));
5617 emit_insn (gen_addqi3_noclobber (src, src, const1_rtx));
5618 for (i = 1; i < len; i++)
5619 {
5620 emit_insn (gen_movqi_parallel (tmp, src_mem, dst_mem, tmp));
5621 emit_insn (gen_addqi3_noclobber (src, src, const1_rtx));
5622 emit_insn (gen_addqi3_noclobber (dst, dst, const1_rtx));
5623 }
5624 emit_insn (gen_movqi (dst_mem, tmp));
5625 emit_insn (gen_addqi3_noclobber (dst, dst, const1_rtx));
5626 }
5627 else
5628 {
5629 for (i = 0; i < len; i++)
5630 {
5631 emit_insn (gen_movqi (tmp, src_mem));
5632 emit_insn (gen_movqi (dst_mem, tmp));
5633 emit_insn (gen_addqi3_noclobber (src, src, const1_rtx));
5634 emit_insn (gen_addqi3_noclobber (dst, dst, const1_rtx));
5635 }
5636 }
5637 DONE;
5638 }
5639 ")
5640
5641
5642 ;
5643 ; BLOCK MOVE
5644 ; We should probably get RC loaded when using RPTB automagically...
5645 ; There's probably no need to call _memcpy() if we don't get
5646 ; an immediate operand for the size. We could do a better job here
5647 ; than most memcpy() implementations.
5648 ; operand 2 is the number of bytes
5649 ; operand 3 is the shared alignment
5650 ; operand 4 is a scratch register
5651
5652 (define_insn "movstrqi_large"
5653 [(set (mem:BLK (match_operand:QI 0 "addr_reg_operand" "a"))
5654 (mem:BLK (match_operand:QI 1 "addr_reg_operand" "a")))
5655 (use (match_operand:QI 2 "immediate_operand" "i"))
5656 (use (match_operand:QI 3 "immediate_operand" ""))
5657 (clobber (match_operand:QI 4 "ext_low_reg_operand" "=&q"))
5658 (clobber (match_scratch:QI 5 "=0"))
5659 (clobber (match_scratch:QI 6 "=1"))
5660 (clobber (reg:QI 25))
5661 (clobber (reg:QI 26))
5662 (clobber (reg:QI 27))]
5663 ""
5664 "*
5665 {
5666 int i;
5667 int len = INTVAL (operands[2]);
5668
5669 output_asm_insn (\"ldiu\\t*%1++,%4\", operands);
5670 if (len < 8)
5671 {
5672 for (i = 1; i < len; i++)
5673 {
5674 output_asm_insn (\"sti\\t%4,*%0++\", operands);
5675 output_asm_insn (\"|| ldi\\t*%1++,%4\", operands);
5676 }
5677 }
5678 else
5679 {
5680 if (TARGET_RPTS_CYCLES (len))
5681 {
5682 output_asm_insn (\"rpts\\t%2-2\", operands);
5683 output_asm_insn (\"sti\\t%4,*%0++\", operands);
5684 output_asm_insn (\"|| ldi\\t*%1++,%4\", operands);
5685 }
5686 else
5687 {
5688 output_asm_insn (\"ldiu\\t%2-2,rc\", operands);
5689 output_asm_insn (\"rptb\\t$+1\", operands);
5690 output_asm_insn (\"sti\\t%4,*%0++\", operands);
5691 output_asm_insn (\"|| ldi\\t*%1++,%4\", operands);
5692 }
5693 }
5694 return \"sti\\t%4,*%0++\";
5695 }"
5696 [(set_attr "type" "multi")])
5697
5698 ; Operand 2 is the count, operand 3 is the alignment.
5699 (define_expand "movstrqi"
5700 [(parallel [(set (mem:BLK (match_operand:BLK 0 "src_operand" ""))
5701 (mem:BLK (match_operand:BLK 1 "src_operand" "")))
5702 (use (match_operand:QI 2 "immediate_operand" ""))
5703 (use (match_operand:QI 3 "immediate_operand" ""))])]
5704 ""
5705 "
5706 {
5707 rtx tmp;
5708 if (GET_CODE (operands[2]) != CONST_INT
5709 || INTVAL (operands[2]) > 32767
5710 || INTVAL (operands[2]) <= 0)
5711 {
5712 FAIL; /* Try to call _memcpy */
5713 }
5714
5715 operands[0] = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
5716 operands[1] = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
5717 tmp = gen_reg_rtx (QImode);
5718 /* Disabled because of reload problems. */
5719 if (0 && INTVAL (operands[2]) < 8)
5720 emit_insn (gen_movstrqi_small (operands[0], operands[1], operands[2],
5721 operands[3], tmp));
5722 else
5723 {
5724 emit_insn (gen_movstrqi_large (operands[0], operands[1], operands[2],
5725 operands[3], tmp));
5726 }
5727 DONE;
5728 }")
5729
5730
5731 (define_insn "*cmpstrqi"
5732 [(set (match_operand:QI 0 "ext_reg_operand" "=d")
5733 (compare:QI (mem:BLK (match_operand:QI 1 "addr_reg_operand" "+a"))
5734 (mem:BLK (match_operand:QI 2 "addr_reg_operand" "+a"))))
5735 (use (match_operand:QI 3 "immediate_operand" "i"))
5736 (use (match_operand:QI 4 "immediate_operand" ""))
5737 (clobber (match_operand:QI 5 "std_reg_operand" "=&c"))
5738 (clobber (reg:QI 21))]
5739 ""
5740 "*
5741 {
5742 output_asm_insn (\"ldi\\t%3-1,%5\", operands);
5743 output_asm_insn (\"$1:\tsubi3\\t*%1++,*%2++,%0\", operands);
5744 output_asm_insn (\"dbeq\\t%5,$1\", operands);
5745 return \"\";
5746 }")
5747
5748 (define_expand "cmpstrqi"
5749 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
5750 (compare:QI (match_operand:BLK 1 "general_operand" "")
5751 (match_operand:BLK 2 "general_operand" "")))
5752 (use (match_operand:QI 3 "immediate_operand" ""))
5753 (use (match_operand:QI 4 "immediate_operand" ""))
5754 (clobber (match_dup 5))
5755 (clobber (reg:QI 21))])]
5756 ""
5757 "
5758 {
5759 if (GET_CODE (operands[3]) != CONST_INT
5760 || INTVAL (operands[3]) > 32767
5761 || INTVAL (operands[3]) <= 0)
5762 {
5763 FAIL;
5764 }
5765 operands[1] = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
5766 operands[2] = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
5767 operands[5] = gen_reg_rtx (QImode);
5768 }")
5769
5770 ;
5771 ; TWO OPERAND LONG DOUBLE INSTRUCTIONS
5772 ;
5773
5774 (define_expand "movhf"
5775 [(set (match_operand:HF 0 "src_operand" "")
5776 (match_operand:HF 1 "src_operand" ""))]
5777 ""
5778 "if (c4x_emit_move_sequence (operands, HFmode))
5779 DONE;")
5780
5781 (define_insn "*movhf_noclobber_reg"
5782 [(set (match_operand:HF 0 "reg_operand" "=h")
5783 (match_operand:HF 1 "src_operand" "Hh"))]
5784 "GET_CODE (operands[1]) != MEM"
5785 "ldfu\\t%1,%0"
5786 [(set_attr "type" "unary")])
5787
5788 (define_insn "*movhf_noclobber"
5789 [(set (match_operand:HF 0 "dst_operand" "=h,m")
5790 (match_operand:HF 1 "src_operand" "Hm,h"))]
5791 "reg_operand (operands[0], HFmode) ^ reg_operand (operands[1], HFmode)"
5792 "#"
5793 [(set_attr "type" "multi,multi")])
5794
5795 (define_insn "*movhf_test"
5796 [(set (reg:CC 21)
5797 (compare:CC (match_operand:HF 1 "reg_operand" "h")
5798 (const_int 0)))
5799 (clobber (match_scratch:HF 0 "=h"))]
5800 ""
5801 "ldf\\t%1,%0"
5802 [(set_attr "type" "unarycc")])
5803
5804 (define_insn "*movhf_set"
5805 [(set (reg:CC 21)
5806 (compare:CC (match_operand:HF 1 "reg_operand" "h")
5807 (match_operand:HF 2 "fp_zero_operand" "G")))
5808 (set (match_operand:HF 0 "reg_operand" "=h")
5809 (match_dup 1))]
5810 ""
5811 "ldf\\t%1,%0"
5812 [(set_attr "type" "unarycc")])
5813
5814 (define_split
5815 [(set (match_operand:HF 0 "reg_operand" "")
5816 (match_operand:HF 1 "memory_operand" ""))]
5817 "reload_completed"
5818 [(set (match_dup 0) (float_extend:HF (match_dup 2)))
5819 (set (match_dup 0) (unspec:HF [(subreg:QI (match_dup 0) 0)
5820 (match_dup 3)] UNSPEC_LOADHF_INT))]
5821 "operands[2] = c4x_operand_subword (operands[1], 0, 1, HFmode);
5822 operands[3] = c4x_operand_subword (operands[1], 1, 1, HFmode);
5823 PUT_MODE (operands[2], QFmode);
5824 PUT_MODE (operands[3], QImode);")
5825
5826 (define_split
5827 [(set (match_operand:HF 0 "reg_operand" "")
5828 (match_operand:HF 1 "const_operand" ""))]
5829 "reload_completed && 0"
5830 [(set (match_dup 0) (float_extend:HF (match_dup 2)))
5831 (set (match_dup 0) (unspec:HF [(subreg:QI (match_dup 0) 0)
5832 (match_dup 3)] UNSPEC_LOADHF_INT))]
5833 "operands[2] = c4x_operand_subword (operands[1], 0, 1, HFmode);
5834 operands[3] = c4x_operand_subword (operands[1], 1, 1, HFmode);
5835 PUT_MODE (operands[2], QFmode);
5836 PUT_MODE (operands[3], QImode);")
5837
5838 (define_split
5839 [(set (match_operand:HF 0 "memory_operand" "")
5840 (match_operand:HF 1 "reg_operand" ""))]
5841 "reload_completed"
5842 [(set (match_dup 2) (float_truncate:QF (match_dup 1)))
5843 (set (match_dup 3) (unspec:QI [(match_dup 1)] UNSPEC_STOREHF_INT))]
5844 "operands[2] = c4x_operand_subword (operands[0], 0, 1, HFmode);
5845 operands[3] = c4x_operand_subword (operands[0], 1, 1, HFmode);
5846 PUT_MODE (operands[2], QFmode);
5847 PUT_MODE (operands[3], QImode);")
5848
5849 (define_insn "*loadhf_float"
5850 [(set (match_operand:HF 0 "reg_operand" "=h")
5851 (float_extend:HF (match_operand:QF 1 "src_operand" "fHm")))]
5852 ""
5853 "ldfu\\t%1,%0"
5854 [(set_attr "type" "unary")])
5855
5856 (define_insn "*loadhf_int"
5857 [(set (match_operand:HF 0 "reg_operand" "+h")
5858 (unspec:HF [(subreg:QI (match_dup 0) 0)
5859 (match_operand:QI 1 "src_operand" "rIm")] UNSPEC_LOADHF_INT))]
5860 ""
5861 "ldiu\\t%1,%0"
5862 [(set_attr "type" "unary")])
5863
5864 (define_insn "*storehf_float"
5865 [(set (match_operand:QF 0 "memory_operand" "=m")
5866 (float_truncate:QF (match_operand:HF 1 "reg_operand" "h")))]
5867 ""
5868 "stf\\t%1,%0"
5869 [(set_attr "type" "store")])
5870
5871 (define_insn "*storehf_int"
5872 [(set (match_operand:QI 0 "memory_operand" "=m")
5873 (unspec:QI [(match_operand:HF 1 "reg_operand" "h")] UNSPEC_STOREHF_INT))]
5874 ""
5875 "sti\\t%1,%0"
5876 [(set_attr "type" "store")])
5877
5878 (define_insn "extendqfhf2"
5879 [(set (match_operand:HF 0 "reg_operand" "=h")
5880 (float_extend:HF (match_operand:QF 1 "reg_operand" "h")))]
5881 ""
5882 "ldfu\\t%1,%0"
5883 [(set_attr "type" "unarycc")])
5884
5885 (define_insn "trunchfqf2"
5886 [(set (match_operand:QF 0 "reg_operand" "=h")
5887 (float_truncate:QF (match_operand:HF 1 "reg_operand" "0")))
5888 (clobber (reg:CC 21))]
5889 ""
5890 "andn\\t0ffh,%0"
5891 [(set_attr "type" "unarycc")])
5892
5893 ;
5894 ; PUSH/POP
5895 ;
5896 (define_insn "pushhf"
5897 [(set (mem:HF (pre_inc:QI (reg:QI 20)))
5898 (match_operand:HF 0 "reg_operand" "h"))]
5899 ""
5900 "#"
5901 [(set_attr "type" "multi")])
5902
5903 (define_split
5904 [(set (mem:HF (pre_inc:QI (reg:QI 20)))
5905 (match_operand:HF 0 "reg_operand" ""))]
5906 "reload_completed"
5907 [(set (mem:QF (pre_inc:QI (reg:QI 20)))
5908 (float_truncate:QF (match_dup 0)))
5909 (set (mem:QI (pre_inc:QI (reg:QI 20)))
5910 (unspec:QI [(match_dup 0)] UNSPEC_STOREHF_INT))]
5911 "")
5912
5913 (define_insn "pushhf_trunc"
5914 [(set (mem:QF (pre_inc:QI (reg:QI 20)))
5915 (float_truncate:QF (match_operand:HF 0 "reg_operand" "h")))]
5916 ""
5917 "pushf\\t%0"
5918 [(set_attr "type" "push")])
5919
5920 (define_insn "pushhf_int"
5921 [(set (mem:QI (pre_inc:QI (reg:QI 20)))
5922 (unspec:QI [(match_operand:HF 0 "reg_operand" "h")] UNSPEC_STOREHF_INT))]
5923 ""
5924 "push\\t%0"
5925 [(set_attr "type" "push")])
5926
5927 ; we can not use this because the popf will destroy the low 8 bits
5928 ;(define_insn "pophf"
5929 ; [(set (match_operand:HF 0 "reg_operand" "=h")
5930 ; (mem:HF (post_dec:QI (reg:QI 20))))
5931 ; (clobber (reg:CC 21))]
5932 ; ""
5933 ; "#"
5934 ; [(set_attr "type" "multi")])
5935
5936 (define_split
5937 [(set (match_operand:HF 0 "reg_operand" "")
5938 (mem:HF (post_dec:QI (reg:QI 20))))
5939 (clobber (reg:CC 21))]
5940 "reload_completed"
5941 [(parallel [(set (match_operand:HF 0 "reg_operand" "=h")
5942 (float_extend:HF (mem:QF (post_dec:QI (reg:QI 20)))))
5943 (clobber (reg:CC 21))])
5944 (parallel [(set (match_dup 0)
5945 (unspec:HF [(subreg:QI (match_dup 0) 0)
5946 (mem:QI (post_dec:QI (reg:QI 20)))] UNSPEC_LOADHF_INT))
5947 (clobber (reg:CC 21))])]
5948 "")
5949
5950 (define_insn "*pophf_int"
5951 [(set (match_operand:HF 0 "reg_operand" "+h")
5952 (unspec:HF [(subreg:QI (match_dup 0) 0)
5953 (mem:QI (post_dec:QI (reg:QI 20)))] UNSPEC_LOADHF_INT))
5954 (clobber (reg:CC 21))]
5955 ""
5956 "pop\\t%0"
5957 [(set_attr "type" "pop")])
5958
5959 (define_insn "*pophf_float"
5960 [(set (match_operand:HF 0 "reg_operand" "=h")
5961 (float_extend:HF (mem:QF (post_dec:QI (reg:QI 20)))))
5962 (clobber (reg:CC 21))]
5963 ""
5964 "popf\\t%0"
5965 [(set_attr "type" "pop")])
5966
5967 ;
5968 ; FIX
5969 ;
5970 (define_expand "fixuns_trunchfqi2"
5971 [(parallel [(set (match_dup 2)
5972 (fix:QI (match_operand:HF 1 "reg_or_const_operand" "hH")))
5973 (clobber (reg:CC 21))])
5974 (parallel [(set (match_dup 3)
5975 (minus:HF (match_dup 1) (match_dup 5)))
5976 (clobber (reg:CC_NOOV 21))])
5977 (parallel [(set (reg:CC 21)
5978 (compare:CC (fix:QI (match_dup 3))
5979 (const_int 0)))
5980 (set (match_dup 4)
5981 (fix:QI (match_dup 3)))])
5982 (parallel [(set (match_dup 4) (unspec:QI [(match_dup 2)] UNSPEC_LDIV))
5983 (use (reg:CC 21))])
5984 (set (match_operand:QI 0 "reg_operand" "=r") (match_dup 4))]
5985 ""
5986 "operands[2] = gen_reg_rtx (QImode);
5987 operands[3] = gen_reg_rtx (HFmode);
5988 operands[4] = gen_reg_rtx (QImode);
5989 operands[5] = gen_reg_rtx (HFmode);
5990 emit_move_insn (operands[5], CONST_DOUBLE_ATOF (\"4294967296.0\", HFmode));")
5991
5992 (define_expand "fix_trunchfqi2"
5993 [(parallel [(set (match_dup 2)
5994 (fix:QI (match_operand:HF 1 "reg_or_const_operand" "")))
5995 (clobber (reg:CC 21))])
5996 (parallel [(set (match_dup 3) (neg:HF (match_dup 1)))
5997 (clobber (reg:CC_NOOV 21))])
5998 (parallel [(set (match_dup 4) (fix:QI (match_dup 3)))
5999 (clobber (reg:CC 21))])
6000 (parallel [(set (reg:CC_NOOV 21)
6001 (compare:CC_NOOV (neg:QI (match_dup 4)) (const_int 0)))
6002 (set (match_dup 5) (neg:QI (match_dup 4)))])
6003 (set (match_dup 2)
6004 (if_then_else:QI (le (reg:CC 21) (const_int 0))
6005 (match_dup 5)
6006 (match_dup 2)))
6007 (set (match_operand:QI 0 "reg_operand" "=r") (match_dup 2))]
6008 ""
6009 "if (TARGET_FAST_FIX)
6010 {
6011 emit_insn (gen_fixhfqi_clobber (operands[0], operands[1]));
6012 DONE;
6013 }
6014 operands[2] = gen_reg_rtx (QImode);
6015 operands[3] = gen_reg_rtx (HFmode);
6016 operands[4] = gen_reg_rtx (QImode);
6017 operands[5] = gen_reg_rtx (QImode);
6018 ")
6019
6020 (define_insn "*fixhfqi_set"
6021 [(set (reg:CC 21)
6022 (compare:CC (fix:QI (match_operand:HF 1 "reg_or_const_operand" "hH"))
6023 (const_int 0)))
6024 (set (match_operand:QI 0 "ext_reg_operand" "=d")
6025 (fix:QI (match_dup 1)))]
6026 ""
6027 "fix\\t%1,%0"
6028 [(set_attr "type" "unarycc")])
6029
6030 (define_insn "fixhfqi_clobber"
6031 [(set (match_operand:QI 0 "reg_operand" "=dc")
6032 (fix:QI (match_operand:HF 1 "reg_or_const_operand" "hH")))
6033 (clobber (reg:CC 21))]
6034 ""
6035 "fix\\t%1,%0"
6036 [(set_attr "type" "unarycc")])
6037
6038 (define_expand "fix_trunchfhi2"
6039 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
6040 (fix:HI (match_operand:HF 1 "reg_operand" "")))
6041 (clobber (reg:CC 21))])]
6042 ""
6043 "c4x_emit_libcall (fix_trunchfhi2_libfunc, FIX, HImode, HFmode, 2, operands);
6044 DONE;")
6045
6046 (define_expand "fixuns_trunchfhi2"
6047 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
6048 (unsigned_fix:HI (match_operand:HF 1 "reg_operand" "")))
6049 (clobber (reg:CC 21))])]
6050 ""
6051 "c4x_emit_libcall (fixuns_trunchfhi2_libfunc, UNSIGNED_FIX,
6052 HImode, HFmode, 2, operands);
6053 DONE;")
6054
6055 ;
6056 ; ABSF
6057 ;
6058 (define_expand "abshf2"
6059 [(parallel [(set (match_operand:HF 0 "reg_operand" "")
6060 (abs:HF (match_operand:HF 1 "reg_or_const_operand" "")))
6061 (clobber (reg:CC_NOOV 21))])]
6062 ""
6063 "")
6064
6065 (define_insn "*abshf2_clobber"
6066 [(set (match_operand:HF 0 "reg_operand" "=h")
6067 (abs:HF (match_operand:HF 1 "reg_or_const_operand" "hH")))
6068 (clobber (reg:CC_NOOV 21))]
6069 ""
6070 "absf\\t%1,%0"
6071 [(set_attr "type" "unarycc")])
6072
6073 (define_insn "*abshf2_test"
6074 [(set (reg:CC_NOOV 21)
6075 (compare:CC_NOOV (abs:HF (match_operand:HF 1 "reg_operand" "h"))
6076 (match_operand:HF 2 "fp_zero_operand" "G")))
6077 (clobber (match_scratch:HF 0 "=h"))]
6078 ""
6079 "absf\\t%1,%0"
6080 [(set_attr "type" "unarycc")])
6081
6082 (define_insn "*abshf2_set"
6083 [(set (reg:CC_NOOV 21)
6084 (compare:CC_NOOV (abs:HF (match_operand:HF 1 "reg_or_const_operand" "hH"))
6085 (match_operand:HF 2 "fp_zero_operand" "G")))
6086 (set (match_operand:HF 0 "reg_operand" "=h")
6087 (abs:HF (match_dup 1)))]
6088
6089 ""
6090 "absf\\t%1,%0"
6091 [(set_attr "type" "unarycc")])
6092
6093 ;
6094 ; NEGF
6095 ;
6096 (define_expand "neghf2"
6097 [(parallel [(set (match_operand:HF 0 "reg_operand" "")
6098 (neg:HF (match_operand:HF 1 "reg_or_const_operand" "")))
6099 (clobber (reg:CC_NOOV 21))])]
6100 ""
6101 "")
6102
6103 (define_insn "*neghf2_clobber"
6104 [(set (match_operand:HF 0 "reg_operand" "=h")
6105 (neg:HF (match_operand:HF 1 "reg_or_const_operand" "hH")))
6106 (clobber (reg:CC_NOOV 21))]
6107 ""
6108 "negf\\t%1,%0"
6109 [(set_attr "type" "unarycc")])
6110
6111 (define_insn "*neghf2_test"
6112 [(set (reg:CC_NOOV 21)
6113 (compare:CC_NOOV (neg:HF (match_operand:HF 1 "reg_or_const_operand" "hH"))
6114 (match_operand:HF 2 "fp_zero_operand" "G")))
6115 (clobber (match_scratch:HF 0 "=h"))]
6116 ""
6117 "negf\\t%1,%0"
6118 [(set_attr "type" "unarycc")])
6119
6120 (define_insn "*neghf2_set"
6121 [(set (reg:CC_NOOV 21)
6122 (compare:CC_NOOV (neg:HF (match_operand:HF 1 "reg_or_const_operand" "hH"))
6123 (match_operand:HF 2 "fp_zero_operand" "G")))
6124 (set (match_operand:HF 0 "reg_operand" "=h")
6125 (neg:HF (match_dup 1)))]
6126 ""
6127 "negf\\t%1,%0"
6128 [(set_attr "type" "unarycc")])
6129
6130 ;
6131 ; RCPF
6132 ;
6133 (define_insn "*rcpfhf_clobber"
6134 [(set (match_operand:HF 0 "reg_operand" "=h")
6135 (unspec:HF [(match_operand:HF 1 "reg_or_const_operand" "hH")] UNSPEC_RCPF))
6136 (clobber (reg:CC_NOOV 21))]
6137 "! TARGET_C3X"
6138 "rcpf\\t%1,%0"
6139 [(set_attr "type" "unarycc")])
6140
6141 ;
6142 ; RSQRF
6143 ;
6144 (define_insn "*rsqrfhf_clobber"
6145 [(set (match_operand:HF 0 "reg_operand" "=h")
6146 (unspec:HF [(match_operand:HF 1 "reg_or_const_operand" "hH")] UNSPEC_RSQRF))
6147 (clobber (reg:CC_NOOV 21))]
6148 "! TARGET_C3X"
6149 "rsqrf\\t%1,%0"
6150 [(set_attr "type" "unarycc")])
6151
6152 ;
6153 ; RNDF
6154 ;
6155 (define_insn "*rndhf_clobber"
6156 [(set (match_operand:HF 0 "reg_operand" "=h")
6157 (unspec:HF [(match_operand:HF 1 "reg_or_const_operand" "hH")] UNSPEC_RND))
6158 (clobber (reg:CC_NOOV 21))]
6159 "! TARGET_C3X"
6160 "rnd\\t%1,%0"
6161 [(set_attr "type" "unarycc")])
6162
6163
6164 ; Inlined float square root for C4x
6165 (define_expand "sqrthf2_inline"
6166 [(parallel [(set (match_dup 2)
6167 (unspec:HF [(match_operand:HF 1 "reg_operand" "")] UNSPEC_RSQRF))
6168 (clobber (reg:CC_NOOV 21))])
6169 (parallel [(set (match_dup 3) (mult:HF (match_dup 5) (match_dup 1)))
6170 (clobber (reg:CC_NOOV 21))])
6171 (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 3)))
6172 (clobber (reg:CC_NOOV 21))])
6173 (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 4)))
6174 (clobber (reg:CC_NOOV 21))])
6175 (parallel [(set (match_dup 4) (minus:HF (match_dup 6) (match_dup 4)))
6176 (clobber (reg:CC_NOOV 21))])
6177 (parallel [(set (match_dup 2) (mult:HF (match_dup 2) (match_dup 4)))
6178 (clobber (reg:CC_NOOV 21))])
6179 (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 3)))
6180 (clobber (reg:CC_NOOV 21))])
6181 (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 4)))
6182 (clobber (reg:CC_NOOV 21))])
6183 (parallel [(set (match_dup 4) (minus:HF (match_dup 6) (match_dup 4)))
6184 (clobber (reg:CC_NOOV 21))])
6185 (parallel [(set (match_dup 2) (mult:HF (match_dup 2) (match_dup 4)))
6186 (clobber (reg:CC_NOOV 21))])
6187 (parallel [(set (match_operand:HF 0 "reg_operand" "")
6188 (mult:HF (match_dup 2) (match_dup 1)))
6189 (clobber (reg:CC_NOOV 21))])]
6190 "! TARGET_C3X"
6191 "
6192 operands[2] = gen_reg_rtx (HFmode);
6193 operands[3] = gen_reg_rtx (HFmode);
6194 operands[4] = gen_reg_rtx (HFmode);
6195 operands[5] = CONST_DOUBLE_ATOF (\"0.5\", HFmode);
6196 operands[6] = CONST_DOUBLE_ATOF (\"1.5\", HFmode);
6197 ")
6198
6199
6200 (define_expand "sqrthf2"
6201 [(parallel [(set (match_operand:HF 0 "reg_operand" "")
6202 (sqrt:HF (match_operand:HF 1 "reg_operand" "")))
6203 (clobber (reg:CC 21))])]
6204 "! TARGET_C3X && TARGET_INLINE"
6205 "emit_insn (gen_sqrthf2_inline (operands[0], operands[1]));
6206 DONE;")
6207
6208 ;
6209 ; THREE OPERAND LONG DOUBLE INSTRUCTIONS
6210 ;
6211
6212 ;
6213 ; ADDF
6214 ;
6215 (define_insn "addhf3"
6216 [(set (match_operand:HF 0 "reg_operand" "=h,?h")
6217 (plus:HF (match_operand:HF 1 "reg_operand" "%0,h")
6218 (match_operand:HF 2 "reg_or_const_operand" "H,h")))
6219 (clobber (reg:CC_NOOV 21))]
6220 ""
6221 "@
6222 addf\\t%2,%0
6223 addf3\\t%2,%1,%0"
6224 [(set_attr "type" "binarycc,binarycc")])
6225
6226 ;
6227 ; SUBF
6228 ;
6229 (define_insn "subhf3"
6230 [(set (match_operand:HF 0 "reg_operand" "=h,h,?h")
6231 (minus:HF (match_operand:HF 1 "reg_or_const_operand" "0,H,h")
6232 (match_operand:HF 2 "reg_or_const_operand" "H,0,h")))
6233 (clobber (reg:CC_NOOV 21))]
6234 ""
6235 "@
6236 subf\\t%2,%0
6237 subrf\\t%1,%0
6238 subf3\\t%2,%1,%0"
6239 [(set_attr "type" "binarycc,binarycc,binarycc")])
6240
6241 ;
6242 ; MULF
6243 ;
6244 ; The C3x MPYF only uses 24-bit precision while the C4x uses 32-bit precision.
6245 ;
6246 (define_expand "mulhf3"
6247 [(parallel [(set (match_operand:HF 0 "reg_operand" "=h")
6248 (mult:HF (match_operand:HF 1 "reg_operand" "h")
6249 (match_operand:HF 2 "reg_operand" "h")))
6250 (clobber (reg:CC_NOOV 21))])]
6251 "! TARGET_C3X"
6252 "")
6253
6254 (define_insn "*mulhf3_c40"
6255 [(set (match_operand:HF 0 "reg_operand" "=h,?h")
6256 (mult:HF (match_operand:HF 1 "reg_operand" "%0,h")
6257 (match_operand:HF 2 "reg_or_const_operand" "hH,h")))
6258 (clobber (reg:CC_NOOV 21))]
6259 ""
6260 "@
6261 mpyf\\t%2,%0
6262 mpyf3\\t%2,%1,%0"
6263 [(set_attr "type" "binarycc,binarycc")])
6264
6265 ;
6266 ; CMPF
6267 ;
6268 (define_expand "cmphf"
6269 [(set (reg:CC 21)
6270 (compare:CC (match_operand:HF 0 "reg_operand" "")
6271 (match_operand:HF 1 "reg_or_const_operand" "")))]
6272 ""
6273 "c4x_compare_op0 = operands[0];
6274 c4x_compare_op1 = operands[1];
6275 DONE;")
6276
6277 (define_insn "*cmphf"
6278 [(set (reg:CC 21)
6279 (compare:CC (match_operand:HF 0 "reg_operand" "h")
6280 (match_operand:HF 1 "reg_or_const_operand" "hH")))]
6281 ""
6282 "cmpf\\t%1,%0"
6283 [(set_attr "type" "compare")])
6284
6285 (define_insn "*cmphf_noov"
6286 [(set (reg:CC_NOOV 21)
6287 (compare:CC_NOOV (match_operand:HF 0 "reg_operand" "h")
6288 (match_operand:HF 1 "reg_or_const_operand" "hH")))]
6289 ""
6290 "cmpf\\t%1,%0"
6291 [(set_attr "type" "compare")])
6292
6293 ; Inlined float divide for C4x
6294 (define_expand "divhf3_inline"
6295 [(parallel [(set (match_dup 3)
6296 (unspec:HF [(match_operand:HF 2 "reg_operand" "")] UNSPEC_RCPF))
6297 (clobber (reg:CC_NOOV 21))])
6298 (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 3)))
6299 (clobber (reg:CC_NOOV 21))])
6300 (parallel [(set (match_dup 4) (minus:HF (match_dup 5) (match_dup 4)))
6301 (clobber (reg:CC_NOOV 21))])
6302 (parallel [(set (match_dup 3) (mult:HF (match_dup 3) (match_dup 4)))
6303 (clobber (reg:CC_NOOV 21))])
6304 (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 3)))
6305 (clobber (reg:CC_NOOV 21))])
6306 (parallel [(set (match_dup 4) (minus:HF (match_dup 5) (match_dup 4)))
6307 (clobber (reg:CC_NOOV 21))])
6308 (parallel [(set (match_dup 3) (mult:HF (match_dup 3) (match_dup 4)))
6309 (clobber (reg:CC_NOOV 21))])
6310 (parallel [(set (match_operand:HF 0 "reg_operand" "")
6311 (mult:HF (match_operand:HF 1 "reg_operand" "")
6312 (match_dup 3)))
6313 (clobber (reg:CC_NOOV 21))])]
6314 "! TARGET_C3X"
6315 "
6316 operands[3] = gen_reg_rtx (HFmode);
6317 operands[4] = gen_reg_rtx (HFmode);
6318 operands[5] = CONST2_RTX (HFmode);
6319 ")
6320
6321 (define_expand "divhf3"
6322 [(parallel [(set (match_operand:HF 0 "reg_operand" "")
6323 (div:HF (match_operand:HF 1 "reg_operand" "")
6324 (match_operand:HF 2 "reg_operand" "")))
6325 (clobber (reg:CC 21))])]
6326 "! TARGET_C3X && TARGET_INLINE"
6327 "emit_insn (gen_divhf3_inline (operands[0], operands[1], operands[2]));
6328 DONE;")
6329
6330
6331 ;
6332 ; TWO OPERAND LONG LONG INSTRUCTIONS
6333 ;
6334
6335 (define_insn "*movhi_stik"
6336 [(set (match_operand:HI 0 "memory_operand" "=m")
6337 (match_operand:HI 1 "stik_const_operand" "K"))]
6338 "! TARGET_C3X"
6339 "#"
6340 [(set_attr "type" "multi")])
6341
6342 ; We could load some constants using define_splits for the C30
6343 ; in the large memory model---these would emit shift and or insns.
6344 (define_expand "movhi"
6345 [(set (match_operand:HI 0 "src_operand" "")
6346 (match_operand:HI 1 "src_operand" ""))]
6347 ""
6348 "if (c4x_emit_move_sequence (operands, HImode))
6349 DONE;")
6350
6351 ; The constraints for movhi must include 'r' if we don't
6352 ; restrict HImode regnos to start on an even number, since
6353 ; we can get RC, R8 allocated as a pair. We want more
6354 ; votes for FP_REGS so we use dr as the constraints.
6355 (define_insn "*movhi_noclobber"
6356 [(set (match_operand:HI 0 "dst_operand" "=dr,m")
6357 (match_operand:HI 1 "src_operand" "drIm,r"))]
6358 "reg_operand (operands[0], HImode)
6359 || reg_operand (operands[1], HImode)"
6360 "#"
6361 [(set_attr "type" "multi,multi")])
6362
6363 ; This will fail miserably if the destination register is used in the
6364 ; source memory address.
6365 ; The usual strategy in this case is to swap the order of insns we emit,
6366 ; however, this will fail if we have an autoincrement memory address.
6367 ; For example:
6368 ; ldi *ar0++, ar0
6369 ; ldi *ar0++, ar1
6370 ;
6371 ; We could convert this to
6372 ; ldi *ar0(1), ar1
6373 ; ldi *ar0, ar0
6374 ;
6375 ; However, things are likely to be very screwed up if we get this.
6376
6377 (define_split
6378 [(set (match_operand:HI 0 "dst_operand" "")
6379 (match_operand:HI 1 "src_operand" ""))]
6380 "reload_completed
6381 && (reg_operand (operands[0], HImode)
6382 || reg_operand (operands[1], HImode)
6383 || stik_const_operand (operands[1], HImode))"
6384 [(set (match_dup 2) (match_dup 4))
6385 (set (match_dup 3) (match_dup 5))]
6386 "operands[2] = c4x_operand_subword (operands[0], 0, 1, HImode);
6387 operands[3] = c4x_operand_subword (operands[0], 1, 1, HImode);
6388 operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
6389 operands[5] = c4x_operand_subword (operands[1], 1, 1, HImode);
6390 if (reg_overlap_mentioned_p (operands[2], operands[5]))
6391 {
6392 /* Swap order of move insns. */
6393 rtx tmp;
6394 tmp = operands[2];
6395 operands[2] =operands[3];
6396 operands[3] = tmp;
6397 tmp = operands[4];
6398 operands[4] =operands[5];
6399 operands[5] = tmp;
6400 }")
6401
6402
6403 (define_insn "extendqihi2"
6404 [(set (match_operand:HI 0 "reg_operand" "=dc")
6405 (sign_extend:HI (match_operand:QI 1 "src_operand" "rIm")))
6406 (clobber (reg:CC 21))]
6407 ""
6408 "#"
6409 [(set_attr "type" "multi")])
6410
6411 (define_split
6412 [(set (match_operand:HI 0 "reg_operand" "")
6413 (sign_extend:HI (match_operand:QI 1 "src_operand" "")))
6414 (clobber (reg:CC 21))]
6415 "reload_completed && TARGET_C3X"
6416 [(set (match_dup 2) (match_dup 1))
6417 (set (match_dup 3) (match_dup 2))
6418 (parallel [(set (match_dup 3) (ashiftrt:QI (match_dup 3) (const_int 31)))
6419 (clobber (reg:CC 21))])]
6420 "operands[2] = c4x_operand_subword (operands[0], 0, 0, HImode);
6421 operands[3] = c4x_operand_subword (operands[0], 1, 0, HImode);")
6422
6423 (define_split
6424 [(set (match_operand:HI 0 "reg_operand" "")
6425 (sign_extend:HI (match_operand:QI 1 "src_operand" "")))
6426 (clobber (reg:CC 21))]
6427 "reload_completed && ! TARGET_C3X"
6428 [(set (match_dup 2) (match_dup 1))
6429 (parallel [(set (match_dup 3) (ashiftrt:QI (match_dup 2) (const_int 31)))
6430 (clobber (reg:CC 21))])]
6431 "operands[2] = c4x_operand_subword (operands[0], 0, 0, HImode);
6432 operands[3] = c4x_operand_subword (operands[0], 1, 0, HImode);")
6433
6434 (define_insn "zero_extendqihi2"
6435 [(set (match_operand:HI 0 "reg_operand" "=?dc")
6436 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "rm")))
6437 (clobber (reg:CC 21))]
6438 ""
6439 "#"
6440 [(set_attr "type" "multi")])
6441
6442 ; If operand0 and operand1 are the same register we don't need
6443 ; the first set.
6444 (define_split
6445 [(set (match_operand:HI 0 "reg_operand" "")
6446 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "")))
6447 (clobber (reg:CC 21))]
6448 "reload_completed"
6449 [(set (match_dup 2) (match_dup 1))
6450 (set (match_dup 3) (const_int 0))]
6451 "operands[2] = c4x_operand_subword (operands[0], 0, 0, HImode);
6452 operands[3] = c4x_operand_subword (operands[0], 1, 0, HImode);")
6453
6454 ;
6455 ; PUSH/POP
6456 ;
6457 (define_insn "*pushhi"
6458 [(set (mem:HI (pre_inc:QI (reg:QI 20)))
6459 (match_operand:HI 0 "reg_operand" "r"))]
6460 ""
6461 "#"
6462 [(set_attr "type" "multi")])
6463
6464 (define_split
6465 [(set (mem:HI (pre_inc:QI (reg:QI 20)))
6466 (match_operand:HI 0 "reg_operand" ""))]
6467 "reload_completed"
6468 [(set (mem:QI (pre_inc:QI (reg:QI 20))) (match_dup 2))
6469 (set (mem:QI (pre_inc:QI (reg:QI 20))) (match_dup 3))]
6470 "operands[2] = c4x_operand_subword (operands[0], 0, 0, HImode);
6471 operands[3] = c4x_operand_subword (operands[0], 1, 0, HImode);")
6472
6473 (define_insn "*pophi"
6474 [(set (match_operand:HI 0 "reg_operand" "=r")
6475 (mem:HI (post_dec:QI (reg:QI 20))))
6476 (clobber (reg:CC 21))]
6477 ""
6478 "#"
6479 [(set_attr "type" "multi")])
6480
6481 (define_split
6482 [(set (match_operand:HI 0 "reg_operand" "")
6483 (mem:HI (pre_inc:QI (reg:QI 20))))]
6484 "reload_completed"
6485 [(set (match_dup 2) (mem:QI (pre_inc:QI (reg:QI 20))))
6486 (set (match_dup 3) (mem:QI (pre_inc:QI (reg:QI 20))))]
6487 "operands[2] = c4x_operand_subword (operands[0], 0, 0, HImode);
6488 operands[3] = c4x_operand_subword (operands[0], 1, 0, HImode);")
6489
6490 ;
6491 ; NEG
6492 ;
6493 (define_insn "neghi2"
6494 [(set (match_operand:HI 0 "ext_reg_operand" "=d")
6495 (neg:HI (match_operand:HI 1 "src_operand" "rm")))
6496 (clobber (reg:CC_NOOV 21))]
6497 ""
6498 "#"
6499 [(set_attr "type" "multi")])
6500
6501 (define_split
6502 [(set (match_operand:HI 0 "ext_reg_operand" "")
6503 (neg:HI (match_operand:HI 1 "src_operand" "")))
6504 (clobber (reg:CC_NOOV 21))]
6505 "reload_completed"
6506 [(parallel [(set (reg:CC_NOOV 21)
6507 (compare:CC_NOOV (neg:QI (match_dup 3))
6508 (const_int 0)))
6509 (set (match_dup 2) (neg:QI (match_dup 3)))])
6510 (parallel [(set (match_dup 4) (neg:QI (match_dup 5)))
6511 (use (reg:CC_NOOV 21))
6512 (clobber (reg:CC_NOOV 21))])]
6513 "operands[2] = c4x_operand_subword (operands[0], 0, 1, HImode);
6514 operands[3] = c4x_operand_subword (operands[1], 0, 1, HImode);
6515 operands[4] = c4x_operand_subword (operands[0], 1, 1, HImode);
6516 operands[5] = c4x_operand_subword (operands[1], 1, 1, HImode);")
6517
6518 (define_insn "one_cmplhi2"
6519 [(set (match_operand:HI 0 "reg_operand" "=r")
6520 (not:HI (match_operand:HI 1 "src_operand" "rm")))
6521 (clobber (reg:CC 21))]
6522 ""
6523 "#"
6524 [(set_attr "type" "multi")])
6525
6526 (define_split
6527 [(set (match_operand:HI 0 "reg_operand" "")
6528 (not:HI (match_operand:HI 1 "src_operand" "")))
6529 (clobber (reg:CC 21))]
6530 "reload_completed"
6531 [(parallel [(set (match_dup 2) (not:QI (match_dup 3)))
6532 (clobber (reg:CC 21))])
6533 (parallel [(set (match_dup 4) (not:QI (match_dup 5)))
6534 (clobber (reg:CC 21))])]
6535 "operands[2] = c4x_operand_subword (operands[0], 0, 1, HImode);
6536 operands[3] = c4x_operand_subword (operands[1], 0, 1, HImode);
6537 operands[4] = c4x_operand_subword (operands[0], 1, 1, HImode);
6538 operands[5] = c4x_operand_subword (operands[1], 1, 1, HImode);")
6539
6540 (define_expand "floathiqf2"
6541 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
6542 (float:QF (match_operand:HI 1 "src_operand" "")))
6543 (clobber (reg:CC 21))])]
6544 ""
6545 "c4x_emit_libcall (floathiqf2_libfunc, FLOAT, QFmode, HImode, 2, operands);
6546 DONE;")
6547
6548 (define_expand "floatunshiqf2"
6549 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
6550 (unsigned_float:QF (match_operand:HI 1 "src_operand" "")))
6551 (clobber (reg:CC 21))])]
6552 ""
6553 "c4x_emit_libcall (floatunshiqf2_libfunc, UNSIGNED_FLOAT,
6554 QFmode, HImode, 2, operands);
6555 DONE;")
6556
6557 (define_expand "floathihf2"
6558 [(parallel [(set (match_operand:HF 0 "reg_operand" "")
6559 (float:HF (match_operand:HI 1 "src_operand" "")))
6560 (clobber (reg:CC 21))])]
6561 ""
6562 "c4x_emit_libcall (floathihf2_libfunc, FLOAT, HFmode, HImode, 2, operands);
6563 DONE;")
6564
6565 (define_expand "floatunshihf2"
6566 [(parallel [(set (match_operand:HF 0 "reg_operand" "")
6567 (unsigned_float:HF (match_operand:HI 1 "src_operand" "")))
6568 (clobber (reg:CC 21))])]
6569 ""
6570 "c4x_emit_libcall (floatunshihf2_libfunc, UNSIGNED_FLOAT,
6571 HFmode, HImode, 2, operands);
6572 DONE;")
6573
6574
6575 ;
6576 ; THREE OPERAND LONG LONG INSTRUCTIONS
6577 ;
6578
6579 (define_expand "addhi3"
6580 [(parallel [(set (match_operand:HI 0 "ext_reg_operand" "")
6581 (plus:HI (match_operand:HI 1 "src_operand" "")
6582 (match_operand:HI 2 "src_operand" "")))
6583 (clobber (reg:CC_NOOV 21))])]
6584 ""
6585 "legitimize_operands (PLUS, operands, HImode);")
6586
6587 (define_insn "*addhi3_clobber"
6588 [(set (match_operand:HI 0 "ext_reg_operand" "=d,d,?d")
6589 (plus:HI (match_operand:HI 1 "src_operand" "%0,rR,rS<>")
6590 (match_operand:HI 2 "src_operand" "rm,R,rS<>")))
6591 (clobber (reg:CC_NOOV 21))]
6592 "valid_operands (PLUS, operands, HImode)"
6593 "#"
6594 [(set_attr "type" "multi,multi,multi")])
6595
6596 (define_split
6597 [(set (match_operand:HI 0 "ext_reg_operand" "")
6598 (plus:HI (match_operand:HI 1 "src_operand" "")
6599 (match_operand:HI 2 "src_operand" "")))
6600 (clobber (reg:CC_NOOV 21))]
6601 "reload_completed"
6602 [(parallel [(set (reg:CC_NOOV 21)
6603 (compare:CC_NOOV (plus:QI (match_dup 4) (match_dup 5))
6604 (const_int 0)))
6605 (set (match_dup 3) (plus:QI (match_dup 4) (match_dup 5)))])
6606 (parallel [(set (match_dup 6) (plus:QI (match_dup 7) (match_dup 8)))
6607 (use (reg:CC_NOOV 21))
6608 (clobber (reg:CC_NOOV 21))])]
6609 "operands[3] = c4x_operand_subword (operands[0], 0, 1, HImode);
6610 operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
6611 operands[5] = c4x_operand_subword (operands[2], 0, 1, HImode);
6612 operands[6] = c4x_operand_subword (operands[0], 1, 1, HImode);
6613 operands[7] = c4x_operand_subword (operands[1], 1, 1, HImode);
6614 operands[8] = c4x_operand_subword (operands[2], 1, 1, HImode);")
6615
6616 (define_expand "subhi3"
6617 [(parallel [(set (match_operand:HI 0 "ext_reg_operand" "")
6618 (minus:HI (match_operand:HI 1 "src_operand" "")
6619 (match_operand:HI 2 "src_operand" "")))
6620 (clobber (reg:CC_NOOV 21))])]
6621 ""
6622 "legitimize_operands (MINUS, operands, HImode);")
6623
6624
6625 (define_insn "*subhi3_clobber"
6626 [(set (match_operand:HI 0 "ext_reg_operand" "=d,d,?d")
6627 (minus:HI (match_operand:HI 1 "src_operand" "0,rR,rS<>")
6628 (match_operand:HI 2 "src_operand" "rm,R,rS<>")))
6629 (clobber (reg:CC_NOOV 21))]
6630 "valid_operands (MINUS, operands, HImode)"
6631 "#"
6632 [(set_attr "type" "multi,multi,multi")])
6633
6634 (define_split
6635 [(set (match_operand:HI 0 "ext_reg_operand" "")
6636 (minus:HI (match_operand:HI 1 "src_operand" "")
6637 (match_operand:HI 2 "src_operand" "")))
6638 (clobber (reg:CC_NOOV 21))]
6639 "reload_completed"
6640 [(parallel [(set (reg:CC_NOOV 21)
6641 (compare:CC_NOOV (minus:QI (match_dup 4) (match_dup 5))
6642 (const_int 0)))
6643 (set (match_dup 3) (minus:QI (match_dup 4) (match_dup 5)))])
6644 (parallel [(set (match_dup 6) (minus:QI (match_dup 7) (match_dup 8)))
6645 (use (reg:CC_NOOV 21))
6646 (clobber (reg:CC_NOOV 21))])]
6647 "operands[3] = c4x_operand_subword (operands[0], 0, 1, HImode);
6648 operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
6649 operands[5] = c4x_operand_subword (operands[2], 0, 1, HImode);
6650 operands[6] = c4x_operand_subword (operands[0], 1, 1, HImode);
6651 operands[7] = c4x_operand_subword (operands[1], 1, 1, HImode);
6652 operands[8] = c4x_operand_subword (operands[2], 1, 1, HImode);")
6653
6654 (define_expand "iorhi3"
6655 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
6656 (ior:HI (match_operand:HI 1 "src_operand" "")
6657 (match_operand:HI 2 "src_operand" "")))
6658 (clobber (reg:CC 21))])]
6659 ""
6660 "legitimize_operands (IOR, operands, HImode);")
6661
6662 (define_insn "*iorhi3_clobber"
6663 [(set (match_operand:HI 0 "reg_operand" "=d,d,?d")
6664 (ior:HI (match_operand:HI 1 "src_operand" "%0,rR,rS<>")
6665 (match_operand:HI 2 "src_operand" "rm,R,rS<>")))
6666 (clobber (reg:CC 21))]
6667 "valid_operands (IOR, operands, HImode)"
6668 "#"
6669 [(set_attr "type" "multi,multi,multi")])
6670
6671 (define_split
6672 [(set (match_operand:HI 0 "reg_operand" "")
6673 (ior:HI (match_operand:HI 1 "src_operand" "")
6674 (match_operand:HI 2 "src_operand" "")))
6675 (clobber (reg:CC 21))]
6676 "reload_completed"
6677 [(parallel [(set (match_dup 3) (ior:QI (match_dup 4) (match_dup 5)))
6678 (clobber (reg:CC 21))])
6679 (parallel [(set (match_dup 6) (ior:QI (match_dup 7) (match_dup 8)))
6680 (clobber (reg:CC 21))])]
6681 "operands[3] = c4x_operand_subword (operands[0], 0, 1, HImode);
6682 operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
6683 operands[5] = c4x_operand_subword (operands[2], 0, 1, HImode);
6684 operands[6] = c4x_operand_subword (operands[0], 1, 1, HImode);
6685 operands[7] = c4x_operand_subword (operands[1], 1, 1, HImode);
6686 operands[8] = c4x_operand_subword (operands[2], 1, 1, HImode);")
6687
6688 (define_expand "andhi3"
6689 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
6690 (and:HI (match_operand:HI 1 "src_operand" "")
6691 (match_operand:HI 2 "src_operand" "")))
6692 (clobber (reg:CC 21))])]
6693 ""
6694 "legitimize_operands (AND, operands, HImode);")
6695
6696 (define_insn "*andhi3_clobber"
6697 [(set (match_operand:HI 0 "reg_operand" "=d,d,?d")
6698 (and:HI (match_operand:HI 1 "src_operand" "%0,rR,rS<>")
6699 (match_operand:HI 2 "src_operand" "rm,R,rS<>")))
6700 (clobber (reg:CC 21))]
6701 "valid_operands (AND, operands, HImode)"
6702 "#"
6703 [(set_attr "type" "multi,multi,multi")])
6704
6705 (define_split
6706 [(set (match_operand:HI 0 "reg_operand" "")
6707 (and:HI (match_operand:HI 1 "src_operand" "")
6708 (match_operand:HI 2 "src_operand" "")))
6709 (clobber (reg:CC 21))]
6710 "reload_completed"
6711 [(parallel [(set (match_dup 3) (and:QI (match_dup 4) (match_dup 5)))
6712 (clobber (reg:CC 21))])
6713 (parallel [(set (match_dup 6) (and:QI (match_dup 7) (match_dup 8)))
6714 (clobber (reg:CC 21))])]
6715 "operands[3] = c4x_operand_subword (operands[0], 0, 1, HImode);
6716 operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
6717 operands[5] = c4x_operand_subword (operands[2], 0, 1, HImode);
6718 operands[6] = c4x_operand_subword (operands[0], 1, 1, HImode);
6719 operands[7] = c4x_operand_subword (operands[1], 1, 1, HImode);
6720 operands[8] = c4x_operand_subword (operands[2], 1, 1, HImode);")
6721
6722 (define_expand "xorhi3"
6723 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
6724 (xor:HI (match_operand:HI 1 "src_operand" "")
6725 (match_operand:HI 2 "src_operand" "")))
6726 (clobber (reg:CC 21))])]
6727 ""
6728 "legitimize_operands (XOR, operands, HImode);")
6729
6730
6731 (define_insn "*xorhi3_clobber"
6732 [(set (match_operand:HI 0 "reg_operand" "=d,d,?d")
6733 (xor:HI (match_operand:HI 1 "src_operand" "%0,rR,rS<>")
6734 (match_operand:HI 2 "src_operand" "rm,R,rS<>")))
6735 (clobber (reg:CC 21))]
6736 "valid_operands (XOR, operands, HImode)"
6737 "#"
6738 [(set_attr "type" "multi,multi,multi")])
6739
6740 (define_split
6741 [(set (match_operand:HI 0 "reg_operand" "")
6742 (xor:HI (match_operand:HI 1 "src_operand" "")
6743 (match_operand:HI 2 "src_operand" "")))
6744 (clobber (reg:CC 21))]
6745 "reload_completed"
6746 [(parallel [(set (match_dup 3) (xor:QI (match_dup 4) (match_dup 5)))
6747 (clobber (reg:CC 21))])
6748 (parallel [(set (match_dup 6) (xor:QI (match_dup 7) (match_dup 8)))
6749 (clobber (reg:CC 21))])]
6750 "operands[3] = c4x_operand_subword (operands[0], 0, 1, HImode);
6751 operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
6752 operands[5] = c4x_operand_subword (operands[2], 0, 1, HImode);
6753 operands[6] = c4x_operand_subword (operands[0], 1, 1, HImode);
6754 operands[7] = c4x_operand_subword (operands[1], 1, 1, HImode);
6755 operands[8] = c4x_operand_subword (operands[2], 1, 1, HImode);")
6756
6757 (define_expand "ashlhi3"
6758 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
6759 (ashift:HI (match_operand:HI 1 "src_operand" "")
6760 (match_operand:QI 2 "src_operand" "")))
6761 (clobber (reg:CC 21))])]
6762 ""
6763 "if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32)
6764 {
6765 rtx op0hi = operand_subword (operands[0], 1, 0, HImode);
6766 rtx op0lo = operand_subword (operands[0], 0, 0, HImode);
6767 rtx op1lo = operand_subword (operands[1], 0, 0, HImode);
6768 rtx count = GEN_INT ((INTVAL (operands[2]) - 32));
6769
6770 if (INTVAL (count))
6771 emit_insn (gen_ashlqi3 (op0hi, op1lo, count));
6772 else
6773 emit_insn (gen_movqi (op0hi, op1lo));
6774 emit_insn (gen_movqi (op0lo, const0_rtx));
6775 DONE;
6776 }
6777 if (! REG_P (operands[1]))
6778 operands[1] = force_reg (HImode, operands[1]);
6779 emit_insn (gen_ashlhi3_reg (operands[0], operands[1], operands[2]));
6780 DONE;
6781 ")
6782
6783 ; %0.lo = %1.lo << %2
6784 ; %0.hi = (%1.hi << %2 ) | (%1.lo >> (32 - %2))
6785 ; This algorithm should work for shift counts greater than 32
6786 (define_expand "ashlhi3_reg"
6787 [(use (match_operand:HI 1 "reg_operand" ""))
6788 (use (match_operand:HI 0 "reg_operand" ""))
6789 /* If the shift count is greater than 32 this will give zero. */
6790 (parallel [(set (match_dup 7)
6791 (ashift:QI (match_dup 3)
6792 (match_operand:QI 2 "reg_operand" "")))
6793 (clobber (reg:CC 21))])
6794 /* If the shift count is greater than 32 this will give zero. */
6795 (parallel [(set (match_dup 8)
6796 (ashift:QI (match_dup 4) (match_dup 2)))
6797 (clobber (reg:CC 21))])
6798 (parallel [(set (match_dup 10)
6799 (plus:QI (match_dup 2) (const_int -32)))
6800 (clobber (reg:CC_NOOV 21))])
6801 /* If the shift count is greater than 32 this will do a left shift. */
6802 (parallel [(set (match_dup 9)
6803 (lshiftrt:QI (match_dup 3) (neg:QI (match_dup 10))))
6804 (clobber (reg:CC 21))])
6805 (set (match_dup 5) (match_dup 7))
6806 (parallel [(set (match_dup 6)
6807 (ior:QI (match_dup 8) (match_dup 9)))
6808 (clobber (reg:CC 21))])]
6809 ""
6810 "
6811 operands[3] = operand_subword (operands[1], 0, 1, HImode); /* lo */
6812 operands[4] = operand_subword (operands[1], 1, 1, HImode); /* hi */
6813 operands[5] = operand_subword (operands[0], 0, 1, HImode); /* lo */
6814 operands[6] = operand_subword (operands[0], 1, 1, HImode); /* hi */
6815 operands[7] = gen_reg_rtx (QImode); /* lo << count */
6816 operands[8] = gen_reg_rtx (QImode); /* hi << count */
6817 operands[9] = gen_reg_rtx (QImode); /* lo >> (32 - count) */
6818 operands[10] = gen_reg_rtx (QImode); /* 32 - count */
6819 ")
6820
6821 ; This should do all the dirty work with define_split
6822 (define_expand "lshrhi3"
6823 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
6824 (lshiftrt:HI (match_operand:HI 1 "src_operand" "")
6825 (match_operand:QI 2 "src_operand" "")))
6826 (clobber (reg:CC 21))])]
6827 ""
6828 "if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32)
6829 {
6830 rtx op0hi = operand_subword (operands[0], 1, 0, HImode);
6831 rtx op0lo = operand_subword (operands[0], 0, 0, HImode);
6832 rtx op1hi = operand_subword (operands[1], 1, 0, HImode);
6833 rtx count = GEN_INT ((INTVAL (operands[2]) - 32));
6834
6835 if (INTVAL (count))
6836 emit_insn (gen_lshrqi3 (op0lo, op1hi, count));
6837 else
6838 emit_insn (gen_movqi (op0lo, op1hi));
6839 emit_insn (gen_movqi (op0hi, const0_rtx));
6840 DONE;
6841 }
6842 if (! REG_P (operands[1]))
6843 operands[1] = force_reg (HImode, operands[1]);
6844 emit_insn (gen_lshrhi3_reg (operands[0], operands[1], operands[2]));
6845 DONE;")
6846
6847 ; %0.hi = %1.hi >> %2
6848 ; %0.lo = (%1.lo >> %2 ) | (%1.hi << (32 - %2))
6849 ; This algorithm should work for shift counts greater than 32
6850 (define_expand "lshrhi3_reg"
6851 [(use (match_operand:HI 1 "reg_operand" ""))
6852 (use (match_operand:HI 0 "reg_operand" ""))
6853 (parallel [(set (match_dup 11)
6854 (neg:QI (match_operand:QI 2 "reg_operand" "")))
6855 (clobber (reg:CC_NOOV 21))])
6856 /* If the shift count is greater than 32 this will give zero. */
6857 (parallel [(set (match_dup 7)
6858 (lshiftrt:QI (match_dup 3)
6859 (neg:QI (match_dup 11))))
6860 (clobber (reg:CC 21))])
6861 /* If the shift count is greater than 32 this will give zero. */
6862 (parallel [(set (match_dup 8)
6863 (lshiftrt:QI (match_dup 4)
6864 (neg:QI (match_dup 11))))
6865 (clobber (reg:CC 21))])
6866 (parallel [(set (match_dup 10)
6867 (plus:QI (match_dup 11) (const_int 32)))
6868 (clobber (reg:CC_NOOV 21))])
6869 /* If the shift count is greater than 32 this will do an arithmetic
6870 right shift. However, we need a logical right shift. */
6871 (parallel [(set (match_dup 9)
6872 (ashift:QI (match_dup 4) (unspec:QI [(match_dup 10)] UNSPEC_LSH)))
6873 (clobber (reg:CC 21))])
6874 (set (match_dup 6) (match_dup 8))
6875 (parallel [(set (match_dup 5)
6876 (ior:QI (match_dup 7) (match_dup 9)))
6877 (clobber (reg:CC 21))])]
6878 ""
6879 "
6880 operands[3] = operand_subword (operands[1], 0, 1, HImode); /* lo */
6881 operands[4] = operand_subword (operands[1], 1, 1, HImode); /* hi */
6882 operands[5] = operand_subword (operands[0], 0, 1, HImode); /* lo */
6883 operands[6] = operand_subword (operands[0], 1, 1, HImode); /* hi */
6884 operands[7] = gen_reg_rtx (QImode); /* lo >> count */
6885 operands[8] = gen_reg_rtx (QImode); /* hi >> count */
6886 operands[9] = gen_reg_rtx (QImode); /* hi << (32 - count) */
6887 operands[10] = gen_reg_rtx (QImode); /* 32 - count */
6888 operands[11] = gen_reg_rtx (QImode); /* -count */
6889 ")
6890
6891 ; This should do all the dirty work with define_split
6892 (define_expand "ashrhi3"
6893 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
6894 (ashiftrt:HI (match_operand:HI 1 "src_operand" "")
6895 (match_operand:QI 2 "src_operand" "")))
6896 (clobber (reg:CC 21))])]
6897 ""
6898 "if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32)
6899 {
6900 rtx op0hi = operand_subword (operands[0], 1, 0, HImode);
6901 rtx op0lo = operand_subword (operands[0], 0, 0, HImode);
6902 rtx op1hi = operand_subword (operands[1], 1, 0, HImode);
6903 rtx count = GEN_INT ((INTVAL (operands[2]) - 32));
6904
6905 if (INTVAL (count))
6906 emit_insn (gen_ashrqi3 (op0lo, op1hi, count));
6907 else
6908 emit_insn (gen_movqi (op0lo, op1hi));
6909 emit_insn (gen_ashrqi3 (op0hi, op1hi, GEN_INT (31)));
6910 DONE;
6911 }
6912 if (! REG_P (operands[1]))
6913 operands[1] = force_reg (HImode, operands[1]);
6914 emit_insn (gen_ashrhi3_reg (operands[0], operands[1], operands[2]));
6915 DONE;")
6916
6917 ; %0.hi = %1.hi >> %2
6918 ; %0.lo = (%1.lo >> %2 ) | (%1.hi << (32 - %2))
6919 ; This algorithm should work for shift counts greater than 32
6920 (define_expand "ashrhi3_reg"
6921 [(use (match_operand:HI 1 "reg_operand" ""))
6922 (use (match_operand:HI 0 "reg_operand" ""))
6923 (parallel [(set (match_dup 11)
6924 (neg:QI (match_operand:QI 2 "reg_operand" "")))
6925 (clobber (reg:CC_NOOV 21))])
6926 /* If the shift count is greater than 32 this will give zero. */
6927 (parallel [(set (match_dup 7)
6928 (lshiftrt:QI (match_dup 3)
6929 (neg:QI (match_dup 11))))
6930 (clobber (reg:CC 21))])
6931 /* If the shift count is greater than 32 this will give zero. */
6932 (parallel [(set (match_dup 8)
6933 (ashiftrt:QI (match_dup 4)
6934 (neg:QI (match_dup 11))))
6935 (clobber (reg:CC 21))])
6936 (parallel [(set (match_dup 10)
6937 (plus:QI (match_dup 11) (const_int 32)))
6938 (clobber (reg:CC_NOOV 21))])
6939 /* If the shift count is greater than 32 this will do an arithmetic
6940 right shift. */
6941 (parallel [(set (match_dup 9)
6942 (ashift:QI (match_dup 4) (match_dup 10)))
6943 (clobber (reg:CC 21))])
6944 (set (match_dup 6) (match_dup 8))
6945 (parallel [(set (match_dup 5)
6946 (ior:QI (match_dup 7) (match_dup 9)))
6947 (clobber (reg:CC 21))])]
6948 ""
6949 "
6950 operands[3] = operand_subword (operands[1], 0, 1, HImode); /* lo */
6951 operands[4] = operand_subword (operands[1], 1, 1, HImode); /* hi */
6952 operands[5] = operand_subword (operands[0], 0, 1, HImode); /* lo */
6953 operands[6] = operand_subword (operands[0], 1, 1, HImode); /* hi */
6954 operands[7] = gen_reg_rtx (QImode); /* lo >> count */
6955 operands[8] = gen_reg_rtx (QImode); /* hi >> count */
6956 operands[9] = gen_reg_rtx (QImode); /* hi << (32 - count) */
6957 operands[10] = gen_reg_rtx (QImode); /* 32 - count */
6958 operands[11] = gen_reg_rtx (QImode); /* -count */
6959 ")
6960
6961 (define_expand "cmphi"
6962 [(set (reg:CC 21)
6963 (compare:CC (match_operand:HI 0 "src_operand" "")
6964 (match_operand:HI 1 "src_operand" "")))]
6965 ""
6966 "legitimize_operands (COMPARE, operands, HImode);
6967 c4x_compare_op0 = operands[0];
6968 c4x_compare_op1 = operands[1];
6969 DONE;")
6970
6971 (define_insn "*cmphi_cc"
6972 [(set (reg:CC 21)
6973 (compare:CC (match_operand:HI 0 "src_operand" "rR,rS<>")
6974 (match_operand:HI 1 "src_operand" "R,rS<>")))]
6975 "valid_operands (COMPARE, operands, HImode)"
6976 "#"
6977 [(set_attr "type" "multi")])
6978
6979 (define_insn "*cmphi_cc_noov"
6980 [(set (reg:CC_NOOV 21)
6981 (compare:CC_NOOV (match_operand:HI 0 "src_operand" "rR,rS<>")
6982 (match_operand:HI 1 "src_operand" "R,rS<>")))]
6983 "valid_operands (COMPARE, operands, HImode)"
6984 "#"
6985 [(set_attr "type" "multi")])
6986
6987 ; This works only before reload because we need 2 extra registers.
6988 ; Use unspec to avoid recursive split.
6989 (define_split
6990 [(set (reg:CC 21)
6991 (compare:CC (match_operand:HI 0 "src_operand" "")
6992 (match_operand:HI 1 "src_operand" "")))]
6993 "! reload_completed"
6994 [(parallel [(set (reg:CC 21)
6995 (unspec:CC [(compare:CC (match_dup 0)
6996 (match_dup 1))] UNSPEC_CMPHI))
6997 (clobber (match_scratch:QI 2 ""))
6998 (clobber (match_scratch:QI 3 ""))])]
6999 "")
7000
7001 (define_split
7002 [(set (reg:CC_NOOV 21)
7003 (compare:CC_NOOV (match_operand:HI 0 "src_operand" "")
7004 (match_operand:HI 1 "src_operand" "")))]
7005 "! reload_completed"
7006 [(parallel [(set (reg:CC_NOOV 21)
7007 (unspec:CC_NOOV [(compare:CC_NOOV (match_dup 0)
7008 (match_dup 1))] UNSPEC_CMPHI))
7009 (clobber (match_scratch:QI 2 ""))
7010 (clobber (match_scratch:QI 3 ""))])]
7011 "")
7012
7013 ; This is normally not used. The define splits above are used first.
7014 (define_split
7015 [(set (reg:CC 21)
7016 (compare:CC (match_operand:HI 0 "src_operand" "")
7017 (match_operand:HI 1 "src_operand" "")))]
7018 "reload_completed"
7019 [(parallel [(set (reg:CC 21)
7020 (compare:CC (match_dup 0) (match_dup 1)))
7021 (use (reg:QI 20))])]
7022 "")
7023
7024 (define_split
7025 [(set (reg:CC_NOOV 21)
7026 (compare:CC_NOOV (match_operand:HI 0 "src_operand" "")
7027 (match_operand:HI 1 "src_operand" "")))]
7028 "reload_completed"
7029 [(parallel [(set (reg:CC_NOOV 21)
7030 (compare:CC_NOOV (match_dup 0) (match_dup 1)))
7031 (use (reg:QI 20))])]
7032 "")
7033
7034 (define_insn "*cmphi"
7035 [(set (reg:CC 21)
7036 (compare:CC (match_operand:HI 0 "src_operand" "rR,rS<>")
7037 (match_operand:HI 1 "src_operand" "R,rS<>")))
7038 (use (reg:QI 20))]
7039 "valid_operands (COMPARE, operands, HImode)"
7040 "*
7041 {
7042 int use_ir1 = (reg_operand (operands[0], HImode)
7043 && REG_P (operands[0])
7044 && REGNO (operands[0]) == IR1_REGNO)
7045 || (reg_operand (operands[1], HImode)
7046 && REG_P (operands[1])
7047 && REGNO (operands[1]) == IR1_REGNO);
7048
7049 if (use_ir1)
7050 output_asm_insn (\"push\\tir1\", operands);
7051 else
7052 output_asm_insn (\"push\\tbk\", operands);
7053 output_asm_insn (\"push\\tr0\", operands);
7054 output_asm_insn (\"subi3\\t%1,%0,r0\", operands);
7055 if (use_ir1)
7056 {
7057 output_asm_insn (\"ldiu\\tst,ir1\", operands);
7058 output_asm_insn (\"or\\t07bh,ir1\", operands);
7059 }
7060 else
7061 {
7062 output_asm_insn (\"ldiu\\tst,bk\", operands);
7063 output_asm_insn (\"or\\t07bh,bk\", operands);
7064 }
7065 output_asm_insn (\"subb3\\t%O1,%O0,r0\", operands);
7066 if (use_ir1)
7067 output_asm_insn (\"and3\\tir1,st,ir1\", operands);
7068 else
7069 output_asm_insn (\"and3\\tbk,st,bk\", operands);
7070 output_asm_insn (\"pop\\tr0\", operands);
7071 if (use_ir1)
7072 {
7073 output_asm_insn (\"ldiu\\tir1,st\", operands);
7074 output_asm_insn (\"pop\\tir1\", operands);
7075 }
7076 else
7077 {
7078 output_asm_insn (\"ldiu\\tbk,st\", operands);
7079 output_asm_insn (\"pop\\tbk\", operands);
7080 }
7081 return \"\";
7082 }"
7083 [(set_attr "type" "multi")])
7084
7085 (define_insn "*cmphi_noov"
7086 [(set (reg:CC_NOOV 21)
7087 (compare:CC_NOOV (match_operand:HI 0 "src_operand" "rR,rS<>")
7088 (match_operand:HI 1 "src_operand" "R,rS<>")))
7089 (use (reg:QI 20))]
7090 "valid_operands (COMPARE, operands, HImode)"
7091 "*
7092 {
7093 int use_ir1 = (reg_operand (operands[0], HImode)
7094 && REG_P (operands[0])
7095 && REGNO (operands[0]) == IR1_REGNO)
7096 || (reg_operand (operands[1], HImode)
7097 && REG_P (operands[1])
7098 && REGNO (operands[1]) == IR1_REGNO);
7099
7100 if (use_ir1)
7101 output_asm_insn (\"push\\tir1\", operands);
7102 else
7103 output_asm_insn (\"push\\tbk\", operands);
7104 output_asm_insn (\"push\\tr0\", operands);
7105 output_asm_insn (\"subi3\\t%1,%0,r0\", operands);
7106 if (use_ir1)
7107 {
7108 output_asm_insn (\"ldiu\\tst,ir1\", operands);
7109 output_asm_insn (\"or\\t07bh,ir1\", operands);
7110 }
7111 else
7112 {
7113 output_asm_insn (\"ldiu\\tst,bk\", operands);
7114 output_asm_insn (\"or\\t07bh,bk\", operands);
7115 }
7116 output_asm_insn (\"subb3\\t%O1,%O0,r0\", operands);
7117 if (use_ir1)
7118 output_asm_insn (\"and3\\tir1,st,ir1\", operands);
7119 else
7120 output_asm_insn (\"and3\\tbk,st,bk\", operands);
7121 output_asm_insn (\"pop\\tr0\", operands);
7122 if (use_ir1)
7123 {
7124 output_asm_insn (\"ldiu\\tir1,st\", operands);
7125 output_asm_insn (\"pop\\tir1\", operands);
7126 }
7127 else
7128 {
7129 output_asm_insn (\"ldiu\\tbk,st\", operands);
7130 output_asm_insn (\"pop\\tbk\", operands);
7131 }
7132 return \"\";
7133 }"
7134 [(set_attr "type" "multi")])
7135
7136
7137 (define_insn "cmphi_cc"
7138 [(set (reg:CC 21)
7139 (unspec:CC [(compare:CC (match_operand:HI 0 "src_operand" "rR,rS<>")
7140 (match_operand:HI 1 "src_operand" "R,rS<>"))] UNSPEC_CMPHI))
7141 (clobber (match_scratch:QI 2 "=&d,&d"))
7142 (clobber (match_scratch:QI 3 "=&c,&c"))]
7143 "valid_operands (COMPARE, operands, HImode)"
7144 "*
7145 output_asm_insn (\"subi3\\t%1,%0,%2\", operands);
7146 output_asm_insn (\"ldiu\\tst,%3\", operands);
7147 output_asm_insn (\"or\\t07bh,%3\", operands);
7148 output_asm_insn (\"subb3\\t%O1,%O0,%2\", operands);
7149 output_asm_insn (\"and\\t%3,st\", operands);
7150 return \"\";"
7151 [(set_attr "type" "multi")])
7152
7153 (define_insn "cmphi_cc_noov"
7154 [(set (reg:CC_NOOV 21)
7155 (unspec:CC_NOOV [(compare:CC_NOOV (match_operand:HI 0 "src_operand" "rR,rS<>")
7156 (match_operand:HI 1 "src_operand" "R,rS<>"))] UNSPEC_CMPHI))
7157 (clobber (match_scratch:QI 2 "=&d,&d"))
7158 (clobber (match_scratch:QI 3 "=&c,&c"))]
7159 "valid_operands (COMPARE, operands, HImode)"
7160 "*
7161 output_asm_insn (\"subi3\\t%1,%0,%2\", operands);
7162 output_asm_insn (\"ldiu\\tst,%3\", operands);
7163 output_asm_insn (\"or\\t07bh,%3\", operands);
7164 output_asm_insn (\"subb3\\t%O1,%O0,%2\", operands);
7165 output_asm_insn (\"and\\t%3,st\", operands);
7166 return \"\";"
7167 [(set_attr "type" "multi")])
7168
7169 (define_expand "mulhi3"
7170 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
7171 (mult:HI (match_operand:HI 1 "src_operand" "")
7172 (match_operand:HI 2 "src_operand" "")))
7173 (clobber (reg:CC 21))])]
7174 ""
7175 "c4x_emit_libcall3 (smul_optab->handlers[(int) HImode].libfunc,
7176 MULT, HImode, operands);
7177 DONE;")
7178
7179
7180 ;
7181 ; PEEPHOLES
7182 ;
7183
7184 ; dbCC peepholes
7185 ;
7186 ; Turns
7187 ; loop:
7188 ; [ ... ]
7189 ; bCC label ; abnormal loop termination
7190 ; dbu aN, loop ; normal loop termination
7191 ;
7192 ; Into
7193 ; loop:
7194 ; [ ... ]
7195 ; dbCC aN, loop
7196 ; bCC label
7197 ;
7198 ; Which moves the bCC condition outside the inner loop for free.
7199 ;
7200 (define_peephole
7201 [(set (pc) (if_then_else (match_operator 3 "comparison_operator"
7202 [(reg:CC 21) (const_int 0)])
7203 (label_ref (match_operand 2 "" ""))
7204 (pc)))
7205 (parallel
7206 [(set (pc)
7207 (if_then_else
7208 (ge (plus:QI (match_operand:QI 0 "addr_reg_operand" "+a")
7209 (const_int -1))
7210 (const_int 0))
7211 (label_ref (match_operand 1 "" ""))
7212 (pc)))
7213 (set (match_dup 0)
7214 (plus:QI (match_dup 0)
7215 (const_int -1)))
7216 (use (reg:QI 20))
7217 (clobber (reg:CC_NOOV 21))])]
7218 "! c4x_label_conflict (insn, operands[2], operands[1])"
7219 "db%I3\\t%0,%l1\\n\\tb%3\\t%l2"
7220 [(set_attr "type" "multi")])
7221
7222 (define_peephole
7223 [(set (pc) (if_then_else (match_operator 3 "comparison_operator"
7224 [(reg:CC 21) (const_int 0)])
7225 (label_ref (match_operand 2 "" ""))
7226 (pc)))
7227 (parallel
7228 [(set (pc)
7229 (if_then_else
7230 (ne (match_operand:QI 0 "addr_reg_operand" "+a")
7231 (const_int 0))
7232 (label_ref (match_operand 1 "" ""))
7233 (pc)))
7234 (set (match_dup 0)
7235 (plus:QI (match_dup 0)
7236 (const_int -1)))])]
7237 "! c4x_label_conflict (insn, operands[2], operands[1])"
7238 "db%I3\\t%0,%l1\\n\\tb%3\\t%l2"
7239 [(set_attr "type" "multi")])
7240
7241 ;
7242 ; Peepholes to convert 'call label; rets' into jump label
7243 ;
7244
7245 (define_peephole
7246 [(parallel [(call (mem:QI (match_operand:QI 0 "call_address_operand" ""))
7247 (match_operand:QI 1 "general_operand" ""))
7248 (clobber (reg:QI 31))])
7249 (return)]
7250 "! c4x_null_epilogue_p ()"
7251 "*
7252 if (REG_P (operands[0]))
7253 return \"bu%#\\t%C0\";
7254 else
7255 return \"br%#\\t%C0\";"
7256 [(set_attr "type" "jump")])
7257
7258 (define_peephole
7259 [(parallel [(set (match_operand 0 "" "")
7260 (call (mem:QI (match_operand:QI 1 "call_address_operand" ""))
7261 (match_operand:QI 2 "general_operand" "")))
7262 (clobber (reg:QI 31))])
7263 (return)]
7264 "! c4x_null_epilogue_p ()"
7265 "*
7266 if (REG_P (operands[1]))
7267 return \"bu%#\\t%C1\";
7268 else
7269 return \"br%#\\t%C1\";"
7270 [(set_attr "type" "jump")])
7271
7272
7273 ; This peephole should be unnecessary with my patches to flow.c
7274 ; for better autoincrement detection
7275 (define_peephole
7276 [(set (match_operand:QF 0 "ext_low_reg_operand" "")
7277 (mem:QF (match_operand:QI 1 "addr_reg_operand" "")))
7278 (set (match_operand:QF 2 "ext_low_reg_operand" "")
7279 (mem:QF (plus:QI (match_dup 1) (const_int 1))))
7280 (parallel [(set (match_dup 1) (plus:QI (match_dup 1) (const_int 2)))
7281 (clobber (reg:CC_NOOV 21))])]
7282 ""
7283 "ldf\\t*%1++,%0\\n\\tldf\\t*%1++,%2")
7284
7285
7286 ; This peephole should be unnecessary with my patches to flow.c
7287 ; for better autoincrement detection
7288 (define_peephole
7289 [(set (mem:QF (match_operand:QI 0 "addr_reg_operand" ""))
7290 (match_operand:QF 1 "ext_low_reg_operand" ""))
7291 (set (mem:QF (plus:QI (match_dup 0) (const_int 1)))
7292 (match_operand:QF 2 "ext_low_reg_operand" ""))
7293 (parallel [(set (match_dup 0) (plus:QI (match_dup 0) (const_int 2)))
7294 (clobber (reg:CC_NOOV 21))])]
7295 ""
7296 "stf\\t%1,*%0++\\n\\tstf\\t%2,*%0++")
7297
7298
7299 ; The following two peepholes remove an unnecessary load
7300 ; often found at the end of a function. These peepholes
7301 ; could be generalized to other binary operators. They shouldn't
7302 ; be required if we run a post reload mop-up pass.
7303 (define_peephole
7304 [(parallel [(set (match_operand:QF 0 "ext_reg_operand" "")
7305 (plus:QF (match_operand:QF 1 "ext_reg_operand" "")
7306 (match_operand:QF 2 "ext_reg_operand" "")))
7307 (clobber (reg:CC_NOOV 21))])
7308 (set (match_operand:QF 3 "ext_reg_operand" "")
7309 (match_dup 0))]
7310 "dead_or_set_p (insn, operands[0])"
7311 "addf3\\t%2,%1,%3")
7312
7313 (define_peephole
7314 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
7315 (plus:QI (match_operand:QI 1 "reg_operand" "")
7316 (match_operand:QI 2 "reg_operand" "")))
7317 (clobber (reg:CC_NOOV 21))])
7318 (set (match_operand:QI 3 "reg_operand" "")
7319 (match_dup 0))]
7320 "dead_or_set_p (insn, operands[0])"
7321 "addi3\\t%2,%1,%3")