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1750a.md, [...]: Use GEN_INT consistently.
[gcc.git] / gcc / config / convex / convex.h
1 /* Definitions of target machine for GNU compiler. Convex version.
2 Copyright (C) 1988, 1994, 1995, 1996 Free Software Foundation, Inc.
3
4 This file is part of GNU CC.
5
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
20
21
22 /* Standard GCC variables that we reference. */
23
24 extern int target_flags;
25
26 /* Convex machine-specific flags
27 -mc1 target instruction set, libraries, scheduling
28 -mc2
29 -mc32
30 -mc34
31 -mc38
32 -margcount use standard calling sequence, with arg count word
33 -mno-argcount don't push arg count, depend on symbol table
34 -margcount-nop place arg count in a nop instruction (faster than push)
35 -mvolatile-cache use data cache for volatile mem refs (default)
36 -mvolatile-nocache bypass data cache for volatile mem refs
37 -mlong32 cc- and libc-compatible 32-bit longs
38 -mlong64 64-bit longs
39 */
40
41 /* Macro to define tables used to set -mXXX flags.
42 This is a list in braces of pairs in braces,
43 each pair being { "NAME", VALUE }
44 where VALUE is the bits to set or minus the bits to clear.
45 An empty string NAME is used to identify the default VALUE. */
46
47 #ifndef TARGET_DEFAULT
48 #define TARGET_DEFAULT 0
49 #endif
50
51 #define TARGET_SWITCHES \
52 { { "c1", 001 }, \
53 { "c2", 002 }, \
54 { "c32", 004 }, \
55 { "c34", 010 }, \
56 { "c38", 020 }, \
57 { "argcount", 0100 }, \
58 { "argcount-nop", 0200 }, \
59 { "no-argcount", -0300 }, \
60 { "volatile-cache", -0400 }, \
61 { "no-volatile-cache", 0400 }, \
62 { "volatile-nocache", 0400 }, \
63 { "long64", 01000 }, \
64 { "long32", -01000 }, \
65 { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT}}
66
67 /* Macros used in the machine description to test the flags. */
68
69 #define TARGET_C1 (target_cpu == 0)
70 #define TARGET_C2 (target_cpu == 1)
71 #define TARGET_C34 (target_cpu == 2)
72 #define TARGET_C38 (target_cpu == 3)
73 #define TARGET_ARGCOUNT (target_flags & 0100)
74 #define TARGET_ARGCOUNT_NOP (target_flags & 0200)
75 #define TARGET_LONG64 (target_flags & 01000)
76 #define TARGET_VOLATILE_NOCACHE (target_flags & 0400)
77
78 #define OVERRIDE_OPTIONS \
79 { \
80 init_convex (); \
81 if ((target_flags & 077) != ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 077)) \
82 target_flags &= ~ (TARGET_DEFAULT | TARGET_CPU_DEFAULT); \
83 if (target_flags & 001) \
84 target_cpu = 0; \
85 else if (target_flags & 006) \
86 target_cpu = 1; \
87 else if (target_flags & 010) \
88 target_cpu = 2; \
89 else if (target_flags & 020) \
90 target_cpu = 3; \
91 }
92
93 /* Names to predefine in the preprocessor for this target machine. */
94
95 #define CPP_PREDEFINES "-Dconvex -Dunix -Asystem(unix) -Acpu(convex) -Amachine(convex)"
96
97 /* Print subsidiary information on the compiler version in use. */
98
99 #define TARGET_VERSION fprintf (stderr, " (convex)");
100
101 /* Target-dependent specs.
102 Some libraries come in c1 and c2+ versions; use the appropriate ones.
103 Make a target-dependent __convex_cxx__ define to relay the target cpu
104 to the program being compiled. */
105
106 #if (TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 1
107
108 /* C1 default */
109
110 #if _IEEE_FLOAT_
111
112 #define CPP_SPEC \
113 "%{!mc2:%{!mc32:%{!mc34:%{!mc38:-D__convex_c1__}}}} \
114 %{mc2:-D__convex_c2__} \
115 %{mc32:-D__convex_c32__} \
116 %{mc34:-D__convex_c34__} \
117 %{mc38:-D__convex_c38__} \
118 %{fno-builtin:-D__NO_INLINE} \
119 -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
120 -D_IEEE_FLOAT_ \
121 %{.S:-P} \
122 %{!traditional:-D__stdc__} \
123 %{!traditional:-D_LONGLONG} \
124 %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long} \
125 %{!ansi:-D_POSIX_SOURCE} \
126 %{!ansi:-D_CONVEX_SOURCE}"
127
128 #else
129
130 #define CPP_SPEC \
131 "%{!mc2:%{!mc32:%{!mc34:%{!mc38:-D__convex_c1__}}}} \
132 %{mc2:-D__convex_c2__} \
133 %{mc32:-D__convex_c32__} \
134 %{mc34:-D__convex_c34__} \
135 %{mc38:-D__convex_c38__} \
136 %{fno-builtin:-D__NO_INLINE} \
137 -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
138 -D_CONVEX_FLOAT_ \
139 %{.S:-P} \
140 %{!traditional:-D__stdc__} \
141 %{!traditional:-D_LONGLONG} \
142 %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long} \
143 %{!ansi:-D_POSIX_SOURCE} \
144 %{!ansi:-D_CONVEX_SOURCE}"
145
146 #endif
147
148 #define LIB_SPEC \
149 "%{!mc2:%{!mc32:%{!mc34:%{!mc38:-lC1%{traditional:_old}%{p:_p}%{pg:_p}}}}} \
150 %{mc2:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \
151 %{mc32:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \
152 %{mc34:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \
153 %{mc38:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \
154 -lc%{traditional:_old}%{p:_p}%{pg:_p}"
155
156 #endif
157
158 #if (TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 2
159
160 /* C2 default */
161
162 #if _IEEE_FLOAT_
163
164 #define CPP_SPEC \
165 "%{mc1:-D__convex_c1__} \
166 %{!mc1:%{!mc32:%{!mc34:%{!mc38:-D__convex_c2__}}}} \
167 %{mc32:-D__convex_c32__} \
168 %{mc34:-D__convex_c34__} \
169 %{mc38:-D__convex_c38__} \
170 %{fno-builtin:-D__NO_INLINE} \
171 -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
172 -D_IEEE_FLOAT_ \
173 %{.S:-P} \
174 %{!traditional:-D__stdc__} \
175 %{!traditional:-D_LONGLONG} \
176 %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long} \
177 %{!ansi:-D_POSIX_SOURCE} \
178 %{!ansi:-D_CONVEX_SOURCE}"
179
180 #else
181
182 #define CPP_SPEC \
183 "%{mc1:-D__convex_c1__} \
184 %{!mc1:%{!mc32:%{!mc34:%{!mc38:-D__convex_c2__}}}} \
185 %{mc32:-D__convex_c32__} \
186 %{mc34:-D__convex_c34__} \
187 %{mc38:-D__convex_c38__} \
188 %{fno-builtin:-D__NO_INLINE} \
189 -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
190 -D_CONVEX_FLOAT_ \
191 %{.S:-P} \
192 %{!traditional:-D__stdc__} \
193 %{!traditional:-D_LONGLONG} \
194 %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long} \
195 %{!ansi:-D_POSIX_SOURCE} \
196 %{!ansi:-D_CONVEX_SOURCE}"
197
198 #endif
199
200 #define LIB_SPEC \
201 "%{mc1:-lC1%{traditional:_old}%{p:_p}%{pg:_p}} \
202 %{!mc1:%{!mc32:%{!mc34:%{!mc38:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}}}} \
203 %{mc32:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \
204 %{mc34:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \
205 %{mc38:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \
206 -lc%{traditional:_old}%{p:_p}%{pg:_p}"
207
208 #endif
209
210 #if (TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 4
211
212 /* C32 default */
213
214 #if _IEEE_FLOAT_
215
216 #define CPP_SPEC \
217 "%{mc1:-D__convex_c1__} \
218 %{mc2:-D__convex_c2__} \
219 %{!mc1:%{!mc2:%{!mc34:%{!mc38:-D__convex_c32__}}}} \
220 %{mc34:-D__convex_c34__} \
221 %{mc38:-D__convex_c38__} \
222 %{fno-builtin:-D__NO_INLINE} \
223 -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
224 -D_IEEE_FLOAT_ \
225 %{.S:-P} \
226 %{!traditional:-D__stdc__} \
227 %{!traditional:-D_LONGLONG} \
228 %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long} \
229 %{!ansi:-D_POSIX_SOURCE} \
230 %{!ansi:-D_CONVEX_SOURCE}"
231
232 #else
233
234 #define CPP_SPEC \
235 "%{mc1:-D__convex_c1__} \
236 %{mc2:-D__convex_c2__} \
237 %{!mc1:%{!mc2:%{!mc34:%{!mc38:-D__convex_c32__}}}} \
238 %{mc34:-D__convex_c34__} \
239 %{mc38:-D__convex_c38__} \
240 %{fno-builtin:-D__NO_INLINE} \
241 -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
242 -D_CONVEX_FLOAT_ \
243 %{.S:-P} \
244 %{!traditional:-D__stdc__} \
245 %{!traditional:-D_LONGLONG} \
246 %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long} \
247 %{!ansi:-D_POSIX_SOURCE} \
248 %{!ansi:-D_CONVEX_SOURCE}"
249
250 #endif
251
252 #define LIB_SPEC \
253 "%{mc1:-lC1%{traditional:_old}%{p:_p}%{pg:_p}} \
254 %{mc2:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \
255 %{!mc1:%{!mc2:%{!mc34:%{!mc38:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}}}} \
256 %{mc34:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \
257 %{mc38:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \
258 -lc%{traditional:_old}%{p:_p}%{pg:_p}"
259
260 #endif
261
262 #if (TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 010
263
264 /* C34 default */
265
266 #if _IEEE_FLOAT_
267
268 #define CPP_SPEC \
269 "%{mc1:-D__convex_c1__} \
270 %{mc2:-D__convex_c2__} \
271 %{mc32:-D__convex_c32__} \
272 %{!mc1:%{!mc2:%{!mc32:%{!mc38:-D__convex_c34__}}}} \
273 %{mc38:-D__convex_c38__} \
274 %{fno-builtin:-D__NO_INLINE} \
275 -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
276 -D_IEEE_FLOAT_ \
277 %{.S:-P} \
278 %{!traditional:-D__stdc__} \
279 %{!traditional:-D_LONGLONG} \
280 %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long} \
281 %{!ansi:-D_POSIX_SOURCE} \
282 %{!ansi:-D_CONVEX_SOURCE}"
283
284 #else
285
286 #define CPP_SPEC \
287 "%{mc1:-D__convex_c1__} \
288 %{mc2:-D__convex_c2__} \
289 %{mc32:-D__convex_c32__} \
290 %{!mc1:%{!mc2:%{!mc32:%{!mc38:-D__convex_c34__}}}} \
291 %{mc38:-D__convex_c38__} \
292 %{fno-builtin:-D__NO_INLINE} \
293 -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
294 -D_CONVEX_FLOAT_ \
295 %{.S:-P} \
296 %{!traditional:-D__stdc__} \
297 %{!traditional:-D_LONGLONG} \
298 %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long} \
299 %{!ansi:-D_POSIX_SOURCE} \
300 %{!ansi:-D_CONVEX_SOURCE}"
301
302 #endif
303
304 #define LIB_SPEC \
305 "%{mc1:-lC1%{traditional:_old}%{p:_p}%{pg:_p}} \
306 %{mc2:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \
307 %{mc32:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \
308 %{!mc1:%{!mc2:%{!mc32:%{!mc38:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}}}} \
309 %{mc38:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \
310 -lc%{traditional:_old}%{p:_p}%{pg:_p}"
311
312 #endif
313
314 #if (TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 020
315
316 /* C38 default */
317
318 #if _IEEE_FLOAT_
319
320 #define CPP_SPEC \
321 "%{mc1:-D__convex_c1__} \
322 %{mc2:-D__convex_c2__} \
323 %{mc32:-D__convex_c32__} \
324 %{mc34:-D__convex_c34__} \
325 %{fno-builtin:-D__NO_INLINE} \
326 -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
327 -D_IEEE_FLOAT_ \
328 %{!mc1:%{!mc2:%{!mc32:%{!mc34:-D__convex_c38__}}}} \
329 %{.S:-P} \
330 %{!traditional:-D__stdc__} \
331 %{!traditional:-D_LONGLONG} \
332 %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long} \
333 %{!ansi:-D_POSIX_SOURCE} \
334 %{!ansi:-D_CONVEX_SOURCE}"
335
336 #else
337
338 #define CPP_SPEC \
339 "%{mc1:-D__convex_c1__} \
340 %{mc2:-D__convex_c2__} \
341 %{mc32:-D__convex_c32__} \
342 %{mc34:-D__convex_c34__} \
343 %{fno-builtin:-D__NO_INLINE} \
344 -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB \
345 -D_CONVEX_FLOAT_ \
346 %{!mc1:%{!mc2:%{!mc32:%{!mc34:-D__convex_c38__}}}} \
347 %{.S:-P} \
348 %{!traditional:-D__stdc__} \
349 %{!traditional:-D_LONGLONG} \
350 %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long} \
351 %{!ansi:-D_POSIX_SOURCE} \
352 %{!ansi:-D_CONVEX_SOURCE}"
353
354 #endif
355
356 #define LIB_SPEC \
357 "%{mc1:-lC1%{traditional:_old}%{p:_p}%{pg:_p}} \
358 %{mc2:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \
359 %{mc32:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \
360 %{mc34:-lC2%{traditional:_old}%{p:_p}%{pg:_p}} \
361 %{!mc1:%{!mc2:%{!mc32:%{!mc34:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}}}} \
362 -lc%{traditional:_old}%{p:_p}%{pg:_p}"
363
364 #endif
365
366 #if _IEEE_FLOAT_
367
368 /* ieee default */
369
370 #define ASM_SPEC "-fi"
371
372 #define LINK_SPEC \
373 "-E%{traditional:no}posix \
374 -X \
375 %{F} %{M*} %{y*} \
376 -fi \
377 -A__iob=___ap$iob \
378 -A_use_libc_sema=___ap$use_libc_sema \
379 %{traditional:-A___gcc_cleanup=__cleanup} \
380 %{!traditional:-A___gcc_cleanup=___ap$do_registered_functions} \
381 -L/usr/lib"
382
383 #define STARTFILE_SPEC \
384 "%{!pg:%{!p:/usr/lib/crt/crt0.o}} \
385 %{!pg:%{p:/usr/lib/crt/mcrt0.o}} \
386 %{pg:/usr/lib/crt/gcrt0.o} \
387 /usr/lib/crt/fpmode_i.o"
388
389 #else
390
391 /* native default */
392
393 #define ASM_SPEC "-fn"
394
395 #define LINK_SPEC \
396 "-E%{traditional:no}posix \
397 -X \
398 %{F} %{M*} %{y*} \
399 -fn \
400 -A__iob=___ap$iob \
401 -A_use_libc_sema=___ap$use_libc_sema \
402 %{traditional:-A___gcc_cleanup=__cleanup} \
403 %{!traditional:-A___gcc_cleanup=___ap$do_registered_functions} \
404 -L/usr/lib"
405
406 #define STARTFILE_SPEC \
407 "%{!pg:%{!p:/usr/lib/crt/crt0.o}} \
408 %{!pg:%{p:/usr/lib/crt/mcrt0.o}} \
409 %{pg:/usr/lib/crt/gcrt0.o}"
410
411 #endif
412
413 /* Use /path/libgcc.a instead of -lgcc, makes bootstrap work more smoothly. */
414
415 #define LINK_LIBGCC_SPECIAL_1
416
417 /* Since IEEE support was added to gcc, most things seem to like it
418 better if we disable exceptions and check afterward for infinity. */
419
420 #if __convex__
421 #if _IEEE_FLOAT_
422 #define REAL_VALUE_ISNAN(x) 0
423 #define REAL_VALUE_ISINF(x) ((*(short *) &(x) & 0x7ff0) == 0x7ff0)
424 #else
425 #define REAL_VALUE_ISNAN(x) 0
426 #define REAL_VALUE_ISINF(x) ((*(short *) &(x) & 0xfff0) == 0x8000)
427 #endif
428 #endif
429 \f
430 /* Target machine storage layout */
431
432 /* Define this if most significant bit is lowest numbered
433 in instructions that operate on numbered bit-fields. */
434 #define BITS_BIG_ENDIAN 1
435
436 /* Define this if most significant byte of a word is the lowest numbered. */
437 #define BYTES_BIG_ENDIAN 1
438
439 /* Define this if most significant word of a multiword number is numbered. */
440 #define WORDS_BIG_ENDIAN 1
441
442 /* Number of bits in an addressable storage unit */
443 #define BITS_PER_UNIT 8
444
445 /* Width in bits of a "word", which is the contents of a machine register.
446 Note that this is not necessarily the width of data type `int';
447 if using 16-bit ints on a 68000, this would still be 32.
448 But on a machine with 16-bit registers, this would be 16. */
449 #define BITS_PER_WORD 64
450
451 /* Width of a word, in units (bytes). */
452 #define UNITS_PER_WORD 8
453
454 /* Width in bits of a pointer.
455 See also the macro `Pmode' defined below. */
456 #define POINTER_SIZE 32
457
458 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
459 #define PARM_BOUNDARY 32
460
461 /* Boundary (in *bits*) on which stack pointer should be aligned. */
462 #define STACK_BOUNDARY 64
463
464 /* Allocation boundary (in *bits*) for the code of a function. */
465 #define FUNCTION_BOUNDARY 16
466
467 /* Alignment of field after `int : 0' in a structure. */
468 #define EMPTY_FIELD_BOUNDARY 32
469
470 /* Every structure's size must be a multiple of this. */
471 #define STRUCTURE_SIZE_BOUNDARY 8
472
473 /* A bitfield declared as `int' forces `int' alignment for the struct. */
474 #define PCC_BITFIELD_TYPE_MATTERS 1
475
476 /* No data type wants to be aligned rounder than this. */
477 /* beware of doubles in structs -- 64 is incompatible with cc */
478 #define BIGGEST_ALIGNMENT 32
479
480 /* Set this nonzero if move instructions will actually fail to work
481 when given unaligned data. */
482 #define STRICT_ALIGNMENT 0
483
484 /* Define sizes of basic C types to conform to ordinary usage -- these
485 types depend on BITS_PER_WORD otherwise. */
486 #define CHAR_TYPE_SIZE 8
487 #define SHORT_TYPE_SIZE 16
488 #define INT_TYPE_SIZE 32
489 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
490 #define LONG_LONG_TYPE_SIZE 64
491 #define FLOAT_TYPE_SIZE 32
492 #define DOUBLE_TYPE_SIZE 64
493 #define LONG_DOUBLE_TYPE_SIZE 64
494 /* This prevents cexp.c from depending on LONG_TYPE_SIZE. */
495 #define MAX_LONG_TYPE_SIZE 64
496
497 /* Declare the standard types used by builtins to match convex stddef.h --
498 with int rather than long. */
499
500 #define SIZE_TYPE "unsigned int"
501 #define PTRDIFF_TYPE "int"
502 \f
503 /* Standard register usage. */
504
505 /* Number of actual hardware registers.
506 The hardware registers are assigned numbers for the compiler
507 from 0 to just below FIRST_PSEUDO_REGISTER.
508 All registers that the compiler knows about must be given numbers,
509 even those that are not normally considered general registers. */
510 #define FIRST_PSEUDO_REGISTER 16
511
512 /* 1 for registers that have pervasive standard uses
513 and are not available for the register allocator.
514 For Convex, these are AP, FP, and SP. */
515 #define FIXED_REGISTERS \
516 { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1 }
517
518 /* 1 for registers not available across function calls.
519 These must include the FIXED_REGISTERS and also any
520 registers that can be used without being saved.
521 The latter must include the registers where values are returned
522 and the register where structure-value addresses are passed.
523 Aside from that, you can include as many other registers as you like. */
524 #define CALL_USED_REGISTERS \
525 { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
526
527 /* List the order in which to allocate registers. Each register must be
528 listed once, even those in FIXED_REGISTERS.
529 For Convex, put S0 (the return register) last. */
530 #define REG_ALLOC_ORDER \
531 { 1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 0, 8, 14, 15 }
532
533 /* Return number of consecutive hard regs needed starting at reg REGNO
534 to hold something of mode MODE.
535 This is ordinarily the length in words of a value of mode MODE
536 but can be less for certain modes in special long registers. */
537 #define HARD_REGNO_NREGS(REGNO, MODE) \
538 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
539
540 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
541 On Convex, S registers can hold any type, A registers any nonfloat. */
542 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
543 (S_REGNO_P (REGNO) \
544 || (GET_MODE_SIZE (MODE) <= 4 && (MODE) != SFmode))
545
546 /* Value is 1 if it is a good idea to tie two pseudo registers
547 when one has mode MODE1 and one has mode MODE2.
548 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
549 for any hard reg, then this must be 0 for correct output. */
550 #define MODES_TIEABLE_P(MODE1, MODE2) \
551 ((GET_MODE_SIZE (MODE1) <= 4 && (MODE1) != SFmode) \
552 == (GET_MODE_SIZE (MODE2) <= 4 && (MODE2) != SFmode))
553
554 /* Specify the registers used for certain standard purposes.
555 The values of these macros are register numbers. */
556
557 #define S0_REGNUM 0
558 #define A0_REGNUM 8
559
560 /* Register to use for pushing function arguments. */
561 #define STACK_POINTER_REGNUM A0_REGNUM
562
563 /* Base register for access to local variables of the function. */
564 #define FRAME_POINTER_REGNUM (A0_REGNUM + 7)
565
566 /* Value should be nonzero if functions must have frame pointers.
567 Zero means the frame pointer need not be set up (and parms
568 may be accessed via the stack pointer) in functions that seem suitable.
569 This is computed in `reload', in reload1.c. */
570 #define FRAME_POINTER_REQUIRED 1
571
572 /* Base register for access to arguments of the function. */
573 #define ARG_POINTER_REGNUM (A0_REGNUM + 6)
574
575 /* Register in which static-chain is passed to a function.
576 Use S0, not an A reg, because this rare use would otherwise prevent
577 an A reg from being available to global-alloc across calls. */
578 #define STATIC_CHAIN_REGNUM S0_REGNUM
579
580 /* Register in which address to store a structure value
581 is passed to a function. */
582 #define STRUCT_VALUE_REGNUM (A0_REGNUM + 1)
583 \f
584 /* Define the classes of registers for register constraints in the
585 machine description. Also define ranges of constants.
586
587 One of the classes must always be named ALL_REGS and include all hard regs.
588 If there is more than one class, another class must be named NO_REGS
589 and contain no registers.
590
591 The name GENERAL_REGS must be the name of a class (or an alias for
592 another name such as ALL_REGS). This is the class of registers
593 that is allowed by "g" or "r" in a register constraint.
594 Also, registers outside this class are allocated only when
595 instructions express preferences for them.
596
597 The classes must be numbered in nondecreasing order; that is,
598 a larger-numbered class must never be contained completely
599 in a smaller-numbered class.
600
601 For any two classes, it is very desirable that there be another
602 class that represents their union. */
603
604 /* Convex has classes A (address) and S (scalar).
605 A is further divided into SP_REGS (stack pointer) and INDEX_REGS.
606 SI_REGS is S_REGS + INDEX_REGS -- all the regs except SP. */
607
608 enum reg_class {
609 NO_REGS, S_REGS, INDEX_REGS, SP_REGS, A_REGS, SI_REGS,
610 ALL_REGS, LIM_REG_CLASSES
611 };
612
613 #define N_REG_CLASSES (int) LIM_REG_CLASSES
614
615 /* Since GENERAL_REGS is the same class as ALL_REGS,
616 don't give it a different class number; just make it an alias. */
617
618 #define GENERAL_REGS ALL_REGS
619
620 /* Give names of register classes as strings for dump file. */
621
622 #define REG_CLASS_NAMES \
623 {"NO_REGS", "S_REGS", "INDEX_REGS", "SP_REGS", "A_REGS", "SI_REGS", \
624 "ALL_REGS" }
625
626 /* Define which registers fit in which classes.
627 This is an initializer for a vector of HARD_REG_SET
628 of length N_REG_CLASSES. */
629
630 #define REG_CLASS_CONTENTS \
631 { 0, 0x00ff, 0xfe00, 0x0100, 0xff00, 0xfeff, 0xffff }
632
633 /* The same information, inverted:
634 Return the class number of the smallest class containing
635 reg number REGNO. This could be a conditional expression
636 or could index an array. */
637
638 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[REGNO])
639
640 #define S_REGNO_P(REGNO) (((REGNO) - S0_REGNUM) < (unsigned) 8)
641 #define A_REGNO_P(REGNO) (((REGNO) - A0_REGNUM) < (unsigned) 8)
642
643 #define S_REG_P(X) (REG_P (X) && S_REGNO_P (REGNO (X)))
644 #define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X)))
645
646 /* The class value for index registers, and the one for base regs. */
647
648 #define INDEX_REG_CLASS INDEX_REGS
649 #define BASE_REG_CLASS INDEX_REGS
650
651 /* Get reg_class from a letter such as appears in the machine description. */
652 /* a => A_REGS
653 d => S_REGS ('s' is taken)
654 A => INDEX_REGS (i.e., A_REGS except sp) */
655
656 #define REG_CLASS_FROM_LETTER(C) \
657 reg_class_from_letter[(unsigned char) (C)]
658
659 /* The letters I, J, K, L and M in a register constraint string
660 can be used to stand for particular ranges of immediate operands.
661 This macro defines what the ranges are.
662 C is the letter, and VALUE is a constant value.
663 Return 1 if VALUE is in the range specified by C. */
664 /* 'I' is used to pass any CONST_INT and reject any CONST_DOUBLE.
665 CONST_DOUBLE integers are handled by G and H constraint chars. */
666
667 #define CONST_OK_FOR_LETTER_P(VALUE, C) 1
668
669 /* Similar, but for floating constants, and defining letters G and H.
670 Here VALUE is the CONST_DOUBLE rtx itself. */
671 /* Convex uses G, H:
672 value usable in ld.d (low word 0) or ld.l (high word all sign) */
673
674 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
675 (((C) == 'G' && LD_D_P (VALUE)) || \
676 ((C) == 'H' && LD_L_P (VALUE)) || \
677 0)
678
679 #define LD_D_P(X) (const_double_low_int (X) == 0)
680
681 #define LD_L_P(X) (const_double_low_int (X) >= 0 \
682 ? const_double_high_int (X) == 0 \
683 : const_double_high_int (X) == -1)
684
685 /* Optional extra constraints for this machine.
686 For Convex, 'Q' means that OP is a volatile MEM.
687 For volatile scalars, we use instructions that bypass the data cache. */
688
689 #define EXTRA_CONSTRAINT(OP, C) \
690 ((C) == 'Q' ? (GET_CODE (OP) == MEM && MEM_VOLATILE_P (OP) \
691 && ! TARGET_C1 && TARGET_VOLATILE_NOCACHE) \
692 : 0)
693
694 /* Given an rtx X being reloaded into a reg required to be
695 in class CLASS, return the class of reg to actually use.
696 In general this is just CLASS; but on some machines
697 in some cases it is preferable to use a more restrictive class. */
698
699 /* Put 2-word constants that can't be immediate operands into memory. */
700
701 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
702 ((GET_CODE (X) != CONST_DOUBLE \
703 || GET_MODE (X) == SFmode \
704 || LD_L_P (X) || LD_D_P (X)) ? (CLASS) : NO_REGS)
705
706 /* Return the maximum number of consecutive registers
707 needed to represent mode MODE in a register of class CLASS. */
708 #define CLASS_MAX_NREGS(CLASS, MODE) ((GET_MODE_SIZE (MODE) + 7) / 8)
709 \f
710 /* Stack layout; function entry, exit and calling. */
711
712 /* Define this if pushing a word on the stack
713 makes the stack pointer a smaller address. */
714 #define STACK_GROWS_DOWNWARD
715
716 /* Define this if the nominal address of the stack frame
717 is at the high-address end of the local variables;
718 that is, each additional local variable allocated
719 goes at a more negative offset in the frame. */
720 #define FRAME_GROWS_DOWNWARD
721
722 /* Define this if should default to -fcaller-saves. */
723 #define DEFAULT_CALLER_SAVES
724
725 /* Offset within stack frame to start allocating local variables at.
726 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
727 first local allocated. Otherwise, it is the offset to the BEGINNING
728 of the first local allocated. */
729 #define STARTING_FRAME_OFFSET 0
730
731 /* If we generate an insn to push BYTES bytes,
732 this says how many the stack pointer really advances by. */
733 #define PUSH_ROUNDING(BYTES) (((BYTES) + 3) & ~3)
734
735 /* Offset of first parameter from the argument pointer register value. */
736 #define FIRST_PARM_OFFSET(FNDECL) 0
737
738 /* Value is the number of bytes of arguments automatically
739 popped when returning from a subroutine call.
740 FUNDECL is the declaration node of the function (as a tree),
741 FUNTYPE is the data type of the function (as a tree),
742 or for a library call it is an identifier node for the subroutine name.
743 SIZE is the number of bytes of arguments passed on the stack. */
744
745 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) (SIZE)
746
747 /* Define how to find the value returned by a function.
748 VALTYPE is the data type of the value (as a tree).
749 If the precise function being called is known, FUNC is its FUNCTION_DECL;
750 otherwise, FUNC is 0. */
751
752 #define FUNCTION_VALUE(VALTYPE, FUNC) \
753 gen_rtx (REG, TYPE_MODE (VALTYPE), S0_REGNUM)
754
755 /* Define how to find the value returned by a library function
756 assuming the value has mode MODE. */
757
758 #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, S0_REGNUM)
759
760 /* Define this if PCC uses the nonreentrant convention for returning
761 structure and union values. */
762
763 #define PCC_STATIC_STRUCT_RETURN
764
765 /* 1 if N is a possible register number for a function value.
766 On the Convex, S0 is the only register thus used. */
767
768 #define FUNCTION_VALUE_REGNO_P(N) ((N) == S0_REGNUM)
769
770 /* 1 if N is a possible register number for function argument passing. */
771
772 #define FUNCTION_ARG_REGNO_P(N) 0
773 \f
774 /* Define a data type for recording info about an argument list
775 during the scan of that argument list. This data type should
776 hold all necessary information about the function itself
777 and about the args processed so far, enough to enable macros
778 such as FUNCTION_ARG to determine where the next arg should go. */
779 /* On convex, simply count the arguments in case TARGET_ARGCOUNT is set. */
780
781 #define CUMULATIVE_ARGS int
782
783 /* Initialize a variable CUM of type CUMULATIVE_ARGS
784 for a call to a function whose data type is FNTYPE.
785 For a library call, FNTYPE is 0. */
786
787 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
788 ((CUM) = 0)
789
790 /* Update the data in CUM to advance over an argument
791 of mode MODE and data type TYPE.
792 (TYPE is null for libcalls where that information may not be available.) */
793
794 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
795 ((CUM) += 1)
796
797 /* Define where to put the arguments to a function.
798 Value is zero to push the argument on the stack,
799 or a hard register in which to store the argument.
800
801 MODE is the argument's machine mode.
802 TYPE is the data type of the argument (as a tree).
803 This is null for libcalls where that information may
804 not be available.
805 CUM is a variable of type CUMULATIVE_ARGS which gives info about
806 the preceding args and about the function being called.
807 NAMED is nonzero if this argument is a named parameter
808 (otherwise it is an extra parameter matching an ellipsis).
809
810 Convex: all args go on the stack. But return the arg count
811 as the "next arg register" to be passed to gen_call. */
812
813 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
814 ((MODE) == VOIDmode ? GEN_INT ((CUM)) : 0)
815
816 /* This macro generates the assembly code for function entry.
817 FILE is a stdio stream to output the code to.
818 SIZE is an int: how many units of temporary storage to allocate.
819 Refer to the array `regs_ever_live' to determine which registers
820 to save; `regs_ever_live[I]' is nonzero if register number I
821 is ever used in the function. This macro is responsible for
822 knowing which registers should not be saved even if used. */
823
824 #define FUNCTION_PROLOGUE(FILE, SIZE) \
825 { \
826 int size = ((SIZE) + 7) & -8; \
827 if (size != 0) \
828 fprintf (FILE, "\tsub.w #%d,sp\n", size); \
829 }
830
831 /* This macro generates the assembly code for function exit,
832 on machines that need it. If FUNCTION_EPILOGUE is not defined
833 then individual return instructions are generated for each
834 return statement. Args are same as for FUNCTION_PROLOGUE. */
835
836 #define FUNCTION_EPILOGUE(FILE, SIZE) \
837 { \
838 /* Follow function with a zero to stop c34 icache prefetching. */ \
839 fprintf (FILE, "\tds.h 0\n"); \
840 }
841
842 /* Output assembler code for a block containing the constant parts
843 of a trampoline, leaving space for the variable parts. */
844
845 /* On convex, the code for a trampoline is
846 ld.w #<link>,s0
847 jmp <func> */
848
849 #define TRAMPOLINE_TEMPLATE(FILE) \
850 { \
851 fprintf (FILE, "\tld.w #69696969,s0\n"); \
852 fprintf (FILE, "\tjmp 52525252\n"); \
853 }
854
855 /* Length in units of the trampoline for entering a nested function. */
856
857 #define TRAMPOLINE_SIZE 12
858
859 /* Emit RTL insns to initialize the variable parts of a trampoline.
860 FNADDR is an RTX for the address of the function's pure code.
861 CXT is an RTX for the static chain value for the function. */
862
863 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
864 { \
865 emit_move_insn (gen_rtx (MEM, Pmode, plus_constant (TRAMP, 2)), CXT); \
866 emit_move_insn (gen_rtx (MEM, Pmode, plus_constant (TRAMP, 8)), FNADDR); \
867 emit_call_insn (gen_call_pop (gen_rtx (MEM, QImode, \
868 gen_rtx (SYMBOL_REF, Pmode, \
869 "__enable_execute_stack")), \
870 const0_rtx, const0_rtx, const0_rtx)); \
871 }
872
873 /* Output assembler code to FILE to increment profiler label # LABELNO
874 for profiling a function entry. */
875
876 #define FUNCTION_PROFILER(FILE, LABELNO) \
877 fprintf (FILE, "\tldea LP%d,a1\n\tcallq mcount\n", (LABELNO));
878
879 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
880 the stack pointer does not matter. The value is tested only in
881 functions that have frame pointers.
882 No definition is equivalent to always zero. */
883
884 #define EXIT_IGNORE_STACK 1
885
886 /* Store in the variable DEPTH the initial difference between the
887 frame pointer reg contents and the stack pointer reg contents,
888 as of the start of the function body. This depends on the layout
889 of the fixed parts of the stack frame and on how registers are saved. */
890 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
891 { (DEPTH) = (get_frame_size () + 7) & -8; }
892 \f
893 /* Addressing modes, and classification of registers for them. */
894
895 /* #define HAVE_POST_INCREMENT */
896 /* #define HAVE_POST_DECREMENT */
897
898 /* #define HAVE_PRE_DECREMENT */
899 /* #define HAVE_PRE_INCREMENT */
900
901 /* Macros to check register numbers against specific register classes. */
902
903 /* These assume that REGNO is a hard or pseudo reg number.
904 They give nonzero only if REGNO is a hard reg of the suitable class
905 or a pseudo reg currently allocated to a suitable hard reg.
906 Since they use reg_renumber, they are safe only once reg_renumber
907 has been allocated, which happens in local-alloc.c. */
908
909 #define REGNO_OK_FOR_INDEX_P(regno) \
910 ((regno) <= LAST_VIRTUAL_REGISTER \
911 ? regno_ok_for_index_p[regno] \
912 : regno_ok_for_index_p[reg_renumber[regno]])
913
914 #define REGNO_OK_FOR_BASE_P(regno) REGNO_OK_FOR_INDEX_P (regno)
915 \f
916 /* Maximum number of registers that can appear in a valid memory address. */
917
918 #define MAX_REGS_PER_ADDRESS 1
919
920 /* 1 if X is an rtx for a constant that is a valid address. */
921
922 #define CONSTANT_ADDRESS_P(X) \
923 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
924 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
925 || GET_CODE (X) == HIGH)
926
927 /* Nonzero if the constant value X is a legitimate general operand.
928 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
929
930 /* For convex, bounce 2-word constants that can't be immediate operands. */
931
932 #define LEGITIMATE_CONSTANT_P(X) \
933 (GET_CODE (X) != CONST_DOUBLE \
934 || GET_MODE (X) == SFmode \
935 || LD_L_P (X) || LD_D_P (X))
936
937 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
938 and check its validity for a certain class.
939 We have two alternate definitions for each of them.
940 The usual definition accepts all pseudo regs; the other rejects
941 them unless they have been allocated suitable hard regs.
942 The symbol REG_OK_STRICT causes the latter definition to be used.
943
944 Most source files want to accept pseudo regs in the hope that
945 they will get allocated to the class that the insn wants them to be in.
946 Source files for reload pass need to be strict.
947 After reload, it makes no difference, since pseudo regs have
948 been eliminated by then. */
949
950 #ifndef REG_OK_STRICT
951
952 /* Nonzero if X is a hard reg that can be used as an index
953 or if it is a pseudo reg. */
954 #define REG_OK_FOR_INDEX_P(X) \
955 (REGNO (X) > LAST_VIRTUAL_REGISTER || regno_ok_for_index_p[REGNO (X)])
956
957 /* Nonzero if X is a hard reg that can be used as a base reg
958 or if it is a pseudo reg. */
959 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
960
961 #else
962
963 /* Nonzero if X is a hard reg that can be used as an index. */
964 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
965
966 /* Nonzero if X is a hard reg that can be used as a base reg. */
967 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
968
969 #endif
970 \f
971 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
972 that is a valid memory address for an instruction.
973 The MODE argument is the machine mode for the MEM expression
974 that wants to use this address.
975
976 For Convex, valid addresses are
977 indirectable or (MEM indirectable)
978 where indirectable is
979 const, reg, (PLUS reg const)
980
981 We don't use indirection since with insn scheduling, load + indexing
982 is better. */
983
984 /* 1 if X is an address that we could indirect through. */
985 #define INDIRECTABLE_ADDRESS_P(X) \
986 (CONSTANT_ADDRESS_P (X) \
987 || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
988 || (GET_CODE (X) == PLUS \
989 && GET_CODE (XEXP (X, 0)) == REG \
990 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
991 && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
992 || (GET_CODE (X) == PLUS \
993 && GET_CODE (XEXP (X, 1)) == REG \
994 && REG_OK_FOR_BASE_P (XEXP (X, 1)) \
995 && CONSTANT_ADDRESS_P (XEXP (X, 0))))
996
997 /* Go to ADDR if X is a valid address. */
998 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
999 { register rtx xfoob = (X); \
1000 if (INDIRECTABLE_ADDRESS_P (xfoob)) \
1001 goto ADDR; \
1002 if (GET_CODE (xfoob) == PRE_DEC && XEXP (xfoob, 0) == stack_pointer_rtx) \
1003 goto ADDR; \
1004 }
1005 \f
1006 /* Try machine-dependent ways of modifying an illegitimate address
1007 to be legitimate. If we find one, return the new, valid address.
1008 This macro is used in only one place: `memory_address' in explow.c.
1009
1010 OLDX is the address as it was before break_out_memory_refs was called.
1011 In some cases it is useful to look at this to decide what needs to be done.
1012
1013 MODE and WIN are passed so that this macro can use
1014 GO_IF_LEGITIMATE_ADDRESS.
1015
1016 It is always safe for this macro to do nothing. It exists to recognize
1017 opportunities to optimize the output.
1018
1019 For Convex, nothing needs to be done. */
1020
1021 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {}
1022
1023 /* Go to LABEL if ADDR (a legitimate address expression)
1024 has an effect that depends on the machine mode it is used for. */
1025
1026 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
1027 \f
1028 /* Specify the machine mode that this machine uses
1029 for the index in the tablejump instruction. */
1030 #define CASE_VECTOR_MODE SImode
1031
1032 /* Define as C expression which evaluates to nonzero if the tablejump
1033 instruction expects the table to contain offsets from the address of the
1034 table.
1035 Do not define this if the table should contain absolute addresses. */
1036 /* #define CASE_VECTOR_PC_RELATIVE 1 */
1037
1038 /* Define this if the case instruction drops through after the table
1039 when the index is out of range. Don't define it if the case insn
1040 jumps to the default label instead. */
1041 /* #define CASE_DROPS_THROUGH */
1042
1043 /* Specify the tree operation to be used to convert reals to integers. */
1044 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1045
1046 /* This is the kind of divide that is easiest to do in the general case. */
1047 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1048
1049 /* Define this as 1 if `char' should by default be signed; else as 0. */
1050 #define DEFAULT_SIGNED_CHAR 1
1051
1052 /* This flag, if defined, says the same insns that convert to a signed fixnum
1053 also convert validly to an unsigned one. */
1054 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1055
1056 /* Max number of bytes we can move from memory to memory
1057 in one reasonably fast instruction. */
1058 #define MOVE_MAX 8
1059
1060 /* Define this if zero-extension is slow (more than one real instruction). */
1061 /* #define SLOW_ZERO_EXTEND */
1062
1063 /* Nonzero if access to memory by bytes is slow and undesirable. */
1064 #define SLOW_BYTE_ACCESS (! TARGET_C2)
1065
1066 /* Define if shifts truncate the shift count
1067 which implies one can omit a sign-extension or zero-extension
1068 of a shift count. */
1069 /* #define SHIFT_COUNT_TRUNCATED */
1070
1071 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1072 is done just by pretending it is already truncated. */
1073 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1074
1075 /* On Convex, it is as good to call a constant function address as to
1076 call an address kept in a register. */
1077 #define NO_FUNCTION_CSE
1078
1079 /* When a prototype says `char' or `short', really pass an `int'. */
1080 #define PROMOTE_PROTOTYPES
1081
1082 /* Specify the machine mode that pointers have.
1083 After generation of rtl, the compiler makes no further distinction
1084 between pointers and any other objects of this machine mode. */
1085 #define Pmode SImode
1086
1087 /* A function address in a call instruction
1088 is a byte address (for indexing purposes)
1089 so give the MEM rtx a byte's mode. */
1090 #define FUNCTION_MODE QImode
1091
1092 /* Compute the cost of computing a constant rtl expression RTX
1093 whose rtx-code is CODE. The body of this macro is a portion
1094 of a switch statement. If the code is computed here,
1095 return it with a return statement. Otherwise, break from the switch. */
1096
1097 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1098 case CONST: \
1099 case LABEL_REF: \
1100 case SYMBOL_REF: \
1101 case CONST_INT: \
1102 case CONST_DOUBLE: \
1103 return 0;
1104
1105 /* Provide the costs of a rtl expression. This is in the body of a
1106 switch on CODE. */
1107
1108 #define RTX_COSTS(RTX,CODE,OUTER_CODE) \
1109 case PLUS: \
1110 if (regno_pointer_flag != 0 \
1111 && GET_CODE (XEXP (RTX, 0)) == REG \
1112 && REGNO_POINTER_FLAG (REGNO (XEXP (RTX, 0))) \
1113 && GET_CODE (XEXP (RTX, 1)) == CONST_INT) \
1114 return 0; \
1115 else break; \
1116 case MULT: \
1117 return 4 * (char) (0x03060403 >> target_cpu * 8); \
1118 case ASHIFT: \
1119 case LSHIFTRT: \
1120 case ASHIFTRT: \
1121 return 4 * (char) (0x03010403 >> target_cpu * 8); \
1122 case MEM: \
1123 return 5;
1124
1125 /* Compute the cost of an address. This is meant to approximate the size
1126 and/or execution delay of an insn using that address. If the cost is
1127 approximated by the RTL complexity, including CONST_COSTS above, as
1128 is usually the case for CISC machines, this macro should not be defined.
1129 For aggressively RISCy machines, only one insn format is allowed, so
1130 this macro should be a constant. The value of this macro only matters
1131 for valid addresses. */
1132
1133 #define ADDRESS_COST(RTX) 0
1134
1135 /* Specify the cost of a branch insn; roughly the number of extra insns that
1136 should be added to avoid a branch. */
1137
1138 #define BRANCH_COST 0
1139
1140 /* Adjust the cost of dependences. */
1141
1142 #define ADJUST_COST(INSN,LINK,DEP,COST) \
1143 { \
1144 /* Antidependencies don't block issue. */ \
1145 if (REG_NOTE_KIND (LINK) != 0) \
1146 (COST) = 0; \
1147 /* C38 situations where delay depends on context */ \
1148 else if (TARGET_C38 \
1149 && GET_CODE (PATTERN (INSN)) == SET \
1150 && GET_CODE (PATTERN (DEP)) == SET) \
1151 { \
1152 enum attr_type insn_type = get_attr_type (INSN); \
1153 enum attr_type dep_type = get_attr_type (DEP); \
1154 /* index register must be ready one cycle early */ \
1155 if (insn_type == TYPE_MLDW || insn_type == TYPE_MLDL \
1156 || (insn_type == TYPE_MST \
1157 && reg_mentioned_p (SET_DEST (PATTERN (DEP)), \
1158 SET_SRC (PATTERN (INSN))))) \
1159 (COST) += 1; \
1160 /* alu forwarding off alu takes two */ \
1161 if (dep_type == TYPE_ALU \
1162 && insn_type != TYPE_ALU \
1163 && ! (insn_type == TYPE_MST \
1164 && SET_DEST (PATTERN (DEP)) == SET_SRC (PATTERN (INSN)))) \
1165 (COST) += 1; \
1166 } \
1167 }
1168
1169 /* Convex uses Vax or IEEE floats.
1170 Follow the host format. */
1171 #define TARGET_FLOAT_FORMAT HOST_FLOAT_FORMAT
1172
1173 /* But must prevent real.c from constructing Vax dfloats */
1174 #define REAL_VALUE_ATOF(X,S) atof (X)
1175 extern double atof();
1176
1177 /* Check a `double' value for validity for a particular machine mode. */
1178 #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
1179 OVERFLOW = check_float_value (MODE, &D, OVERFLOW)
1180 \f
1181 /* Tell final.c how to eliminate redundant test instructions. */
1182
1183 /* Here we define machine-dependent flags and fields in cc_status
1184 (see `conditions.h'). No extra ones are needed for convex. */
1185
1186 /* Store in cc_status the expressions
1187 that the condition codes will describe
1188 after execution of an instruction whose pattern is EXP.
1189 Do not alter them if the instruction would not alter the cc's. */
1190
1191 #define NOTICE_UPDATE_CC(EXP,INSN) {}
1192 \f
1193 /* Control the assembler format that we output. */
1194
1195 /* Output at beginning of assembler file. */
1196
1197 #if _IEEE_FLOAT_
1198 #define ASM_FILE_START(FILE) fprintf (FILE, ";NO_APP\n.fpmode ieee\n")
1199 #else
1200 #define ASM_FILE_START(FILE) fprintf (FILE, ";NO_APP\n.fpmode native\n")
1201 #endif
1202
1203 /* Output to assembler file text saying following lines
1204 may contain character constants, extra white space, comments, etc. */
1205
1206 #define ASM_APP_ON ";APP\n"
1207
1208 /* Output to assembler file text saying following lines
1209 no longer contain unusual constructs. */
1210
1211 #define ASM_APP_OFF ";NO_APP\n"
1212
1213 /* Alignment with Convex's assembler goes like this:
1214 .text can be .aligned up to a halfword.
1215 .data and .bss can be .aligned up to a longword.
1216 .lcomm is not supported, explicit declarations in .bss must be used instead.
1217 We get alignment for word and longword .text data by conventionally
1218 using .text 2 for word-aligned data and .text 3 for longword-aligned
1219 data. This requires that the data's size be a multiple of its alignment,
1220 which seems to be always true. */
1221
1222 /* Output before read-only data. */
1223
1224 #define TEXT_SECTION_ASM_OP (current_section_is_text = 1, ".text")
1225
1226 /* Output before writable data. */
1227
1228 #define DATA_SECTION_ASM_OP (current_section_is_text = 0, ".data")
1229
1230 /* Output before uninitialized data. */
1231
1232 #define BSS_SECTION_ASM_OP (current_section_is_text = 0, ".bss")
1233
1234 /* This is how to output an assembler line
1235 that says to advance the location counter
1236 to a multiple of 2**LOG bytes. */
1237
1238 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1239 if (current_section_is_text && (LOG) > 1) \
1240 fprintf (FILE, ".text %d\n", LOG); \
1241 else if (current_section_is_text) \
1242 fprintf (FILE, ".text\n.align %d\n", 1 << (LOG)); \
1243 else \
1244 fprintf (FILE, ".align %d\n", 1 << (LOG))
1245
1246 /* How to refer to registers in assembler output.
1247 This sequence is indexed by compiler's hard-register-number (see above). */
1248
1249 #define REGISTER_NAMES \
1250 { \
1251 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
1252 "sp", "a1", "a2", "a3", "a4", "a5", "ap", "fp", \
1253 }
1254
1255 /* This is BSD, so it wants DBX format. */
1256
1257 #define DBX_DEBUGGING_INFO
1258
1259 /* How to renumber registers for dbx and gdb. */
1260
1261 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1262
1263 /* Do not break .stabs pseudos into continuations. */
1264
1265 #define DBX_CONTIN_LENGTH 0
1266
1267 /* This is the char to use for continuation (in case we need to turn
1268 continuation back on). */
1269
1270 #define DBX_CONTIN_CHAR '?'
1271
1272 /* Don't use stab extensions until GDB v4 port is available for convex. */
1273
1274 #define DEFAULT_GDB_EXTENSIONS 0
1275 #define DBX_NO_XREFS
1276
1277 /* This is how to output the definition of a user-level label named NAME,
1278 such as the label on a static function or variable NAME. */
1279
1280 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1281 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1282
1283 /* This is how to output a command to make the user-level label named NAME
1284 defined for reference from other files. */
1285
1286 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1287 do { fputs (".globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1288
1289 /* The prefix to add to user-visible assembler symbols. */
1290
1291 #define USER_LABEL_PREFIX "_"
1292
1293 /* This is how to output an internal numbered label where
1294 PREFIX is the class of label and NUM is the number within the class. */
1295
1296 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1297 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1298
1299 /* Put case tables in .text 2, where they will be word-aligned */
1300
1301 #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \
1302 ASM_OUTPUT_ALIGN (FILE, 2); \
1303 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM)
1304
1305 #define ASM_OUTPUT_CASE_END(FILE,NUM,TABLE) \
1306 ASM_OUTPUT_ALIGN (FILE, 1)
1307
1308 /* This is how to store into the string LABEL
1309 the symbol_ref name of an internal numbered label where
1310 PREFIX is the class of label and NUM is the number within the class.
1311 This is suitable for output with `assemble_name'. */
1312
1313 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1314 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1315
1316 /* This is how to output an assembler line defining a `double' constant. */
1317
1318 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1319 outfloat (FILE, VALUE, "%.17e", "\tds.d ", "\n")
1320
1321 /* This is how to output an assembler line defining a `float' constant. */
1322
1323 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1324 outfloat (FILE, VALUE, "%.9e", "\tds.s ", "\n")
1325
1326 /* This is how to output an assembler line defining an `int' constant. */
1327
1328 #define ASM_OUTPUT_INT(FILE,VALUE) \
1329 { \
1330 fprintf (FILE, "\tds.w "); \
1331 output_addr_const (FILE, simplify_for_convex (VALUE)); \
1332 fprintf (FILE, "\n"); \
1333 }
1334
1335 /* Likewise for a `long long int' constant. */
1336
1337 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
1338 { \
1339 if (GET_CODE (VALUE) == CONST_DOUBLE) \
1340 fprintf (FILE, "\tds.w %d,%d\n", \
1341 const_double_high_int (VALUE), const_double_low_int (VALUE)); \
1342 else if (GET_CODE (VALUE) == CONST_INT) \
1343 { \
1344 int val = INTVAL (VALUE); \
1345 fprintf (FILE, "\tds.w %d,%d\n", val < 0 ? -1 : 0, val); \
1346 } \
1347 else \
1348 abort (); \
1349 }
1350
1351 /* Likewise for `char' and `short' constants. */
1352
1353 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1354 ( fprintf (FILE, "\tds.h "), \
1355 output_addr_const (FILE, (VALUE)), \
1356 fprintf (FILE, "\n"))
1357
1358 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1359 ( fprintf (FILE, "\tds.b "), \
1360 output_addr_const (FILE, (VALUE)), \
1361 fprintf (FILE, "\n"))
1362
1363 /* This is how to output an assembler line for a numeric constant byte. */
1364
1365 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1366 fprintf (FILE, "\tds.b %#x\n", (VALUE))
1367
1368 /* This is how to output a string */
1369
1370 #define ASM_OUTPUT_ASCII(FILE,STR,SIZE) do { \
1371 int i; \
1372 fprintf ((FILE), "\tds.b \""); \
1373 for (i = 0; i < (SIZE); i++) { \
1374 register int c = (STR)[i] & 0377; \
1375 if (c >= ' ' && c < 0177 && c != '\\' && c != '"') \
1376 putc (c, (FILE)); \
1377 else \
1378 fprintf ((FILE), "\\%03o", c);} \
1379 fprintf ((FILE), "\"\n");} while (0)
1380
1381 /* This is how to output an insn to push a register on the stack.
1382 It need not be very fast code. */
1383
1384 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1385 fprintf (FILE, "\tpsh.%c %s\n", \
1386 S_REGNO_P (REGNO) ? 'l' : 'w', \
1387 reg_names[REGNO])
1388
1389 /* This is how to output an insn to pop a register from the stack.
1390 It need not be very fast code. */
1391
1392 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1393 fprintf (FILE, "\tpop.%c %s\n", \
1394 S_REGNO_P (REGNO) ? 'l' : 'w', \
1395 reg_names[REGNO])
1396
1397 /* This is how to output an element of a case-vector that is absolute. */
1398
1399 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1400 fprintf (FILE, "\tds.w L%d\n", VALUE)
1401
1402 /* This is how to output an element of a case-vector that is relative.
1403 (not used on Convex) */
1404
1405 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1406 fprintf (FILE, "\tds.w L%d-L%d\n", VALUE, REL)
1407
1408 /* This is how to output an assembler line
1409 that says to advance the location counter by SIZE bytes. */
1410
1411 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1412 fprintf (FILE, "\tds.b %u(0)\n", (SIZE))
1413
1414 /* This says how to output an assembler line
1415 to define a global common symbol. */
1416
1417 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1418 ( fputs (".comm ", (FILE)), \
1419 assemble_name ((FILE), (NAME)), \
1420 fprintf ((FILE), ",%u\n", (ROUNDED)))
1421
1422 /* This says how to output an assembler line
1423 to define a local common symbol. */
1424
1425 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1426 ( bss_section (), \
1427 assemble_name ((FILE), (NAME)), \
1428 fprintf ((FILE), ":\tbs.b %u\n", (ROUNDED)))
1429
1430 /* Store in OUTPUT a string (made with alloca) containing
1431 an assembler-name for a local static variable named NAME.
1432 LABELNO is an integer which is different for each call. */
1433
1434 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1435 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1436 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1437
1438 /* Output an arg count before function entries. */
1439
1440 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
1441 asm_declare_function_name (FILE, NAME, DECL)
1442
1443 /* Define the parentheses used to group arithmetic operations
1444 in assembler code. */
1445
1446 #define ASM_OPEN_PAREN "("
1447 #define ASM_CLOSE_PAREN ")"
1448
1449 /* Define results of standard character escape sequences. */
1450 #define TARGET_BELL 007
1451 #define TARGET_BS 010
1452 #define TARGET_TAB 011
1453 #define TARGET_NEWLINE 012
1454 #define TARGET_VT 013
1455 #define TARGET_FF 014
1456 #define TARGET_CR 015
1457
1458 /* Print an instruction operand X on file FILE.
1459 CODE is the code from the %-spec that requested printing this operand;
1460 if `%z3' was used to print operand 3, then CODE is 'z'. */
1461
1462 #define PRINT_OPERAND(FILE, X, CODE) \
1463 print_operand (FILE, X, CODE)
1464
1465 /* Print a memory operand whose address is X, on file FILE. */
1466
1467 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1468 print_operand_address (FILE, ADDR)
1469 \f
1470 /* Do not put out GNU stabs for constructors and destructors.
1471 ld bounces them. */
1472
1473 #define FASCIST_ASSEMBLER
1474
1475 /* __gcc_cleanup is loader-aliased to __ap$do_registered_functions if we
1476 are linking against standard libc, 0 if old (-traditional) libc. */
1477
1478 #define EXIT_BODY \
1479 { \
1480 extern void __gcc_cleanup (); \
1481 if (__gcc_cleanup != _cleanup) \
1482 __gcc_cleanup (); \
1483 _cleanup (); \
1484 }
1485 \f
1486 /* Header for convex.c.
1487 Here at the end so we can use types defined above. */
1488
1489 extern int target_cpu;
1490 extern int current_section_is_text;
1491 extern enum reg_class regno_reg_class[];
1492 extern enum reg_class reg_class_from_letter[];
1493 extern char regno_ok_for_index_p_base[];
1494 #define regno_ok_for_index_p (regno_ok_for_index_p_base + 1)
1495
1496 extern int const_double_low_int ();
1497 extern int const_double_high_int ();
1498 extern char *output_cmp ();
1499 extern char *output_condjump ();
1500 extern char *output_call ();
1501 extern void gen_ap_for_call ();
1502 extern int check_float_value ();
1503 extern void asm_declare_function_name ();