1 /* Definitions of target machine for GNU compiler. Alliant FX version.
2 Copyright (C) 1989 Free Software Foundation, Inc.
3 Adapted from m68k.h by Paul Petersen (petersen@uicsrd.csrd.uiuc.edu)
4 and Joe Weening (weening@gang-of-four.stanford.edu).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
23 /* This file is based on m68k.h, simplified by removing support for
24 the Sun FPA and other things not applicable to the Alliant. Some
25 remnants of these features remain. */
27 /* Names to predefine in the preprocessor for this target machine. */
29 #define CPP_PREDEFINES "-Dmc68000 -Dalliant -Dunix -Asystem(unix) -Acpu(m68k) -Amachine(m68k)"
31 /* Print subsidiary information on the compiler version in use. */
33 #define TARGET_VERSION fprintf (stderr, " (Alliant)");
35 /* Run-time compilation parameters selecting different hardware
36 subsets. The Alliant IP is an mc68020. (Older mc68010-based IPs
37 are no longer supported.) The Alliant CE is 68020-compatible, and
38 also has floating point, vector and concurrency instructions.
40 Although the IP doesn't have floating point, it emulates it in the
41 operating system. Using this generally is faster than running code
42 compiled with -msoft-float, because the soft-float code still uses
43 (simulated) FP registers and ends up emulating several fmove{s,d}
44 instructions per call. So I don't recommend using soft-float for
45 any Alliant code. -- JSW
48 extern int target_flags
;
50 /* Macros used in the machine description to test the flags. */
52 /* Compile for a 68020 (not a 68000 or 68010). */
53 #define TARGET_68020 (target_flags & 1)
54 /* Compile CE insns for floating point (not library calls). */
55 #define TARGET_CE (target_flags & 2)
56 /* Compile using 68020 bitfield insns. */
57 #define TARGET_BITFIELD (target_flags & 4)
58 /* Compile with 16-bit `int'. */
59 #define TARGET_SHORT (target_flags & 040)
61 /* Default 3 means compile 68020 and CE instructions. We don't use
62 bitfield instructions because there appears to be a bug in the
63 implementation of bfins on the CE. */
65 #define TARGET_DEFAULT 3
67 /* Define __HAVE_CE__ in preprocessor according to the -m flags.
68 This will control the use of inline FP insns in certain macros.
69 Also inform the program which CPU this is for. */
71 #if TARGET_DEFAULT & 02
73 /* -mce is the default */
75 "%{!msoft-float:-D__HAVE_CE__ }\
76 %{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}"
80 /* -msoft-float is the default */
82 "%{mce:-D__HAVE_CE__ }\
83 %{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}"
87 /* Link with libg.a when debugging, for dbx's sake. */
89 #define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} "
91 /* Make the linker remove temporary labels, since the Alliant assembler
94 #define LINK_SPEC "-X"
96 /* Every structure or union's size must be a multiple of 2 bytes. */
98 #define STRUCTURE_SIZE_BOUNDARY 16
100 /* This is BSD, so it wants DBX format. */
102 #define DBX_DEBUGGING_INFO
104 /* Macro to define tables used to set the flags.
105 This is a list in braces of pairs in braces,
106 each pair being { "NAME", VALUE }
107 where VALUE is the bits to set or minus the bits to clear.
108 An empty string NAME is used to identify the default VALUE. */
110 #define TARGET_SWITCHES \
116 { "soft-float", -2}, \
117 { "nobitfield", -4}, \
119 { "noshort", -040}, \
120 { "", TARGET_DEFAULT}}
122 /* target machine storage layout */
124 /* Define this if most significant bit is lowest numbered
125 in instructions that operate on numbered bit-fields.
126 This is true for 68020 insns such as bfins and bfexts.
127 We make it true always by avoiding using the single-bit insns
128 except in special cases with constant bit numbers. */
129 #define BITS_BIG_ENDIAN 1
131 /* Define this if most significant byte of a word is the lowest numbered. */
132 /* That is true on the 68000. */
133 #define BYTES_BIG_ENDIAN 1
135 /* Define this if most significant word of a multiword number is the lowest
137 /* For 68000 we can decide arbitrarily
138 since there are no machine instructions for them. */
139 #define WORDS_BIG_ENDIAN 0
141 /* number of bits in an addressable storage unit */
142 #define BITS_PER_UNIT 8
144 /* Width in bits of a "word", which is the contents of a machine register.
145 Note that this is not necessarily the width of data type `int';
146 if using 16-bit ints on a 68000, this would still be 32.
147 But on a machine with 16-bit registers, this would be 16. */
148 #define BITS_PER_WORD 32
150 /* Width of a word, in units (bytes). */
151 #define UNITS_PER_WORD 4
153 /* Width in bits of a pointer.
154 See also the macro `Pmode' defined below. */
155 #define POINTER_SIZE 32
157 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
158 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
160 /* Boundary (in *bits*) on which stack pointer should be aligned. */
161 #define STACK_BOUNDARY 16
163 /* Allocation boundary (in *bits*) for the code of a function. */
164 #define FUNCTION_BOUNDARY 16
166 /* Alignment of field after `int : 0' in a structure. */
167 #define EMPTY_FIELD_BOUNDARY 16
169 /* No data type wants to be aligned rounder than this. */
170 #define BIGGEST_ALIGNMENT 16
172 /* Set this non-zero if move instructions will actually fail to work
173 when given unaligned data. */
174 #define STRICT_ALIGNMENT 1
176 /* Define number of bits in most basic integer type.
177 (If undefined, default is BITS_PER_WORD). */
179 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
181 /* Define these to avoid dependence on meaning of `int'.
182 Note that WCHAR_TYPE_SIZE is used in cexp.y,
183 where TARGET_SHORT is not available. */
185 #define WCHAR_TYPE "long int"
186 #define WCHAR_TYPE_SIZE 32
188 /* Standard register usage. */
190 /* Number of actual hardware registers.
191 The hardware registers are assigned numbers for the compiler
192 from 0 to just below FIRST_PSEUDO_REGISTER.
193 All registers that the compiler knows about must be given numbers,
194 even those that are not normally considered general registers.
195 For the Alliant, we give the data registers numbers 0-7,
196 the address registers numbers 010-017,
197 and the floating point registers numbers 020-027. */
198 #define FIRST_PSEUDO_REGISTER 24
200 /* 1 for registers that have pervasive standard uses
201 and are not available for the register allocator.
202 On the Alliant, these are a0 (argument pointer),
203 a6 (frame pointer) and a7 (stack pointer). */
204 #define FIXED_REGISTERS \
205 {0, 0, 0, 0, 0, 0, 0, 0, \
206 1, 0, 0, 0, 0, 0, 1, 1, \
207 0, 0, 0, 0, 0, 0, 0, 0 }
209 /* 1 for registers not available across function calls.
210 These must include the FIXED_REGISTERS and also any
211 registers that can be used without being saved.
212 The latter must include the registers where values are returned
213 and the register where structure-value addresses are passed.
214 Aside from that, you can include as many other registers as you like.
215 The Alliant calling sequence allows a function to use any register,
216 so we include them all here. */
218 #define CALL_USED_REGISTERS \
219 {1, 1, 1, 1, 1, 1, 1, 1, \
220 1, 1, 1, 1, 1, 1, 1, 1, \
221 1, 1, 1, 1, 1, 1, 1, 1 }
223 /* Return number of consecutive hard regs needed starting at reg REGNO
224 to hold something of mode MODE.
225 This is ordinarily the length in words of a value of mode MODE
226 but can be less for certain modes in special long registers.
228 On the Alliant, ordinary registers hold 32 bits worth;
229 for the FP registers, a single register is always enough for
230 any floating-point value. */
231 #define HARD_REGNO_NREGS(REGNO, MODE) \
232 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
233 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
235 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
236 On the Alliant, the cpu registers can hold any mode but the FP registers
237 can hold only floating point. */
238 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
239 ((REGNO) < 16 || GET_MODE_CLASS (MODE) == MODE_FLOAT \
240 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)
242 /* Value is 1 if it is a good idea to tie two pseudo registers
243 when one has mode MODE1 and one has mode MODE2.
244 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
245 for any hard reg, then this must be 0 for correct output. */
246 #define MODES_TIEABLE_P(MODE1, MODE2) \
247 (((MODE1) == SFmode || (MODE1) == DFmode \
248 || (MODE1) == SCmode || (MODE1) == DCmode) \
249 == ((MODE2) == SFmode || (MODE2) == DFmode \
250 || (MODE2) == SCmode || (MODE2) == DCmode))
252 /* Specify the registers used for certain standard purposes.
253 The values of these macros are register numbers. */
255 /* m68000 pc isn't overloaded on a register. */
256 /* #define PC_REGNUM */
258 /* Register to use for pushing function arguments. */
259 #define STACK_POINTER_REGNUM 15
261 /* Base register for access to local variables of the function. */
262 #define FRAME_POINTER_REGNUM 14
264 /* Value should be nonzero if functions must have frame pointers.
265 Zero means the frame pointer need not be set up (and parms
266 may be accessed via the stack pointer) in functions that seem suitable.
267 This is computed in `reload', in reload1.c. */
268 /* Set for now on Alliant until we find a way to make this work with
269 their calling sequence. */
270 #define FRAME_POINTER_REQUIRED 1
272 /* Base register for access to arguments of the function. */
273 #define ARG_POINTER_REGNUM 8
275 /* Register in which static-chain is passed to a function. */
276 #define STATIC_CHAIN_REGNUM 10
278 /* Register in which address to store a structure value
279 is passed to a function. */
280 #define STRUCT_VALUE_REGNUM 9
282 /* Define the classes of registers for register constraints in the
283 machine description. Also define ranges of constants.
285 One of the classes must always be named ALL_REGS and include all hard regs.
286 If there is more than one class, another class must be named NO_REGS
287 and contain no registers.
289 The name GENERAL_REGS must be the name of a class (or an alias for
290 another name such as ALL_REGS). This is the class of registers
291 that is allowed by "g" or "r" in a register constraint.
292 Also, registers outside this class are allocated only when
293 instructions express preferences for them.
295 The classes must be numbered in nondecreasing order; that is,
296 a larger-numbered class must never be contained completely
297 in a smaller-numbered class.
299 For any two classes, it is very desirable that there be another
300 class that represents their union. */
302 /* The Alliant has three kinds of registers, so eight classes would be
303 a complete set. One of them is not needed. */
305 enum reg_class
{ NO_REGS
, FP_REGS
, DATA_REGS
, DATA_OR_FP_REGS
,
306 ADDR_REGS
, GENERAL_REGS
, ALL_REGS
, LIM_REG_CLASSES
};
308 #define N_REG_CLASSES (int) LIM_REG_CLASSES
310 /* Give names of register classes as strings for dump file. */
312 #define REG_CLASS_NAMES \
313 { "NO_REGS", "FP_REGS", "DATA_REGS", "DATA_OR_FP_REGS", \
314 "ADDR_REGS", "GENERAL_REGS", "ALL_REGS" }
316 /* Define which registers fit in which classes.
317 This is an initializer for a vector of HARD_REG_SET
318 of length N_REG_CLASSES. */
320 #define REG_CLASS_CONTENTS \
323 0x00ff0000, /* FP_REGS */ \
324 0x000000ff, /* DATA_REGS */ \
325 0x00ff00ff, /* DATA_OR_FP_REGS */ \
326 0x0000ff00, /* ADDR_REGS */ \
327 0x0000ffff, /* GENERAL_REGS */ \
328 0x00ffffff /* ALL_REGS */ \
331 /* The same information, inverted:
332 Return the class number of the smallest class containing
333 reg number REGNO. This could be a conditional expression
334 or could index an array. */
336 extern enum reg_class regno_reg_class
[];
337 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3])
339 /* The class value for index registers, and the one for base regs. */
341 #define INDEX_REG_CLASS GENERAL_REGS
342 #define BASE_REG_CLASS ADDR_REGS
344 /* Get reg_class from a letter such as appears in the machine description. */
346 #define REG_CLASS_FROM_LETTER(C) \
347 ((C) == 'a' ? ADDR_REGS : \
348 ((C) == 'd' ? DATA_REGS : \
349 ((C) == 'f' ? FP_REGS : \
352 /* The letters I, J, K, L and M in a register constraint string
353 can be used to stand for particular ranges of immediate operands.
354 This macro defines what the ranges are.
355 C is the letter, and VALUE is a constant value.
356 Return 1 if VALUE is in the range specified by C.
358 For the 68000, `I' is used for the range 1 to 8
359 allowed as immediate shift counts and in addq.
360 `J' is used for the range of signed numbers that fit in 16 bits.
361 `K' is for numbers that moveq can't handle.
362 `L' is for range -8 to -1, range of values that can be added with subq. */
364 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
365 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
366 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
367 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
368 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : 0)
370 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
372 /* Given an rtx X being reloaded into a reg required to be
373 in class CLASS, return the class of reg to actually use.
374 In general this is just CLASS; but on some machines
375 in some cases it is preferable to use a more restrictive class.
376 On the 68000 series, use a data reg if possible when the
377 value is a constant in the range where moveq could be used
378 and we ensure that QImodes are reloaded into data regs. */
380 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
381 ((GET_CODE (X) == CONST_INT \
382 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
383 && (CLASS) != ADDR_REGS) \
385 : GET_MODE (X) == QImode \
389 /* Return the maximum number of consecutive registers
390 needed to represent mode MODE in a register of class CLASS. */
391 /* On the 68000, this is the size of MODE in words,
392 except in the FP regs, where a single reg is always enough. */
393 #define CLASS_MAX_NREGS(CLASS, MODE) \
394 ((CLASS) == FP_REGS ? 1 \
395 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
397 /* Moves between fp regs and other regs are two insns. */
398 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
399 ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
400 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS)) \
403 /* Stack layout; function entry, exit and calling. */
405 /* Define this if pushing a word on the stack
406 makes the stack pointer a smaller address. */
407 #define STACK_GROWS_DOWNWARD
409 /* Define this if the nominal address of the stack frame
410 is at the high-address end of the local variables;
411 that is, each additional local variable allocated
412 goes at a more negative offset in the frame. */
413 #define FRAME_GROWS_DOWNWARD
415 /* The Alliant uses -fcaller-saves by default. */
416 #define DEFAULT_CALLER_SAVES
418 /* Offset within stack frame to start allocating local variables at.
419 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
420 first local allocated. Otherwise, it is the offset to the BEGINNING
421 of the first local allocated. */
422 #define STARTING_FRAME_OFFSET -4
424 /* If we generate an insn to push BYTES bytes,
425 this says how many the stack pointer really advances by.
426 On the 68000, sp@- in a byte insn really pushes a word. */
427 #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1)
429 /* Offset of first parameter from the argument pointer register value. */
430 #define FIRST_PARM_OFFSET(FNDECL) 0
432 /* Value is the number of bytes of arguments automatically
433 popped when returning from a subroutine call.
434 FUNTYPE is the data type of the function (as a tree),
435 or for a library call it is an identifier node for the subroutine name.
436 SIZE is the number of bytes of arguments passed on the stack.
438 On the Alliant we define this as SIZE and make the calling sequence
439 (in alliant.md) pop the args. This wouldn't be necessary if we
440 could add to the pending stack adjustment the size of the argument
441 descriptors that are pushed after the arguments. */
443 #define RETURN_POPS_ARGS(FUNTYPE,SIZE) (SIZE)
445 /* Define how to find the value returned by a function.
446 VALTYPE is the data type of the value (as a tree).
447 If the precise function being called is known, FUNC is its FUNCTION_DECL;
448 otherwise, FUNC is 0. */
450 /* On the Alliant the return value is in FP0 if real, else D0. */
452 #define FUNCTION_VALUE(VALTYPE, FUNC) \
453 (TREE_CODE (VALTYPE) == REAL_TYPE \
454 ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \
455 : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))
457 /* Define how to find the value returned by a library function
458 assuming the value has mode MODE. */
460 /* On the Alliant the return value is in FP0 if real, else D0. The
461 Alliant library functions for floating-point emulation return their
462 values both in FP0 and in D0/D1. But since not all libgcc functions
463 return the results of these directly, we cannot assume that D0/D1
464 contain the values we expect on return from a libgcc function. */
466 #define LIBCALL_VALUE(MODE) \
467 (((MODE) == DFmode || (MODE) == SFmode) \
468 ? gen_rtx (REG, MODE, 16) \
469 : gen_rtx (REG, MODE, 0))
471 /* 1 if N is a possible register number for a function value.
472 On the Alliant, D0 and FP0 are the only registers thus used.
473 (No need to mention D1 when used as a pair with D0.) */
475 #define FUNCTION_VALUE_REGNO_P(N) (((N) & ~16) == 0)
477 /* Define this if PCC uses the nonreentrant convention for returning
478 structure and union values. */
480 #define PCC_STATIC_STRUCT_RETURN
482 /* 1 if N is a possible register number for function argument passing.
483 On the Alliant, no registers are used in this way. */
485 #define FUNCTION_ARG_REGNO_P(N) 0
487 /* Define a data type for recording info about an argument list
488 during the scan of that argument list. This data type should
489 hold all necessary information about the function itself
490 and about the args processed so far, enough to enable macros
491 such as FUNCTION_ARG to determine where the next arg should go.
493 On the Alliant, this is a single integer, which is a number of bytes
494 of arguments scanned so far. */
496 #define CUMULATIVE_ARGS int
498 /* Initialize a variable CUM of type CUMULATIVE_ARGS
499 for a call to a function whose data type is FNTYPE.
500 For a library call, FNTYPE is 0.
502 On the Alliant, the offset starts at 0. */
504 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \
507 /* Update the data in CUM to advance over an argument
508 of mode MODE and data type TYPE.
509 (TYPE is null for libcalls where that information may not be available.) */
511 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
512 ((CUM) += ((MODE) != BLKmode \
513 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
514 : (int_size_in_bytes (TYPE) + 3) & ~3))
516 /* Define where to put the arguments to a function.
517 Value is zero to push the argument on the stack,
518 or a hard register in which to store the argument.
520 MODE is the argument's machine mode.
521 TYPE is the data type of the argument (as a tree).
522 This is null for libcalls where that information may
524 CUM is a variable of type CUMULATIVE_ARGS which gives info about
525 the preceding args and about the function being called.
526 NAMED is nonzero if this argument is a named parameter
527 (otherwise it is an extra parameter matching an ellipsis). */
529 /* On the Alliant all args are pushed. */
531 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
533 /* For an arg passed partly in registers and partly in memory,
534 this is the number of registers used.
535 For args passed entirely in registers or entirely in memory, zero. */
537 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
539 /* This macro generates the assembly code for function entry.
540 FILE is a stdio stream to output the code to.
541 SIZE is an int: how many units of temporary storage to allocate.
542 Refer to the array `regs_ever_live' to determine which registers
543 to save; `regs_ever_live[I]' is nonzero if register number I
544 is ever used in the function. This macro is responsible for
545 knowing which registers should not be saved even if used.
546 The Alliant uses caller-saves, so this macro is very simple. */
548 #define FUNCTION_PROLOGUE(FILE, SIZE) \
549 { int fsize = ((SIZE) - STARTING_FRAME_OFFSET + 3) & -4; \
550 if (frame_pointer_needed) \
552 if (fsize < 0x8000) \
553 fprintf(FILE,"\tlinkw a6,#%d\n", -fsize); \
554 else if (TARGET_68020) \
555 fprintf(FILE,"\tlinkl a6,#%d\n", -fsize); \
557 fprintf(FILE,"\tlinkw a6,#0\n\tsubl #%d,sp\n", fsize); \
558 fprintf(FILE, "\tmovl a0,a6@(-4)\n" ); }}
560 /* Output assembler code to FILE to increment profiler label # LABELNO
561 for profiling a function entry. */
563 #define FUNCTION_PROFILER(FILE, LABELNO) \
564 fprintf (FILE, "\tjbsr __mcount_\n")
566 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
567 the stack pointer does not matter. The value is tested only in
568 functions that have frame pointers.
569 No definition is equivalent to always zero. */
571 #define EXIT_IGNORE_STACK 1
573 /* This macro generates the assembly code for function exit,
574 on machines that need it. If FUNCTION_EPILOGUE is not defined
575 then individual return instructions are generated for each
576 return statement. Args are same as for FUNCTION_PROLOGUE.
578 The function epilogue should not depend on the current stack pointer!
579 It should use the frame pointer only. This is mandatory because
580 of alloca; we also take advantage of it to omit stack adjustments
583 #define FUNCTION_EPILOGUE(FILE, SIZE) \
584 { if (frame_pointer_needed) \
585 fprintf (FILE, "\tunlk a6\n"); \
586 fprintf (FILE, "\trts\n"); }
588 /* Store in the variable DEPTH the initial difference between the
589 frame pointer reg contents and the stack pointer reg contents,
590 as of the start of the function body. This depends on the layout
591 of the fixed parts of the stack frame and on how registers are saved. */
593 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
597 for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \
598 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
600 for (regno = 0; regno < 16; regno++) \
601 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
603 (DEPTH) = offset - ((get_frame_size () + 3) & -4); \
606 /* Addressing modes, and classification of registers for them. */
608 #define HAVE_POST_INCREMENT
609 /* #define HAVE_POST_DECREMENT */
611 #define HAVE_PRE_DECREMENT
612 /* #define HAVE_PRE_INCREMENT */
614 /* Macros to check register numbers against specific register classes. */
616 /* These assume that REGNO is a hard or pseudo reg number.
617 They give nonzero only if REGNO is a hard reg of the suitable class
618 or a pseudo reg currently allocated to a suitable hard reg.
619 Since they use reg_renumber, they are safe only once reg_renumber
620 has been allocated, which happens in local-alloc.c. */
622 #define REGNO_OK_FOR_INDEX_P(REGNO) \
623 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
624 #define REGNO_OK_FOR_BASE_P(REGNO) \
625 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
626 #define REGNO_OK_FOR_DATA_P(REGNO) \
627 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
628 #define REGNO_OK_FOR_FP_P(REGNO) \
629 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
631 /* Now macros that check whether X is a register and also,
632 strictly, whether it is in a specified class.
634 These macros are specific to the 68000, and may be used only
635 in code for printing assembler insns and in conditions for
636 define_optimization. */
638 /* 1 if X is a data register. */
640 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
642 /* 1 if X is an fp register. */
644 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
646 /* 1 if X is an address register */
648 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
650 /* Maximum number of registers that can appear in a valid memory address. */
652 #define MAX_REGS_PER_ADDRESS 2
654 /* Recognize any constant value that is a valid address. */
656 #define CONSTANT_ADDRESS_P(X) \
657 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
658 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
659 || GET_CODE (X) == HIGH)
661 /* Nonzero if the constant value X is a legitimate general operand.
662 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
664 /* Alliant FP instructions don't take immediate operands, so this
665 forces them into memory. */
666 #define LEGITIMATE_CONSTANT_P(X) (GET_CODE (X) != CONST_DOUBLE)
668 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
669 and check its validity for a certain class.
670 We have two alternate definitions for each of them.
671 The usual definition accepts all pseudo regs; the other rejects
672 them unless they have been allocated suitable hard regs.
673 The symbol REG_OK_STRICT causes the latter definition to be used.
675 Most source files want to accept pseudo regs in the hope that
676 they will get allocated to the class that the insn wants them to be in.
677 Source files for reload pass need to be strict.
678 After reload, it makes no difference, since pseudo regs have
679 been eliminated by then. */
681 #ifndef REG_OK_STRICT
683 /* Nonzero if X is a hard reg that can be used as an index
684 or if it is a pseudo reg. */
685 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
686 /* Nonzero if X is a hard reg that can be used as a base reg
687 or if it is a pseudo reg. */
688 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
692 /* Nonzero if X is a hard reg that can be used as an index. */
693 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
694 /* Nonzero if X is a hard reg that can be used as a base reg. */
695 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
699 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
700 that is a valid memory address for an instruction.
701 The MODE argument is the machine mode for the MEM expression
702 that wants to use this address.
704 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
706 #define INDIRECTABLE_1_ADDRESS_P(X) \
707 (CONSTANT_ADDRESS_P (X) \
708 || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
709 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
710 && REG_P (XEXP (X, 0)) \
711 && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
712 || (GET_CODE (X) == PLUS \
713 && REG_P (XEXP (X, 0)) && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
714 && GET_CODE (XEXP (X, 1)) == CONST_INT \
715 && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000))
717 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
718 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
720 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
721 { if (GET_CODE (X) == LABEL_REF) goto ADDR; \
722 if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR; }
724 #define GO_IF_INDEXING(X, ADDR) \
725 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
726 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
727 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
728 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
730 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
731 { GO_IF_INDEXING (X, ADDR); \
732 if (GET_CODE (X) == PLUS) \
733 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
734 && (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100) \
735 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
736 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
737 && (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100) \
738 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
740 #define LEGITIMATE_INDEX_REG_P(X) \
741 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
742 || (GET_CODE (X) == SIGN_EXTEND \
743 && GET_CODE (XEXP (X, 0)) == REG \
744 && GET_MODE (XEXP (X, 0)) == HImode \
745 && REG_OK_FOR_INDEX_P (XEXP (X, 0))))
747 #define LEGITIMATE_INDEX_P(X) \
748 (LEGITIMATE_INDEX_REG_P (X) \
749 || (TARGET_68020 && GET_CODE (X) == MULT \
750 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
751 && GET_CODE (XEXP (X, 1)) == CONST_INT \
752 && (INTVAL (XEXP (X, 1)) == 2 \
753 || INTVAL (XEXP (X, 1)) == 4 \
754 || INTVAL (XEXP (X, 1)) == 8)))
756 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
757 { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
758 GO_IF_INDEXED_ADDRESS (X, ADDR); }
760 /* Try machine-dependent ways of modifying an illegitimate address
761 to be legitimate. If we find one, return the new, valid address.
762 This macro is used in only one place: `memory_address' in explow.c.
764 OLDX is the address as it was before break_out_memory_refs was called.
765 In some cases it is useful to look at this to decide what needs to be done.
767 MODE and WIN are passed so that this macro can use
768 GO_IF_LEGITIMATE_ADDRESS.
770 It is always safe for this macro to do nothing. It exists to recognize
771 opportunities to optimize the output.
773 For the 68000, we handle X+REG by loading X into a register R and
774 using R+REG. R will go in an address reg and indexing will be used.
775 However, if REG is a broken-out memory address or multiplication,
776 nothing needs to be done because REG can certainly go in an address reg. */
778 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
779 { register int ch = (X) != (OLDX); \
780 if (GET_CODE (X) == PLUS) \
781 { if (GET_CODE (XEXP (X, 0)) == MULT) \
782 ch = 1, XEXP (X, 0) = force_operand (XEXP (X, 0), 0); \
783 if (GET_CODE (XEXP (X, 1)) == MULT) \
784 ch = 1, XEXP (X, 1) = force_operand (XEXP (X, 1), 0); \
785 if (ch && GET_CODE (XEXP (X, 1)) == REG \
786 && GET_CODE (XEXP (X, 0)) == REG) \
788 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
789 if (GET_CODE (XEXP (X, 0)) == REG \
790 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
791 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
792 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
793 { register rtx temp = gen_reg_rtx (Pmode); \
794 register rtx val = force_operand (XEXP (X, 1), 0); \
795 emit_move_insn (temp, val); \
796 XEXP (X, 1) = temp; \
798 else if (GET_CODE (XEXP (X, 1)) == REG \
799 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
800 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
801 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
802 { register rtx temp = gen_reg_rtx (Pmode); \
803 register rtx val = force_operand (XEXP (X, 0), 0); \
804 emit_move_insn (temp, val); \
805 XEXP (X, 0) = temp; \
808 /* Go to LABEL if ADDR (a legitimate address expression)
809 has an effect that depends on the machine mode it is used for.
810 On the 68000, only predecrement and postincrement address depend thus
811 (the amount of decrement or increment being the length of the operand). */
813 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
814 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
816 /* Specify the machine mode that this machine uses
817 for the index in the tablejump instruction. */
818 #define CASE_VECTOR_MODE HImode
820 /* Define this if the tablejump instruction expects the table
821 to contain offsets from the address of the table.
822 Do not define this if the table should contain absolute addresses. */
823 #define CASE_VECTOR_PC_RELATIVE
825 /* Specify the tree operation to be used to convert reals to integers. */
826 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
828 /* This is the kind of divide that is easiest to do in the general case. */
829 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
831 /* Define this as 1 if `char' should by default be signed; else as 0. */
832 #define DEFAULT_SIGNED_CHAR 1
834 /* Max number of bytes we can move from memory to memory
835 in one reasonably fast instruction. */
838 /* Define this if zero-extension is slow (more than one real instruction). */
839 #define SLOW_ZERO_EXTEND
841 /* Nonzero if access to memory by bytes is slow and undesirable. */
842 #define SLOW_BYTE_ACCESS 0
844 /* Define if shifts truncate the shift count
845 which implies one can omit a sign-extension or zero-extension
847 #define SHIFT_COUNT_TRUNCATED
849 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
850 is done just by pretending it is already truncated. */
851 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
853 /* We assume that the store-condition-codes instructions store 0 for false
854 and some other value for true. This is the value stored for true. */
856 #define STORE_FLAG_VALUE -1
858 /* When a prototype says `char' or `short', really pass an `int'. */
859 #define PROMOTE_PROTOTYPES
861 /* Specify the machine mode that pointers have.
862 After generation of rtl, the compiler makes no further distinction
863 between pointers and any other objects of this machine mode. */
866 /* A function address in a call instruction
867 is a byte address (for indexing purposes)
868 so give the MEM rtx a byte's mode. */
869 #define FUNCTION_MODE QImode
871 /* Compute the cost of computing a constant rtl expression RTX
872 whose rtx-code is CODE. The body of this macro is a portion
873 of a switch statement. If the code is computed here,
874 return it with a return statement. Otherwise, break from the switch. */
876 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
878 /* Constant zero is super cheap due to clr instruction. */ \
879 if (RTX == const0_rtx) return 0; \
880 if ((unsigned) INTVAL (RTX) < 077) return 1; \
888 /* Check a `double' value for validity for a particular machine mode.
889 This is defined to avoid crashes outputting certain constants. */
891 #define CHECK_FLOAT_VALUE(mode, d) \
892 if ((mode) == SFmode) \
894 if ((d) > 3.4028234663852890e+38) \
895 { warning ("magnitude of value too large for `float'"); \
896 (d) = 3.4028234663852890e+38; } \
897 else if ((d) < -3.4028234663852890e+38) \
898 { warning ("magnitude of value too large for `float'"); \
899 (d) = -3.4028234663852890e+38; } \
900 else if (((d) > 0) && ((d) < 1.1754943508222873e-38)) \
902 else if (((d) < 0) && ((d) > -1.1754943508222873e-38)) \
906 /* Tell final.c how to eliminate redundant test instructions. */
908 /* Here we define machine-dependent flags and fields in cc_status
909 (see `conditions.h'). */
911 /* On the Alliant, floating-point instructions do not modify the
912 ordinary CC register. Only fcmp and ftest instructions modify the
913 floating-point CC register. We should actually keep track of what
914 both kinds of CC registers contain, but for now we only consider
915 the most recent instruction that has set either register. */
917 /* Set if the cc value came from a floating point test, so a floating
918 point conditional branch must be output. */
919 #define CC_IN_FP 04000
921 /* Store in cc_status the expressions
922 that the condition codes will describe
923 after execution of an instruction whose pattern is EXP.
924 Do not alter them if the instruction would not alter the cc's. */
926 /* On the 68000, all the insns to store in an address register
927 fail to set the cc's. However, in some cases these instructions
928 can make it possibly invalid to use the saved cc's. In those
929 cases we clear out some or all of the saved cc's so they won't be used. */
931 #define NOTICE_UPDATE_CC(EXP, INSN) \
933 if (GET_CODE (EXP) == SET) \
934 { if (ADDRESS_REG_P (SET_DEST (EXP)) || FP_REG_P (SET_DEST (EXP))) \
935 { if (cc_status.value1 \
936 && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value1)) \
937 cc_status.value1 = 0; \
938 if (cc_status.value2 \
939 && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value2)) \
940 cc_status.value2 = 0; } \
941 else if (GET_CODE (SET_SRC (EXP)) == MOD \
942 || GET_CODE (SET_SRC (EXP)) == UMOD \
943 || (GET_CODE (SET_SRC (EXP)) == TRUNCATE \
944 && (GET_CODE (XEXP (SET_SRC (EXP))) == MOD \
945 || GET_CODE (XEXP (SET_SRC (EXP))) == UMOD))) \
946 /* The swap insn produces cc's that don't correspond to the \
949 else if (SET_DEST (EXP) != cc0_rtx \
950 && (FP_REG_P (SET_SRC (EXP)) \
951 || GET_CODE (SET_SRC (EXP)) == FIX \
952 || GET_CODE (SET_SRC (EXP)) == FLOAT_TRUNCATE \
953 || GET_CODE (SET_SRC (EXP)) == FLOAT_EXTEND)) \
954 { CC_STATUS_INIT; } \
955 /* A pair of move insns doesn't produce a useful overall cc. */ \
956 else if (!FP_REG_P (SET_DEST (EXP)) \
957 && !FP_REG_P (SET_SRC (EXP)) \
958 && GET_MODE_SIZE (GET_MODE (SET_SRC (EXP))) > 4 \
959 && (GET_CODE (SET_SRC (EXP)) == REG \
960 || GET_CODE (SET_SRC (EXP)) == MEM \
961 || GET_CODE (SET_SRC (EXP)) == CONST_DOUBLE))\
962 { CC_STATUS_INIT; } \
963 else if (GET_CODE (SET_SRC (EXP)) == CALL) \
964 { CC_STATUS_INIT; } \
965 else if (XEXP (EXP, 0) != pc_rtx) \
966 { cc_status.flags = 0; \
967 cc_status.value1 = XEXP (EXP, 0); \
968 cc_status.value2 = XEXP (EXP, 1); } } \
969 else if (GET_CODE (EXP) == PARALLEL \
970 && GET_CODE (XVECEXP (EXP, 0, 0)) == SET) \
972 if (ADDRESS_REG_P (XEXP (XVECEXP (EXP, 0, 0), 0))) \
974 else if (XEXP (XVECEXP (EXP, 0, 0), 0) != pc_rtx) \
975 { cc_status.flags = 0; \
976 cc_status.value1 = XEXP (XVECEXP (EXP, 0, 0), 0); \
977 cc_status.value2 = XEXP (XVECEXP (EXP, 0, 0), 1); } } \
978 else CC_STATUS_INIT; \
979 if (cc_status.value2 != 0 \
980 && ADDRESS_REG_P (cc_status.value2) \
981 && GET_MODE (cc_status.value2) == QImode) \
983 if (cc_status.value2 != 0) \
984 switch (GET_CODE (cc_status.value2)) \
985 { case PLUS: case MINUS: case MULT: \
986 case DIV: case UDIV: case MOD: case UMOD: case NEG: \
987 case ASHIFT: case LSHIFT: case ASHIFTRT: case LSHIFTRT: \
988 case ROTATE: case ROTATERT: \
989 if (GET_MODE (cc_status.value2) != VOIDmode) \
990 cc_status.flags |= CC_NO_OVERFLOW; \
993 /* (SET r1 (ZERO_EXTEND r2)) on this machine
994 ends with a move insn moving r2 in r2's mode.
995 Thus, the cc's are set for r2.
996 This can set N bit spuriously. */ \
997 cc_status.flags |= CC_NOT_NEGATIVE; } \
998 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \
999 && cc_status.value2 \
1000 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \
1001 cc_status.value2 = 0; \
1002 if ((cc_status.value1 && FP_REG_P (cc_status.value1)) \
1003 || (cc_status.value2 && FP_REG_P (cc_status.value2))) \
1004 cc_status.flags = CC_IN_FP; }
1006 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1007 { if (cc_prev_status.flags & CC_IN_FP) \
1009 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1013 /* Control the assembler format that we output. */
1015 /* Output at beginning of assembler file. */
1017 #define ASM_FILE_START(FILE) \
1018 fprintf (FILE, "#NO_APP\n");
1020 /* Output to assembler file text saying following lines
1021 may contain character constants, extra white space, comments, etc. */
1023 #define ASM_APP_ON "#APP\n"
1025 /* Output to assembler file text saying following lines
1026 no longer contain unusual constructs. */
1028 #define ASM_APP_OFF "#NO_APP\n"
1030 /* Output before read-only data. */
1032 #define TEXT_SECTION_ASM_OP ".text"
1034 /* Output before writable data. */
1036 #define DATA_SECTION_ASM_OP ".data"
1038 /* How to refer to registers in assembler output.
1039 This sequence is indexed by compiler's hard-register-number (see above). */
1041 #define REGISTER_NAMES \
1042 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1043 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1044 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" }
1046 /* How to renumber registers for dbx and gdb.
1047 On the Sun-3, the floating point registers have numbers
1048 18 to 25, not 16 to 23 as they do in the compiler. */
1049 /* (On the Alliant, dbx isn't working yet at all. */
1051 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1053 /* This is how to output the definition of a user-level label named NAME,
1054 such as the label on a static function or variable NAME. */
1056 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1057 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1059 /* This is how to output a command to make the user-level label named NAME
1060 defined for reference from other files. */
1062 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1063 do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1065 /* This is how to output a reference to a user-level label named NAME.
1066 `assemble_name' uses this. */
1068 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1069 fprintf (FILE, "_%s", NAME)
1071 /* This is how to output an internal numbered label where
1072 PREFIX is the class of label and NUM is the number within the class. */
1074 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1075 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1077 /* This is how to store into the string LABEL
1078 the symbol_ref name of an internal numbered label where
1079 PREFIX is the class of label and NUM is the number within the class.
1080 This is suitable for output with `assemble_name'. */
1082 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1083 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1085 /* This is how to output an assembler line defining a `double' constant. */
1087 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1088 do { union { double d; long v[2];} tem; \
1090 fprintf (FILE, "\t.long 0x%x,0x%x\n", tem.v[0], tem.v[1]); \
1093 /* This is how to output an assembler line defining a `float' constant. */
1095 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1096 do { union { float f; long l;} tem; \
1098 fprintf (FILE, "\t.long 0x%x\n", tem.l); \
1101 /* This is how to output an assembler line defining an `int' constant. */
1103 #define ASM_OUTPUT_INT(FILE,VALUE) \
1104 ( fprintf (FILE, "\t.long "), \
1105 output_addr_const (FILE, (VALUE)), \
1106 fprintf (FILE, "\n"))
1108 /* Likewise for `char' and `short' constants. */
1110 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1111 ( fprintf (FILE, "\t.word "), \
1112 output_addr_const (FILE, (VALUE)), \
1113 fprintf (FILE, "\n"))
1115 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1116 ( fprintf (FILE, "\t.byte "), \
1117 output_addr_const (FILE, (VALUE)), \
1118 fprintf (FILE, "\n"))
1120 #define ASM_OUTPUT_ASCII(FILE,PTR,SIZE) \
1121 { int i; unsigned char *pp = (unsigned char *) (PTR); \
1122 fprintf((FILE), "\t.byte %d", (unsigned int)*pp++); \
1123 for (i = 1; i < (SIZE); ++i, ++pp) { \
1125 fprintf((FILE), "\n\t.byte %d", (unsigned int) *pp); \
1127 fprintf((FILE), ",%d", (unsigned int) *pp); } \
1128 fprintf ((FILE), "\n"); }
1130 /* This is how to output an assembler line for a numeric constant byte. */
1132 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1133 fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1135 /* This is how to output an insn to push a register on the stack.
1136 It need not be very fast code. */
1138 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1139 fprintf (FILE, "\tmovl %s,sp@-\n", reg_names[REGNO])
1141 /* This is how to output an insn to pop a register from the stack.
1142 It need not be very fast code. */
1144 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1145 fprintf (FILE, "\tmovl sp@+,%s\n", reg_names[REGNO])
1147 /* This is how to output an element of a case-vector that is absolute.
1148 (The 68000 does not use such vectors,
1149 but we must define this macro anyway.) */
1151 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1152 fprintf (FILE, "\t.long L%d\n", VALUE)
1154 /* This is how to output an element of a case-vector that is relative. */
1156 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1157 fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL)
1159 /* This is how to output an assembler line
1160 that says to advance the location counter
1161 to a multiple of 2**LOG bytes. */
1163 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1165 fprintf (FILE, "\t.even\n"); \
1166 else if ((LOG) != 0) \
1167 fprintf (FILE, "\t.align %dn", (LOG));
1169 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1170 fprintf (FILE, "\t. = . + %u\n", (SIZE))
1172 /* This says how to output an assembler line
1173 to define a global common symbol. */
1175 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1176 ( fputs ("\t.comm ", (FILE)), \
1177 assemble_name ((FILE), (NAME)), \
1178 fprintf ((FILE), ",%u\n", (ROUNDED)))
1180 /* This says how to output an assembler line
1181 to define a local common symbol. */
1183 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1184 ( fputs ("\t.lcomm ", (FILE)), \
1185 assemble_name ((FILE), (NAME)), \
1186 fprintf ((FILE), ",%u\n", (ROUNDED)))
1188 /* Store in OUTPUT a string (made with alloca) containing
1189 an assembler-name for a local static variable named NAME.
1190 LABELNO is an integer which is different for each call. */
1192 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1193 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1194 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1196 /* Define the parentheses used to group arithmetic operations
1197 in assembler code. */
1199 #define ASM_OPEN_PAREN "("
1200 #define ASM_CLOSE_PAREN ")"
1202 /* Define results of standard character escape sequences. */
1203 #define TARGET_BELL 007
1204 #define TARGET_BS 010
1205 #define TARGET_TAB 011
1206 #define TARGET_NEWLINE 012
1207 #define TARGET_VT 013
1208 #define TARGET_FF 014
1209 #define TARGET_CR 015
1211 /* Print operand X (an rtx) in assembler syntax to file FILE.
1212 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1213 For `%' followed by punctuation, CODE is the punctuation and X is null.
1215 On the Alliant, we use several CODE characters:
1216 '.' for dot needed in Motorola-style opcode names.
1217 '-' for an operand pushing on the stack:
1218 sp@-, -(sp) or -(%sp) depending on the style of syntax.
1219 '+' for an operand pushing on the stack:
1220 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1221 '@' for a reference to the top word on the stack:
1222 sp@, (sp) or (%sp) depending on the style of syntax.
1223 '#' for an immediate operand prefix (# in MIT and Motorola syntax
1224 but & in SGS syntax).
1225 '!' for the cc register (used in an `and to cc' insn).
1227 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1228 'd' to force memory addressing to be absolute, not relative.
1229 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1230 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1231 or print pair of registers as rx:ry. */
1233 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1234 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1235 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!')
1237 #define PRINT_OPERAND(FILE, X, CODE) \
1239 if (CODE == '.') ; \
1240 else if (CODE == '#') fprintf (FILE, "#"); \
1241 else if (CODE == '-') fprintf (FILE, "sp@-"); \
1242 else if (CODE == '+') fprintf (FILE, "sp@+"); \
1243 else if (CODE == '@') fprintf (FILE, "sp@"); \
1244 else if (CODE == '!') fprintf (FILE, "cc"); \
1245 else if ((X) == 0 ) ; \
1246 else if (GET_CODE (X) == REG) \
1247 { if (REGNO (X) < 16 && (CODE == 'y' || CODE == 'x') && GET_MODE (X) == DFmode) \
1248 fprintf (FILE, "%s,%s", reg_names[REGNO (X)], reg_names[REGNO (X)+1]); \
1250 fprintf (FILE, "%s", reg_names[REGNO (X)]); \
1252 else if (GET_CODE (X) == MEM) \
1254 output_address (XEXP (X, 0)); \
1255 if (CODE == 'd' && ! TARGET_68020 \
1256 && CONSTANT_ADDRESS_P (XEXP (X, 0)) \
1257 && !(GET_CODE (XEXP (X, 0)) == CONST_INT \
1258 && INTVAL (XEXP (X, 0)) < 0x8000 \
1259 && INTVAL (XEXP (X, 0)) >= -0x8000)) \
1260 fprintf (FILE, ":l"); \
1262 else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \
1263 { union { double d; int i[2]; } u; \
1264 union { float f; int i; } u1; \
1265 u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \
1268 fprintf (FILE, "#0r%.9g", u1.f); \
1270 fprintf (FILE, "#0x%x", u1.i); } \
1271 else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != DImode) \
1272 { union { double d; int i[2]; } u; \
1273 u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \
1274 fprintf (FILE, "#0r%.20g", u.d); } \
1275 else { putc ('#', FILE); output_addr_const (FILE, X); }}
1277 /* Note that this contains a kludge that knows that the only reason
1278 we have an address (plus (label_ref...) (reg...))
1279 is in the insn before a tablejump, and we know that m68k.md
1280 generates a label LInnn: on such an insn. */
1281 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1282 { register rtx reg1, reg2, breg, ireg; \
1283 register rtx addr = ADDR; \
1284 static char *sz = ".BW.L...D"; \
1286 switch (GET_CODE (addr)) \
1289 fprintf (FILE, "%s@", reg_names[REGNO (addr)]); \
1292 fprintf (FILE, "%s@-", reg_names[REGNO (XEXP (addr, 0))]); \
1295 fprintf (FILE, "%s@+", reg_names[REGNO (XEXP (addr, 0))]); \
1298 reg1 = 0; reg2 = 0; \
1299 ireg = 0; breg = 0; \
1301 if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) \
1303 offset = XEXP (addr, 0); \
1304 addr = XEXP (addr, 1); \
1306 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) \
1308 offset = XEXP (addr, 1); \
1309 addr = XEXP (addr, 0); \
1311 if (GET_CODE (addr) != PLUS) ; \
1312 else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) \
1314 reg1 = XEXP (addr, 0); \
1315 addr = XEXP (addr, 1); \
1317 else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) \
1319 reg1 = XEXP (addr, 1); \
1320 addr = XEXP (addr, 0); \
1322 else if (GET_CODE (XEXP (addr, 0)) == MULT) \
1324 reg1 = XEXP (addr, 0); \
1325 addr = XEXP (addr, 1); \
1327 else if (GET_CODE (XEXP (addr, 1)) == MULT) \
1329 reg1 = XEXP (addr, 1); \
1330 addr = XEXP (addr, 0); \
1332 else if (GET_CODE (XEXP (addr, 0)) == REG) \
1334 reg1 = XEXP (addr, 0); \
1335 addr = XEXP (addr, 1); \
1337 else if (GET_CODE (XEXP (addr, 1)) == REG) \
1339 reg1 = XEXP (addr, 1); \
1340 addr = XEXP (addr, 0); \
1342 if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT \
1343 || GET_CODE (addr) == SIGN_EXTEND) \
1344 { if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; } \
1345 /* for OLD_INDEXING \
1346 else if (GET_CODE (addr) == PLUS) \
1348 if (GET_CODE (XEXP (addr, 0)) == REG) \
1350 reg2 = XEXP (addr, 0); \
1351 addr = XEXP (addr, 1); \
1353 else if (GET_CODE (XEXP (addr, 1)) == REG) \
1355 reg2 = XEXP (addr, 1); \
1356 addr = XEXP (addr, 0); \
1360 if (offset != 0) { if (addr != 0) abort (); addr = offset; } \
1361 if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND \
1362 || GET_CODE (reg1) == MULT)) \
1363 || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) \
1364 { breg = reg2; ireg = reg1; } \
1365 else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) \
1366 { breg = reg1; ireg = reg2; } \
1367 if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF) \
1369 if (GET_CODE (ireg) == MULT) \
1370 { scale = INTVAL (XEXP (ireg, 1)); \
1371 ireg = XEXP (ireg, 0); } \
1372 if (GET_CODE (ireg) == SIGN_EXTEND) \
1373 fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:W", \
1374 CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1375 CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1376 reg_names[REGNO (XEXP (ireg, 0))]); \
1378 fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L", \
1379 CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1380 CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1381 reg_names[REGNO (ireg)]); \
1382 fprintf (FILE, ":%c", sz[scale]); \
1385 if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF) \
1386 { fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L:B]", \
1387 CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1388 CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1389 reg_names[REGNO (breg)]); \
1391 if (ireg != 0 || breg != 0) \
1395 if (addr && GET_CODE (addr) == LABEL_REF) abort (); \
1396 fprintf (FILE, "%s@", reg_names[REGNO (breg)]); \
1398 putc( '(', FILE ); \
1399 output_addr_const (FILE, addr); \
1401 if (GET_CODE(addr) == CONST_INT) { \
1402 int size_of = 1, val = INTVAL(addr); \
1403 if (val < -0x8000 || val >= 0x8000) \
1405 else if (val < -0x80 || val >= 0x80) \
1407 fprintf(FILE, ":%c", sz[size_of]); \
1410 fprintf(FILE, ":L"); } \
1411 putc( ')', FILE ); } \
1414 if (ireg != 0 && GET_CODE (ireg) == MULT) \
1415 { scale = INTVAL (XEXP (ireg, 1)); \
1416 ireg = XEXP (ireg, 0); } \
1417 if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) \
1418 fprintf (FILE, "%s:W", reg_names[REGNO (XEXP (ireg, 0))]); \
1419 else if (ireg != 0) \
1420 fprintf (FILE, "%s:L", reg_names[REGNO (ireg)]); \
1421 fprintf (FILE, ":%c", sz[scale]); \
1426 else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF) \
1427 { fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L:B]", \
1428 CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1429 CODE_LABEL_NUMBER (XEXP (addr, 0)), \
1430 reg_names[REGNO (reg1)]); \
1433 if (GET_CODE (addr) == CONST_INT \
1434 && INTVAL (addr) < 0x8000 \
1435 && INTVAL (addr) >= -0x8000) \
1436 fprintf (FILE, "%d:W", INTVAL (addr)); \
1438 output_addr_const (FILE, addr); \