1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
40 /* Forward declarations. */
41 void print_operand_address ();
44 static int h8300_interrupt_function_p
PROTO ((tree
));
45 static int h8300_monitor_function_p
PROTO ((tree
));
46 static int h8300_os_task_function_p
PROTO ((tree
));
48 /* CPU_TYPE, says what cpu we're compiling for. */
51 /* True if the current function is an interrupt handler
52 (either via #pragma or an attribute specification). */
53 int interrupt_handler
;
55 /* True if the current fucntion is an OS Task
56 (via an attribute specification). */
59 /* True if the current function is a monitor
60 (via an attribute specification). */
63 /* True if a #pragma saveall has been seen for the current function. */
66 static char *names_big
[] =
67 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7"};
69 static char *names_extended
[] =
70 {"er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7"};
72 static char *names_upper_extended
[] =
73 {"e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7"};
75 /* Points to one of the above. */
76 /* ??? The above could be put in an array indexed by CPU_TYPE. */
79 /* Various operations needed by the following, indexed by CPU_TYPE. */
81 static char *h8_push_ops
[2] =
83 static char *h8_pop_ops
[2] =
85 static char *h8_mov_ops
[2] =
88 char *h8_push_op
, *h8_pop_op
, *h8_mov_op
;
90 /* Initialize various cpu specific globals at start up. */
97 cpu_type
= (int) CPU_H8300
;
98 h8_reg_names
= names_big
;
102 cpu_type
= (int) CPU_H8300H
;
103 h8_reg_names
= names_extended
;
105 h8_push_op
= h8_push_ops
[cpu_type
];
106 h8_pop_op
= h8_pop_ops
[cpu_type
];
107 h8_mov_op
= h8_mov_ops
[cpu_type
];
115 static char *names_small
[] =
116 {"r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
117 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"};
119 return names_small
[REGNO (x
) * 2 + b
];
122 /* REGNO must be saved/restored across calls if this macro is true. */
124 #define WORD_REG_USED(regno) \
128 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
129 || (regs_ever_live[regno] & !call_used_regs[regno])))
131 /* Output assembly language to FILE for the operation OP with operand size
132 SIZE to adjust the stack pointer. */
135 dosize (file
, op
, size
)
140 /* On the h8300h, for sizes <= 8 bytes it is as good or
141 better to use adds/subs insns rather than add.l/sub.l
142 with an immediate value. */
143 if (size
> 4 && size
<= 8 && TARGET_H8300H
)
145 /* Crank the size down to <= 4 */
146 fprintf (file
, "\t%ss\t#%d,sp\n", op
, 4);
155 fprintf (file
, "\t%ss\t#%d,sp\n", op
, 4);
160 fprintf (file
, "\t%ss\t#%d,sp\n", op
, 2);
162 /* Fall through... */
165 fprintf (file
, "\t%ss\t#%d,sp\n", op
, size
);
172 fprintf (file
, "\tmov.w\t#%d,r3\n\t%s.w\tr3,sp\n", size
, op
);
174 fprintf (file
, "\t%s\t#%d,sp\n", op
, size
);
180 /* Output assembly language code for the function prologue. */
181 static int push_order
[FIRST_PSEUDO_REGISTER
] =
182 {6, 5, 4, 3, 2, 1, 0, -1, -1};
183 static int pop_order
[FIRST_PSEUDO_REGISTER
] =
184 {0, 1, 2, 3, 4, 5, 6, -1, -1};
186 /* This is what the stack looks like after the prolog of
187 a function with a frame has been set up:
193 <saved registers> <- sp
195 This is what the stack looks like after the prolog of
196 a function which doesn't have a frame:
201 <saved registers> <- sp
205 function_prologue (file
, size
)
209 register int mask
= 0;
210 int fsize
= (size
+ STACK_BOUNDARY
/ 8 - 1) & -STACK_BOUNDARY
/ 8;
213 /* Note a function with the interrupt attribute and set interrupt_handler
215 if (h8300_interrupt_function_p (current_function_decl
))
216 interrupt_handler
= 1;
218 /* If the current function has the OS_Task attribute set, then
219 we have a naked prologue. */
220 if (h8300_os_task_function_p (current_function_decl
))
222 fprintf (file
, ";OS_Task prologue\n");
227 if (h8300_monitor_function_p (current_function_decl
))
229 /* My understanding of monitor functions is they act just
230 like interrupt functions, except the prologue must
232 fprintf (file
, ";monitor prologue\n");
233 interrupt_handler
= 1;
235 fprintf (file
, "\torc\t#128,ccr\n");
238 if (frame_pointer_needed
)
241 fprintf (file
, "\t%s\t%s\n", h8_push_op
,
242 h8_reg_names
[FRAME_POINTER_REGNUM
]);
243 fprintf (file
, "\t%s\t%s,%s\n", h8_mov_op
,
244 h8_reg_names
[STACK_POINTER_REGNUM
],
245 h8_reg_names
[FRAME_POINTER_REGNUM
]);
247 /* leave room for locals */
248 dosize (file
, "sub", fsize
);
250 /* Push the rest of the registers */
251 for (idx
= 0; idx
< FIRST_PSEUDO_REGISTER
; idx
++)
253 int regno
= push_order
[idx
];
255 if (regno
>= 0 && WORD_REG_USED (regno
) && regno
!= FRAME_POINTER_REGNUM
)
256 fprintf (file
, "\t%s\t%s\n", h8_push_op
, h8_reg_names
[regno
]);
261 dosize (file
, "sub", fsize
);
262 for (idx
= 0; idx
< FIRST_PSEUDO_REGISTER
; idx
++)
264 int regno
= push_order
[idx
];
266 if (regno
>= 0 && WORD_REG_USED (regno
))
267 fprintf (file
, "\t%s\t%s\n", h8_push_op
, h8_reg_names
[regno
]);
272 /* Output assembly language code for the function epilogue. */
275 function_epilogue (file
, size
)
280 register int mask
= 0;
281 int fsize
= (size
+ STACK_BOUNDARY
/ 8 - 1) & -STACK_BOUNDARY
/ 8;
285 rtx insn
= get_last_insn ();
289 /* OS_Task epilogues are nearly naked -- they just have an
291 fprintf (file
, ";OS_task epilogue\n");
292 fprintf (file
, "\trts\n");
296 /* monitor epilogues are the same as interrupt function epilogues.
297 Just make a note that we're in an monitor epilogue. */
299 fprintf(file
, ";monitor epilogue\n");
301 /* If the last insn was a BARRIER, we don't have to write any code. */
302 if (GET_CODE (insn
) == NOTE
)
303 insn
= prev_nonnote_insn (insn
);
304 if (insn
&& GET_CODE (insn
) == BARRIER
)
309 if (frame_pointer_needed
)
311 /* Pop saved registers */
312 for (idx
= 0; idx
< FIRST_PSEUDO_REGISTER
; idx
++)
314 regno
= pop_order
[idx
];
315 if (regno
>= 0 && regno
!= FRAME_POINTER_REGNUM
&& WORD_REG_USED (regno
))
316 fprintf (file
, "\t%s\t%s\n", h8_pop_op
, h8_reg_names
[regno
]);
318 /* deallocate locals */
319 dosize (file
, "add", fsize
);
320 /* pop frame pointer */
321 fprintf (file
, "\t%s\t%s\n", h8_pop_op
, h8_reg_names
[FRAME_POINTER_REGNUM
]);
325 /* pop saved registers */
326 for (idx
= 0; idx
< FIRST_PSEUDO_REGISTER
; idx
++)
328 regno
= pop_order
[idx
];
329 if (regno
>= 0 && WORD_REG_USED (regno
))
330 fprintf (file
, "\t%s\t%s\n", h8_pop_op
, h8_reg_names
[regno
]);
332 /* deallocate locals */
333 dosize (file
, "add", fsize
);
336 if (interrupt_handler
)
337 fprintf (file
, "\trte\n");
339 fprintf (file
, "\trts\n");
342 interrupt_handler
= 0;
348 /* Output assembly code for the start of the file. */
350 asm_file_start (file
)
353 fprintf (file
, ";\tGCC For the Hitachi H8/300\n");
354 fprintf (file
, ";\tBy Hitachi America Ltd and Cygnus Support\n");
355 fprintf (file
, ";\trelease F-1\n");
357 fprintf (file
, "; -O%d\n", optimize
);
359 fprintf (file
, "\n\t.h8300h\n");
361 fprintf (file
, "\n\n");
362 output_file_directive (file
, main_input_filename
);
365 /* Output assembly language code for the end of file. */
371 fprintf (file
, "\t.end\n");
374 /* Return true if VALUE is a valid constant for constraint 'P'.
375 IE: VALUE is a power of two <= 2**15. */
378 small_power_of_two (value
)
404 /* Return true if VALUE is a valid constant for constraint 'O', which
405 means that the constant would be ok to use as a bit for a bclr
412 return small_power_of_two ((~value
) & 0xff);
415 /* Return true is OP is a valid source operand for an integer move
419 general_operand_src (op
, mode
)
421 enum machine_mode mode
;
423 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == POST_INC
)
425 return general_operand (op
, mode
);
428 /* Return true if OP is a valid destination operand for an integer move
432 general_operand_dst (op
, mode
)
434 enum machine_mode mode
;
436 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == PRE_DEC
)
438 return general_operand (op
, mode
);
441 /* Return true if OP is a const valid for a bit clear instruction. */
444 o_operand (operand
, mode
)
446 enum machine_mode mode
;
448 return (GET_CODE (operand
) == CONST_INT
449 && CONST_OK_FOR_O (INTVAL (operand
)));
452 /* Return true if OP is a const valid for a bit set or bit xor instruction. */
455 p_operand (operand
, mode
)
457 enum machine_mode mode
;
459 return (GET_CODE (operand
) == CONST_INT
460 && CONST_OK_FOR_P (INTVAL (operand
)));
463 /* Return true if OP is a valid call operand. */
466 call_insn_operand (op
, mode
)
468 enum machine_mode mode
;
470 if (GET_CODE (op
) == MEM
)
472 rtx inside
= XEXP (op
, 0);
473 if (register_operand (inside
, Pmode
))
475 if (CONSTANT_ADDRESS_P (inside
))
482 adds_subs_operand (op
, mode
)
484 enum machine_mode mode
;
486 if (GET_CODE (op
) == CONST_INT
)
488 if (INTVAL (op
) <= 4 && INTVAL (op
) >= 0)
490 if (INTVAL (op
) >= -4 && INTVAL (op
) <= 0)
494 && (INTVAL (op
) <= 8 && INTVAL (op
) >= 0))
498 && (INTVAL (op
) >= -8 && INTVAL (op
) <= 0))
504 /* Return nonzero if op is an adds/subs operand which only requires
505 one insn to implement. It is assumed that OP is already an adds/subs
508 one_insn_adds_subs_operand (op
, mode
)
510 enum machine_mode mode
;
512 int val
= INTVAL (op
);
514 if (val
== 1 || val
== -1
515 || val
== 2 || val
== -2
517 && (val
== 4 || val
== -4)))
523 output_adds_subs (operands
)
526 int val
= INTVAL (operands
[2]);
528 /* First get the value into the range -4..4 inclusive.
530 The only way it can be out of this range is when TARGET_H8300H
531 is true, thus it is safe to use adds #4 and subs #4. */
534 output_asm_insn ("adds #4,%A0", operands
);
540 output_asm_insn ("subs #4,%A0", operands
);
544 /* Handle case were val == 4 or val == -4 and we're compiling
545 for TARGET_H8300H. */
546 if (TARGET_H8300H
&& val
== 4)
547 return "adds #4,%A0";
549 if (TARGET_H8300H
&& val
== -4)
550 return "subs #4,%A0";
554 output_asm_insn ("adds #2,%A0", operands
);
560 output_asm_insn ("subs #2,%A0", operands
);
564 /* val should be one or two now. */
566 return "adds #2,%A0";
569 return "subs #2,%A0";
571 /* val should be one now. */
573 return "adds #1,%A0";
576 return "subs #1,%A0";
578 /* In theory, this can't happen. */
582 /* Return true if OP is a valid call operand, and OP represents
583 an operand for a small call (4 bytes instead of 6 bytes). */
586 small_call_insn_operand (op
, mode
)
588 enum machine_mode mode
;
590 if (GET_CODE (op
) == MEM
)
592 rtx inside
= XEXP (op
, 0);
594 /* Register indirect is a small call. */
595 if (register_operand (inside
, Pmode
))
598 /* A call through the function vector is a small
600 if (GET_CODE (inside
) == SYMBOL_REF
601 && SYMBOL_REF_FLAG (inside
))
604 /* Otherwise it's a large call. */
608 /* Return true if OP is a valid jump operand. */
611 jump_address_operand (op
, mode
)
613 enum machine_mode mode
;
615 if (GET_CODE (op
) == REG
)
616 return mode
== Pmode
;
618 if (GET_CODE (op
) == MEM
)
620 rtx inside
= XEXP (op
, 0);
621 if (register_operand (inside
, Pmode
))
623 if (CONSTANT_ADDRESS_P (inside
))
629 /* Recognize valid operands for bitfield instructions. */
631 extern int rtx_equal_function_value_matters
;
634 bit_operand (op
, mode
)
636 enum machine_mode mode
;
638 /* We can except any general operand, expept that MEM operands must
639 be limited to those that use addresses valid for the 'U' constraint. */
640 if (!general_operand (op
, mode
))
643 /* Accept any mem during RTL generation. Otherwise, the code that does
644 insv and extzv will think that we can not handle memory. However,
645 to avoid reload problems, we only accept 'U' MEM operands after RTL
646 generation. This means that any named pattern which uses this predicate
647 must force its operands to match 'U' before emitting RTL. */
649 if (GET_CODE (op
) == REG
)
651 if (GET_CODE (op
) == SUBREG
)
653 if (!rtx_equal_function_value_matters
)
655 /* We're building rtl */
656 return GET_CODE (op
) == MEM
;
660 return (GET_CODE (op
) == MEM
661 && EXTRA_CONSTRAINT (op
, 'U'));
666 bit_memory_operand (op
, mode
)
668 enum machine_mode mode
;
670 return (GET_CODE (op
) == MEM
671 && EXTRA_CONSTRAINT (op
, 'U'));
674 /* Recognize valid operators for bit test. */
677 eq_operator (x
, mode
)
679 enum machine_mode mode
;
681 return (GET_CODE (x
) == EQ
|| GET_CODE (x
) == NE
);
684 /* Handle machine specific pragmas for compatibility with existing
685 compilers for the H8/300.
687 pragma saveall generates prolog/epilog code which saves and
688 restores all the registers on function entry.
690 pragma interrupt saves and restores all registers, and exits with
691 an rte instruction rather than an rts. A pointer to a function
692 with this attribute may be safely used in an interrupt vector. */
695 handle_pragma (file
, t
)
700 register char *pname
;
702 if (TREE_CODE (t
) != IDENTIFIER_NODE
)
705 pname
= IDENTIFIER_POINTER (t
);
706 if (strcmp (pname
, "interrupt") == 0)
707 interrupt_handler
= retval
= 1;
708 else if (strcmp (pname
, "saveall") == 0)
709 pragma_saveall
= retval
= 1;
714 /* If the next arg with MODE and TYPE is to be passed in a register, return
715 the rtx to represent where it is passed. CUM represents the state after
716 the last argument. NAMED is not used. */
718 static char *hand_list
[] =
738 /* Return an RTX to represent where a value with mode MODE will be returned
739 from a function. If the result is 0, the argument is pushed. */
742 function_arg (cum
, mode
, type
, named
)
743 CUMULATIVE_ARGS
*cum
;
744 enum machine_mode mode
;
752 /* Never pass unnamed arguments in registers. */
756 /* Pass 3 regs worth of data in regs when user asked on the command line. */
757 if (TARGET_QUICKCALL
)
760 /* If calling hand written assembler, use 4 regs of args. */
766 fname
= XSTR (cum
->libcall
, 0);
768 /* See if this libcall is one of the hand coded ones. */
770 for (p
= hand_list
; *p
&& strcmp (*p
, fname
) != 0; p
++)
782 size
= int_size_in_bytes (type
);
784 size
= GET_MODE_SIZE (mode
);
786 if (size
+ cum
->nbytes
> regpass
* UNITS_PER_WORD
)
792 switch (cum
->nbytes
/ UNITS_PER_WORD
)
795 result
= gen_rtx (REG
, mode
, 0);
798 result
= gen_rtx (REG
, mode
, 1);
801 result
= gen_rtx (REG
, mode
, 2);
804 result
= gen_rtx (REG
, mode
, 3);
815 /* Return the cost of the rtx R with code CODE. */
856 /* Documentation for the machine specific operand escapes:
858 'A' print rn in h8/300 mode, erN in H8/300H mode
859 'C' print (operand - 2).
860 'E' like s but negative.
861 'F' like t but negative.
862 'G' constant just the negative
863 'L' fake label, changed after used twice.
864 'M' turn a 'M' constant into its negative mod 2.
865 'P' if operand is incing/decing sp, print .w, otherwise .b.
866 'R' print operand as a byte:8 address if appropriate, else fall back to
868 'S' print operand as a long word
869 'T' print operand as a word
870 'U' if operand is incing/decing sp, print l, otherwise nothing.
871 'V' find the set bit, and print its number.
872 'W' find the clear bit, and print its number.
873 'X' print operand as a byte
874 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
875 If this operand isn't a register, fall back to 'R' handling.
877 'b' print the bit opcode
878 'c' print the ibit opcode
879 'd' bcc if EQ, bcs if NE
880 'e' first word of 32 bit value - if reg, then least reg. if mem
881 then least. if const then most sig word
882 'f' second word of 32 bit value - if reg, then biggest reg. if mem
883 then +2. if const then least sig word
884 'g' bcs if EQ, bcc if NE
885 'j' print operand as condition code.
886 'k' print operand as reverse condition code.
887 's' print as low byte of 16 bit value
888 't' print as high byte of 16 bit value
889 'w' print as low byte of 32 bit value
890 'x' print as 2nd byte of 32 bit value
891 'y' print as 3rd byte of 32 bit value
892 'z' print as msb of 32 bit value
895 /* Return assembly language string which identifies a comparison type. */
928 /* Print operand X using operand code CODE to assembly language output file
932 print_operand (file
, x
, code
)
937 /* This is used to general unique labels for the 'L' code. */
938 static int lab
= 1000;
940 /* This is used for communication between the 'P' and 'U' codes. */
943 /* This is used for communication between codes V,W,Z and Y. */
949 if (GET_CODE (x
) == REG
)
950 fprintf (file
, "%s", h8_reg_names
[REGNO (x
)]);
955 fprintf (file
, "#%d", INTVAL (x
) - 2);
958 switch (GET_CODE (x
))
961 fprintf (file
, "%sl", names_big
[REGNO (x
)]);
964 fprintf (file
, "#%d", (-INTVAL (x
)) & 0xff);
971 switch (GET_CODE (x
))
974 fprintf (file
, "%sh", names_big
[REGNO (x
)]);
977 fprintf (file
, "#%d", ((-INTVAL (x
)) & 0xff00) >> 8);
984 if (GET_CODE (x
) != CONST_INT
)
986 fprintf (file
, "#%d", 0xff & (-INTVAL (x
)));
989 /* 'L' must always be used twice in a single pattern. It generates
990 the same label twice, and then will generate a unique label the
991 next time it is used. */
992 asm_fprintf (file
, "tl%d", (lab
++) / 2);
995 /* For 3/-3 and 4/-4, the other 2 is handled separately. */
1002 fprintf (file
, "#2");
1008 fprintf (file
, "#1");
1015 if (REGNO (XEXP (XEXP (x
, 0), 0)) == STACK_POINTER_REGNUM
)
1018 fprintf (file
, ".w");
1023 fprintf (file
, ".b");
1027 if (GET_CODE (x
) == REG
)
1028 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1033 if (GET_CODE (x
) == REG
)
1034 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1039 fprintf (file
, "%s%s", names_big
[REGNO (x
)], last_p
);
1042 bitint
= exact_log2 (INTVAL (x
));
1045 fprintf (file
, "#%d", bitint
& 7);
1048 bitint
= exact_log2 ((~INTVAL (x
)) & 0xff);
1051 fprintf (file
, "#%d", bitint
& 7);
1055 if (GET_CODE (x
) == REG
)
1056 fprintf (file
, "%s", byte_reg (x
, 0));
1063 if (GET_CODE (x
) == REG
)
1064 fprintf (file
, "%s%c", names_big
[REGNO (x
)], bitint
> 7 ? 'h' : 'l');
1066 print_operand (file
, x
, 'R');
1070 bitint
= INTVAL (x
);
1071 fprintf (file
, "#%d", bitint
& 7);
1074 switch (GET_CODE (x
))
1077 fprintf (file
, "bor");
1080 fprintf (file
, "bxor");
1083 fprintf (file
, "band");
1088 switch (GET_CODE (x
))
1091 fprintf (file
, "bior");
1094 fprintf (file
, "bixor");
1097 fprintf (file
, "biand");
1102 switch (GET_CODE (x
))
1105 fprintf (file
, "bcc");
1108 fprintf (file
, "bcs");
1115 switch (GET_CODE (x
))
1119 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1121 fprintf (file
, "%s", names_upper_extended
[REGNO (x
)]);
1124 x
= adj_offsettable_operand (x
, 0);
1125 print_operand (file
, x
, 0);
1128 fprintf (file
, "#%d", ((INTVAL (x
) >> 16) & 0xffff));
1136 switch (GET_CODE (x
))
1140 fprintf (file
, "%s", names_big
[REGNO (x
) + 1]);
1142 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1145 x
= adj_offsettable_operand (x
, 2);
1146 print_operand (file
, x
, 0);
1149 fprintf (file
, "#%d", INTVAL (x
) & 0xffff);
1156 switch (GET_CODE (x
))
1159 fprintf (file
, "bcc");
1162 fprintf (file
, "bcs");
1169 asm_fprintf (file
, cond_string (GET_CODE (x
)));
1172 asm_fprintf (file
, cond_string (reverse_condition (GET_CODE (x
))));
1175 if (GET_CODE (x
) == CONST_INT
)
1176 fprintf (file
, "#%d", (INTVAL (x
)) & 0xff);
1178 fprintf (file
, "%s", byte_reg (x
, 0));
1181 if (GET_CODE (x
) == CONST_INT
)
1182 fprintf (file
, "#%d", (INTVAL (x
) >> 8) & 0xff);
1184 fprintf (file
, "%s", byte_reg (x
, 1));
1187 if (GET_CODE (x
) != CONST_INT
)
1189 fprintf (file
, "%d", INTVAL (x
));
1192 if (GET_CODE (x
) == CONST_INT
)
1193 fprintf (file
, "#%d", INTVAL (x
) & 0xff);
1195 fprintf (file
, "%s", byte_reg (x
, TARGET_H8300
? 2 : 0));
1198 if (GET_CODE (x
) == CONST_INT
)
1199 fprintf (file
, "#%d", (INTVAL (x
) >> 8) & 0xff);
1201 fprintf (file
, "%s", byte_reg (x
, TARGET_H8300
? 3 : 1));
1204 if (GET_CODE (x
) == CONST_INT
)
1205 fprintf (file
, "#%d", (INTVAL (x
) >> 16) & 0xff);
1207 fprintf (file
, "%s", byte_reg (x
, 0));
1210 if (GET_CODE (x
) == CONST_INT
)
1211 fprintf (file
, "#%d", (INTVAL (x
) >> 24) & 0xff);
1213 fprintf (file
, "%s", byte_reg (x
, 1));
1218 switch (GET_CODE (x
))
1221 switch (GET_MODE (x
))
1224 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1225 fprintf (file
, "%s", byte_reg (x
, 0));
1226 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1227 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1231 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1235 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1243 fprintf (file
, "@");
1244 output_address (XEXP (x
, 0));
1246 /* If this is an 'R' operand (reference into the 8-bit area),
1247 then specify a symbolic address as "foo:8". */
1249 && GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
1250 && SYMBOL_REF_FLAG (XEXP (x
, 0)))
1251 fprintf (file
, ":8");
1252 if (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
1253 && TINY_DATA_NAME_P (XSTR (XEXP (x
, 0), 0)))
1254 fprintf (file
, ":16");
1261 fprintf (file
, "#");
1262 print_operand_address (file
, x
);
1268 /* Output assembly language output for the address ADDR to FILE. */
1271 print_operand_address (file
, addr
)
1275 switch (GET_CODE (addr
))
1278 fprintf (file
, "%s", h8_reg_names
[REGNO (addr
)]);
1282 fprintf (file
, "-%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1286 fprintf (file
, "%s+", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1290 fprintf (file
, "(");
1291 if (GET_CODE (XEXP (addr
, 0)) == REG
)
1294 print_operand_address (file
, XEXP (addr
, 1));
1295 fprintf (file
, ",");
1296 print_operand_address (file
, XEXP (addr
, 0));
1301 print_operand_address (file
, XEXP (addr
, 0));
1302 fprintf (file
, "+");
1303 print_operand_address (file
, XEXP (addr
, 1));
1305 fprintf (file
, ")");
1310 /* Since the h8/300 only has 16 bit pointers, negative values are also
1311 those >= 32768. This happens for example with pointer minus a
1312 constant. We don't want to turn (char *p - 2) into
1313 (char *p + 65534) because loop unrolling can build upon this
1314 (IE: char *p + 131068). */
1315 int n
= INTVAL (addr
);
1317 n
= (int) (short) n
;
1319 /* ??? Why the special case for -ve values? */
1320 fprintf (file
, "-%d", -n
);
1322 fprintf (file
, "%d", n
);
1327 output_addr_const (file
, addr
);
1332 /* Output all insn addresses and their sizes into the assembly language
1333 output file. This is helpful for debugging whether the length attributes
1334 in the md file are correct. This is not meant to be a user selectable
1338 final_prescan_insn (insn
, operand
, num_operands
)
1342 /* This holds the last insn address. */
1343 static int last_insn_address
= 0;
1345 int uid
= INSN_UID (insn
);
1347 if (TARGET_RTL_DUMP
)
1349 fprintf (asm_out_file
, "\n****************");
1350 print_rtl (asm_out_file
, PATTERN (insn
));
1351 fprintf (asm_out_file
, "\n");
1354 if (TARGET_ADDRESSES
)
1356 fprintf (asm_out_file
, "; 0x%x %d\n", insn_addresses
[uid
],
1357 insn_addresses
[uid
] - last_insn_address
);
1358 last_insn_address
= insn_addresses
[uid
];
1362 /* Prepare for an SI sized move. */
1368 rtx src
= operands
[1];
1369 rtx dst
= operands
[0];
1370 if (!reload_in_progress
&& !reload_completed
)
1372 if (!register_operand (dst
, GET_MODE (dst
)))
1374 rtx tmp
= gen_reg_rtx (GET_MODE (dst
));
1375 emit_move_insn (tmp
, src
);
1382 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1383 Define the offset between two registers, one to be eliminated, and the other
1384 its replacement, at the start of a routine. */
1387 initial_offset (from
, to
)
1391 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
1392 offset
= UNITS_PER_WORD
+ frame_pointer_needed
* UNITS_PER_WORD
;
1397 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1398 if ((regs_ever_live
[regno
]
1399 && (!call_used_regs
[regno
] || regno
== FRAME_POINTER_REGNUM
)))
1400 offset
+= UNITS_PER_WORD
;
1402 /* See the comments for get_frame_size. We need to round it up to
1405 offset
+= ((get_frame_size () + STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
1406 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
1408 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1409 offset
+= UNITS_PER_WORD
; /* Skip saved PC */
1414 /* Update the condition code from the insn. */
1417 notice_update_cc (body
, insn
)
1421 switch (get_attr_cc (insn
))
1424 /* Insn does not affect CC at all. */
1428 /* Insn does not change CC, but the 0'th operand has been changed. */
1429 if (cc_status
.value1
!= 0
1430 && reg_overlap_mentioned_p (recog_operand
[0], cc_status
.value1
))
1431 cc_status
.value1
= 0;
1435 /* Insn sets the Z,N flags of CC to recog_operand[0].
1436 V is always set to 0. C may or may not be set to 0 but that's ok
1437 because alter_cond will change tests to use EQ/NE. */
1439 cc_status
.flags
|= CC_OVERFLOW_0
| CC_NO_CARRY
;
1440 cc_status
.value1
= recog_operand
[0];
1444 /* Insn sets the Z,N flags of CC to recog_operand[0].
1445 The V flag is unusable. The C flag may or may not be known but
1446 that's ok because alter_cond will change tests to use EQ/NE. */
1448 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
1449 cc_status
.value1
= recog_operand
[0];
1453 /* The insn is a compare instruction. */
1455 cc_status
.value1
= SET_SRC (body
);
1459 /* Insn doesn't leave CC in a usable state. */
1465 /* Return 1 if a previous compare needs to be re-issued. This will happen
1466 if the compare was deleted because the previous insn set it, but the
1467 branch needs CC flags not set.
1469 OP is the comparison being performed. */
1472 restore_compare_p (op
)
1475 switch (GET_CODE (op
))
1484 if (cc_status
.flags
& CC_OVERFLOW_UNUSABLE
)
1491 /* If the carry flag isn't usable, the test should have been changed
1493 if (cc_status
.flags
& CC_NO_CARRY
)
1503 /* Recognize valid operators for bit instructions */
1506 bit_operator (x
, mode
)
1508 enum machine_mode mode
;
1510 enum rtx_code code
= GET_CODE (x
);
1519 We devote a fair bit of code to getting efficient shifts since we can only
1520 shift one bit at a time. See the .md file for more comments.
1522 Here are some thoughts on what the absolutely positively best code is.
1523 "Best" here means some rational trade-off between code size and speed,
1524 where speed is more preferred but not at the expense of generating 20 insns.
1526 H8/300 QImode shifts
1527 1-4 - do them inline
1528 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1530 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1531 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1533 H8/300 HImode shifts
1534 1-4 - do them inline
1536 7 - shift other way once, move byte into place, move carry bit into place
1537 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1538 9 - inline shift 1-4, move byte, set other byte
1539 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1541 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1542 - ASHIFTRT: shll, subx, set other byte
1544 H8/300 SImode shifts
1545 1-2 - do them inline
1547 7 - shift other way once, move bytes into place,
1548 move carry into place (possibly with sign extension)
1549 8 - move bytes into place, zero or sign extend other
1551 15 - shift other way once, move word into place, move carry into place
1552 16 - move word, zero or sign extend other
1554 24 - move bytes into place, zero or sign extend other
1556 28-30 - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1559 31 - ASHIFT | LSHIFTRT: rotate top byte, mask, byte byte into place,
1561 ASHIFTRT: shll top byte, subx, copy to other bytes
1563 H8/300H QImode shifts
1566 H8/300H HImode shifts
1569 H8/300H SImode shifts
1570 (These are complicated by the fact that we don't have byte level access to
1572 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1573 1-4 - do them inline
1575 15 - shift other way once, move word into place, move carry into place
1576 (with sign extension for ASHIFTRT)
1577 16 - move word into place, zero or sign extend other
1579 24 - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1580 move word 0 to word 1, zero word 0
1581 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1582 zero word 1, zero byte 1
1583 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1584 sign extend byte 0, sign extend word 0
1585 25-27 - either loop, or
1586 do 24 bit shift, inline rest
1587 28-30 - ASHIFT: rotate 4/3/2, mask
1588 LSHIFTRT: rotate 4/3/2, mask
1590 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1594 All of these haven't been implemented. I've just documented them and
1595 provided hooks so they can be.
1599 nshift_operator (x
, mode
)
1601 enum machine_mode mode
;
1603 switch (GET_CODE (x
))
1615 /* Called from the .md file to emit code to do shifts.
1616 Returns a boolean indicating success
1617 (currently this is always TRUE). */
1620 expand_a_shift (mode
, code
, operands
)
1621 enum machine_mode mode
;
1625 emit_move_insn (operands
[0], operands
[1]);
1627 /* need a loop to get all the bits we want - we generate the
1628 code at emit time, but need to allocate a scratch reg now */
1631 (PARALLEL
, VOIDmode
,
1633 gen_rtx (SET
, VOIDmode
, operands
[0],
1634 gen_rtx (code
, mode
, operands
[0], operands
[2])),
1635 gen_rtx (CLOBBER
, VOIDmode
, gen_rtx (SCRATCH
, QImode
, 0)))));
1640 /* Shift algorithm determination.
1642 There are various ways of doing a shift:
1643 SHIFT_INLINE: If the amount is small enough, just generate as many one-bit
1645 SHIFT_ROT_AND: If the amount is large but close to either end, rotate the
1646 necessary bits into position and then set the rest to zero.
1647 SHIFT_SPECIAL: Hand crafted assembler.
1648 SHIFT_LOOP: If the above methods fail, just loop. */
1659 /* Symbols of the various shifts which can be used as indices. */
1663 SHIFT_ASHIFT
, SHIFT_LSHIFTRT
, SHIFT_ASHIFTRT
1666 /* Symbols of the various modes which can be used as indices. */
1670 QIshift
, HIshift
, SIshift
1673 /* For single bit shift insns, record assembler and what bits of the
1674 condition code are valid afterwards (represented as various CC_FOO
1675 bits, 0 means CC isn't left in a usable state). */
1683 /* Assembler instruction shift table.
1685 These tables are used to look up the basic shifts.
1686 They are indexed by cpu, shift_type, and mode.
1689 static const struct shift_insn shift_one
[2][3][3] =
1695 { "shll %X0", CC_OVERFLOW_0
| CC_NO_CARRY
},
1696 { "add.w %T0,%T0\t; shal.w", CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
},
1697 { "add.w %f0,%f0\t; shal.l\n\taddx %y0,%y0\n\taddx %z0,%z0\t; end shal.l", 0 }
1699 /* SHIFT_LSHIFTRT */
1701 { "shlr %X0", CC_OVERFLOW_0
| CC_NO_CARRY
},
1702 { "shlr %t0\t; shlr.w\n\trotxr %s0\t; end shlr.w", 0 },
1703 { "shlr %z0\t; shlr.l\n\trotxr %y0\n\trotxr %x0\n\trotxr %w0\t; end shlr.l", 0 }
1705 /* SHIFT_ASHIFTRT */
1707 { "shar %X0", CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
},
1708 { "shar %t0\t; shar.w\n\trotxr %s0\t; end shar.w", 0 },
1709 { "shar %z0\t; shar.l\n\trotxr %y0\n\trotxr %x0\n\trotxr %w0\t; end shar.l", 0 }
1716 { "shll.b %X0", CC_OVERFLOW_0
| CC_NO_CARRY
},
1717 { "shll.w %T0", CC_OVERFLOW_0
| CC_NO_CARRY
},
1718 { "shll.l %S0", CC_OVERFLOW_0
| CC_NO_CARRY
}
1720 /* SHIFT_LSHIFTRT */
1722 { "shlr.b %X0", CC_OVERFLOW_0
| CC_NO_CARRY
},
1723 { "shlr.w %T0", CC_OVERFLOW_0
| CC_NO_CARRY
},
1724 { "shlr.l %S0", CC_OVERFLOW_0
| CC_NO_CARRY
}
1726 /* SHIFT_ASHIFTRT */
1728 { "shar.b %X0", CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
},
1729 { "shar.w %T0", CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
},
1730 { "shar.l %S0", CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
}
1735 /* Rotates are organized by which shift they'll be used in implementing.
1736 There's no need to record whether the cc is valid afterwards because
1737 it is the AND insn that will decide this. */
1739 static const char *const rotate_one
[2][3][3] =
1746 "shlr %t0\t; rotr.w\n\trotxr %s0\n\tbst #7,%t0\t; end rotr.w",
1749 /* SHIFT_LSHIFTRT */
1752 "shll %s0\t; rotl.w\n\trotxl %t0\n\tbst #0,%s0\t; end rotl.w",
1755 /* SHIFT_ASHIFTRT */
1758 "shll %s0\t; rotl.w\n\trotxl %t0\n\tbst #0,%s0\t; end rotl.w",
1770 /* SHIFT_LSHIFTRT */
1776 /* SHIFT_ASHIFTRT */
1785 /* Given CPU, MODE, SHIFT_TYPE, and shift count COUNT, determine the best
1786 algorithm for doing the shift. The assembler code is stored in ASSEMBLER.
1787 We don't achieve maximum efficiency in all cases, but the hooks are here
1790 For now we just use lots of switch statements. Since we don't even come
1791 close to supporting all the cases, this is simplest. If this function ever
1792 gets too big, perhaps resort to a more table based lookup. Of course,
1793 at this point you may just wish to do it all in rtl.
1795 WARNING: The constraints on insns shiftbyn_QI/HI/SI assume shifts of
1796 1,2,3,4 will be inlined (1,2 for SI). */
1798 static enum shift_alg
1799 get_shift_alg (cpu
, shift_type
, mode
, count
, assembler_p
, cc_valid_p
)
1801 enum shift_type shift_type
;
1802 enum machine_mode mode
;
1804 const char **assembler_p
;
1807 /* The default is to loop. */
1808 enum shift_alg alg
= SHIFT_LOOP
;
1809 enum shift_mode shift_mode
;
1811 /* We don't handle negative shifts or shifts greater than the word size,
1812 they should have been handled already. */
1814 if (count
< 0 || count
> GET_MODE_BITSIZE (mode
))
1820 shift_mode
= QIshift
;
1823 shift_mode
= HIshift
;
1826 shift_mode
= SIshift
;
1832 /* Assume either SHIFT_LOOP or SHIFT_INLINE.
1833 It is up to the caller to know that looping clobbers cc. */
1834 *assembler_p
= shift_one
[cpu
][shift_type
][shift_mode
].assembler
;
1835 *cc_valid_p
= shift_one
[cpu
][shift_type
][shift_mode
].cc_valid
;
1837 /* Now look for cases we want to optimize. */
1843 return SHIFT_INLINE
;
1844 else if (count
<= 6)
1846 if (shift_type
== SHIFT_ASHIFTRT
)
1852 *assembler_p
= rotate_one
[cpu
][shift_type
][shift_mode
];
1854 return SHIFT_ROT_AND
;
1857 else if (count
== 7)
1859 if (shift_type
== SHIFT_ASHIFTRT
)
1861 *assembler_p
= "shll %X0\t; shar.b(7)\n\tsubx %X0,%X0\t; end shar.b(7)";
1863 return SHIFT_SPECIAL
;
1867 *assembler_p
= rotate_one
[cpu
][shift_type
][shift_mode
];
1869 return SHIFT_ROT_AND
;
1875 return SHIFT_INLINE
;
1876 else if (count
== 8)
1881 *assembler_p
= "mov.b %s0,%t0\t; shal.w(8)\n\tsub.b %s0,%s0\t; end shal.w(8)";
1883 return SHIFT_SPECIAL
;
1884 case SHIFT_LSHIFTRT
:
1885 *assembler_p
= "mov.b %t0,%s0\t; shlr.w(8)\n\tsub.b %t0,%t0\t; end shlr.w(8)";
1887 return SHIFT_SPECIAL
;
1888 case SHIFT_ASHIFTRT
:
1889 if (cpu
== CPU_H8300
)
1890 *assembler_p
= "mov.b %t0,%s0\t; shar.w(8)\n\tshll %t0\n\tsubx %t0,%t0\t; end shar.w(8)";
1892 *assembler_p
= "mov.b %t0,%s0\t; shar.w(8)\n\texts.w %T0\t; end shar.w(8)";
1894 return SHIFT_SPECIAL
;
1898 else if (count
== 15)
1900 if (shift_type
== SHIFT_ASHIFTRT
)
1902 *assembler_p
= "shll %t0,%t0\t; shar.w(15)\n\tsubx %t0,%t0\n\tmov.b %t0,%s0\t; end shar.w(15)";
1904 return SHIFT_SPECIAL
;
1908 *assembler_p
= rotate_one
[cpu
][shift_type
][shift_mode
];
1910 return SHIFT_ROT_AND
;
1915 if (count
<= (cpu
== CPU_H8300
? 2 : 4))
1916 return SHIFT_INLINE
;
1917 else if (count
== 8)
1919 if (cpu
== CPU_H8300
)
1924 *assembler_p
= "mov.b %y0,%z0\t; shal.l(8)\n\tmov.b %x0,%y0\n\tmov.b %w0,%x0\n\tsub.b %w0,%w0\t; end shal.l(8)";
1926 return SHIFT_SPECIAL
;
1927 case SHIFT_LSHIFTRT
:
1928 *assembler_p
= "mov.b %x0,%w0\t; shlr.l(8)\n\tmov.b %y0,%x0\n\tmov.b %z0,%y0\n\tsub.b %z0,%z0\t; end shlr.l(8)";
1930 return SHIFT_SPECIAL
;
1931 case SHIFT_ASHIFTRT
:
1932 *assembler_p
= "mov.b %x0,%w0\t; shar.l(8)\n\tmov.b %y0,%x0\n\tmov.b %z0,%y0\n\tshll %z0\n\tsubx %z0,%z0; end shar.l(8)";
1934 return SHIFT_SPECIAL
;
1937 else /* CPU_H8300H */
1938 /* We don't have byte level access to the high word so this isn't
1939 easy to do. For now, just loop. */
1942 else if (count
== 16)
1947 *assembler_p
= "mov.w %f0,%e0\t; shal.l(16)\n\tsub.w %f0,%f0\t; end shal.l(16)";
1949 return SHIFT_SPECIAL
;
1950 case SHIFT_LSHIFTRT
:
1951 *assembler_p
= "mov.w %e0,%f0\t; shlr.l(16)\n\tsub.w %e0,%e0\t; end shlr.l(16)";
1953 return SHIFT_SPECIAL
;
1954 case SHIFT_ASHIFTRT
:
1955 if (cpu
== CPU_H8300
)
1956 *assembler_p
= "mov.w %e0,%f0\t; shar.l(16)\n\tshll %z0\n\tsubx %z0,%z0\n\tmov.b %z0,%y0\t; end shar.l(16)";
1958 *assembler_p
= "mov.w %e0,%f0\t; shar.l(16)\n\texts.l %S0\t; end shar.l(16)";
1960 return SHIFT_SPECIAL
;
1963 else if (count
>= 28 && count
<= 30)
1965 if (shift_type
== SHIFT_ASHIFTRT
)
1971 if (cpu
== CPU_H8300
)
1975 *assembler_p
= rotate_one
[cpu
][shift_type
][shift_mode
];
1977 return SHIFT_ROT_AND
;
1981 else if (count
== 31)
1983 if (shift_type
== SHIFT_ASHIFTRT
)
1985 if (cpu
== CPU_H8300
)
1986 *assembler_p
= "shll %z0\t; shar.l(31)\n\tsubx %w0,%w0\n\tmov.b %w0,%x0\n\tmov.w %f0,%e0\t; end shar.l(31)";
1988 *assembler_p
= "shll %e0\t; shar.l(31)\n\tsubx %w0,%w0\n\tmov.b %w0,%x0\n\tmov.w %f0,%e0\t; end shar.l(31)";
1990 return SHIFT_SPECIAL
;
1994 if (cpu
== CPU_H8300
)
1996 if (shift_type
== SHIFT_ASHIFT
)
1997 *assembler_p
= "sub.w %e0,%e0\t; shal.l(31)\n\tshlr %w0\n\tmov.w %e0,%f0\n\trotxr %z0\t; end shal.l(31)";
1999 *assembler_p
= "sub.w %f0,%f0\t; shlr.l(31)\n\tshll %z0\n\tmov.w %f0,%e0\n\trotxl %w0\t; end shlr.l(31)";
2001 return SHIFT_SPECIAL
;
2005 *assembler_p
= rotate_one
[cpu
][shift_type
][shift_mode
];
2007 return SHIFT_ROT_AND
;
2019 /* Emit the assembler code for doing shifts. */
2022 emit_a_shift (insn
, operands
)
2026 static int loopend_lab
;
2029 rtx inside
= PATTERN (insn
);
2030 rtx shift
= operands
[3];
2031 enum machine_mode mode
= GET_MODE (shift
);
2032 enum rtx_code code
= GET_CODE (shift
);
2033 enum shift_type shift_type
;
2034 enum shift_mode shift_mode
;
2041 shift_mode
= QIshift
;
2044 shift_mode
= HIshift
;
2047 shift_mode
= SIshift
;
2056 shift_type
= SHIFT_ASHIFTRT
;
2059 shift_type
= SHIFT_LSHIFTRT
;
2062 shift_type
= SHIFT_ASHIFT
;
2068 if (GET_CODE (operands
[2]) != CONST_INT
)
2070 /* Indexing by reg, so have to loop and test at top */
2071 output_asm_insn ("mov.b %X2,%X4", operands
);
2072 fprintf (asm_out_file
, "\tble .Lle%d\n", loopend_lab
);
2074 /* Get the assembler code to do one shift. */
2075 get_shift_alg (cpu_type
, shift_type
, mode
, 1, &assembler
, &cc_valid
);
2079 int n
= INTVAL (operands
[2]);
2082 /* If the count is negative, make it 0. */
2085 /* If the count is too big, truncate it.
2086 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
2087 do the intuitive thing. */
2088 else if (n
> GET_MODE_BITSIZE (mode
))
2089 n
= GET_MODE_BITSIZE (mode
);
2091 alg
= get_shift_alg (cpu_type
, shift_type
, mode
, n
, &assembler
, &cc_valid
);
2097 output_asm_insn (assembler
, operands
);
2100 cc_status
.value1
= operands
[0];
2101 cc_status
.flags
|= cc_valid
;
2106 int m
= GET_MODE_BITSIZE (mode
) - n
;
2107 int mask
= (shift_type
== SHIFT_ASHIFT
2108 ? ((1 << GET_MODE_BITSIZE (mode
) - n
) - 1) << n
2109 : (1 << GET_MODE_BITSIZE (mode
) - n
) - 1);
2111 /* Not all possibilities of rotate are supported. They shouldn't
2112 be generated, but let's watch for 'em. */
2116 output_asm_insn (assembler
, operands
);
2122 sprintf (insn_buf
, "and #%d,%%X0\t; end shift %d via rotate+and",
2124 cc_status
.value1
= operands
[0];
2125 cc_status
.flags
|= CC_OVERFLOW_0
| CC_NO_CARRY
;
2128 sprintf (insn_buf
, "and #%d,%%s0\n\tand #%d,%%t0\t; end shift %d via rotate+and",
2129 mask
& 255, mask
>> 8, n
);
2137 sprintf (insn_buf
, "and.%c #%d,%%%c0",
2138 "bwl"[shift_mode
], mask
,
2139 mode
== QImode
? 'X' : mode
== HImode
? 'T' : 'S');
2140 cc_status
.value1
= operands
[0];
2141 cc_status
.flags
|= CC_OVERFLOW_0
| CC_NO_CARRY
;
2143 output_asm_insn (insn_buf
, operands
);
2147 output_asm_insn (assembler
, operands
);
2151 /* Need a loop, move limit to tmp reg */
2152 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
, names_big
[REGNO (operands
[4])]);
2155 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
2156 output_asm_insn (assembler
, operands
);
2157 output_asm_insn ("add #0xff,%X4", operands
);
2158 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
2159 fprintf (asm_out_file
, ".Lle%d:\n", loopend_lab
);
2164 /* Fix the operands of a gen_xxx so that it could become a bit
2168 fix_bit_operand (operands
, what
, type
)
2173 /* The bit_operand predicate accepts any memory during RTL generation, but
2174 only 'U' memory afterwards, so if this is a MEM operand, we must force
2175 it to be valid for 'U' by reloading the address. */
2177 if (GET_CODE (operands
[2]) == CONST_INT
)
2179 if (CONST_OK_FOR_LETTER_P (INTVAL (operands
[2]), what
))
2181 /* Ok to have a memory dest. */
2182 if (GET_CODE (operands
[0]) == MEM
&& !EXTRA_CONSTRAINT (operands
[0], 'U'))
2185 mem
= gen_rtx (MEM
, GET_MODE (operands
[0]),
2186 copy_to_mode_reg (Pmode
, XEXP (operands
[0], 0)));
2187 RTX_UNCHANGING_P (mem
) = RTX_UNCHANGING_P (operands
[0]);
2188 MEM_IN_STRUCT_P (mem
) = MEM_IN_STRUCT_P (operands
[0]);
2189 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (operands
[0]);
2193 if (GET_CODE (operands
[1]) == MEM
&& !EXTRA_CONSTRAINT (operands
[1], 'U'))
2196 mem
= gen_rtx (MEM
, GET_MODE (operands
[1]),
2197 copy_to_mode_reg (Pmode
, XEXP (operands
[1], 0)));
2198 RTX_UNCHANGING_P (mem
) = RTX_UNCHANGING_P (operands
[1]);
2199 MEM_IN_STRUCT_P (mem
) = MEM_IN_STRUCT_P (operands
[1]);
2200 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (operands
[1]);
2207 /* Dest and src op must be register. */
2209 operands
[1] = force_reg (QImode
, operands
[1]);
2211 rtx res
= gen_reg_rtx (QImode
);
2212 emit_insn (gen_rtx (SET
, VOIDmode
, res
, gen_rtx (type
, QImode
, operands
[1], operands
[2])));
2213 emit_insn (gen_rtx (SET
, VOIDmode
, operands
[0], res
));
2218 /* Return nonzero if FUNC is an interrupt function as specified
2219 by the "interrupt" attribute. */
2222 h8300_interrupt_function_p (func
)
2227 if (TREE_CODE (func
) != FUNCTION_DECL
)
2230 a
= lookup_attribute ("interrupt_handler", DECL_MACHINE_ATTRIBUTES (func
));
2231 return a
!= NULL_TREE
;
2234 /* Return nonzero if FUNC is an OS_Task function as specified
2235 by the "OS_Task" attribute. */
2238 h8300_os_task_function_p (func
)
2243 if (TREE_CODE (func
) != FUNCTION_DECL
)
2246 a
= lookup_attribute ("OS_Task", DECL_MACHINE_ATTRIBUTES (func
));
2247 return a
!= NULL_TREE
;
2250 /* Return nonzero if FUNC is a monitor function as specified
2251 by the "monitor" attribute. */
2254 h8300_monitor_function_p (func
)
2259 if (TREE_CODE (func
) != FUNCTION_DECL
)
2262 a
= lookup_attribute ("monitor", DECL_MACHINE_ATTRIBUTES (func
));
2263 return a
!= NULL_TREE
;
2266 /* Return nonzero if FUNC is a function that should be called
2267 through the function vector. */
2270 h8300_funcvec_function_p (func
)
2275 if (TREE_CODE (func
) != FUNCTION_DECL
)
2278 a
= lookup_attribute ("function_vector", DECL_MACHINE_ATTRIBUTES (func
));
2279 return a
!= NULL_TREE
;
2282 /* Return nonzero if DECL is a variable that's in the eight bit
2286 h8300_eightbit_data_p (decl
)
2291 if (TREE_CODE (decl
) != VAR_DECL
)
2294 a
= lookup_attribute ("eightbit_data", DECL_MACHINE_ATTRIBUTES (decl
));
2295 return a
!= NULL_TREE
;
2298 /* Return nonzero if DECL is a variable that's in the tiny
2302 h8300_tiny_data_p (decl
)
2307 if (TREE_CODE (decl
) != VAR_DECL
)
2310 a
= lookup_attribute ("tiny_data", DECL_MACHINE_ATTRIBUTES (decl
));
2311 return a
!= NULL_TREE
;
2314 /* Return nonzero if ATTR is a valid attribute for DECL.
2315 ATTRIBUTES are any existing attributes and ARGS are the arguments
2318 Supported attributes:
2320 interrupt_handler: output a prologue and epilogue suitable for an
2323 function_vector: This function should be called through the
2326 eightbit_data: This variable lives in the 8-bit data area and can
2327 be referenced with 8-bit absolute memory addresses.
2329 tiny_data: This variable lives in the tiny data area and can be
2330 referenced with 16-bit absolute memory references. */
2333 h8300_valid_machine_decl_attribute (decl
, attributes
, attr
, args
)
2339 if (args
!= NULL_TREE
)
2342 if (is_attribute_p ("interrupt_handler", attr
)
2343 || is_attribute_p ("OS_Task", attr
)
2344 || is_attribute_p ("monitor", attr
)
2345 || is_attribute_p ("function_vector", attr
))
2346 return TREE_CODE (decl
) == FUNCTION_DECL
;
2348 if (is_attribute_p ("eightbit_data", attr
)
2349 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
2351 if (DECL_INITIAL (decl
) == NULL_TREE
)
2353 warning ("Only initialized variables can be placed into the 8-bit area.");
2356 DECL_SECTION_NAME (decl
) = build_string (7, ".eight");
2360 if (is_attribute_p ("tiny_data", attr
)
2361 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
2363 if (DECL_INITIAL (decl
) == NULL_TREE
)
2365 warning ("Only initialized variables can be placed into the 8-bit area.");
2368 DECL_SECTION_NAME (decl
) = build_string (6, ".tiny");
2375 extern struct obstack
*saveable_obstack
;
2377 h8300_encode_label (decl
)
2380 char *str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2381 int len
= strlen (str
);
2384 newstr
= obstack_alloc (saveable_obstack
, len
+ 2);
2386 strcpy (newstr
+ 1, str
);
2388 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
2392 output_simode_bld (bild
, log2
, operands
)
2397 /* Clear the destination register. */
2399 output_asm_insn ("sub.l\t%S0,%S0", operands
);
2401 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands
);
2403 /* Get the bit number we want to load. */
2405 operands
[2] = GEN_INT (exact_log2 (INTVAL (operands
[2])));
2407 /* Now output the bit load or bit inverse load, and store it in
2410 output_asm_insn ("bild\t%Z2,%Y1\n\tbst\t#0,%w0", operands
);
2412 output_asm_insn ("bld\t%Z2,%Y1\n\tbst\t#0,%w0", operands
);
2418 /* Given INSN and it's current length LENGTH, return the adjustment
2419 (in bytes) to correctly compute INSN's length.
2421 We use this to get the lengths of various memory references correct. */
2423 h8300_adjust_insn_length (insn
, length
)
2427 rtx pat
= PATTERN (insn
);
2429 /* Adjust length for reg->mem and mem->reg copies. */
2430 if (GET_CODE (pat
) == SET
2431 && (GET_CODE (SET_SRC (pat
)) == MEM
2432 || GET_CODE (SET_DEST (pat
)) == MEM
))
2434 /* This insn might need a length adjustment. */
2437 if (GET_CODE (SET_SRC (pat
)) == MEM
)
2438 addr
= XEXP (SET_SRC (pat
), 0);
2440 addr
= XEXP (SET_DEST (pat
), 0);
2442 /* On the H8/300, only one adjustment is necessary; if the
2443 address mode is register indirect, then this insn is two
2444 bytes shorter than indicated in the machine description. */
2445 if (TARGET_H8300
&& GET_CODE (addr
) == REG
)
2448 /* On the H8/300H, register indirect is 6 bytes shorter than
2449 indicated in the machine description. */
2450 if (TARGET_H8300H
&& GET_CODE (addr
) == REG
)
2453 /* On the H8/300H, reg + d, for small displacements is 4 bytes
2454 shorter than indicated in the machine description. */
2456 && GET_CODE (addr
) == PLUS
2457 && GET_CODE (XEXP (addr
, 0)) == REG
2458 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
2459 && INTVAL (XEXP (addr
, 1)) > -32768
2460 && INTVAL (XEXP (addr
, 1)) < 32767)
2463 /* On the H8/300H, abs:16 is two bytes shorter than the
2464 more general abs:24. */
2466 && GET_CODE (addr
) == SYMBOL_REF
2467 && TINY_DATA_NAME_P (XSTR (addr
, 0)))
2471 /* Loading some constants needs adjustment. */
2472 if (GET_CODE (pat
) == SET
2473 && GET_CODE (SET_SRC (pat
)) == CONST_INT
2474 && GET_MODE (SET_DEST (pat
)) == SImode
2475 && INTVAL (SET_SRC (pat
)) != 0)
2478 && ((INTVAL (SET_SRC (pat
)) & 0xffff) == 0
2479 || ((INTVAL (SET_SRC (pat
)) >> 16) & 0xffff) == 0))
2484 int val
= INTVAL (SET_SRC (pat
));
2486 if (val
== (val
& 0xff)
2487 || val
== (val
& 0xff00))
2490 if (val
== -4 || val
== -2 || val
== -1)
2495 /* Shifts need various adjustments. */
2496 if (GET_CODE (pat
) == PARALLEL
2497 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
2498 && (GET_CODE (SET_SRC (XVECEXP (pat
, 0, 0))) == ASHIFTRT
2499 || GET_CODE (SET_SRC (XVECEXP (pat
, 0, 0))) == LSHIFTRT
2500 || GET_CODE (SET_SRC (XVECEXP (pat
, 0, 0))) == ASHIFT
))
2502 rtx src
= SET_SRC (XVECEXP (pat
, 0, 0));
2503 enum machine_mode mode
= GET_MODE (src
);
2505 if (GET_CODE (XEXP (src
, 1)) != CONST_INT
)
2508 /* QImode shifts by small constants take one insn
2509 per shift. So the adjustment is 20 (md length) -
2511 if (mode
== QImode
&& INTVAL (XEXP (src
, 1)) <= 4)
2512 return -(20 - INTVAL (XEXP (src
, 1)) * 2);
2514 /* Similarly for HImode and SImode shifts by
2515 small constants on the H8/300H. */
2517 && (mode
== HImode
|| mode
== SImode
)
2518 && INTVAL (XEXP (src
, 1)) <= 4)
2519 return -(20 - INTVAL (XEXP (src
, 1)) * 2);
2521 /* HImode shifts by small constants for the H8/300. */
2523 && INTVAL (XEXP (src
, 1)) <= 4)
2524 return -(20 - (INTVAL (XEXP (src
, 1))
2525 * (GET_CODE (src
) == ASHIFT
? 2 : 4)));
2527 /* SImode shifts by small constants for the H8/300. */
2529 && INTVAL (XEXP (src
, 1)) <= 2)
2530 return -(20 - (INTVAL (XEXP (src
, 1))
2531 * (GET_CODE (src
) == ASHIFT
? 6 : 8)));
2533 /* XXX ??? Could check for more shift/rotate cases here. */