1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
40 /* Forward declarations. */
41 void print_operand_address ();
44 static int h8300_interrupt_function_p
PROTO ((tree
));
46 /* CPU_TYPE, says what cpu we're compiling for. */
49 /* True if the current function is an interrupt handler
50 (either via #pragma or an attribute specification). */
51 int interrupt_handler
;
54 /* True if a #pragma saveall has been seen for the current function. */
57 static char *names_big
[] =
58 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7"};
60 static char *names_extended
[] =
61 {"er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7"};
63 static char *names_upper_extended
[] =
64 {"e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7"};
66 /* Points to one of the above. */
67 /* ??? The above could be put in an array indexed by CPU_TYPE. */
70 /* Various operations needed by the following, indexed by CPU_TYPE. */
72 static char *h8_push_ops
[2] =
74 static char *h8_pop_ops
[2] =
76 static char *h8_mov_ops
[2] =
79 char *h8_push_op
, *h8_pop_op
, *h8_mov_op
;
81 /* Initialize various cpu specific globals at start up. */
88 cpu_type
= (int) CPU_H8300
;
89 h8_reg_names
= names_big
;
93 cpu_type
= (int) CPU_H8300H
;
94 h8_reg_names
= names_extended
;
96 h8_push_op
= h8_push_ops
[cpu_type
];
97 h8_pop_op
= h8_pop_ops
[cpu_type
];
98 h8_mov_op
= h8_mov_ops
[cpu_type
];
106 static char *names_small
[] =
107 {"r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
108 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"};
110 return names_small
[REGNO (x
) * 2 + b
];
113 /* REGNO must be saved/restored across calls if this macro is true. */
115 #define WORD_REG_USED(regno) \
119 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
120 || (regs_ever_live[regno] & !call_used_regs[regno])))
122 /* Output assembly language to FILE for the operation OP with operand size
123 SIZE to adjust the stack pointer. */
126 dosize (file
, op
, size
)
131 /* On the h8300h, for sizes <= 8 bytes it is as good or
132 better to use adds/subs insns rather than add.l/sub.l
133 with an immediate value. */
134 if (size
> 4 && size
<= 8 && TARGET_H8300H
)
136 /* Crank the size down to <= 4 */
137 fprintf (file
, "\t%ss\t#%d,sp\n", op
, 4);
146 fprintf (file
, "\t%ss\t#%d,sp\n", op
, 4);
151 fprintf (file
, "\t%ss\t#%d,sp\n", op
, 2);
153 /* Fall through... */
156 fprintf (file
, "\t%ss\t#%d,sp\n", op
, size
);
163 fprintf (file
, "\tmov.w\t#%d,r3\n\t%s.w\tr3,sp\n", size
, op
);
165 fprintf (file
, "\t%s\t#%d,sp\n", op
, size
);
171 /* Output assembly language code for the function prologue. */
172 static int push_order
[FIRST_PSEUDO_REGISTER
] =
173 {6, 5, 4, 3, 2, 1, 0, -1, -1};
174 static int pop_order
[FIRST_PSEUDO_REGISTER
] =
175 {0, 1, 2, 3, 4, 5, 6, -1, -1};
177 /* This is what the stack looks like after the prolog of
178 a function with a frame has been set up:
184 <saved registers> <- sp
186 This is what the stack looks like after the prolog of
187 a function which doesn't have a frame:
192 <saved registers> <- sp
196 function_prologue (file
, size
)
200 register int mask
= 0;
201 int fsize
= (size
+ STACK_BOUNDARY
/ 8 - 1) & -STACK_BOUNDARY
/ 8;
204 /* Note a function with the interrupt attribute and set interrupt_handler
206 if (h8300_interrupt_function_p (current_function_decl
))
207 interrupt_handler
= 1;
209 if (frame_pointer_needed
)
212 fprintf (file
, "\t%s\t%s\n", h8_push_op
,
213 h8_reg_names
[FRAME_POINTER_REGNUM
]);
214 fprintf (file
, "\t%s\t%s,%s\n", h8_mov_op
,
215 h8_reg_names
[STACK_POINTER_REGNUM
],
216 h8_reg_names
[FRAME_POINTER_REGNUM
]);
218 /* leave room for locals */
219 dosize (file
, "sub", fsize
);
221 /* Push the rest of the registers */
222 for (idx
= 0; idx
< FIRST_PSEUDO_REGISTER
; idx
++)
224 int regno
= push_order
[idx
];
226 if (regno
>= 0 && WORD_REG_USED (regno
) && regno
!= FRAME_POINTER_REGNUM
)
227 fprintf (file
, "\t%s\t%s\n", h8_push_op
, h8_reg_names
[regno
]);
232 dosize (file
, "sub", fsize
);
233 for (idx
= 0; idx
< FIRST_PSEUDO_REGISTER
; idx
++)
235 int regno
= push_order
[idx
];
237 if (regno
>= 0 && WORD_REG_USED (regno
))
238 fprintf (file
, "\t%s\t%s\n", h8_push_op
, h8_reg_names
[regno
]);
243 /* Output assembly language code for the function epilogue. */
246 function_epilogue (file
, size
)
251 register int mask
= 0;
252 int fsize
= (size
+ STACK_BOUNDARY
/ 8 - 1) & -STACK_BOUNDARY
/ 8;
256 rtx insn
= get_last_insn ();
258 /* If the last insn was a BARRIER, we don't have to write any code. */
259 if (GET_CODE (insn
) == NOTE
)
260 insn
= prev_nonnote_insn (insn
);
261 if (insn
&& GET_CODE (insn
) == BARRIER
)
266 if (frame_pointer_needed
)
268 /* Pop saved registers */
269 for (idx
= 0; idx
< FIRST_PSEUDO_REGISTER
; idx
++)
271 regno
= pop_order
[idx
];
272 if (regno
>= 0 && regno
!= FRAME_POINTER_REGNUM
&& WORD_REG_USED (regno
))
273 fprintf (file
, "\t%s\t%s\n", h8_pop_op
, h8_reg_names
[regno
]);
275 /* deallocate locals */
276 dosize (file
, "add", fsize
);
277 /* pop frame pointer */
278 fprintf (file
, "\t%s\t%s\n", h8_pop_op
, h8_reg_names
[FRAME_POINTER_REGNUM
]);
282 /* pop saved registers */
283 for (idx
= 0; idx
< FIRST_PSEUDO_REGISTER
; idx
++)
285 regno
= pop_order
[idx
];
286 if (regno
>= 0 && WORD_REG_USED (regno
))
287 fprintf (file
, "\t%s\t%s\n", h8_pop_op
, h8_reg_names
[regno
]);
289 /* deallocate locals */
290 dosize (file
, "add", fsize
);
293 if (interrupt_handler
)
294 fprintf (file
, "\trte\n");
296 fprintf (file
, "\trts\n");
298 interrupt_handler
= 0;
302 /* Output assembly code for the start of the file. */
304 asm_file_start (file
)
307 fprintf (file
, ";\tGCC For the Hitachi H8/300\n");
308 fprintf (file
, ";\tBy Hitachi America Ltd and Cygnus Support\n");
309 fprintf (file
, ";\trelease F-1\n");
311 fprintf (file
, "; -O%d\n", optimize
);
313 fprintf (file
, "\n\t.h8300h\n");
315 fprintf (file
, "\n\n");
316 output_file_directive (file
, main_input_filename
);
319 /* Output assembly language code for the end of file. */
325 fprintf (file
, "\t.end\n");
328 /* Return true if VALUE is a valid constant for constraint 'P'.
329 IE: VALUE is a power of two <= 2**15. */
332 small_power_of_two (value
)
358 /* Return true if VALUE is a valid constant for constraint 'O', which
359 means that the constant would be ok to use as a bit for a bclr
366 return small_power_of_two ((~value
) & 0xff);
369 /* Return true is OP is a valid source operand for an integer move
373 general_operand_src (op
, mode
)
375 enum machine_mode mode
;
377 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == POST_INC
)
379 return general_operand (op
, mode
);
382 /* Return true if OP is a valid destination operand for an integer move
386 general_operand_dst (op
, mode
)
388 enum machine_mode mode
;
390 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == PRE_DEC
)
392 return general_operand (op
, mode
);
395 /* Return true if OP is a const valid for a bit clear instruction. */
398 o_operand (operand
, mode
)
400 enum machine_mode mode
;
402 return (GET_CODE (operand
) == CONST_INT
403 && CONST_OK_FOR_O (INTVAL (operand
)));
406 /* Return true if OP is a const valid for a bit set or bit xor instruction. */
409 p_operand (operand
, mode
)
411 enum machine_mode mode
;
413 return (GET_CODE (operand
) == CONST_INT
414 && CONST_OK_FOR_P (INTVAL (operand
)));
417 /* Return true if OP is a valid call operand. */
420 call_insn_operand (op
, mode
)
422 enum machine_mode mode
;
424 if (GET_CODE (op
) == MEM
)
426 rtx inside
= XEXP (op
, 0);
427 if (register_operand (inside
, Pmode
))
429 if (CONSTANT_ADDRESS_P (inside
))
436 adds_subs_operand (op
, mode
)
438 enum machine_mode mode
;
440 if (GET_CODE (op
) == CONST_INT
)
442 if (INTVAL (op
) <= 4 && INTVAL (op
) >= 0)
444 if (INTVAL (op
) >= -4 && INTVAL (op
) <= 0)
448 && (INTVAL (op
) <= 8 && INTVAL (op
) >= 0))
452 && (INTVAL (op
) >= -8 && INTVAL (op
) <= 0))
458 /* Return nonzero if op is an adds/subs operand which only requires
459 one insn to implement. It is assumed that OP is already an adds/subs
462 one_insn_adds_subs_operand (op
, mode
)
464 enum machine_mode mode
;
466 int val
= INTVAL (op
);
468 if (val
== 1 || val
== -1
469 || val
== 2 || val
== -2
471 && (val
== 4 || val
== -4)))
477 output_adds_subs (operands
)
480 int val
= INTVAL (operands
[2]);
482 /* First get the value into the range -4..4 inclusive.
484 The only way it can be out of this range is when TARGET_H8300H
485 is true, thus it is safe to use adds #4 and subs #4. */
488 output_asm_insn ("adds #4,%A0", operands
);
494 output_asm_insn ("subs #4,%A0", operands
);
498 /* Handle case were val == 4 or val == -4 and we're compiling
499 for TARGET_H8300H. */
500 if (TARGET_H8300H
&& val
== 4)
501 return "adds #4,%A0";
503 if (TARGET_H8300H
&& val
== -4)
504 return "subs #4,%A0";
508 output_asm_insn ("adds #2,%A0", operands
);
514 output_asm_insn ("subs #2,%A0", operands
);
518 /* val should be one or two now. */
520 return "adds #2,%A0";
523 return "subs #2,%A0";
525 /* val should be one now. */
527 return "adds #1,%A0";
530 return "subs #1,%A0";
532 /* In theory, this can't happen. */
536 /* Return true if OP is a valid call operand, and OP represents
537 an operand for a small call (4 bytes instead of 6 bytes). */
540 small_call_insn_operand (op
, mode
)
542 enum machine_mode mode
;
544 if (GET_CODE (op
) == MEM
)
546 rtx inside
= XEXP (op
, 0);
548 /* Register indirect is a small call. */
549 if (register_operand (inside
, Pmode
))
552 /* A call through the function vector is a small
554 if (GET_CODE (inside
) == SYMBOL_REF
555 && SYMBOL_REF_FLAG (inside
))
558 /* Otherwise it's a large call. */
562 /* Return true if OP is a valid jump operand. */
565 jump_address_operand (op
, mode
)
567 enum machine_mode mode
;
569 if (GET_CODE (op
) == REG
)
570 return mode
== Pmode
;
572 if (GET_CODE (op
) == MEM
)
574 rtx inside
= XEXP (op
, 0);
575 if (register_operand (inside
, Pmode
))
577 if (CONSTANT_ADDRESS_P (inside
))
583 /* Recognize valid operands for bitfield instructions. */
585 extern int rtx_equal_function_value_matters
;
588 bit_operand (op
, mode
)
590 enum machine_mode mode
;
592 /* We can except any general operand, expept that MEM operands must
593 be limited to those that use addresses valid for the 'U' constraint. */
594 if (!general_operand (op
, mode
))
597 /* Accept any mem during RTL generation. Otherwise, the code that does
598 insv and extzv will think that we can not handle memory. However,
599 to avoid reload problems, we only accept 'U' MEM operands after RTL
600 generation. This means that any named pattern which uses this predicate
601 must force its operands to match 'U' before emitting RTL. */
603 if (GET_CODE (op
) == REG
)
605 if (GET_CODE (op
) == SUBREG
)
607 if (!rtx_equal_function_value_matters
)
609 /* We're building rtl */
610 return GET_CODE (op
) == MEM
;
614 return (GET_CODE (op
) == MEM
615 && EXTRA_CONSTRAINT (op
, 'U'));
620 bit_memory_operand (op
, mode
)
622 enum machine_mode mode
;
624 return (GET_CODE (op
) == MEM
625 && EXTRA_CONSTRAINT (op
, 'U'));
628 /* Recognize valid operators for bit test. */
631 eq_operator (x
, mode
)
633 enum machine_mode mode
;
635 return (GET_CODE (x
) == EQ
|| GET_CODE (x
) == NE
);
638 /* Handle machine specific pragmas for compatibility with existing
639 compilers for the H8/300.
641 pragma saveall generates prolog/epilog code which saves and
642 restores all the registers on function entry.
644 pragma interrupt saves and restores all registers, and exits with
645 an rte instruction rather than an rts. A pointer to a function
646 with this attribute may be safely used in an interrupt vector. */
649 handle_pragma (file
, t
)
654 register char *pname
;
656 if (TREE_CODE (t
) != IDENTIFIER_NODE
)
659 pname
= IDENTIFIER_POINTER (t
);
660 if (strcmp (pname
, "interrupt") == 0)
661 interrupt_handler
= retval
= 1;
662 else if (strcmp (pname
, "saveall") == 0)
663 pragma_saveall
= retval
= 1;
668 /* If the next arg with MODE and TYPE is to be passed in a register, return
669 the rtx to represent where it is passed. CUM represents the state after
670 the last argument. NAMED is not used. */
672 static char *hand_list
[] =
692 /* Return an RTX to represent where a value with mode MODE will be returned
693 from a function. If the result is 0, the argument is pushed. */
696 function_arg (cum
, mode
, type
, named
)
697 CUMULATIVE_ARGS
*cum
;
698 enum machine_mode mode
;
706 /* Never pass unnamed arguments in registers. */
710 /* Pass 3 regs worth of data in regs when user asked on the command line. */
711 if (TARGET_QUICKCALL
)
714 /* If calling hand written assembler, use 4 regs of args. */
720 fname
= XSTR (cum
->libcall
, 0);
722 /* See if this libcall is one of the hand coded ones. */
724 for (p
= hand_list
; *p
&& strcmp (*p
, fname
) != 0; p
++)
736 size
= int_size_in_bytes (type
);
738 size
= GET_MODE_SIZE (mode
);
740 if (size
+ cum
->nbytes
> regpass
* UNITS_PER_WORD
)
746 switch (cum
->nbytes
/ UNITS_PER_WORD
)
749 result
= gen_rtx (REG
, mode
, 0);
752 result
= gen_rtx (REG
, mode
, 1);
755 result
= gen_rtx (REG
, mode
, 2);
758 result
= gen_rtx (REG
, mode
, 3);
769 /* Return the cost of the rtx R with code CODE. */
810 /* Documentation for the machine specific operand escapes:
812 'A' print rn in h8/300 mode, erN in H8/300H mode
813 'C' print (operand - 2).
814 'E' like s but negative.
815 'F' like t but negative.
816 'G' constant just the negative
817 'L' fake label, changed after used twice.
818 'M' turn a 'M' constant into its negative mod 2.
819 'P' if operand is incing/decing sp, print .w, otherwise .b.
820 'R' print operand as a byte:8 address if appropriate, else fall back to
822 'S' print operand as a long word
823 'T' print operand as a word
824 'U' if operand is incing/decing sp, print l, otherwise nothing.
825 'V' find the set bit, and print its number.
826 'W' find the clear bit, and print its number.
827 'X' print operand as a byte
828 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
829 If this operand isn't a register, fall back to 'R' handling.
831 'b' print the bit opcode
832 'c' print the ibit opcode
833 'd' bcc if EQ, bcs if NE
834 'e' first word of 32 bit value - if reg, then least reg. if mem
835 then least. if const then most sig word
836 'f' second word of 32 bit value - if reg, then biggest reg. if mem
837 then +2. if const then least sig word
838 'g' bcs if EQ, bcc if NE
839 'j' print operand as condition code.
840 'k' print operand as reverse condition code.
841 's' print as low byte of 16 bit value
842 't' print as high byte of 16 bit value
843 'w' print as low byte of 32 bit value
844 'x' print as 2nd byte of 32 bit value
845 'y' print as 3rd byte of 32 bit value
846 'z' print as msb of 32 bit value
849 /* Return assembly language string which identifies a comparison type. */
882 /* Print operand X using operand code CODE to assembly language output file
886 print_operand (file
, x
, code
)
891 /* This is used to general unique labels for the 'L' code. */
892 static int lab
= 1000;
894 /* This is used for communication between the 'P' and 'U' codes. */
897 /* This is used for communication between codes V,W,Z and Y. */
903 if (GET_CODE (x
) == REG
)
904 fprintf (file
, "%s", h8_reg_names
[REGNO (x
)]);
909 fprintf (file
, "#%d", INTVAL (x
) - 2);
912 switch (GET_CODE (x
))
915 fprintf (file
, "%sl", names_big
[REGNO (x
)]);
918 fprintf (file
, "#%d", (-INTVAL (x
)) & 0xff);
925 switch (GET_CODE (x
))
928 fprintf (file
, "%sh", names_big
[REGNO (x
)]);
931 fprintf (file
, "#%d", ((-INTVAL (x
)) & 0xff00) >> 8);
938 if (GET_CODE (x
) != CONST_INT
)
940 fprintf (file
, "#%d", 0xff & (-INTVAL (x
)));
943 /* 'L' must always be used twice in a single pattern. It generates
944 the same label twice, and then will generate a unique label the
945 next time it is used. */
946 asm_fprintf (file
, "tl%d", (lab
++) / 2);
949 /* For 3/-3 and 4/-4, the other 2 is handled separately. */
956 fprintf (file
, "#2");
962 fprintf (file
, "#1");
969 if (REGNO (XEXP (XEXP (x
, 0), 0)) == STACK_POINTER_REGNUM
)
972 fprintf (file
, ".w");
977 fprintf (file
, ".b");
981 if (GET_CODE (x
) == REG
)
982 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
987 if (GET_CODE (x
) == REG
)
988 fprintf (file
, "%s", names_big
[REGNO (x
)]);
993 fprintf (file
, "%s%s", names_big
[REGNO (x
)], last_p
);
996 bitint
= exact_log2 (INTVAL (x
));
999 fprintf (file
, "#%d", bitint
& 7);
1002 bitint
= exact_log2 ((~INTVAL (x
)) & 0xff);
1005 fprintf (file
, "#%d", bitint
& 7);
1009 if (GET_CODE (x
) == REG
)
1010 fprintf (file
, "%s", byte_reg (x
, 0));
1017 if (GET_CODE (x
) == REG
)
1018 fprintf (file
, "%s%c", names_big
[REGNO (x
)], bitint
> 7 ? 'h' : 'l');
1020 print_operand (file
, x
, 'R');
1024 bitint
= INTVAL (x
);
1025 fprintf (file
, "#%d", bitint
& 7);
1028 switch (GET_CODE (x
))
1031 fprintf (file
, "bor");
1034 fprintf (file
, "bxor");
1037 fprintf (file
, "band");
1042 switch (GET_CODE (x
))
1045 fprintf (file
, "bior");
1048 fprintf (file
, "bixor");
1051 fprintf (file
, "biand");
1056 switch (GET_CODE (x
))
1059 fprintf (file
, "bcc");
1062 fprintf (file
, "bcs");
1069 switch (GET_CODE (x
))
1073 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1075 fprintf (file
, "%s", names_upper_extended
[REGNO (x
)]);
1078 x
= adj_offsettable_operand (x
, 0);
1079 print_operand (file
, x
, 0);
1082 fprintf (file
, "#%d", ((INTVAL (x
) >> 16) & 0xffff));
1090 switch (GET_CODE (x
))
1094 fprintf (file
, "%s", names_big
[REGNO (x
) + 1]);
1096 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1099 x
= adj_offsettable_operand (x
, 2);
1100 print_operand (file
, x
, 0);
1103 fprintf (file
, "#%d", INTVAL (x
) & 0xffff);
1110 switch (GET_CODE (x
))
1113 fprintf (file
, "bcc");
1116 fprintf (file
, "bcs");
1123 asm_fprintf (file
, cond_string (GET_CODE (x
)));
1126 asm_fprintf (file
, cond_string (reverse_condition (GET_CODE (x
))));
1129 if (GET_CODE (x
) == CONST_INT
)
1130 fprintf (file
, "#%d", (INTVAL (x
)) & 0xff);
1132 fprintf (file
, "%s", byte_reg (x
, 0));
1135 if (GET_CODE (x
) == CONST_INT
)
1136 fprintf (file
, "#%d", (INTVAL (x
) >> 8) & 0xff);
1138 fprintf (file
, "%s", byte_reg (x
, 1));
1141 if (GET_CODE (x
) != CONST_INT
)
1143 fprintf (file
, "%d", INTVAL (x
));
1146 if (GET_CODE (x
) == CONST_INT
)
1147 fprintf (file
, "#%d", INTVAL (x
) & 0xff);
1149 fprintf (file
, "%s", byte_reg (x
, TARGET_H8300
? 2 : 0));
1152 if (GET_CODE (x
) == CONST_INT
)
1153 fprintf (file
, "#%d", (INTVAL (x
) >> 8) & 0xff);
1155 fprintf (file
, "%s", byte_reg (x
, TARGET_H8300
? 3 : 1));
1158 if (GET_CODE (x
) == CONST_INT
)
1159 fprintf (file
, "#%d", (INTVAL (x
) >> 16) & 0xff);
1161 fprintf (file
, "%s", byte_reg (x
, 0));
1164 if (GET_CODE (x
) == CONST_INT
)
1165 fprintf (file
, "#%d", (INTVAL (x
) >> 24) & 0xff);
1167 fprintf (file
, "%s", byte_reg (x
, 1));
1172 switch (GET_CODE (x
))
1175 switch (GET_MODE (x
))
1178 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1179 fprintf (file
, "%s", byte_reg (x
, 0));
1180 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1181 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1185 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1189 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1197 fprintf (file
, "@");
1198 output_address (XEXP (x
, 0));
1200 /* If this is an 'R' operand (reference into the 8-bit area),
1201 then specify a symbolic address as "foo:8". */
1203 && GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
1204 && SYMBOL_REF_FLAG (XEXP (x
, 0)))
1205 fprintf (file
, ":8");
1206 if (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
1207 && TINY_DATA_NAME_P (XSTR (XEXP (x
, 0), 0)))
1208 fprintf (file
, ":16");
1215 fprintf (file
, "#");
1216 print_operand_address (file
, x
);
1222 /* Output assembly language output for the address ADDR to FILE. */
1225 print_operand_address (file
, addr
)
1229 switch (GET_CODE (addr
))
1232 fprintf (file
, "%s", h8_reg_names
[REGNO (addr
)]);
1236 fprintf (file
, "-%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1240 fprintf (file
, "%s+", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1244 fprintf (file
, "(");
1245 if (GET_CODE (XEXP (addr
, 0)) == REG
)
1248 print_operand_address (file
, XEXP (addr
, 1));
1249 fprintf (file
, ",");
1250 print_operand_address (file
, XEXP (addr
, 0));
1255 print_operand_address (file
, XEXP (addr
, 0));
1256 fprintf (file
, "+");
1257 print_operand_address (file
, XEXP (addr
, 1));
1259 fprintf (file
, ")");
1264 /* Since the h8/300 only has 16 bit pointers, negative values are also
1265 those >= 32768. This happens for example with pointer minus a
1266 constant. We don't want to turn (char *p - 2) into
1267 (char *p + 65534) because loop unrolling can build upon this
1268 (IE: char *p + 131068). */
1269 int n
= INTVAL (addr
);
1271 n
= (int) (short) n
;
1273 /* ??? Why the special case for -ve values? */
1274 fprintf (file
, "-%d", -n
);
1276 fprintf (file
, "%d", n
);
1281 output_addr_const (file
, addr
);
1286 /* Output all insn addresses and their sizes into the assembly language
1287 output file. This is helpful for debugging whether the length attributes
1288 in the md file are correct. This is not meant to be a user selectable
1292 final_prescan_insn (insn
, operand
, num_operands
)
1296 /* This holds the last insn address. */
1297 static int last_insn_address
= 0;
1299 int uid
= INSN_UID (insn
);
1301 if (TARGET_RTL_DUMP
)
1303 fprintf (asm_out_file
, "\n****************");
1304 print_rtl (asm_out_file
, PATTERN (insn
));
1305 fprintf (asm_out_file
, "\n");
1308 if (TARGET_ADDRESSES
)
1310 fprintf (asm_out_file
, "; 0x%x %d\n", insn_addresses
[uid
],
1311 insn_addresses
[uid
] - last_insn_address
);
1312 last_insn_address
= insn_addresses
[uid
];
1316 /* Prepare for an SI sized move. */
1322 rtx src
= operands
[1];
1323 rtx dst
= operands
[0];
1324 if (!reload_in_progress
&& !reload_completed
)
1326 if (!register_operand (dst
, GET_MODE (dst
)))
1328 rtx tmp
= gen_reg_rtx (GET_MODE (dst
));
1329 emit_move_insn (tmp
, src
);
1336 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1337 Define the offset between two registers, one to be eliminated, and the other
1338 its replacement, at the start of a routine. */
1341 initial_offset (from
, to
)
1345 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
1346 offset
= UNITS_PER_WORD
+ frame_pointer_needed
* UNITS_PER_WORD
;
1351 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1352 if ((regs_ever_live
[regno
]
1353 && (!call_used_regs
[regno
] || regno
== FRAME_POINTER_REGNUM
)))
1354 offset
+= UNITS_PER_WORD
;
1356 /* See the comments for get_frame_size. We need to round it up to
1359 offset
+= ((get_frame_size () + STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
1360 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
1362 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1363 offset
+= UNITS_PER_WORD
; /* Skip saved PC */
1368 /* Update the condition code from the insn. */
1371 notice_update_cc (body
, insn
)
1375 switch (get_attr_cc (insn
))
1378 /* Insn does not affect CC at all. */
1382 /* Insn does not change CC, but the 0'th operand has been changed. */
1383 if (cc_status
.value1
!= 0
1384 && reg_overlap_mentioned_p (recog_operand
[0], cc_status
.value1
))
1385 cc_status
.value1
= 0;
1389 /* Insn sets the Z,N flags of CC to recog_operand[0].
1390 V is always set to 0. C may or may not be set to 0 but that's ok
1391 because alter_cond will change tests to use EQ/NE. */
1393 cc_status
.flags
|= CC_OVERFLOW_0
| CC_NO_CARRY
;
1394 cc_status
.value1
= recog_operand
[0];
1398 /* Insn sets the Z,N flags of CC to recog_operand[0].
1399 The V flag is unusable. The C flag may or may not be known but
1400 that's ok because alter_cond will change tests to use EQ/NE. */
1402 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
1403 cc_status
.value1
= recog_operand
[0];
1407 /* The insn is a compare instruction. */
1409 cc_status
.value1
= SET_SRC (body
);
1413 /* Insn doesn't leave CC in a usable state. */
1419 /* Return 1 if a previous compare needs to be re-issued. This will happen
1420 if the compare was deleted because the previous insn set it, but the
1421 branch needs CC flags not set.
1423 OP is the comparison being performed. */
1426 restore_compare_p (op
)
1429 switch (GET_CODE (op
))
1438 if (cc_status
.flags
& CC_OVERFLOW_UNUSABLE
)
1445 /* If the carry flag isn't usable, the test should have been changed
1447 if (cc_status
.flags
& CC_NO_CARRY
)
1457 /* Recognize valid operators for bit instructions */
1460 bit_operator (x
, mode
)
1462 enum machine_mode mode
;
1464 enum rtx_code code
= GET_CODE (x
);
1473 We devote a fair bit of code to getting efficient shifts since we can only
1474 shift one bit at a time. See the .md file for more comments.
1476 Here are some thoughts on what the absolutely positively best code is.
1477 "Best" here means some rational trade-off between code size and speed,
1478 where speed is more preferred but not at the expense of generating 20 insns.
1480 H8/300 QImode shifts
1481 1-4 - do them inline
1482 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1484 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1485 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1487 H8/300 HImode shifts
1488 1-4 - do them inline
1490 7 - shift other way once, move byte into place, move carry bit into place
1491 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1492 9 - inline shift 1-4, move byte, set other byte
1493 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1495 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1496 - ASHIFTRT: shll, subx, set other byte
1498 H8/300 SImode shifts
1499 1-2 - do them inline
1501 7 - shift other way once, move bytes into place,
1502 move carry into place (possibly with sign extension)
1503 8 - move bytes into place, zero or sign extend other
1505 15 - shift other way once, move word into place, move carry into place
1506 16 - move word, zero or sign extend other
1508 24 - move bytes into place, zero or sign extend other
1510 28-30 - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1513 31 - ASHIFT | LSHIFTRT: rotate top byte, mask, byte byte into place,
1515 ASHIFTRT: shll top byte, subx, copy to other bytes
1517 H8/300H QImode shifts
1520 H8/300H HImode shifts
1523 H8/300H SImode shifts
1524 (These are complicated by the fact that we don't have byte level access to
1526 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1527 1-4 - do them inline
1529 15 - shift other way once, move word into place, move carry into place
1530 (with sign extension for ASHIFTRT)
1531 16 - move word into place, zero or sign extend other
1533 24 - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1534 move word 0 to word 1, zero word 0
1535 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1536 zero word 1, zero byte 1
1537 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1538 sign extend byte 0, sign extend word 0
1539 25-27 - either loop, or
1540 do 24 bit shift, inline rest
1541 28-30 - ASHIFT: rotate 4/3/2, mask
1542 LSHIFTRT: rotate 4/3/2, mask
1544 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1548 All of these haven't been implemented. I've just documented them and
1549 provided hooks so they can be.
1553 nshift_operator (x
, mode
)
1555 enum machine_mode mode
;
1557 switch (GET_CODE (x
))
1569 /* Called from the .md file to emit code to do shifts.
1570 Returns a boolean indicating success
1571 (currently this is always TRUE). */
1574 expand_a_shift (mode
, code
, operands
)
1575 enum machine_mode mode
;
1579 emit_move_insn (operands
[0], operands
[1]);
1581 /* need a loop to get all the bits we want - we generate the
1582 code at emit time, but need to allocate a scratch reg now */
1585 (PARALLEL
, VOIDmode
,
1587 gen_rtx (SET
, VOIDmode
, operands
[0],
1588 gen_rtx (code
, mode
, operands
[0], operands
[2])),
1589 gen_rtx (CLOBBER
, VOIDmode
, gen_rtx (SCRATCH
, QImode
, 0)))));
1594 /* Shift algorithm determination.
1596 There are various ways of doing a shift:
1597 SHIFT_INLINE: If the amount is small enough, just generate as many one-bit
1599 SHIFT_ROT_AND: If the amount is large but close to either end, rotate the
1600 necessary bits into position and then set the rest to zero.
1601 SHIFT_SPECIAL: Hand crafted assembler.
1602 SHIFT_LOOP: If the above methods fail, just loop. */
1613 /* Symbols of the various shifts which can be used as indices. */
1617 SHIFT_ASHIFT
, SHIFT_LSHIFTRT
, SHIFT_ASHIFTRT
1620 /* Symbols of the various modes which can be used as indices. */
1624 QIshift
, HIshift
, SIshift
1627 /* For single bit shift insns, record assembler and what bits of the
1628 condition code are valid afterwards (represented as various CC_FOO
1629 bits, 0 means CC isn't left in a usable state). */
1637 /* Assembler instruction shift table.
1639 These tables are used to look up the basic shifts.
1640 They are indexed by cpu, shift_type, and mode.
1643 static const struct shift_insn shift_one
[2][3][3] =
1649 { "shll %X0", CC_OVERFLOW_0
| CC_NO_CARRY
},
1650 { "add.w %T0,%T0\t; shal.w", CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
},
1651 { "add.w %f0,%f0\t; shal.l\n\taddx %y0,%y0\n\taddx %z0,%z0\t; end shal.l", 0 }
1653 /* SHIFT_LSHIFTRT */
1655 { "shlr %X0", CC_OVERFLOW_0
| CC_NO_CARRY
},
1656 { "shlr %t0\t; shlr.w\n\trotxr %s0\t; end shlr.w", 0 },
1657 { "shlr %z0\t; shlr.l\n\trotxr %y0\n\trotxr %x0\n\trotxr %w0\t; end shlr.l", 0 }
1659 /* SHIFT_ASHIFTRT */
1661 { "shar %X0", CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
},
1662 { "shar %t0\t; shar.w\n\trotxr %s0\t; end shar.w", 0 },
1663 { "shar %z0\t; shar.l\n\trotxr %y0\n\trotxr %x0\n\trotxr %w0\t; end shar.l", 0 }
1670 { "shll.b %X0", CC_OVERFLOW_0
| CC_NO_CARRY
},
1671 { "shll.w %T0", CC_OVERFLOW_0
| CC_NO_CARRY
},
1672 { "shll.l %S0", CC_OVERFLOW_0
| CC_NO_CARRY
}
1674 /* SHIFT_LSHIFTRT */
1676 { "shlr.b %X0", CC_OVERFLOW_0
| CC_NO_CARRY
},
1677 { "shlr.w %T0", CC_OVERFLOW_0
| CC_NO_CARRY
},
1678 { "shlr.l %S0", CC_OVERFLOW_0
| CC_NO_CARRY
}
1680 /* SHIFT_ASHIFTRT */
1682 { "shar.b %X0", CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
},
1683 { "shar.w %T0", CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
},
1684 { "shar.l %S0", CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
}
1689 /* Rotates are organized by which shift they'll be used in implementing.
1690 There's no need to record whether the cc is valid afterwards because
1691 it is the AND insn that will decide this. */
1693 static const char *const rotate_one
[2][3][3] =
1700 "shlr %t0\t; rotr.w\n\trotxr %s0\n\tbst #7,%t0\t; end rotr.w",
1703 /* SHIFT_LSHIFTRT */
1706 "shll %s0\t; rotl.w\n\trotxl %t0\n\tbst #0,%s0\t; end rotl.w",
1709 /* SHIFT_ASHIFTRT */
1712 "shll %s0\t; rotl.w\n\trotxl %t0\n\tbst #0,%s0\t; end rotl.w",
1724 /* SHIFT_LSHIFTRT */
1730 /* SHIFT_ASHIFTRT */
1739 /* Given CPU, MODE, SHIFT_TYPE, and shift count COUNT, determine the best
1740 algorithm for doing the shift. The assembler code is stored in ASSEMBLER.
1741 We don't achieve maximum efficiency in all cases, but the hooks are here
1744 For now we just use lots of switch statements. Since we don't even come
1745 close to supporting all the cases, this is simplest. If this function ever
1746 gets too big, perhaps resort to a more table based lookup. Of course,
1747 at this point you may just wish to do it all in rtl.
1749 WARNING: The constraints on insns shiftbyn_QI/HI/SI assume shifts of
1750 1,2,3,4 will be inlined (1,2 for SI). */
1752 static enum shift_alg
1753 get_shift_alg (cpu
, shift_type
, mode
, count
, assembler_p
, cc_valid_p
)
1755 enum shift_type shift_type
;
1756 enum machine_mode mode
;
1758 const char **assembler_p
;
1761 /* The default is to loop. */
1762 enum shift_alg alg
= SHIFT_LOOP
;
1763 enum shift_mode shift_mode
;
1765 /* We don't handle negative shifts or shifts greater than the word size,
1766 they should have been handled already. */
1768 if (count
< 0 || count
> GET_MODE_BITSIZE (mode
))
1774 shift_mode
= QIshift
;
1777 shift_mode
= HIshift
;
1780 shift_mode
= SIshift
;
1786 /* Assume either SHIFT_LOOP or SHIFT_INLINE.
1787 It is up to the caller to know that looping clobbers cc. */
1788 *assembler_p
= shift_one
[cpu
][shift_type
][shift_mode
].assembler
;
1789 *cc_valid_p
= shift_one
[cpu
][shift_type
][shift_mode
].cc_valid
;
1791 /* Now look for cases we want to optimize. */
1797 return SHIFT_INLINE
;
1798 else if (count
<= 6)
1800 if (shift_type
== SHIFT_ASHIFTRT
)
1806 *assembler_p
= rotate_one
[cpu
][shift_type
][shift_mode
];
1808 return SHIFT_ROT_AND
;
1811 else if (count
== 7)
1813 if (shift_type
== SHIFT_ASHIFTRT
)
1815 *assembler_p
= "shll %X0\t; shar.b(7)\n\tsubx %X0,%X0\t; end shar.b(7)";
1817 return SHIFT_SPECIAL
;
1821 *assembler_p
= rotate_one
[cpu
][shift_type
][shift_mode
];
1823 return SHIFT_ROT_AND
;
1829 return SHIFT_INLINE
;
1830 else if (count
== 8)
1835 *assembler_p
= "mov.b %s0,%t0\t; shal.w(8)\n\tsub.b %s0,%s0\t; end shal.w(8)";
1837 return SHIFT_SPECIAL
;
1838 case SHIFT_LSHIFTRT
:
1839 *assembler_p
= "mov.b %t0,%s0\t; shlr.w(8)\n\tsub.b %t0,%t0\t; end shlr.w(8)";
1841 return SHIFT_SPECIAL
;
1842 case SHIFT_ASHIFTRT
:
1843 if (cpu
== CPU_H8300
)
1844 *assembler_p
= "mov.b %t0,%s0\t; shar.w(8)\n\tshll %t0\n\tsubx %t0,%t0\t; end shar.w(8)";
1846 *assembler_p
= "mov.b %t0,%s0\t; shar.w(8)\n\texts.w %T0\t; end shar.w(8)";
1848 return SHIFT_SPECIAL
;
1852 else if (count
== 15)
1854 if (shift_type
== SHIFT_ASHIFTRT
)
1856 *assembler_p
= "shll %t0,%t0\t; shar.w(15)\n\tsubx %t0,%t0\n\tmov.b %t0,%s0\t; end shar.w(15)";
1858 return SHIFT_SPECIAL
;
1862 *assembler_p
= rotate_one
[cpu
][shift_type
][shift_mode
];
1864 return SHIFT_ROT_AND
;
1869 if (count
<= (cpu
== CPU_H8300
? 2 : 4))
1870 return SHIFT_INLINE
;
1871 else if (count
== 8)
1873 if (cpu
== CPU_H8300
)
1878 *assembler_p
= "mov.b %y0,%z0\t; shal.l(8)\n\tmov.b %x0,%y0\n\tmov.b %w0,%x0\n\tsub.b %w0,%w0\t; end shal.l(8)";
1880 return SHIFT_SPECIAL
;
1881 case SHIFT_LSHIFTRT
:
1882 *assembler_p
= "mov.b %x0,%w0\t; shlr.l(8)\n\tmov.b %y0,%x0\n\tmov.b %z0,%y0\n\tsub.b %z0,%z0\t; end shlr.l(8)";
1884 return SHIFT_SPECIAL
;
1885 case SHIFT_ASHIFTRT
:
1886 *assembler_p
= "mov.b %x0,%w0\t; shar.l(8)\n\tmov.b %y0,%x0\n\tmov.b %z0,%y0\n\tshll %z0\n\tsubx %z0,%z0; end shar.l(8)";
1888 return SHIFT_SPECIAL
;
1891 else /* CPU_H8300H */
1892 /* We don't have byte level access to the high word so this isn't
1893 easy to do. For now, just loop. */
1896 else if (count
== 16)
1901 *assembler_p
= "mov.w %f0,%e0\t; shal.l(16)\n\tsub.w %f0,%f0\t; end shal.l(16)";
1903 return SHIFT_SPECIAL
;
1904 case SHIFT_LSHIFTRT
:
1905 *assembler_p
= "mov.w %e0,%f0\t; shlr.l(16)\n\tsub.w %e0,%e0\t; end shlr.l(16)";
1907 return SHIFT_SPECIAL
;
1908 case SHIFT_ASHIFTRT
:
1909 if (cpu
== CPU_H8300
)
1910 *assembler_p
= "mov.w %e0,%f0\t; shar.l(16)\n\tshll %z0\n\tsubx %z0,%z0\n\tmov.b %z0,%y0\t; end shar.l(16)";
1912 *assembler_p
= "mov.w %e0,%f0\t; shar.l(16)\n\texts.l %S0\t; end shar.l(16)";
1914 return SHIFT_SPECIAL
;
1917 else if (count
>= 28 && count
<= 30)
1919 if (shift_type
== SHIFT_ASHIFTRT
)
1925 if (cpu
== CPU_H8300
)
1929 *assembler_p
= rotate_one
[cpu
][shift_type
][shift_mode
];
1931 return SHIFT_ROT_AND
;
1935 else if (count
== 31)
1937 if (shift_type
== SHIFT_ASHIFTRT
)
1939 if (cpu
== CPU_H8300
)
1940 *assembler_p
= "shll %z0\t; shar.l(31)\n\tsubx %w0,%w0\n\tmov.b %w0,%x0\n\tmov.w %f0,%e0\t; end shar.l(31)";
1942 *assembler_p
= "shll %e0\t; shar.l(31)\n\tsubx %w0,%w0\n\tmov.b %w0,%x0\n\tmov.w %f0,%e0\t; end shar.l(31)";
1944 return SHIFT_SPECIAL
;
1948 if (cpu
== CPU_H8300
)
1950 if (shift_type
== SHIFT_ASHIFT
)
1951 *assembler_p
= "sub.w %e0,%e0\t; shal.l(31)\n\tshlr %w0\n\tmov.w %e0,%f0\n\trotxr %z0\t; end shal.l(31)";
1953 *assembler_p
= "sub.w %f0,%f0\t; shlr.l(31)\n\tshll %z0\n\tmov.w %f0,%e0\n\trotxl %w0\t; end shlr.l(31)";
1955 return SHIFT_SPECIAL
;
1959 *assembler_p
= rotate_one
[cpu
][shift_type
][shift_mode
];
1961 return SHIFT_ROT_AND
;
1973 /* Emit the assembler code for doing shifts. */
1976 emit_a_shift (insn
, operands
)
1980 static int loopend_lab
;
1983 rtx inside
= PATTERN (insn
);
1984 rtx shift
= operands
[3];
1985 enum machine_mode mode
= GET_MODE (shift
);
1986 enum rtx_code code
= GET_CODE (shift
);
1987 enum shift_type shift_type
;
1988 enum shift_mode shift_mode
;
1995 shift_mode
= QIshift
;
1998 shift_mode
= HIshift
;
2001 shift_mode
= SIshift
;
2010 shift_type
= SHIFT_ASHIFTRT
;
2013 shift_type
= SHIFT_LSHIFTRT
;
2016 shift_type
= SHIFT_ASHIFT
;
2022 if (GET_CODE (operands
[2]) != CONST_INT
)
2024 /* Indexing by reg, so have to loop and test at top */
2025 output_asm_insn ("mov.b %X2,%X4", operands
);
2026 fprintf (asm_out_file
, "\tble .Lle%d\n", loopend_lab
);
2028 /* Get the assembler code to do one shift. */
2029 get_shift_alg (cpu_type
, shift_type
, mode
, 1, &assembler
, &cc_valid
);
2033 int n
= INTVAL (operands
[2]);
2036 /* If the count is negative, make it 0. */
2039 /* If the count is too big, truncate it.
2040 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
2041 do the intuitive thing. */
2042 else if (n
> GET_MODE_BITSIZE (mode
))
2043 n
= GET_MODE_BITSIZE (mode
);
2045 alg
= get_shift_alg (cpu_type
, shift_type
, mode
, n
, &assembler
, &cc_valid
);
2051 output_asm_insn (assembler
, operands
);
2054 cc_status
.value1
= operands
[0];
2055 cc_status
.flags
|= cc_valid
;
2060 int m
= GET_MODE_BITSIZE (mode
) - n
;
2061 int mask
= (shift_type
== SHIFT_ASHIFT
2062 ? ((1 << GET_MODE_BITSIZE (mode
) - n
) - 1) << n
2063 : (1 << GET_MODE_BITSIZE (mode
) - n
) - 1);
2065 /* Not all possibilities of rotate are supported. They shouldn't
2066 be generated, but let's watch for 'em. */
2070 output_asm_insn (assembler
, operands
);
2076 sprintf (insn_buf
, "and #%d,%%X0\t; end shift %d via rotate+and",
2078 cc_status
.value1
= operands
[0];
2079 cc_status
.flags
|= CC_OVERFLOW_0
| CC_NO_CARRY
;
2082 sprintf (insn_buf
, "and #%d,%%s0\n\tand #%d,%%t0\t; end shift %d via rotate+and",
2083 mask
& 255, mask
>> 8, n
);
2091 sprintf (insn_buf
, "and.%c #%d,%%%c0",
2092 "bwl"[shift_mode
], mask
,
2093 mode
== QImode
? 'X' : mode
== HImode
? 'T' : 'S');
2094 cc_status
.value1
= operands
[0];
2095 cc_status
.flags
|= CC_OVERFLOW_0
| CC_NO_CARRY
;
2097 output_asm_insn (insn_buf
, operands
);
2101 output_asm_insn (assembler
, operands
);
2105 /* Need a loop, move limit to tmp reg */
2106 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
, names_big
[REGNO (operands
[4])]);
2109 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
2110 output_asm_insn (assembler
, operands
);
2111 output_asm_insn ("add #0xff,%X4", operands
);
2112 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
2113 fprintf (asm_out_file
, ".Lle%d:\n", loopend_lab
);
2118 /* Fix the operands of a gen_xxx so that it could become a bit
2122 fix_bit_operand (operands
, what
, type
)
2127 /* The bit_operand predicate accepts any memory during RTL generation, but
2128 only 'U' memory afterwards, so if this is a MEM operand, we must force
2129 it to be valid for 'U' by reloading the address. */
2131 if (GET_CODE (operands
[2]) == CONST_INT
)
2133 if (CONST_OK_FOR_LETTER_P (INTVAL (operands
[2]), what
))
2135 /* Ok to have a memory dest. */
2136 if (GET_CODE (operands
[0]) == MEM
&& !EXTRA_CONSTRAINT (operands
[0], 'U'))
2139 mem
= gen_rtx (MEM
, GET_MODE (operands
[0]),
2140 copy_to_mode_reg (Pmode
, XEXP (operands
[0], 0)));
2141 RTX_UNCHANGING_P (mem
) = RTX_UNCHANGING_P (operands
[0]);
2142 MEM_IN_STRUCT_P (mem
) = MEM_IN_STRUCT_P (operands
[0]);
2143 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (operands
[0]);
2147 if (GET_CODE (operands
[1]) == MEM
&& !EXTRA_CONSTRAINT (operands
[1], 'U'))
2150 mem
= gen_rtx (MEM
, GET_MODE (operands
[1]),
2151 copy_to_mode_reg (Pmode
, XEXP (operands
[1], 0)));
2152 RTX_UNCHANGING_P (mem
) = RTX_UNCHANGING_P (operands
[1]);
2153 MEM_IN_STRUCT_P (mem
) = MEM_IN_STRUCT_P (operands
[1]);
2154 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (operands
[1]);
2161 /* Dest and src op must be register. */
2163 operands
[1] = force_reg (QImode
, operands
[1]);
2165 rtx res
= gen_reg_rtx (QImode
);
2166 emit_insn (gen_rtx (SET
, VOIDmode
, res
, gen_rtx (type
, QImode
, operands
[1], operands
[2])));
2167 emit_insn (gen_rtx (SET
, VOIDmode
, operands
[0], res
));
2172 /* Return nonzero if FUNC is an interrupt function as specified
2173 by the "interrupt" attribute. */
2176 h8300_interrupt_function_p (func
)
2181 if (TREE_CODE (func
) != FUNCTION_DECL
)
2184 a
= lookup_attribute ("interrupt_handler", DECL_MACHINE_ATTRIBUTES (func
));
2185 return a
!= NULL_TREE
;
2188 /* Return nonzero if FUNC is a function that should be called
2189 through the function vector. */
2192 h8300_funcvec_function_p (func
)
2197 if (TREE_CODE (func
) != FUNCTION_DECL
)
2200 a
= lookup_attribute ("function_vector", DECL_MACHINE_ATTRIBUTES (func
));
2201 return a
!= NULL_TREE
;
2204 /* Return nonzero if DECL is a variable that's in the eight bit
2208 h8300_eightbit_data_p (decl
)
2213 if (TREE_CODE (decl
) != VAR_DECL
)
2216 a
= lookup_attribute ("eightbit_data", DECL_MACHINE_ATTRIBUTES (decl
));
2217 return a
!= NULL_TREE
;
2220 /* Return nonzero if DECL is a variable that's in the tiny
2224 h8300_tiny_data_p (decl
)
2229 if (TREE_CODE (decl
) != VAR_DECL
)
2232 a
= lookup_attribute ("tiny_data", DECL_MACHINE_ATTRIBUTES (decl
));
2233 return a
!= NULL_TREE
;
2236 /* Return nonzero if ATTR is a valid attribute for DECL.
2237 ATTRIBUTES are any existing attributes and ARGS are the arguments
2240 Supported attributes:
2242 interrupt_handler: output a prologue and epilogue suitable for an
2245 function_vector: This function should be called through the
2248 eightbit_data: This variable lives in the 8-bit data area and can
2249 be referenced with 8-bit absolute memory addresses.
2251 tiny_data: This variable lives in the tiny data area and can be
2252 referenced with 16-bit absolute memory references. */
2255 h8300_valid_machine_decl_attribute (decl
, attributes
, attr
, args
)
2261 if (args
!= NULL_TREE
)
2264 if (is_attribute_p ("interrupt_handler", attr
)
2265 || is_attribute_p ("function_vector", attr
))
2266 return TREE_CODE (decl
) == FUNCTION_DECL
;
2268 if (is_attribute_p ("eightbit_data", attr
)
2269 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
2271 if (DECL_INITIAL (decl
) == NULL_TREE
)
2273 warning ("Only initialized variables can be placed into the 8-bit area.");
2276 DECL_SECTION_NAME (decl
) = build_string (7, ".eight");
2280 if (is_attribute_p ("tiny_data", attr
)
2281 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
2283 if (DECL_INITIAL (decl
) == NULL_TREE
)
2285 warning ("Only initialized variables can be placed into the 8-bit area.");
2288 DECL_SECTION_NAME (decl
) = build_string (6, ".tiny");
2295 extern struct obstack
*saveable_obstack
;
2297 h8300_encode_label (decl
)
2300 char *str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2301 int len
= strlen (str
);
2304 newstr
= obstack_alloc (saveable_obstack
, len
+ 2);
2306 strcpy (newstr
+ 1, str
);
2308 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
2312 output_simode_bld (bild
, log2
, operands
)
2317 /* Clear the destination register. */
2319 output_asm_insn ("sub.l\t%S0,%S0", operands
);
2321 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands
);
2323 /* Get the bit number we want to load. */
2325 operands
[2] = GEN_INT (exact_log2 (INTVAL (operands
[2])));
2327 /* Now output the bit load or bit inverse load, and store it in
2330 output_asm_insn ("bild\t%Z2,%Y1\n\tbst\t#0,%w0", operands
);
2332 output_asm_insn ("bld\t%Z2,%Y1\n\tbst\t#0,%w0", operands
);
2338 /* Given INSN and it's current length LENGTH, return the adjustment
2339 (in bytes) to correctly compute INSN's length.
2341 We use this to get the lengths of various memory references correct. */
2343 h8300_adjust_insn_length (insn
, length
)
2347 rtx pat
= PATTERN (insn
);
2349 /* Adjust length for reg->mem and mem->reg copies. */
2350 if (GET_CODE (pat
) == SET
2351 && (GET_CODE (SET_SRC (pat
)) == MEM
2352 || GET_CODE (SET_DEST (pat
)) == MEM
))
2354 /* This insn might need a length adjustment. */
2357 if (GET_CODE (SET_SRC (pat
)) == MEM
)
2358 addr
= XEXP (SET_SRC (pat
), 0);
2360 addr
= XEXP (SET_DEST (pat
), 0);
2362 /* On the H8/300, only one adjustment is necessary; if the
2363 address mode is register indirect, then this insn is two
2364 bytes shorter than indicated in the machine description. */
2365 if (TARGET_H8300
&& GET_CODE (addr
) == REG
)
2368 /* On the H8/300H, register indirect is 6 bytes shorter than
2369 indicated in the machine description. */
2370 if (TARGET_H8300H
&& GET_CODE (addr
) == REG
)
2373 /* On the H8/300H, reg + d, for small displacements is 4 bytes
2374 shorter than indicated in the machine description. */
2376 && GET_CODE (addr
) == PLUS
2377 && GET_CODE (XEXP (addr
, 0)) == REG
2378 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
2379 && INTVAL (XEXP (addr
, 1)) > -32768
2380 && INTVAL (XEXP (addr
, 1)) < 32767)
2383 /* On the H8/300H, abs:16 is two bytes shorter than the
2384 more general abs:24. */
2386 && GET_CODE (addr
) == SYMBOL_REF
2387 && TINY_DATA_NAME_P (XSTR (addr
, 0)))
2391 /* Loading some constants needs adjustment. */
2392 if (GET_CODE (pat
) == SET
2393 && GET_CODE (SET_SRC (pat
)) == CONST_INT
2394 && GET_MODE (SET_DEST (pat
)) == SImode
2395 && INTVAL (SET_SRC (pat
)) != 0)
2398 && ((INTVAL (SET_SRC (pat
)) & 0xffff) == 0
2399 || ((INTVAL (SET_SRC (pat
)) >> 16) & 0xffff) == 0))
2404 int val
= INTVAL (SET_SRC (pat
));
2406 if (val
== (val
& 0xff)
2407 || val
== (val
& 0xff00))
2410 if (val
== -4 || val
== -2 || val
== -1)
2415 /* Shifts need various adjustments. */
2416 if (GET_CODE (pat
) == PARALLEL
2417 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
2418 && (GET_CODE (SET_SRC (XVECEXP (pat
, 0, 0))) == ASHIFTRT
2419 || GET_CODE (SET_SRC (XVECEXP (pat
, 0, 0))) == LSHIFTRT
2420 || GET_CODE (SET_SRC (XVECEXP (pat
, 0, 0))) == ASHIFT
))
2422 rtx src
= SET_SRC (XVECEXP (pat
, 0, 0));
2423 enum machine_mode mode
= GET_MODE (src
);
2425 if (GET_CODE (XEXP (src
, 1)) != CONST_INT
)
2428 /* QImode shifts by small constants take one insn
2429 per shift. So the adjustment is 20 (md length) -
2431 if (mode
== QImode
&& INTVAL (XEXP (src
, 1)) <= 4)
2432 return -(20 - INTVAL (XEXP (src
, 1)) * 2);
2434 /* Similarly for HImode and SImode shifts by
2435 small constants on the H8/300H. */
2437 && (mode
== HImode
|| mode
== SImode
)
2438 && INTVAL (XEXP (src
, 1)) <= 4)
2439 return -(20 - INTVAL (XEXP (src
, 1)) * 2);
2441 /* HImode shifts by small constants for the H8/300. */
2443 && INTVAL (XEXP (src
, 1)) <= 4)
2444 return -(20 - (INTVAL (XEXP (src
, 1))
2445 * (GET_CODE (src
) == ASHIFT
? 2 : 4)));
2447 /* SImode shifts by small constants for the H8/300. */
2449 && INTVAL (XEXP (src
, 1)) <= 2)
2450 return -(20 - (INTVAL (XEXP (src
, 1))
2451 * (GET_CODE (src
) == ASHIFT
? 6 : 8)));
2453 /* XXX ??? Could check for more shift/rotate cases here. */