1 ;; GCC machine description for Hitachi H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001 Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 ;; This file is part of GNU CC.
10 ;; GNU CC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GNU CC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GNU CC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;; The original PO technology requires these to be ordered by speed,
26 ;; so that assigner will pick the fastest.
28 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 (define_attr "cpu" "h8300,h8300h"
31 (const (symbol_ref "cpu_type")))
33 ;; Many logical operations should have "bit" variants if only one
34 ;; bit is going to be operated on.
36 ;; (and (logical op) (const_int X))
37 ;; If const_int only specifies a few bits (like a single byte in a 4 byte
38 ;; operation, then it's more efficient to only apply the and and logical_op
39 ;; to the bits we care about.
41 ;; Some of the extend instructions accept a general_operand_src, which
42 ;; allows all the normal memory addressing modes. The length computations
43 ;; don't take this into account. The lengths in the MD file should be
44 ;; "worst case" and then be adjusted to their correct values by
45 ;; h8300_adjust_insn_length.
47 ;; On the h8300h, adds/subs operate on the 32bit "er" registers. Right
48 ;; now GCC doesn't expose the "e" half to the compiler, so using add/subs
49 ;; for addhi and subhi is safe.
50 ;; Long term, we want to expose the "e" half to the compiler (gives us
51 ;; 8 more 16bit registers). At that point addhi and subhi can't use adds/subs.
53 ;; There's currently no way to have a insv/extzv expander for the H8/300H
54 ;; because word_mode is different for the H8/300 and H8/300H.
56 ;; Shifts/rotates by small constants should be handled by special
57 ;; patterns so we get the length and cc status correct.
59 ;; Bitfield operations no longer accept memory operands. We need
60 ;; to add variants which operate on memory back to the MD.
62 ;; ??? Implement remaining bit ops available on the h8300
64 (define_attr "type" "branch,arith"
65 (const_string "arith"))
67 ;; The size of instructions in bytes.
69 (define_attr "length" ""
70 (cond [(eq_attr "type" "branch")
71 (if_then_else (and (ge (minus (pc) (match_dup 0))
73 (le (minus (pc) (match_dup 0))
76 (if_then_else (and (eq_attr "cpu" "h8300h")
77 (and (ge (minus (pc) (match_dup 0))
79 (le (minus (pc) (match_dup 0))
85 ;; The necessity of instruction length adjustment.
87 (define_attr "adjust_length" "yes,no"
88 (cond [(eq_attr "type" "branch") (const_string "no")]
89 (const_string "yes")))
91 ;; Condition code settings.
92 ;; none - insn does not affect cc
93 ;; none_0hit - insn does not affect cc but it does modify operand 0
94 ;; This attribute is used to keep track of when operand 0 changes.
95 ;; See the description of NOTICE_UPDATE_CC for more info.
96 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
97 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
98 ;; compare - compare instruction
99 ;; clobber - value of cc is unknown
100 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
101 (const_string "clobber"))
103 ;; ----------------------------------------------------------------------
105 ;; ----------------------------------------------------------------------
110 [(set (match_operand:QI 0 "general_operand_dst_push" "=r,r ,<,T,r,r,m")
111 (match_operand:QI 1 "general_operand_src" " I,r>,r,r,n,m,r"))]
113 && (register_operand (operands[0],QImode)
114 || register_operand (operands[1], QImode))"
123 [(set_attr "length" "2,2,2,2,2,4,4")
124 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv,set_znv")])
127 [(set (match_operand:QI 0 "general_operand_dst_push" "=r,r ,<,r,T,r,m")
128 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,r,m,r"))]
129 "(TARGET_H8300H || TARGET_H8300S)
130 && (register_operand (operands[0],QImode)
131 || register_operand (operands[1], QImode))"
140 [(set_attr "length" "2,2,2,2,4,8,8")
141 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv,set_znv")])
143 (define_expand "movqi"
144 [(set (match_operand:QI 0 "general_operand_dst_push" "")
145 (match_operand:QI 1 "general_operand_src" ""))]
149 /* One of the ops has to be in a register. */
150 if (!register_operand (operand0, QImode)
151 && !register_operand (operand1, QImode))
153 operands[1] = copy_to_mode_reg (QImode, operand1);
157 (define_insn "movstrictqi"
158 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r,r,r"))
159 (match_operand:QI 1 "general_operand_src" "I,r,n,m"))]
166 [(set_attr_alternative "length"
167 [(const_int 2) (const_int 2) (const_int 2)
168 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
169 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
174 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
175 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
177 && (register_operand (operands[0],HImode)
178 || register_operand (operands[1], HImode))
179 && !(GET_CODE (operands[0]) == MEM
180 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
181 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
182 && GET_CODE (operands[1]) == REG
183 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
191 [(set_attr "length" "2,2,2,4,4,4")
192 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
195 [(set (match_operand:HI 0 "general_operand_dst_push" "=r,r,<,T,r,r,m")
196 (match_operand:HI 1 "general_operand_src" "I,r>,r,r,i,m,r"))]
197 "(TARGET_H8300H || TARGET_H8300S)
198 && (register_operand (operands[0],HImode)
199 || register_operand (operands[1], HImode))"
208 [(set_attr "length" "2,2,2,4,4,8,8")
209 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv,set_znv")])
211 (define_expand "movhi"
212 [(set (match_operand:HI 0 "general_operand_dst_push" "")
213 (match_operand:HI 1 "general_operand_src" ""))]
217 /* One of the ops has to be in a register. */
218 if (!register_operand (operand1, HImode)
219 && !register_operand (operand0, HImode))
221 operands[1] = copy_to_mode_reg (HImode, operand1);
225 (define_insn "movstricthi"
226 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r,r"))
227 (match_operand:HI 1 "general_operand_src" "I,r,i,m"))]
234 [(set_attr_alternative "length"
235 [(const_int 2) (const_int 2) (const_int 4)
236 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
237 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
241 (define_expand "movsi"
242 [(set (match_operand:SI 0 "general_operand_dst" "")
243 (match_operand:SI 1 "general_operand_src" ""))]
249 if (do_movsi (operands))
254 /* One of the ops has to be in a register. */
255 if (!register_operand (operand1, SImode)
256 && !register_operand (operand0, SImode))
258 operands[1] = copy_to_mode_reg (SImode, operand1);
263 (define_expand "movsf"
264 [(set (match_operand:SF 0 "general_operand_dst" "")
265 (match_operand:SF 1 "general_operand_src" ""))]
271 if (do_movsi (operands))
276 /* One of the ops has to be in a register. */
277 if (!register_operand (operand1, SFmode)
278 && !register_operand (operand0, SFmode))
280 operands[1] = copy_to_mode_reg (SFmode, operand1);
285 (define_insn "movsi_h8300"
286 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
287 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
289 && (register_operand (operands[0], SImode)
290 || register_operand (operands[1], SImode))"
294 switch (which_alternative)
297 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
299 if (REGNO (operands[0]) < REGNO (operands[1]))
300 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
302 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
304 /* Make sure we don't trample the register we index with. */
305 if (GET_CODE (operands[1]) == MEM)
307 rtx inside = XEXP (operands[1],0);
312 else if (GET_CODE (inside) == PLUS)
314 rtx lhs = XEXP (inside,0);
315 rtx rhs = XEXP (inside,1);
316 if (REG_P (lhs)) rn = REGNO (lhs);
317 if (REG_P (rhs)) rn = REGNO (rhs);
320 if (rn == REGNO (operands[0]))
322 /* Move the second word first. */
323 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
327 /* See if either half is zero. If so, use sub.w to clear
329 if (GET_CODE (operands[1]) == CONST_INT)
331 if ((INTVAL (operands[1]) & 0xffff) == 0)
332 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
333 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
334 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
336 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
339 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
341 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
343 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
348 [(set_attr "length" "4,4,8,8,4,4")
349 (set_attr "cc" "clobber")])
351 (define_insn "movsf_h8300"
352 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
353 (match_operand:SF 1 "general_operand_src" "I,r,io,r,r,>"))]
355 && (register_operand (operands[0], SFmode)
356 || register_operand (operands[1], SFmode))"
359 /* Copy of the movsi stuff. */
361 switch (which_alternative)
364 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
366 if (REGNO (operands[0]) < REGNO (operands[1]))
367 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
369 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
371 /* Make sure we don't trample the register we index with. */
372 if (GET_CODE (operands[1]) == MEM)
374 rtx inside = XEXP (operands[1],0);
379 else if (GET_CODE (inside) == PLUS)
381 rtx lhs = XEXP (inside,0);
382 rtx rhs = XEXP (inside,1);
383 if (REG_P (lhs)) rn = REGNO (lhs);
384 if (REG_P (rhs)) rn = REGNO (rhs);
387 if (rn == REGNO (operands[0]))
388 /* Move the second word first. */
389 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
391 /* Move the first word first. */
392 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
395 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
397 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
399 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
404 [(set_attr "length" "4,4,8,8,4,4")
405 (set_attr "cc" "clobber")])
407 (define_insn "movsi_h8300hs"
408 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,r,m,<,r,*a,*a,r")
409 (match_operand:SI 1 "general_operand_src" "I,r,i,m,r,r,>,I,r,*a"))]
410 "(TARGET_H8300S || TARGET_H8300H)
411 && (register_operand (operands[0], SImode)
412 || register_operand (operands[1], SImode))
413 && !(GET_CODE (operands[0]) == MEM
414 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
415 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
416 && GET_CODE (operands[1]) == REG
417 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
420 switch (which_alternative)
423 return \"sub.l %S0,%S0\";
427 return \"clrmac\;ldmac %1,macl\";
429 return \"stmac macl,%0\";
431 if (GET_CODE (operands[1]) == CONST_INT)
433 int val = INTVAL (operands[1]);
435 /* Look for constants which can be made by adding an 8-bit
436 number to zero in one of the two low bytes. */
437 if (val == (val & 0xff))
439 operands[1] = GEN_INT ((char) val & 0xff);
440 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
443 if (val == (val & 0xff00))
445 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
446 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
449 /* Look for constants that can be obtained by subs, inc, and
454 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
456 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
458 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
461 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
463 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
466 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
468 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
471 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
473 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
477 return \"mov.l %S1,%S0\";
479 [(set_attr "length" "2,2,10,10,10,4,4,2,6,4")
480 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
482 (define_insn "movsf_h8300h"
483 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
484 (match_operand:SF 1 "general_operand_src" "I,r,im,r,r,>"))]
485 "(TARGET_H8300H || TARGET_H8300S)
486 && (register_operand (operands[0], SFmode)
487 || register_operand (operands[1], SFmode))"
495 [(set_attr "length" "2,2,10,10,4,4")
496 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
498 ;; ----------------------------------------------------------------------
500 ;; ----------------------------------------------------------------------
503 [(set (cc0) (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "rU")
505 (match_operand:QI 1 "const_int_operand" "n")))]
508 [(set_attr "length" "2")
509 (set_attr "cc" "set_zn")])
512 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "rU")
514 (match_operand:QI 1 "const_int_operand" "n")))]
517 [(set_attr "length" "2")
518 (set_attr "cc" "set_zn")])
521 [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_memory_operand" "rU")
523 (match_operand:QI 1 "const_int_operand" "n")))]
526 [(set_attr "length" "2")
527 (set_attr "cc" "set_zn")])
530 [(set (cc0) (zero_extract:QI (match_operand:HI 0 "register_operand" "r")
532 (match_operand:HI 1 "const_int_operand" "n")))]
535 [(set_attr "length" "2")
536 (set_attr "cc" "set_zn")])
539 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
541 (match_operand:HI 1 "const_int_operand" "n")))]
544 [(set_attr "length" "2")
545 (set_attr "cc" "set_zn")])
548 [(set (cc0) (zero_extract:SI (match_operand:HI 0 "register_operand" "r")
550 (match_operand:HI 1 "const_int_operand" "n")))]
553 [(set_attr "length" "2")
554 (set_attr "cc" "set_zn")])
557 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
560 [(set_attr "length" "2")
561 (set_attr "cc" "set_znv")])
564 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
567 [(set_attr "length" "2")
568 (set_attr "cc" "set_znv")])
571 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
572 "TARGET_H8300H || TARGET_H8300S"
574 [(set_attr "length" "2")
575 (set_attr "cc" "set_znv")])
579 (compare:QI (match_operand:QI 0 "register_operand" "r")
580 (match_operand:QI 1 "nonmemory_operand" "rn")))]
583 [(set_attr "length" "2")
584 (set_attr "cc" "compare")])
586 (define_expand "cmphi"
588 (compare:HI (match_operand:HI 0 "register_operand" "")
589 (match_operand:HI 1 "nonmemory_operand" "")))]
593 /* Force operand1 into a register if we're compiling
595 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
596 operands[1] = force_reg (HImode, operands[1]);
601 (compare:HI (match_operand:HI 0 "register_operand" "r")
602 (match_operand:HI 1 "register_operand" "r")))]
605 [(set_attr "length" "2")
606 (set_attr "cc" "compare")])
610 (compare:HI (match_operand:HI 0 "register_operand" "r,r")
611 (match_operand:HI 1 "nonmemory_operand" "r,n")))]
612 "TARGET_H8300H || TARGET_H8300S"
614 [(set_attr "length" "2,4")
615 (set_attr "cc" "compare,compare")])
619 (compare:SI (match_operand:SI 0 "register_operand" "r,r")
620 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
621 "TARGET_H8300H || TARGET_H8300S"
623 [(set_attr "length" "2,6")
624 (set_attr "cc" "compare,compare")])
626 ;; ----------------------------------------------------------------------
628 ;; ----------------------------------------------------------------------
630 (define_insn "addqi3"
631 [(set (match_operand:QI 0 "register_operand" "=r")
632 (plus:QI (match_operand:QI 1 "register_operand" "%0")
633 (match_operand:QI 2 "nonmemory_operand" "rn")))]
636 [(set_attr "length" "2")
637 (set_attr "cc" "set_zn")])
639 (define_expand "addhi3"
640 [(set (match_operand:HI 0 "register_operand" "")
641 (plus:HI (match_operand:HI 1 "register_operand" "")
642 (match_operand:HI 2 "nonmemory_operand" "")))]
647 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,&r")
648 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,g")
649 (match_operand:HI 2 "nonmemory_operand" "L,N,n,r,r")))]
654 add.b %s2,%s0\;addx %t2,%t0
656 mov.w %T1,%T0\;add.w %T2,%T0"
657 [(set_attr "length" "2,2,4,2,6")
658 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
661 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
662 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0")
663 (match_operand:HI 2 "nonmemory_operand" "L,N,n,r")))]
664 "TARGET_H8300H || TARGET_H8300S"
670 [(set_attr "length" "2,2,4,2")
671 (set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])
674 [(set (match_operand:HI 0 "register_operand" "")
675 (plus:HI (match_dup 0)
676 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
679 "split_adds_subs (HImode, operands); DONE;")
681 (define_expand "addsi3"
682 [(set (match_operand:SI 0 "register_operand" "")
683 (plus:SI (match_operand:SI 1 "register_operand" "")
684 (match_operand:SI 2 "nonmemory_operand" "")))]
688 (define_insn "addsi_h8300"
689 [(set (match_operand:SI 0 "register_operand" "=r,r,&r")
690 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
691 (match_operand:SI 2 "nonmemory_operand" "n,r,r")))]
694 add %w2,%w0\;addx %x2,%x0\;addx %y2,%y0\;addx %z2,%z0
695 add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0
696 mov.w %f1,%f0\;mov.w %e1,%e0\;add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0"
697 [(set_attr "length" "8,6,10")
698 (set_attr "cc" "clobber")])
700 (define_insn "addsi_h8300h"
701 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
702 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0")
703 (match_operand:SI 2 "nonmemory_operand" "L,N,i,r")))]
704 "TARGET_H8300H || TARGET_H8300S"
710 [(set_attr "length" "2,2,6,2")
711 (set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])
714 [(set (match_operand:SI 0 "register_operand" "")
715 (plus:SI (match_dup 0)
716 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
717 "TARGET_H8300H || TARGET_H8300S"
719 "split_adds_subs (SImode, operands); DONE;")
721 ;; ----------------------------------------------------------------------
722 ;; SUBTRACT INSTRUCTIONS
723 ;; ----------------------------------------------------------------------
725 (define_insn "subqi3"
726 [(set (match_operand:QI 0 "register_operand" "=r,r")
727 (minus:QI (match_operand:QI 1 "register_operand" "0,0")
728 (match_operand:QI 2 "nonmemory_operand" "r,n")))]
733 [(set_attr "length" "2")
734 (set_attr "cc" "set_zn")])
736 (define_expand "subhi3"
737 [(set (match_operand:HI 0 "register_operand" "")
738 (minus:HI (match_operand:HI 1 "general_operand" "")
739 (match_operand:HI 2 "nonmemory_operand" "")))]
744 [(set (match_operand:HI 0 "register_operand" "=r,&r")
745 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
746 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
750 add.b %E2,%s0\;addx %F2,%t0"
751 [(set_attr "length" "2,4")
752 (set_attr "cc" "set_zn,clobber")])
755 [(set (match_operand:HI 0 "register_operand" "=r,&r")
756 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
757 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
758 "TARGET_H8300H || TARGET_H8300S"
762 [(set_attr "length" "2,4")
763 (set_attr "cc" "set_zn,set_zn")])
765 (define_expand "subsi3"
766 [(set (match_operand:SI 0 "register_operand" "")
767 (minus:SI (match_operand:SI 1 "register_operand" "")
768 (match_operand:SI 2 "nonmemory_operand" "")))]
772 (define_insn "subsi3_h8300"
773 [(set (match_operand:SI 0 "register_operand" "=r")
774 (minus:SI (match_operand:SI 1 "register_operand" "0")
775 (match_operand:SI 2 "register_operand" "r")))]
777 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
778 [(set_attr "length" "6")
779 (set_attr "cc" "clobber")])
781 (define_insn "subsi3_h8300h"
782 [(set (match_operand:SI 0 "register_operand" "=r,r")
783 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
784 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
785 "TARGET_H8300H || TARGET_H8300S"
789 [(set_attr "length" "2,6")
790 (set_attr "cc" "set_zn,set_zn")])
792 ;; ----------------------------------------------------------------------
793 ;; MULTIPLY INSTRUCTIONS
794 ;; ----------------------------------------------------------------------
796 ;; Note that the H8/300 can only handle umulqihi3.
798 (define_insn "mulqihi3"
799 [(set (match_operand:HI 0 "register_operand" "=r")
800 (mult:HI (sign_extend:HI (match_operand:QI 1 "general_operand" "%0"))
801 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
802 "TARGET_H8300H || TARGET_H8300S"
804 [(set_attr "length" "4")
805 (set_attr "cc" "set_zn")])
807 (define_insn "mulhisi3"
808 [(set (match_operand:SI 0 "register_operand" "=r")
809 (mult:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "%0"))
810 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
811 "TARGET_H8300H || TARGET_H8300S"
813 [(set_attr "length" "4")
814 (set_attr "cc" "set_zn")])
816 (define_insn "umulqihi3"
817 [(set (match_operand:HI 0 "register_operand" "=r")
818 (mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%0"))
819 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
822 [(set_attr "length" "2")
823 (set_attr "cc" "none_0hit")])
825 (define_insn "umulhisi3"
826 [(set (match_operand:SI 0 "register_operand" "=r")
827 (mult:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "%0"))
828 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
829 "TARGET_H8300H || TARGET_H8300S"
831 [(set_attr "length" "2")
832 (set_attr "cc" "none_0hit")])
834 ;; This is a "bridge" instruction. Combine can't cram enough insns
835 ;; together to crate a MAC instruction directly, but it can create
836 ;; this instruction, which then allows combine to create the real
839 ;; Unfortunately, if combine doesn't create a MAC instruction, this
840 ;; insn must generate reasonably correct code. Egad.
842 [(set (match_operand:SI 0 "register_operand" "=a")
845 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
847 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
849 "clrmac\;mac @%2+,@%1+"
850 [(set_attr "length" "6")
851 (set_attr "cc" "none_0hit")])
854 [(set (match_operand:SI 0 "register_operand" "=a")
856 (sign_extend:SI (mem:HI
857 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
858 (sign_extend:SI (mem:HI
859 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
860 (match_operand:SI 3 "register_operand" "0")))]
863 [(set_attr "length" "4")
864 (set_attr "cc" "none_0hit")])
866 ;; ----------------------------------------------------------------------
867 ;; DIVIDE INSTRUCTIONS
868 ;; ----------------------------------------------------------------------
870 (define_insn "udivqi3"
871 [(set (match_operand:QI 0 "register_operand" "=r")
874 (match_operand:HI 1 "general_operand" "0")
875 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
878 [(set_attr "length" "2")
879 (set_attr "cc" "clobber")])
881 ;; ??? Will divxu always work here?
883 (define_insn "divqi3"
884 [(set (match_operand:QI 0 "register_operand" "=r")
887 (match_operand:HI 1 "general_operand" "0")
888 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
891 [(set_attr "length" "2")
892 (set_attr "cc" "clobber")])
894 (define_insn "udivhi3"
895 [(set (match_operand:HI 0 "register_operand" "=r")
898 (match_operand:SI 1 "general_operand" "0")
899 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
900 "TARGET_H8300H || TARGET_H8300S"
902 [(set_attr "length" "2")
903 (set_attr "cc" "clobber")])
905 (define_insn "divhi3"
906 [(set (match_operand:HI 0 "register_operand" "=r")
909 (match_operand:SI 1 "general_operand" "0")
910 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
911 "TARGET_H8300H || TARGET_H8300S"
913 [(set_attr "length" "4")
914 (set_attr "cc" "clobber")])
916 ;; ----------------------------------------------------------------------
918 ;; ----------------------------------------------------------------------
920 (define_insn "umodqi3"
921 [(set (match_operand:QI 0 "register_operand" "=r")
924 (match_operand:HI 1 "general_operand" "0")
925 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
927 "divxu %X2,%T0\;mov %t0,%s0"
928 [(set_attr "length" "4")
929 (set_attr "cc" "clobber")])
931 (define_insn "modqi3"
932 [(set (match_operand:QI 0 "register_operand" "=r")
935 (match_operand:HI 1 "general_operand" "0")
936 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
937 "TARGET_H8300H || TARGET_H8300S"
938 "divxs.b %X2,%T0\;mov %t0,%s0"
939 [(set_attr "length" "6")
940 (set_attr "cc" "clobber")])
942 (define_insn "umodhi3"
943 [(set (match_operand:HI 0 "register_operand" "=r")
946 (match_operand:SI 1 "general_operand" "0")
947 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
948 "TARGET_H8300H || TARGET_H8300S"
949 "divxu.w %T2,%S0\;mov %e0,%f0"
950 [(set_attr "length" "4")
951 (set_attr "cc" "clobber")])
953 (define_insn "modhi3"
954 [(set (match_operand:HI 0 "register_operand" "=r")
957 (match_operand:SI 1 "general_operand" "0")
958 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
959 "TARGET_H8300H || TARGET_H8300S"
960 "divxs.w %T2,%S0\;mov %e0,%f0"
961 [(set_attr "length" "6")
962 (set_attr "cc" "clobber")])
964 ;; ----------------------------------------------------------------------
966 ;; ----------------------------------------------------------------------
969 [(set (match_operand:QI 0 "bit_operand" "=r,U")
970 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
971 (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
972 "register_operand (operands[0], QImode) || o_operand (operands[2], QImode)"
976 [(set_attr "length" "2,4")
977 (set_attr "adjust_length" "no")
978 (set_attr "cc" "set_znv,none_0hit")])
980 (define_expand "andqi3"
981 [(set (match_operand:QI 0 "bit_operand" "")
982 (and:QI (match_operand:QI 1 "bit_operand" "")
983 (match_operand:QI 2 "nonmemory_operand" "")))]
987 if (fix_bit_operand (operands, 'O', AND))
991 (define_insn "andhi3"
992 [(set (match_operand:HI 0 "register_operand" "=r")
993 (and:HI (match_operand:HI 1 "register_operand" "%0")
994 (match_operand:HI 2 "nonmemory_operand" "rn")))]
998 if (GET_CODE (operands[2]) == CONST_INT)
1000 int i = INTVAL (operands[2]);
1002 if ((i & 0x00ff) != 0x00ff)
1003 output_asm_insn (\"and %s2,%s0\", operands);
1004 if ((i & 0xff00) != 0xff00)
1005 output_asm_insn (\"and %t2,%t0\", operands);
1008 if (TARGET_H8300H || TARGET_H8300S)
1009 return \"and.w %T2,%T0\";
1010 return \"and %s2,%s0\;and %t2,%t0;\";
1012 [(set_attr "length" "4")
1013 (set_attr "cc" "clobber")])
1015 (define_insn "andsi3"
1016 [(set (match_operand:SI 0 "register_operand" "=r")
1017 (and:SI (match_operand:SI 1 "register_operand" "%0")
1018 (match_operand:SI 2 "nonmemory_operand" "rn")))]
1022 if (GET_CODE (operands[2]) == CONST_INT)
1024 int i = INTVAL (operands[2]);
1025 int upper_cleared, lower_cleared;
1027 /* The h8300h can't do byte-wise operations on the
1028 upper 16bits of 32bit registers. However, if
1029 those bits aren't going to change, or they're
1030 going to be zero'd out, then we can work on the
1032 if ((TARGET_H8300H || TARGET_H8300S)
1033 && ((i & 0xffff0000) != 0xffff0000
1034 || (i & 0xffff0000) == 0x00000000))
1035 return \"and.l %S2,%S0\";
1038 if ((i & 0x0000ffff) == 0x00000000)
1040 output_asm_insn (\"sub.w %f0,%f0\", operands);
1045 if ((i & 0xffff0000) == 0x00000000)
1047 output_asm_insn (\"sub.w %e0,%e0\", operands);
1051 if ((i & 0x000000ff) != 0x000000ff && !lower_cleared)
1052 output_asm_insn (\"and %w2,%w0\", operands);
1053 if ((i & 0x0000ff00) != 0x0000ff00 && !lower_cleared)
1054 output_asm_insn (\"and %x2,%x0\", operands);
1055 if ((i & 0x00ff0000) != 0x00ff0000 && !upper_cleared)
1056 output_asm_insn (\"and %y2,%y0\", operands);
1057 if ((i & 0xff000000) != 0xff000000 && !upper_cleared)
1058 output_asm_insn (\"and %z2,%z0\", operands);
1061 if (TARGET_H8300H || TARGET_H8300S)
1062 return \"and.l %S2,%S0\";
1063 return \"and %w2,%w0\;and %x2,%x0\;and %y2,%y0\;and %z2,%z0\";
1065 [(set_attr "length" "8")
1066 (set_attr "cc" "clobber")])
1069 ;; ----------------------------------------------------------------------
1071 ;; ----------------------------------------------------------------------
1074 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1075 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1076 (match_operand:QI 2 "nonmemory_operand" "rn,P")))]
1077 "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)"
1081 [(set_attr "length" "2,4")
1082 (set_attr "adjust_length" "no")
1083 (set_attr "cc" "set_znv,none_0hit")])
1085 (define_expand "iorqi3"
1086 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1087 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1088 (match_operand:QI 2 "nonmemory_operand" "rn,P")))]
1092 if (fix_bit_operand (operands, 'P', IOR))
1096 (define_insn "iorhi3"
1097 [(set (match_operand:HI 0 "general_operand" "=r,r")
1098 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
1099 (match_operand:HI 2 "general_operand" "J,rn")))]
1103 if (GET_CODE (operands[2]) == CONST_INT)
1105 int i = INTVAL (operands[2]);
1107 if ((i & 0x00ff) != 0)
1108 output_asm_insn (\"or %s2,%s0\", operands);
1109 if ((i & 0xff00) != 0)
1110 output_asm_insn (\"or %t2,%t0\", operands);
1113 if (TARGET_H8300H || TARGET_H8300S)
1114 return \"or.w %T2,%T0\";
1115 return \"or %s2,%s0\;or %t2,%t0; %2 or2\";
1117 [(set_attr "length" "2,4")
1118 (set_attr "cc" "clobber,clobber")])
1120 (define_insn "iorsi3"
1121 [(set (match_operand:SI 0 "register_operand" "=r,r")
1122 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
1123 (match_operand:SI 2 "nonmemory_operand" "J,rn")))]
1127 if (GET_CODE (operands[2]) == CONST_INT)
1129 int i = INTVAL (operands[2]);
1131 /* The h8300h can't do byte-wise operations on the
1132 upper 16bits of 32bit registers. However, if
1133 those bits aren't going to change, then we can
1134 work on the low-order bits. */
1135 if ((TARGET_H8300H || TARGET_H8300S)
1136 && (i & 0xffff0000) != 0x00000000)
1137 return \"or.l %S2,%S0\";
1139 if ((i & 0x000000ff) != 0)
1140 output_asm_insn (\"or %w2,%w0\", operands);
1141 if ((i & 0x0000ff00) != 0)
1142 output_asm_insn (\"or %x2,%x0\", operands);
1143 if ((i & 0x00ff0000) != 0)
1144 output_asm_insn (\"or %y2,%y0\", operands);
1145 if ((i & 0xff000000) != 0)
1146 output_asm_insn (\"or %z2,%z0\", operands);
1149 if (TARGET_H8300H || TARGET_H8300S)
1150 return \"or.l %S2,%S0\";
1151 return \"or %w2,%w0\;or %x2,%x0\;or %y2,%y0\;or %z2,%z0\";
1153 [(set_attr "length" "2,8")
1154 (set_attr "cc" "clobber,clobber")])
1156 ;; ----------------------------------------------------------------------
1158 ;; ----------------------------------------------------------------------
1161 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1162 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1163 (match_operand:QI 2 "nonmemory_operand" "rn,P")))]
1164 "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)"
1168 [(set_attr "length" "2,4")
1169 (set_attr "adjust_length" "no")
1170 (set_attr "cc" "set_znv,none_0hit")])
1172 (define_expand "xorqi3"
1173 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1174 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1175 (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
1179 if (fix_bit_operand (operands, 'O', XOR))
1183 (define_insn "xorhi3"
1184 [(set (match_operand:HI 0 "register_operand" "=r,r")
1185 (xor:HI (match_operand:HI 1 "general_operand" "%0,0")
1186 (match_operand:HI 2 "nonmemory_operand" "J,rn")))]
1190 if (GET_CODE (operands[2]) == CONST_INT)
1192 int i = INTVAL (operands[2]);
1194 if ((i & 0x00ff) != 0)
1195 output_asm_insn (\"xor %s2,%s0\", operands);
1196 if ((i & 0xff00) != 0)
1197 output_asm_insn (\"xor %t2,%t0\", operands);
1200 if (TARGET_H8300H || TARGET_H8300S)
1201 return \"xor.w %T2,%T0\";
1202 return \"xor %s2,%s0\;xor %t2,%t0\";
1204 [(set_attr "length" "2,4")
1205 (set_attr "cc" "clobber,clobber")])
1207 (define_insn "xorsi3"
1208 [(set (match_operand:SI 0 "register_operand" "=r,r")
1209 (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
1210 (match_operand:SI 2 "nonmemory_operand" "J,rn")))]
1214 if (GET_CODE (operands[2]) == CONST_INT)
1216 int i = INTVAL (operands[2]);
1218 /* The h8300h can't do byte-wise operations on the
1219 upper 16bits of 32bit registers. However, if
1220 those bits aren't going to change, then we can
1221 work on the low-order bits. */
1222 if ((TARGET_H8300H || TARGET_H8300S)
1223 && (i & 0xffff0000) != 0x00000000)
1224 return \"xor.l %S2,%S0\";
1226 if ((i & 0x000000ff) != 0)
1227 output_asm_insn (\"xor %w2,%w0\", operands);
1228 if ((i & 0x0000ff00) != 0)
1229 output_asm_insn (\"xor %x2,%x0\", operands);
1230 if ((i & 0x00ff0000) != 0)
1231 output_asm_insn (\"xor %y2,%y0\", operands);
1232 if ((i & 0xff000000) != 0)
1233 output_asm_insn (\"xor %z2,%z0\", operands);
1236 if (TARGET_H8300H || TARGET_H8300S)
1237 return \"xor.l %S2,%S0\";
1238 return \"xor %w2,%w0\;xor %x2,%x0\;xor %y2,%y0\;xor %z2,%z0\";
1240 [(set_attr "length" "2,8")
1241 (set_attr "cc" "clobber,clobber")])
1243 ;; ----------------------------------------------------------------------
1244 ;; NEGATION INSTRUCTIONS
1245 ;; ----------------------------------------------------------------------
1247 (define_insn "negqi2"
1248 [(set (match_operand:QI 0 "register_operand" "=r")
1249 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
1252 [(set_attr "length" "2")
1253 (set_attr "cc" "set_zn")])
1255 (define_expand "neghi2"
1256 [(set (match_operand:HI 0 "register_operand" "=r")
1257 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
1263 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1268 (define_expand "neghi2_h8300"
1270 (not:HI (match_operand:HI 1 "register_operand" "r")))
1271 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1272 (set (match_operand:HI 0 "register_operand" "=r")
1275 "{ operands[2] = gen_reg_rtx (HImode); }")
1277 (define_insn "neghi2_h8300h"
1278 [(set (match_operand:HI 0 "register_operand" "=r")
1279 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
1280 "TARGET_H8300H || TARGET_H8300S"
1282 [(set_attr "length" "2")
1283 (set_attr "cc" "set_zn")])
1285 (define_expand "negsi2"
1286 [(set (match_operand:SI 0 "register_operand" "=r")
1287 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
1293 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1298 (define_expand "negsi2_h8300"
1300 (not:SI (match_operand:SI 1 "register_operand" "r")))
1301 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1302 (set (match_operand:SI 0 "register_operand" "=r")
1305 "{ operands[2] = gen_reg_rtx(SImode); }")
1307 (define_insn "negsi2_h8300h"
1308 [(set (match_operand:SI 0 "register_operand" "=r")
1309 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
1310 "TARGET_H8300H || TARGET_H8300S"
1312 [(set_attr "length" "2")
1313 (set_attr "cc" "set_zn")])
1315 ;; ----------------------------------------------------------------------
1317 ;; ----------------------------------------------------------------------
1319 (define_insn "one_cmplqi2"
1320 [(set (match_operand:QI 0 "register_operand" "=r")
1321 (not:QI (match_operand:QI 1 "general_operand" "0")))]
1324 [(set_attr "length" "2")
1325 (set_attr "cc" "set_znv")])
1327 (define_insn "one_cmplhi2"
1328 [(set (match_operand:HI 0 "register_operand" "=r")
1329 (not:HI (match_operand:HI 1 "general_operand" "0")))]
1334 return \"not %s0\;not %t0\";
1338 [(set_attr "cc" "clobber")
1339 (set (attr "length")
1340 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
1345 (define_insn "one_cmplsi2"
1346 [(set (match_operand:SI 0 "register_operand" "=r")
1347 (not:SI (match_operand:SI 1 "general_operand" "0")))]
1352 return \"not %w0\;not %x0\;not %y0\;not %z0\";
1356 [(set_attr "cc" "clobber")
1357 (set (attr "length")
1358 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
1363 ;; ----------------------------------------------------------------------
1364 ;; JUMP INSTRUCTIONS
1365 ;; ----------------------------------------------------------------------
1367 ;; Conditional jump instructions
1369 (define_expand "ble"
1371 (if_then_else (le (cc0)
1373 (label_ref (match_operand 0 "" ""))
1378 (define_expand "bleu"
1380 (if_then_else (leu (cc0)
1382 (label_ref (match_operand 0 "" ""))
1387 (define_expand "bge"
1389 (if_then_else (ge (cc0)
1391 (label_ref (match_operand 0 "" ""))
1396 (define_expand "bgeu"
1398 (if_then_else (geu (cc0)
1400 (label_ref (match_operand 0 "" ""))
1405 (define_expand "blt"
1407 (if_then_else (lt (cc0)
1409 (label_ref (match_operand 0 "" ""))
1414 (define_expand "bltu"
1416 (if_then_else (ltu (cc0)
1418 (label_ref (match_operand 0 "" ""))
1423 (define_expand "bgt"
1425 (if_then_else (gt (cc0)
1427 (label_ref (match_operand 0 "" ""))
1432 (define_expand "bgtu"
1434 (if_then_else (gtu (cc0)
1436 (label_ref (match_operand 0 "" ""))
1441 (define_expand "beq"
1443 (if_then_else (eq (cc0)
1445 (label_ref (match_operand 0 "" ""))
1450 (define_expand "bne"
1452 (if_then_else (ne (cc0)
1454 (label_ref (match_operand 0 "" ""))
1459 (define_insn "branch_true"
1461 (if_then_else (match_operator 1 "comparison_operator"
1462 [(cc0) (const_int 0)])
1463 (label_ref (match_operand 0 "" ""))
1468 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1469 && (GET_CODE (operands[1]) == GT
1470 || GET_CODE (operands[1]) == GE
1471 || GET_CODE (operands[1]) == LE
1472 || GET_CODE (operands[1]) == LT))
1474 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1478 if (get_attr_length (insn) == 2)
1479 return \"b%j1 %l0\";
1480 else if (get_attr_length (insn) == 4)
1481 return \"b%j1 %l0:16\";
1483 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1485 [(set_attr "type" "branch")
1486 (set_attr "cc" "none")])
1488 (define_insn "branch_false"
1490 (if_then_else (match_operator 1 "comparison_operator"
1491 [(cc0) (const_int 0)])
1493 (label_ref (match_operand 0 "" ""))))]
1497 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1498 && (GET_CODE (operands[1]) == GT
1499 || GET_CODE (operands[1]) == GE
1500 || GET_CODE (operands[1]) == LE
1501 || GET_CODE (operands[1]) == LT))
1503 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1507 if (get_attr_length (insn) == 2)
1508 return \"b%k1 %l0\";
1509 else if (get_attr_length (insn) == 4)
1510 return \"b%k1 %l0:16\";
1512 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1514 [(set_attr "type" "branch")
1515 (set_attr "cc" "none")])
1517 ;; Unconditional and other jump instructions.
1521 (label_ref (match_operand 0 "" "")))]
1525 if (get_attr_length (insn) == 2)
1527 else if (get_attr_length (insn) == 4)
1528 return \"bra %l0:16\";
1530 return \"jmp @%l0\";
1532 [(set_attr "type" "branch")
1533 (set_attr "cc" "none")])
1535 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1537 (define_expand "tablejump"
1538 [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
1539 (use (label_ref (match_operand 1 "" "")))])]
1543 (define_insn "tablejump_h8300"
1544 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1545 (use (label_ref (match_operand 1 "" "")))]
1548 [(set_attr "cc" "none")
1549 (set_attr "length" "2")])
1551 (define_insn "tablejump_h8300h"
1552 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1553 (use (label_ref (match_operand 1 "" "")))]
1554 "TARGET_H8300H || TARGET_H8300S"
1556 [(set_attr "cc" "none")
1557 (set_attr "length" "2")])
1559 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1561 (define_expand "indirect_jump"
1562 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1566 (define_insn "indirect_jump_h8300"
1567 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1570 [(set_attr "cc" "none")
1571 (set_attr "length" "2")])
1573 (define_insn "indirect_jump_h8300h"
1574 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1575 "TARGET_H8300H || TARGET_H8300S"
1577 [(set_attr "cc" "none")
1578 (set_attr "length" "2")])
1580 ;; Call subroutine with no return value.
1582 ;; ??? Even though we use HImode here, this works for the 300h.
1585 [(call (match_operand:QI 0 "call_insn_operand" "or")
1586 (match_operand:HI 1 "general_operand" "g"))]
1590 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1591 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1592 return \"jsr\\t\@%0:8\";
1594 return \"jsr\\t%0\";
1596 [(set_attr "cc" "clobber")
1597 (set (attr "length")
1598 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1602 ;; Call subroutine, returning value in operand 0
1603 ;; (which must be a hard register).
1605 ;; ??? Even though we use HImode here, this works on the 300h.
1607 (define_insn "call_value"
1608 [(set (match_operand 0 "" "=r")
1609 (call (match_operand:QI 1 "call_insn_operand" "or")
1610 (match_operand:HI 2 "general_operand" "g")))]
1614 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1615 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1616 return \"jsr\\t\@%1:8\";
1618 return \"jsr\\t%1\";
1620 [(set_attr "cc" "clobber")
1621 (set (attr "length")
1622 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1630 [(set_attr "cc" "none")
1631 (set_attr "length" "2")])
1633 ;; ----------------------------------------------------------------------
1634 ;; EXTEND INSTRUCTIONS
1635 ;; ----------------------------------------------------------------------
1637 (define_insn "zero_extendqihi2"
1638 [(set (match_operand:HI 0 "register_operand" "=r,r")
1639 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1643 mov.b %R1,%s0\;mov.b #0,%t0"
1644 [(set_attr "length" "2,10")
1645 (set_attr "cc" "clobber,clobber")])
1647 ;; The compiler can synthesize a 300H variant of this which is
1648 ;; just as efficient as one that we'd create
1649 (define_insn "zero_extendqisi2"
1650 [(set (match_operand:SI 0 "register_operand" "=r,r")
1651 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1654 mov.b #0,%x0\;sub.w %e0,%e0
1655 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
1656 [(set_attr "length" "4,6")
1657 (set_attr "cc" "clobber,clobber")])
1659 (define_expand "zero_extendhisi2"
1660 [(set (match_operand:SI 0 "register_operand" "")
1661 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
1665 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
1667 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1668 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
1672 mov.w %f1,%f0\;sub.w %e0,%e0
1673 mov.w %e1,%f0\;sub.w %e0,%e0"
1674 [(set_attr "length" "2,4,4")
1675 (set_attr "cc" "clobber,clobber,clobber")])
1678 [(set (match_operand:SI 0 "register_operand" "=r")
1679 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1680 "TARGET_H8300H || TARGET_H8300S"
1682 [(set_attr "length" "2")
1683 (set_attr "cc" "set_znv")])
1685 (define_expand "extendqihi2"
1686 [(set (match_operand:HI 0 "register_operand" "")
1687 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
1692 [(set (match_operand:HI 0 "register_operand" "=r,r")
1693 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1696 bld #7,%s0\;subx %t0,%t0
1697 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
1698 [(set_attr "length" "4,6")
1699 (set_attr "cc" "clobber,clobber")])
1702 [(set (match_operand:HI 0 "register_operand" "=r")
1703 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
1704 "TARGET_H8300H || TARGET_H8300S"
1706 [(set_attr "length" "2")
1707 (set_attr "cc" "set_znv")])
1709 ;; The compiler can synthesize a 300H variant of this which is
1710 ;; just as efficient as one that we'd create
1711 (define_insn "extendqisi2"
1712 [(set (match_operand:SI 0 "register_operand" "=r,r")
1713 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1716 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
1717 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
1718 [(set_attr "length" "8,10")
1719 (set_attr "cc" "clobber,clobber")])
1721 (define_expand "extendhisi2"
1722 [(set (match_operand:SI 0 "register_operand" "")
1723 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
1728 [(set (match_operand:SI 0 "register_operand" "=r,r")
1729 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
1732 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
1733 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
1734 [(set_attr "length" "6,8")
1735 (set_attr "cc" "clobber,clobber")])
1738 [(set (match_operand:SI 0 "register_operand" "=r")
1739 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1740 "TARGET_H8300H || TARGET_H8300S"
1742 [(set_attr "length" "2")
1743 (set_attr "cc" "set_znv")])
1745 ;; ----------------------------------------------------------------------
1747 ;; ----------------------------------------------------------------------
1749 ;; We make some attempt to provide real efficient shifting. One example is
1750 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
1751 ;; reg and moving 0 into the former reg.
1753 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
1754 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
1755 ;; give the optimizer more cracks at the code. However, we wish to do things
1756 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
1757 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
1758 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
1759 ;; to detect cases it can optimize.
1761 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
1762 ;; easier "do it at insn emit time" route.
1766 (define_expand "ashlqi3"
1767 [(set (match_operand:QI 0 "register_operand" "")
1768 (ashift:QI (match_operand:QI 1 "register_operand" "")
1769 (match_operand:QI 2 "nonmemory_operand" "")))]
1771 "if (expand_a_shift (QImode, ASHIFT, operands)) DONE;else FAIL;")
1773 (define_expand "ashrqi3"
1774 [(set (match_operand:QI 0 "register_operand" "")
1775 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
1776 (match_operand:QI 2 "nonmemory_operand" "")))]
1778 "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE;else FAIL;")
1780 (define_expand "lshrqi3"
1781 [(set (match_operand:QI 0 "register_operand" "")
1782 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
1783 (match_operand:QI 2 "nonmemory_operand" "")))]
1785 "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE;else FAIL;")
1788 [(set (match_operand:QI 0 "register_operand" "=r,r")
1789 (match_operator:QI 3 "nshift_operator"
1790 [ (match_operand:QI 1 "register_operand" "0,0")
1791 (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
1792 (clobber (match_scratch:QI 4 "=X,&r"))]
1794 "* return emit_a_shift (insn, operands);"
1795 [(set_attr "length" "20")
1796 (set_attr "cc" "clobber")])
1800 (define_expand "ashlhi3"
1801 [(set (match_operand:HI 0 "register_operand" "")
1802 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
1803 (match_operand:QI 2 "nonmemory_operand" "")))]
1805 "if (expand_a_shift (HImode, ASHIFT, operands)) DONE;else FAIL;")
1807 (define_expand "lshrhi3"
1808 [(set (match_operand:HI 0 "register_operand" "")
1809 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
1810 (match_operand:QI 2 "nonmemory_operand" "")))]
1812 "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE;else FAIL;")
1814 (define_expand "ashrhi3"
1815 [(set (match_operand:HI 0 "register_operand" "")
1816 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
1817 (match_operand:QI 2 "nonmemory_operand" "")))]
1819 "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE;else FAIL;")
1822 [(set (match_operand:HI 0 "register_operand" "=r,r")
1823 (match_operator:HI 3 "nshift_operator"
1824 [ (match_operand:HI 1 "register_operand" "0,0")
1825 (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
1826 (clobber (match_scratch:QI 4 "=X,&r"))]
1828 "* return emit_a_shift (insn, operands);"
1829 [(set_attr "length" "20")
1830 (set_attr "cc" "clobber")])
1834 (define_expand "ashlsi3"
1835 [(set (match_operand:SI 0 "register_operand" "")
1837 (match_operand:SI 1 "general_operand" "")
1838 (match_operand:QI 2 "nonmemory_operand" "")))]
1840 "if (expand_a_shift (SImode, ASHIFT, operands)) DONE;else FAIL;")
1842 (define_expand "lshrsi3"
1843 [(set (match_operand:SI 0 "register_operand" "")
1845 (match_operand:SI 1 "general_operand" "")
1846 (match_operand:QI 2 "nonmemory_operand" "")))]
1848 "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE;else FAIL;")
1850 (define_expand "ashrsi3"
1851 [(set (match_operand:SI 0 "register_operand" "")
1853 (match_operand:SI 1 "general_operand" "")
1854 (match_operand:QI 2 "nonmemory_operand" "")))]
1856 "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE;else FAIL;")
1859 [(set (match_operand:SI 0 "register_operand" "=r,r")
1860 (match_operator:SI 3 "nshift_operator"
1861 [ (match_operand:SI 1 "register_operand" "0,0")
1862 (match_operand:QI 2 "nonmemory_operand" "K,rn")]))
1863 (clobber (match_scratch:QI 4 "=X,&r"))]
1865 "* return emit_a_shift (insn, operands);"
1866 [(set_attr "length" "20")
1867 (set_attr "cc" "clobber")])
1869 ;; ----------------------------------------------------------------------
1871 ;; ----------------------------------------------------------------------
1873 (define_expand "rotlqi3"
1874 [(set (match_operand:QI 0 "register_operand" "")
1875 (rotate:QI (match_operand:QI 1 "register_operand" "")
1876 (match_operand:QI 2 "nonmemory_operand" "")))]
1878 "if (expand_a_rotate (ROTATE, operands)) DONE;else FAIL;")
1880 (define_insn "*rotlqi3_1"
1881 [(set (match_operand:QI 0 "register_operand" "=r")
1882 (rotate:QI (match_operand:QI 1 "register_operand" "0")
1883 (match_operand:QI 2 "immediate_operand" "")))]
1885 "* return emit_a_rotate (ROTATE, operands);"
1886 [(set_attr "length" "20")
1887 (set_attr "cc" "clobber")])
1889 (define_expand "rotlhi3"
1890 [(set (match_operand:HI 0 "register_operand" "")
1891 (rotate:HI (match_operand:HI 1 "register_operand" "")
1892 (match_operand:QI 2 "nonmemory_operand" "")))]
1894 "if (expand_a_rotate (ROTATE, operands)) DONE;else FAIL;")
1896 (define_insn "*rotlhi3_1"
1897 [(set (match_operand:HI 0 "register_operand" "=r")
1898 (rotate:HI (match_operand:HI 1 "register_operand" "0")
1899 (match_operand:QI 2 "immediate_operand" "")))]
1901 "* return emit_a_rotate (ROTATE, operands);"
1902 [(set_attr "length" "20")
1903 (set_attr "cc" "clobber")])
1905 (define_expand "rotlsi3"
1906 [(set (match_operand:SI 0 "register_operand" "")
1907 (rotate:SI (match_operand:SI 1 "register_operand" "")
1908 (match_operand:QI 2 "nonmemory_operand" "")))]
1909 "TARGET_H8300H || TARGET_H8300S"
1910 "if (expand_a_rotate (ROTATE, operands)) DONE;else FAIL;")
1912 (define_insn "*rotlsi3_1"
1913 [(set (match_operand:SI 0 "register_operand" "=r")
1914 (rotate:SI (match_operand:SI 1 "register_operand" "0")
1915 (match_operand:QI 2 "immediate_operand" "")))]
1916 "TARGET_H8300H || TARGET_H8300S"
1917 "* return emit_a_rotate (ROTATE, operands);"
1918 [(set_attr "length" "20")
1919 (set_attr "cc" "clobber")])
1921 ;; -----------------------------------------------------------------
1923 ;; -----------------------------------------------------------------
1924 ;; The H8/300 has given 1/8th of its opcode space to bitfield
1925 ;; instructions so let's use them as well as we can.
1927 ;; You'll never believe all these patterns perform one basic action --
1928 ;; load a bit from the source, optionally invert the bit, then store it
1929 ;; in the destination (which is known to be zero).
1931 ;; Combine obviously need some work to better identify this situation and
1932 ;; canonicalize the form better.
1935 ;; Normal loads with a 16bit destination.
1937 ;; Yes, both cases are needed.
1940 [(set (match_operand:HI 0 "register_operand" "=&r")
1941 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
1943 (match_operand:HI 2 "immediate_operand" "n")))]
1945 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
1946 [(set_attr "cc" "clobber")
1947 (set_attr "length" "6")])
1950 [(set (match_operand:HI 0 "register_operand" "=&r")
1951 (subreg:HI (zero_extract:SI
1952 (match_operand:HI 1 "register_operand" "r")
1954 (match_operand:HI 2 "immediate_operand" "n")) 2))]
1956 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
1957 [(set_attr "cc" "clobber")
1958 (set_attr "length" "6")])
1961 ;; Inverted loads with a 16bit destination.
1963 ;; Yes, all four cases are needed.
1967 [(set (match_operand:HI 0 "register_operand" "=&r")
1968 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
1969 (match_operand:HI 3 "p_operand" "P"))
1971 (match_operand:HI 2 "const_int_operand" "n")))]
1972 "(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
1973 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
1974 [(set_attr "cc" "clobber")
1975 (set_attr "length" "8")])
1978 [(set (match_operand:HI 0 "register_operand" "=&r")
1981 (match_operand:HI 1 "bit_operand" "Ur")
1982 (match_operand:HI 2 "const_int_operand" "n")))
1985 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
1986 [(set_attr "cc" "clobber")
1987 (set_attr "length" "8")])
1990 [(set (match_operand:HI 0 "register_operand" "=&r")
1994 (match_operand:SI 1 "register_operand" "Ur")
1995 (match_operand:SI 2 "const_int_operand" "n")) 2))
1997 "INTVAL (operands[2]) < 16"
1998 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
1999 [(set_attr "cc" "clobber")
2000 (set_attr "length" "8")])
2003 [(set (match_operand:HI 0 "register_operand" "=&r")
2007 (match_operand:SI 1 "bit_operand" "Ur")
2008 (match_operand:SI 2 "const_int_operand" "n")) 0))
2010 "(TARGET_H8300H || TARGET_H8300S)
2011 && INTVAL (operands[2]) < 16"
2012 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2013 [(set_attr "cc" "clobber")
2014 (set_attr "length" "8")])
2017 ;; Normal loads with a 32bit destination.
2019 ;; Yes, all three cases are needed.
2022 [(set (match_operand:SI 0 "register_operand" "=&r")
2023 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2025 (match_operand:HI 2 "const_int_operand" "n")))]
2027 "* return output_simode_bld (0, 0, operands);"
2028 [(set_attr "cc" "clobber")
2029 (set (attr "length")
2030 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2036 [(set (match_operand:SI 0 "register_operand" "=&r")
2037 (and:SI (zero_extend:SI
2039 (match_operand:QI 1 "bit_operand" "Ur")
2040 (match_operand:QI 2 "const_int_operand" "n")))
2043 "* return output_simode_bld (0, 0, operands);"
2044 [(set_attr "cc" "clobber")
2045 (set (attr "length")
2046 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2052 [(set (match_operand:SI 0 "register_operand" "=&r")
2053 (and:SI (zero_extend:SI
2055 (match_operand:HI 1 "bit_operand" "Ur")
2056 (match_operand:HI 2 "const_int_operand" "n")))
2059 "* return output_simode_bld (0, 0, operands);"
2060 [(set_attr "cc" "clobber")
2061 (set (attr "length")
2062 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2068 ;; Inverted loads with a 32bit destination.
2070 ;; Yes, all seven cases are needed.
2073 [(set (match_operand:SI 0 "register_operand" "=&r")
2075 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))
2076 (match_operand:SI 2 "p_operand" "P")))]
2078 "* return output_simode_bld (1, 1, operands);"
2079 [(set_attr "cc" "clobber")
2080 (set (attr "length")
2081 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2086 [(set (match_operand:SI 0 "register_operand" "=&r")
2089 (lshiftrt:HI (match_operand:HI 1 "bit_operand" "Ur")
2090 (match_operand:HI 2 "const_int_operand" "n"))))
2093 "* return output_simode_bld (1, 0, operands);"
2094 [(set_attr "cc" "clobber")
2095 (set (attr "length")
2096 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2102 [(set (match_operand:SI 0 "register_operand" "=&r")
2104 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))
2105 (match_operand:SI 2 "p_operand" "P")))]
2107 "* return output_simode_bld (1, 1, operands);"
2108 [(set_attr "cc" "clobber")
2109 (set (attr "length")
2110 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2115 [(set (match_operand:SI 0 "register_operand" "=&r")
2118 (lshiftrt:QI (match_operand:QI 1 "bit_operand" "Ur")
2119 (match_operand:QI 2 "const_int_operand" "n"))))
2122 "* return output_simode_bld (1, 0, operands);"
2123 [(set_attr "cc" "clobber")
2124 (set (attr "length")
2125 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2131 [(set (match_operand:SI 0 "register_operand" "=&r")
2135 (match_operand:HI 1 "bit_operand" "Ur")
2136 (match_operand:HI 2 "const_int_operand" "n")) 0))
2139 "* return output_simode_bld (1, 0, operands);"
2140 [(set_attr "cc" "clobber")
2141 (set (attr "length")
2142 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2148 [(set (match_operand:SI 0 "register_operand" "=&r")
2152 (match_operand:QI 1 "bit_operand" "Ur")
2153 (match_operand:QI 2 "const_int_operand" "n")) 0))
2156 "* return output_simode_bld (1, 0, operands);"
2157 [(set_attr "cc" "clobber")
2158 (set (attr "length")
2159 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2165 [(set (match_operand:SI 0 "register_operand" "=&r")
2166 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2167 (match_operand:HI 3 "p_operand" "P"))
2169 (match_operand:HI 2 "const_int_operand" "n")))]
2170 "(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2171 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2172 [(set_attr "cc" "clobber")
2173 (set_attr "length" "8")])
2175 (define_expand "insv"
2176 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2177 (match_operand:HI 1 "general_operand" "")
2178 (match_operand:HI 2 "general_operand" ""))
2179 (match_operand:HI 3 "general_operand" ""))]
2183 /* We only have single bit bitfield instructions. */
2184 if (INTVAL (operands[1]) != 1)
2187 /* For now, we don't allow memory operands. */
2188 if (GET_CODE (operands[0]) == MEM
2189 || GET_CODE (operands[3]) == MEM)
2194 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2196 (match_operand:HI 1 "immediate_operand" "n"))
2197 (match_operand:HI 2 "register_operand" "r"))]
2199 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2200 [(set_attr "cc" "clobber")
2201 (set_attr "length" "4")])
2203 (define_expand "extzv"
2204 [(set (match_operand:HI 0 "register_operand" "")
2205 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2206 (match_operand:HI 2 "general_operand" "")
2207 (match_operand:HI 3 "general_operand" "")))]
2211 /* We only have single bit bitfield instructions. */
2212 if (INTVAL (operands[2]) != 1)
2215 /* For now, we don't allow memory operands. */
2216 if (GET_CODE (operands[1]) == MEM)
2220 ;; BAND, BOR, and BXOR patterns
2223 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2224 (match_operator:HI 4 "bit_operator"
2225 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2227 (match_operand:HI 2 "immediate_operand" "n"))
2228 (match_operand:HI 3 "bit_operand" "0")]))]
2230 "bld %Z2,%Y1\;%b4 #0,%R0\;bst #0,%R0; bl1"
2231 [(set_attr "cc" "clobber")
2232 (set_attr "length" "6")
2233 (set_attr "adjust_length" "no")])
2236 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2237 (match_operator:HI 5 "bit_operator"
2238 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2240 (match_operand:HI 2 "immediate_operand" "n"))
2241 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2243 (match_operand:HI 4 "immediate_operand" "n"))]))]
2245 "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%R0; bl3"
2246 [(set_attr "cc" "clobber")
2247 (set_attr "length" "6")
2248 (set_attr "adjust_length" "no")])