1 ;; GCC machine description for Renesas H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010
4 ;; Free Software Foundation, Inc.
6 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
7 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
9 ;; This file is part of GCC.
11 ;; GCC is free software; you can redistribute it and/or modify
12 ;; it under the terms of the GNU General Public License as published by
13 ;; the Free Software Foundation; either version 3, or (at your option)
16 ;; GCC is distributed in the hope that it will be useful,
17 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
18 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 ;; GNU General Public License for more details.
21 ;; You should have received a copy of the GNU General Public License
22 ;; along with GCC; see the file COPYING3. If not see
23 ;; <http://www.gnu.org/licenses/>.
25 ;; We compute exact length on each instruction for most of the time.
26 ;; In some case, most notably bit operations that may involve memory
27 ;; operands, the lengths in this file are "worst case".
29 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
30 ;; registers. Right now GCC doesn't expose the "e" half to the
31 ;; compiler, so using add/subs for addhi and subhi is safe. Long
32 ;; term, we want to expose the "e" half to the compiler (gives us 8
33 ;; more 16bit registers). At that point addhi and subhi can't use
36 ;; There's currently no way to have an insv/extzv expander for the H8/300H
37 ;; because word_mode is different for the H8/300 and H8/300H.
39 ;; Shifts/rotates by small constants should be handled by special
40 ;; patterns so we get the length and cc status correct.
42 ;; Bitfield operations no longer accept memory operands. We need
43 ;; to add variants which operate on memory back to the MD.
45 ;; ??? Implement remaining bit ops available on the h8300
47 ;; ----------------------------------------------------------------------
49 ;; ----------------------------------------------------------------------
72 ;; ----------------------------------------------------------------------
74 ;; ----------------------------------------------------------------------
76 (define_attr "cpu" "h8300,h8300h"
77 (const (symbol_ref "cpu_type")))
79 (define_attr "type" "branch,arith,bitbranch,call"
80 (const_string "arith"))
82 (define_attr "length_table" "none,addb,addw,addl,logicb,movb,movw,movl,mova_zero,mova,unary,mov_imm4,short_immediate,bitfield,bitbranch"
83 (const_string "none"))
85 ;; The size of instructions in bytes.
87 (define_attr "length" ""
88 (cond [(eq_attr "type" "branch")
89 ;; In a forward delayed branch, (pc) represents the end of the
90 ;; delay sequence, not the end of the branch itself.
91 (if_then_else (and (ge (minus (match_dup 0) (pc))
93 (le (plus (minus (match_dup 0) (pc))
94 (symbol_ref "DELAY_SLOT_LENGTH (insn)"))
97 (if_then_else (and (eq_attr "cpu" "h8300h")
98 (and (ge (minus (pc) (match_dup 0))
100 (le (minus (pc) (match_dup 0))
104 (eq_attr "type" "bitbranch")
106 (and (ge (minus (match_dup 0) (pc))
108 (le (minus (match_dup 0) (pc))
111 (symbol_ref "h8300_insn_length_from_table (insn, operands)")
114 (and (eq_attr "cpu" "h8300h")
115 (and (ge (minus (pc) (match_dup 0))
117 (le (minus (pc) (match_dup 0))
120 (symbol_ref "h8300_insn_length_from_table (insn, operands)")
123 (symbol_ref "h8300_insn_length_from_table (insn, operands)")
125 (eq_attr "length_table" "!none")
126 (symbol_ref "h8300_insn_length_from_table (insn, operands)")]
129 ;; Condition code settings.
131 ;; none - insn does not affect cc
132 ;; none_0hit - insn does not affect cc but it does modify operand 0
133 ;; This attribute is used to keep track of when operand 0 changes.
134 ;; See the description of NOTICE_UPDATE_CC for more info.
135 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
136 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
137 ;; compare - compare instruction
138 ;; clobber - value of cc is unknown
140 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
141 (const_string "clobber"))
143 ;; Type of delay slot. NONE means the instruction has no delay slot.
144 ;; JUMP means it is an unconditional jump that (if short enough)
145 ;; could be implemented using bra/s.
146 (define_attr "delay_slot" "none,jump"
147 (const_string "none"))
149 ;; "yes" if the instruction can be put into a delay slot. It's not
150 ;; entirely clear that jsr is not valid in delay slots, but it
151 ;; definitely doesn't have the effect of causing the called function
152 ;; to return to the target of the delayed branch.
153 (define_attr "can_delay" "no,yes"
154 (cond [(eq_attr "type" "branch,bitbranch,call")
156 (geu (symbol_ref "get_attr_length (insn)") (const_int 2))
158 (const_string "yes")))
160 ;; Only allow jumps to have a delay slot if we think they might
161 ;; be short enough. This is just an optimization: we don't know
162 ;; for certain whether they will be or not.
163 (define_delay (and (eq_attr "delay_slot" "jump")
164 (eq (symbol_ref "get_attr_length (insn)") (const_int 2)))
165 [(eq_attr "can_delay" "yes")
169 ;; Provide the maximum length of an assembly instruction in an asm
170 ;; statement. The maximum length of 14 bytes is achieved on H8SX.
172 (define_asm_attributes
173 [(set (attr "length")
174 (cond [(ne (symbol_ref "TARGET_H8300") (const_int 0)) (const_int 4)
175 (ne (symbol_ref "TARGET_H8300H") (const_int 0)) (const_int 10)
176 (ne (symbol_ref "TARGET_H8300S") (const_int 0)) (const_int 10)]
179 (include "predicates.md")
180 (include "constraints.md")
182 ;; ----------------------------------------------------------------------
184 ;; ----------------------------------------------------------------------
186 ;; This mode iterator allows :P to be used for patterns that operate on
187 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
188 (define_mode_iterator P [(HI "Pmode == HImode") (SI "Pmode == SImode")])
191 ;; ----------------------------------------------------------------------
193 ;; ----------------------------------------------------------------------
197 (define_insn "*movqi_h8300"
198 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
199 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
201 && h8300_move_ok (operands[0], operands[1])"
209 [(set_attr "length" "2,2,2,2,4,4")
210 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
212 (define_insn "*movqi_h8300hs"
213 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
214 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
215 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
216 && h8300_move_ok (operands[0], operands[1])"
224 [(set (attr "length")
225 (symbol_ref "compute_mov_length (operands)"))
226 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
228 (define_insn "*movqi_h8sx"
229 [(set (match_operand:QI 0 "general_operand_dst" "=Z,rQ")
230 (match_operand:QI 1 "general_operand_src" "P4>X,rQi"))]
235 [(set_attr "length_table" "mov_imm4,movb")
236 (set_attr "cc" "set_znv")])
238 (define_expand "movqi"
239 [(set (match_operand:QI 0 "general_operand_dst" "")
240 (match_operand:QI 1 "general_operand_src" ""))]
243 /* One of the ops has to be in a register. */
244 if (!TARGET_H8300SX && !h8300_move_ok (operands[0], operands[1]))
245 operands[1] = copy_to_mode_reg (QImode, operands[1]);
248 (define_insn "movstrictqi"
249 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r"))
250 (match_operand:QI 1 "general_operand_src" "I,rmi>"))]
255 [(set_attr "length" "2,*")
256 (set_attr "length_table" "*,movb")
257 (set_attr "cc" "set_zn,set_znv")])
261 (define_insn "*movhi_h8300"
262 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
263 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
265 && h8300_move_ok (operands[0], operands[1])"
273 [(set (attr "length")
274 (symbol_ref "compute_mov_length (operands)"))
275 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
277 (define_insn "*movhi_h8300hs"
278 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
279 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
280 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
281 && h8300_move_ok (operands[0], operands[1])"
289 [(set (attr "length")
290 (symbol_ref "compute_mov_length (operands)"))
291 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
293 (define_insn "*movhi_h8sx"
294 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Z,Q,rQ")
295 (match_operand:HI 1 "general_operand_src" "I,P3>X,P4>X,IP8>X,rQi"))]
303 [(set_attr "length_table" "*,*,mov_imm4,short_immediate,movw")
304 (set_attr "length" "2,2,*,*,*")
305 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
307 (define_expand "movhi"
308 [(set (match_operand:HI 0 "general_operand_dst" "")
309 (match_operand:HI 1 "general_operand_src" ""))]
312 /* One of the ops has to be in a register. */
313 if (!h8300_move_ok (operands[0], operands[1]))
314 operands[1] = copy_to_mode_reg (HImode, operand1);
317 (define_insn "movstricthi"
318 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r"))
319 (match_operand:HI 1 "general_operand_src" "I,P3>X,rmi"))]
325 [(set_attr "length" "2,2,*")
326 (set_attr "length_table" "*,*,movw")
327 (set_attr "cc" "set_zn,set_znv,set_znv")])
331 (define_expand "movsi"
332 [(set (match_operand:SI 0 "general_operand_dst" "")
333 (match_operand:SI 1 "general_operand_src" ""))]
338 if (h8300_expand_movsi (operands))
341 else if (!TARGET_H8300SX)
343 /* One of the ops has to be in a register. */
344 if (!h8300_move_ok (operands[0], operands[1]))
345 operands[1] = copy_to_mode_reg (SImode, operand1);
349 (define_insn "*movsi_h8300"
350 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
351 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
353 && h8300_move_ok (operands[0], operands[1])"
356 unsigned int rn = -1;
357 switch (which_alternative)
360 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
362 if (REGNO (operands[0]) < REGNO (operands[1]))
363 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
365 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
367 /* Make sure we don't trample the register we index with. */
368 if (GET_CODE (operands[1]) == MEM)
370 rtx inside = XEXP (operands[1], 0);
375 else if (GET_CODE (inside) == PLUS)
377 rtx lhs = XEXP (inside, 0);
378 rtx rhs = XEXP (inside, 1);
379 if (REG_P (lhs)) rn = REGNO (lhs);
380 if (REG_P (rhs)) rn = REGNO (rhs);
383 if (rn == REGNO (operands[0]))
385 /* Move the second word first. */
386 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
390 if (GET_CODE (operands[1]) == CONST_INT)
392 /* If either half is zero, use sub.w to clear that
394 if ((INTVAL (operands[1]) & 0xffff) == 0)
395 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
396 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
397 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
398 /* If the upper half and the lower half are the same,
399 copy one half to the other. */
400 if ((INTVAL (operands[1]) & 0xffff)
401 == ((INTVAL (operands[1]) >> 16) & 0xffff))
402 return \"mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0\";
404 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
407 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
409 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
411 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
416 [(set (attr "length")
417 (symbol_ref "compute_mov_length (operands)"))])
419 (define_insn "*movsi_h8300hs"
420 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
421 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
422 "(TARGET_H8300S || TARGET_H8300H) && !TARGET_H8300SX
423 && h8300_move_ok (operands[0], operands[1])"
426 switch (which_alternative)
429 return \"sub.l %S0,%S0\";
433 return \"clrmac\;ldmac %1,macl\";
435 return \"stmac macl,%0\";
437 if (GET_CODE (operands[1]) == CONST_INT)
439 int val = INTVAL (operands[1]);
441 /* Look for constants which can be made by adding an 8-bit
442 number to zero in one of the two low bytes. */
443 if (val == (val & 0xff))
445 operands[1] = GEN_INT ((char) val & 0xff);
446 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
449 if (val == (val & 0xff00))
451 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
452 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
455 /* Look for constants that can be obtained by subs, inc, and
457 switch (val & 0xffffffff)
460 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
462 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
464 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
467 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
469 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
472 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
474 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
477 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
479 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
483 return \"mov.l %S1,%S0\";
485 [(set (attr "length")
486 (symbol_ref "compute_mov_length (operands)"))
487 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
489 (define_insn "*movsi_h8sx"
490 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,Q,rQ,*a,*a,r")
491 (match_operand:SI 1 "general_operand_src" "I,P3>X,IP8>X,rQi,I,r,*a"))]
499 clrmac\;ldmac %1,macl
501 [(set_attr "length_table" "*,*,short_immediate,movl,*,*,*")
502 (set_attr "length" "2,2,*,*,2,6,4")
503 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
505 (define_insn "*movsf_h8sx"
506 [(set (match_operand:SF 0 "general_operand_dst" "=r,rQ")
507 (match_operand:SF 1 "general_operand_src" "G,rQi"))]
512 [(set_attr "length" "2,*")
513 (set_attr "length_table" "*,movl")
514 (set_attr "cc" "set_zn,set_znv")])
516 ;; Implement block moves using movmd. Defining movmemsi allows the full
517 ;; range of constant lengths (up to 0x40000 bytes when using movmd.l).
518 ;; See h8sx_emit_movmd for details.
519 (define_expand "movmemsi"
520 [(use (match_operand:BLK 0 "memory_operand" ""))
521 (use (match_operand:BLK 1 "memory_operand" ""))
522 (use (match_operand:SI 2 "" ""))
523 (use (match_operand:SI 3 "const_int_operand" ""))]
526 if (h8sx_emit_movmd (operands[0], operands[1], operands[2],
527 INTVAL (operands[3])))
533 ;; Expander for generating movmd insns. Operand 0 is the destination
534 ;; memory region, operand 1 is the source, operand 2 is the counter
535 ;; register and operand 3 is the chunk size (1, 2 or 4).
536 (define_expand "movmd"
538 [(set (match_operand:BLK 0 "memory_operand" "")
539 (match_operand:BLK 1 "memory_operand" ""))
540 (unspec [(match_operand:HI 2 "register_operand" "")
541 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
542 (clobber (match_dup 4))
543 (clobber (match_dup 5))
548 operands[4] = copy_rtx (XEXP (operands[0], 0));
549 operands[5] = copy_rtx (XEXP (operands[1], 0));
553 ;; This is a difficult instruction to reload since operand 0 must be the
554 ;; frame pointer. See h8300_reg_class_from_letter for an explanation.
555 (define_insn "movmd_internal_normal"
556 [(set (mem:BLK (match_operand:HI 3 "register_operand" "0,r"))
557 (mem:BLK (match_operand:HI 4 "register_operand" "1,1")))
558 (unspec [(match_operand:HI 5 "register_operand" "2,2")
559 (match_operand:HI 6 "const_int_operand" "n,n")] UNSPEC_MOVMD)
560 (clobber (match_operand:HI 0 "register_operand" "=d,??D"))
561 (clobber (match_operand:HI 1 "register_operand" "=f,f"))
562 (set (match_operand:HI 2 "register_operand" "=c,c")
564 "TARGET_H8300SX && TARGET_NORMAL_MODE"
568 [(set_attr "length" "2,14")
569 (set_attr "can_delay" "no")
570 (set_attr "cc" "none,clobber")])
572 (define_insn "movmd_internal"
573 [(set (mem:BLK (match_operand:SI 3 "register_operand" "0,r"))
574 (mem:BLK (match_operand:SI 4 "register_operand" "1,1")))
575 (unspec [(match_operand:HI 5 "register_operand" "2,2")
576 (match_operand:HI 6 "const_int_operand" "n,n")] UNSPEC_MOVMD)
577 (clobber (match_operand:SI 0 "register_operand" "=d,??D"))
578 (clobber (match_operand:SI 1 "register_operand" "=f,f"))
579 (set (match_operand:HI 2 "register_operand" "=c,c")
581 "TARGET_H8300SX && !TARGET_NORMAL_MODE"
585 [(set_attr "length" "2,14")
586 (set_attr "can_delay" "no")
587 (set_attr "cc" "none,clobber")])
589 ;; Split the above instruction if the destination register isn't er6.
590 ;; We need a sequence like:
598 ;; where <dest> is the current destination register (operand 4).
599 ;; The fourth instruction will be deleted if <dest> dies here.
601 [(set (match_operand:BLK 0 "memory_operand" "")
602 (match_operand:BLK 1 "memory_operand" ""))
603 (unspec [(match_operand:HI 2 "register_operand" "")
604 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
605 (clobber (match_operand:HI 4 "register_operand" ""))
606 (clobber (match_operand:HI 5 "register_operand" ""))
609 "TARGET_H8300SX && TARGET_NORMAL_MODE
611 && REGNO (operands[4]) != DESTINATION_REG"
616 h8300_swap_into_er6 (XEXP (operands[0], 0));
617 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
618 emit_insn (gen_movmd (dest, operands[1], operands[2], operands[3]));
619 h8300_swap_out_of_er6 (operands[4]);
624 [(set (match_operand:BLK 0 "memory_operand" "")
625 (match_operand:BLK 1 "memory_operand" ""))
626 (unspec [(match_operand:HI 2 "register_operand" "")
627 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
628 (clobber (match_operand:SI 4 "register_operand" ""))
629 (clobber (match_operand:SI 5 "register_operand" ""))
632 "TARGET_H8300SX && !TARGET_NORMAL_MODE
634 && REGNO (operands[4]) != DESTINATION_REG"
639 h8300_swap_into_er6 (XEXP (operands[0], 0));
640 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
641 emit_insn (gen_movmd (dest, operands[1], operands[2], operands[3]));
642 h8300_swap_out_of_er6 (operands[4]);
646 ;; Expand a call to stpcpy() using movsd. Operand 0 should point to
647 ;; the final character, but movsd leaves it pointing to the character
649 (define_expand "movstr"
650 [(use (match_operand 0 "register_operand" ""))
651 (use (match_operand:BLK 1 "memory_operand" ""))
652 (use (match_operand:BLK 2 "memory_operand" ""))]
655 operands[1] = replace_equiv_address
656 (operands[1], copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
657 operands[2] = replace_equiv_address
658 (operands[2], copy_to_mode_reg (Pmode, XEXP (operands[2], 0)));
659 emit_insn (gen_movsd (operands[1], operands[2], gen_reg_rtx (Pmode)));
660 emit_insn (gen_add3_insn (operands[0],
661 XEXP (operands[1], 0),
666 ;; Expander for generating a movsd instruction. Operand 0 is the
667 ;; destination string, operand 1 is the source string and operand 2
668 ;; is a scratch register.
669 (define_expand "movsd"
671 [(set (match_operand:BLK 0 "memory_operand" "")
672 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")]
674 (clobber (match_dup 3))
675 (clobber (match_dup 4))
676 (clobber (match_operand 2 "register_operand" ""))])]
679 operands[3] = copy_rtx (XEXP (operands[0], 0));
680 operands[4] = copy_rtx (XEXP (operands[1], 0));
683 ;; See comments above memcpy_internal().
684 (define_insn "stpcpy_internal_normal"
685 [(set (mem:BLK (match_operand:HI 3 "register_operand" "0,r"))
686 (unspec:BLK [(mem:BLK (match_operand:HI 4 "register_operand" "1,1"))]
688 (clobber (match_operand:HI 0 "register_operand" "=d,??D"))
689 (clobber (match_operand:HI 1 "register_operand" "=f,f"))
690 (clobber (match_operand:HI 2 "register_operand" "=c,c"))]
691 "TARGET_H8300SX && TARGET_NORMAL_MODE"
693 \n1:\tmovsd\t2f\;bra\t1b\n2:
695 [(set_attr "length" "6,18")
696 (set_attr "cc" "none,clobber")])
698 (define_insn "stpcpy_internal"
699 [(set (mem:BLK (match_operand:SI 3 "register_operand" "0,r"))
700 (unspec:BLK [(mem:BLK (match_operand:SI 4 "register_operand" "1,1"))]
702 (clobber (match_operand:SI 0 "register_operand" "=d,??D"))
703 (clobber (match_operand:SI 1 "register_operand" "=f,f"))
704 (clobber (match_operand:SI 2 "register_operand" "=c,c"))]
705 "TARGET_H8300SX && !TARGET_NORMAL_MODE"
707 \n1:\tmovsd\t2f\;bra\t1b\n2:
709 [(set_attr "length" "6,18")
710 (set_attr "cc" "none,clobber")])
712 ;; Split the above instruction if the destination isn't er6. This works
713 ;; in the same way as the movmd splitter.
715 [(set (match_operand:BLK 0 "memory_operand" "")
716 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY))
717 (clobber (match_operand:HI 2 "register_operand" ""))
718 (clobber (match_operand:HI 3 "register_operand" ""))
719 (clobber (match_operand:HI 4 "register_operand" ""))]
720 "TARGET_H8300SX && TARGET_NORMAL_MODE
722 && REGNO (operands[2]) != DESTINATION_REG"
727 h8300_swap_into_er6 (XEXP (operands[0], 0));
728 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
729 emit_insn (gen_movsd (dest, operands[1], operands[4]));
730 h8300_swap_out_of_er6 (operands[2]);
735 [(set (match_operand:BLK 0 "memory_operand" "")
736 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY))
737 (clobber (match_operand:SI 2 "register_operand" ""))
738 (clobber (match_operand:SI 3 "register_operand" ""))
739 (clobber (match_operand:SI 4 "register_operand" ""))]
740 "TARGET_H8300SX && !TARGET_NORMAL_MODE
742 && REGNO (operands[2]) != DESTINATION_REG"
747 h8300_swap_into_er6 (XEXP (operands[0], 0));
748 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
749 emit_insn (gen_movsd (dest, operands[1], operands[4]));
750 h8300_swap_out_of_er6 (operands[2]);
756 (define_expand "movsf"
757 [(set (match_operand:SF 0 "general_operand_dst" "")
758 (match_operand:SF 1 "general_operand_src" ""))]
764 if (h8300_expand_movsi (operands))
767 else if (!TARGET_H8300SX)
769 /* One of the ops has to be in a register. */
770 if (!register_operand (operand1, SFmode)
771 && !register_operand (operand0, SFmode))
773 operands[1] = copy_to_mode_reg (SFmode, operand1);
778 (define_insn "*movsf_h8300"
779 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
780 (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))]
782 && (register_operand (operands[0], SFmode)
783 || register_operand (operands[1], SFmode))"
786 /* Copy of the movsi stuff. */
787 unsigned int rn = -1;
788 switch (which_alternative)
791 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
793 if (REGNO (operands[0]) < REGNO (operands[1]))
794 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
796 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
798 /* Make sure we don't trample the register we index with. */
799 if (GET_CODE (operands[1]) == MEM)
801 rtx inside = XEXP (operands[1], 0);
806 else if (GET_CODE (inside) == PLUS)
808 rtx lhs = XEXP (inside, 0);
809 rtx rhs = XEXP (inside, 1);
810 if (REG_P (lhs)) rn = REGNO (lhs);
811 if (REG_P (rhs)) rn = REGNO (rhs);
814 if (rn == REGNO (operands[0]))
815 /* Move the second word first. */
816 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
818 /* Move the first word first. */
819 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
822 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
824 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
826 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
831 [(set (attr "length")
832 (symbol_ref "compute_mov_length (operands)"))])
834 (define_insn "*movsf_h8300hs"
835 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
836 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
837 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
838 && (register_operand (operands[0], SFmode)
839 || register_operand (operands[1], SFmode))"
847 [(set (attr "length")
848 (symbol_ref "compute_mov_length (operands)"))
849 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
851 ;; ----------------------------------------------------------------------
853 ;; ----------------------------------------------------------------------
855 (define_insn "*pushqi1_h8300"
859 (plus:HI (reg:HI SP_REG) (const_int -2))))
860 (match_operand:QI 0 "register_no_sp_elim_operand" "r"))]
863 [(set_attr "length" "2")])
865 (define_insn "*pushqi1_h8300hs_<mode>"
869 (plus:P (reg:P SP_REG) (const_int -4))))
870 (match_operand:QI 0 "register_no_sp_elim_operand" "r"))]
871 "TARGET_H8300H || TARGET_H8300S"
873 [(set_attr "length" "4")])
875 (define_insn "*pushhi1_h8300hs_<mode>"
879 (plus:P (reg:P SP_REG) (const_int -4))))
880 (match_operand:HI 0 "register_no_sp_elim_operand" "r"))]
881 "TARGET_H8300H || TARGET_H8300S"
883 [(set_attr "length" "4")])
885 ;; ----------------------------------------------------------------------
887 ;; ----------------------------------------------------------------------
891 (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "r,U")
893 (match_operand 1 "const_int_operand" "n,n"))
897 [(set_attr "length" "2,4")
898 (set_attr "cc" "set_zn,set_zn")])
902 (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
904 (match_operand 1 "const_int_operand" "n"))
908 [(set_attr "length" "2")
909 (set_attr "cc" "set_zn")])
911 (define_insn_and_split "*tst_extzv_1_n"
913 (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
915 (match_operand 1 "const_int_operand" "n,n,n"))
917 (clobber (match_scratch:QI 2 "=X,X,&r"))]
918 "(TARGET_H8300H || TARGET_H8300S)"
924 && !satisfies_constraint_U (operands[0])"
927 (parallel [(set (cc0) (compare (zero_extract:SI (match_dup 2)
931 (clobber (scratch:QI))])]
933 [(set_attr "length" "2,8,10")
934 (set_attr "cc" "set_zn,set_zn,set_zn")])
937 [(set (cc0) (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
939 (match_operand 1 "const_int_operand" "n"))
941 "(TARGET_H8300H || TARGET_H8300S)
942 && INTVAL (operands[1]) <= 15"
944 [(set_attr "length" "2")
945 (set_attr "cc" "set_zn")])
947 (define_insn_and_split "*tstsi_upper_bit"
948 [(set (cc0) (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
950 (match_operand 1 "const_int_operand" "n"))
952 (clobber (match_scratch:SI 2 "=&r"))]
953 "(TARGET_H8300H || TARGET_H8300S)
954 && INTVAL (operands[1]) >= 16"
956 "&& reload_completed"
958 (ior:SI (and:SI (match_dup 2)
960 (lshiftrt:SI (match_dup 0)
962 (set (cc0) (compare (zero_extract:SI (match_dup 2)
966 "operands[3] = GEN_INT (INTVAL (operands[1]) - 16);")
968 (define_insn "*tstsi_variable_bit"
969 [(set (cc0) (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
971 (and:SI (match_operand:SI 1 "register_operand" "r")
974 "TARGET_H8300H || TARGET_H8300S"
976 [(set_attr "length" "2")
977 (set_attr "cc" "set_zn")])
979 (define_insn_and_split "*tstsi_variable_bit_qi"
982 (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>"))
984 (and:SI (match_operand:SI 1 "register_operand" "r,r,r")
987 (clobber (match_scratch:QI 2 "=X,X,&r"))]
988 "(TARGET_H8300H || TARGET_H8300S)"
994 && !satisfies_constraint_U (operands[0])"
997 (parallel [(set (cc0) (compare (zero_extract:SI (zero_extend:SI (match_dup 2))
999 (and:SI (match_dup 1)
1002 (clobber (scratch:QI))])]
1004 [(set_attr "length" "2,8,10")
1005 (set_attr "cc" "set_zn,set_zn,set_zn")])
1007 (define_insn "*tstqi"
1008 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "r")
1012 [(set_attr "length" "2")
1013 (set_attr "cc" "set_znv")])
1015 (define_insn "*tsthi"
1016 [(set (cc0) (compare (match_operand:HI 0 "register_operand" "r")
1020 [(set_attr "length" "2")
1021 (set_attr "cc" "set_znv")])
1023 (define_insn "*tsthi_upper"
1024 [(set (cc0) (compare (and:HI (match_operand:HI 0 "register_operand" "r")
1029 [(set_attr "length" "2")
1030 (set_attr "cc" "set_znv")])
1032 (define_insn "*tstsi"
1033 [(set (cc0) (compare (match_operand:SI 0 "register_operand" "r")
1035 "TARGET_H8300H || TARGET_H8300S"
1037 [(set_attr "length" "2")
1038 (set_attr "cc" "set_znv")])
1040 (define_insn "*tstsi_upper"
1041 [(set (cc0) (compare (and:SI (match_operand:SI 0 "register_operand" "r")
1046 [(set_attr "length" "2")
1047 (set_attr "cc" "set_znv")])
1049 (define_insn "*cmpqi"
1051 (compare (match_operand:QI 0 "h8300_dst_operand" "rQ")
1052 (match_operand:QI 1 "h8300_src_operand" "rQi")))]
1055 [(set_attr "length_table" "addb")
1056 (set_attr "cc" "compare")])
1058 (define_insn "*cmphi_h8300_znvc"
1060 (compare (match_operand:HI 0 "register_operand" "r")
1061 (match_operand:HI 1 "register_operand" "r")))]
1064 [(set_attr "length" "2")
1065 (set_attr "cc" "compare")])
1067 (define_insn "*cmphi_h8300hs_znvc"
1069 (compare (match_operand:HI 0 "h8300_dst_operand" "rU,rQ")
1070 (match_operand:HI 1 "h8300_src_operand" "P3>X,rQi")))]
1071 "TARGET_H8300H || TARGET_H8300S"
1074 switch (which_alternative)
1077 if (!TARGET_H8300SX)
1078 return \"cmp.w %T1,%T0\";
1080 return \"cmp.w %T1:3,%T0\";
1082 return \"cmp.w %T1,%T0\";
1087 [(set_attr "length_table" "short_immediate,addw")
1088 (set_attr "cc" "compare,compare")])
1090 (define_insn "cmpsi"
1092 (compare (match_operand:SI 0 "h8300_dst_operand" "r,rQ")
1093 (match_operand:SI 1 "h8300_src_operand" "P3>X,rQi")))]
1094 "TARGET_H8300H || TARGET_H8300S"
1097 switch (which_alternative)
1100 if (!TARGET_H8300SX)
1101 return \"cmp.l %S1,%S0\";
1103 return \"cmp.l %S1:3,%S0\";
1105 return \"cmp.l %S1,%S0\";
1110 [(set_attr "length" "2,*")
1111 (set_attr "length_table" "*,addl")
1112 (set_attr "cc" "compare,compare")])
1114 ;; ----------------------------------------------------------------------
1116 ;; ----------------------------------------------------------------------
1118 (define_expand "addqi3"
1119 [(set (match_operand:QI 0 "register_operand" "")
1120 (plus:QI (match_operand:QI 1 "register_operand" "")
1121 (match_operand:QI 2 "h8300_src_operand" "")))]
1125 (define_insn "*addqi3"
1126 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1127 (plus:QI (match_operand:QI 1 "h8300_dst_operand" "%0")
1128 (match_operand:QI 2 "h8300_src_operand" "rQi")))]
1129 "h8300_operands_match_p (operands)"
1131 [(set_attr "length_table" "addb")
1132 (set_attr "cc" "set_zn")])
1134 (define_expand "addhi3"
1135 [(set (match_operand:HI 0 "register_operand" "")
1136 (plus:HI (match_operand:HI 1 "register_operand" "")
1137 (match_operand:HI 2 "h8300_src_operand" "")))]
1141 (define_insn "*addhi3_h8300"
1142 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1143 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
1144 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
1150 add.b %s2,%s0\;addx %t2,%t0
1152 [(set_attr "length" "2,2,2,4,2")
1153 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
1155 ;; This splitter is very important to make the stack adjustment
1156 ;; interrupt-safe. The combination of add.b and addx is unsafe!
1158 ;; We apply this split after the peephole2 pass so that we won't end
1159 ;; up creating too many adds/subs when a scratch register is
1160 ;; available, which is actually a common case because stack unrolling
1161 ;; tends to happen immediately after a function call.
1164 [(set (match_operand:HI 0 "stack_pointer_operand" "")
1165 (plus:HI (match_dup 0)
1166 (match_operand 1 "const_int_gt_2_operand" "")))]
1167 "TARGET_H8300 && epilogue_completed"
1169 "split_adds_subs (HImode, operands); DONE;")
1172 [(match_scratch:HI 2 "r")
1173 (set (match_operand:HI 0 "stack_pointer_operand" "")
1174 (plus:HI (match_dup 0)
1175 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
1180 (plus:HI (match_dup 0)
1184 (define_insn "*addhi3_h8300hs"
1185 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1186 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
1187 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
1188 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
1195 [(set_attr "length" "2,2,2,4,2")
1196 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
1198 (define_insn "*addhi3_incdec"
1199 [(set (match_operand:HI 0 "register_operand" "=r,r")
1200 (unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
1201 (match_operand:HI 2 "incdec_operand" "M,O")]
1203 "TARGET_H8300H || TARGET_H8300S"
1207 [(set_attr "length" "2,2")
1208 (set_attr "cc" "set_zn,set_zn")])
1210 (define_insn "*addhi3_h8sx"
1211 [(set (match_operand:HI 0 "h8300_dst_operand" "=rU,rU,r,rQ")
1212 (plus:HI (match_operand:HI 1 "h8300_dst_operand" "%0,0,0,0")
1213 (match_operand:HI 2 "h8300_src_operand" "P3>X,P3<X,J,rQi")))]
1214 "TARGET_H8300SX && h8300_operands_match_p (operands)"
1220 [(set_attr "length_table" "short_immediate,short_immediate,*,addw")
1221 (set_attr "length" "*,*,2,*")
1222 (set_attr "cc" "set_zn")])
1225 [(set (match_operand:HI 0 "register_operand" "")
1226 (plus:HI (match_dup 0)
1227 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
1230 "split_adds_subs (HImode, operands); DONE;")
1232 (define_expand "addsi3"
1233 [(set (match_operand:SI 0 "register_operand" "")
1234 (plus:SI (match_operand:SI 1 "register_operand" "")
1235 (match_operand:SI 2 "h8300_src_operand" "")))]
1239 (define_insn "*addsi_h8300"
1240 [(set (match_operand:SI 0 "register_operand" "=r,r")
1241 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
1242 (match_operand:SI 2 "h8300_src_operand" "n,r")))]
1244 "* return output_plussi (operands);"
1245 [(set (attr "length")
1246 (symbol_ref "compute_plussi_length (operands)"))
1248 (symbol_ref "compute_plussi_cc (operands)"))])
1250 (define_insn "*addsi_h8300hs"
1251 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
1252 (plus:SI (match_operand:SI 1 "h8300_dst_operand" "%0,0")
1253 (match_operand:SI 2 "h8300_src_operand" "i,rQ")))]
1254 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1255 "* return output_plussi (operands);"
1256 [(set (attr "length")
1257 (symbol_ref "compute_plussi_length (operands)"))
1259 (symbol_ref "compute_plussi_cc (operands)"))])
1261 (define_insn "*addsi3_incdec"
1262 [(set (match_operand:SI 0 "register_operand" "=r,r")
1263 (unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
1264 (match_operand:SI 2 "incdec_operand" "M,O")]
1266 "TARGET_H8300H || TARGET_H8300S"
1270 [(set_attr "length" "2,2")
1271 (set_attr "cc" "set_zn,set_zn")])
1274 [(set (match_operand:SI 0 "register_operand" "")
1275 (plus:SI (match_dup 0)
1276 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
1277 "TARGET_H8300H || TARGET_H8300S"
1279 "split_adds_subs (SImode, operands); DONE;")
1281 ;; ----------------------------------------------------------------------
1282 ;; SUBTRACT INSTRUCTIONS
1283 ;; ----------------------------------------------------------------------
1285 (define_expand "subqi3"
1286 [(set (match_operand:QI 0 "register_operand" "")
1287 (minus:QI (match_operand:QI 1 "register_operand" "")
1288 (match_operand:QI 2 "h8300_src_operand" "")))]
1292 (define_insn "*subqi3"
1293 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1294 (minus:QI (match_operand:QI 1 "h8300_dst_operand" "0")
1295 (match_operand:QI 2 "h8300_dst_operand" "rQ")))]
1296 "h8300_operands_match_p (operands)"
1298 [(set_attr "length_table" "addb")
1299 (set_attr "cc" "set_zn")])
1301 (define_expand "subhi3"
1302 [(set (match_operand:HI 0 "register_operand" "")
1303 (minus:HI (match_operand:HI 1 "register_operand" "")
1304 (match_operand:HI 2 "h8300_src_operand" "")))]
1308 (define_insn "*subhi3_h8300"
1309 [(set (match_operand:HI 0 "register_operand" "=r,r")
1310 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
1311 (match_operand:HI 2 "h8300_src_operand" "r,n")))]
1315 add.b %E2,%s0\;addx %F2,%t0"
1316 [(set_attr "length" "2,4")
1317 (set_attr "cc" "set_zn,clobber")])
1319 (define_insn "*subhi3_h8300hs"
1320 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ,rQ")
1321 (minus:HI (match_operand:HI 1 "h8300_dst_operand" "0,0")
1322 (match_operand:HI 2 "h8300_src_operand" "rQ,i")))]
1323 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1327 [(set_attr "length_table" "addw")
1328 (set_attr "cc" "set_zn")])
1330 (define_expand "subsi3"
1331 [(set (match_operand:SI 0 "register_operand" "")
1332 (minus:SI (match_operand:SI 1 "register_operand" "")
1333 (match_operand:SI 2 "h8300_src_operand" "")))]
1337 operands[2] = force_reg (SImode, operands[2]);
1340 (define_insn "*subsi3_h8300"
1341 [(set (match_operand:SI 0 "register_operand" "=r")
1342 (minus:SI (match_operand:SI 1 "register_operand" "0")
1343 (match_operand:SI 2 "register_operand" "r")))]
1345 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
1346 [(set_attr "length" "6")])
1348 (define_insn "*subsi3_h8300hs"
1349 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
1350 (minus:SI (match_operand:SI 1 "h8300_dst_operand" "0,0")
1351 (match_operand:SI 2 "h8300_src_operand" "rQ,i")))]
1352 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1356 [(set_attr "length_table" "addl")
1357 (set_attr "cc" "set_zn")])
1359 ;; ----------------------------------------------------------------------
1360 ;; MULTIPLY INSTRUCTIONS
1361 ;; ----------------------------------------------------------------------
1363 ;; Note that the H8/300 can only handle umulqihi3.
1365 (define_expand "mulqihi3"
1366 [(set (match_operand:HI 0 "register_operand" "")
1367 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" ""))
1368 ;; intentionally-mismatched modes
1369 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1370 "TARGET_H8300H || TARGET_H8300S"
1373 if (GET_MODE (operands[2]) != VOIDmode)
1374 operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]);
1377 (define_insn "*mulqihi3_const"
1378 [(set (match_operand:HI 0 "register_operand" "=r")
1379 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1380 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1383 [(set_attr "length" "4")
1384 (set_attr "cc" "set_zn")])
1386 (define_insn "*mulqihi3"
1387 [(set (match_operand:HI 0 "register_operand" "=r")
1388 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1389 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1390 "TARGET_H8300H || TARGET_H8300S"
1392 [(set_attr "length" "4")
1393 (set_attr "cc" "set_zn")])
1395 (define_expand "mulhisi3"
1396 [(set (match_operand:SI 0 "register_operand" "")
1397 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
1398 ;; intentionally-mismatched modes
1399 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1400 "TARGET_H8300H || TARGET_H8300S"
1403 if (GET_MODE (operands[2]) != VOIDmode)
1404 operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]);
1407 (define_insn "*mulhisi3_const"
1408 [(set (match_operand:SI 0 "register_operand" "=r")
1409 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1410 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1413 [(set_attr "length" "4")
1414 (set_attr "cc" "set_zn")])
1416 (define_insn "*mulhisi3"
1417 [(set (match_operand:SI 0 "register_operand" "=r")
1418 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1419 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1420 "TARGET_H8300H || TARGET_H8300S"
1422 [(set_attr "length" "4")
1423 (set_attr "cc" "set_zn")])
1425 (define_expand "umulqihi3"
1426 [(set (match_operand:HI 0 "register_operand" "")
1427 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" ""))
1428 ;; intentionally-mismatched modes
1429 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1430 "TARGET_H8300H || TARGET_H8300S"
1433 if (GET_MODE (operands[2]) != VOIDmode)
1434 operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]);
1437 (define_insn "*umulqihi3_const"
1438 [(set (match_operand:HI 0 "register_operand" "=r")
1439 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1440 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1443 [(set_attr "length" "4")
1444 (set_attr "cc" "set_zn")])
1446 (define_insn "*umulqihi3"
1447 [(set (match_operand:HI 0 "register_operand" "=r")
1448 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1449 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1452 [(set_attr "length" "2")
1453 (set_attr "cc" "none_0hit")])
1455 (define_expand "umulhisi3"
1456 [(set (match_operand:SI 0 "register_operand" "")
1457 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" ""))
1458 ;; intentionally-mismatched modes
1459 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1460 "TARGET_H8300H || TARGET_H8300S"
1463 if (GET_MODE (operands[2]) != VOIDmode)
1464 operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]);
1467 (define_insn "*umulhisi3_const"
1468 [(set (match_operand:SI 0 "register_operand" "=r")
1469 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1470 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1473 [(set_attr "length" "4")
1474 (set_attr "cc" "set_zn")])
1476 (define_insn "*umulhisi3"
1477 [(set (match_operand:SI 0 "register_operand" "=r")
1478 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1479 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1480 "TARGET_H8300H || TARGET_H8300S"
1482 [(set_attr "length" "2")
1483 (set_attr "cc" "none_0hit")])
1485 ;; We could have used mulu.[wl] here, but mulu.[lw] is only available
1486 ;; on a H8SX with a multiplier, whereas muls.w seems to be available
1487 ;; on all H8SX variants.
1488 (define_insn "mulhi3"
1489 [(set (match_operand:HI 0 "register_operand" "=r")
1490 (mult:HI (match_operand:HI 1 "register_operand" "%0")
1491 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1494 [(set_attr "length" "2")
1495 (set_attr "cc" "set_zn")])
1497 (define_insn "mulsi3"
1498 [(set (match_operand:SI 0 "register_operand" "=r")
1499 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1500 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1503 [(set_attr "length" "2")
1504 (set_attr "cc" "set_zn")])
1506 (define_insn "smulsi3_highpart"
1507 [(set (match_operand:SI 0 "register_operand" "=r")
1511 (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1512 (sign_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1515 "muls/u.l\\t%S2,%S0"
1516 [(set_attr "length" "2")
1517 (set_attr "cc" "set_zn")])
1519 (define_insn "umulsi3_highpart"
1520 [(set (match_operand:SI 0 "register_operand" "=r")
1524 (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1525 (zero_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1528 "mulu/u.l\\t%S2,%S0"
1529 [(set_attr "length" "2")
1530 (set_attr "cc" "none_0hit")])
1532 ;; This is a "bridge" instruction. Combine can't cram enough insns
1533 ;; together to crate a MAC instruction directly, but it can create
1534 ;; this instruction, which then allows combine to create the real
1537 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1538 ;; insn must generate reasonably correct code. Egad.
1540 [(set (match_operand:SI 0 "register_operand" "=a")
1543 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1545 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
1547 "clrmac\;mac @%2+,@%1+"
1548 [(set_attr "length" "6")
1549 (set_attr "cc" "none_0hit")])
1552 [(set (match_operand:SI 0 "register_operand" "=a")
1554 (sign_extend:SI (mem:HI
1555 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1556 (sign_extend:SI (mem:HI
1557 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1558 (match_operand:SI 3 "register_operand" "0")))]
1561 [(set_attr "length" "4")
1562 (set_attr "cc" "none_0hit")])
1564 ;; ----------------------------------------------------------------------
1565 ;; DIVIDE/MOD INSTRUCTIONS
1566 ;; ----------------------------------------------------------------------
1568 (define_insn "udivhi3"
1569 [(set (match_operand:HI 0 "register_operand" "=r")
1571 (match_operand:HI 1 "register_operand" "0")
1572 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1575 [(set_attr "length" "2")])
1577 (define_insn "divhi3"
1578 [(set (match_operand:HI 0 "register_operand" "=r")
1580 (match_operand:HI 1 "register_operand" "0")
1581 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1584 [(set_attr "length" "2")])
1586 (define_insn "udivsi3"
1587 [(set (match_operand:SI 0 "register_operand" "=r")
1589 (match_operand:SI 1 "register_operand" "0")
1590 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1593 [(set_attr "length" "2")])
1595 (define_insn "divsi3"
1596 [(set (match_operand:SI 0 "register_operand" "=r")
1598 (match_operand:SI 1 "register_operand" "0")
1599 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1602 [(set_attr "length" "2")])
1604 (define_insn "udivmodqi4"
1605 [(set (match_operand:QI 0 "register_operand" "=r")
1608 (match_operand:HI 1 "register_operand" "0")
1609 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1610 (set (match_operand:QI 3 "register_operand" "=r")
1614 (zero_extend:HI (match_dup 2)))))]
1618 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1619 return \"divxu.b\\t%X2,%T0\";
1621 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1623 [(set_attr "length" "4")])
1625 (define_insn "divmodqi4"
1626 [(set (match_operand:QI 0 "register_operand" "=r")
1629 (match_operand:HI 1 "register_operand" "0")
1630 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1631 (set (match_operand:QI 3 "register_operand" "=r")
1635 (sign_extend:HI (match_dup 2)))))]
1636 "TARGET_H8300H || TARGET_H8300S"
1639 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1640 return \"divxs.b\\t%X2,%T0\";
1642 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1644 [(set_attr "length" "6")])
1646 (define_insn "udivmodhi4"
1647 [(set (match_operand:HI 0 "register_operand" "=r")
1650 (match_operand:SI 1 "register_operand" "0")
1651 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1652 (set (match_operand:HI 3 "register_operand" "=r")
1656 (zero_extend:SI (match_dup 2)))))]
1657 "TARGET_H8300H || TARGET_H8300S"
1660 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1661 return \"divxu.w\\t%T2,%S0\";
1663 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1665 [(set_attr "length" "4")])
1667 (define_insn "divmodhi4"
1668 [(set (match_operand:HI 0 "register_operand" "=r")
1671 (match_operand:SI 1 "register_operand" "0")
1672 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1673 (set (match_operand:HI 3 "register_operand" "=r")
1677 (sign_extend:SI (match_dup 2)))))]
1678 "TARGET_H8300H || TARGET_H8300S"
1681 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1682 return \"divxs.w\\t%T2,%S0\";
1684 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1686 [(set_attr "length" "6")])
1688 ;; ----------------------------------------------------------------------
1690 ;; ----------------------------------------------------------------------
1691 (define_insn "bclrqi_msx"
1692 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1693 (and:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1694 (match_operand:QI 2 "single_zero_operand" "Y0")))]
1696 && rtx_equal_p(operands[0], operands[1])"
1698 [(set_attr "length" "8")])
1701 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=U")
1702 (and:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1703 (match_operand:HI 2 "single_zero_operand" "Y0")))]
1706 (and:QI (match_dup 1)
1709 if (abs (INTVAL (operands[2])) > 0xFF)
1711 operands[0] = adjust_address (operands[0], QImode, 0);
1712 operands[1] = adjust_address (operands[1], QImode, 0);
1713 operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
1717 operands[0] = adjust_address (operands[0], QImode, 1);
1718 operands[1] = adjust_address (operands[1], QImode, 1);
1722 (define_insn "bclrhi_msx"
1723 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1724 (and:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1725 (match_operand:HI 2 "single_zero_operand" "Y0")))]
1728 [(set_attr "length" "8")])
1730 (define_insn "*andqi3_2"
1731 [(set (match_operand:QI 0 "bit_operand" "=U,rQ,r")
1732 (and:QI (match_operand:QI 1 "bit_operand" "%0,0,WU")
1733 (match_operand:QI 2 "h8300_src_operand" "Y0,rQi,IP1>X")))]
1739 [(set_attr "length" "8,*,8")
1740 (set_attr "length_table" "*,logicb,*")
1741 (set_attr "cc" "none_0hit,set_znv,none_0hit")])
1743 (define_insn "andqi3_1"
1744 [(set (match_operand:QI 0 "bit_operand" "=U,r")
1745 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1746 (match_operand:QI 2 "h8300_src_operand" "Y0,rn")))]
1747 "register_operand (operands[0], QImode)
1748 || single_zero_operand (operands[2], QImode)"
1752 [(set_attr "length" "2,8")
1753 (set_attr "cc" "none_0hit,set_znv")])
1755 (define_expand "andqi3"
1756 [(set (match_operand:QI 0 "register_operand" "")
1757 (and:QI (match_operand:QI 1 "register_operand" "")
1758 (match_operand:QI 2 "h8300_src_operand" "")))]
1762 (define_expand "andhi3"
1763 [(set (match_operand:HI 0 "register_operand" "")
1764 (and:HI (match_operand:HI 1 "register_operand" "")
1765 (match_operand:HI 2 "h8300_src_operand" "")))]
1769 (define_insn "*andorqi3"
1770 [(set (match_operand:QI 0 "register_operand" "=r")
1771 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1772 (match_operand:QI 3 "single_one_operand" "n"))
1773 (match_operand:QI 1 "register_operand" "0")))]
1775 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1776 [(set_attr "length" "6")])
1778 (define_insn "*andorhi3"
1779 [(set (match_operand:HI 0 "register_operand" "=r")
1780 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1781 (match_operand:HI 3 "single_one_operand" "n"))
1782 (match_operand:HI 1 "register_operand" "0")))]
1786 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1787 if (INTVAL (operands[3]) > 128)
1789 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1790 return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\";
1792 return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\";
1794 [(set_attr "length" "6")])
1796 (define_insn "*andorsi3"
1797 [(set (match_operand:SI 0 "register_operand" "=r")
1798 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1799 (match_operand:SI 3 "single_one_operand" "n"))
1800 (match_operand:SI 1 "register_operand" "0")))]
1801 "(INTVAL (operands[3]) & 0xffff) != 0"
1804 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1805 if (INTVAL (operands[3]) > 128)
1807 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1808 return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\";
1810 return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\";
1812 [(set_attr "length" "6")])
1814 (define_insn "*andorsi3_shift_8"
1815 [(set (match_operand:SI 0 "register_operand" "=r")
1816 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1819 (match_operand:SI 1 "register_operand" "0")))]
1822 [(set_attr "length" "2")])
1824 (define_expand "andsi3"
1825 [(set (match_operand:SI 0 "register_operand" "")
1826 (and:SI (match_operand:SI 1 "register_operand" "")
1827 (match_operand:SI 2 "h8300_src_operand" "")))]
1831 ;; ----------------------------------------------------------------------
1833 ;; ----------------------------------------------------------------------
1835 (define_insn "bsetqi_msx"
1836 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1837 (ior:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1838 (match_operand:QI 2 "single_one_operand" "Y2")))]
1840 && rtx_equal_p(operands[0], operands[1])"
1842 [(set_attr "length" "8")])
1845 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=U")
1846 (ior:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1847 (match_operand:HI 2 "single_one_operand" "Y2")))]
1850 (ior:QI (match_dup 1)
1853 if (abs (INTVAL (operands[2])) > 0xFF)
1855 operands[0] = adjust_address (operands[0], QImode, 0);
1856 operands[1] = adjust_address (operands[1], QImode, 0);
1857 operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
1861 operands[0] = adjust_address (operands[0], QImode, 1);
1862 operands[1] = adjust_address (operands[1], QImode, 1);
1866 (define_insn "bsethi_msx"
1867 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1868 (ior:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1869 (match_operand:HI 2 "single_one_operand" "Y2")))]
1872 [(set_attr "length" "8")])
1874 (define_insn "iorqi3_1"
1875 [(set (match_operand:QI 0 "bit_operand" "=U,rQ")
1876 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1877 (match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))]
1878 "TARGET_H8300SX || register_operand (operands[0], QImode)
1879 || single_one_operand (operands[2], QImode)"
1883 [(set_attr "length" "8,*")
1884 (set_attr "length_table" "*,logicb")
1885 (set_attr "cc" "none_0hit,set_znv")])
1888 (define_expand "iorqi3"
1889 [(set (match_operand:QI 0 "register_operand" "")
1890 (ior:QI (match_operand:QI 1 "register_operand" "")
1891 (match_operand:QI 2 "h8300_src_operand" "")))]
1895 (define_expand "iorhi3"
1896 [(set (match_operand:HI 0 "register_operand" "")
1897 (ior:HI (match_operand:HI 1 "register_operand" "")
1898 (match_operand:HI 2 "h8300_src_operand" "")))]
1902 (define_expand "iorsi3"
1903 [(set (match_operand:SI 0 "register_operand" "")
1904 (ior:SI (match_operand:SI 1 "register_operand" "")
1905 (match_operand:SI 2 "h8300_src_operand" "")))]
1909 ;; ----------------------------------------------------------------------
1911 ;; ----------------------------------------------------------------------
1912 (define_insn "bnotqi_msx"
1913 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1914 (xor:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1915 (match_operand:QI 2 "single_one_operand" "Y2")))]
1917 && rtx_equal_p(operands[0], operands[1])"
1919 [(set_attr "length" "8")])
1922 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=U")
1923 (xor:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1924 (match_operand:HI 2 "single_one_operand" "Y2")))]
1927 (xor:QI (match_dup 1)
1930 if (abs (INTVAL (operands[2])) > 0xFF)
1932 operands[0] = adjust_address (operands[0], QImode, 0);
1933 operands[1] = adjust_address (operands[1], QImode, 0);
1934 operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
1938 operands[0] = adjust_address (operands[0], QImode, 1);
1939 operands[1] = adjust_address (operands[1], QImode, 1);
1943 (define_insn "bnothi_msx"
1944 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1945 (xor:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1946 (match_operand:HI 2 "single_one_operand" "Y2")))]
1949 [(set_attr "length" "8")])
1951 (define_insn "xorqi3_1"
1952 [(set (match_operand:QI 0 "bit_operand" "=U,r")
1953 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1954 (match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))]
1955 "TARGET_H8300SX || register_operand (operands[0], QImode)
1956 || single_one_operand (operands[2], QImode)"
1960 [(set_attr "length" "8,*")
1961 (set_attr "length_table" "*,logicb")
1962 (set_attr "cc" "none_0hit,set_znv")])
1965 (define_expand "xorqi3"
1966 [(set (match_operand:QI 0 "register_operand" "")
1967 (xor:QI (match_operand:QI 1 "register_operand" "")
1968 (match_operand:QI 2 "h8300_src_operand" "")))]
1972 (define_expand "xorhi3"
1973 [(set (match_operand:HI 0 "register_operand" "")
1974 (xor:HI (match_operand:HI 1 "register_operand" "")
1975 (match_operand:HI 2 "h8300_src_operand" "")))]
1979 (define_expand "xorsi3"
1980 [(set (match_operand:SI 0 "register_operand" "")
1981 (xor:SI (match_operand:SI 1 "register_operand" "")
1982 (match_operand:SI 2 "h8300_src_operand" "")))]
1986 ;; ----------------------------------------------------------------------
1987 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1988 ;; ----------------------------------------------------------------------
1990 ;; We need a separate pattern here because machines other than the
1991 ;; original H8300 don't have to split the 16-bit operand into a pair
1992 ;; of high/low instructions, so we can accept literal addresses, that
1993 ;; have to be loaded into a register on H8300.
1994 (define_insn "*logicalhi3_sn"
1995 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
1996 (match_operator:HI 3 "bit_operator"
1997 [(match_operand:HI 1 "h8300_dst_operand" "%0")
1998 (match_operand:HI 2 "h8300_src_operand" "rQi")]))]
1999 "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)"
2000 "* return output_logical_op (HImode, operands);"
2001 [(set (attr "length")
2002 (symbol_ref "compute_logical_op_length (HImode, operands)"))
2004 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
2006 (define_insn "*logicalsi3_sn"
2007 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2008 (match_operator:SI 3 "bit_operator"
2009 [(match_operand:SI 1 "h8300_dst_operand" "%0")
2010 (match_operand:SI 2 "h8300_src_operand" "rQi")]))]
2011 "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)"
2012 "* return output_logical_op (SImode, operands);"
2013 [(set (attr "length")
2014 (symbol_ref "compute_logical_op_length (SImode, operands)"))
2016 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
2018 (define_insn "*logicalhi3"
2019 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2020 (match_operator:HI 3 "bit_operator"
2021 [(match_operand:HI 1 "h8300_dst_operand" "%0")
2022 (match_operand:HI 2 "h8300_src_operand" "rQi")]))]
2023 "h8300_operands_match_p (operands)"
2024 "* return output_logical_op (HImode, operands);"
2025 [(set (attr "length")
2026 (symbol_ref "compute_logical_op_length (HImode, operands)"))
2028 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
2030 (define_insn "*logicalsi3"
2031 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2032 (match_operator:SI 3 "bit_operator"
2033 [(match_operand:SI 1 "h8300_dst_operand" "%0")
2034 (match_operand:SI 2 "h8300_src_operand" "rQi")]))]
2035 "h8300_operands_match_p (operands)"
2036 "* return output_logical_op (SImode, operands);"
2037 [(set (attr "length")
2038 (symbol_ref "compute_logical_op_length (SImode, operands)"))
2040 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
2042 ;; ----------------------------------------------------------------------
2043 ;; NEGATION INSTRUCTIONS
2044 ;; ----------------------------------------------------------------------
2046 (define_expand "negqi2"
2047 [(set (match_operand:QI 0 "register_operand" "")
2048 (neg:QI (match_operand:QI 1 "register_operand" "")))]
2052 (define_insn "*negqi2"
2053 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2054 (neg:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
2057 [(set_attr "length_table" "unary")
2058 (set_attr "cc" "set_zn")])
2060 (define_expand "neghi2"
2061 [(set (match_operand:HI 0 "register_operand" "")
2062 (neg:HI (match_operand:HI 1 "register_operand" "")))]
2068 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
2073 (define_expand "neghi2_h8300"
2075 (not:HI (match_operand:HI 1 "register_operand" "")))
2076 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
2077 (set (match_operand:HI 0 "register_operand" "")
2080 "operands[2] = gen_reg_rtx (HImode);")
2082 (define_insn "*neghi2_h8300hs"
2083 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2084 (neg:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
2085 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2087 [(set_attr "length_table" "unary")
2088 (set_attr "cc" "set_zn")])
2090 (define_expand "negsi2"
2091 [(set (match_operand:SI 0 "register_operand" "")
2092 (neg:SI (match_operand:SI 1 "register_operand" "")))]
2098 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
2103 (define_expand "negsi2_h8300"
2105 (not:SI (match_operand:SI 1 "register_operand" "")))
2106 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
2107 (set (match_operand:SI 0 "register_operand" "")
2110 "operands[2] = gen_reg_rtx (SImode);")
2112 (define_insn "*negsi2_h8300hs"
2113 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2114 (neg:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
2115 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2117 [(set_attr "length_table" "unary")
2118 (set_attr "cc" "set_zn")])
2120 (define_expand "negsf2"
2121 [(set (match_operand:SF 0 "register_operand" "")
2122 (neg:SF (match_operand:SF 1 "register_operand" "")))]
2126 (define_insn "*negsf2_h8300"
2127 [(set (match_operand:SF 0 "register_operand" "=r")
2128 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
2131 [(set_attr "length" "2")])
2133 (define_insn "*negsf2_h8300hs"
2134 [(set (match_operand:SF 0 "register_operand" "=r")
2135 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
2136 "TARGET_H8300H || TARGET_H8300S"
2137 "xor.w\\t#32768,%e0"
2138 [(set_attr "length" "4")])
2140 ;; ----------------------------------------------------------------------
2141 ;; ABSOLUTE VALUE INSTRUCTIONS
2142 ;; ----------------------------------------------------------------------
2144 (define_expand "abssf2"
2145 [(set (match_operand:SF 0 "register_operand" "")
2146 (abs:SF (match_operand:SF 1 "register_operand" "")))]
2150 (define_insn "*abssf2_h8300"
2151 [(set (match_operand:SF 0 "register_operand" "=r")
2152 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2155 [(set_attr "length" "2")])
2157 (define_insn "*abssf2_h8300hs"
2158 [(set (match_operand:SF 0 "register_operand" "=r")
2159 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2160 "TARGET_H8300H || TARGET_H8300S"
2161 "and.w\\t#32767,%e0"
2162 [(set_attr "length" "4")])
2164 ;; ----------------------------------------------------------------------
2166 ;; ----------------------------------------------------------------------
2168 (define_expand "one_cmplqi2"
2169 [(set (match_operand:QI 0 "register_operand" "")
2170 (not:QI (match_operand:QI 1 "register_operand" "")))]
2174 (define_insn "*one_cmplqi2"
2175 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2176 (not:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
2179 [(set_attr "length_table" "unary")
2180 (set_attr "cc" "set_znv")])
2182 (define_expand "one_cmplhi2"
2183 [(set (match_operand:HI 0 "register_operand" "")
2184 (not:HI (match_operand:HI 1 "register_operand" "")))]
2188 (define_insn "*one_cmplhi2_h8300"
2189 [(set (match_operand:HI 0 "register_operand" "=r")
2190 (not:HI (match_operand:HI 1 "register_operand" "0")))]
2193 [(set_attr "length" "4")])
2195 (define_insn "*one_cmplhi2_h8300hs"
2196 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2197 (not:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
2198 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2200 [(set_attr "cc" "set_znv")
2201 (set_attr "length_table" "unary")])
2203 (define_expand "one_cmplsi2"
2204 [(set (match_operand:SI 0 "register_operand" "")
2205 (not:SI (match_operand:SI 1 "register_operand" "")))]
2209 (define_insn "*one_cmplsi2_h8300"
2210 [(set (match_operand:SI 0 "register_operand" "=r")
2211 (not:SI (match_operand:SI 1 "register_operand" "0")))]
2213 "not %w0\;not %x0\;not %y0\;not %z0"
2214 [(set_attr "length" "8")])
2216 (define_insn "*one_cmplsi2_h8300hs"
2217 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2218 (not:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
2219 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2221 [(set_attr "cc" "set_znv")
2222 (set_attr "length_table" "unary")])
2224 ;; ----------------------------------------------------------------------
2225 ;; JUMP INSTRUCTIONS
2226 ;; ----------------------------------------------------------------------
2228 ;; Conditional jump instructions
2230 (define_expand "cbranchqi4"
2231 [(use (match_operator 0 "ordered_comparison_operator"
2232 [(match_operand:QI 1 "h8300_dst_operand" "")
2233 (match_operand:QI 2 "h8300_src_operand" "")]))
2234 (use (match_operand 3 ""))]
2236 "h8300_expand_branch (operands); DONE;")
2238 (define_expand "cbranchhi4"
2239 [(use (match_operator 0 "ordered_comparison_operator"
2240 [(match_operand:HI 1 "h8300_dst_operand" "")
2241 (match_operand:HI 2 "h8300_src_operand" "")]))
2242 (use (match_operand 3 ""))]
2246 /* Force operand1 into a register if we're compiling
2248 if ((GET_CODE (operands[2]) != REG && operands[2] != const0_rtx)
2250 operands[2] = force_reg (HImode, operands[2]);
2251 h8300_expand_branch (operands); DONE;
2254 (define_expand "cbranchsi4"
2255 [(use (match_operator 0 "ordered_comparison_operator"
2256 [(match_operand:SI 1 "h8300_dst_operand" "")
2257 (match_operand:SI 2 "h8300_src_operand" "")]))
2258 (use (match_operand 3 ""))]
2259 "TARGET_H8300H || TARGET_H8300S"
2260 "h8300_expand_branch (operands); DONE;")
2262 (define_insn "branch_true"
2264 (if_then_else (match_operator 1 "comparison_operator"
2265 [(cc0) (const_int 0)])
2266 (label_ref (match_operand 0 "" ""))
2271 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
2272 && (GET_CODE (operands[1]) == GT
2273 || GET_CODE (operands[1]) == GE
2274 || GET_CODE (operands[1]) == LE
2275 || GET_CODE (operands[1]) == LT))
2277 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
2281 if (get_attr_length (insn) == 2)
2282 return \"b%j1 %l0\";
2283 else if (get_attr_length (insn) == 4)
2284 return \"b%j1 %l0:16\";
2286 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2288 [(set_attr "type" "branch")
2289 (set_attr "cc" "none")])
2291 (define_insn "branch_false"
2293 (if_then_else (match_operator 1 "comparison_operator"
2294 [(cc0) (const_int 0)])
2296 (label_ref (match_operand 0 "" ""))))]
2300 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
2301 && (GET_CODE (operands[1]) == GT
2302 || GET_CODE (operands[1]) == GE
2303 || GET_CODE (operands[1]) == LE
2304 || GET_CODE (operands[1]) == LT))
2306 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
2310 if (get_attr_length (insn) == 2)
2311 return \"b%k1 %l0\";
2312 else if (get_attr_length (insn) == 4)
2313 return \"b%k1 %l0:16\";
2315 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2317 [(set_attr "type" "branch")
2318 (set_attr "cc" "none")])
2320 (define_insn "*brabc"
2323 (eq (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
2325 (match_operand:QI 2 "immediate_operand" "n"))
2327 (label_ref (match_operand 0 "" ""))
2332 switch (get_attr_length (insn)
2333 - h8300_insn_length_from_table (insn, operands))
2336 return \"bra/bc %2,%R1,%l0\";
2339 return \"bra/bc %2,%R1,%l0:16\";
2342 return \"bra/bs %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2345 [(set_attr "type" "bitbranch")
2346 (set_attr "length_table" "bitbranch")
2347 (set_attr "cc" "none")])
2349 (define_insn "*brabs"
2352 (ne (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
2354 (match_operand:QI 2 "immediate_operand" "n"))
2356 (label_ref (match_operand 0 "" ""))
2361 switch (get_attr_length (insn)
2362 - h8300_insn_length_from_table (insn, operands))
2365 return \"bra/bs %2,%R1,%l0\";
2368 return \"bra/bs %2,%R1,%l0:16\";
2371 return \"bra/bc %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2374 [(set_attr "type" "bitbranch")
2375 (set_attr "length_table" "bitbranch")
2376 (set_attr "cc" "none")])
2378 ;; Unconditional and other jump instructions.
2382 (label_ref (match_operand 0 "" "")))]
2386 if (final_sequence != 0)
2388 if (get_attr_length (insn) == 2)
2389 return \"bra/s %l0\";
2392 /* The branch isn't short enough to use bra/s. Output the
2393 branch and delay slot in their normal order.
2395 If this is a backward branch, it will now be branching two
2396 bytes further than previously thought. The length-based
2397 test for bra vs. jump is very conservative though, so the
2398 branch will still be within range. */
2402 vec = XVEC (final_sequence, 0);
2404 final_scan_insn (RTVEC_ELT (vec, 1), asm_out_file, optimize, 1, & seen);
2405 final_scan_insn (RTVEC_ELT (vec, 0), asm_out_file, optimize, 1, & seen);
2406 INSN_DELETED_P (RTVEC_ELT (vec, 1)) = 1;
2410 else if (get_attr_length (insn) == 2)
2412 else if (get_attr_length (insn) == 4)
2413 return \"bra %l0:16\";
2415 return \"jmp @%l0\";
2417 [(set_attr "type" "branch")
2418 (set (attr "delay_slot")
2419 (if_then_else (ne (symbol_ref "TARGET_H8300SX") (const_int 0))
2420 (const_string "jump")
2421 (const_string "none")))
2422 (set_attr "cc" "none")])
2424 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2426 (define_expand "tablejump"
2427 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
2428 (use (label_ref (match_operand 1 "" "")))])]
2432 (define_insn "*tablejump_h8300"
2433 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2434 (use (label_ref (match_operand 1 "" "")))]
2437 [(set_attr "cc" "none")
2438 (set_attr "length" "2")])
2440 (define_insn "*tablejump_h8300hs_advanced"
2441 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
2442 (use (label_ref (match_operand 1 "" "")))]
2443 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2445 [(set_attr "cc" "none")
2446 (set_attr "length" "2")])
2448 (define_insn "*tablejump_h8300hs_normal"
2449 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2450 (use (label_ref (match_operand 1 "" "")))]
2451 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2453 [(set_attr "cc" "none")
2454 (set_attr "length" "2")])
2456 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2458 (define_expand "indirect_jump"
2459 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
2463 (define_insn "*indirect_jump_h8300"
2464 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2467 [(set_attr "cc" "none")
2468 (set_attr "length" "2")])
2470 (define_insn "*indirect_jump_h8300hs_advanced"
2471 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
2472 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2474 [(set_attr "cc" "none")
2475 (set_attr "length" "2")])
2477 (define_insn "*indirect_jump_h8300hs_normal"
2478 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2479 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2481 [(set_attr "cc" "none")
2482 (set_attr "length" "2")])
2484 ;; Call subroutine with no return value.
2486 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2489 [(call (match_operand:QI 0 "call_insn_operand" "or")
2490 (match_operand:HI 1 "general_operand" "g"))]
2494 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
2495 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
2496 return \"jsr\\t@%0:8\";
2498 return \"jsr\\t%0\";
2500 [(set_attr "type" "call")
2501 (set (attr "length")
2502 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2506 ;; Call subroutine, returning value in operand 0
2507 ;; (which must be a hard register).
2509 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2511 (define_insn "call_value"
2512 [(set (match_operand 0 "" "=r")
2513 (call (match_operand:QI 1 "call_insn_operand" "or")
2514 (match_operand:HI 2 "general_operand" "g")))]
2518 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2519 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
2520 return \"jsr\\t@%1:8\";
2522 return \"jsr\\t%1\";
2524 [(set_attr "type" "call")
2525 (set (attr "length")
2526 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2534 [(set_attr "cc" "none")
2535 (set_attr "length" "2")])
2537 ;; ----------------------------------------------------------------------
2538 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
2539 ;; ----------------------------------------------------------------------
2541 (define_expand "push_h8300"
2542 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
2543 (match_operand:HI 0 "register_operand" ""))]
2547 (define_expand "push_h8300hs_advanced"
2548 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2549 (match_operand:SI 0 "register_operand" ""))]
2550 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2553 (define_expand "push_h8300hs_normal"
2554 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
2555 (match_operand:SI 0 "register_operand" ""))]
2556 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2559 (define_expand "pop_h8300"
2560 [(set (match_operand:HI 0 "register_operand" "")
2561 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
2565 (define_expand "pop_h8300hs_advanced"
2566 [(set (match_operand:SI 0 "register_operand" "")
2567 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
2568 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2571 (define_expand "pop_h8300hs_normal"
2572 [(set (match_operand:SI 0 "register_operand" "")
2573 (mem:SI (post_inc:HI (reg:HI SP_REG))))]
2574 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2577 (define_insn "ldm_h8300sx"
2578 [(match_parallel 0 "h8300_ldm_parallel"
2579 [(set (match_operand:SI 1 "register_operand" "")
2580 (match_operand:SI 2 "memory_operand" ""))])]
2583 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2584 XVECLEN (operands[0], 0) - 2));
2585 return "ldm.l\t@er7+,%S1-%S3";
2587 [(set_attr "cc" "none")
2588 (set_attr "length" "4")])
2590 (define_insn "stm_h8300sx"
2591 [(match_parallel 0 "h8300_stm_parallel"
2592 [(set (match_operand:SI 1 "memory_operand" "")
2593 (match_operand:SI 2 "register_operand" ""))])]
2596 operands[3] = SET_SRC (XVECEXP (operands[0], 0,
2597 XVECLEN (operands[0], 0) - 2));
2598 return "stm.l\t%S2-%S3,@-er7";
2600 [(set_attr "cc" "none")
2601 (set_attr "length" "4")])
2603 (define_insn "return_h8sx"
2604 [(match_parallel 0 "h8300_return_parallel"
2606 (set (match_operand:SI 1 "register_operand" "")
2607 (match_operand:SI 2 "memory_operand" ""))])]
2610 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2611 XVECLEN (operands[0], 0) - 2));
2612 if (h8300_current_function_interrupt_function_p ())
2613 return "rte/l\t%S1-%S3";
2615 return "rts/l\t%S1-%S3";
2617 [(set_attr "cc" "none")
2618 (set_attr "can_delay" "no")
2619 (set_attr "length" "2")])
2621 (define_expand "return"
2623 "h8300_can_use_return_insn_p ()"
2626 (define_insn "*return_1"
2631 if (h8300_current_function_interrupt_function_p ())
2636 [(set_attr "cc" "none")
2637 (set_attr "can_delay" "no")
2638 (set_attr "length" "2")])
2640 (define_expand "prologue"
2643 "h8300_expand_prologue (); DONE;")
2645 (define_expand "epilogue"
2648 "h8300_expand_epilogue (); DONE;")
2650 (define_insn "monitor_prologue"
2651 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2656 return \"subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr\";
2657 else if (TARGET_H8300H)
2658 return \"mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr\";
2659 else if (TARGET_H8300S)
2660 return \"stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\";
2663 [(set_attr "length" "20")])
2665 ;; ----------------------------------------------------------------------
2666 ;; EXTEND INSTRUCTIONS
2667 ;; ----------------------------------------------------------------------
2669 (define_expand "zero_extendqihi2"
2670 [(set (match_operand:HI 0 "register_operand" "")
2671 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2675 (define_insn "*zero_extendqihi2_h8300"
2676 [(set (match_operand:HI 0 "register_operand" "=r,r")
2677 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2682 [(set_attr "length" "2,10")])
2684 (define_insn "*zero_extendqihi2_h8300hs"
2685 [(set (match_operand:HI 0 "register_operand" "=r,r")
2686 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2687 "TARGET_H8300H || TARGET_H8300S"
2691 [(set_attr "length" "2,10")
2692 (set_attr "cc" "set_znv,set_znv")])
2694 ;; Split the zero extension of a general operand (actually a memory
2695 ;; operand) into a load of the operand and the actual zero extension
2696 ;; so that 1) the length will be accurate, and 2) the zero extensions
2697 ;; appearing at the end of basic blocks may be merged.
2700 [(set (match_operand:HI 0 "register_operand" "")
2701 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2706 (zero_extend:HI (match_dup 2)))]
2707 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2709 (define_expand "zero_extendqisi2"
2710 [(set (match_operand:SI 0 "register_operand" "")
2711 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2715 operands[1] = force_reg (QImode, operands[1]);
2718 (define_insn "*zero_extendqisi2_h8300"
2719 [(set (match_operand:SI 0 "register_operand" "=r,r")
2720 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2723 mov.b #0,%x0\;sub.w %e0,%e0
2724 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
2725 [(set_attr "length" "4,8")])
2727 (define_insn "*zero_extendqisi2_h8300hs"
2728 [(set (match_operand:SI 0 "register_operand" "=r,r")
2729 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2730 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2734 [(set (match_operand:SI 0 "register_operand" "")
2735 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2736 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2737 && reg_overlap_mentioned_p (operands[0], operands[1])
2738 && reload_completed"
2742 (zero_extend:HI (match_dup 2)))
2744 (zero_extend:SI (match_dup 3)))]
2745 "operands[2] = gen_lowpart (QImode, operands[0]);
2746 operands[3] = gen_lowpart (HImode, operands[0]);")
2749 [(set (match_operand:SI 0 "register_operand" "")
2750 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2751 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2752 && !reg_overlap_mentioned_p (operands[0], operands[1])
2753 && reload_completed"
2756 (set (strict_low_part (match_dup 2))
2758 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2760 (define_insn "*zero_extendqisi2_h8sx"
2761 [(set (match_operand:SI 0 "register_operand" "=r")
2762 (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2765 [(set_attr "length" "2")
2766 (set_attr "cc" "set_znv")])
2768 (define_expand "zero_extendhisi2"
2769 [(set (match_operand:SI 0 "register_operand" "")
2770 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2774 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
2775 (define_insn "*zero_extendhisi2_h8300"
2776 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2777 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
2781 mov.w %f1,%f0\;sub.w %e0,%e0
2782 mov.w %e1,%f0\;sub.w %e0,%e0"
2783 [(set_attr "length" "2,4,6")])
2785 (define_insn "*zero_extendhisi2_h8300hs"
2786 [(set (match_operand:SI 0 "register_operand" "=r")
2787 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2788 "TARGET_H8300H || TARGET_H8300S"
2790 [(set_attr "length" "2")
2791 (set_attr "cc" "set_znv")])
2793 (define_expand "extendqihi2"
2794 [(set (match_operand:HI 0 "register_operand" "")
2795 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
2799 (define_insn "*extendqihi2_h8300"
2800 [(set (match_operand:HI 0 "register_operand" "=r,r")
2801 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2804 bld #7,%s0\;subx %t0,%t0
2805 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
2806 [(set_attr "length" "4,8")])
2808 (define_insn "*extendqihi2_h8300hs"
2809 [(set (match_operand:HI 0 "register_operand" "=r")
2810 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
2811 "TARGET_H8300H || TARGET_H8300S"
2813 [(set_attr "length" "2")
2814 (set_attr "cc" "set_znv")])
2816 (define_expand "extendqisi2"
2817 [(set (match_operand:SI 0 "register_operand" "")
2818 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2822 (define_insn "*extendqisi2_h8300"
2823 [(set (match_operand:SI 0 "register_operand" "=r,r")
2824 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2827 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
2828 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
2829 [(set_attr "length" "8,12")])
2831 ;; The following pattern is needed because without the pattern, the
2832 ;; combiner would split (sign_extend:SI (reg:QI)) into two 24-bit
2833 ;; shifts, one ashift and one ashiftrt.
2835 (define_insn_and_split "*extendqisi2_h8300hs"
2836 [(set (match_operand:SI 0 "register_operand" "=r")
2837 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2838 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2840 "&& reload_completed"
2842 (sign_extend:HI (match_dup 1)))
2844 (sign_extend:SI (match_dup 2)))]
2845 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2847 (define_insn "*extendqisi2_h8sx"
2848 [(set (match_operand:SI 0 "register_operand" "=r")
2849 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2852 [(set_attr "length" "2")
2853 (set_attr "cc" "set_znv")])
2855 (define_expand "extendhisi2"
2856 [(set (match_operand:SI 0 "register_operand" "")
2857 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2861 (define_insn "*extendhisi2_h8300"
2862 [(set (match_operand:SI 0 "register_operand" "=r,r")
2863 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
2866 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
2867 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
2868 [(set_attr "length" "6,10")])
2870 (define_insn "*extendhisi2_h8300hs"
2871 [(set (match_operand:SI 0 "register_operand" "=r")
2872 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2873 "TARGET_H8300H || TARGET_H8300S"
2875 [(set_attr "length" "2")
2876 (set_attr "cc" "set_znv")])
2878 ;; ----------------------------------------------------------------------
2880 ;; ----------------------------------------------------------------------
2882 ;; We make some attempt to provide real efficient shifting. One example is
2883 ;; doing an 8-bit shift of a 16-bit value by moving a byte reg into the other
2884 ;; reg and moving 0 into the former reg.
2886 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2887 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2888 ;; give the optimizer more cracks at the code. However, we wish to do things
2889 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
2890 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
2891 ;; 16-bit rotates. Also, if we emit complicated rtl, combine may not be able
2892 ;; to detect cases it can optimize.
2894 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2895 ;; easier "do it at insn emit time" route.
2899 (define_expand "ashlqi3"
2900 [(set (match_operand:QI 0 "register_operand" "")
2901 (ashift:QI (match_operand:QI 1 "register_operand" "")
2902 (match_operand:QI 2 "nonmemory_operand" "")))]
2904 "if (expand_a_shift (QImode, ASHIFT, operands)) DONE;")
2906 (define_expand "ashrqi3"
2907 [(set (match_operand:QI 0 "register_operand" "")
2908 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2909 (match_operand:QI 2 "nonmemory_operand" "")))]
2911 "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE;")
2913 (define_expand "lshrqi3"
2914 [(set (match_operand:QI 0 "register_operand" "")
2915 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2916 (match_operand:QI 2 "nonmemory_operand" "")))]
2918 "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE;")
2921 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2922 (match_operator:QI 3 "h8sx_unary_shift_operator"
2923 [(match_operand:QI 1 "h8300_dst_operand" "0")
2924 (match_operand:QI 2 "const_int_operand" "")]))]
2925 "h8300_operands_match_p (operands)"
2926 { return output_h8sx_shift (operands, 'b', 'X'); }
2927 [(set_attr "length_table" "unary")
2928 (set_attr "cc" "set_znv")])
2931 [(set (match_operand:QI 0 "register_operand" "=r")
2932 (match_operator:QI 3 "h8sx_binary_shift_operator"
2933 [(match_operand:QI 1 "register_operand" "0")
2934 (match_operand:QI 2 "nonmemory_operand" "r P3>X")]))]
2936 { return output_h8sx_shift (operands, 'b', 'X'); }
2937 [(set_attr "length" "4")
2938 (set_attr "cc" "set_znv")])
2940 (define_insn "*shiftqi"
2941 [(set (match_operand:QI 0 "register_operand" "=r,r")
2942 (match_operator:QI 3 "nshift_operator"
2943 [ (match_operand:QI 1 "register_operand" "0,0")
2944 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2945 (clobber (match_scratch:QI 4 "=X,&r"))]
2947 "* return output_a_shift (operands);"
2948 [(set (attr "length")
2949 (symbol_ref "compute_a_shift_length (insn, operands)"))
2951 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2955 (define_expand "ashlhi3"
2956 [(set (match_operand:HI 0 "register_operand" "")
2957 (ashift:HI (match_operand:HI 1 "register_operand" "")
2958 (match_operand:QI 2 "nonmemory_operand" "")))]
2960 "if (expand_a_shift (HImode, ASHIFT, operands)) DONE;")
2962 (define_expand "lshrhi3"
2963 [(set (match_operand:HI 0 "register_operand" "")
2964 (lshiftrt:HI (match_operand:HI 1 "register_operand" "")
2965 (match_operand:QI 2 "nonmemory_operand" "")))]
2967 "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE;")
2969 (define_expand "ashrhi3"
2970 [(set (match_operand:HI 0 "register_operand" "")
2971 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
2972 (match_operand:QI 2 "nonmemory_operand" "")))]
2974 "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE;")
2977 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2978 (match_operator:HI 3 "h8sx_unary_shift_operator"
2979 [(match_operand:HI 1 "h8300_dst_operand" "0")
2980 (match_operand:QI 2 "const_int_operand" "")]))]
2981 "h8300_operands_match_p (operands)"
2982 { return output_h8sx_shift (operands, 'w', 'T'); }
2983 [(set_attr "length_table" "unary")
2984 (set_attr "cc" "set_znv")])
2987 [(set (match_operand:HI 0 "register_operand" "=r")
2988 (match_operator:HI 3 "h8sx_binary_shift_operator"
2989 [(match_operand:HI 1 "register_operand" "0")
2990 (match_operand:QI 2 "nonmemory_operand" "r P4>X")]))]
2992 { return output_h8sx_shift (operands, 'w', 'T'); }
2993 [(set_attr "length" "4")
2994 (set_attr "cc" "set_znv")])
2996 (define_insn "*shifthi"
2997 [(set (match_operand:HI 0 "register_operand" "=r,r")
2998 (match_operator:HI 3 "nshift_operator"
2999 [ (match_operand:HI 1 "register_operand" "0,0")
3000 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
3001 (clobber (match_scratch:QI 4 "=X,&r"))]
3003 "* return output_a_shift (operands);"
3004 [(set (attr "length")
3005 (symbol_ref "compute_a_shift_length (insn, operands)"))
3007 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
3011 (define_expand "ashlsi3"
3012 [(set (match_operand:SI 0 "register_operand" "")
3013 (ashift:SI (match_operand:SI 1 "register_operand" "")
3014 (match_operand:QI 2 "nonmemory_operand" "")))]
3016 "if (expand_a_shift (SImode, ASHIFT, operands)) DONE;")
3018 (define_expand "lshrsi3"
3019 [(set (match_operand:SI 0 "register_operand" "")
3020 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
3021 (match_operand:QI 2 "nonmemory_operand" "")))]
3023 "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE;")
3025 (define_expand "ashrsi3"
3026 [(set (match_operand:SI 0 "register_operand" "")
3027 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
3028 (match_operand:QI 2 "nonmemory_operand" "")))]
3030 "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE;")
3033 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
3034 (match_operator:SI 3 "h8sx_unary_shift_operator"
3035 [(match_operand:SI 1 "h8300_dst_operand" "0")
3036 (match_operand:QI 2 "const_int_operand" "")]))]
3037 "h8300_operands_match_p (operands)"
3038 { return output_h8sx_shift (operands, 'l', 'S'); }
3039 [(set_attr "length_table" "unary")
3040 (set_attr "cc" "set_znv")])
3043 [(set (match_operand:SI 0 "register_operand" "=r")
3044 (match_operator:SI 3 "h8sx_binary_shift_operator"
3045 [(match_operand:SI 1 "register_operand" "0")
3046 (match_operand:QI 2 "nonmemory_operand" "r P5>X")]))]
3048 { return output_h8sx_shift (operands, 'l', 'S'); }
3049 [(set_attr "length" "4")
3050 (set_attr "cc" "set_znv")])
3052 (define_insn "*shiftsi"
3053 [(set (match_operand:SI 0 "register_operand" "=r,r")
3054 (match_operator:SI 3 "nshift_operator"
3055 [ (match_operand:SI 1 "register_operand" "0,0")
3056 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
3057 (clobber (match_scratch:QI 4 "=X,&r"))]
3059 "* return output_a_shift (operands);"
3060 [(set (attr "length")
3061 (symbol_ref "compute_a_shift_length (insn, operands)"))
3063 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
3065 ;; Split a variable shift into a loop. If the register containing
3066 ;; the shift count dies, then we just use that register.
3069 [(set (match_operand 0 "register_operand" "")
3070 (match_operator 2 "nshift_operator"
3072 (match_operand:QI 1 "register_operand" "")]))
3073 (clobber (match_operand:QI 3 "register_operand" ""))]
3075 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
3076 [(set (cc0) (compare (match_dup 1)
3079 (if_then_else (le (cc0) (const_int 0))
3080 (label_ref (match_dup 5))
3085 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
3086 (clobber (scratch:QI))])
3088 (plus:QI (match_dup 1) (const_int -1)))
3089 (set (cc0) (compare (match_dup 1)
3092 (if_then_else (ne (cc0) (const_int 0))
3093 (label_ref (match_dup 4))
3096 "operands[4] = gen_label_rtx ();
3097 operands[5] = gen_label_rtx ();")
3100 [(set (match_operand 0 "register_operand" "")
3101 (match_operator 2 "nshift_operator"
3103 (match_operand:QI 1 "register_operand" "")]))
3104 (clobber (match_operand:QI 3 "register_operand" ""))]
3106 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
3109 (set (cc0) (compare (match_dup 3)
3112 (if_then_else (le (cc0) (const_int 0))
3113 (label_ref (match_dup 5))
3118 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
3119 (clobber (scratch:QI))])
3121 (plus:QI (match_dup 3) (const_int -1)))
3122 (set (cc0) (compare (match_dup 3)
3125 (if_then_else (ne (cc0) (const_int 0))
3126 (label_ref (match_dup 4))
3129 "operands[4] = gen_label_rtx ();
3130 operands[5] = gen_label_rtx ();")
3132 ;; ----------------------------------------------------------------------
3134 ;; ----------------------------------------------------------------------
3136 (define_expand "rotlqi3"
3137 [(set (match_operand:QI 0 "register_operand" "")
3138 (rotate:QI (match_operand:QI 1 "register_operand" "")
3139 (match_operand:QI 2 "nonmemory_operand" "")))]
3141 "if (expand_a_rotate (operands)) DONE;")
3143 (define_insn "rotlqi3_1"
3144 [(set (match_operand:QI 0 "register_operand" "=r")
3145 (rotate:QI (match_operand:QI 1 "register_operand" "0")
3146 (match_operand:QI 2 "immediate_operand" "")))]
3148 "* return output_a_rotate (ROTATE, operands);"
3149 [(set (attr "length")
3150 (symbol_ref "compute_a_rotate_length (operands)"))])
3152 (define_expand "rotlhi3"
3153 [(set (match_operand:HI 0 "register_operand" "")
3154 (rotate:HI (match_operand:HI 1 "register_operand" "")
3155 (match_operand:QI 2 "nonmemory_operand" "")))]
3157 "if (expand_a_rotate (operands)) DONE;")
3159 (define_insn "rotlhi3_1"
3160 [(set (match_operand:HI 0 "register_operand" "=r")
3161 (rotate:HI (match_operand:HI 1 "register_operand" "0")
3162 (match_operand:QI 2 "immediate_operand" "")))]
3164 "* return output_a_rotate (ROTATE, operands);"
3165 [(set (attr "length")
3166 (symbol_ref "compute_a_rotate_length (operands)"))])
3168 (define_expand "rotlsi3"
3169 [(set (match_operand:SI 0 "register_operand" "")
3170 (rotate:SI (match_operand:SI 1 "register_operand" "")
3171 (match_operand:QI 2 "nonmemory_operand" "")))]
3172 "TARGET_H8300H || TARGET_H8300S"
3173 "if (expand_a_rotate (operands)) DONE;")
3175 (define_insn "rotlsi3_1"
3176 [(set (match_operand:SI 0 "register_operand" "=r")
3177 (rotate:SI (match_operand:SI 1 "register_operand" "0")
3178 (match_operand:QI 2 "immediate_operand" "")))]
3179 "TARGET_H8300H || TARGET_H8300S"
3180 "* return output_a_rotate (ROTATE, operands);"
3181 [(set (attr "length")
3182 (symbol_ref "compute_a_rotate_length (operands)"))])
3184 ;; -----------------------------------------------------------------
3186 ;; -----------------------------------------------------------------
3187 ;; The H8/300 has given 1/8th of its opcode space to bitfield
3188 ;; instructions so let's use them as well as we can.
3190 ;; You'll never believe all these patterns perform one basic action --
3191 ;; load a bit from the source, optionally invert the bit, then store it
3192 ;; in the destination (which is known to be zero).
3194 ;; Combine obviously need some work to better identify this situation and
3195 ;; canonicalize the form better.
3198 ;; Normal loads with a 16bit destination.
3202 [(set (match_operand:HI 0 "register_operand" "=&r")
3203 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3205 (match_operand:HI 2 "immediate_operand" "n")))]
3207 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
3208 [(set_attr "length" "6")])
3211 ;; Inverted loads with a 16bit destination.
3215 [(set (match_operand:HI 0 "register_operand" "=&r")
3216 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
3217 (match_operand:HI 3 "const_int_operand" "n"))
3219 (match_operand:HI 2 "const_int_operand" "n")))]
3220 "(TARGET_H8300 || TARGET_H8300SX)
3221 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3222 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
3223 [(set_attr "length" "8")])
3226 ;; Normal loads with a 32bit destination.
3229 (define_insn "*extzv_1_r_h8300"
3230 [(set (match_operand:SI 0 "register_operand" "=&r")
3231 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
3233 (match_operand 2 "const_int_operand" "n")))]
3235 && INTVAL (operands[2]) < 16"
3236 "* return output_simode_bld (0, operands);"
3237 [(set_attr "length" "8")])
3239 (define_insn "*extzv_1_r_h8300hs"
3240 [(set (match_operand:SI 0 "register_operand" "=r,r")
3241 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
3243 (match_operand 2 "const_int_operand" "n,n")))]
3244 "(TARGET_H8300H || TARGET_H8300S)
3245 && INTVAL (operands[2]) < 16"
3246 "* return output_simode_bld (0, operands);"
3247 [(set_attr "cc" "set_znv,set_znv")
3248 (set_attr "length" "8,6")])
3251 ;; Inverted loads with a 32bit destination.
3254 (define_insn "*extzv_1_r_inv_h8300"
3255 [(set (match_operand:SI 0 "register_operand" "=&r")
3256 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
3257 (match_operand:HI 3 "const_int_operand" "n"))
3259 (match_operand 2 "const_int_operand" "n")))]
3261 && INTVAL (operands[2]) < 16
3262 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3263 "* return output_simode_bld (1, operands);"
3264 [(set_attr "length" "8")])
3266 (define_insn "*extzv_1_r_inv_h8300hs"
3267 [(set (match_operand:SI 0 "register_operand" "=r,r")
3268 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
3269 (match_operand 3 "const_int_operand" "n,n"))
3271 (match_operand 2 "const_int_operand" "n,n")))]
3272 "(TARGET_H8300H || TARGET_H8300S)
3273 && INTVAL (operands[2]) < 16
3274 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3275 "* return output_simode_bld (1, operands);"
3276 [(set_attr "cc" "set_znv,set_znv")
3277 (set_attr "length" "8,6")])
3279 (define_expand "insv"
3280 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
3281 (match_operand:HI 1 "general_operand" "")
3282 (match_operand:HI 2 "general_operand" ""))
3283 (match_operand:HI 3 "general_operand" ""))]
3284 "TARGET_H8300 || TARGET_H8300SX"
3289 if (GET_CODE (operands[1]) == CONST_INT
3290 && GET_CODE (operands[2]) == CONST_INT
3291 && INTVAL (operands[1]) <= 8
3292 && INTVAL (operands[2]) >= 0
3293 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8
3294 && memory_operand (operands[0], GET_MODE (operands[0])))
3296 /* If the source operand is zero, it's better to use AND rather
3297 than BFST. Likewise OR if the operand is all ones. */
3298 if (GET_CODE (operands[3]) == CONST_INT)
3300 HOST_WIDE_INT mask = (1 << INTVAL (operands[1])) - 1;
3301 if ((INTVAL (operands[3]) & mask) == 0)
3303 if ((INTVAL (operands[3]) & mask) == mask)
3306 if (! bit_memory_operand (operands[0], GET_MODE (operands[0])))
3308 if (!can_create_pseudo_p ())
3311 replace_equiv_address (operands[0],
3313 XEXP (operands[0], 0)));
3315 operands[3] = gen_lowpart (QImode, operands[3]);
3318 if (! register_operand (operands[3], QImode))
3320 if (!can_create_pseudo_p ())
3322 operands[3] = force_reg (QImode, operands[3]);
3324 emit_insn (gen_bfst (adjust_address (operands[0], QImode, 0),
3325 operands[3], operands[1], operands[2]));
3332 /* We only have single bit bit-field instructions. */
3333 if (INTVAL (operands[1]) != 1)
3336 /* For now, we don't allow memory operands. */
3337 if (GET_CODE (operands[0]) == MEM
3338 || GET_CODE (operands[3]) == MEM)
3341 if (GET_CODE (operands[3]) != REG)
3342 operands[3] = force_reg (HImode, operands[3]);
3346 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
3348 (match_operand:HI 1 "immediate_operand" "n"))
3349 (match_operand:HI 2 "register_operand" "r"))]
3351 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
3352 [(set_attr "length" "4")])
3354 (define_expand "extzv"
3355 [(set (match_operand:HI 0 "register_operand" "")
3356 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
3357 (match_operand:HI 2 "general_operand" "")
3358 (match_operand:HI 3 "general_operand" "")))]
3359 "TARGET_H8300 || TARGET_H8300SX"
3364 if (GET_CODE (operands[2]) == CONST_INT
3365 && GET_CODE (operands[3]) == CONST_INT
3366 && INTVAL (operands[2]) <= 8
3367 && INTVAL (operands[3]) >= 0
3368 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8
3369 && memory_operand (operands[1], QImode))
3373 /* Optimize the case where we're extracting into a paradoxical
3374 subreg. It's only necessary to extend to the inner reg. */
3375 if (GET_CODE (operands[0]) == SUBREG
3376 && subreg_lowpart_p (operands[0])
3377 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0])))
3378 < GET_MODE_SIZE (GET_MODE (operands[0])))
3379 && (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0])))
3381 operands[0] = SUBREG_REG (operands[0]);
3383 if (!can_create_pseudo_p ())
3384 temp = gen_lowpart (QImode, operands[0]);
3386 temp = gen_reg_rtx (QImode);
3389 if (! bit_memory_operand (operands[1], QImode))
3391 if (!can_create_pseudo_p ())
3394 replace_equiv_address (operands[1],
3396 XEXP (operands[1], 0)));
3398 emit_insn (gen_bfld (temp, operands[1], operands[2], operands[3]));
3399 convert_move (operands[0], temp, 1);
3405 /* We only have single bit bit-field instructions. */
3406 if (INTVAL (operands[2]) != 1)
3409 /* For now, we don't allow memory operands. */
3410 if (GET_CODE (operands[1]) == MEM)
3414 ;; BAND, BOR, and BXOR patterns
3417 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3418 (match_operator:HI 4 "bit_operator"
3419 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3421 (match_operand:HI 2 "immediate_operand" "n"))
3422 (match_operand:HI 3 "bit_operand" "0")]))]
3424 "bld %Z2,%Y1\;b%c4 #0,%R0\;bst #0,%R0; bl1"
3425 [(set_attr "length" "6")])
3428 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3429 (match_operator:HI 5 "bit_operator"
3430 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3432 (match_operand:HI 2 "immediate_operand" "n"))
3433 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
3435 (match_operand:HI 4 "immediate_operand" "n"))]))]
3437 "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #0,%R0; bl3"
3438 [(set_attr "length" "6")])
3441 [(set (match_operand:QI 0 "register_operand" "=r")
3442 (zero_extract:QI (match_operand:QI 1 "bit_memory_operand" "WU")
3443 (match_operand:QI 2 "immediate_operand" "n")
3444 (match_operand:QI 3 "immediate_operand" "n")))]
3445 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3448 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3449 - (1 << INTVAL (operands[3])));
3450 return \"bfld %2,%1,%R0\";
3452 [(set_attr "cc" "none_0hit")
3453 (set_attr "length_table" "bitfield")])
3456 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3457 (match_operand:QI 2 "immediate_operand" "n")
3458 (match_operand:QI 3 "immediate_operand" "n"))
3459 (match_operand:QI 1 "register_operand" "r"))]
3460 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3463 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3464 - (1 << INTVAL (operands[3])));
3465 return \"bfst %R1,%2,%0\";
3467 [(set_attr "cc" "none_0hit")
3468 (set_attr "length_table" "bitfield")])
3470 (define_expand "cstoreqi4"
3471 [(use (match_operator 1 "eqne_operator"
3472 [(match_operand:QI 2 "h8300_dst_operand" "")
3473 (match_operand:QI 3 "h8300_src_operand" "")]))
3474 (clobber (match_operand:HI 0 "register_operand"))]
3476 "h8300_expand_store (operands); DONE;")
3478 (define_expand "cstorehi4"
3479 [(use (match_operator 1 "eqne_operator"
3480 [(match_operand:HI 2 "h8300_dst_operand" "")
3481 (match_operand:HI 3 "h8300_src_operand" "")]))
3482 (clobber (match_operand:HI 0 "register_operand"))]
3484 "h8300_expand_store (operands); DONE;")
3486 (define_expand "cstoresi4"
3487 [(use (match_operator 1 "eqne_operator"
3488 [(match_operand:SI 2 "h8300_dst_operand" "")
3489 (match_operand:SI 3 "h8300_src_operand" "")]))
3490 (clobber (match_operand:HI 0 "register_operand"))]
3492 "h8300_expand_store (operands); DONE;")
3494 (define_insn "*bstzhireg"
3495 [(set (match_operand:HI 0 "register_operand" "=r")
3496 (match_operator:HI 1 "eqne_operator" [(cc0) (const_int 0)]))]
3498 "mulu.w #0,%T0\;b%k1 .Lh8BR%=\;inc.w #1,%T0\\n.Lh8BR%=:"
3499 [(set_attr "cc" "clobber")])
3501 (define_insn_and_split "*cmpstz"
3502 [(set (zero_extract:QI
3503 (match_operand:QI 0 "bit_memory_operand" "+WU,+WU")
3505 (match_operand:QI 1 "immediate_operand" "n,n"))
3508 [(match_operand 3 "h8300_dst_operand" "r,rQ")
3509 (match_operand 4 "h8300_src_operand" "I,rQi")]))]
3511 && (GET_MODE (operands[3]) == GET_MODE (operands[4])
3512 || GET_CODE (operands[4]) == CONST_INT)
3513 && GET_MODE_CLASS (GET_MODE (operands[3])) == MODE_INT
3514 && GET_MODE_SIZE (GET_MODE (operands[3])) <= 4"
3517 [(set (cc0) (match_dup 5))
3518 (set (zero_extract:QI (match_dup 0) (const_int 1) (match_dup 1))
3519 (match_op_dup:QI 2 [(cc0) (const_int 0)]))]
3520 "operands[5] = gen_rtx_COMPARE (VOIDmode, operands[3], operands[4]);"
3521 [(set_attr "cc" "set_znv,compare")])
3523 (define_insn "*bstz"
3524 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3526 (match_operand:QI 1 "immediate_operand" "n"))
3527 (eq:QI (cc0) (const_int 0)))]
3528 "TARGET_H8300SX && reload_completed"
3530 [(set_attr "cc" "none_0hit")
3531 (set_attr "length_table" "unary")])
3533 (define_insn "*bistz"
3534 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3536 (match_operand:QI 1 "immediate_operand" "n"))
3537 (ne:QI (cc0) (const_int 0)))]
3538 "TARGET_H8300SX && reload_completed"
3540 [(set_attr "cc" "none_0hit")
3541 (set_attr "length_table" "unary")])
3543 (define_insn_and_split "*cmpcondbset"
3544 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3548 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3549 (match_operand 3 "h8300_src_operand" "I,rQi")])
3551 (match_operand:QI 4 "bit_memory_operand" "0,0")
3552 (match_operand:QI 5 "single_one_operand" "n,n"))
3557 [(set (cc0) (match_dup 6))
3560 (match_op_dup 1 [(cc0) (const_int 0)])
3561 (ior:QI (match_dup 4) (match_dup 5)) (match_dup 4)))]
3562 "operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);"
3563 [(set_attr "cc" "set_znv,compare")])
3565 (define_insn "*condbset"
3566 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3568 (match_operator:QI 2 "eqne_operator"
3569 [(cc0) (const_int 0)])
3571 (match_operand:QI 3 "bit_memory_operand" "0")
3572 (match_operand:QI 1 "single_one_operand" "n"))
3574 "TARGET_H8300SX && reload_completed"
3576 [(set_attr "cc" "none_0hit")
3577 (set_attr "length_table" "logicb")])
3579 (define_insn_and_split "*cmpcondbclr"
3580 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3584 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3585 (match_operand 3 "h8300_src_operand" "I,rQi")])
3587 (match_operand:QI 4 "bit_memory_operand" "0,0")
3588 (match_operand:QI 5 "single_zero_operand" "n,n"))
3593 [(set (cc0) (match_dup 6))
3596 (match_op_dup 1 [(cc0) (const_int 0)])
3597 (and:QI (match_dup 4) (match_dup 5)) (match_dup 4)))]
3598 "operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);"
3599 [(set_attr "cc" "set_znv,compare")])
3601 (define_insn "*condbclr"
3602 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3604 (match_operator:QI 2 "eqne_operator"
3605 [(cc0) (const_int 0)])
3607 (match_operand:QI 3 "bit_memory_operand" "0")
3608 (match_operand:QI 1 "single_zero_operand" "n"))
3610 "TARGET_H8300SX && reload_completed"
3612 [(set_attr "cc" "none_0hit")
3613 (set_attr "length_table" "logicb")])
3615 (define_insn_and_split "*cmpcondbsetreg"
3616 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3620 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3621 (match_operand 3 "h8300_src_operand" "I,rQi")])
3623 (match_operand:QI 4 "bit_memory_operand" "0,0")
3624 (ashift:QI (const_int 1)
3625 (match_operand:QI 5 "register_operand" "r,r")))
3630 [(set (cc0) (match_dup 6))
3633 (match_op_dup 1 [(cc0) (const_int 0)])
3634 (ior:QI (match_dup 4)
3635 (ashift:QI (const_int 1)
3636 (match_operand:QI 5 "register_operand" "r,r")))
3638 "operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);"
3639 [(set_attr "cc" "set_znv,compare")])
3641 (define_insn "*condbsetreg"
3642 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3644 (match_operator:QI 2 "eqne_operator"
3645 [(cc0) (const_int 0)])
3647 (match_operand:QI 3 "bit_memory_operand" "0")
3648 (ashift:QI (const_int 1)
3649 (match_operand:QI 1 "register_operand" "r")))
3651 "TARGET_H8300SX && reload_completed"
3653 [(set_attr "cc" "none_0hit")
3654 (set_attr "length_table" "logicb")])
3656 (define_insn_and_split "*cmpcondbclrreg"
3657 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3661 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3662 (match_operand 3 "h8300_src_operand" "I,rQi")])
3664 (match_operand:QI 4 "bit_memory_operand" "0,0")
3665 (ashift:QI (const_int 1)
3666 (match_operand:QI 5 "register_operand" "r,r")))
3671 [(set (cc0) (match_dup 6))
3674 (match_op_dup 1 [(cc0) (const_int 0)])
3675 (and:QI (match_dup 4)
3676 (ashift:QI (const_int 1)
3677 (match_operand:QI 5 "register_operand" "r,r")))
3679 "operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);"
3680 [(set_attr "cc" "set_znv,compare")])
3682 (define_insn "*condbclrreg"
3683 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3685 (match_operator:QI 2 "eqne_operator"
3686 [(cc0) (const_int 0)])
3688 (match_operand:QI 3 "bit_memory_operand" "0")
3689 (ashift:QI (const_int 1)
3690 (match_operand:QI 1 "register_operand" "r")))
3692 "TARGET_H8300SX && reload_completed"
3694 [(set_attr "cc" "none_0hit")
3695 (set_attr "length_table" "logicb")])
3698 ;; -----------------------------------------------------------------
3700 ;; -----------------------------------------------------------------
3704 (define_insn "*insv_si_1_n"
3705 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3707 (match_operand:SI 1 "const_int_operand" "n"))
3708 (match_operand:SI 2 "register_operand" "r"))]
3709 "(TARGET_H8300H || TARGET_H8300S)
3710 && INTVAL (operands[1]) < 16"
3711 "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
3712 [(set_attr "length" "4")])
3714 (define_insn "*insv_si_1_n_lshiftrt"
3715 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3717 (match_operand:SI 1 "const_int_operand" "n"))
3718 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3719 (match_operand:SI 3 "const_int_operand" "n")))]
3720 "(TARGET_H8300H || TARGET_H8300S)
3721 && INTVAL (operands[1]) < 16
3722 && INTVAL (operands[3]) < 16"
3723 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
3724 [(set_attr "length" "4")])
3726 (define_insn "*insv_si_1_n_lshiftrt_16"
3727 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3729 (match_operand:SI 1 "const_int_operand" "n"))
3730 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3732 "(TARGET_H8300H || TARGET_H8300S)
3733 && INTVAL (operands[1]) < 16"
3734 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
3735 [(set_attr "length" "6")])
3737 (define_insn "*insv_si_8_8"
3738 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3741 (match_operand:SI 1 "register_operand" "r"))]
3742 "TARGET_H8300H || TARGET_H8300S"
3744 [(set_attr "length" "2")])
3746 (define_insn "*insv_si_8_8_lshiftrt_8"
3747 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3750 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3752 "TARGET_H8300H || TARGET_H8300S"
3754 [(set_attr "length" "2")])
3758 (define_insn "*extzv_8_8"
3759 [(set (match_operand:SI 0 "register_operand" "=r,r")
3760 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
3763 "TARGET_H8300H || TARGET_H8300S"
3765 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
3766 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
3767 [(set_attr "cc" "set_znv,clobber")
3768 (set_attr "length" "6,4")])
3770 (define_insn "*extzv_8_16"
3771 [(set (match_operand:SI 0 "register_operand" "=r")
3772 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3775 "TARGET_H8300H || TARGET_H8300S"
3776 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
3777 [(set_attr "cc" "set_znv")
3778 (set_attr "length" "6")])
3780 (define_insn "*extzv_16_8"
3781 [(set (match_operand:SI 0 "register_operand" "=r")
3782 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3785 (clobber (match_scratch:SI 2 "=&r"))]
3787 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
3788 [(set_attr "length" "8")
3789 (set_attr "cc" "set_znv")])
3791 ;; Extract the exponent of a float.
3793 (define_insn_and_split "*extzv_8_23"
3794 [(set (match_operand:SI 0 "register_operand" "=r")
3795 (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
3798 "(TARGET_H8300H || TARGET_H8300S)"
3800 "&& reload_completed"
3801 [(parallel [(set (match_dup 0)
3802 (ashift:SI (match_dup 0)
3804 (clobber (scratch:QI))])
3805 (parallel [(set (match_dup 0)
3806 (lshiftrt:SI (match_dup 0)
3808 (clobber (scratch:QI))])]
3813 ;; ((SImode) HImode) << 15
3815 (define_insn_and_split "*twoshifts_l16_r1"
3816 [(set (match_operand:SI 0 "register_operand" "=r")
3817 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3819 (const_int 2147450880)))]
3820 "(TARGET_H8300H || TARGET_H8300S)"
3822 "&& reload_completed"
3823 [(parallel [(set (match_dup 0)
3824 (ashift:SI (match_dup 0)
3826 (clobber (scratch:QI))])
3827 (parallel [(set (match_dup 0)
3828 (lshiftrt:SI (match_dup 0)
3830 (clobber (scratch:QI))])]
3833 ;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
3835 (define_insn_and_split "*andsi3_ashift_n_lower"
3836 [(set (match_operand:SI 0 "register_operand" "=r,r")
3837 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
3838 (match_operand:QI 2 "const_int_operand" "S,n"))
3839 (match_operand:SI 3 "const_int_operand" "n,n")))
3840 (clobber (match_scratch:QI 4 "=X,&r"))]
3841 "(TARGET_H8300H || TARGET_H8300S)
3842 && INTVAL (operands[2]) <= 15
3843 && INTVAL (operands[3]) == ((-1 << INTVAL (operands[2])) & 0xffff)"
3845 "&& reload_completed"
3846 [(parallel [(set (match_dup 5)
3847 (ashift:HI (match_dup 5)
3849 (clobber (match_dup 4))])
3851 (zero_extend:SI (match_dup 5)))]
3852 "operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3854 ;; Accept (A >> 30) & 2 and the like.
3856 (define_insn "*andsi3_lshiftrt_n_sb"
3857 [(set (match_operand:SI 0 "register_operand" "=r")
3858 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3859 (match_operand:SI 2 "const_int_operand" "n"))
3860 (match_operand:SI 3 "single_one_operand" "n")))]
3861 "(TARGET_H8300H || TARGET_H8300S)
3862 && exact_log2 (INTVAL (operands[3])) < 16
3863 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
3866 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
3867 return \"shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0\";
3869 [(set_attr "length" "8")])
3871 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
3872 [(set (match_operand:SI 0 "register_operand" "=r")
3873 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3875 (const_int 4194304)))]
3876 "(TARGET_H8300H || TARGET_H8300S)"
3878 "&& reload_completed"
3880 (and:SI (lshiftrt:SI (match_dup 0)
3883 (parallel [(set (match_dup 0)
3884 (ashift:SI (match_dup 0)
3886 (clobber (scratch:QI))])]
3891 (define_insn "*addsi3_upper"
3892 [(set (match_operand:SI 0 "register_operand" "=r")
3893 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3895 (match_operand:SI 2 "register_operand" "0")))]
3896 "TARGET_H8300H || TARGET_H8300S"
3898 [(set_attr "length" "2")])
3900 (define_insn "*addsi3_lshiftrt_16_zexthi"
3901 [(set (match_operand:SI 0 "register_operand" "=r")
3902 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3904 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
3905 "TARGET_H8300H || TARGET_H8300S"
3906 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0"
3907 [(set_attr "length" "6")])
3909 (define_insn_and_split "*addsi3_and_r_1"
3910 [(set (match_operand:SI 0 "register_operand" "=r")
3911 (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
3913 (match_operand:SI 2 "register_operand" "0")))]
3914 "(TARGET_H8300H || TARGET_H8300S)"
3916 "&& reload_completed"
3917 [(set (cc0) (compare (zero_extract:SI (match_dup 1)
3922 (if_then_else (eq (cc0)
3924 (label_ref (match_dup 3))
3927 (plus:SI (match_dup 2)
3930 "operands[3] = gen_label_rtx ();")
3932 (define_insn_and_split "*addsi3_and_not_r_1"
3933 [(set (match_operand:SI 0 "register_operand" "=r")
3934 (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3936 (match_operand:SI 2 "register_operand" "0")))]
3937 "(TARGET_H8300H || TARGET_H8300S)"
3939 "&& reload_completed"
3940 [(set (cc0) (compare (zero_extract:SI (match_dup 1)
3945 (if_then_else (ne (cc0)
3947 (label_ref (match_dup 3))
3950 (plus:SI (match_dup 2)
3953 "operands[3] = gen_label_rtx ();")
3957 (define_insn "*ixorhi3_zext"
3958 [(set (match_operand:HI 0 "register_operand" "=r")
3959 (match_operator:HI 1 "iorxor_operator"
3960 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
3961 (match_operand:HI 3 "register_operand" "0")]))]
3964 [(set_attr "length" "2")])
3968 (define_insn "*ixorsi3_zext_qi"
3969 [(set (match_operand:SI 0 "register_operand" "=r")
3970 (match_operator:SI 1 "iorxor_operator"
3971 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
3972 (match_operand:SI 3 "register_operand" "0")]))]
3975 [(set_attr "length" "2")])
3977 (define_insn "*ixorsi3_zext_hi"
3978 [(set (match_operand:SI 0 "register_operand" "=r")
3979 (match_operator:SI 1 "iorxor_operator"
3980 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
3981 (match_operand:SI 3 "register_operand" "0")]))]
3982 "TARGET_H8300H || TARGET_H8300S"
3984 [(set_attr "length" "2")])
3986 (define_insn "*ixorsi3_ashift_16"
3987 [(set (match_operand:SI 0 "register_operand" "=r")
3988 (match_operator:SI 1 "iorxor_operator"
3989 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
3991 (match_operand:SI 3 "register_operand" "0")]))]
3992 "TARGET_H8300H || TARGET_H8300S"
3994 [(set_attr "length" "2")])
3996 (define_insn "*ixorsi3_lshiftrt_16"
3997 [(set (match_operand:SI 0 "register_operand" "=r")
3998 (match_operator:SI 1 "iorxor_operator"
3999 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
4001 (match_operand:SI 3 "register_operand" "0")]))]
4002 "TARGET_H8300H || TARGET_H8300S"
4004 [(set_attr "length" "2")])
4008 (define_insn "*iorhi3_ashift_8"
4009 [(set (match_operand:HI 0 "register_operand" "=r")
4010 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
4012 (match_operand:HI 2 "register_operand" "0")))]
4015 [(set_attr "length" "2")])
4017 (define_insn "*iorhi3_lshiftrt_8"
4018 [(set (match_operand:HI 0 "register_operand" "=r")
4019 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
4021 (match_operand:HI 2 "register_operand" "0")))]
4024 [(set_attr "length" "2")])
4026 (define_insn "*iorhi3_two_qi"
4027 [(set (match_operand:HI 0 "register_operand" "=r")
4028 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
4029 (ashift:HI (match_operand:HI 2 "register_operand" "r")
4033 [(set_attr "length" "2")])
4035 (define_insn "*iorhi3_two_qi_mem"
4036 [(set (match_operand:HI 0 "register_operand" "=&r")
4037 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
4038 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
4041 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
4042 [(set_attr "length" "16")])
4045 [(set (match_operand:HI 0 "register_operand" "")
4046 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
4047 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
4049 "(TARGET_H8300H || TARGET_H8300S)
4051 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
4054 "operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));")
4058 (define_insn "*iorsi3_two_hi"
4059 [(set (match_operand:SI 0 "register_operand" "=r")
4060 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
4061 (ashift:SI (match_operand:SI 2 "register_operand" "r")
4063 "TARGET_H8300H || TARGET_H8300S"
4065 [(set_attr "length" "2")])
4067 (define_insn_and_split "*iorsi3_two_qi_zext"
4068 [(set (match_operand:SI 0 "register_operand" "=&r")
4069 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
4071 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
4073 (const_int 65280))))]
4074 "(TARGET_H8300H || TARGET_H8300S)"
4076 "&& reload_completed"
4078 (ior:HI (zero_extend:HI (match_dup 1))
4079 (ashift:HI (subreg:HI (match_dup 2) 0)
4082 (zero_extend:SI (match_dup 3)))]
4083 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
4085 (define_insn "*iorsi3_e2f"
4086 [(set (match_operand:SI 0 "register_operand" "=r")
4087 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
4089 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
4091 "TARGET_H8300H || TARGET_H8300S"
4093 [(set_attr "length" "2")])
4095 (define_insn_and_split "*iorsi3_two_qi_sext"
4096 [(set (match_operand:SI 0 "register_operand" "=r")
4097 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
4098 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
4100 "(TARGET_H8300H || TARGET_H8300S)"
4102 "&& reload_completed"
4104 (ior:HI (zero_extend:HI (match_dup 1))
4105 (ashift:HI (match_dup 4)
4108 (sign_extend:SI (match_dup 3)))]
4109 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4110 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4112 (define_insn "*iorsi3_w"
4113 [(set (match_operand:SI 0 "register_operand" "=r,&r")
4114 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
4116 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
4117 "TARGET_H8300H || TARGET_H8300S"
4119 [(set_attr "length" "2,8")])
4121 (define_insn "*iorsi3_ashift_31"
4122 [(set (match_operand:SI 0 "register_operand" "=&r")
4123 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4125 (match_operand:SI 2 "register_operand" "0")))]
4126 "TARGET_H8300H || TARGET_H8300S"
4127 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
4128 [(set_attr "length" "6")
4129 (set_attr "cc" "set_znv")])
4131 (define_insn "*iorsi3_and_ashift"
4132 [(set (match_operand:SI 0 "register_operand" "=r")
4133 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4134 (match_operand:SI 2 "const_int_operand" "n"))
4135 (match_operand:SI 3 "single_one_operand" "n"))
4136 (match_operand:SI 4 "register_operand" "0")))]
4137 "(TARGET_H8300H || TARGET_H8300S)
4138 && (INTVAL (operands[3]) & ~0xffff) == 0"
4141 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
4142 - INTVAL (operands[2]));
4143 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
4144 operands[2] = srcpos;
4145 operands[3] = dstpos;
4146 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
4148 [(set_attr "length" "6")])
4150 (define_insn "*iorsi3_and_lshiftrt"
4151 [(set (match_operand:SI 0 "register_operand" "=r")
4152 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4153 (match_operand:SI 2 "const_int_operand" "n"))
4154 (match_operand:SI 3 "single_one_operand" "n"))
4155 (match_operand:SI 4 "register_operand" "0")))]
4156 "(TARGET_H8300H || TARGET_H8300S)
4157 && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
4160 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
4161 + INTVAL (operands[2]));
4162 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
4163 operands[2] = srcpos;
4164 operands[3] = dstpos;
4165 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
4167 [(set_attr "length" "6")])
4169 (define_insn "*iorsi3_zero_extract"
4170 [(set (match_operand:SI 0 "register_operand" "=r")
4171 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
4173 (match_operand:SI 2 "const_int_operand" "n"))
4174 (match_operand:SI 3 "register_operand" "0")))]
4175 "(TARGET_H8300H || TARGET_H8300S)
4176 && INTVAL (operands[2]) < 16"
4177 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
4178 [(set_attr "length" "6")])
4180 (define_insn "*iorsi3_and_lshiftrt_n_sb"
4181 [(set (match_operand:SI 0 "register_operand" "=r")
4182 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4185 (match_operand:SI 2 "register_operand" "0")))]
4186 "(TARGET_H8300H || TARGET_H8300S)"
4187 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
4188 [(set_attr "length" "8")])
4190 (define_insn "*iorsi3_and_lshiftrt_9_sb"
4191 [(set (match_operand:SI 0 "register_operand" "=r")
4192 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4194 (const_int 4194304))
4195 (match_operand:SI 2 "register_operand" "0")))
4196 (clobber (match_scratch:HI 3 "=&r"))]
4197 "(TARGET_H8300H || TARGET_H8300S)"
4200 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4201 return \"shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
4203 return \"rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
4205 [(set_attr "length" "10")])
4207 ;; Used to OR the exponent of a float.
4209 (define_insn "*iorsi3_shift"
4210 [(set (match_operand:SI 0 "register_operand" "=r")
4211 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4213 (match_operand:SI 2 "register_operand" "0")))
4214 (clobber (match_scratch:SI 3 "=&r"))]
4215 "TARGET_H8300H || TARGET_H8300S"
4219 [(set (match_operand:SI 0 "register_operand" "")
4220 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4223 (clobber (match_operand:SI 2 "register_operand" ""))]
4224 "(TARGET_H8300H || TARGET_H8300S)
4225 && epilogue_completed
4226 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4227 && REGNO (operands[0]) != REGNO (operands[1])"
4228 [(parallel [(set (match_dup 3)
4229 (ashift:HI (match_dup 3)
4231 (clobber (scratch:QI))])
4233 (ior:SI (ashift:SI (match_dup 1)
4236 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
4239 [(set (match_operand:SI 0 "register_operand" "")
4240 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4243 (clobber (match_operand:SI 2 "register_operand" ""))]
4244 "(TARGET_H8300H || TARGET_H8300S)
4245 && epilogue_completed
4246 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4247 && REGNO (operands[0]) != REGNO (operands[1]))"
4250 (parallel [(set (match_dup 3)
4251 (ashift:HI (match_dup 3)
4253 (clobber (scratch:QI))])
4255 (ior:SI (ashift:SI (match_dup 2)
4258 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4260 (define_insn "*iorsi2_and_1_lshiftrt_1"
4261 [(set (match_operand:SI 0 "register_operand" "=r")
4262 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
4264 (lshiftrt:SI (match_dup 1)
4266 "TARGET_H8300H || TARGET_H8300S"
4267 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
4268 [(set_attr "length" "6")])
4270 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
4271 [(set (match_operand:SI 0 "register_operand" "=r")
4272 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
4274 (ashift:SI (match_operand:SI 2 "register_operand" "r")
4276 "(TARGET_H8300H || TARGET_H8300S)"
4278 "&& reload_completed"
4280 (ior:HI (ashift:HI (match_dup 4)
4283 (parallel [(set (match_dup 0)
4284 (ashift:SI (match_dup 0)
4286 (clobber (scratch:QI))])]
4287 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4288 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4290 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
4291 [(set (match_operand:SI 0 "register_operand" "=&r")
4292 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
4294 (const_int 16711680))
4295 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
4297 "(TARGET_H8300H || TARGET_H8300S)"
4299 "&& reload_completed"
4301 (ior:HI (zero_extend:HI (match_dup 1))
4302 (ashift:HI (subreg:HI (match_dup 2) 0)
4304 (parallel [(set (match_dup 0)
4305 (ashift:SI (match_dup 0)
4307 (clobber (scratch:QI))])]
4308 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
4310 ;; Used to add the exponent of a float.
4312 (define_insn "*addsi3_shift"
4313 [(set (match_operand:SI 0 "register_operand" "=r")
4314 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
4315 (const_int 8388608))
4316 (match_operand:SI 2 "register_operand" "0")))
4317 (clobber (match_scratch:SI 3 "=&r"))]
4318 "TARGET_H8300H || TARGET_H8300S"
4322 [(set (match_operand:SI 0 "register_operand" "")
4323 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4324 (const_int 8388608))
4326 (clobber (match_operand:SI 2 "register_operand" ""))]
4327 "(TARGET_H8300H || TARGET_H8300S)
4328 && epilogue_completed
4329 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4330 && REGNO (operands[0]) != REGNO (operands[1])"
4331 [(parallel [(set (match_dup 3)
4332 (ashift:HI (match_dup 3)
4334 (clobber (scratch:QI))])
4336 (plus:SI (mult:SI (match_dup 1)
4339 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
4342 [(set (match_operand:SI 0 "register_operand" "")
4343 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4344 (const_int 8388608))
4346 (clobber (match_operand:SI 2 "register_operand" ""))]
4347 "(TARGET_H8300H || TARGET_H8300S)
4348 && epilogue_completed
4349 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4350 && REGNO (operands[0]) != REGNO (operands[1]))"
4353 (parallel [(set (match_dup 3)
4354 (ashift:HI (match_dup 3)
4356 (clobber (scratch:QI))])
4358 (plus:SI (mult:SI (match_dup 2)
4361 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4365 (define_insn_and_split "*ashiftsi_sextqi_7"
4366 [(set (match_operand:SI 0 "register_operand" "=r")
4367 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
4369 "(TARGET_H8300H || TARGET_H8300S)"
4371 "&& reload_completed"
4372 [(parallel [(set (match_dup 2)
4373 (ashift:HI (match_dup 2)
4375 (clobber (scratch:QI))])
4377 (sign_extend:SI (match_dup 2)))
4378 (parallel [(set (match_dup 0)
4379 (ashiftrt:SI (match_dup 0)
4381 (clobber (scratch:QI))])]
4382 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
4384 ;; Storing a part of HImode to QImode.
4387 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4388 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
4392 [(set_attr "cc" "set_znv")
4393 (set_attr "length" "8")])
4395 ;; Storing a part of SImode to QImode.
4398 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4399 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4403 [(set_attr "cc" "set_znv")
4404 (set_attr "length" "8")])
4407 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4408 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4410 (clobber (match_scratch:SI 2 "=&r"))]
4411 "TARGET_H8300H || TARGET_H8300S"
4412 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
4413 [(set_attr "cc" "set_znv")
4414 (set_attr "length" "10")])
4417 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4418 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4420 (clobber (match_scratch:SI 2 "=&r"))]
4421 "TARGET_H8300H || TARGET_H8300S"
4422 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
4423 [(set_attr "cc" "set_znv")
4424 (set_attr "length" "10")])
4426 (define_insn_and_split ""
4428 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4432 (label_ref (match_operand 1 "" ""))
4437 [(set (cc0) (compare (match_dup 0)
4440 (if_then_else (ge (cc0)
4442 (label_ref (match_dup 1))
4446 (define_insn_and_split ""
4448 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4452 (label_ref (match_operand 1 "" ""))
4457 [(set (cc0) (compare (match_dup 0)
4460 (if_then_else (lt (cc0)
4462 (label_ref (match_dup 1))
4466 ;; -----------------------------------------------------------------
4467 ;; PEEPHOLE PATTERNS
4468 ;; -----------------------------------------------------------------
4470 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4473 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4474 (lshiftrt:HI (match_dup 0)
4475 (match_operand:HI 1 "const_int_operand" "")))
4476 (clobber (match_operand:HI 2 "" ""))])
4478 (and:HI (match_dup 0)
4479 (match_operand:HI 3 "const_int_operand" "")))]
4480 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4482 (and:HI (match_dup 0)
4486 (lshiftrt:HI (match_dup 0)
4488 (clobber (match_dup 2))])]
4491 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4494 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4495 (ashift:HI (match_dup 0)
4496 (match_operand:HI 1 "const_int_operand" "")))
4497 (clobber (match_operand:HI 2 "" ""))])
4499 (and:HI (match_dup 0)
4500 (match_operand:HI 3 "const_int_operand" "")))]
4501 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4503 (and:HI (match_dup 0)
4507 (ashift:HI (match_dup 0)
4509 (clobber (match_dup 2))])]
4512 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4515 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4516 (lshiftrt:SI (match_dup 0)
4517 (match_operand:SI 1 "const_int_operand" "")))
4518 (clobber (match_operand:SI 2 "" ""))])
4520 (and:SI (match_dup 0)
4521 (match_operand:SI 3 "const_int_operand" "")))]
4522 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4524 (and:SI (match_dup 0)
4528 (lshiftrt:SI (match_dup 0)
4530 (clobber (match_dup 2))])]
4533 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4536 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4537 (ashift:SI (match_dup 0)
4538 (match_operand:SI 1 "const_int_operand" "")))
4539 (clobber (match_operand:SI 2 "" ""))])
4541 (and:SI (match_dup 0)
4542 (match_operand:SI 3 "const_int_operand" "")))]
4543 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4545 (and:SI (match_dup 0)
4549 (ashift:SI (match_dup 0)
4551 (clobber (match_dup 2))])]
4554 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
4557 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4558 (lshiftrt:SI (match_dup 0)
4559 (match_operand:SI 1 "const_int_operand" "")))
4560 (clobber (match_operand:SI 2 "" ""))])
4562 (and:SI (match_dup 0)
4563 (match_operand:SI 3 "const_int_operand" "")))]
4564 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
4566 (and:SI (match_dup 0)
4570 (lshiftrt:SI (match_dup 0)
4572 (clobber (match_dup 2))])]
4575 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
4578 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4579 (ashift:SI (match_dup 0)
4580 (match_operand:SI 1 "const_int_operand" "")))
4581 (clobber (match_operand:SI 2 "" ""))])
4583 (and:SI (match_dup 0)
4584 (match_operand:SI 3 "const_int_operand" "")))]
4585 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
4587 (and:SI (match_dup 0)
4591 (ashift:SI (match_dup 0)
4593 (clobber (match_dup 2))])]
4596 ;; Convert a QImode push into an SImode push so that the
4597 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4600 [(parallel [(set (reg:SI SP_REG)
4601 (plus:SI (reg:SI SP_REG) (const_int -4)))
4602 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
4603 (match_operand:QI 0 "register_operand" ""))])]
4604 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4605 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4607 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4610 [(parallel [(set (reg:HI SP_REG)
4611 (plus:HI (reg:HI SP_REG) (const_int -4)))
4612 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
4613 (match_operand:QI 0 "register_operand" ""))])]
4614 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4615 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4617 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4619 ;; Convert a HImode push into an SImode push so that the
4620 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4623 [(parallel [(set (reg:SI SP_REG)
4624 (plus:SI (reg:SI SP_REG) (const_int -4)))
4625 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
4626 (match_operand:HI 0 "register_operand" ""))])]
4627 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4628 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4630 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4633 [(parallel [(set (reg:HI SP_REG)
4634 (plus:HI (reg:HI SP_REG) (const_int -4)))
4635 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
4636 (match_operand:HI 0 "register_operand" ""))])]
4637 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4638 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4640 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4642 ;; Cram four pushes into stm.l.
4645 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4646 (match_operand:SI 0 "register_operand" ""))
4647 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4648 (match_operand:SI 1 "register_operand" ""))
4649 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4650 (match_operand:SI 2 "register_operand" ""))
4651 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4652 (match_operand:SI 3 "register_operand" ""))]
4653 "TARGET_H8300S && !TARGET_NORMAL_MODE
4654 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4655 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4656 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4657 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4658 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4659 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4661 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4663 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4665 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
4667 (set (reg:SI SP_REG)
4668 (plus:SI (reg:SI SP_REG)
4669 (const_int -16)))])]
4673 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4674 (match_operand:SI 0 "register_operand" ""))
4675 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4676 (match_operand:SI 1 "register_operand" ""))
4677 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4678 (match_operand:SI 2 "register_operand" ""))
4679 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4680 (match_operand:SI 3 "register_operand" ""))]
4681 "TARGET_H8300S && TARGET_NORMAL_MODE
4682 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4683 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4684 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4685 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4686 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4687 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4689 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4691 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4693 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
4695 (set (reg:HI SP_REG)
4696 (plus:HI (reg:HI SP_REG)
4697 (const_int -16)))])]
4700 ;; Cram three pushes into stm.l.
4703 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4704 (match_operand:SI 0 "register_operand" ""))
4705 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4706 (match_operand:SI 1 "register_operand" ""))
4707 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4708 (match_operand:SI 2 "register_operand" ""))]
4709 "TARGET_H8300S && !TARGET_NORMAL_MODE
4710 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4711 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4712 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4713 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4714 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4716 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4718 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4720 (set (reg:SI SP_REG)
4721 (plus:SI (reg:SI SP_REG)
4722 (const_int -12)))])]
4726 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4727 (match_operand:SI 0 "register_operand" ""))
4728 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4729 (match_operand:SI 1 "register_operand" ""))
4730 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4731 (match_operand:SI 2 "register_operand" ""))]
4732 "TARGET_H8300S && TARGET_NORMAL_MODE
4733 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4734 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4735 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4736 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4737 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4739 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4741 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4743 (set (reg:HI SP_REG)
4744 (plus:HI (reg:HI SP_REG)
4745 (const_int -12)))])]
4748 ;; Cram two pushes into stm.l.
4751 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4752 (match_operand:SI 0 "register_operand" ""))
4753 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4754 (match_operand:SI 1 "register_operand" ""))]
4755 "TARGET_H8300S && !TARGET_NORMAL_MODE
4756 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4757 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4758 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4759 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4761 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4763 (set (reg:SI SP_REG)
4764 (plus:SI (reg:SI SP_REG)
4769 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4770 (match_operand:SI 0 "register_operand" ""))
4771 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4772 (match_operand:SI 1 "register_operand" ""))]
4773 "TARGET_H8300S && TARGET_NORMAL_MODE
4774 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4775 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4776 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4777 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4779 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4781 (set (reg:HI SP_REG)
4782 (plus:HI (reg:HI SP_REG)
4789 ;; add.w r7,r0 (6 bytes)
4794 ;; adds #2,r0 (4 bytes)
4797 [(set (match_operand:HI 0 "register_operand" "")
4798 (match_operand:HI 1 "const_int_operand" ""))
4800 (plus:HI (match_dup 0)
4801 (match_operand:HI 2 "register_operand" "")))]
4802 "REG_P (operands[0]) && REG_P (operands[2])
4803 && REGNO (operands[0]) != REGNO (operands[2])
4804 && (satisfies_constraint_J (operands[1])
4805 || satisfies_constraint_L (operands[1])
4806 || satisfies_constraint_N (operands[1]))"
4810 (plus:HI (match_dup 0)
4818 ;; add.l er7,er0 (6 bytes)
4823 ;; adds #4,er0 (4 bytes)
4826 [(set (match_operand:SI 0 "register_operand" "")
4827 (match_operand:SI 1 "const_int_operand" ""))
4829 (plus:SI (match_dup 0)
4830 (match_operand:SI 2 "register_operand" "")))]
4831 "(TARGET_H8300H || TARGET_H8300S)
4832 && REG_P (operands[0]) && REG_P (operands[2])
4833 && REGNO (operands[0]) != REGNO (operands[2])
4834 && (satisfies_constraint_L (operands[1])
4835 || satisfies_constraint_N (operands[1]))"
4839 (plus:SI (match_dup 0)
4846 ;; add.l #10,er0 (takes 8 bytes)
4852 ;; add.l er7,er0 (takes 6 bytes)
4855 [(set (match_operand:SI 0 "register_operand" "")
4856 (match_operand:SI 1 "register_operand" ""))
4858 (plus:SI (match_dup 0)
4859 (match_operand:SI 2 "const_int_operand" "")))]
4860 "(TARGET_H8300H || TARGET_H8300S)
4861 && REG_P (operands[0]) && REG_P (operands[1])
4862 && REGNO (operands[0]) != REGNO (operands[1])
4863 && !satisfies_constraint_L (operands[2])
4864 && !satisfies_constraint_N (operands[2])
4865 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
4866 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
4867 || INTVAL (operands[2]) == 0xffff
4868 || INTVAL (operands[2]) == 0xfffe)"
4872 (plus:SI (match_dup 0)
4888 [(set (match_operand:HI 0 "register_operand" "")
4889 (plus:HI (match_dup 0)
4890 (match_operand 1 "incdec_operand" "")))
4891 (set (cc0) (compare (match_dup 0)
4894 (if_then_else (match_operator 3 "eqne_operator"
4895 [(cc0) (const_int 0)])
4896 (label_ref (match_operand 2 "" ""))
4898 "TARGET_H8300H || TARGET_H8300S"
4899 [(set (match_operand:HI 0 "register_operand" "")
4900 (unspec:HI [(match_dup 0)
4903 (set (cc0) (compare (match_dup 0)
4906 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4907 (label_ref (match_dup 2))
4911 ;; The SImode version of the previous pattern.
4914 [(set (match_operand:SI 0 "register_operand" "")
4915 (plus:SI (match_dup 0)
4916 (match_operand 1 "incdec_operand" "")))
4917 (set (cc0) (compare (match_dup 0)
4920 (if_then_else (match_operator 3 "eqne_operator"
4921 [(cc0) (const_int 0)])
4922 (label_ref (match_operand 2 "" ""))
4924 "TARGET_H8300H || TARGET_H8300S"
4925 [(set (match_operand:SI 0 "register_operand" "")
4926 (unspec:SI [(match_dup 0)
4929 (set (cc0) (compare (match_dup 0)
4932 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4933 (label_ref (match_dup 2))
4938 [(parallel [(set (cc0)
4939 (compare (zero_extract:SI (match_operand:QI 0 "register_operand" "")
4943 (clobber (scratch:QI))])
4945 (if_then_else (match_operator 1 "eqne_operator"
4946 [(cc0) (const_int 0)])
4947 (label_ref (match_operand 2 "" ""))
4949 "(TARGET_H8300H || TARGET_H8300S)"
4950 [(set (cc0) (compare (match_dup 0)
4953 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4954 (label_ref (match_dup 2))
4956 "operands[3] = ((GET_CODE (operands[1]) == EQ)
4957 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
4958 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));")
4960 ;; The next three peephole2's will try to transform
4962 ;; mov.b A,r0l (or mov.l A,er0)
4969 ;; and.b #CST,r0l (if CST is not 255)
4972 [(set (match_operand:QI 0 "register_operand" "")
4973 (match_operand:QI 1 "general_operand" ""))
4974 (set (match_operand:SI 2 "register_operand" "")
4975 (and:SI (match_dup 2)
4977 "(TARGET_H8300H || TARGET_H8300S)
4978 && !reg_overlap_mentioned_p (operands[2], operands[1])
4979 && REGNO (operands[0]) == REGNO (operands[2])"
4982 (set (strict_low_part (match_dup 0))
4987 [(set (match_operand:SI 0 "register_operand" "")
4988 (match_operand:SI 1 "general_operand" ""))
4990 (and:SI (match_dup 0)
4992 "(TARGET_H8300H || TARGET_H8300S)
4993 && !reg_overlap_mentioned_p (operands[0], operands[1])
4994 && !(GET_CODE (operands[1]) == MEM && !offsettable_memref_p (operands[1]))
4995 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
4998 (set (strict_low_part (match_dup 2))
5000 "operands[2] = gen_lowpart (QImode, operands[0]);
5001 operands[3] = gen_lowpart (QImode, operands[1]);")
5004 [(set (match_operand 0 "register_operand" "")
5005 (match_operand 1 "general_operand" ""))
5006 (set (match_operand:SI 2 "register_operand" "")
5007 (and:SI (match_dup 2)
5008 (match_operand:SI 3 "const_int_qi_operand" "")))]
5009 "(TARGET_H8300H || TARGET_H8300S)
5010 && (GET_MODE (operands[0]) == QImode
5011 || GET_MODE (operands[0]) == HImode
5012 || GET_MODE (operands[0]) == SImode)
5013 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5014 && REGNO (operands[0]) == REGNO (operands[2])
5015 && !reg_overlap_mentioned_p (operands[2], operands[1])
5016 && !(GET_MODE (operands[1]) != QImode
5017 && GET_CODE (operands[1]) == MEM
5018 && !offsettable_memref_p (operands[1]))
5019 && !(GET_MODE (operands[1]) != QImode
5020 && GET_CODE (operands[1]) == MEM
5021 && MEM_VOLATILE_P (operands[1]))"
5024 (set (strict_low_part (match_dup 4))
5027 (and:SI (match_dup 2)
5029 "operands[4] = gen_lowpart (QImode, operands[0]);
5030 operands[5] = gen_lowpart (QImode, operands[1]);
5031 operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));")
5034 [(set (match_operand:SI 0 "register_operand" "")
5035 (match_operand:SI 1 "register_operand" ""))
5037 (and:SI (match_dup 0)
5038 (const_int 65280)))]
5039 "(TARGET_H8300H || TARGET_H8300S)
5040 && !reg_overlap_mentioned_p (operands[0], operands[1])"
5043 (set (zero_extract:SI (match_dup 0)
5046 (lshiftrt:SI (match_dup 1)
5050 ;; If a load of mem:SI is followed by an AND that turns off the upper
5051 ;; half, then we can load mem:HI instead.
5054 [(set (match_operand:SI 0 "register_operand" "")
5055 (match_operand:SI 1 "memory_operand" ""))
5057 (and:SI (match_dup 0)
5058 (match_operand:SI 2 "const_int_operand" "")))]
5059 "(TARGET_H8300H || TARGET_H8300S)
5060 && !MEM_VOLATILE_P (operands[1])
5061 && offsettable_memref_p (operands[1])
5062 && (INTVAL (operands[2]) & ~0xffff) == 0
5063 && INTVAL (operands[2]) != 255"
5067 (and:SI (match_dup 0)
5069 "operands[3] = gen_lowpart (HImode, operands[0]);
5070 operands[4] = gen_lowpart (HImode, operands[1]);")
5072 ;; Convert a memory comparison to a move if there is a scratch register.
5075 [(match_scratch:QI 1 "r")
5077 (compare (match_operand:QI 0 "memory_operand" "")
5082 (set (cc0) (compare (match_dup 1)
5087 [(match_scratch:HI 1 "r")
5089 (compare (match_operand:HI 0 "memory_operand" "")
5091 "(TARGET_H8300H || TARGET_H8300S)"
5094 (set (cc0) (compare (match_dup 1)
5099 [(match_scratch:SI 1 "r")
5101 (compare (match_operand:SI 0 "memory_operand" "")
5103 "(TARGET_H8300H || TARGET_H8300S)"
5106 (set (cc0) (compare (match_dup 1)
5111 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
5112 ;; the equivalent with shorter sequences. Here is the summary. Cases
5113 ;; are grouped for each define_peephole2.
5115 ;; reg const_int use insn
5116 ;; --------------------------------------------------------
5117 ;; dead -2 eq/ne inc.l
5118 ;; dead -1 eq/ne inc.l
5119 ;; dead 1 eq/ne dec.l
5120 ;; dead 2 eq/ne dec.l
5122 ;; dead 1 ge/lt shar.l
5123 ;; dead 3 (H8S) ge/lt shar.l
5125 ;; dead 1 geu/ltu shar.l
5126 ;; dead 3 (H8S) geu/ltu shar.l
5128 ;; ---- 255 ge/lt mov.b
5130 ;; ---- 255 geu/ltu mov.b
5144 (compare (match_operand:HI 0 "register_operand" "")
5145 (match_operand:HI 1 "incdec_operand" "")))
5147 (if_then_else (match_operator 3 "eqne_operator"
5148 [(cc0) (const_int 0)])
5149 (label_ref (match_operand 2 "" ""))
5151 "(TARGET_H8300H || TARGET_H8300S)
5152 && INTVAL (operands[1]) != 0
5153 && peep2_reg_dead_p (1, operands[0])"
5155 (unspec:HI [(match_dup 0)
5158 (set (cc0) (compare (match_dup 0)
5161 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5162 (label_ref (match_dup 2))
5164 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
5178 (compare (match_operand:HI 0 "register_operand" "")
5179 (match_operand:HI 1 "const_int_operand" "")))
5181 (if_then_else (match_operator 2 "gtle_operator"
5182 [(cc0) (const_int 0)])
5183 (label_ref (match_operand 3 "" ""))
5185 "(TARGET_H8300H || TARGET_H8300S)
5186 && peep2_reg_dead_p (1, operands[0])
5187 && (INTVAL (operands[1]) == 1
5188 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5189 [(parallel [(set (match_dup 0)
5190 (ashiftrt:HI (match_dup 0)
5192 (clobber (scratch:QI))])
5193 (set (cc0) (compare (match_dup 0)
5196 (if_then_else (match_dup 2)
5197 (label_ref (match_dup 3))
5199 "operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
5213 (compare (match_operand:HI 0 "register_operand" "")
5214 (match_operand:HI 1 "const_int_operand" "")))
5216 (if_then_else (match_operator 2 "gtuleu_operator"
5217 [(cc0) (const_int 0)])
5218 (label_ref (match_operand 3 "" ""))
5220 "(TARGET_H8300H || TARGET_H8300S)
5221 && peep2_reg_dead_p (1, operands[0])
5222 && (INTVAL (operands[1]) == 1
5223 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5224 [(parallel [(set (match_dup 0)
5225 (ashiftrt:HI (match_dup 0)
5227 (clobber (scratch:QI))])
5228 (set (cc0) (compare (match_dup 0)
5231 (if_then_else (match_dup 5)
5232 (label_ref (match_dup 3))
5235 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5236 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5254 (compare (match_operand:HI 0 "register_operand" "")
5257 (if_then_else (match_operator 1 "gtle_operator"
5258 [(cc0) (const_int 0)])
5259 (label_ref (match_operand 2 "" ""))
5261 "TARGET_H8300H || TARGET_H8300S"
5262 [(set (cc0) (compare (and:HI (match_dup 0)
5266 (if_then_else (match_dup 1)
5267 (label_ref (match_dup 2))
5283 (compare (match_operand:HI 0 "register_operand" "")
5286 (if_then_else (match_operator 1 "gtuleu_operator"
5287 [(cc0) (const_int 0)])
5288 (label_ref (match_operand 2 "" ""))
5290 "TARGET_H8300H || TARGET_H8300S"
5291 [(set (cc0) (compare (and:HI (match_dup 0)
5295 (if_then_else (match_dup 3)
5296 (label_ref (match_dup 2))
5299 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
5305 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
5306 ;; the equivalent with shorter sequences. Here is the summary. Cases
5307 ;; are grouped for each define_peephole2.
5309 ;; reg const_int use insn
5310 ;; --------------------------------------------------------
5311 ;; live -2 eq/ne copy and inc.l
5312 ;; live -1 eq/ne copy and inc.l
5313 ;; live 1 eq/ne copy and dec.l
5314 ;; live 2 eq/ne copy and dec.l
5316 ;; dead -2 eq/ne inc.l
5317 ;; dead -1 eq/ne inc.l
5318 ;; dead 1 eq/ne dec.l
5319 ;; dead 2 eq/ne dec.l
5321 ;; dead -131072 eq/ne inc.w and test
5322 ;; dead -65536 eq/ne inc.w and test
5323 ;; dead 65536 eq/ne dec.w and test
5324 ;; dead 131072 eq/ne dec.w and test
5326 ;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
5327 ;; dead 0x0000??00 eq/ne xor.b and test
5328 ;; dead 0x0000ffff eq/ne not.w and test
5330 ;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
5331 ;; dead 0xffff??ff eq/ne xor.b and not.l
5332 ;; dead 0x40000000 (H8S) eq/ne rotl.l and dec.l
5333 ;; dead 0x80000000 eq/ne rotl.l and dec.l
5335 ;; live 1 ge/lt copy and shar.l
5336 ;; live 3 (H8S) ge/lt copy and shar.l
5338 ;; live 1 geu/ltu copy and shar.l
5339 ;; live 3 (H8S) geu/ltu copy and shar.l
5341 ;; dead 1 ge/lt shar.l
5342 ;; dead 3 (H8S) ge/lt shar.l
5344 ;; dead 1 geu/ltu shar.l
5345 ;; dead 3 (H8S) geu/ltu shar.l
5347 ;; dead 3 (H8/300H) ge/lt and.b and test
5348 ;; dead 7 ge/lt and.b and test
5349 ;; dead 15 ge/lt and.b and test
5350 ;; dead 31 ge/lt and.b and test
5351 ;; dead 63 ge/lt and.b and test
5352 ;; dead 127 ge/lt and.b and test
5353 ;; dead 255 ge/lt and.b and test
5355 ;; dead 3 (H8/300H) geu/ltu and.b and test
5356 ;; dead 7 geu/ltu and.b and test
5357 ;; dead 15 geu/ltu and.b and test
5358 ;; dead 31 geu/ltu and.b and test
5359 ;; dead 63 geu/ltu and.b and test
5360 ;; dead 127 geu/ltu and.b and test
5361 ;; dead 255 geu/ltu and.b and test
5363 ;; ---- 65535 ge/lt mov.w
5365 ;; ---- 65535 geu/ltu mov.w
5379 (compare (match_operand:SI 0 "register_operand" "")
5380 (match_operand:SI 1 "incdec_operand" "")))
5382 (if_then_else (match_operator 3 "eqne_operator"
5383 [(cc0) (const_int 0)])
5384 (label_ref (match_operand 2 "" ""))
5386 "(TARGET_H8300H || TARGET_H8300S)
5387 && INTVAL (operands[1]) != 0
5388 && peep2_reg_dead_p (1, operands[0])"
5390 (unspec:SI [(match_dup 0)
5393 (set (cc0) (compare (match_dup 0)
5396 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5397 (label_ref (match_dup 2))
5399 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
5413 (compare (match_operand:SI 0 "register_operand" "")
5414 (match_operand:SI 1 "const_int_operand" "")))
5416 (if_then_else (match_operator 3 "eqne_operator"
5417 [(cc0) (const_int 0)])
5418 (label_ref (match_operand 2 "" ""))
5420 "(TARGET_H8300H || TARGET_H8300S)
5421 && peep2_reg_dead_p (1, operands[0])
5422 && (INTVAL (operands[1]) == -131072
5423 || INTVAL (operands[1]) == -65536
5424 || INTVAL (operands[1]) == 65536
5425 || INTVAL (operands[1]) == 131072)"
5427 (plus:SI (match_dup 0)
5429 (set (cc0) (compare (match_dup 0)
5432 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5433 (label_ref (match_dup 2))
5435 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
5450 (compare (match_operand:SI 0 "register_operand" "")
5451 (match_operand:SI 1 "const_int_operand" "")))
5453 (if_then_else (match_operator 3 "eqne_operator"
5454 [(cc0) (const_int 0)])
5455 (label_ref (match_operand 2 "" ""))
5457 "(TARGET_H8300H || TARGET_H8300S)
5458 && peep2_reg_dead_p (1, operands[0])
5459 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
5460 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
5461 || INTVAL (operands[1]) == 0x0000ffff)
5462 && INTVAL (operands[1]) != 0
5463 && INTVAL (operands[1]) != 1
5464 && INTVAL (operands[1]) != 2"
5466 (xor:SI (match_dup 0)
5468 (set (cc0) (compare (match_dup 0)
5471 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5472 (label_ref (match_dup 2))
5489 (compare (match_operand:SI 0 "register_operand" "")
5490 (match_operand:SI 1 "const_int_operand" "")))
5492 (if_then_else (match_operator 3 "eqne_operator"
5493 [(cc0) (const_int 0)])
5494 (label_ref (match_operand 2 "" ""))
5496 "(TARGET_H8300H || TARGET_H8300S)
5497 && peep2_reg_dead_p (1, operands[0])
5498 && ((INTVAL (operands[1]) | 0x00ff) == -1
5499 || (INTVAL (operands[1]) | 0xff00) == -1)
5500 && INTVAL (operands[1]) != -1
5501 && INTVAL (operands[1]) != -2"
5503 (xor:SI (match_dup 0)
5506 (not:SI (match_dup 0)))
5507 (set (cc0) (compare (match_dup 0)
5510 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5511 (label_ref (match_dup 2))
5513 "operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);")
5517 ;; cmp.l #-2147483648,er0
5528 (compare (match_operand:SI 0 "register_operand" "")
5529 (match_operand:SI 1 "const_int_operand" "")))
5531 (if_then_else (match_operator 3 "eqne_operator"
5532 [(cc0) (const_int 0)])
5533 (label_ref (match_operand 2 "" ""))
5535 "(TARGET_H8300H || TARGET_H8300S)
5536 && peep2_reg_dead_p (1, operands[0])
5537 && (INTVAL (operands[1]) == -2147483647 - 1
5538 || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
5540 (rotate:SI (match_dup 0)
5543 (unspec:SI [(match_dup 0)
5546 (set (cc0) (compare (match_dup 0)
5549 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5550 (label_ref (match_dup 2))
5552 "operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2);")
5565 ;; We avoid this transformation if we see more than one copy of the
5566 ;; same compare insn immediately before this one.
5569 [(match_scratch:SI 4 "r")
5571 (compare (match_operand:SI 0 "register_operand" "")
5572 (match_operand:SI 1 "const_int_operand" "")))
5574 (if_then_else (match_operator 2 "gtle_operator"
5575 [(cc0) (const_int 0)])
5576 (label_ref (match_operand 3 "" ""))
5578 "(TARGET_H8300H || TARGET_H8300S)
5579 && !peep2_reg_dead_p (1, operands[0])
5580 && (INTVAL (operands[1]) == 1
5581 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5582 && !same_cmp_preceding_p (insn)"
5585 (parallel [(set (match_dup 4)
5586 (ashiftrt:SI (match_dup 4)
5588 (clobber (scratch:QI))])
5589 (set (cc0) (compare (match_dup 4)
5592 (if_then_else (match_dup 2)
5593 (label_ref (match_dup 3))
5595 "operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
5608 ;; We avoid this transformation if we see more than one copy of the
5609 ;; same compare insn immediately before this one.
5612 [(match_scratch:SI 4 "r")
5614 (compare (match_operand:SI 0 "register_operand" "")
5615 (match_operand:SI 1 "const_int_operand" "")))
5617 (if_then_else (match_operator 2 "gtuleu_operator"
5618 [(cc0) (const_int 0)])
5619 (label_ref (match_operand 3 "" ""))
5621 "(TARGET_H8300H || TARGET_H8300S)
5622 && !peep2_reg_dead_p (1, operands[0])
5623 && (INTVAL (operands[1]) == 1
5624 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5625 && !same_cmp_preceding_p (insn)"
5628 (parallel [(set (match_dup 4)
5629 (ashiftrt:SI (match_dup 4)
5631 (clobber (scratch:QI))])
5632 (set (cc0) (compare (match_dup 4)
5635 (if_then_else (match_dup 6)
5636 (label_ref (match_dup 3))
5639 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5640 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5658 (compare (match_operand:SI 0 "register_operand" "")
5659 (match_operand:SI 1 "const_int_operand" "")))
5661 (if_then_else (match_operator 2 "gtle_operator"
5662 [(cc0) (const_int 0)])
5663 (label_ref (match_operand 3 "" ""))
5665 "(TARGET_H8300H || TARGET_H8300S)
5666 && peep2_reg_dead_p (1, operands[0])
5667 && (INTVAL (operands[1]) == 1
5668 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5669 [(parallel [(set (match_dup 0)
5670 (ashiftrt:SI (match_dup 0)
5672 (clobber (scratch:QI))])
5673 (set (cc0) (compare (match_dup 0)
5676 (if_then_else (match_dup 2)
5677 (label_ref (match_dup 3))
5679 "operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
5693 (compare (match_operand:SI 0 "register_operand" "")
5694 (match_operand:SI 1 "const_int_operand" "")))
5696 (if_then_else (match_operator 2 "gtuleu_operator"
5697 [(cc0) (const_int 0)])
5698 (label_ref (match_operand 3 "" ""))
5700 "(TARGET_H8300H || TARGET_H8300S)
5701 && peep2_reg_dead_p (1, operands[0])
5702 && (INTVAL (operands[1]) == 1
5703 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5704 [(parallel [(set (match_dup 0)
5705 (ashiftrt:SI (match_dup 0)
5707 (clobber (scratch:QI))])
5708 (set (cc0) (compare (match_dup 0)
5711 (if_then_else (match_dup 5)
5712 (label_ref (match_dup 3))
5715 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5716 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5735 (compare (match_operand:SI 0 "register_operand" "")
5736 (match_operand:SI 1 "const_int_operand" "")))
5738 (if_then_else (match_operator 2 "gtle_operator"
5739 [(cc0) (const_int 0)])
5740 (label_ref (match_operand 3 "" ""))
5742 "(TARGET_H8300H || TARGET_H8300S)
5743 && peep2_reg_dead_p (1, operands[0])
5744 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
5745 || INTVAL (operands[1]) == 7
5746 || INTVAL (operands[1]) == 15
5747 || INTVAL (operands[1]) == 31
5748 || INTVAL (operands[1]) == 63
5749 || INTVAL (operands[1]) == 127
5750 || INTVAL (operands[1]) == 255)"
5752 (and:SI (match_dup 0)
5754 (set (cc0) (compare (match_dup 0)
5757 (if_then_else (match_dup 2)
5758 (label_ref (match_dup 3))
5760 "operands[4] = GEN_INT (~INTVAL (operands[1]));")
5775 (compare (match_operand:SI 0 "register_operand" "")
5776 (match_operand:SI 1 "const_int_operand" "")))
5778 (if_then_else (match_operator 2 "gtuleu_operator"
5779 [(cc0) (const_int 0)])
5780 (label_ref (match_operand 3 "" ""))
5782 "(TARGET_H8300H || TARGET_H8300S)
5783 && peep2_reg_dead_p (1, operands[0])
5784 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
5785 || INTVAL (operands[1]) == 7
5786 || INTVAL (operands[1]) == 15
5787 || INTVAL (operands[1]) == 31
5788 || INTVAL (operands[1]) == 63
5789 || INTVAL (operands[1]) == 127
5790 || INTVAL (operands[1]) == 255)"
5792 (and:SI (match_dup 0)
5794 (set (cc0) (compare (match_dup 0)
5797 (if_then_else (match_dup 5)
5798 (label_ref (match_dup 3))
5801 operands[4] = GEN_INT (~INTVAL (operands[1]));
5802 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5820 (compare (match_operand:SI 0 "register_operand" "")
5823 (if_then_else (match_operator 1 "gtle_operator"
5824 [(cc0) (const_int 0)])
5825 (label_ref (match_operand 2 "" ""))
5827 "TARGET_H8300H || TARGET_H8300S"
5828 [(set (cc0) (compare (and:SI (match_dup 0)
5832 (if_then_else (match_dup 1)
5833 (label_ref (match_dup 2))
5849 (compare (match_operand:SI 0 "register_operand" "")
5852 (if_then_else (match_operator 1 "gtuleu_operator"
5853 [(cc0) (const_int 0)])
5854 (label_ref (match_operand 2 "" ""))
5856 "TARGET_H8300H || TARGET_H8300S"
5857 [(set (cc0) (compare (and:SI (match_dup 0)
5861 (if_then_else (match_dup 3)
5862 (label_ref (match_dup 2))
5865 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
5882 ;; We avoid this transformation if we see more than one copy of the
5883 ;; same compare insn.
5886 [(match_scratch:SI 4 "r")
5888 (compare (match_operand:SI 0 "register_operand" "")
5889 (match_operand:SI 1 "incdec_operand" "")))
5891 (if_then_else (match_operator 3 "eqne_operator"
5892 [(cc0) (const_int 0)])
5893 (label_ref (match_operand 2 "" ""))
5895 "(TARGET_H8300H || TARGET_H8300S)
5896 && INTVAL (operands[1]) != 0
5897 && !peep2_reg_dead_p (1, operands[0])
5898 && !same_cmp_following_p (insn)"
5902 (unspec:SI [(match_dup 4)
5905 (set (cc0) (compare (match_dup 4)
5908 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5909 (label_ref (match_dup 2))
5911 "operands[5] = GEN_INT (- INTVAL (operands[1]));")
5913 ;; Narrow the mode of testing if possible.
5916 [(set (match_operand:HI 0 "register_operand" "")
5917 (and:HI (match_dup 0)
5918 (match_operand:HI 1 "const_int_qi_operand" "")))
5919 (set (cc0) (compare (match_dup 0)
5922 (if_then_else (match_operator 3 "eqne_operator"
5923 [(cc0) (const_int 0)])
5924 (label_ref (match_operand 2 "" ""))
5926 "peep2_reg_dead_p (2, operands[0])"
5928 (and:QI (match_dup 4)
5930 (set (cc0) (compare (match_dup 4)
5933 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5934 (label_ref (match_dup 2))
5936 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
5937 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
5940 [(set (match_operand:SI 0 "register_operand" "")
5941 (and:SI (match_dup 0)
5942 (match_operand:SI 1 "const_int_qi_operand" "")))
5943 (set (cc0) (compare (match_dup 0)
5946 (if_then_else (match_operator 3 "eqne_operator"
5947 [(cc0) (const_int 0)])
5948 (label_ref (match_operand 2 "" ""))
5950 "peep2_reg_dead_p (2, operands[0])"
5952 (and:QI (match_dup 4)
5954 (set (cc0) (compare (match_dup 4)
5957 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5958 (label_ref (match_dup 2))
5960 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
5961 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
5964 [(set (match_operand:SI 0 "register_operand" "")
5965 (and:SI (match_dup 0)
5966 (match_operand:SI 1 "const_int_hi_operand" "")))
5967 (set (cc0) (compare (match_dup 0)
5970 (if_then_else (match_operator 3 "eqne_operator"
5971 [(cc0) (const_int 0)])
5972 (label_ref (match_operand 2 "" ""))
5974 "peep2_reg_dead_p (2, operands[0])"
5976 (and:HI (match_dup 4)
5978 (set (cc0) (compare (match_dup 4)
5981 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5982 (label_ref (match_dup 2))
5984 "operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
5985 operands[5] = gen_int_mode (INTVAL (operands[1]), HImode);")
5988 [(set (match_operand:SI 0 "register_operand" "")
5989 (and:SI (match_dup 0)
5990 (match_operand:SI 1 "const_int_qi_operand" "")))
5992 (xor:SI (match_dup 0)
5993 (match_operand:SI 2 "const_int_qi_operand" "")))
5994 (set (cc0) (compare (match_dup 0)
5997 (if_then_else (match_operator 4 "eqne_operator"
5998 [(cc0) (const_int 0)])
5999 (label_ref (match_operand 3 "" ""))
6001 "peep2_reg_dead_p (3, operands[0])
6002 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
6004 (and:QI (match_dup 5)
6007 (xor:QI (match_dup 5)
6009 (set (cc0) (compare (match_dup 5)
6012 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
6013 (label_ref (match_dup 3))
6015 "operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
6016 operands[6] = gen_int_mode (INTVAL (operands[1]), QImode);
6017 operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);")
6019 ;; These triggers right at the end of allocation of locals in the
6020 ;; prologue (and possibly at other places).
6022 ;; stack adjustment of -4, generate one push
6024 ;; before : 6 bytes, 10 clocks
6025 ;; after : 4 bytes, 10 clocks
6028 [(set (reg:SI SP_REG)
6029 (plus:SI (reg:SI SP_REG)
6031 (set (mem:SI (reg:SI SP_REG))
6032 (match_operand:SI 0 "register_operand" ""))]
6033 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
6034 && REGNO (operands[0]) != SP_REG"
6035 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
6039 ;; stack adjustment of -12, generate one push
6041 ;; before : 10 bytes, 14 clocks
6042 ;; after : 8 bytes, 14 clocks
6045 [(set (reg:SI SP_REG)
6046 (plus:SI (reg:SI SP_REG)
6048 (set (mem:SI (reg:SI SP_REG))
6049 (match_operand:SI 0 "register_operand" ""))]
6050 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
6051 && REGNO (operands[0]) != SP_REG"
6052 [(set (reg:SI SP_REG)
6053 (plus:SI (reg:SI SP_REG)
6055 (set (reg:SI SP_REG)
6056 (plus:SI (reg:SI SP_REG)
6058 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
6072 ;; if "reg" dies at the end of the sequence.
6074 [(set (match_operand 0 "register_operand" "")
6075 (match_operand 1 "memory_operand" ""))
6077 (match_operator 2 "h8sx_binary_memory_operator"
6079 (match_operand 3 "h8300_src_operand" "")]))
6080 (set (match_operand 4 "memory_operand" "")
6082 "0 /* Disable because it breaks compiling fp-bit.c. */
6084 && peep2_reg_dead_p (3, operands[0])
6085 && !reg_overlap_mentioned_p (operands[0], operands[3])
6086 && !reg_overlap_mentioned_p (operands[0], operands[4])
6087 && h8sx_mergeable_memrefs_p (operands[4], operands[1])"
6091 operands[5] = shallow_copy_rtx (operands[2]);
6092 XEXP (operands[5], 0) = operands[1];
6104 ;; if "reg" dies in the second insn.
6106 [(set (match_operand 0 "register_operand" "")
6107 (match_operand 1 "h8300_src_operand" ""))
6108 (set (match_operand 2 "h8300_dst_operand" "")
6109 (match_operator 3 "h8sx_binary_memory_operator"
6110 [(match_operand 4 "h8300_dst_operand" "")
6112 "0 /* Disable because it breaks compiling fp-bit.c. */
6114 && peep2_reg_dead_p (2, operands[0])
6115 && !reg_overlap_mentioned_p (operands[0], operands[4])"
6119 operands[5] = shallow_copy_rtx (operands[3]);
6120 XEXP (operands[5], 1) = operands[1];
6133 ;; if "reg" dies at the end of the sequence.
6135 [(set (match_operand 0 "register_operand" "")
6136 (match_operand 1 "memory_operand" ""))
6138 (match_operator 2 "h8sx_unary_memory_operator"
6140 (set (match_operand 3 "memory_operand" "")
6143 && peep2_reg_dead_p (3, operands[0])
6144 && !reg_overlap_mentioned_p (operands[0], operands[3])
6145 && h8sx_mergeable_memrefs_p (operands[3], operands[1])"
6149 operands[4] = shallow_copy_rtx (operands[2]);
6150 XEXP (operands[4], 0) = operands[1];
6162 ;; if "reg" dies in the comparison.
6164 [(set (match_operand 0 "register_operand" "")
6165 (match_operand 1 "h8300_dst_operand" ""))
6167 (compare (match_dup 0)
6168 (match_operand 2 "h8300_src_operand" "")))]
6170 && peep2_reg_dead_p (2, operands[0])
6171 && !reg_overlap_mentioned_p (operands[0], operands[2])
6172 && operands[2] != const0_rtx"
6174 (compare (match_dup 1)
6177 ;; Likewise for the second operand.
6179 [(set (match_operand 0 "register_operand" "")
6180 (match_operand 1 "h8300_src_operand" ""))
6182 (compare (match_operand 2 "h8300_dst_operand" "")
6185 && peep2_reg_dead_p (2, operands[0])
6186 && !reg_overlap_mentioned_p (operands[0], operands[2])"
6188 (compare (match_dup 2)
6191 ;; Combine two moves.
6193 [(set (match_operand 0 "register_operand" "")
6194 (match_operand 1 "h8300_src_operand" ""))
6195 (set (match_operand 2 "h8300_dst_operand" "")
6198 && peep2_reg_dead_p (2, operands[0])
6199 && !reg_overlap_mentioned_p (operands[0], operands[2])"