1 ;; GCC machine description for Hitachi H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003 Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;; Some of the extend instructions accept a general_operand_src, which
26 ;; allows all the normal memory addressing modes. The length computations
27 ;; don't take this into account. The lengths in the MD file should be
28 ;; "worst case" and then be adjusted to their correct values by
29 ;; h8300_adjust_insn_length.
31 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
32 ;; registers. Right now GCC doesn't expose the "e" half to the
33 ;; compiler, so using add/subs for addhi and subhi is safe. Long
34 ;; term, we want to expose the "e" half to the compiler (gives us 8
35 ;; more 16bit registers). At that point addhi and subhi can't use
38 ;; There's currently no way to have an insv/extzv expander for the H8/300H
39 ;; because word_mode is different for the H8/300 and H8/300H.
41 ;; Shifts/rotates by small constants should be handled by special
42 ;; patterns so we get the length and cc status correct.
44 ;; Bitfield operations no longer accept memory operands. We need
45 ;; to add variants which operate on memory back to the MD.
47 ;; ??? Implement remaining bit ops available on the h8300
49 ;; ----------------------------------------------------------------------
51 ;; ----------------------------------------------------------------------
65 ;; ----------------------------------------------------------------------
67 ;; ----------------------------------------------------------------------
69 (define_attr "cpu" "h8300,h8300h"
70 (const (symbol_ref "cpu_type")))
72 (define_attr "type" "branch,arith"
73 (const_string "arith"))
75 ;; The size of instructions in bytes.
77 (define_attr "length" ""
78 (cond [(eq_attr "type" "branch")
79 (if_then_else (and (ge (minus (match_dup 0) (pc))
81 (le (minus (match_dup 0) (pc))
84 (if_then_else (and (eq_attr "cpu" "h8300h")
85 (and (ge (minus (pc) (match_dup 0))
87 (le (minus (pc) (match_dup 0))
93 ;; The necessity of instruction length adjustment.
95 (define_attr "adjust_length" "yes,no"
96 (cond [(eq_attr "type" "branch") (const_string "no")]
97 (const_string "yes")))
99 ;; Condition code settings.
101 ;; none - insn does not affect cc
102 ;; none_0hit - insn does not affect cc but it does modify operand 0
103 ;; This attribute is used to keep track of when operand 0 changes.
104 ;; See the description of NOTICE_UPDATE_CC for more info.
105 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
106 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
107 ;; compare - compare instruction
108 ;; clobber - value of cc is unknown
110 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
111 (const_string "clobber"))
113 ;; ----------------------------------------------------------------------
115 ;; ----------------------------------------------------------------------
119 (define_insn "pushqi1_h8300"
120 [(parallel [(set (reg:HI SP_REG)
121 (plus:HI (reg:HI SP_REG) (const_int -2)))
122 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
123 (match_operand:QI 0 "register_operand" "r"))])]
125 && REGNO (operands[0]) != SP_REG"
127 [(set_attr "length" "2")
128 (set_attr "cc" "clobber")])
130 (define_insn "pushqi1_h8300hs"
131 [(parallel [(set (reg:SI SP_REG)
132 (plus:SI (reg:SI SP_REG) (const_int -4)))
133 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
134 (match_operand:QI 0 "register_operand" "r"))])]
135 "(TARGET_H8300H || TARGET_H8300S)
136 && REGNO (operands[0]) != SP_REG"
138 [(set_attr "length" "4")
139 (set_attr "cc" "clobber")])
141 (define_expand "pushqi1"
142 [(use (match_operand:QI 0 "register_operand" ""))]
147 emit_insn (gen_pushqi1_h8300 (operands[0]));
149 emit_insn (gen_pushqi1_h8300hs (operands[0]));
154 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
155 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
157 && (register_operand (operands[0], QImode)
158 || register_operand (operands[1], QImode))"
166 [(set_attr "length" "2,2,2,2,4,4")
167 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
170 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
171 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
172 "(TARGET_H8300H || TARGET_H8300S)
173 && (register_operand (operands[0], QImode)
174 || register_operand (operands[1], QImode))"
182 [(set_attr "length" "2,2,2,2,8,8")
183 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
185 (define_expand "movqi"
186 [(set (match_operand:QI 0 "general_operand_dst" "")
187 (match_operand:QI 1 "general_operand_src" ""))]
191 /* One of the ops has to be in a register. */
192 if (!register_operand (operand0, QImode)
193 && !register_operand (operand1, QImode))
195 operands[1] = copy_to_mode_reg (QImode, operand1);
199 (define_insn "movstrictqi"
200 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r,r,r"))
201 (match_operand:QI 1 "general_operand_src" "I,r,n,m"))]
208 [(set_attr_alternative "length"
209 [(const_int 2) (const_int 2) (const_int 2)
210 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
211 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
215 (define_expand "pushhi1_h8300"
216 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
217 (match_operand:HI 0 "register_operand" ""))]
219 && REGNO (operands[0]) != SP_REG"
222 (define_insn "pushhi1_h8300hs"
223 [(parallel [(set (reg:SI SP_REG)
224 (plus:SI (reg:SI SP_REG) (const_int -4)))
225 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
226 (match_operand:HI 0 "register_operand" "r"))])]
227 "(TARGET_H8300H || TARGET_H8300S)
228 && REGNO (operands[0]) != SP_REG"
230 [(set_attr "length" "4")
231 (set_attr "cc" "clobber")])
233 (define_expand "pushhi1"
234 [(use (match_operand:HI 0 "register_operand" ""))]
239 emit_insn (gen_pushhi1_h8300 (operands[0]));
241 emit_insn (gen_pushhi1_h8300hs (operands[0]));
246 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
247 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
249 && (register_operand (operands[0], HImode)
250 || register_operand (operands[1], HImode))
251 && !(GET_CODE (operands[0]) == MEM
252 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
253 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
254 && GET_CODE (operands[1]) == REG
255 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
263 [(set_attr "length" "2,2,2,4,4,4")
264 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
267 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
268 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
269 "(TARGET_H8300H || TARGET_H8300S)
270 && (register_operand (operands[0], HImode)
271 || register_operand (operands[1], HImode))"
279 [(set_attr "length" "2,2,2,4,8,8")
280 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
282 (define_expand "movhi"
283 [(set (match_operand:HI 0 "general_operand_dst" "")
284 (match_operand:HI 1 "general_operand_src" ""))]
288 /* One of the ops has to be in a register. */
289 if (!register_operand (operand1, HImode)
290 && !register_operand (operand0, HImode))
292 operands[1] = copy_to_mode_reg (HImode, operand1);
296 (define_insn "movstricthi"
297 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r,r"))
298 (match_operand:HI 1 "general_operand_src" "I,r,i,m"))]
305 [(set_attr_alternative "length"
306 [(const_int 2) (const_int 2) (const_int 4)
307 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
308 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
312 (define_expand "movsi"
313 [(set (match_operand:SI 0 "general_operand_dst" "")
314 (match_operand:SI 1 "general_operand_src" ""))]
320 if (do_movsi (operands))
325 /* One of the ops has to be in a register. */
326 if (!register_operand (operand1, SImode)
327 && !register_operand (operand0, SImode))
329 operands[1] = copy_to_mode_reg (SImode, operand1);
334 (define_expand "movsf"
335 [(set (match_operand:SF 0 "general_operand_dst" "")
336 (match_operand:SF 1 "general_operand_src" ""))]
342 if (do_movsi (operands))
347 /* One of the ops has to be in a register. */
348 if (!register_operand (operand1, SFmode)
349 && !register_operand (operand0, SFmode))
351 operands[1] = copy_to_mode_reg (SFmode, operand1);
356 (define_insn "movsi_h8300"
357 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
358 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
360 && (register_operand (operands[0], SImode)
361 || register_operand (operands[1], SImode))"
364 unsigned int rn = -1;
365 switch (which_alternative)
368 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
370 if (REGNO (operands[0]) < REGNO (operands[1]))
371 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
373 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
375 /* Make sure we don't trample the register we index with. */
376 if (GET_CODE (operands[1]) == MEM)
378 rtx inside = XEXP (operands[1], 0);
383 else if (GET_CODE (inside) == PLUS)
385 rtx lhs = XEXP (inside, 0);
386 rtx rhs = XEXP (inside, 1);
387 if (REG_P (lhs)) rn = REGNO (lhs);
388 if (REG_P (rhs)) rn = REGNO (rhs);
391 if (rn == REGNO (operands[0]))
393 /* Move the second word first. */
394 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
398 /* See if either half is zero. If so, use sub.w to clear
400 if (GET_CODE (operands[1]) == CONST_INT)
402 if ((INTVAL (operands[1]) & 0xffff) == 0)
403 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
404 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
405 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
407 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
410 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
412 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
414 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
419 [(set_attr "length" "4,4,8,8,4,4")
420 (set_attr "cc" "clobber")])
422 (define_insn "movsf_h8300"
423 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
424 (match_operand:SF 1 "general_operand_src" "I,r,io,r,r,>"))]
426 && (register_operand (operands[0], SFmode)
427 || register_operand (operands[1], SFmode))"
430 /* Copy of the movsi stuff. */
431 unsigned int rn = -1;
432 switch (which_alternative)
435 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
437 if (REGNO (operands[0]) < REGNO (operands[1]))
438 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
440 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
442 /* Make sure we don't trample the register we index with. */
443 if (GET_CODE (operands[1]) == MEM)
445 rtx inside = XEXP (operands[1], 0);
450 else if (GET_CODE (inside) == PLUS)
452 rtx lhs = XEXP (inside, 0);
453 rtx rhs = XEXP (inside, 1);
454 if (REG_P (lhs)) rn = REGNO (lhs);
455 if (REG_P (rhs)) rn = REGNO (rhs);
458 if (rn == REGNO (operands[0]))
459 /* Move the second word first. */
460 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
462 /* Move the first word first. */
463 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
466 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
468 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
470 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
475 [(set_attr "length" "4,4,8,8,4,4")
476 (set_attr "cc" "clobber")])
478 (define_insn "movsi_h8300hs"
479 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
480 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
481 "(TARGET_H8300S || TARGET_H8300H)
482 && (register_operand (operands[0], SImode)
483 || register_operand (operands[1], SImode))
484 && !(GET_CODE (operands[0]) == MEM
485 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
486 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
487 && GET_CODE (operands[1]) == REG
488 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
491 switch (which_alternative)
494 return \"sub.l %S0,%S0\";
498 return \"clrmac\;ldmac %1,macl\";
500 return \"stmac macl,%0\";
502 if (GET_CODE (operands[1]) == CONST_INT)
504 int val = INTVAL (operands[1]);
506 /* Look for constants which can be made by adding an 8-bit
507 number to zero in one of the two low bytes. */
508 if (val == (val & 0xff))
510 operands[1] = GEN_INT ((char) val & 0xff);
511 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
514 if (val == (val & 0xff00))
516 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
517 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
520 /* Look for constants that can be obtained by subs, inc, and
522 switch (val & 0xffffffff)
525 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
527 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
529 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
532 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
534 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
537 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
539 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
542 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
544 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
548 return \"mov.l %S1,%S0\";
550 [(set_attr "length" "2,2,6,4,4,10,10,2,6,4")
551 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
553 (define_insn "movsf_h8300h"
554 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
555 (match_operand:SF 1 "general_operand_src" "I,r,im,r,r,>"))]
556 "(TARGET_H8300H || TARGET_H8300S)
557 && (register_operand (operands[0], SFmode)
558 || register_operand (operands[1], SFmode))"
566 [(set_attr "length" "2,2,10,10,4,4")
567 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
569 ;; ----------------------------------------------------------------------
571 ;; ----------------------------------------------------------------------
574 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
576 (match_operand 1 "const_int_operand" "n,n")))]
579 [(set_attr "length" "2,4")
580 (set_attr "cc" "set_zn,set_zn")])
583 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
585 (match_operand 1 "const_int_operand" "n")))]
588 [(set_attr "length" "2")
589 (set_attr "cc" "set_zn")])
591 (define_insn "*tst_extzv_1_n"
593 (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
595 (match_operand 1 "const_int_operand" "n,n,n")))
596 (clobber (match_scratch:QI 2 "=X,X,&r"))]
597 "(TARGET_H8300H || TARGET_H8300S)"
602 [(set_attr "length" "2,8,10")
603 (set_attr "cc" "set_zn,set_zn,set_zn")])
607 (zero_extract:SI (match_operand:QI 0 "general_operand" "")
609 (match_operand 1 "const_int_operand" "")))
610 (clobber (match_operand:QI 2 "register_operand" ""))]
611 "(TARGET_H8300H || TARGET_H8300S)
613 && !EXTRA_CONSTRAINT (operands[0], 'U')"
616 (parallel [(set (cc0) (zero_extract:SI (match_dup 2)
619 (clobber (scratch:QI))])]
623 [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
625 (match_operand 1 "const_int_operand" "n")))]
626 "(TARGET_H8300H || TARGET_H8300S)
627 && INTVAL (operands[1]) <= 15"
629 [(set_attr "length" "2")
630 (set_attr "cc" "set_zn")])
632 (define_insn_and_split "*tstsi_upper_bit"
634 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
636 (match_operand 1 "const_int_operand" "n")))
637 (clobber (match_scratch:SI 2 "=&r"))]
638 "(TARGET_H8300H || TARGET_H8300S)
639 && INTVAL (operands[1]) >= 16"
641 "&& reload_completed"
643 (ior:SI (and:SI (match_dup 2)
645 (lshiftrt:SI (match_dup 0)
648 (zero_extract:SI (match_dup 2)
651 "operands[3] = GEN_INT (INTVAL (operands[1]) - 16);")
655 (and:HI (match_operand:HI 0 "register_operand" "r")
656 (match_operand:HI 1 "single_one_operand" "n")))]
660 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
661 if (INTVAL (operands[1]) > 128)
663 operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
664 return \"btst\\t%V1,%t0\";
666 return \"btst\\t%V1,%s0\";
668 [(set_attr "length" "2")
669 (set_attr "cc" "set_zn")])
673 (and:SI (match_operand:SI 0 "register_operand" "r")
674 (match_operand:SI 1 "single_one_operand" "n")))]
675 "(TARGET_H8300H || TARGET_H8300S)
676 && (INTVAL (operands[1]) & 0xffff) != 0"
679 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
680 if (INTVAL (operands[1]) > 128)
682 operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
683 return \"btst\\t%V1,%x0\";
685 return \"btst\\t%V1,%w0\";
687 [(set_attr "length" "2")
688 (set_attr "cc" "set_zn")])
691 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
694 [(set_attr "length" "2")
695 (set_attr "cc" "set_znv")])
698 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
701 [(set_attr "length" "2")
702 (set_attr "cc" "set_znv")])
706 (and:HI (match_operand:HI 0 "register_operand" "r")
710 [(set_attr "length" "2")
711 (set_attr "cc" "set_znv")])
714 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
715 "TARGET_H8300H || TARGET_H8300S"
717 [(set_attr "length" "2")
718 (set_attr "cc" "set_znv")])
722 (and:SI (match_operand:SI 0 "register_operand" "r")
723 (const_int -65536)))]
726 [(set_attr "length" "2")
727 (set_attr "cc" "set_znv")])
731 (compare (match_operand:QI 0 "register_operand" "r")
732 (match_operand:QI 1 "nonmemory_operand" "rn")))]
735 [(set_attr "length" "2")
736 (set_attr "cc" "compare")])
738 (define_expand "cmphi"
740 (compare (match_operand:HI 0 "register_operand" "")
741 (match_operand:HI 1 "nonmemory_operand" "")))]
745 /* Force operand1 into a register if we're compiling
747 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
748 operands[1] = force_reg (HImode, operands[1]);
751 (define_insn "*cmphi_h8300"
753 (compare (match_operand:HI 0 "register_operand" "r")
754 (match_operand:HI 1 "register_operand" "r")))]
757 [(set_attr "length" "2")
758 (set_attr "cc" "compare")])
760 (define_insn "*cmphi_h8300hs"
762 (compare (match_operand:HI 0 "register_operand" "r,r")
763 (match_operand:HI 1 "nonmemory_operand" "r,n")))]
764 "TARGET_H8300H || TARGET_H8300S"
766 [(set_attr "length" "2,4")
767 (set_attr "cc" "compare,compare")])
771 (compare (match_operand:SI 0 "register_operand" "r,r")
772 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
773 "TARGET_H8300H || TARGET_H8300S"
775 [(set_attr "length" "2,6")
776 (set_attr "cc" "compare,compare")])
778 ;; ----------------------------------------------------------------------
780 ;; ----------------------------------------------------------------------
782 (define_insn "addqi3"
783 [(set (match_operand:QI 0 "register_operand" "=r")
784 (plus:QI (match_operand:QI 1 "register_operand" "%0")
785 (match_operand:QI 2 "nonmemory_operand" "rn")))]
788 [(set_attr "length" "2")
789 (set_attr "cc" "set_zn")])
791 (define_expand "addhi3"
792 [(set (match_operand:HI 0 "register_operand" "")
793 (plus:HI (match_operand:HI 1 "register_operand" "")
794 (match_operand:HI 2 "nonmemory_operand" "")))]
798 (define_insn "*addhi3_h8300"
799 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
800 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
801 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
807 add.b %s2,%s0\;addx %t2,%t0
809 [(set_attr "length" "2,2,2,4,2")
810 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
812 ;; This splitter is very important to make the stack adjustment
813 ;; interrupt-safe. The combination of add.b and addx is unsafe!
815 ;; We apply this split after the peephole2 pass so that we won't end
816 ;; up creating too many adds/subs when a scratch register is
817 ;; available, which is actually a common case because stack unrolling
818 ;; tends to happen immediately after a function call.
821 [(set (match_operand:HI 0 "stack_pointer_operand" "")
822 (plus:HI (match_dup 0)
823 (match_operand 1 "const_int_gt_2_operand" "")))]
824 "TARGET_H8300 && flow2_completed"
826 "split_adds_subs (HImode, operands); DONE;")
829 [(match_scratch:HI 2 "r")
830 (set (match_operand:HI 0 "stack_pointer_operand" "")
831 (plus:HI (match_dup 0)
832 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
837 (plus:HI (match_dup 0)
841 (define_insn "*addhi3_h8300hs"
842 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
843 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
844 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
845 "TARGET_H8300H || TARGET_H8300S"
852 [(set_attr "length" "2,2,2,4,2")
853 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
855 (define_insn "*addhi3_incdec"
856 [(set (match_operand:HI 0 "register_operand" "=r,r")
857 (unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
858 (match_operand:HI 2 "incdec_operand" "M,O")]
860 "TARGET_H8300H || TARGET_H8300S"
864 [(set_attr "length" "2,2")
865 (set_attr "cc" "set_zn,set_zn")])
868 [(set (match_operand:HI 0 "register_operand" "")
869 (plus:HI (match_dup 0)
870 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
873 "split_adds_subs (HImode, operands); DONE;")
875 (define_expand "addsi3"
876 [(set (match_operand:SI 0 "register_operand" "")
877 (plus:SI (match_operand:SI 1 "register_operand" "")
878 (match_operand:SI 2 "nonmemory_operand" "")))]
882 (define_insn "addsi_h8300"
883 [(set (match_operand:SI 0 "register_operand" "=r,r")
884 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
885 (match_operand:SI 2 "nonmemory_operand" "n,r")))]
887 "* return output_plussi (operands);"
888 [(set (attr "length")
889 (symbol_ref "compute_plussi_length (operands)"))
891 (symbol_ref "compute_plussi_cc (operands)"))])
893 (define_insn "addsi_h8300h"
894 [(set (match_operand:SI 0 "register_operand" "=r,r")
895 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
896 (match_operand:SI 2 "nonmemory_operand" "i,r")))]
897 "TARGET_H8300H || TARGET_H8300S"
898 "* return output_plussi (operands);"
899 [(set (attr "length")
900 (symbol_ref "compute_plussi_length (operands)"))
902 (symbol_ref "compute_plussi_cc (operands)"))])
904 (define_insn "*addsi3_incdec"
905 [(set (match_operand:SI 0 "register_operand" "=r,r")
906 (unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
907 (match_operand:SI 2 "incdec_operand" "M,O")]
909 "TARGET_H8300H || TARGET_H8300S"
913 [(set_attr "length" "2,2")
914 (set_attr "cc" "set_zn,set_zn")])
917 [(set (match_operand:SI 0 "register_operand" "")
918 (plus:SI (match_dup 0)
919 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
920 "TARGET_H8300H || TARGET_H8300S"
922 "split_adds_subs (SImode, operands); DONE;")
924 ;; ----------------------------------------------------------------------
925 ;; SUBTRACT INSTRUCTIONS
926 ;; ----------------------------------------------------------------------
928 (define_insn "subqi3"
929 [(set (match_operand:QI 0 "register_operand" "=r")
930 (minus:QI (match_operand:QI 1 "register_operand" "0")
931 (match_operand:QI 2 "register_operand" "r")))]
934 [(set_attr "length" "2")
935 (set_attr "cc" "set_zn")])
937 (define_expand "subhi3"
938 [(set (match_operand:HI 0 "register_operand" "")
939 (minus:HI (match_operand:HI 1 "general_operand" "")
940 (match_operand:HI 2 "nonmemory_operand" "")))]
945 [(set (match_operand:HI 0 "register_operand" "=r,&r")
946 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
947 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
951 add.b %E2,%s0\;addx %F2,%t0"
952 [(set_attr "length" "2,4")
953 (set_attr "cc" "set_zn,clobber")])
956 [(set (match_operand:HI 0 "register_operand" "=r,&r")
957 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
958 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
959 "TARGET_H8300H || TARGET_H8300S"
963 [(set_attr "length" "2,4")
964 (set_attr "cc" "set_zn,set_zn")])
966 (define_expand "subsi3"
967 [(set (match_operand:SI 0 "register_operand" "")
968 (minus:SI (match_operand:SI 1 "register_operand" "")
969 (match_operand:SI 2 "nonmemory_operand" "")))]
973 (define_insn "subsi3_h8300"
974 [(set (match_operand:SI 0 "register_operand" "=r")
975 (minus:SI (match_operand:SI 1 "register_operand" "0")
976 (match_operand:SI 2 "register_operand" "r")))]
978 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
979 [(set_attr "length" "6")
980 (set_attr "cc" "clobber")])
982 (define_insn "subsi3_h8300h"
983 [(set (match_operand:SI 0 "register_operand" "=r,r")
984 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
985 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
986 "TARGET_H8300H || TARGET_H8300S"
990 [(set_attr "length" "2,6")
991 (set_attr "cc" "set_zn,set_zn")])
993 ;; ----------------------------------------------------------------------
994 ;; MULTIPLY INSTRUCTIONS
995 ;; ----------------------------------------------------------------------
997 ;; Note that the H8/300 can only handle umulqihi3.
999 (define_insn "mulqihi3"
1000 [(set (match_operand:HI 0 "register_operand" "=r")
1001 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1002 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1003 "TARGET_H8300H || TARGET_H8300S"
1005 [(set_attr "length" "4")
1006 (set_attr "cc" "set_zn")])
1008 (define_insn "mulhisi3"
1009 [(set (match_operand:SI 0 "register_operand" "=r")
1010 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1011 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1012 "TARGET_H8300H || TARGET_H8300S"
1014 [(set_attr "length" "4")
1015 (set_attr "cc" "set_zn")])
1017 (define_insn "umulqihi3"
1018 [(set (match_operand:HI 0 "register_operand" "=r")
1019 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1020 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1023 [(set_attr "length" "2")
1024 (set_attr "cc" "none_0hit")])
1026 (define_insn "umulhisi3"
1027 [(set (match_operand:SI 0 "register_operand" "=r")
1028 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1029 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1030 "TARGET_H8300H || TARGET_H8300S"
1032 [(set_attr "length" "2")
1033 (set_attr "cc" "none_0hit")])
1035 ;; This is a "bridge" instruction. Combine can't cram enough insns
1036 ;; together to crate a MAC instruction directly, but it can create
1037 ;; this instruction, which then allows combine to create the real
1040 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1041 ;; insn must generate reasonably correct code. Egad.
1043 [(set (match_operand:SI 0 "register_operand" "=a")
1046 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1048 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
1050 "clrmac\;mac @%2+,@%1+"
1051 [(set_attr "length" "6")
1052 (set_attr "cc" "none_0hit")])
1055 [(set (match_operand:SI 0 "register_operand" "=a")
1057 (sign_extend:SI (mem:HI
1058 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1059 (sign_extend:SI (mem:HI
1060 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1061 (match_operand:SI 3 "register_operand" "0")))]
1064 [(set_attr "length" "4")
1065 (set_attr "cc" "none_0hit")])
1067 ;; ----------------------------------------------------------------------
1068 ;; DIVIDE/MOD INSTRUCTIONS
1069 ;; ----------------------------------------------------------------------
1071 (define_insn "udivmodqi4"
1072 [(set (match_operand:QI 0 "register_operand" "=r")
1075 (match_operand:HI 1 "register_operand" "0")
1076 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1077 (set (match_operand:QI 3 "register_operand" "=r")
1081 (zero_extend:HI (match_dup 2)))))]
1085 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1086 return \"divxu.b\\t%X2,%T0\";
1088 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1090 [(set_attr "length" "4")
1091 (set_attr "cc" "clobber")])
1093 (define_insn "divmodqi4"
1094 [(set (match_operand:QI 0 "register_operand" "=r")
1097 (match_operand:HI 1 "register_operand" "0")
1098 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1099 (set (match_operand:QI 3 "register_operand" "=r")
1103 (sign_extend:HI (match_dup 2)))))]
1104 "TARGET_H8300H || TARGET_H8300S"
1107 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1108 return \"divxs.b\\t%X2,%T0\";
1110 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1112 [(set_attr "length" "6")
1113 (set_attr "cc" "clobber")])
1115 (define_insn "udivmodhi4"
1116 [(set (match_operand:HI 0 "register_operand" "=r")
1119 (match_operand:SI 1 "register_operand" "0")
1120 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1121 (set (match_operand:HI 3 "register_operand" "=r")
1125 (zero_extend:SI (match_dup 2)))))]
1126 "TARGET_H8300H || TARGET_H8300S"
1129 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1130 return \"divxu.w\\t%T2,%S0\";
1132 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1134 [(set_attr "length" "4")
1135 (set_attr "cc" "clobber")])
1137 (define_insn "divmodhi4"
1138 [(set (match_operand:HI 0 "register_operand" "=r")
1141 (match_operand:SI 1 "register_operand" "0")
1142 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1143 (set (match_operand:HI 3 "register_operand" "=r")
1147 (sign_extend:SI (match_dup 2)))))]
1148 "TARGET_H8300H || TARGET_H8300S"
1151 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1152 return \"divxs.w\\t%T2,%S0\";
1154 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1156 [(set_attr "length" "6")
1157 (set_attr "cc" "clobber")])
1159 ;; ----------------------------------------------------------------------
1161 ;; ----------------------------------------------------------------------
1164 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1165 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1166 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1167 "register_operand (operands[0], QImode)
1168 || single_zero_operand (operands[2], QImode)"
1172 [(set_attr "length" "2,8")
1173 (set_attr "adjust_length" "no")
1174 (set_attr "cc" "set_znv,none_0hit")])
1176 (define_expand "andqi3"
1177 [(set (match_operand:QI 0 "bit_operand" "")
1178 (and:QI (match_operand:QI 1 "bit_operand" "")
1179 (match_operand:QI 2 "nonmemory_operand" "")))]
1183 if (fix_bit_operand (operands, 0, AND))
1187 (define_expand "andhi3"
1188 [(set (match_operand:HI 0 "register_operand" "")
1189 (and:HI (match_operand:HI 1 "register_operand" "")
1190 (match_operand:HI 2 "nonmemory_operand" "")))]
1194 (define_insn "*andorqi3"
1195 [(set (match_operand:QI 0 "register_operand" "=r")
1196 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1197 (match_operand:QI 3 "single_one_operand" "n"))
1198 (match_operand:QI 1 "register_operand" "0")))]
1200 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1201 [(set_attr "length" "6")
1202 (set_attr "cc" "clobber")])
1204 (define_insn "*andorhi3"
1205 [(set (match_operand:HI 0 "register_operand" "=r")
1206 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1207 (match_operand:HI 3 "single_one_operand" "n"))
1208 (match_operand:HI 1 "register_operand" "0")))]
1212 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1213 if (INTVAL (operands[3]) > 128)
1215 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1216 return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\";
1218 return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\";
1220 [(set_attr "length" "6")
1221 (set_attr "cc" "clobber")])
1223 (define_insn "*andorsi3"
1224 [(set (match_operand:SI 0 "register_operand" "=r")
1225 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1226 (match_operand:SI 3 "single_one_operand" "n"))
1227 (match_operand:SI 1 "register_operand" "0")))]
1228 "(INTVAL (operands[3]) & 0xffff) != 0"
1231 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1232 if (INTVAL (operands[3]) > 128)
1234 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1235 return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\";
1237 return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\";
1239 [(set_attr "length" "6")
1240 (set_attr "cc" "clobber")])
1242 (define_insn "*andorsi3_shift_8"
1243 [(set (match_operand:SI 0 "register_operand" "=r")
1244 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1247 (match_operand:SI 1 "register_operand" "0")))]
1250 [(set_attr "length" "2")
1251 (set_attr "cc" "clobber")])
1253 (define_expand "andsi3"
1254 [(set (match_operand:SI 0 "register_operand" "")
1255 (and:SI (match_operand:SI 1 "register_operand" "")
1256 (match_operand:SI 2 "nonmemory_operand" "")))]
1260 ;; ----------------------------------------------------------------------
1262 ;; ----------------------------------------------------------------------
1265 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1266 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1267 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1268 "register_operand (operands[0], QImode)
1269 || single_one_operand (operands[2], QImode)"
1273 [(set_attr "length" "2,8")
1274 (set_attr "adjust_length" "no")
1275 (set_attr "cc" "set_znv,none_0hit")])
1277 (define_expand "iorqi3"
1278 [(set (match_operand:QI 0 "bit_operand" "")
1279 (ior:QI (match_operand:QI 1 "bit_operand" "")
1280 (match_operand:QI 2 "nonmemory_operand" "")))]
1284 if (fix_bit_operand (operands, 1, IOR))
1288 (define_expand "iorhi3"
1289 [(set (match_operand:HI 0 "register_operand" "")
1290 (ior:HI (match_operand:HI 1 "register_operand" "")
1291 (match_operand:HI 2 "nonmemory_operand" "")))]
1295 (define_expand "iorsi3"
1296 [(set (match_operand:SI 0 "register_operand" "")
1297 (ior:SI (match_operand:SI 1 "register_operand" "")
1298 (match_operand:SI 2 "nonmemory_operand" "")))]
1302 ;; ----------------------------------------------------------------------
1304 ;; ----------------------------------------------------------------------
1307 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1308 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1309 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1310 "register_operand (operands[0], QImode)
1311 || single_one_operand (operands[2], QImode)"
1315 [(set_attr "length" "2,8")
1316 (set_attr "adjust_length" "no")
1317 (set_attr "cc" "set_znv,none_0hit")])
1319 (define_expand "xorqi3"
1320 [(set (match_operand:QI 0 "bit_operand" "")
1321 (xor:QI (match_operand:QI 1 "bit_operand" "")
1322 (match_operand:QI 2 "nonmemory_operand" "")))]
1326 if (fix_bit_operand (operands, 1, XOR))
1330 (define_expand "xorhi3"
1331 [(set (match_operand:HI 0 "register_operand" "")
1332 (xor:HI (match_operand:HI 1 "register_operand" "")
1333 (match_operand:HI 2 "nonmemory_operand" "")))]
1337 (define_expand "xorsi3"
1338 [(set (match_operand:SI 0 "register_operand" "")
1339 (xor:SI (match_operand:SI 1 "register_operand" "")
1340 (match_operand:SI 2 "nonmemory_operand" "")))]
1344 ;; ----------------------------------------------------------------------
1345 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1346 ;; ----------------------------------------------------------------------
1349 [(set (match_operand:HI 0 "register_operand" "=r")
1350 (match_operator:HI 3 "bit_operator"
1351 [(match_operand:HI 1 "register_operand" "%0")
1352 (match_operand:HI 2 "nonmemory_operand" "rn")]))]
1354 "* return output_logical_op (HImode, operands);"
1355 [(set (attr "length")
1356 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1358 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1361 [(set (match_operand:SI 0 "register_operand" "=r")
1362 (match_operator:SI 3 "bit_operator"
1363 [(match_operand:SI 1 "register_operand" "%0")
1364 (match_operand:SI 2 "nonmemory_operand" "rn")]))]
1366 "* return output_logical_op (SImode, operands);"
1367 [(set (attr "length")
1368 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1370 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1372 ;; ----------------------------------------------------------------------
1373 ;; NEGATION INSTRUCTIONS
1374 ;; ----------------------------------------------------------------------
1376 (define_insn "negqi2"
1377 [(set (match_operand:QI 0 "register_operand" "=r")
1378 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1381 [(set_attr "length" "2")
1382 (set_attr "cc" "set_zn")])
1384 (define_expand "neghi2"
1385 [(set (match_operand:HI 0 "register_operand" "")
1386 (neg:HI (match_operand:HI 1 "register_operand" "")))]
1392 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1397 (define_expand "neghi2_h8300"
1399 (not:HI (match_operand:HI 1 "register_operand" "")))
1400 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1401 (set (match_operand:HI 0 "register_operand" "")
1404 "operands[2] = gen_reg_rtx (HImode);")
1406 (define_insn "neghi2_h8300h"
1407 [(set (match_operand:HI 0 "register_operand" "=r")
1408 (neg:HI (match_operand:HI 1 "register_operand" "0")))]
1409 "TARGET_H8300H || TARGET_H8300S"
1411 [(set_attr "length" "2")
1412 (set_attr "cc" "set_zn")])
1414 (define_expand "negsi2"
1415 [(set (match_operand:SI 0 "register_operand" "")
1416 (neg:SI (match_operand:SI 1 "register_operand" "")))]
1422 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1427 (define_expand "negsi2_h8300"
1429 (not:SI (match_operand:SI 1 "register_operand" "")))
1430 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1431 (set (match_operand:SI 0 "register_operand" "")
1434 "operands[2] = gen_reg_rtx (SImode);")
1436 (define_insn "negsi2_h8300h"
1437 [(set (match_operand:SI 0 "register_operand" "=r")
1438 (neg:SI (match_operand:SI 1 "register_operand" "0")))]
1439 "TARGET_H8300H || TARGET_H8300S"
1441 [(set_attr "length" "2")
1442 (set_attr "cc" "set_zn")])
1444 (define_expand "negsf2"
1445 [(set (match_operand:SF 0 "register_operand" "")
1446 (neg:SF (match_operand:SF 1 "register_operand" "")))]
1450 (define_insn "*negsf2_h8300"
1451 [(set (match_operand:SF 0 "register_operand" "=r")
1452 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1455 [(set_attr "cc" "clobber")
1456 (set_attr "length" "2")])
1458 (define_insn "*negsf2_h8300hs"
1459 [(set (match_operand:SF 0 "register_operand" "=r")
1460 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1461 "TARGET_H8300H || TARGET_H8300S"
1462 "xor.w\\t#32768,%e0"
1463 [(set_attr "cc" "clobber")
1464 (set_attr "length" "4")])
1466 ;; ----------------------------------------------------------------------
1467 ;; ABSOLUTE VALUE INSTRUCTIONS
1468 ;; ----------------------------------------------------------------------
1470 (define_expand "abssf2"
1471 [(set (match_operand:SF 0 "register_operand" "")
1472 (abs:SF (match_operand:SF 1 "register_operand" "")))]
1476 (define_insn "*abssf2_h8300"
1477 [(set (match_operand:SF 0 "register_operand" "=r")
1478 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1481 [(set_attr "cc" "clobber")
1482 (set_attr "length" "2")])
1484 (define_insn "*abssf2_h8300hs"
1485 [(set (match_operand:SF 0 "register_operand" "=r")
1486 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1487 "TARGET_H8300H || TARGET_H8300S"
1488 "and.w\\t#32767,%e0"
1489 [(set_attr "cc" "clobber")
1490 (set_attr "length" "4")])
1492 ;; ----------------------------------------------------------------------
1494 ;; ----------------------------------------------------------------------
1496 (define_insn "one_cmplqi2"
1497 [(set (match_operand:QI 0 "register_operand" "=r")
1498 (not:QI (match_operand:QI 1 "register_operand" "0")))]
1501 [(set_attr "length" "2")
1502 (set_attr "cc" "set_znv")])
1504 (define_expand "one_cmplhi2"
1505 [(set (match_operand:HI 0 "register_operand" "=r")
1506 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1511 [(set (match_operand:HI 0 "register_operand" "=r")
1512 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1515 [(set_attr "cc" "clobber")
1516 (set_attr "length" "4")])
1519 [(set (match_operand:HI 0 "register_operand" "=r")
1520 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1521 "TARGET_H8300H || TARGET_H8300S"
1523 [(set_attr "cc" "set_znv")
1524 (set_attr "length" "2")])
1526 (define_expand "one_cmplsi2"
1527 [(set (match_operand:SI 0 "register_operand" "=r")
1528 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1533 [(set (match_operand:SI 0 "register_operand" "=r")
1534 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1536 "not %w0\;not %x0\;not %y0\;not %z0"
1537 [(set_attr "cc" "clobber")
1538 (set_attr "length" "8")])
1541 [(set (match_operand:SI 0 "register_operand" "=r")
1542 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1543 "TARGET_H8300H || TARGET_H8300S"
1545 [(set_attr "cc" "set_znv")
1546 (set_attr "length" "2")])
1548 ;; ----------------------------------------------------------------------
1549 ;; JUMP INSTRUCTIONS
1550 ;; ----------------------------------------------------------------------
1552 ;; Conditional jump instructions
1554 (define_expand "ble"
1556 (if_then_else (le (cc0)
1558 (label_ref (match_operand 0 "" ""))
1563 (define_expand "bleu"
1565 (if_then_else (leu (cc0)
1567 (label_ref (match_operand 0 "" ""))
1572 (define_expand "bge"
1574 (if_then_else (ge (cc0)
1576 (label_ref (match_operand 0 "" ""))
1581 (define_expand "bgeu"
1583 (if_then_else (geu (cc0)
1585 (label_ref (match_operand 0 "" ""))
1590 (define_expand "blt"
1592 (if_then_else (lt (cc0)
1594 (label_ref (match_operand 0 "" ""))
1599 (define_expand "bltu"
1601 (if_then_else (ltu (cc0)
1603 (label_ref (match_operand 0 "" ""))
1608 (define_expand "bgt"
1610 (if_then_else (gt (cc0)
1612 (label_ref (match_operand 0 "" ""))
1617 (define_expand "bgtu"
1619 (if_then_else (gtu (cc0)
1621 (label_ref (match_operand 0 "" ""))
1626 (define_expand "beq"
1628 (if_then_else (eq (cc0)
1630 (label_ref (match_operand 0 "" ""))
1635 (define_expand "bne"
1637 (if_then_else (ne (cc0)
1639 (label_ref (match_operand 0 "" ""))
1644 (define_insn "branch_true"
1646 (if_then_else (match_operator 1 "comparison_operator"
1647 [(cc0) (const_int 0)])
1648 (label_ref (match_operand 0 "" ""))
1653 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1654 && (GET_CODE (operands[1]) == GT
1655 || GET_CODE (operands[1]) == GE
1656 || GET_CODE (operands[1]) == LE
1657 || GET_CODE (operands[1]) == LT))
1659 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1663 if (get_attr_length (insn) == 2)
1664 return \"b%j1 %l0\";
1665 else if (get_attr_length (insn) == 4)
1666 return \"b%j1 %l0:16\";
1668 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1670 [(set_attr "type" "branch")
1671 (set_attr "cc" "none")])
1673 (define_insn "branch_false"
1675 (if_then_else (match_operator 1 "comparison_operator"
1676 [(cc0) (const_int 0)])
1678 (label_ref (match_operand 0 "" ""))))]
1682 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1683 && (GET_CODE (operands[1]) == GT
1684 || GET_CODE (operands[1]) == GE
1685 || GET_CODE (operands[1]) == LE
1686 || GET_CODE (operands[1]) == LT))
1688 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1692 if (get_attr_length (insn) == 2)
1693 return \"b%k1 %l0\";
1694 else if (get_attr_length (insn) == 4)
1695 return \"b%k1 %l0:16\";
1697 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1699 [(set_attr "type" "branch")
1700 (set_attr "cc" "none")])
1702 ;; Unconditional and other jump instructions.
1706 (label_ref (match_operand 0 "" "")))]
1710 if (get_attr_length (insn) == 2)
1712 else if (get_attr_length (insn) == 4)
1713 return \"bra %l0:16\";
1715 return \"jmp @%l0\";
1717 [(set_attr "type" "branch")
1718 (set_attr "cc" "none")])
1720 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1722 (define_expand "tablejump"
1723 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
1724 (use (label_ref (match_operand 1 "" "")))])]
1728 (define_insn "tablejump_h8300"
1729 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1730 (use (label_ref (match_operand 1 "" "")))]
1733 [(set_attr "cc" "none")
1734 (set_attr "length" "2")])
1736 (define_insn "tablejump_h8300h"
1737 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1738 (use (label_ref (match_operand 1 "" "")))]
1739 "TARGET_H8300H || TARGET_H8300S"
1741 [(set_attr "cc" "none")
1742 (set_attr "length" "2")])
1744 (define_insn "tablejump_normal_mode"
1745 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1746 (use (label_ref (match_operand 1 "" "")))]
1747 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1749 [(set_attr "cc" "none")
1750 (set_attr "length" "2")])
1752 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1754 (define_expand "indirect_jump"
1755 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1759 (define_insn "indirect_jump_h8300"
1760 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1763 [(set_attr "cc" "none")
1764 (set_attr "length" "2")])
1766 (define_insn "indirect_jump_h8300h"
1767 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1768 "TARGET_H8300H || TARGET_H8300S"
1770 [(set_attr "cc" "none")
1771 (set_attr "length" "2")])
1773 (define_insn "indirect_jump_normal_mode"
1774 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1775 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1777 [(set_attr "cc" "none")
1778 (set_attr "length" "2")])
1780 ;; Call subroutine with no return value.
1782 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1785 [(call (match_operand:QI 0 "call_insn_operand" "or")
1786 (match_operand:HI 1 "general_operand" "g"))]
1790 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1791 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1792 return \"jsr\\t@%0:8\";
1794 return \"jsr\\t%0\";
1796 [(set_attr "cc" "clobber")
1797 (set (attr "length")
1798 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1802 ;; Call subroutine, returning value in operand 0
1803 ;; (which must be a hard register).
1805 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1807 (define_insn "call_value"
1808 [(set (match_operand 0 "" "=r")
1809 (call (match_operand:QI 1 "call_insn_operand" "or")
1810 (match_operand:HI 2 "general_operand" "g")))]
1814 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1815 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1816 return \"jsr\\t@%1:8\";
1818 return \"jsr\\t%1\";
1820 [(set_attr "cc" "clobber")
1821 (set (attr "length")
1822 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1830 [(set_attr "cc" "none")
1831 (set_attr "length" "2")])
1833 ;; ----------------------------------------------------------------------
1834 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
1835 ;; ----------------------------------------------------------------------
1837 (define_expand "push_h8300"
1838 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
1839 (match_operand:HI 0 "register_operand" "=r"))]
1844 (define_expand "push_h8300hs"
1845 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
1846 (match_operand:SI 0 "register_operand" "=r"))]
1847 "TARGET_H8300H && TARGET_H8300S"
1850 (define_expand "pop_h8300"
1851 [(set (match_operand:HI 0 "register_operand" "=r")
1852 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
1856 (define_expand "pop_h8300hs"
1857 [(set (match_operand:SI 0 "register_operand" "=r")
1858 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
1859 "TARGET_H8300H && TARGET_H8300S"
1862 (define_insn "stm_h8300s_2"
1864 [(set (reg:SI SP_REG)
1865 (plus:SI (reg:SI SP_REG) (const_int -8)))
1866 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1867 (match_operand:SI 0 "register_operand" ""))
1868 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1869 (match_operand:SI 1 "register_operand" ""))])]
1871 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
1872 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
1873 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
1874 "stm.l\\t%S0-%S1,@-er7"
1875 [(set_attr "cc" "none")
1876 (set_attr "length" "4")])
1878 (define_insn "stm_h8300s_3"
1880 [(set (reg:SI SP_REG)
1881 (plus:SI (reg:SI SP_REG) (const_int -12)))
1882 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1883 (match_operand:SI 0 "register_operand" ""))
1884 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1885 (match_operand:SI 1 "register_operand" ""))
1886 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1887 (match_operand:SI 2 "register_operand" ""))])]
1889 && ((REGNO (operands[0]) == 0
1890 && REGNO (operands[1]) == 1
1891 && REGNO (operands[2]) == 2)
1892 || (REGNO (operands[0]) == 4
1893 && REGNO (operands[1]) == 5
1894 && REGNO (operands[2]) == 6))"
1895 "stm.l\\t%S0-%S2,@-er7"
1896 [(set_attr "cc" "none")
1897 (set_attr "length" "4")])
1899 (define_insn "stm_h8300s_4"
1901 [(set (reg:SI SP_REG)
1902 (plus:SI (reg:SI SP_REG) (const_int -16)))
1903 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1904 (match_operand:SI 0 "register_operand" ""))
1905 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1906 (match_operand:SI 1 "register_operand" ""))
1907 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1908 (match_operand:SI 2 "register_operand" ""))
1909 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
1910 (match_operand:SI 3 "register_operand" ""))])]
1912 && REGNO (operands[0]) == 0
1913 && REGNO (operands[1]) == 1
1914 && REGNO (operands[2]) == 2
1915 && REGNO (operands[3]) == 3"
1916 "stm.l\\t%S0-%S3,@-er7"
1917 [(set_attr "cc" "none")
1918 (set_attr "length" "4")])
1920 (define_insn "ldm_h8300s_2"
1922 [(set (reg:SI SP_REG)
1923 (plus:SI (reg:SI SP_REG) (const_int 8)))
1924 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
1925 (match_operand:SI 0 "register_operand" ""))
1926 (set (mem:SI (reg:SI SP_REG))
1927 (match_operand:SI 1 "register_operand" ""))])]
1929 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
1930 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
1931 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
1932 "ldm.l\\t@er7+,%S0-%S1"
1933 [(set_attr "cc" "none")
1934 (set_attr "length" "4")])
1936 (define_insn "ldm_h8300s_3"
1938 [(set (reg:SI SP_REG)
1939 (plus:SI (reg:SI SP_REG) (const_int 12)))
1940 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
1941 (match_operand:SI 0 "register_operand" ""))
1942 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
1943 (match_operand:SI 1 "register_operand" ""))
1944 (set (mem:SI (reg:SI SP_REG))
1945 (match_operand:SI 2 "register_operand" ""))])]
1947 && ((REGNO (operands[0]) == 0
1948 && REGNO (operands[1]) == 1
1949 && REGNO (operands[2]) == 2)
1950 || (REGNO (operands[0]) == 4
1951 && REGNO (operands[1]) == 5
1952 && REGNO (operands[2]) == 6))"
1953 "ldm.l\\t@er7+,%S0-%S2"
1954 [(set_attr "cc" "none")
1955 (set_attr "length" "4")])
1957 (define_insn "ldm_h8300s_4"
1959 [(set (reg:SI SP_REG)
1960 (plus:SI (reg:SI SP_REG) (const_int 16)))
1961 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 12)))
1962 (match_operand:SI 0 "register_operand" ""))
1963 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
1964 (match_operand:SI 1 "register_operand" ""))
1965 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
1966 (match_operand:SI 2 "register_operand" ""))
1967 (set (mem:SI (reg:SI SP_REG))
1968 (match_operand:SI 3 "register_operand" ""))])]
1970 && REGNO (operands[0]) == 0
1971 && REGNO (operands[1]) == 1
1972 && REGNO (operands[2]) == 2
1973 && REGNO (operands[3]) == 3"
1974 "ldm.l\\t@er7+,%S0-%S3"
1975 [(set_attr "cc" "none")
1976 (set_attr "length" "4")])
1978 (define_expand "return"
1980 "h8300_can_use_return_insn_p ()"
1983 (define_insn "*return_1"
1988 if (h8300_current_function_interrupt_function_p ())
1993 [(set_attr "cc" "none")
1994 (set_attr "length" "2")])
1996 (define_expand "prologue"
1999 "h8300_expand_prologue (); DONE;")
2001 (define_expand "epilogue"
2004 "h8300_expand_epilogue ();")
2006 (define_insn "monitor_prologue"
2007 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2012 return \"subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr\";
2013 else if (TARGET_H8300H)
2014 return \"mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr\";
2015 else if (TARGET_H8300S)
2016 return \"stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\";
2019 [(set_attr "length" "20")
2020 (set_attr "cc" "clobber")])
2022 ;; ----------------------------------------------------------------------
2023 ;; EXTEND INSTRUCTIONS
2024 ;; ----------------------------------------------------------------------
2026 (define_expand "zero_extendqihi2"
2027 [(set (match_operand:HI 0 "register_operand" "")
2028 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2032 (define_insn "*zero_extendqihi2_h8300"
2033 [(set (match_operand:HI 0 "register_operand" "=r,r")
2034 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2039 [(set_attr "length" "2,10")
2040 (set_attr "cc" "clobber,clobber")])
2042 (define_insn "*zero_extendqihi2_h8300hs"
2043 [(set (match_operand:HI 0 "register_operand" "=r,r")
2044 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2045 "TARGET_H8300H || TARGET_H8300S"
2049 [(set_attr "length" "2,10")
2050 (set_attr "cc" "set_znv,set_znv")])
2052 ;; Split the zero extension of a general operand (actually a memory
2053 ;; operand) into a load of the operand and the actual zero extension
2054 ;; so that 1) the length will be accurate, and 2) the zero extensions
2055 ;; appearing at the end of basic blocks may be merged.
2058 [(set (match_operand:HI 0 "register_operand" "")
2059 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2064 (zero_extend:HI (match_dup 2)))]
2065 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2067 (define_expand "zero_extendqisi2"
2068 [(set (match_operand:SI 0 "register_operand" "")
2069 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2073 (define_insn "*zero_extendqisi2_h8300"
2074 [(set (match_operand:SI 0 "register_operand" "=r,r")
2075 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2078 mov.b #0,%x0\;sub.w %e0,%e0
2079 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
2080 [(set_attr "length" "4,8")
2081 (set_attr "cc" "clobber,clobber")])
2083 (define_insn "*zero_extendqisi2_h8300hs"
2084 [(set (match_operand:SI 0 "register_operand" "=r,r")
2085 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2086 "TARGET_H8300H || TARGET_H8300S"
2090 [(set (match_operand:SI 0 "register_operand" "")
2091 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2092 "(TARGET_H8300H || TARGET_H8300S)
2093 && reg_overlap_mentioned_p (operands[0], operands[1])
2094 && reload_completed"
2098 (zero_extend:HI (match_dup 2)))
2100 (zero_extend:SI (match_dup 3)))]
2101 "operands[2] = gen_lowpart (QImode, operands[0]);
2102 operands[3] = gen_lowpart (HImode, operands[0]);")
2105 [(set (match_operand:SI 0 "register_operand" "")
2106 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2107 "(TARGET_H8300H || TARGET_H8300S)
2108 && !reg_overlap_mentioned_p (operands[0], operands[1])
2109 && reload_completed"
2112 (set (strict_low_part (match_dup 2))
2114 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2116 (define_expand "zero_extendhisi2"
2117 [(set (match_operand:SI 0 "register_operand" "")
2118 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2122 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
2123 (define_insn "*zero_extendhisi2_h8300"
2124 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2125 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
2129 mov.w %f1,%f0\;sub.w %e0,%e0
2130 mov.w %e1,%f0\;sub.w %e0,%e0"
2131 [(set_attr "length" "2,4,6")
2132 (set_attr "cc" "clobber,clobber,clobber")])
2135 [(set (match_operand:SI 0 "register_operand" "=r")
2136 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2137 "TARGET_H8300H || TARGET_H8300S"
2139 [(set_attr "length" "2")
2140 (set_attr "cc" "set_znv")])
2142 (define_expand "extendqihi2"
2143 [(set (match_operand:HI 0 "register_operand" "")
2144 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
2149 [(set (match_operand:HI 0 "register_operand" "=r,r")
2150 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2153 bld #7,%s0\;subx %t0,%t0
2154 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
2155 [(set_attr "length" "4,8")
2156 (set_attr "cc" "clobber,clobber")])
2159 [(set (match_operand:HI 0 "register_operand" "=r")
2160 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
2161 "TARGET_H8300H || TARGET_H8300S"
2163 [(set_attr "length" "2")
2164 (set_attr "cc" "set_znv")])
2166 (define_expand "extendqisi2"
2167 [(set (match_operand:SI 0 "register_operand" "=r,r")
2168 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2172 (define_insn "*extendqisi2_h8300"
2173 [(set (match_operand:SI 0 "register_operand" "")
2174 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2177 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
2178 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
2179 [(set_attr "length" "8,12")
2180 (set_attr "cc" "clobber,clobber")])
2182 ;; The following pattern is needed because without the pattern, the
2183 ;; combiner would split (sign_extend:SI (reg:QI)) into into two 24-bit
2184 ;; shifts, one ashift and one ashiftrt.
2186 (define_insn_and_split "*extendqisi2_h8300hs"
2187 [(set (match_operand:SI 0 "register_operand" "=r")
2188 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2189 "(TARGET_H8300H || TARGET_H8300S)"
2191 "&& reload_completed"
2193 (sign_extend:HI (match_dup 1)))
2195 (sign_extend:SI (match_dup 2)))]
2196 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2198 (define_expand "extendhisi2"
2199 [(set (match_operand:SI 0 "register_operand" "")
2200 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2204 (define_insn "*extendhisi2_h8300"
2205 [(set (match_operand:SI 0 "register_operand" "=r,r")
2206 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
2209 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
2210 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
2211 [(set_attr "length" "6,10")
2212 (set_attr "cc" "clobber,clobber")])
2215 [(set (match_operand:SI 0 "register_operand" "=r")
2216 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2217 "TARGET_H8300H || TARGET_H8300S"
2219 [(set_attr "length" "2")
2220 (set_attr "cc" "set_znv")])
2222 ;; ----------------------------------------------------------------------
2224 ;; ----------------------------------------------------------------------
2226 ;; We make some attempt to provide real efficient shifting. One example is
2227 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
2228 ;; reg and moving 0 into the former reg.
2230 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2231 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2232 ;; give the optimizer more cracks at the code. However, we wish to do things
2233 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
2234 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
2235 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
2236 ;; to detect cases it can optimize.
2238 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2239 ;; easier "do it at insn emit time" route.
2243 (define_expand "ashlqi3"
2244 [(set (match_operand:QI 0 "register_operand" "")
2245 (ashift:QI (match_operand:QI 1 "register_operand" "")
2246 (match_operand:QI 2 "nonmemory_operand" "")))]
2248 "expand_a_shift (QImode, ASHIFT, operands); DONE;")
2250 (define_expand "ashrqi3"
2251 [(set (match_operand:QI 0 "register_operand" "")
2252 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2253 (match_operand:QI 2 "nonmemory_operand" "")))]
2255 "expand_a_shift (QImode, ASHIFTRT, operands); DONE;")
2257 (define_expand "lshrqi3"
2258 [(set (match_operand:QI 0 "register_operand" "")
2259 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2260 (match_operand:QI 2 "nonmemory_operand" "")))]
2262 "expand_a_shift (QImode, LSHIFTRT, operands); DONE;")
2265 [(set (match_operand:QI 0 "register_operand" "=r,r")
2266 (match_operator:QI 3 "nshift_operator"
2267 [ (match_operand:QI 1 "register_operand" "0,0")
2268 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2269 (clobber (match_scratch:QI 4 "=X,&r"))]
2271 "* return output_a_shift (operands);"
2272 [(set (attr "length")
2273 (symbol_ref "compute_a_shift_length (insn, operands)"))
2275 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2279 (define_expand "ashlhi3"
2280 [(set (match_operand:HI 0 "register_operand" "")
2281 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
2282 (match_operand:QI 2 "nonmemory_operand" "")))]
2284 "expand_a_shift (HImode, ASHIFT, operands); DONE;")
2286 (define_expand "lshrhi3"
2287 [(set (match_operand:HI 0 "register_operand" "")
2288 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
2289 (match_operand:QI 2 "nonmemory_operand" "")))]
2291 "expand_a_shift (HImode, LSHIFTRT, operands); DONE;")
2293 (define_expand "ashrhi3"
2294 [(set (match_operand:HI 0 "register_operand" "")
2295 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
2296 (match_operand:QI 2 "nonmemory_operand" "")))]
2298 "expand_a_shift (HImode, ASHIFTRT, operands); DONE;")
2301 [(set (match_operand:HI 0 "register_operand" "=r,r")
2302 (match_operator:HI 3 "nshift_operator"
2303 [ (match_operand:HI 1 "register_operand" "0,0")
2304 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
2305 (clobber (match_scratch:QI 4 "=X,&r"))]
2307 "* return output_a_shift (operands);"
2308 [(set (attr "length")
2309 (symbol_ref "compute_a_shift_length (insn, operands)"))
2311 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2315 (define_expand "ashlsi3"
2316 [(set (match_operand:SI 0 "register_operand" "")
2317 (ashift:SI (match_operand:SI 1 "general_operand" "")
2318 (match_operand:QI 2 "nonmemory_operand" "")))]
2320 "expand_a_shift (SImode, ASHIFT, operands); DONE;")
2322 (define_expand "lshrsi3"
2323 [(set (match_operand:SI 0 "register_operand" "")
2324 (lshiftrt:SI (match_operand:SI 1 "general_operand" "")
2325 (match_operand:QI 2 "nonmemory_operand" "")))]
2327 "expand_a_shift (SImode, LSHIFTRT, operands); DONE;")
2329 (define_expand "ashrsi3"
2330 [(set (match_operand:SI 0 "register_operand" "")
2331 (ashiftrt:SI (match_operand:SI 1 "general_operand" "")
2332 (match_operand:QI 2 "nonmemory_operand" "")))]
2334 "expand_a_shift (SImode, ASHIFTRT, operands); DONE;")
2337 [(set (match_operand:SI 0 "register_operand" "=r,r")
2338 (match_operator:SI 3 "nshift_operator"
2339 [ (match_operand:SI 1 "register_operand" "0,0")
2340 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
2341 (clobber (match_scratch:QI 4 "=X,&r"))]
2343 "* return output_a_shift (operands);"
2344 [(set (attr "length")
2345 (symbol_ref "compute_a_shift_length (insn, operands)"))
2347 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2349 ;; Split a variable shift into a loop. If the register containing
2350 ;; the shift count dies, then we just use that register.
2354 [(set (match_operand 0 "register_operand" "")
2355 (match_operator 2 "nshift_operator"
2357 (match_operand:QI 1 "register_operand" "")]))
2358 (clobber (match_operand:QI 3 "register_operand" ""))])]
2360 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2364 (if_then_else (le (cc0) (const_int 0))
2365 (label_ref (match_dup 5))
2370 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2371 (clobber (scratch:QI))])
2373 (plus:QI (match_dup 1) (const_int -1)))
2377 (if_then_else (ne (cc0) (const_int 0))
2378 (label_ref (match_dup 4))
2381 "operands[4] = gen_label_rtx ();
2382 operands[5] = gen_label_rtx ();")
2386 [(set (match_operand 0 "register_operand" "")
2387 (match_operator 2 "nshift_operator"
2389 (match_operand:QI 1 "register_operand" "")]))
2390 (clobber (match_operand:QI 3 "register_operand" ""))])]
2392 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2398 (if_then_else (le (cc0) (const_int 0))
2399 (label_ref (match_dup 5))
2404 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2405 (clobber (scratch:QI))])
2407 (plus:QI (match_dup 3) (const_int -1)))
2411 (if_then_else (ne (cc0) (const_int 0))
2412 (label_ref (match_dup 4))
2415 "operands[4] = gen_label_rtx ();
2416 operands[5] = gen_label_rtx ();")
2418 ;; ----------------------------------------------------------------------
2420 ;; ----------------------------------------------------------------------
2422 (define_expand "rotlqi3"
2423 [(set (match_operand:QI 0 "register_operand" "")
2424 (rotate:QI (match_operand:QI 1 "register_operand" "")
2425 (match_operand:QI 2 "nonmemory_operand" "")))]
2427 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2429 (define_insn "*rotlqi3_1"
2430 [(set (match_operand:QI 0 "register_operand" "=r")
2431 (rotate:QI (match_operand:QI 1 "register_operand" "0")
2432 (match_operand:QI 2 "immediate_operand" "")))]
2434 "* return emit_a_rotate (ROTATE, operands);"
2435 [(set_attr "length" "20")
2436 (set_attr "cc" "clobber")])
2438 (define_expand "rotlhi3"
2439 [(set (match_operand:HI 0 "register_operand" "")
2440 (rotate:HI (match_operand:HI 1 "register_operand" "")
2441 (match_operand:QI 2 "nonmemory_operand" "")))]
2443 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2445 (define_insn "*rotlhi3_1"
2446 [(set (match_operand:HI 0 "register_operand" "=r")
2447 (rotate:HI (match_operand:HI 1 "register_operand" "0")
2448 (match_operand:QI 2 "immediate_operand" "")))]
2450 "* return emit_a_rotate (ROTATE, operands);"
2451 [(set_attr "length" "20")
2452 (set_attr "cc" "clobber")])
2454 (define_expand "rotlsi3"
2455 [(set (match_operand:SI 0 "register_operand" "")
2456 (rotate:SI (match_operand:SI 1 "register_operand" "")
2457 (match_operand:QI 2 "nonmemory_operand" "")))]
2458 "TARGET_H8300H || TARGET_H8300S"
2459 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2461 (define_insn "*rotlsi3_1"
2462 [(set (match_operand:SI 0 "register_operand" "=r")
2463 (rotate:SI (match_operand:SI 1 "register_operand" "0")
2464 (match_operand:QI 2 "immediate_operand" "")))]
2465 "TARGET_H8300H || TARGET_H8300S"
2466 "* return emit_a_rotate (ROTATE, operands);"
2467 [(set_attr "length" "20")
2468 (set_attr "cc" "clobber")])
2470 ;; -----------------------------------------------------------------
2472 ;; -----------------------------------------------------------------
2473 ;; The H8/300 has given 1/8th of its opcode space to bitfield
2474 ;; instructions so let's use them as well as we can.
2476 ;; You'll never believe all these patterns perform one basic action --
2477 ;; load a bit from the source, optionally invert the bit, then store it
2478 ;; in the destination (which is known to be zero).
2480 ;; Combine obviously need some work to better identify this situation and
2481 ;; canonicalize the form better.
2484 ;; Normal loads with a 16bit destination.
2488 [(set (match_operand:HI 0 "register_operand" "=&r")
2489 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2491 (match_operand:HI 2 "immediate_operand" "n")))]
2493 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
2494 [(set_attr "cc" "clobber")
2495 (set_attr "length" "6")])
2498 ;; Inverted loads with a 16bit destination.
2502 [(set (match_operand:HI 0 "register_operand" "=&r")
2503 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
2504 (match_operand:HI 3 "const_int_operand" "n"))
2506 (match_operand:HI 2 "const_int_operand" "n")))]
2508 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2509 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2510 [(set_attr "cc" "clobber")
2511 (set_attr "length" "8")])
2514 ;; Normal loads with a 32bit destination.
2517 (define_insn "*extzv_1_r_h8300"
2518 [(set (match_operand:SI 0 "register_operand" "=&r")
2519 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2521 (match_operand 2 "const_int_operand" "n")))]
2523 && INTVAL (operands[2]) < 16"
2524 "* return output_simode_bld (0, operands);"
2525 [(set_attr "cc" "clobber")
2526 (set_attr "length" "8")])
2528 (define_insn "*extzv_1_r_h8300hs"
2529 [(set (match_operand:SI 0 "register_operand" "=r,r")
2530 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2532 (match_operand 2 "const_int_operand" "n,n")))]
2533 "(TARGET_H8300H || TARGET_H8300S)
2534 && INTVAL (operands[2]) < 16"
2535 "* return output_simode_bld (0, operands);"
2536 [(set_attr "cc" "clobber,clobber")
2537 (set_attr "length" "8,6")])
2540 ;; Inverted loads with a 32bit destination.
2543 (define_insn "*extzv_1_r_inv_h8300"
2544 [(set (match_operand:SI 0 "register_operand" "=&r")
2545 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2546 (match_operand:HI 3 "const_int_operand" "n"))
2548 (match_operand 2 "const_int_operand" "n")))]
2550 && INTVAL (operands[2]) < 16
2551 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2552 "* return output_simode_bld (1, operands);"
2553 [(set_attr "cc" "clobber")
2554 (set_attr "length" "8")])
2556 (define_insn "*extzv_1_r_inv_h8300hs"
2557 [(set (match_operand:SI 0 "register_operand" "=r,r")
2558 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
2559 (match_operand 3 "const_int_operand" "n,n"))
2561 (match_operand 2 "const_int_operand" "n,n")))]
2562 "(TARGET_H8300H || TARGET_H8300S)
2563 && INTVAL (operands[2]) < 16
2564 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2565 "* return output_simode_bld (1, operands);"
2566 [(set_attr "cc" "clobber,clobber")
2567 (set_attr "length" "8,6")])
2569 (define_expand "insv"
2570 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2571 (match_operand:HI 1 "general_operand" "")
2572 (match_operand:HI 2 "general_operand" ""))
2573 (match_operand:HI 3 "general_operand" ""))]
2577 /* We only have single bit bit-field instructions. */
2578 if (INTVAL (operands[1]) != 1)
2581 /* For now, we don't allow memory operands. */
2582 if (GET_CODE (operands[0]) == MEM
2583 || GET_CODE (operands[3]) == MEM)
2588 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2590 (match_operand:HI 1 "immediate_operand" "n"))
2591 (match_operand:HI 2 "register_operand" "r"))]
2593 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2594 [(set_attr "cc" "clobber")
2595 (set_attr "length" "4")])
2597 (define_expand "extzv"
2598 [(set (match_operand:HI 0 "register_operand" "")
2599 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2600 (match_operand:HI 2 "general_operand" "")
2601 (match_operand:HI 3 "general_operand" "")))]
2605 /* We only have single bit bit-field instructions. */
2606 if (INTVAL (operands[2]) != 1)
2609 /* For now, we don't allow memory operands. */
2610 if (GET_CODE (operands[1]) == MEM)
2614 ;; BAND, BOR, and BXOR patterns
2617 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2618 (match_operator:HI 4 "bit_operator"
2619 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2621 (match_operand:HI 2 "immediate_operand" "n"))
2622 (match_operand:HI 3 "bit_operand" "0")]))]
2624 "bld %Z2,%Y1\;%b4 #0,%R0\;bst #0,%R0; bl1"
2625 [(set_attr "cc" "clobber")
2626 (set_attr "length" "6")
2627 (set_attr "adjust_length" "no")])
2630 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2631 (match_operator:HI 5 "bit_operator"
2632 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2634 (match_operand:HI 2 "immediate_operand" "n"))
2635 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2637 (match_operand:HI 4 "immediate_operand" "n"))]))]
2639 "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%R0; bl3"
2640 [(set_attr "cc" "clobber")
2641 (set_attr "length" "6")
2642 (set_attr "adjust_length" "no")])
2644 ;; -----------------------------------------------------------------
2646 ;; -----------------------------------------------------------------
2650 (define_insn "*insv_si_1_n"
2651 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2653 (match_operand:SI 1 "const_int_operand" "n"))
2654 (match_operand:SI 2 "register_operand" "r"))]
2655 "(TARGET_H8300H || TARGET_H8300S)
2656 && INTVAL (operands[1]) < 16"
2657 "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
2658 [(set_attr "cc" "clobber")
2659 (set_attr "length" "4")])
2661 (define_insn "*insv_si_1_n_lshiftrt"
2662 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2664 (match_operand:SI 1 "const_int_operand" "n"))
2665 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2666 (match_operand:SI 3 "const_int_operand" "n")))]
2667 "(TARGET_H8300H || TARGET_H8300S)
2668 && INTVAL (operands[1]) < 16
2669 && INTVAL (operands[3]) < 16"
2670 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
2671 [(set_attr "cc" "clobber")
2672 (set_attr "length" "4")])
2674 (define_insn "*insv_si_1_n_lshiftrt_16"
2675 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2677 (match_operand:SI 1 "const_int_operand" "n"))
2678 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2680 "(TARGET_H8300H || TARGET_H8300S)
2681 && INTVAL (operands[1]) < 16"
2682 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
2683 [(set_attr "cc" "clobber")
2684 (set_attr "length" "6")])
2686 (define_insn "*insv_si_8_8"
2687 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2690 (match_operand:SI 1 "register_operand" "r"))]
2691 "TARGET_H8300H || TARGET_H8300S"
2693 [(set_attr "cc" "clobber")
2694 (set_attr "length" "2")])
2696 (define_insn "*insv_si_8_8_lshiftrt_8"
2697 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2700 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2702 "TARGET_H8300H || TARGET_H8300S"
2704 [(set_attr "cc" "clobber")
2705 (set_attr "length" "2")])
2709 (define_insn "*extzv_8_8"
2710 [(set (match_operand:SI 0 "register_operand" "=r,r")
2711 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2714 "TARGET_H8300H || TARGET_H8300S"
2716 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
2717 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
2718 [(set_attr "cc" "set_znv,clobber")
2719 (set_attr "length" "6,4")])
2721 (define_insn "*extzv_8_16"
2722 [(set (match_operand:SI 0 "register_operand" "=r")
2723 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2726 "TARGET_H8300H || TARGET_H8300S"
2727 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
2728 [(set_attr "cc" "set_znv")
2729 (set_attr "length" "6")])
2731 (define_insn "*extzv_16_8"
2732 [(set (match_operand:SI 0 "register_operand" "=r")
2733 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2736 (clobber (match_scratch:SI 2 "=&r"))]
2738 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
2739 [(set_attr "length" "8")
2740 (set_attr "cc" "set_znv")])
2742 ;; Extract the exponent of a float.
2744 (define_insn_and_split "*extzv_8_23"
2745 [(set (match_operand:SI 0 "register_operand" "=r")
2746 (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
2749 "(TARGET_H8300H || TARGET_H8300S)"
2751 "&& reload_completed"
2752 [(parallel [(set (match_dup 0)
2753 (ashift:SI (match_dup 0)
2755 (clobber (scratch:QI))])
2756 (parallel [(set (match_dup 0)
2757 (lshiftrt:SI (match_dup 0)
2759 (clobber (scratch:QI))])]
2764 ;; ((SImode) HImode) << 15
2766 (define_insn_and_split "*twoshifts_l16_r1"
2767 [(set (match_operand:SI 0 "register_operand" "=r")
2768 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2770 (const_int 2147450880)))]
2771 "(TARGET_H8300H || TARGET_H8300S)"
2773 "&& reload_completed"
2774 [(parallel [(set (match_dup 0)
2775 (ashift:SI (match_dup 0)
2777 (clobber (scratch:QI))])
2778 (parallel [(set (match_dup 0)
2779 (lshiftrt:SI (match_dup 0)
2781 (clobber (scratch:QI))])]
2784 ;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
2786 (define_insn_and_split "*andsi3_ashift_n_lower"
2787 [(set (match_operand:SI 0 "register_operand" "=r,r")
2788 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
2789 (match_operand:QI 2 "const_int_operand" "S,n"))
2790 (match_operand:SI 3 "const_int_operand" "n,n")))
2791 (clobber (match_scratch:QI 4 "=X,&r"))]
2792 "(TARGET_H8300H || TARGET_H8300S)
2793 && INTVAL (operands[2]) <= 15
2794 && INTVAL (operands[3]) == ((-1 << INTVAL (operands[2])) & 0xffff)"
2796 "&& reload_completed"
2797 [(parallel [(set (match_dup 5)
2798 (ashift:HI (match_dup 5)
2800 (clobber (match_dup 4))])
2802 (zero_extend:SI (match_dup 5)))]
2803 "operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2805 ;; Accept (A >> 30) & 2 and the like.
2807 (define_insn "*andsi3_lshiftrt_n_sb"
2808 [(set (match_operand:SI 0 "register_operand" "=r")
2809 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
2810 (match_operand:SI 2 "const_int_operand" "n"))
2811 (match_operand:SI 3 "single_one_operand" "n")))]
2812 "(TARGET_H8300H || TARGET_H8300S)
2813 && exact_log2 (INTVAL (operands[3])) < 16
2814 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
2817 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
2818 return \"shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0\";
2820 [(set_attr "length" "8")
2821 (set_attr "cc" "clobber")])
2823 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
2824 [(set (match_operand:SI 0 "register_operand" "=r")
2825 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
2827 (const_int 4194304)))]
2828 "(TARGET_H8300H || TARGET_H8300S)"
2830 "&& reload_completed"
2832 (and:SI (lshiftrt:SI (match_dup 0)
2835 (parallel [(set (match_dup 0)
2836 (ashift:SI (match_dup 0)
2838 (clobber (scratch:QI))])]
2843 (define_insn "*addsi3_upper"
2844 [(set (match_operand:SI 0 "register_operand" "=r")
2845 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
2847 (match_operand:SI 2 "register_operand" "0")))]
2848 "TARGET_H8300H || TARGET_H8300S"
2850 [(set_attr "length" "2")
2851 (set_attr "cc" "clobber")])
2853 (define_insn "*addsi3_lshiftrt_16_zexthi"
2854 [(set (match_operand:SI 0 "register_operand" "=r")
2855 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2857 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
2858 "TARGET_H8300H || TARGET_H8300S"
2859 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0,%e0"
2860 [(set_attr "cc" "clobber")
2861 (set_attr "length" "6")])
2863 (define_insn_and_split "*addsi3_and_r_1"
2864 [(set (match_operand:SI 0 "register_operand" "=r")
2865 (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
2867 (match_operand:SI 2 "register_operand" "0")))]
2868 "(TARGET_H8300H || TARGET_H8300S)"
2870 "&& reload_completed"
2872 (zero_extract:SI (match_dup 1)
2876 (if_then_else (eq (cc0)
2878 (label_ref (match_dup 3))
2881 (plus:SI (match_dup 2)
2884 "operands[3] = gen_label_rtx ();")
2886 (define_insn_and_split "*addsi3_and_not_r_1"
2887 [(set (match_operand:SI 0 "register_operand" "=r")
2888 (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
2890 (match_operand:SI 2 "register_operand" "0")))]
2891 "(TARGET_H8300H || TARGET_H8300S)"
2893 "&& reload_completed"
2895 (zero_extract:SI (match_dup 1)
2899 (if_then_else (ne (cc0)
2901 (label_ref (match_dup 3))
2904 (plus:SI (match_dup 2)
2907 "operands[3] = gen_label_rtx ();")
2911 (define_insn "*ixorhi3_zext"
2912 [(set (match_operand:HI 0 "register_operand" "=r")
2913 (match_operator:HI 1 "iorxor_operator"
2914 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
2915 (match_operand:HI 3 "register_operand" "0")]))]
2918 [(set_attr "cc" "clobber")
2919 (set_attr "length" "2")])
2923 (define_insn "*ixorsi3_zext_qi"
2924 [(set (match_operand:SI 0 "register_operand" "=r")
2925 (match_operator:SI 1 "iorxor_operator"
2926 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
2927 (match_operand:SI 3 "register_operand" "0")]))]
2930 [(set_attr "cc" "clobber")
2931 (set_attr "length" "2")])
2933 (define_insn "*ixorsi3_zext_hi"
2934 [(set (match_operand:SI 0 "register_operand" "=r")
2935 (match_operator:SI 1 "iorxor_operator"
2936 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
2937 (match_operand:SI 3 "register_operand" "0")]))]
2938 "TARGET_H8300H || TARGET_H8300S"
2940 [(set_attr "cc" "clobber")
2941 (set_attr "length" "2")])
2943 (define_insn "*ixorsi3_ashift_16"
2944 [(set (match_operand:SI 0 "register_operand" "=r")
2945 (match_operator:SI 1 "iorxor_operator"
2946 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
2948 (match_operand:SI 3 "register_operand" "0")]))]
2949 "TARGET_H8300H || TARGET_H8300S"
2951 [(set_attr "cc" "clobber")
2952 (set_attr "length" "2")])
2954 (define_insn "*ixorsi3_lshiftrt_16"
2955 [(set (match_operand:SI 0 "register_operand" "=r")
2956 (match_operator:SI 1 "iorxor_operator"
2957 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2959 (match_operand:SI 3 "register_operand" "0")]))]
2960 "TARGET_H8300H || TARGET_H8300S"
2962 [(set_attr "cc" "clobber")
2963 (set_attr "length" "2")])
2967 (define_insn "*iorhi3_ashift_8"
2968 [(set (match_operand:HI 0 "register_operand" "=r")
2969 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
2971 (match_operand:HI 2 "register_operand" "0")))]
2974 [(set_attr "cc" "clobber")
2975 (set_attr "length" "2")])
2977 (define_insn "*iorhi3_lshiftrt_8"
2978 [(set (match_operand:HI 0 "register_operand" "=r")
2979 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
2981 (match_operand:HI 2 "register_operand" "0")))]
2984 [(set_attr "cc" "clobber")
2985 (set_attr "length" "2")])
2987 (define_insn "*iorhi3_two_qi"
2988 [(set (match_operand:HI 0 "register_operand" "=r")
2989 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
2990 (ashift:HI (match_operand:HI 2 "register_operand" "r")
2994 [(set_attr "cc" "clobber")
2995 (set_attr "length" "2")])
2997 (define_insn "*iorhi3_two_qi_mem"
2998 [(set (match_operand:HI 0 "register_operand" "=&r")
2999 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
3000 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
3003 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
3004 [(set_attr "cc" "clobber")
3005 (set_attr "length" "16")])
3008 [(set (match_operand:HI 0 "register_operand" "")
3009 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
3010 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
3012 "(TARGET_H8300H || TARGET_H8300S)
3014 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
3017 "operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));")
3021 (define_insn "*iorsi3_two_hi"
3022 [(set (match_operand:SI 0 "register_operand" "=r")
3023 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
3024 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3026 "TARGET_H8300H || TARGET_H8300S"
3028 [(set_attr "cc" "clobber")
3029 (set_attr "length" "2")])
3031 (define_insn_and_split "*iorsi3_two_qi_zext"
3032 [(set (match_operand:SI 0 "register_operand" "=&r")
3033 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
3035 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3037 (const_int 65280))))]
3038 "(TARGET_H8300H || TARGET_H8300S)"
3040 "&& reload_completed"
3042 (ior:HI (zero_extend:HI (match_dup 1))
3043 (ashift:HI (subreg:HI (match_dup 2) 0)
3046 (zero_extend:SI (match_dup 3)))]
3047 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3049 (define_insn "*iorsi3_e2f"
3050 [(set (match_operand:SI 0 "register_operand" "=r")
3051 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3053 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3055 "TARGET_H8300H || TARGET_H8300S"
3057 [(set_attr "length" "2")
3058 (set_attr "cc" "clobber")])
3060 (define_insn_and_split "*iorsi3_two_qi_sext"
3061 [(set (match_operand:SI 0 "register_operand" "=r")
3062 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
3063 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
3065 "(TARGET_H8300H || TARGET_H8300S)"
3067 "&& reload_completed"
3069 (ior:HI (zero_extend:HI (match_dup 1))
3070 (ashift:HI (match_dup 4)
3073 (sign_extend:SI (match_dup 3)))]
3074 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3075 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3077 (define_insn "*iorsi3_w"
3078 [(set (match_operand:SI 0 "register_operand" "=r,&r")
3079 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
3081 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
3082 "TARGET_H8300H || TARGET_H8300S"
3084 [(set_attr "length" "2,8")
3085 (set_attr "cc" "clobber,clobber")])
3087 (define_insn "*iorsi3_ashift_31"
3088 [(set (match_operand:SI 0 "register_operand" "=&r")
3089 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3091 (match_operand:SI 2 "register_operand" "0")))]
3092 "TARGET_H8300H || TARGET_H8300S"
3093 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
3094 [(set_attr "length" "6")
3095 (set_attr "cc" "set_znv")])
3097 (define_insn "*iorsi3_and_ashift"
3098 [(set (match_operand:SI 0 "register_operand" "=r")
3099 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3100 (match_operand:SI 2 "const_int_operand" "n"))
3101 (match_operand:SI 3 "single_one_operand" "n"))
3102 (match_operand:SI 4 "register_operand" "0")))]
3103 "(TARGET_H8300H || TARGET_H8300S)
3104 && (INTVAL (operands[3]) & ~0xffff) == 0"
3107 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3108 - INTVAL (operands[2]));
3109 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3110 operands[2] = srcpos;
3111 operands[3] = dstpos;
3112 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
3114 [(set_attr "length" "6")
3115 (set_attr "cc" "clobber")])
3117 (define_insn "*iorsi3_and_lshiftrt"
3118 [(set (match_operand:SI 0 "register_operand" "=r")
3119 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3120 (match_operand:SI 2 "const_int_operand" "n"))
3121 (match_operand:SI 3 "single_one_operand" "n"))
3122 (match_operand:SI 4 "register_operand" "0")))]
3123 "(TARGET_H8300H || TARGET_H8300S)
3124 && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
3127 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3128 + INTVAL (operands[2]));
3129 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3130 operands[2] = srcpos;
3131 operands[3] = dstpos;
3132 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
3134 [(set_attr "length" "6")
3135 (set_attr "cc" "clobber")])
3137 (define_insn "*iorsi3_zero_extract"
3138 [(set (match_operand:SI 0 "register_operand" "=r")
3139 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3141 (match_operand:SI 2 "const_int_operand" "n"))
3142 (match_operand:SI 3 "register_operand" "0")))]
3143 "(TARGET_H8300H || TARGET_H8300S)
3144 && INTVAL (operands[2]) < 16"
3145 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
3146 [(set_attr "length" "6")
3147 (set_attr "cc" "clobber")])
3149 (define_insn "*iorsi3_and_lshiftrt_n_sb"
3150 [(set (match_operand:SI 0 "register_operand" "=r")
3151 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3154 (match_operand:SI 2 "register_operand" "0")))]
3155 "(TARGET_H8300H || TARGET_H8300S)"
3156 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
3157 [(set_attr "length" "8")
3158 (set_attr "cc" "clobber")])
3160 (define_insn "*iorsi3_and_lshiftrt_9_sb"
3161 [(set (match_operand:SI 0 "register_operand" "=r")
3162 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3164 (const_int 4194304))
3165 (match_operand:SI 2 "register_operand" "0")))
3166 (clobber (match_scratch:HI 3 "=&r"))]
3167 "(TARGET_H8300H || TARGET_H8300S)"
3170 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3171 return \"shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3173 return \"rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3175 [(set_attr "length" "10")
3176 (set_attr "cc" "clobber")])
3178 ;; Used to OR the exponent of a float.
3180 (define_insn "*iorsi3_shift"
3181 [(set (match_operand:SI 0 "register_operand" "=r")
3182 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3184 (match_operand:SI 2 "register_operand" "0")))
3185 (clobber (match_scratch:SI 3 "=&r"))]
3186 "TARGET_H8300H || TARGET_H8300S"
3191 [(set (match_operand:SI 0 "register_operand" "")
3192 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3195 (clobber (match_operand:SI 2 "register_operand" ""))])]
3196 "(TARGET_H8300H || TARGET_H8300S)
3198 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3199 && REGNO (operands[0]) != REGNO (operands[1])"
3200 [(parallel [(set (match_dup 3)
3201 (ashift:HI (match_dup 3)
3203 (clobber (scratch:QI))])
3205 (ior:SI (ashift:SI (match_dup 1)
3208 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3212 [(set (match_operand:SI 0 "register_operand" "")
3213 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3216 (clobber (match_operand:SI 2 "register_operand" ""))])]
3217 "(TARGET_H8300H || TARGET_H8300S)
3219 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3220 && REGNO (operands[0]) != REGNO (operands[1]))"
3223 (parallel [(set (match_dup 3)
3224 (ashift:HI (match_dup 3)
3226 (clobber (scratch:QI))])
3228 (ior:SI (ashift:SI (match_dup 2)
3231 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3233 (define_insn "*iorsi2_and_1_lshiftrt_1"
3234 [(set (match_operand:SI 0 "register_operand" "=r")
3235 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3237 (lshiftrt:SI (match_dup 1)
3239 "TARGET_H8300H || TARGET_H8300S"
3240 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
3241 [(set_attr "length" "6")
3242 (set_attr "cc" "clobber")])
3244 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
3245 [(set (match_operand:SI 0 "register_operand" "=r")
3246 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3248 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3250 "(TARGET_H8300H || TARGET_H8300S)"
3252 "&& reload_completed"
3254 (ior:HI (ashift:HI (match_dup 4)
3257 (parallel [(set (match_dup 0)
3258 (ashift:SI (match_dup 0)
3260 (clobber (scratch:QI))])]
3261 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3262 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3264 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
3265 [(set (match_operand:SI 0 "register_operand" "=&r")
3266 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
3268 (const_int 16711680))
3269 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3271 "(TARGET_H8300H || TARGET_H8300S)"
3273 "&& reload_completed"
3275 (ior:HI (zero_extend:HI (match_dup 1))
3276 (ashift:HI (subreg:HI (match_dup 2) 0)
3278 (parallel [(set (match_dup 0)
3279 (ashift:SI (match_dup 0)
3281 (clobber (scratch:QI))])]
3282 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3284 ;; Used to add the exponent of a float.
3286 (define_insn "*addsi3_shift"
3287 [(set (match_operand:SI 0 "register_operand" "=r")
3288 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3289 (const_int 8388608))
3290 (match_operand:SI 2 "register_operand" "0")))
3291 (clobber (match_scratch:SI 3 "=&r"))]
3292 "TARGET_H8300H || TARGET_H8300S"
3297 [(set (match_operand:SI 0 "register_operand" "")
3298 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3299 (const_int 8388608))
3301 (clobber (match_operand:SI 2 "register_operand" ""))])]
3302 "(TARGET_H8300H || TARGET_H8300S)
3304 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3305 && REGNO (operands[0]) != REGNO (operands[1])"
3306 [(parallel [(set (match_dup 3)
3307 (ashift:HI (match_dup 3)
3309 (clobber (scratch:QI))])
3311 (plus:SI (mult:SI (match_dup 1)
3314 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3318 [(set (match_operand:SI 0 "register_operand" "")
3319 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3320 (const_int 8388608))
3322 (clobber (match_operand:SI 2 "register_operand" ""))])]
3323 "(TARGET_H8300H || TARGET_H8300S)
3325 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3326 && REGNO (operands[0]) != REGNO (operands[1]))"
3329 (parallel [(set (match_dup 3)
3330 (ashift:HI (match_dup 3)
3332 (clobber (scratch:QI))])
3334 (plus:SI (mult:SI (match_dup 2)
3337 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3341 (define_insn_and_split "*ashiftsi_sextqi_7"
3342 [(set (match_operand:SI 0 "register_operand" "=r")
3343 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
3345 "(TARGET_H8300H || TARGET_H8300S)"
3347 "&& reload_completed"
3348 [(parallel [(set (match_dup 2)
3349 (ashift:HI (match_dup 2)
3351 (clobber (scratch:QI))])
3353 (sign_extend:SI (match_dup 2)))
3354 (parallel [(set (match_dup 0)
3355 (ashiftrt:SI (match_dup 0)
3357 (clobber (scratch:QI))])]
3358 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3360 ;; Storing a part of HImode to QImode.
3363 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3364 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3368 [(set_attr "cc" "set_znv")
3369 (set_attr "length" "8")])
3371 ;; Storing a part of SImode to QImode.
3374 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3375 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3379 [(set_attr "cc" "set_znv")
3380 (set_attr "length" "8")])
3383 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3384 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3386 (clobber (match_scratch:SI 2 "=&r"))]
3387 "TARGET_H8300H || TARGET_H8300S"
3388 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
3389 [(set_attr "cc" "set_znv")
3390 (set_attr "length" "10")])
3393 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3394 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3396 (clobber (match_scratch:SI 2 "=&r"))]
3397 "TARGET_H8300H || TARGET_H8300S"
3398 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
3399 [(set_attr "cc" "set_znv")
3400 (set_attr "length" "10")])
3402 (define_insn_and_split ""
3404 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3408 (label_ref (match_operand 1 "" ""))
3416 (if_then_else (ge (cc0)
3418 (label_ref (match_dup 1))
3422 (define_insn_and_split ""
3424 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3428 (label_ref (match_operand 1 "" ""))
3436 (if_then_else (lt (cc0)
3438 (label_ref (match_dup 1))
3442 ;; -----------------------------------------------------------------
3443 ;; PEEPHOLE PATTERNS
3444 ;; -----------------------------------------------------------------
3446 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3450 [(set (match_operand:HI 0 "register_operand" "")
3451 (lshiftrt:HI (match_dup 0)
3452 (match_operand:HI 1 "const_int_operand" "")))
3453 (clobber (match_operand:HI 2 "" ""))])
3455 (and:HI (match_dup 0)
3456 (match_operand:HI 3 "const_int_operand" "")))]
3457 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3459 (and:HI (match_dup 0)
3463 (lshiftrt:HI (match_dup 0)
3465 (clobber (match_dup 2))])]
3468 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3472 [(set (match_operand:HI 0 "register_operand" "")
3473 (ashift:HI (match_dup 0)
3474 (match_operand:HI 1 "const_int_operand" "")))
3475 (clobber (match_operand:HI 2 "" ""))])
3477 (and:HI (match_dup 0)
3478 (match_operand:HI 3 "const_int_operand" "")))]
3479 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3481 (and:HI (match_dup 0)
3485 (ashift:HI (match_dup 0)
3487 (clobber (match_dup 2))])]
3490 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3494 [(set (match_operand:SI 0 "register_operand" "")
3495 (lshiftrt:SI (match_dup 0)
3496 (match_operand:SI 1 "const_int_operand" "")))
3497 (clobber (match_operand:SI 2 "" ""))])
3499 (and:SI (match_dup 0)
3500 (match_operand:SI 3 "const_int_operand" "")))]
3501 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3503 (and:SI (match_dup 0)
3507 (lshiftrt:SI (match_dup 0)
3509 (clobber (match_dup 2))])]
3512 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3516 [(set (match_operand:SI 0 "register_operand" "")
3517 (ashift:SI (match_dup 0)
3518 (match_operand:SI 1 "const_int_operand" "")))
3519 (clobber (match_operand:SI 2 "" ""))])
3521 (and:SI (match_dup 0)
3522 (match_operand:SI 3 "const_int_operand" "")))]
3523 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3525 (and:SI (match_dup 0)
3529 (ashift:SI (match_dup 0)
3531 (clobber (match_dup 2))])]
3534 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
3538 [(set (match_operand:SI 0 "register_operand" "")
3539 (lshiftrt:SI (match_dup 0)
3540 (match_operand:SI 1 "const_int_operand" "")))
3541 (clobber (match_operand:SI 2 "" ""))])
3543 (and:SI (match_dup 0)
3544 (match_operand:SI 3 "const_int_operand" "")))]
3545 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
3547 (and:SI (match_dup 0)
3551 (lshiftrt:SI (match_dup 0)
3553 (clobber (match_dup 2))])]
3556 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
3560 [(set (match_operand:SI 0 "register_operand" "")
3561 (ashift:SI (match_dup 0)
3562 (match_operand:SI 1 "const_int_operand" "")))
3563 (clobber (match_operand:SI 2 "" ""))])
3565 (and:SI (match_dup 0)
3566 (match_operand:SI 3 "const_int_operand" "")))]
3567 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
3569 (and:SI (match_dup 0)
3573 (ashift:SI (match_dup 0)
3575 (clobber (match_dup 2))])]
3578 ;; Convert a QImode push into an SImode push so that the
3579 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3582 [(parallel [(set (reg:SI SP_REG)
3583 (plus:SI (reg:SI SP_REG) (const_int -4)))
3584 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
3585 (match_operand:QI 0 "register_operand" ""))])]
3587 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3589 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3591 ;; Convert a HImode push into an SImode push so that the
3592 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3595 [(parallel [(set (reg:SI SP_REG)
3596 (plus:SI (reg:SI SP_REG) (const_int -4)))
3597 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
3598 (match_operand:HI 0 "register_operand" ""))])]
3600 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3602 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3604 ;; Cram four pushes into stm.l.
3607 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3608 (match_operand:SI 0 "register_operand" ""))
3609 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3610 (match_operand:SI 1 "register_operand" ""))
3611 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3612 (match_operand:SI 2 "register_operand" ""))
3613 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3614 (match_operand:SI 3 "register_operand" ""))]
3616 && REGNO (operands[0]) == 0
3617 && REGNO (operands[1]) == 1
3618 && REGNO (operands[2]) == 2
3619 && REGNO (operands[3]) == 3"
3620 [(parallel [(set (reg:SI SP_REG)
3621 (plus:SI (reg:SI SP_REG)
3623 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3625 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3627 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3629 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
3633 ;; Cram three pushes into stm.l.
3636 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3637 (match_operand:SI 0 "register_operand" ""))
3638 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3639 (match_operand:SI 1 "register_operand" ""))
3640 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3641 (match_operand:SI 2 "register_operand" ""))]
3643 && ((REGNO (operands[0]) == 0
3644 && REGNO (operands[1]) == 1
3645 && REGNO (operands[2]) == 2)
3646 || (REGNO (operands[0]) == 4
3647 && REGNO (operands[1]) == 5
3648 && REGNO (operands[2]) == 6))"
3649 [(parallel [(set (reg:SI SP_REG)
3650 (plus:SI (reg:SI SP_REG)
3652 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3654 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3656 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3660 ;; Cram two pushes into stm.l.
3663 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3664 (match_operand:SI 0 "register_operand" ""))
3665 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3666 (match_operand:SI 1 "register_operand" ""))]
3668 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
3669 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
3670 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
3671 [(parallel [(set (reg:SI SP_REG)
3672 (plus:SI (reg:SI SP_REG)
3674 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3676 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3683 ;; add.w r7,r0 (6 bytes)
3688 ;; adds #2,r0 (4 bytes)
3691 [(set (match_operand:HI 0 "register_operand" "")
3692 (match_operand:HI 1 "const_int_operand" ""))
3694 (plus:HI (match_dup 0)
3695 (match_operand:HI 2 "register_operand" "")))]
3696 "REG_P (operands[0]) && REG_P (operands[2])
3697 && REGNO (operands[0]) != REGNO (operands[2])
3698 && (CONST_OK_FOR_J (INTVAL (operands[1]))
3699 || CONST_OK_FOR_L (INTVAL (operands[1]))
3700 || CONST_OK_FOR_N (INTVAL (operands[1])))"
3704 (plus:HI (match_dup 0)
3712 ;; add.l er7,er0 (6 bytes)
3717 ;; adds #4,er0 (4 bytes)
3720 [(set (match_operand:SI 0 "register_operand" "")
3721 (match_operand:SI 1 "const_int_operand" ""))
3723 (plus:SI (match_dup 0)
3724 (match_operand:SI 2 "register_operand" "")))]
3725 "(TARGET_H8300H || TARGET_H8300S)
3726 && REG_P (operands[0]) && REG_P (operands[2])
3727 && REGNO (operands[0]) != REGNO (operands[2])
3728 && (CONST_OK_FOR_L (INTVAL (operands[1]))
3729 || CONST_OK_FOR_N (INTVAL (operands[1])))"
3733 (plus:SI (match_dup 0)
3740 ;; add.l #10,er0 (takes 8 bytes)
3746 ;; add.l er7,er0 (takes 6 bytes)
3749 [(set (match_operand:SI 0 "register_operand" "")
3750 (match_operand:SI 1 "register_operand" ""))
3752 (plus:SI (match_dup 0)
3753 (match_operand:SI 2 "const_int_operand" "")))]
3754 "(TARGET_H8300H || TARGET_H8300S)
3755 && REG_P (operands[0]) && REG_P (operands[1])
3756 && REGNO (operands[0]) != REGNO (operands[1])
3757 && !CONST_OK_FOR_L (INTVAL (operands[2]))
3758 && !CONST_OK_FOR_N (INTVAL (operands[2]))
3759 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
3760 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
3761 || INTVAL (operands[2]) == 0xffff
3762 || INTVAL (operands[2]) == 0xfffe)"
3766 (plus:SI (match_dup 0)
3782 [(set (match_operand:HI 0 "register_operand" "")
3783 (plus:HI (match_dup 0)
3784 (match_operand 1 "incdec_operand" "")))
3788 (if_then_else (match_operator 3 "eqne_operator"
3789 [(cc0) (const_int 0)])
3790 (label_ref (match_operand 2 "" ""))
3792 "TARGET_H8300H || TARGET_H8300S"
3793 [(set (match_operand:HI 0 "register_operand" "")
3794 (unspec:HI [(match_dup 0)
3800 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
3801 (label_ref (match_dup 2))
3805 ;; The SImode version of the previous pattern.
3808 [(set (match_operand:SI 0 "register_operand" "")
3809 (plus:SI (match_dup 0)
3810 (match_operand 1 "incdec_operand" "")))
3814 (if_then_else (match_operator 3 "eqne_operator"
3815 [(cc0) (const_int 0)])
3816 (label_ref (match_operand 2 "" ""))
3818 "TARGET_H8300H || TARGET_H8300S"
3819 [(set (match_operand:SI 0 "register_operand" "")
3820 (unspec:SI [(match_dup 0)
3826 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
3827 (label_ref (match_dup 2))
3832 [(parallel [(set (cc0)
3833 (zero_extract:SI (match_operand:QI 0 "register_operand" "")
3836 (clobber (scratch:QI))])
3838 (if_then_else (match_operator 1 "eqne_operator"
3839 [(cc0) (const_int 0)])
3840 (label_ref (match_operand 2 "" ""))
3842 "(TARGET_H8300H || TARGET_H8300S)"
3846 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
3847 (label_ref (match_dup 2))
3849 "operands[3] = ((GET_CODE (operands[1]) == EQ)
3850 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
3851 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));")
3853 ;; The next three peephole2's will try to transform
3855 ;; mov.b A,r0l (or mov.l A,er0)
3862 ;; and.b #CST,r0l (if CST is not 255)
3865 [(set (match_operand:QI 0 "register_operand" "")
3866 (match_operand:QI 1 "general_operand" ""))
3867 (set (match_operand:SI 2 "register_operand" "")
3868 (and:SI (match_dup 2)
3870 "(TARGET_H8300H || TARGET_H8300S)
3871 && !reg_overlap_mentioned_p (operands[2], operands[1])
3872 && REGNO (operands[0]) == REGNO (operands[2])"
3875 (set (strict_low_part (match_dup 0))
3880 [(set (match_operand:SI 0 "register_operand" "")
3881 (match_operand:SI 1 "general_operand" ""))
3883 (and:SI (match_dup 0)
3885 "(TARGET_H8300H || TARGET_H8300S)
3886 && !reg_overlap_mentioned_p (operands[0], operands[1])
3887 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
3890 (set (strict_low_part (match_dup 2))
3892 "operands[2] = gen_lowpart (QImode, operands[0]);
3893 operands[3] = gen_lowpart (QImode, operands[1]);")
3896 [(set (match_operand 0 "register_operand" "")
3897 (match_operand 1 "general_operand" ""))
3898 (set (match_operand:SI 2 "register_operand" "")
3899 (and:SI (match_dup 2)
3900 (match_operand:SI 3 "const_int_qi_operand" "")))]
3901 "(TARGET_H8300H || TARGET_H8300S)
3902 && (GET_MODE (operands[0]) == QImode
3903 || GET_MODE (operands[0]) == HImode
3904 || GET_MODE (operands[0]) == SImode)
3905 && GET_MODE (operands[0]) == GET_MODE (operands[1])
3906 && REGNO (operands[0]) == REGNO (operands[2])
3907 && !reg_overlap_mentioned_p (operands[2], operands[1])
3908 && !(GET_MODE (operands[1]) != QImode
3909 && GET_CODE (operands[1]) == MEM
3910 && MEM_VOLATILE_P (operands[1]))"
3913 (set (strict_low_part (match_dup 4))
3916 (and:SI (match_dup 2)
3918 "operands[4] = gen_lowpart (QImode, operands[0]);
3919 operands[5] = gen_lowpart (QImode, operands[1]);
3920 operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));")
3923 [(set (match_operand:SI 0 "register_operand" "")
3924 (match_operand:SI 1 "register_operand" ""))
3926 (and:SI (match_dup 0)
3927 (const_int 65280)))]
3928 "(TARGET_H8300H || TARGET_H8300S)
3929 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3932 (set (zero_extract:SI (match_dup 0)
3935 (lshiftrt:SI (match_dup 1)
3939 ;; If a load of mem:SI is followed by an AND that turns off the upper
3940 ;; half, then we can load mem:HI instead.
3943 [(set (match_operand:SI 0 "register_operand" "")
3944 (match_operand:SI 1 "memory_operand" ""))
3946 (and:SI (match_dup 0)
3947 (match_operand:SI 2 "const_int_operand" "")))]
3948 "(TARGET_H8300H || TARGET_H8300S)
3949 && !MEM_VOLATILE_P (operands[1])
3950 && (INTVAL (operands[2]) & ~0xffff) == 0
3951 && INTVAL (operands[2]) != 255"
3955 (and:SI (match_dup 0)
3957 "operands[3] = gen_lowpart (HImode, operands[0]);
3958 operands[4] = gen_lowpart (HImode, operands[1]);")
3960 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
3961 ;; the equivalent with shorter sequences. Here is the summary. Cases
3962 ;; are grouped for each define_peephole2.
3964 ;; reg const_int use insn
3965 ;; --------------------------------------------------------
3966 ;; dead -2 eq/ne inc.l
3967 ;; dead -1 eq/ne inc.l
3968 ;; dead 1 eq/ne dec.l
3969 ;; dead 2 eq/ne dec.l
3971 ;; dead 1 geu/ltu shlr.l
3972 ;; dead 3 (H8S) geu/ltu shlr.l
3974 ;; ---- 255 geu/ltu mov.b
3988 (compare (match_operand:HI 0 "register_operand" "")
3989 (match_operand:HI 1 "incdec_operand" "")))
3991 (if_then_else (match_operator 3 "eqne_operator"
3992 [(cc0) (const_int 0)])
3993 (label_ref (match_operand 2 "" ""))
3995 "(TARGET_H8300H || TARGET_H8300S)
3996 && peep2_reg_dead_p (1, operands[0])"
3998 (unspec:HI [(match_dup 0)
4004 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4005 (label_ref (match_dup 2))
4007 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4021 (compare (match_operand:HI 0 "register_operand" "")
4022 (match_operand:HI 1 "const_int_operand" "")))
4024 (if_then_else (match_operator 2 "gtuleu_operator"
4025 [(cc0) (const_int 0)])
4026 (label_ref (match_operand 3 "" ""))
4028 "(TARGET_H8300H || TARGET_H8300S)
4029 && peep2_reg_dead_p (1, operands[0])
4030 && (INTVAL (operands[1]) == 1
4031 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4032 [(parallel [(set (match_dup 0)
4033 (lshiftrt:HI (match_dup 0)
4035 (clobber (scratch:QI))])
4039 (if_then_else (match_dup 4)
4040 (label_ref (match_dup 3))
4042 "operands[4] = ((GET_CODE (operands[2]) == GTU) ?
4043 gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx) :
4044 gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx));
4045 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4059 (compare (match_operand:HI 0 "register_operand" "")
4062 (if_then_else (match_operator 1 "gtle_operator"
4063 [(cc0) (const_int 0)])
4064 (label_ref (match_operand 2 "" ""))
4066 "TARGET_H8300H || TARGET_H8300S"
4068 (and:HI (match_dup 0)
4071 (if_then_else (match_dup 3)
4072 (label_ref (match_dup 2))
4074 "switch (GET_CODE (operands[1]))
4077 operands[3] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4080 operands[3] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4083 operands[3] = operands[1];
4087 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
4088 ;; the equivalent with shorter sequences. Here is the summary. Cases
4089 ;; are grouped for each define_peephole2.
4091 ;; reg const_int use insn
4092 ;; --------------------------------------------------------
4093 ;; live -2 eq/ne copy and inc.l
4094 ;; live -1 eq/ne copy and inc.l
4095 ;; live 1 eq/ne copy and dec.l
4096 ;; live 2 eq/ne copy and dec.l
4098 ;; dead -2 eq/ne inc.l
4099 ;; dead -1 eq/ne inc.l
4100 ;; dead 1 eq/ne dec.l
4101 ;; dead 2 eq/ne dec.l
4103 ;; dead -131072 eq/ne inc.w and test
4104 ;; dead -65536 eq/ne inc.w and test
4105 ;; dead 65536 eq/ne dec.w and test
4106 ;; dead 131072 eq/ne dec.w and test
4108 ;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
4109 ;; dead 0x0000??00 eq/ne xor.b and test
4110 ;; dead 0x0000ffff eq/ne not.w and test
4112 ;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
4113 ;; dead 0xffff??ff eq/ne xor.b and not.l
4115 ;; live 1 geu/ltu copy and shlr.l
4116 ;; live 3 (H8S) geu/ltu copy and shlr.l
4118 ;; dead 1 geu/ltu shlr.l
4119 ;; dead 3 (H8S) geu/ltu shlr.l
4121 ;; dead 3 (H8/300H) geu/ltu and.b and test
4122 ;; dead 7 geu/ltu and.b and test
4123 ;; dead 15 geu/ltu and.b and test
4124 ;; dead 31 geu/ltu and.b and test
4125 ;; dead 63 geu/ltu and.b and test
4126 ;; dead 127 geu/ltu and.b and test
4127 ;; dead 255 geu/ltu and.b and test
4129 ;; dead 65535 geu/ltu mov.w
4131 ;; For a small constant, it is cheaper to actually do the subtraction
4132 ;; and then test the register.
4136 (compare (match_operand:SI 0 "register_operand" "")
4137 (match_operand:SI 1 "incdec_operand" "")))
4139 (if_then_else (match_operator 3 "eqne_operator"
4140 [(cc0) (const_int 0)])
4141 (label_ref (match_operand 2 "" ""))
4143 "(TARGET_H8300H || TARGET_H8300S)
4144 && peep2_reg_dead_p (1, operands[0])"
4146 (unspec:SI [(match_dup 0)
4152 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4153 (label_ref (match_dup 2))
4155 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4159 (compare (match_operand:SI 0 "register_operand" "")
4160 (match_operand:SI 1 "const_int_operand" "")))
4162 (if_then_else (match_operator 3 "eqne_operator"
4163 [(cc0) (const_int 0)])
4164 (label_ref (match_operand 2 "" ""))
4166 "(TARGET_H8300H || TARGET_H8300S)
4167 && peep2_reg_dead_p (1, operands[0])
4168 && (INTVAL (operands[1]) == -131072
4169 || INTVAL (operands[1]) == -65536
4170 || INTVAL (operands[1]) == 65536
4171 || INTVAL (operands[1]) == 131072)"
4173 (plus:SI (match_dup 0)
4178 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4179 (label_ref (match_dup 2))
4181 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4183 ;; For certain (in)equaltity comparisions against a constant, we can
4184 ;; XOR the register with the constant, and test the register against
4189 (compare (match_operand:SI 0 "register_operand" "")
4190 (match_operand:SI 1 "const_int_operand" "")))
4192 (if_then_else (match_operator 3 "eqne_operator"
4193 [(cc0) (const_int 0)])
4194 (label_ref (match_operand 2 "" ""))
4196 "(TARGET_H8300H || TARGET_H8300S)
4197 && peep2_reg_dead_p (1, operands[0])
4198 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
4199 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
4200 || INTVAL (operands[1]) == 0x0000ffff)
4201 && INTVAL (operands[1]) != 1
4202 && INTVAL (operands[1]) != 2"
4204 (xor:SI (match_dup 0)
4209 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4210 (label_ref (match_dup 2))
4216 (compare (match_operand:SI 0 "register_operand" "")
4217 (match_operand:SI 1 "const_int_operand" "")))
4219 (if_then_else (match_operator 3 "eqne_operator"
4220 [(cc0) (const_int 0)])
4221 (label_ref (match_operand 2 "" ""))
4223 "(TARGET_H8300H || TARGET_H8300S)
4224 && peep2_reg_dead_p (1, operands[0])
4225 && ((INTVAL (operands[1]) | 0x00ff) == -1
4226 || (INTVAL (operands[1]) | 0xff00) == -1)
4227 && INTVAL (operands[1]) != -1
4228 && INTVAL (operands[1]) != -2"
4230 (xor:SI (match_dup 0)
4233 (not:SI (match_dup 0)))
4237 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4238 (label_ref (match_dup 2))
4240 "operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);")
4254 [(match_scratch:SI 4 "r")
4256 (compare (match_operand:SI 0 "register_operand" "")
4257 (match_operand:SI 1 "const_int_operand" "")))
4259 (if_then_else (match_operator 2 "gtuleu_operator"
4260 [(cc0) (const_int 0)])
4261 (label_ref (match_operand 3 "" ""))
4263 "(TARGET_H8300H || TARGET_H8300S)
4264 && !peep2_reg_dead_p (1, operands[0])
4265 && (INTVAL (operands[1]) == 1
4266 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4269 (parallel [(set (match_dup 4)
4270 (lshiftrt:SI (match_dup 4)
4272 (clobber (scratch:QI))])
4276 (if_then_else (match_dup 5)
4277 (label_ref (match_dup 3))
4279 "operands[5] = ((GET_CODE (operands[2]) == GTU) ?
4280 gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx) :
4281 gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx));
4282 operands[6] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4296 (compare (match_operand:SI 0 "register_operand" "")
4297 (match_operand:SI 1 "const_int_operand" "")))
4299 (if_then_else (match_operator 2 "gtuleu_operator"
4300 [(cc0) (const_int 0)])
4301 (label_ref (match_operand 3 "" ""))
4303 "(TARGET_H8300H || TARGET_H8300S)
4304 && peep2_reg_dead_p (1, operands[0])
4305 && (INTVAL (operands[1]) == 1
4306 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4307 [(parallel [(set (match_dup 0)
4308 (lshiftrt:SI (match_dup 0)
4310 (clobber (scratch:QI))])
4314 (if_then_else (match_dup 4)
4315 (label_ref (match_dup 3))
4317 "operands[4] = ((GET_CODE (operands[2]) == GTU) ?
4318 gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx) :
4319 gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx));
4320 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4335 (compare (match_operand:SI 0 "register_operand" "")
4336 (match_operand:SI 1 "const_int_operand" "")))
4338 (if_then_else (match_operator 2 "gtle_operator"
4339 [(cc0) (const_int 0)])
4340 (label_ref (match_operand 3 "" ""))
4342 "(TARGET_H8300H || TARGET_H8300S)
4343 && peep2_reg_dead_p (1, operands[0])
4344 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
4345 || INTVAL (operands[1]) == 7
4346 || INTVAL (operands[1]) == 15
4347 || INTVAL (operands[1]) == 31
4348 || INTVAL (operands[1]) == 63
4349 || INTVAL (operands[1]) == 127
4350 || INTVAL (operands[1]) == 255)"
4352 (and:SI (match_dup 0)
4357 (if_then_else (match_dup 4)
4358 (label_ref (match_dup 3))
4360 "switch (GET_CODE (operands[2]))
4363 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4366 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4369 operands[4] = operands[2];
4372 operands[5] = GEN_INT (~INTVAL (operands[1]));")
4374 ;; Transform A <= 65535 to (A & 0xffff0000) == 0.
4378 (compare (match_operand:SI 0 "register_operand" "")
4381 (if_then_else (match_operator 1 "gtle_operator"
4382 [(cc0) (const_int 0)])
4383 (label_ref (match_operand 2 "" ""))
4385 "TARGET_H8300H || TARGET_H8300S"
4387 (and:SI (match_dup 0)
4388 (const_int -65536)))
4390 (if_then_else (match_dup 3)
4391 (label_ref (match_dup 2))
4393 "switch (GET_CODE (operands[1]))
4396 operands[3] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4399 operands[3] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4402 operands[3] = operands[1];
4406 ;; For constants like -1, -2, 1, 2, it is still cheaper to make a copy
4407 ;; of the register being tested, do the subtraction on the copy, and
4408 ;; then test the copy. We avoid this transformation if we see more
4409 ;; than one copy of the same compare insn.
4412 [(match_scratch:SI 4 "r")
4414 (compare (match_operand:SI 0 "register_operand" "")
4415 (match_operand:SI 1 "incdec_operand" "")))
4417 (if_then_else (match_operator 3 "eqne_operator"
4418 [(cc0) (const_int 0)])
4419 (label_ref (match_operand 2 "" ""))
4421 "(TARGET_H8300H || TARGET_H8300S)
4422 && !peep2_reg_dead_p (1, operands[0])
4423 && !rtx_equal_p (PATTERN (insn),
4424 PATTERN (next_nonnote_insn (next_nonnote_insn (insn))))"
4428 (unspec:SI [(match_dup 4)
4434 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4435 (label_ref (match_dup 2))
4437 "operands[5] = GEN_INT (- INTVAL (operands[1]));")
4439 ;; Narrow the mode of testing if possible.
4442 [(set (match_operand:HI 0 "register_operand" "")
4443 (and:HI (match_dup 0)
4444 (match_operand:HI 1 "const_int_qi_operand" "")))
4448 (if_then_else (match_operator 3 "eqne_operator"
4449 [(cc0) (const_int 0)])
4450 (label_ref (match_operand 2 "" ""))
4452 "peep2_reg_dead_p (2, operands[0])"
4454 (and:QI (match_dup 4)
4459 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4460 (label_ref (match_dup 2))
4462 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
4463 operands[5] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]), QImode));")
4466 [(set (match_operand:SI 0 "register_operand" "")
4467 (and:SI (match_dup 0)
4468 (match_operand:SI 1 "const_int_qi_operand" "")))
4472 (if_then_else (match_operator 3 "eqne_operator"
4473 [(cc0) (const_int 0)])
4474 (label_ref (match_operand 2 "" ""))
4476 "peep2_reg_dead_p (2, operands[0])"
4478 (and:QI (match_dup 4)
4483 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4484 (label_ref (match_dup 2))
4486 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
4487 operands[5] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]), QImode));")
4490 [(set (match_operand:SI 0 "register_operand" "")
4491 (and:SI (match_dup 0)
4492 (match_operand:SI 1 "const_int_hi_operand" "")))
4496 (if_then_else (match_operator 3 "eqne_operator"
4497 [(cc0) (const_int 0)])
4498 (label_ref (match_operand 2 "" ""))
4500 "peep2_reg_dead_p (2, operands[0])"
4502 (and:HI (match_dup 4)
4507 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4508 (label_ref (match_dup 2))
4510 "operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
4511 operands[5] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]), HImode));")
4514 [(set (match_operand:SI 0 "register_operand" "")
4515 (and:SI (match_dup 0)
4516 (match_operand:SI 1 "const_int_qi_operand" "")))
4518 (xor:SI (match_dup 0)
4519 (match_operand:SI 2 "const_int_qi_operand" "")))
4523 (if_then_else (match_operator 4 "eqne_operator"
4524 [(cc0) (const_int 0)])
4525 (label_ref (match_operand 3 "" ""))
4527 "peep2_reg_dead_p (3, operands[0])
4528 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
4530 (and:QI (match_dup 5)
4533 (xor:QI (match_dup 5)
4538 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
4539 (label_ref (match_dup 3))
4541 "operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
4542 operands[6] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]), QImode));
4543 operands[7] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));")