1 ;; GCC machine description for Hitachi H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003 Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;; Some of the extend instructions accept a general_operand_src, which
26 ;; allows all the normal memory addressing modes. The length computations
27 ;; don't take this into account. The lengths in the MD file should be
28 ;; "worst case" and then be adjusted to their correct values by
29 ;; h8300_adjust_insn_length.
31 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
32 ;; registers. Right now GCC doesn't expose the "e" half to the
33 ;; compiler, so using add/subs for addhi and subhi is safe. Long
34 ;; term, we want to expose the "e" half to the compiler (gives us 8
35 ;; more 16bit registers). At that point addhi and subhi can't use
38 ;; There's currently no way to have an insv/extzv expander for the H8/300H
39 ;; because word_mode is different for the H8/300 and H8/300H.
41 ;; Shifts/rotates by small constants should be handled by special
42 ;; patterns so we get the length and cc status correct.
44 ;; Bitfield operations no longer accept memory operands. We need
45 ;; to add variants which operate on memory back to the MD.
47 ;; ??? Implement remaining bit ops available on the h8300
49 ;; ----------------------------------------------------------------------
51 ;; ----------------------------------------------------------------------
65 ;; ----------------------------------------------------------------------
67 ;; ----------------------------------------------------------------------
69 (define_attr "cpu" "h8300,h8300h"
70 (const (symbol_ref "cpu_type")))
72 (define_attr "type" "branch,arith"
73 (const_string "arith"))
75 ;; The size of instructions in bytes.
77 (define_attr "length" ""
78 (cond [(eq_attr "type" "branch")
79 (if_then_else (and (ge (minus (match_dup 0) (pc))
81 (le (minus (match_dup 0) (pc))
84 (if_then_else (and (eq_attr "cpu" "h8300h")
85 (and (ge (minus (pc) (match_dup 0))
87 (le (minus (pc) (match_dup 0))
93 ;; The necessity of instruction length adjustment.
95 (define_attr "adjust_length" "yes,no"
96 (cond [(eq_attr "type" "branch") (const_string "no")]
97 (const_string "yes")))
99 ;; Condition code settings.
101 ;; none - insn does not affect cc
102 ;; none_0hit - insn does not affect cc but it does modify operand 0
103 ;; This attribute is used to keep track of when operand 0 changes.
104 ;; See the description of NOTICE_UPDATE_CC for more info.
105 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
106 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
107 ;; compare - compare instruction
108 ;; clobber - value of cc is unknown
110 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
111 (const_string "clobber"))
113 ;; ----------------------------------------------------------------------
115 ;; ----------------------------------------------------------------------
119 (define_insn "pushqi1_h8300"
120 [(parallel [(set (reg:HI SP_REG)
121 (plus:HI (reg:HI SP_REG) (const_int -2)))
122 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
123 (match_operand:QI 0 "register_operand" "r"))])]
125 && REGNO (operands[0]) != SP_REG"
127 [(set_attr "length" "2")
128 (set_attr "cc" "clobber")])
130 (define_insn "pushqi1_h8300hs"
131 [(parallel [(set (reg:SI SP_REG)
132 (plus:SI (reg:SI SP_REG) (const_int -4)))
133 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
134 (match_operand:QI 0 "register_operand" "r"))])]
135 "(TARGET_H8300H || TARGET_H8300S)
136 && REGNO (operands[0]) != SP_REG"
138 [(set_attr "length" "4")
139 (set_attr "cc" "clobber")])
141 (define_expand "pushqi1"
142 [(use (match_operand:QI 0 "register_operand" ""))]
147 emit_insn (gen_pushqi1_h8300 (operands[0]));
149 emit_insn (gen_pushqi1_h8300hs (operands[0]));
154 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
155 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
157 && (register_operand (operands[0], QImode)
158 || register_operand (operands[1], QImode))"
166 [(set_attr "length" "2,2,2,2,4,4")
167 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
170 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
171 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
172 "(TARGET_H8300H || TARGET_H8300S)
173 && (register_operand (operands[0], QImode)
174 || register_operand (operands[1], QImode))"
182 [(set_attr "length" "2,2,2,2,8,8")
183 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
185 (define_expand "movqi"
186 [(set (match_operand:QI 0 "general_operand_dst" "")
187 (match_operand:QI 1 "general_operand_src" ""))]
191 /* One of the ops has to be in a register. */
192 if (!register_operand (operand0, QImode)
193 && !register_operand (operand1, QImode))
195 operands[1] = copy_to_mode_reg (QImode, operand1);
199 (define_insn "movstrictqi"
200 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r,r,r"))
201 (match_operand:QI 1 "general_operand_src" "I,r,n,m"))]
208 [(set_attr_alternative "length"
209 [(const_int 2) (const_int 2) (const_int 2)
210 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
211 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
215 (define_expand "pushhi1_h8300"
216 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
217 (match_operand:HI 0 "register_operand" ""))]
219 && REGNO (operands[0]) != SP_REG"
222 (define_insn "pushhi1_h8300hs"
223 [(parallel [(set (reg:SI SP_REG)
224 (plus:SI (reg:SI SP_REG) (const_int -4)))
225 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
226 (match_operand:HI 0 "register_operand" "r"))])]
227 "(TARGET_H8300H || TARGET_H8300S)
228 && REGNO (operands[0]) != SP_REG"
230 [(set_attr "length" "4")
231 (set_attr "cc" "clobber")])
233 (define_expand "pushhi1"
234 [(use (match_operand:HI 0 "register_operand" ""))]
239 emit_insn (gen_pushhi1_h8300 (operands[0]));
241 emit_insn (gen_pushhi1_h8300hs (operands[0]));
246 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
247 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
249 && (register_operand (operands[0], HImode)
250 || register_operand (operands[1], HImode))
251 && !(GET_CODE (operands[0]) == MEM
252 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
253 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
254 && GET_CODE (operands[1]) == REG
255 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
263 [(set_attr "length" "2,2,2,4,4,4")
264 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
267 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
268 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
269 "(TARGET_H8300H || TARGET_H8300S)
270 && (register_operand (operands[0], HImode)
271 || register_operand (operands[1], HImode))"
279 [(set_attr "length" "2,2,2,4,8,8")
280 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
282 (define_expand "movhi"
283 [(set (match_operand:HI 0 "general_operand_dst" "")
284 (match_operand:HI 1 "general_operand_src" ""))]
288 /* One of the ops has to be in a register. */
289 if (!register_operand (operand1, HImode)
290 && !register_operand (operand0, HImode))
292 operands[1] = copy_to_mode_reg (HImode, operand1);
296 (define_insn "movstricthi"
297 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r,r"))
298 (match_operand:HI 1 "general_operand_src" "I,r,i,m"))]
305 [(set_attr_alternative "length"
306 [(const_int 2) (const_int 2) (const_int 4)
307 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
308 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
312 (define_expand "movsi"
313 [(set (match_operand:SI 0 "general_operand_dst" "")
314 (match_operand:SI 1 "general_operand_src" ""))]
320 if (do_movsi (operands))
325 /* One of the ops has to be in a register. */
326 if (!register_operand (operand1, SImode)
327 && !register_operand (operand0, SImode))
329 operands[1] = copy_to_mode_reg (SImode, operand1);
334 (define_expand "movsf"
335 [(set (match_operand:SF 0 "general_operand_dst" "")
336 (match_operand:SF 1 "general_operand_src" ""))]
342 if (do_movsi (operands))
347 /* One of the ops has to be in a register. */
348 if (!register_operand (operand1, SFmode)
349 && !register_operand (operand0, SFmode))
351 operands[1] = copy_to_mode_reg (SFmode, operand1);
356 (define_insn "movsi_h8300"
357 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
358 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
360 && (register_operand (operands[0], SImode)
361 || register_operand (operands[1], SImode))"
364 unsigned int rn = -1;
365 switch (which_alternative)
368 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
370 if (REGNO (operands[0]) < REGNO (operands[1]))
371 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
373 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
375 /* Make sure we don't trample the register we index with. */
376 if (GET_CODE (operands[1]) == MEM)
378 rtx inside = XEXP (operands[1], 0);
383 else if (GET_CODE (inside) == PLUS)
385 rtx lhs = XEXP (inside, 0);
386 rtx rhs = XEXP (inside, 1);
387 if (REG_P (lhs)) rn = REGNO (lhs);
388 if (REG_P (rhs)) rn = REGNO (rhs);
391 if (rn == REGNO (operands[0]))
393 /* Move the second word first. */
394 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
398 /* See if either half is zero. If so, use sub.w to clear
400 if (GET_CODE (operands[1]) == CONST_INT)
402 if ((INTVAL (operands[1]) & 0xffff) == 0)
403 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
404 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
405 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
407 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
410 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
412 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
414 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
419 [(set_attr "length" "4,4,8,8,4,4")
420 (set_attr "cc" "clobber")])
422 (define_insn "movsf_h8300"
423 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
424 (match_operand:SF 1 "general_operand_src" "I,r,io,r,r,>"))]
426 && (register_operand (operands[0], SFmode)
427 || register_operand (operands[1], SFmode))"
430 /* Copy of the movsi stuff. */
431 unsigned int rn = -1;
432 switch (which_alternative)
435 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
437 if (REGNO (operands[0]) < REGNO (operands[1]))
438 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
440 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
442 /* Make sure we don't trample the register we index with. */
443 if (GET_CODE (operands[1]) == MEM)
445 rtx inside = XEXP (operands[1], 0);
450 else if (GET_CODE (inside) == PLUS)
452 rtx lhs = XEXP (inside, 0);
453 rtx rhs = XEXP (inside, 1);
454 if (REG_P (lhs)) rn = REGNO (lhs);
455 if (REG_P (rhs)) rn = REGNO (rhs);
458 if (rn == REGNO (operands[0]))
459 /* Move the second word first. */
460 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
462 /* Move the first word first. */
463 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
466 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
468 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
470 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
475 [(set_attr "length" "4,4,8,8,4,4")
476 (set_attr "cc" "clobber")])
478 (define_insn "movsi_h8300hs"
479 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
480 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
481 "(TARGET_H8300S || TARGET_H8300H)
482 && (register_operand (operands[0], SImode)
483 || register_operand (operands[1], SImode))
484 && !(GET_CODE (operands[0]) == MEM
485 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
486 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
487 && GET_CODE (operands[1]) == REG
488 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
491 switch (which_alternative)
494 return \"sub.l %S0,%S0\";
498 return \"clrmac\;ldmac %1,macl\";
500 return \"stmac macl,%0\";
502 if (GET_CODE (operands[1]) == CONST_INT)
504 int val = INTVAL (operands[1]);
506 /* Look for constants which can be made by adding an 8-bit
507 number to zero in one of the two low bytes. */
508 if (val == (val & 0xff))
510 operands[1] = GEN_INT ((char) val & 0xff);
511 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
514 if (val == (val & 0xff00))
516 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
517 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
520 /* Look for constants that can be obtained by subs, inc, and
522 switch (val & 0xffffffff)
525 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
527 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
529 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
532 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
534 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
537 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
539 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
542 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
544 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
548 return \"mov.l %S1,%S0\";
550 [(set_attr "length" "2,2,6,4,4,10,10,2,6,4")
551 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
553 (define_insn "movsf_h8300h"
554 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
555 (match_operand:SF 1 "general_operand_src" "I,r,im,r,r,>"))]
556 "(TARGET_H8300H || TARGET_H8300S)
557 && (register_operand (operands[0], SFmode)
558 || register_operand (operands[1], SFmode))"
566 [(set_attr "length" "2,2,10,10,4,4")
567 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
569 ;; ----------------------------------------------------------------------
571 ;; ----------------------------------------------------------------------
574 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
576 (match_operand 1 "const_int_operand" "n,n")))]
579 [(set_attr "length" "2,4")
580 (set_attr "cc" "set_zn,set_zn")])
583 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
585 (match_operand 1 "const_int_operand" "n")))]
588 [(set_attr "length" "2")
589 (set_attr "cc" "set_zn")])
591 (define_insn "*tst_extzv_1_n"
593 (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
595 (match_operand 1 "const_int_operand" "n,n,n")))
596 (clobber (match_scratch:QI 2 "=X,X,&r"))]
597 "(TARGET_H8300H || TARGET_H8300S)"
602 [(set_attr "length" "2,8,10")
603 (set_attr "cc" "set_zn,set_zn,set_zn")])
607 (zero_extract:SI (match_operand:QI 0 "general_operand" "")
609 (match_operand 1 "const_int_operand" "")))
610 (clobber (match_operand:QI 2 "register_operand" ""))]
611 "(TARGET_H8300H || TARGET_H8300S)
613 && !EXTRA_CONSTRAINT (operands[0], 'U')"
616 (parallel [(set (cc0) (zero_extract:SI (match_dup 2)
619 (clobber (scratch:QI))])]
623 [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
625 (match_operand 1 "const_int_operand" "n")))]
626 "(TARGET_H8300H || TARGET_H8300S)
627 && INTVAL (operands[1]) <= 15"
629 [(set_attr "length" "2")
630 (set_attr "cc" "set_zn")])
632 (define_insn_and_split "*tstsi_upper_bit"
634 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
636 (match_operand 1 "const_int_operand" "n")))
637 (clobber (match_scratch:SI 2 "=&r"))]
638 "(TARGET_H8300H || TARGET_H8300S)
639 && INTVAL (operands[1]) >= 16"
641 "&& reload_completed"
643 (ior:SI (and:SI (match_dup 2)
645 (lshiftrt:SI (match_dup 0)
648 (zero_extract:SI (match_dup 2)
651 "operands[3] = GEN_INT (INTVAL (operands[1]) - 16);")
655 (and:HI (match_operand:HI 0 "register_operand" "r")
656 (match_operand:HI 1 "single_one_operand" "n")))]
660 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
661 if (INTVAL (operands[1]) > 128)
663 operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
664 return \"btst\\t%V1,%t0\";
666 return \"btst\\t%V1,%s0\";
668 [(set_attr "length" "2")
669 (set_attr "cc" "set_zn")])
673 (and:SI (match_operand:SI 0 "register_operand" "r")
674 (match_operand:SI 1 "single_one_operand" "n")))]
675 "(TARGET_H8300H || TARGET_H8300S)
676 && (INTVAL (operands[1]) & 0xffff) != 0"
679 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
680 if (INTVAL (operands[1]) > 128)
682 operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
683 return \"btst\\t%V1,%x0\";
685 return \"btst\\t%V1,%w0\";
687 [(set_attr "length" "2")
688 (set_attr "cc" "set_zn")])
691 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
694 [(set_attr "length" "2")
695 (set_attr "cc" "set_znv")])
698 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
701 [(set_attr "length" "2")
702 (set_attr "cc" "set_znv")])
706 (and:HI (match_operand:HI 0 "register_operand" "r")
710 [(set_attr "length" "2")
711 (set_attr "cc" "set_znv")])
714 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
715 "TARGET_H8300H || TARGET_H8300S"
717 [(set_attr "length" "2")
718 (set_attr "cc" "set_znv")])
722 (and:SI (match_operand:SI 0 "register_operand" "r")
723 (const_int -65536)))]
726 [(set_attr "length" "2")
727 (set_attr "cc" "set_znv")])
731 (compare (match_operand:QI 0 "register_operand" "r")
732 (match_operand:QI 1 "nonmemory_operand" "rn")))]
735 [(set_attr "length" "2")
736 (set_attr "cc" "compare")])
738 (define_expand "cmphi"
740 (compare (match_operand:HI 0 "register_operand" "")
741 (match_operand:HI 1 "nonmemory_operand" "")))]
745 /* Force operand1 into a register if we're compiling
747 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
748 operands[1] = force_reg (HImode, operands[1]);
751 (define_insn "*cmphi_h8300"
753 (compare (match_operand:HI 0 "register_operand" "r")
754 (match_operand:HI 1 "register_operand" "r")))]
757 [(set_attr "length" "2")
758 (set_attr "cc" "compare")])
760 (define_insn "*cmphi_h8300hs"
762 (compare (match_operand:HI 0 "register_operand" "r,r")
763 (match_operand:HI 1 "nonmemory_operand" "r,n")))]
764 "TARGET_H8300H || TARGET_H8300S"
766 [(set_attr "length" "2,4")
767 (set_attr "cc" "compare,compare")])
771 (compare (match_operand:SI 0 "register_operand" "r,r")
772 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
773 "TARGET_H8300H || TARGET_H8300S"
775 [(set_attr "length" "2,6")
776 (set_attr "cc" "compare,compare")])
778 ;; ----------------------------------------------------------------------
780 ;; ----------------------------------------------------------------------
782 (define_insn "addqi3"
783 [(set (match_operand:QI 0 "register_operand" "=r")
784 (plus:QI (match_operand:QI 1 "register_operand" "%0")
785 (match_operand:QI 2 "nonmemory_operand" "rn")))]
788 [(set_attr "length" "2")
789 (set_attr "cc" "set_zn")])
791 (define_expand "addhi3"
792 [(set (match_operand:HI 0 "register_operand" "")
793 (plus:HI (match_operand:HI 1 "register_operand" "")
794 (match_operand:HI 2 "nonmemory_operand" "")))]
798 (define_insn "*addhi3_h8300"
799 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
800 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
801 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
807 add.b %s2,%s0\;addx %t2,%t0
809 [(set_attr "length" "2,2,2,4,2")
810 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
812 ;; This splitter is very important to make the stack adjustment
813 ;; interrupt-safe. The combination of add.b and addx is unsafe!
815 ;; We apply this split after the peephole2 pass so that we won't end
816 ;; up creating too many adds/subs when a scratch register is
817 ;; available, which is actually a common case because stack unrolling
818 ;; tends to happen immediately after a function call.
821 [(set (match_operand:HI 0 "stack_pointer_operand" "")
822 (plus:HI (match_dup 0)
823 (match_operand 1 "const_int_gt_2_operand" "")))]
824 "TARGET_H8300 && flow2_completed"
826 "split_adds_subs (HImode, operands); DONE;")
829 [(match_scratch:HI 2 "r")
830 (set (match_operand:HI 0 "stack_pointer_operand" "")
831 (plus:HI (match_dup 0)
832 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
837 (plus:HI (match_dup 0)
841 (define_insn "*addhi3_h8300hs"
842 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
843 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
844 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
845 "TARGET_H8300H || TARGET_H8300S"
852 [(set_attr "length" "2,2,2,4,2")
853 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
855 (define_insn "*addhi3_incdec"
856 [(set (match_operand:HI 0 "register_operand" "=r,r")
857 (unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
858 (match_operand:HI 2 "incdec_operand" "M,O")]
860 "TARGET_H8300H || TARGET_H8300S"
864 [(set_attr "length" "2,2")
865 (set_attr "cc" "set_zn,set_zn")])
868 [(set (match_operand:HI 0 "register_operand" "")
869 (plus:HI (match_dup 0)
870 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
873 "split_adds_subs (HImode, operands); DONE;")
875 (define_expand "addsi3"
876 [(set (match_operand:SI 0 "register_operand" "")
877 (plus:SI (match_operand:SI 1 "register_operand" "")
878 (match_operand:SI 2 "nonmemory_operand" "")))]
882 (define_insn "addsi_h8300"
883 [(set (match_operand:SI 0 "register_operand" "=r,r")
884 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
885 (match_operand:SI 2 "nonmemory_operand" "n,r")))]
887 "* return output_plussi (operands);"
888 [(set (attr "length")
889 (symbol_ref "compute_plussi_length (operands)"))
891 (symbol_ref "compute_plussi_cc (operands)"))])
893 (define_insn "addsi_h8300h"
894 [(set (match_operand:SI 0 "register_operand" "=r,r")
895 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
896 (match_operand:SI 2 "nonmemory_operand" "i,r")))]
897 "TARGET_H8300H || TARGET_H8300S"
898 "* return output_plussi (operands);"
899 [(set (attr "length")
900 (symbol_ref "compute_plussi_length (operands)"))
902 (symbol_ref "compute_plussi_cc (operands)"))])
904 (define_insn "*addsi3_incdec"
905 [(set (match_operand:SI 0 "register_operand" "=r,r")
906 (unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
907 (match_operand:SI 2 "incdec_operand" "M,O")]
909 "TARGET_H8300H || TARGET_H8300S"
913 [(set_attr "length" "2,2")
914 (set_attr "cc" "set_zn,set_zn")])
917 [(set (match_operand:SI 0 "register_operand" "")
918 (plus:SI (match_dup 0)
919 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
920 "TARGET_H8300H || TARGET_H8300S"
922 "split_adds_subs (SImode, operands); DONE;")
924 ;; ----------------------------------------------------------------------
925 ;; SUBTRACT INSTRUCTIONS
926 ;; ----------------------------------------------------------------------
928 (define_insn "subqi3"
929 [(set (match_operand:QI 0 "register_operand" "=r")
930 (minus:QI (match_operand:QI 1 "register_operand" "0")
931 (match_operand:QI 2 "register_operand" "r")))]
934 [(set_attr "length" "2")
935 (set_attr "cc" "set_zn")])
937 (define_expand "subhi3"
938 [(set (match_operand:HI 0 "register_operand" "")
939 (minus:HI (match_operand:HI 1 "general_operand" "")
940 (match_operand:HI 2 "nonmemory_operand" "")))]
945 [(set (match_operand:HI 0 "register_operand" "=r,&r")
946 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
947 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
951 add.b %E2,%s0\;addx %F2,%t0"
952 [(set_attr "length" "2,4")
953 (set_attr "cc" "set_zn,clobber")])
956 [(set (match_operand:HI 0 "register_operand" "=r,&r")
957 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
958 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
959 "TARGET_H8300H || TARGET_H8300S"
963 [(set_attr "length" "2,4")
964 (set_attr "cc" "set_zn,set_zn")])
966 (define_expand "subsi3"
967 [(set (match_operand:SI 0 "register_operand" "")
968 (minus:SI (match_operand:SI 1 "register_operand" "")
969 (match_operand:SI 2 "nonmemory_operand" "")))]
973 (define_insn "subsi3_h8300"
974 [(set (match_operand:SI 0 "register_operand" "=r")
975 (minus:SI (match_operand:SI 1 "register_operand" "0")
976 (match_operand:SI 2 "register_operand" "r")))]
978 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
979 [(set_attr "length" "6")
980 (set_attr "cc" "clobber")])
982 (define_insn "subsi3_h8300h"
983 [(set (match_operand:SI 0 "register_operand" "=r,r")
984 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
985 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
986 "TARGET_H8300H || TARGET_H8300S"
990 [(set_attr "length" "2,6")
991 (set_attr "cc" "set_zn,set_zn")])
993 ;; ----------------------------------------------------------------------
994 ;; MULTIPLY INSTRUCTIONS
995 ;; ----------------------------------------------------------------------
997 ;; Note that the H8/300 can only handle umulqihi3.
999 (define_insn "mulqihi3"
1000 [(set (match_operand:HI 0 "register_operand" "=r")
1001 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1002 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1003 "TARGET_H8300H || TARGET_H8300S"
1005 [(set_attr "length" "4")
1006 (set_attr "cc" "set_zn")])
1008 (define_insn "mulhisi3"
1009 [(set (match_operand:SI 0 "register_operand" "=r")
1010 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1011 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1012 "TARGET_H8300H || TARGET_H8300S"
1014 [(set_attr "length" "4")
1015 (set_attr "cc" "set_zn")])
1017 (define_insn "umulqihi3"
1018 [(set (match_operand:HI 0 "register_operand" "=r")
1019 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1020 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1023 [(set_attr "length" "2")
1024 (set_attr "cc" "none_0hit")])
1026 (define_insn "umulhisi3"
1027 [(set (match_operand:SI 0 "register_operand" "=r")
1028 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1029 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1030 "TARGET_H8300H || TARGET_H8300S"
1032 [(set_attr "length" "2")
1033 (set_attr "cc" "none_0hit")])
1035 ;; This is a "bridge" instruction. Combine can't cram enough insns
1036 ;; together to crate a MAC instruction directly, but it can create
1037 ;; this instruction, which then allows combine to create the real
1040 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1041 ;; insn must generate reasonably correct code. Egad.
1043 [(set (match_operand:SI 0 "register_operand" "=a")
1046 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1048 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
1050 "clrmac\;mac @%2+,@%1+"
1051 [(set_attr "length" "6")
1052 (set_attr "cc" "none_0hit")])
1055 [(set (match_operand:SI 0 "register_operand" "=a")
1057 (sign_extend:SI (mem:HI
1058 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1059 (sign_extend:SI (mem:HI
1060 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1061 (match_operand:SI 3 "register_operand" "0")))]
1064 [(set_attr "length" "4")
1065 (set_attr "cc" "none_0hit")])
1067 ;; ----------------------------------------------------------------------
1068 ;; DIVIDE/MOD INSTRUCTIONS
1069 ;; ----------------------------------------------------------------------
1071 (define_insn "udivmodqi4"
1072 [(set (match_operand:QI 0 "register_operand" "=r")
1075 (match_operand:HI 1 "register_operand" "0")
1076 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1077 (set (match_operand:QI 3 "register_operand" "=r")
1081 (zero_extend:HI (match_dup 2)))))]
1085 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1086 return \"divxu.b\\t%X2,%T0\";
1088 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1090 [(set_attr "length" "4")
1091 (set_attr "cc" "clobber")])
1093 (define_insn "divmodqi4"
1094 [(set (match_operand:QI 0 "register_operand" "=r")
1097 (match_operand:HI 1 "register_operand" "0")
1098 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1099 (set (match_operand:QI 3 "register_operand" "=r")
1103 (sign_extend:HI (match_dup 2)))))]
1104 "TARGET_H8300H || TARGET_H8300S"
1107 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1108 return \"divxs.b\\t%X2,%T0\";
1110 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1112 [(set_attr "length" "6")
1113 (set_attr "cc" "clobber")])
1115 (define_insn "udivmodhi4"
1116 [(set (match_operand:HI 0 "register_operand" "=r")
1119 (match_operand:SI 1 "register_operand" "0")
1120 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1121 (set (match_operand:HI 3 "register_operand" "=r")
1125 (zero_extend:SI (match_dup 2)))))]
1126 "TARGET_H8300H || TARGET_H8300S"
1129 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1130 return \"divxu.w\\t%T2,%S0\";
1132 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1134 [(set_attr "length" "4")
1135 (set_attr "cc" "clobber")])
1137 (define_insn "divmodhi4"
1138 [(set (match_operand:HI 0 "register_operand" "=r")
1141 (match_operand:SI 1 "register_operand" "0")
1142 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1143 (set (match_operand:HI 3 "register_operand" "=r")
1147 (sign_extend:SI (match_dup 2)))))]
1148 "TARGET_H8300H || TARGET_H8300S"
1151 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1152 return \"divxs.w\\t%T2,%S0\";
1154 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1156 [(set_attr "length" "6")
1157 (set_attr "cc" "clobber")])
1159 ;; ----------------------------------------------------------------------
1161 ;; ----------------------------------------------------------------------
1164 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1165 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1166 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1167 "register_operand (operands[0], QImode)
1168 || single_zero_operand (operands[2], QImode)"
1172 [(set_attr "length" "2,8")
1173 (set_attr "adjust_length" "no")
1174 (set_attr "cc" "set_znv,none_0hit")])
1176 (define_expand "andqi3"
1177 [(set (match_operand:QI 0 "bit_operand" "")
1178 (and:QI (match_operand:QI 1 "bit_operand" "")
1179 (match_operand:QI 2 "nonmemory_operand" "")))]
1183 if (fix_bit_operand (operands, 0, AND))
1187 (define_expand "andhi3"
1188 [(set (match_operand:HI 0 "register_operand" "")
1189 (and:HI (match_operand:HI 1 "register_operand" "")
1190 (match_operand:HI 2 "nonmemory_operand" "")))]
1194 (define_insn "*andorqi3"
1195 [(set (match_operand:QI 0 "register_operand" "=r")
1196 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1197 (match_operand:QI 3 "single_one_operand" "n"))
1198 (match_operand:QI 1 "register_operand" "0")))]
1200 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1201 [(set_attr "length" "6")
1202 (set_attr "cc" "clobber")])
1204 (define_insn "*andorhi3"
1205 [(set (match_operand:HI 0 "register_operand" "=r")
1206 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1207 (match_operand:HI 3 "single_one_operand" "n"))
1208 (match_operand:HI 1 "register_operand" "0")))]
1212 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1213 if (INTVAL (operands[3]) > 128)
1215 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1216 return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\";
1218 return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\";
1220 [(set_attr "length" "6")
1221 (set_attr "cc" "clobber")])
1223 (define_insn "*andorsi3"
1224 [(set (match_operand:SI 0 "register_operand" "=r")
1225 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1226 (match_operand:SI 3 "single_one_operand" "n"))
1227 (match_operand:SI 1 "register_operand" "0")))]
1228 "(INTVAL (operands[3]) & 0xffff) != 0"
1231 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1232 if (INTVAL (operands[3]) > 128)
1234 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1235 return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\";
1237 return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\";
1239 [(set_attr "length" "6")
1240 (set_attr "cc" "clobber")])
1242 (define_insn "*andorsi3_shift_8"
1243 [(set (match_operand:SI 0 "register_operand" "=r")
1244 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1247 (match_operand:SI 1 "register_operand" "0")))]
1250 [(set_attr "length" "2")
1251 (set_attr "cc" "clobber")])
1253 (define_expand "andsi3"
1254 [(set (match_operand:SI 0 "register_operand" "")
1255 (and:SI (match_operand:SI 1 "register_operand" "")
1256 (match_operand:SI 2 "nonmemory_operand" "")))]
1260 ;; ----------------------------------------------------------------------
1262 ;; ----------------------------------------------------------------------
1265 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1266 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1267 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1268 "register_operand (operands[0], QImode)
1269 || single_one_operand (operands[2], QImode)"
1273 [(set_attr "length" "2,8")
1274 (set_attr "adjust_length" "no")
1275 (set_attr "cc" "set_znv,none_0hit")])
1277 (define_expand "iorqi3"
1278 [(set (match_operand:QI 0 "bit_operand" "")
1279 (ior:QI (match_operand:QI 1 "bit_operand" "")
1280 (match_operand:QI 2 "nonmemory_operand" "")))]
1284 if (fix_bit_operand (operands, 1, IOR))
1288 (define_expand "iorhi3"
1289 [(set (match_operand:HI 0 "register_operand" "")
1290 (ior:HI (match_operand:HI 1 "register_operand" "")
1291 (match_operand:HI 2 "nonmemory_operand" "")))]
1295 (define_expand "iorsi3"
1296 [(set (match_operand:SI 0 "register_operand" "")
1297 (ior:SI (match_operand:SI 1 "register_operand" "")
1298 (match_operand:SI 2 "nonmemory_operand" "")))]
1302 ;; ----------------------------------------------------------------------
1304 ;; ----------------------------------------------------------------------
1307 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1308 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1309 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1310 "register_operand (operands[0], QImode)
1311 || single_one_operand (operands[2], QImode)"
1315 [(set_attr "length" "2,8")
1316 (set_attr "adjust_length" "no")
1317 (set_attr "cc" "set_znv,none_0hit")])
1319 (define_expand "xorqi3"
1320 [(set (match_operand:QI 0 "bit_operand" "")
1321 (xor:QI (match_operand:QI 1 "bit_operand" "")
1322 (match_operand:QI 2 "nonmemory_operand" "")))]
1326 if (fix_bit_operand (operands, 1, XOR))
1330 (define_expand "xorhi3"
1331 [(set (match_operand:HI 0 "register_operand" "")
1332 (xor:HI (match_operand:HI 1 "register_operand" "")
1333 (match_operand:HI 2 "nonmemory_operand" "")))]
1337 (define_expand "xorsi3"
1338 [(set (match_operand:SI 0 "register_operand" "")
1339 (xor:SI (match_operand:SI 1 "register_operand" "")
1340 (match_operand:SI 2 "nonmemory_operand" "")))]
1344 ;; ----------------------------------------------------------------------
1345 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1346 ;; ----------------------------------------------------------------------
1349 [(set (match_operand:HI 0 "register_operand" "=r")
1350 (match_operator:HI 3 "bit_operator"
1351 [(match_operand:HI 1 "register_operand" "%0")
1352 (match_operand:HI 2 "nonmemory_operand" "rn")]))]
1354 "* return output_logical_op (HImode, operands);"
1355 [(set (attr "length")
1356 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1358 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1361 [(set (match_operand:SI 0 "register_operand" "=r")
1362 (match_operator:SI 3 "bit_operator"
1363 [(match_operand:SI 1 "register_operand" "%0")
1364 (match_operand:SI 2 "nonmemory_operand" "rn")]))]
1366 "* return output_logical_op (SImode, operands);"
1367 [(set (attr "length")
1368 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1370 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1372 ;; ----------------------------------------------------------------------
1373 ;; NEGATION INSTRUCTIONS
1374 ;; ----------------------------------------------------------------------
1376 (define_insn "negqi2"
1377 [(set (match_operand:QI 0 "register_operand" "=r")
1378 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1381 [(set_attr "length" "2")
1382 (set_attr "cc" "set_zn")])
1384 (define_expand "neghi2"
1385 [(set (match_operand:HI 0 "register_operand" "")
1386 (neg:HI (match_operand:HI 1 "register_operand" "")))]
1392 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1397 (define_expand "neghi2_h8300"
1399 (not:HI (match_operand:HI 1 "register_operand" "")))
1400 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1401 (set (match_operand:HI 0 "register_operand" "")
1404 "operands[2] = gen_reg_rtx (HImode);")
1406 (define_insn "neghi2_h8300h"
1407 [(set (match_operand:HI 0 "register_operand" "=r")
1408 (neg:HI (match_operand:HI 1 "register_operand" "0")))]
1409 "TARGET_H8300H || TARGET_H8300S"
1411 [(set_attr "length" "2")
1412 (set_attr "cc" "set_zn")])
1414 (define_expand "negsi2"
1415 [(set (match_operand:SI 0 "register_operand" "")
1416 (neg:SI (match_operand:SI 1 "register_operand" "")))]
1422 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1427 (define_expand "negsi2_h8300"
1429 (not:SI (match_operand:SI 1 "register_operand" "")))
1430 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1431 (set (match_operand:SI 0 "register_operand" "")
1434 "operands[2] = gen_reg_rtx (SImode);")
1436 (define_insn "negsi2_h8300h"
1437 [(set (match_operand:SI 0 "register_operand" "=r")
1438 (neg:SI (match_operand:SI 1 "register_operand" "0")))]
1439 "TARGET_H8300H || TARGET_H8300S"
1441 [(set_attr "length" "2")
1442 (set_attr "cc" "set_zn")])
1444 (define_expand "negsf2"
1445 [(set (match_operand:SF 0 "register_operand" "")
1446 (neg:SF (match_operand:SF 1 "register_operand" "")))]
1450 (define_insn "*negsf2_h8300"
1451 [(set (match_operand:SF 0 "register_operand" "=r")
1452 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1455 [(set_attr "cc" "clobber")
1456 (set_attr "length" "2")])
1458 (define_insn "*negsf2_h8300hs"
1459 [(set (match_operand:SF 0 "register_operand" "=r")
1460 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1461 "TARGET_H8300H || TARGET_H8300S"
1462 "xor.w\\t#32768,%e0"
1463 [(set_attr "cc" "clobber")
1464 (set_attr "length" "4")])
1466 ;; ----------------------------------------------------------------------
1467 ;; ABSOLUTE VALUE INSTRUCTIONS
1468 ;; ----------------------------------------------------------------------
1470 (define_expand "abssf2"
1471 [(set (match_operand:SF 0 "register_operand" "")
1472 (abs:SF (match_operand:SF 1 "register_operand" "")))]
1476 (define_insn "*abssf2_h8300"
1477 [(set (match_operand:SF 0 "register_operand" "=r")
1478 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1481 [(set_attr "cc" "clobber")
1482 (set_attr "length" "2")])
1484 (define_insn "*abssf2_h8300hs"
1485 [(set (match_operand:SF 0 "register_operand" "=r")
1486 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1487 "TARGET_H8300H || TARGET_H8300S"
1488 "and.w\\t#32767,%e0"
1489 [(set_attr "cc" "clobber")
1490 (set_attr "length" "4")])
1492 ;; ----------------------------------------------------------------------
1494 ;; ----------------------------------------------------------------------
1496 (define_insn "one_cmplqi2"
1497 [(set (match_operand:QI 0 "register_operand" "=r")
1498 (not:QI (match_operand:QI 1 "register_operand" "0")))]
1501 [(set_attr "length" "2")
1502 (set_attr "cc" "set_znv")])
1504 (define_expand "one_cmplhi2"
1505 [(set (match_operand:HI 0 "register_operand" "=r")
1506 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1511 [(set (match_operand:HI 0 "register_operand" "=r")
1512 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1515 [(set_attr "cc" "clobber")
1516 (set_attr "length" "4")])
1519 [(set (match_operand:HI 0 "register_operand" "=r")
1520 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1521 "TARGET_H8300H || TARGET_H8300S"
1523 [(set_attr "cc" "set_znv")
1524 (set_attr "length" "2")])
1526 (define_expand "one_cmplsi2"
1527 [(set (match_operand:SI 0 "register_operand" "=r")
1528 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1533 [(set (match_operand:SI 0 "register_operand" "=r")
1534 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1536 "not %w0\;not %x0\;not %y0\;not %z0"
1537 [(set_attr "cc" "clobber")
1538 (set_attr "length" "8")])
1541 [(set (match_operand:SI 0 "register_operand" "=r")
1542 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1543 "TARGET_H8300H || TARGET_H8300S"
1545 [(set_attr "cc" "set_znv")
1546 (set_attr "length" "2")])
1548 ;; ----------------------------------------------------------------------
1549 ;; JUMP INSTRUCTIONS
1550 ;; ----------------------------------------------------------------------
1552 ;; Conditional jump instructions
1554 (define_expand "ble"
1556 (if_then_else (le (cc0)
1558 (label_ref (match_operand 0 "" ""))
1563 (define_expand "bleu"
1565 (if_then_else (leu (cc0)
1567 (label_ref (match_operand 0 "" ""))
1572 (define_expand "bge"
1574 (if_then_else (ge (cc0)
1576 (label_ref (match_operand 0 "" ""))
1581 (define_expand "bgeu"
1583 (if_then_else (geu (cc0)
1585 (label_ref (match_operand 0 "" ""))
1590 (define_expand "blt"
1592 (if_then_else (lt (cc0)
1594 (label_ref (match_operand 0 "" ""))
1599 (define_expand "bltu"
1601 (if_then_else (ltu (cc0)
1603 (label_ref (match_operand 0 "" ""))
1608 (define_expand "bgt"
1610 (if_then_else (gt (cc0)
1612 (label_ref (match_operand 0 "" ""))
1617 (define_expand "bgtu"
1619 (if_then_else (gtu (cc0)
1621 (label_ref (match_operand 0 "" ""))
1626 (define_expand "beq"
1628 (if_then_else (eq (cc0)
1630 (label_ref (match_operand 0 "" ""))
1635 (define_expand "bne"
1637 (if_then_else (ne (cc0)
1639 (label_ref (match_operand 0 "" ""))
1644 (define_insn "branch_true"
1646 (if_then_else (match_operator 1 "comparison_operator"
1647 [(cc0) (const_int 0)])
1648 (label_ref (match_operand 0 "" ""))
1653 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1654 && (GET_CODE (operands[1]) == GT
1655 || GET_CODE (operands[1]) == GE
1656 || GET_CODE (operands[1]) == LE
1657 || GET_CODE (operands[1]) == LT))
1659 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1663 if (get_attr_length (insn) == 2)
1664 return \"b%j1 %l0\";
1665 else if (get_attr_length (insn) == 4)
1666 return \"b%j1 %l0:16\";
1668 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1670 [(set_attr "type" "branch")
1671 (set_attr "cc" "none")])
1673 (define_insn "branch_false"
1675 (if_then_else (match_operator 1 "comparison_operator"
1676 [(cc0) (const_int 0)])
1678 (label_ref (match_operand 0 "" ""))))]
1682 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1683 && (GET_CODE (operands[1]) == GT
1684 || GET_CODE (operands[1]) == GE
1685 || GET_CODE (operands[1]) == LE
1686 || GET_CODE (operands[1]) == LT))
1688 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1692 if (get_attr_length (insn) == 2)
1693 return \"b%k1 %l0\";
1694 else if (get_attr_length (insn) == 4)
1695 return \"b%k1 %l0:16\";
1697 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1699 [(set_attr "type" "branch")
1700 (set_attr "cc" "none")])
1702 ;; Unconditional and other jump instructions.
1706 (label_ref (match_operand 0 "" "")))]
1710 if (get_attr_length (insn) == 2)
1712 else if (get_attr_length (insn) == 4)
1713 return \"bra %l0:16\";
1715 return \"jmp @%l0\";
1717 [(set_attr "type" "branch")
1718 (set_attr "cc" "none")])
1720 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1722 (define_expand "tablejump"
1723 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
1724 (use (label_ref (match_operand 1 "" "")))])]
1728 (define_insn "tablejump_h8300"
1729 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1730 (use (label_ref (match_operand 1 "" "")))]
1733 [(set_attr "cc" "none")
1734 (set_attr "length" "2")])
1736 (define_insn "tablejump_h8300h"
1737 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1738 (use (label_ref (match_operand 1 "" "")))]
1739 "TARGET_H8300H || TARGET_H8300S"
1741 [(set_attr "cc" "none")
1742 (set_attr "length" "2")])
1744 (define_insn "tablejump_normal_mode"
1745 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1746 (use (label_ref (match_operand 1 "" "")))]
1747 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1749 [(set_attr "cc" "none")
1750 (set_attr "length" "2")])
1752 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1754 (define_expand "indirect_jump"
1755 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1759 (define_insn "indirect_jump_h8300"
1760 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1763 [(set_attr "cc" "none")
1764 (set_attr "length" "2")])
1766 (define_insn "indirect_jump_h8300h"
1767 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1768 "TARGET_H8300H || TARGET_H8300S"
1770 [(set_attr "cc" "none")
1771 (set_attr "length" "2")])
1773 (define_insn "indirect_jump_normal_mode"
1774 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1775 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1777 [(set_attr "cc" "none")
1778 (set_attr "length" "2")])
1780 ;; Call subroutine with no return value.
1782 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1785 [(call (match_operand:QI 0 "call_insn_operand" "or")
1786 (match_operand:HI 1 "general_operand" "g"))]
1790 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1791 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1792 return \"jsr\\t@%0:8\";
1794 return \"jsr\\t%0\";
1796 [(set_attr "cc" "clobber")
1797 (set (attr "length")
1798 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1802 ;; Call subroutine, returning value in operand 0
1803 ;; (which must be a hard register).
1805 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1807 (define_insn "call_value"
1808 [(set (match_operand 0 "" "=r")
1809 (call (match_operand:QI 1 "call_insn_operand" "or")
1810 (match_operand:HI 2 "general_operand" "g")))]
1814 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1815 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1816 return \"jsr\\t@%1:8\";
1818 return \"jsr\\t%1\";
1820 [(set_attr "cc" "clobber")
1821 (set (attr "length")
1822 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1830 [(set_attr "cc" "none")
1831 (set_attr "length" "2")])
1833 ;; ----------------------------------------------------------------------
1834 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
1835 ;; ----------------------------------------------------------------------
1837 (define_expand "push_h8300"
1838 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
1839 (match_operand:HI 0 "register_operand" "=r"))]
1844 (define_expand "push_h8300hs"
1845 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
1846 (match_operand:SI 0 "register_operand" "=r"))]
1847 "TARGET_H8300H && TARGET_H8300S"
1850 (define_expand "pop_h8300"
1851 [(set (match_operand:HI 0 "register_operand" "=r")
1852 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
1856 (define_expand "pop_h8300hs"
1857 [(set (match_operand:SI 0 "register_operand" "=r")
1858 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
1859 "TARGET_H8300H && TARGET_H8300S"
1862 (define_insn "stm_h8300s_2"
1864 [(set (reg:SI SP_REG)
1865 (plus:SI (reg:SI SP_REG) (const_int -8)))
1866 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1867 (match_operand:SI 0 "register_operand" ""))
1868 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1869 (match_operand:SI 1 "register_operand" ""))])]
1871 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
1872 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
1873 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
1874 "stm.l\\t%S0-%S1,@-er7"
1875 [(set_attr "cc" "none")
1876 (set_attr "length" "4")])
1878 (define_insn "stm_h8300s_3"
1880 [(set (reg:SI SP_REG)
1881 (plus:SI (reg:SI SP_REG) (const_int -12)))
1882 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1883 (match_operand:SI 0 "register_operand" ""))
1884 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1885 (match_operand:SI 1 "register_operand" ""))
1886 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1887 (match_operand:SI 2 "register_operand" ""))])]
1889 && ((REGNO (operands[0]) == 0
1890 && REGNO (operands[1]) == 1
1891 && REGNO (operands[2]) == 2)
1892 || (REGNO (operands[0]) == 4
1893 && REGNO (operands[1]) == 5
1894 && REGNO (operands[2]) == 6))"
1895 "stm.l\\t%S0-%S2,@-er7"
1896 [(set_attr "cc" "none")
1897 (set_attr "length" "4")])
1899 (define_insn "stm_h8300s_4"
1901 [(set (reg:SI SP_REG)
1902 (plus:SI (reg:SI SP_REG) (const_int -16)))
1903 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1904 (match_operand:SI 0 "register_operand" ""))
1905 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1906 (match_operand:SI 1 "register_operand" ""))
1907 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1908 (match_operand:SI 2 "register_operand" ""))
1909 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
1910 (match_operand:SI 3 "register_operand" ""))])]
1912 && REGNO (operands[0]) == 0
1913 && REGNO (operands[1]) == 1
1914 && REGNO (operands[2]) == 2
1915 && REGNO (operands[3]) == 3"
1916 "stm.l\\t%S0-%S3,@-er7"
1917 [(set_attr "cc" "none")
1918 (set_attr "length" "4")])
1920 (define_insn "ldm_h8300s_2"
1922 [(set (reg:SI SP_REG)
1923 (plus:SI (reg:SI SP_REG) (const_int 8)))
1924 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
1925 (match_operand:SI 0 "register_operand" ""))
1926 (set (mem:SI (reg:SI SP_REG))
1927 (match_operand:SI 1 "register_operand" ""))])]
1929 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
1930 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
1931 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
1932 "ldm.l\\t@er7+,%S0-%S1"
1933 [(set_attr "cc" "none")
1934 (set_attr "length" "4")])
1936 (define_insn "ldm_h8300s_3"
1938 [(set (reg:SI SP_REG)
1939 (plus:SI (reg:SI SP_REG) (const_int 12)))
1940 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
1941 (match_operand:SI 0 "register_operand" ""))
1942 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
1943 (match_operand:SI 1 "register_operand" ""))
1944 (set (mem:SI (reg:SI SP_REG))
1945 (match_operand:SI 2 "register_operand" ""))])]
1947 && ((REGNO (operands[0]) == 0
1948 && REGNO (operands[1]) == 1
1949 && REGNO (operands[2]) == 2)
1950 || (REGNO (operands[0]) == 4
1951 && REGNO (operands[1]) == 5
1952 && REGNO (operands[2]) == 6))"
1953 "ldm.l\\t@er7+,%S0-%S2"
1954 [(set_attr "cc" "none")
1955 (set_attr "length" "4")])
1957 (define_insn "ldm_h8300s_4"
1959 [(set (reg:SI SP_REG)
1960 (plus:SI (reg:SI SP_REG) (const_int 16)))
1961 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 12)))
1962 (match_operand:SI 0 "register_operand" ""))
1963 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
1964 (match_operand:SI 1 "register_operand" ""))
1965 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
1966 (match_operand:SI 2 "register_operand" ""))
1967 (set (mem:SI (reg:SI SP_REG))
1968 (match_operand:SI 3 "register_operand" ""))])]
1970 && REGNO (operands[0]) == 0
1971 && REGNO (operands[1]) == 1
1972 && REGNO (operands[2]) == 2
1973 && REGNO (operands[3]) == 3"
1974 "ldm.l\\t@er7+,%S0-%S3"
1975 [(set_attr "cc" "none")
1976 (set_attr "length" "4")])
1978 (define_expand "return"
1980 "h8300_can_use_return_insn_p ()"
1983 (define_insn "*return_1"
1988 if (h8300_current_function_interrupt_function_p ())
1993 [(set_attr "cc" "none")
1994 (set_attr "length" "2")])
1996 (define_expand "prologue"
1999 "h8300_expand_prologue (); DONE;")
2001 (define_expand "epilogue"
2004 "h8300_expand_epilogue ();")
2006 (define_insn "monitor_prologue"
2007 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2012 return \"subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr\";
2013 else if (TARGET_H8300H)
2014 return \"mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr\";
2015 else if (TARGET_H8300S)
2016 return \"stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\";
2019 [(set_attr "length" "20")
2020 (set_attr "cc" "clobber")])
2022 ;; ----------------------------------------------------------------------
2023 ;; EXTEND INSTRUCTIONS
2024 ;; ----------------------------------------------------------------------
2026 (define_expand "zero_extendqihi2"
2027 [(set (match_operand:HI 0 "register_operand" "")
2028 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2032 (define_insn "*zero_extendqihi2_h8300"
2033 [(set (match_operand:HI 0 "register_operand" "=r,r")
2034 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2039 [(set_attr "length" "2,10")
2040 (set_attr "cc" "clobber,clobber")])
2042 (define_insn "*zero_extendqihi2_h8300hs"
2043 [(set (match_operand:HI 0 "register_operand" "=r,r")
2044 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2045 "TARGET_H8300H || TARGET_H8300S"
2049 [(set_attr "length" "2,10")
2050 (set_attr "cc" "set_znv,set_znv")])
2052 ;; Split the zero extension of a general operand (actually a memory
2053 ;; operand) into a load of the operand and the actual zero extension
2054 ;; so that 1) the length will be accurate, and 2) the zero extensions
2055 ;; appearing at the end of basic blocks may be merged.
2058 [(set (match_operand:HI 0 "register_operand" "")
2059 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2064 (zero_extend:HI (match_dup 2)))]
2065 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2067 (define_expand "zero_extendqisi2"
2068 [(set (match_operand:SI 0 "register_operand" "")
2069 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2073 (define_insn "*zero_extendqisi2_h8300"
2074 [(set (match_operand:SI 0 "register_operand" "=r,r")
2075 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2078 mov.b #0,%x0\;sub.w %e0,%e0
2079 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
2080 [(set_attr "length" "4,8")
2081 (set_attr "cc" "clobber,clobber")])
2083 (define_insn "*zero_extendqisi2_h8300hs"
2084 [(set (match_operand:SI 0 "register_operand" "=r,r")
2085 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2086 "TARGET_H8300H || TARGET_H8300S"
2088 extu.w %T0\;extu.l %S0
2089 mov.b %R1,%w0\;extu.w %T0\;extu.l %S0"
2090 [(set_attr "length" "4,12")
2091 (set_attr "cc" "set_znv,set_znv")])
2094 [(set (match_operand:SI 0 "register_operand" "")
2095 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2096 "(TARGET_H8300H || TARGET_H8300S)
2097 && reg_overlap_mentioned_p (operands[0], operands[1])
2098 && reload_completed"
2102 (zero_extend:SI (match_dup 2)))]
2103 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2106 [(set (match_operand:SI 0 "register_operand" "")
2107 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2108 "(TARGET_H8300H || TARGET_H8300S)
2109 && !reg_overlap_mentioned_p (operands[0], operands[1])
2110 && reload_completed"
2113 (set (strict_low_part (match_dup 2))
2115 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2117 (define_expand "zero_extendhisi2"
2118 [(set (match_operand:SI 0 "register_operand" "")
2119 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2123 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
2124 (define_insn "*zero_extendhisi2_h8300"
2125 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2126 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
2130 mov.w %f1,%f0\;sub.w %e0,%e0
2131 mov.w %e1,%f0\;sub.w %e0,%e0"
2132 [(set_attr "length" "2,4,6")
2133 (set_attr "cc" "clobber,clobber,clobber")])
2136 [(set (match_operand:SI 0 "register_operand" "=r")
2137 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2138 "TARGET_H8300H || TARGET_H8300S"
2140 [(set_attr "length" "2")
2141 (set_attr "cc" "set_znv")])
2143 (define_expand "extendqihi2"
2144 [(set (match_operand:HI 0 "register_operand" "")
2145 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
2150 [(set (match_operand:HI 0 "register_operand" "=r,r")
2151 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2154 bld #7,%s0\;subx %t0,%t0
2155 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
2156 [(set_attr "length" "4,8")
2157 (set_attr "cc" "clobber,clobber")])
2160 [(set (match_operand:HI 0 "register_operand" "=r")
2161 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
2162 "TARGET_H8300H || TARGET_H8300S"
2164 [(set_attr "length" "2")
2165 (set_attr "cc" "set_znv")])
2167 (define_expand "extendqisi2"
2168 [(set (match_operand:SI 0 "register_operand" "=r,r")
2169 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2173 (define_insn "*extendqisi2_h8300"
2174 [(set (match_operand:SI 0 "register_operand" "")
2175 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2178 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
2179 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
2180 [(set_attr "length" "8,12")
2181 (set_attr "cc" "clobber,clobber")])
2183 ;; The following pattern is needed because without the pattern, the
2184 ;; combiner would split (sign_extend:SI (reg:QI)) into into two 24-bit
2185 ;; shifts, one ashift and one ashiftrt.
2187 (define_insn_and_split "*extendqisi2_h8300hs"
2188 [(set (match_operand:SI 0 "register_operand" "=r")
2189 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2190 "(TARGET_H8300H || TARGET_H8300S)"
2192 "&& reload_completed"
2194 (sign_extend:HI (match_dup 1)))
2196 (sign_extend:SI (match_dup 2)))]
2197 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2199 (define_expand "extendhisi2"
2200 [(set (match_operand:SI 0 "register_operand" "")
2201 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2205 (define_insn "*extendhisi2_h8300"
2206 [(set (match_operand:SI 0 "register_operand" "=r,r")
2207 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
2210 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
2211 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
2212 [(set_attr "length" "6,10")
2213 (set_attr "cc" "clobber,clobber")])
2216 [(set (match_operand:SI 0 "register_operand" "=r")
2217 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2218 "TARGET_H8300H || TARGET_H8300S"
2220 [(set_attr "length" "2")
2221 (set_attr "cc" "set_znv")])
2223 ;; ----------------------------------------------------------------------
2225 ;; ----------------------------------------------------------------------
2227 ;; We make some attempt to provide real efficient shifting. One example is
2228 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
2229 ;; reg and moving 0 into the former reg.
2231 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2232 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2233 ;; give the optimizer more cracks at the code. However, we wish to do things
2234 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
2235 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
2236 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
2237 ;; to detect cases it can optimize.
2239 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2240 ;; easier "do it at insn emit time" route.
2244 (define_expand "ashlqi3"
2245 [(set (match_operand:QI 0 "register_operand" "")
2246 (ashift:QI (match_operand:QI 1 "register_operand" "")
2247 (match_operand:QI 2 "nonmemory_operand" "")))]
2249 "expand_a_shift (QImode, ASHIFT, operands); DONE;")
2251 (define_expand "ashrqi3"
2252 [(set (match_operand:QI 0 "register_operand" "")
2253 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2254 (match_operand:QI 2 "nonmemory_operand" "")))]
2256 "expand_a_shift (QImode, ASHIFTRT, operands); DONE;")
2258 (define_expand "lshrqi3"
2259 [(set (match_operand:QI 0 "register_operand" "")
2260 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2261 (match_operand:QI 2 "nonmemory_operand" "")))]
2263 "expand_a_shift (QImode, LSHIFTRT, operands); DONE;")
2266 [(set (match_operand:QI 0 "register_operand" "=r,r")
2267 (match_operator:QI 3 "nshift_operator"
2268 [ (match_operand:QI 1 "register_operand" "0,0")
2269 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2270 (clobber (match_scratch:QI 4 "=X,&r"))]
2272 "* return output_a_shift (operands);"
2273 [(set (attr "length")
2274 (symbol_ref "compute_a_shift_length (insn, operands)"))
2275 (set_attr "cc" "clobber")])
2279 (define_expand "ashlhi3"
2280 [(set (match_operand:HI 0 "register_operand" "")
2281 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
2282 (match_operand:QI 2 "nonmemory_operand" "")))]
2284 "expand_a_shift (HImode, ASHIFT, operands); DONE;")
2286 (define_expand "lshrhi3"
2287 [(set (match_operand:HI 0 "register_operand" "")
2288 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
2289 (match_operand:QI 2 "nonmemory_operand" "")))]
2291 "expand_a_shift (HImode, LSHIFTRT, operands); DONE;")
2293 (define_expand "ashrhi3"
2294 [(set (match_operand:HI 0 "register_operand" "")
2295 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
2296 (match_operand:QI 2 "nonmemory_operand" "")))]
2298 "expand_a_shift (HImode, ASHIFTRT, operands); DONE;")
2301 [(set (match_operand:HI 0 "register_operand" "=r,r")
2302 (match_operator:HI 3 "nshift_operator"
2303 [ (match_operand:HI 1 "register_operand" "0,0")
2304 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
2305 (clobber (match_scratch:QI 4 "=X,&r"))]
2307 "* return output_a_shift (operands);"
2308 [(set (attr "length")
2309 (symbol_ref "compute_a_shift_length (insn, operands)"))
2310 (set_attr "cc" "clobber")])
2314 (define_expand "ashlsi3"
2315 [(set (match_operand:SI 0 "register_operand" "")
2316 (ashift:SI (match_operand:SI 1 "general_operand" "")
2317 (match_operand:QI 2 "nonmemory_operand" "")))]
2319 "expand_a_shift (SImode, ASHIFT, operands); DONE;")
2321 (define_expand "lshrsi3"
2322 [(set (match_operand:SI 0 "register_operand" "")
2323 (lshiftrt:SI (match_operand:SI 1 "general_operand" "")
2324 (match_operand:QI 2 "nonmemory_operand" "")))]
2326 "expand_a_shift (SImode, LSHIFTRT, operands); DONE;")
2328 (define_expand "ashrsi3"
2329 [(set (match_operand:SI 0 "register_operand" "")
2330 (ashiftrt:SI (match_operand:SI 1 "general_operand" "")
2331 (match_operand:QI 2 "nonmemory_operand" "")))]
2333 "expand_a_shift (SImode, ASHIFTRT, operands); DONE;")
2336 [(set (match_operand:SI 0 "register_operand" "=r,r")
2337 (match_operator:SI 3 "nshift_operator"
2338 [ (match_operand:SI 1 "register_operand" "0,0")
2339 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
2340 (clobber (match_scratch:QI 4 "=X,&r"))]
2342 "* return output_a_shift (operands);"
2343 [(set (attr "length")
2344 (symbol_ref "compute_a_shift_length (insn, operands)"))
2345 (set_attr "cc" "clobber")])
2347 ;; Split a variable shift into a loop. If the register containing
2348 ;; the shift count dies, then we just use that register.
2352 [(set (match_operand 0 "register_operand" "")
2353 (match_operator 2 "nshift_operator"
2355 (match_operand:QI 1 "register_operand" "")]))
2356 (clobber (match_operand:QI 3 "register_operand" ""))])]
2358 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2362 (if_then_else (le (cc0) (const_int 0))
2363 (label_ref (match_dup 5))
2368 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2369 (clobber (scratch:QI))])
2371 (plus:QI (match_dup 1) (const_int -1)))
2375 (if_then_else (ne (cc0) (const_int 0))
2376 (label_ref (match_dup 4))
2379 "operands[4] = gen_label_rtx ();
2380 operands[5] = gen_label_rtx ();")
2384 [(set (match_operand 0 "register_operand" "")
2385 (match_operator 2 "nshift_operator"
2387 (match_operand:QI 1 "register_operand" "")]))
2388 (clobber (match_operand:QI 3 "register_operand" ""))])]
2390 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2396 (if_then_else (le (cc0) (const_int 0))
2397 (label_ref (match_dup 5))
2402 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2403 (clobber (scratch:QI))])
2405 (plus:QI (match_dup 3) (const_int -1)))
2409 (if_then_else (ne (cc0) (const_int 0))
2410 (label_ref (match_dup 4))
2413 "operands[4] = gen_label_rtx ();
2414 operands[5] = gen_label_rtx ();")
2416 ;; ----------------------------------------------------------------------
2418 ;; ----------------------------------------------------------------------
2420 (define_expand "rotlqi3"
2421 [(set (match_operand:QI 0 "register_operand" "")
2422 (rotate:QI (match_operand:QI 1 "register_operand" "")
2423 (match_operand:QI 2 "nonmemory_operand" "")))]
2425 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2427 (define_insn "*rotlqi3_1"
2428 [(set (match_operand:QI 0 "register_operand" "=r")
2429 (rotate:QI (match_operand:QI 1 "register_operand" "0")
2430 (match_operand:QI 2 "immediate_operand" "")))]
2432 "* return emit_a_rotate (ROTATE, operands);"
2433 [(set_attr "length" "20")
2434 (set_attr "cc" "clobber")])
2436 (define_expand "rotlhi3"
2437 [(set (match_operand:HI 0 "register_operand" "")
2438 (rotate:HI (match_operand:HI 1 "register_operand" "")
2439 (match_operand:QI 2 "nonmemory_operand" "")))]
2441 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2443 (define_insn "*rotlhi3_1"
2444 [(set (match_operand:HI 0 "register_operand" "=r")
2445 (rotate:HI (match_operand:HI 1 "register_operand" "0")
2446 (match_operand:QI 2 "immediate_operand" "")))]
2448 "* return emit_a_rotate (ROTATE, operands);"
2449 [(set_attr "length" "20")
2450 (set_attr "cc" "clobber")])
2452 (define_expand "rotlsi3"
2453 [(set (match_operand:SI 0 "register_operand" "")
2454 (rotate:SI (match_operand:SI 1 "register_operand" "")
2455 (match_operand:QI 2 "nonmemory_operand" "")))]
2456 "TARGET_H8300H || TARGET_H8300S"
2457 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2459 (define_insn "*rotlsi3_1"
2460 [(set (match_operand:SI 0 "register_operand" "=r")
2461 (rotate:SI (match_operand:SI 1 "register_operand" "0")
2462 (match_operand:QI 2 "immediate_operand" "")))]
2463 "TARGET_H8300H || TARGET_H8300S"
2464 "* return emit_a_rotate (ROTATE, operands);"
2465 [(set_attr "length" "20")
2466 (set_attr "cc" "clobber")])
2468 ;; -----------------------------------------------------------------
2470 ;; -----------------------------------------------------------------
2471 ;; The H8/300 has given 1/8th of its opcode space to bitfield
2472 ;; instructions so let's use them as well as we can.
2474 ;; You'll never believe all these patterns perform one basic action --
2475 ;; load a bit from the source, optionally invert the bit, then store it
2476 ;; in the destination (which is known to be zero).
2478 ;; Combine obviously need some work to better identify this situation and
2479 ;; canonicalize the form better.
2482 ;; Normal loads with a 16bit destination.
2486 [(set (match_operand:HI 0 "register_operand" "=&r")
2487 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2489 (match_operand:HI 2 "immediate_operand" "n")))]
2491 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
2492 [(set_attr "cc" "clobber")
2493 (set_attr "length" "6")])
2496 ;; Inverted loads with a 16bit destination.
2500 [(set (match_operand:HI 0 "register_operand" "=&r")
2501 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
2502 (match_operand:HI 3 "const_int_operand" "n"))
2504 (match_operand:HI 2 "const_int_operand" "n")))]
2506 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2507 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2508 [(set_attr "cc" "clobber")
2509 (set_attr "length" "8")])
2512 ;; Normal loads with a 32bit destination.
2515 (define_insn "*extzv_1_r_h8300"
2516 [(set (match_operand:SI 0 "register_operand" "=&r")
2517 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2519 (match_operand 2 "const_int_operand" "n")))]
2521 && INTVAL (operands[2]) < 16"
2522 "* return output_simode_bld (0, operands);"
2523 [(set_attr "cc" "clobber")
2524 (set_attr "length" "8")])
2526 (define_insn "*extzv_1_r_h8300hs"
2527 [(set (match_operand:SI 0 "register_operand" "=r,r")
2528 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2530 (match_operand 2 "const_int_operand" "n,n")))]
2531 "(TARGET_H8300H || TARGET_H8300S)
2532 && INTVAL (operands[2]) < 16"
2533 "* return output_simode_bld (0, operands);"
2534 [(set_attr "cc" "clobber,clobber")
2535 (set_attr "length" "8,6")])
2538 ;; Inverted loads with a 32bit destination.
2541 (define_insn "*extzv_1_r_inv_h8300"
2542 [(set (match_operand:SI 0 "register_operand" "=&r")
2543 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2544 (match_operand:HI 3 "const_int_operand" "n"))
2546 (match_operand 2 "const_int_operand" "n")))]
2548 && INTVAL (operands[2]) < 16
2549 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2550 "* return output_simode_bld (1, operands);"
2551 [(set_attr "cc" "clobber")
2552 (set_attr "length" "8")])
2554 (define_insn "*extzv_1_r_inv_h8300hs"
2555 [(set (match_operand:SI 0 "register_operand" "=r,r")
2556 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
2557 (match_operand 3 "const_int_operand" "n,n"))
2559 (match_operand 2 "const_int_operand" "n,n")))]
2560 "(TARGET_H8300H || TARGET_H8300S)
2561 && INTVAL (operands[2]) < 16
2562 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2563 "* return output_simode_bld (1, operands);"
2564 [(set_attr "cc" "clobber,clobber")
2565 (set_attr "length" "8,6")])
2567 (define_expand "insv"
2568 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2569 (match_operand:HI 1 "general_operand" "")
2570 (match_operand:HI 2 "general_operand" ""))
2571 (match_operand:HI 3 "general_operand" ""))]
2575 /* We only have single bit bit-field instructions. */
2576 if (INTVAL (operands[1]) != 1)
2579 /* For now, we don't allow memory operands. */
2580 if (GET_CODE (operands[0]) == MEM
2581 || GET_CODE (operands[3]) == MEM)
2586 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2588 (match_operand:HI 1 "immediate_operand" "n"))
2589 (match_operand:HI 2 "register_operand" "r"))]
2591 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2592 [(set_attr "cc" "clobber")
2593 (set_attr "length" "4")])
2595 (define_expand "extzv"
2596 [(set (match_operand:HI 0 "register_operand" "")
2597 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2598 (match_operand:HI 2 "general_operand" "")
2599 (match_operand:HI 3 "general_operand" "")))]
2603 /* We only have single bit bit-field instructions. */
2604 if (INTVAL (operands[2]) != 1)
2607 /* For now, we don't allow memory operands. */
2608 if (GET_CODE (operands[1]) == MEM)
2612 ;; BAND, BOR, and BXOR patterns
2615 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2616 (match_operator:HI 4 "bit_operator"
2617 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2619 (match_operand:HI 2 "immediate_operand" "n"))
2620 (match_operand:HI 3 "bit_operand" "0")]))]
2622 "bld %Z2,%Y1\;%b4 #0,%R0\;bst #0,%R0; bl1"
2623 [(set_attr "cc" "clobber")
2624 (set_attr "length" "6")
2625 (set_attr "adjust_length" "no")])
2628 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2629 (match_operator:HI 5 "bit_operator"
2630 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2632 (match_operand:HI 2 "immediate_operand" "n"))
2633 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2635 (match_operand:HI 4 "immediate_operand" "n"))]))]
2637 "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%R0; bl3"
2638 [(set_attr "cc" "clobber")
2639 (set_attr "length" "6")
2640 (set_attr "adjust_length" "no")])
2642 ;; -----------------------------------------------------------------
2644 ;; -----------------------------------------------------------------
2648 (define_insn "*extzv_8_8"
2649 [(set (match_operand:SI 0 "register_operand" "=r,r")
2650 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2653 "TARGET_H8300H || TARGET_H8300S"
2655 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
2656 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
2657 [(set_attr "cc" "set_znv,clobber")
2658 (set_attr "length" "6,4")])
2660 (define_insn "*extzv_8_16"
2661 [(set (match_operand:SI 0 "register_operand" "=r")
2662 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2665 "TARGET_H8300H || TARGET_H8300S"
2666 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
2667 [(set_attr "cc" "set_znv")
2668 (set_attr "length" "6")])
2670 (define_insn "*extzv_16_8"
2671 [(set (match_operand:SI 0 "register_operand" "=r")
2672 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2675 (clobber (match_scratch:SI 2 "=&r"))]
2677 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
2678 [(set_attr "length" "8")
2679 (set_attr "cc" "set_znv")])
2681 ;; Extract the exponent of a float.
2683 (define_insn_and_split "*extzv_8_23"
2684 [(set (match_operand:SI 0 "register_operand" "=r")
2685 (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
2688 "(TARGET_H8300H || TARGET_H8300S)"
2690 "&& reload_completed"
2691 [(parallel [(set (match_dup 0)
2692 (ashift:SI (match_dup 0)
2694 (clobber (scratch:QI))])
2695 (parallel [(set (match_dup 0)
2696 (lshiftrt:SI (match_dup 0)
2698 (clobber (scratch:QI))])]
2703 ;; ((SImode) HImode) << 15
2705 (define_insn_and_split "*twoshifts_l16_r1"
2706 [(set (match_operand:SI 0 "register_operand" "=r")
2707 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2709 (const_int 2147450880)))]
2710 "(TARGET_H8300H || TARGET_H8300S)"
2712 "&& reload_completed"
2713 [(parallel [(set (match_dup 0)
2714 (ashift:SI (match_dup 0)
2716 (clobber (scratch:QI))])
2717 (parallel [(set (match_dup 0)
2718 (lshiftrt:SI (match_dup 0)
2720 (clobber (scratch:QI))])]
2723 ;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
2725 (define_insn_and_split "*andsi3_ashift_n_lower"
2726 [(set (match_operand:SI 0 "register_operand" "=r,r")
2727 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
2728 (match_operand:QI 2 "const_int_operand" "S,n"))
2729 (match_operand:SI 3 "const_int_operand" "n,n")))
2730 (clobber (match_scratch:QI 4 "=X,&r"))]
2731 "(TARGET_H8300H || TARGET_H8300S)
2732 && INTVAL (operands[2]) <= 15
2733 && INTVAL (operands[3]) == ((-1 << INTVAL (operands[2])) & 0xffff)"
2735 "&& reload_completed"
2736 [(parallel [(set (match_dup 5)
2737 (ashift:HI (match_dup 5)
2739 (clobber (match_dup 4))])
2741 (zero_extend:SI (match_dup 5)))]
2742 "operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2744 ;; Accept (A >> 30) & 2 and the like.
2746 (define_insn "*andsi3_lshiftrt_n_sb"
2747 [(set (match_operand:SI 0 "register_operand" "=r")
2748 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
2749 (match_operand:SI 2 "const_int_operand" "n"))
2750 (match_operand:SI 3 "single_one_operand" "n")))]
2751 "(TARGET_H8300H || TARGET_H8300S)
2752 && exact_log2 (INTVAL (operands[3])) < 16
2753 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
2756 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
2757 return \"shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0\";
2759 [(set_attr "length" "8")
2760 (set_attr "cc" "clobber")])
2762 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
2763 [(set (match_operand:SI 0 "register_operand" "=r")
2764 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
2766 (const_int 4194304)))]
2767 "(TARGET_H8300H || TARGET_H8300S)"
2769 "&& reload_completed"
2771 (and:SI (lshiftrt:SI (match_dup 0)
2774 (parallel [(set (match_dup 0)
2775 (ashift:SI (match_dup 0)
2777 (clobber (scratch:QI))])]
2782 (define_insn "*addsi3_upper"
2783 [(set (match_operand:SI 0 "register_operand" "=r")
2784 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
2786 (match_operand:SI 2 "register_operand" "0")))]
2787 "TARGET_H8300H || TARGET_H8300S"
2789 [(set_attr "length" "2")
2790 (set_attr "cc" "clobber")])
2792 (define_insn "*addsi3_lshiftrt_16_zexthi"
2793 [(set (match_operand:SI 0 "register_operand" "=r")
2794 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2796 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
2797 "TARGET_H8300H || TARGET_H8300S"
2798 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0,%e0"
2799 [(set_attr "cc" "clobber")
2800 (set_attr "length" "6")])
2804 (define_insn "*ixorhi3_zext"
2805 [(set (match_operand:HI 0 "register_operand" "=r")
2806 (match_operator:HI 1 "iorxor_operator"
2807 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
2808 (match_operand:HI 3 "register_operand" "0")]))]
2811 [(set_attr "cc" "clobber")
2812 (set_attr "length" "2")])
2816 (define_insn "*ixorsi3_zext_qi"
2817 [(set (match_operand:SI 0 "register_operand" "=r")
2818 (match_operator:SI 1 "iorxor_operator"
2819 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
2820 (match_operand:SI 3 "register_operand" "0")]))]
2823 [(set_attr "cc" "clobber")
2824 (set_attr "length" "2")])
2826 (define_insn "*ixorsi3_zext_hi"
2827 [(set (match_operand:SI 0 "register_operand" "=r")
2828 (match_operator:SI 1 "iorxor_operator"
2829 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
2830 (match_operand:SI 3 "register_operand" "0")]))]
2831 "TARGET_H8300H || TARGET_H8300S"
2833 [(set_attr "cc" "clobber")
2834 (set_attr "length" "2")])
2836 (define_insn "*ixorsi3_ashift_16"
2837 [(set (match_operand:SI 0 "register_operand" "=r")
2838 (match_operator:SI 1 "iorxor_operator"
2839 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
2841 (match_operand:SI 3 "register_operand" "0")]))]
2842 "TARGET_H8300H || TARGET_H8300S"
2844 [(set_attr "cc" "clobber")
2845 (set_attr "length" "2")])
2847 (define_insn "*ixorsi3_lshiftrt_16"
2848 [(set (match_operand:SI 0 "register_operand" "=r")
2849 (match_operator:SI 1 "iorxor_operator"
2850 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2852 (match_operand:SI 3 "register_operand" "0")]))]
2853 "TARGET_H8300H || TARGET_H8300S"
2855 [(set_attr "cc" "clobber")
2856 (set_attr "length" "2")])
2860 (define_insn "*iorhi3_ashift_8"
2861 [(set (match_operand:HI 0 "register_operand" "=r")
2862 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
2864 (match_operand:HI 2 "register_operand" "0")))]
2867 [(set_attr "cc" "clobber")
2868 (set_attr "length" "2")])
2870 (define_insn "*iorhi3_lshiftrt_8"
2871 [(set (match_operand:HI 0 "register_operand" "=r")
2872 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
2874 (match_operand:HI 2 "register_operand" "0")))]
2877 [(set_attr "cc" "clobber")
2878 (set_attr "length" "2")])
2880 (define_insn "*iorhi3_two_qi"
2881 [(set (match_operand:HI 0 "register_operand" "=r")
2882 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
2883 (ashift:HI (match_operand:HI 2 "register_operand" "r")
2887 [(set_attr "cc" "clobber")
2888 (set_attr "length" "2")])
2890 (define_insn "*iorhi3_two_qi_mem"
2891 [(set (match_operand:HI 0 "register_operand" "=&r")
2892 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
2893 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
2896 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
2897 [(set_attr "cc" "clobber")
2898 (set_attr "length" "16")])
2901 [(set (match_operand:HI 0 "register_operand" "")
2902 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
2903 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
2905 "(TARGET_H8300H || TARGET_H8300S)
2907 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
2910 "operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));")
2914 (define_insn "*iorsi3_two_hi"
2915 [(set (match_operand:SI 0 "register_operand" "=r")
2916 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
2917 (ashift:SI (match_operand:SI 2 "register_operand" "r")
2919 "TARGET_H8300H || TARGET_H8300S"
2921 [(set_attr "cc" "clobber")
2922 (set_attr "length" "2")])
2924 (define_insn_and_split "*iorsi3_two_qi_zext"
2925 [(set (match_operand:SI 0 "register_operand" "=&r")
2926 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
2928 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
2930 (const_int 65280))))]
2931 "(TARGET_H8300H || TARGET_H8300S)"
2933 "&& reload_completed"
2935 (ior:HI (zero_extend:HI (match_dup 1))
2936 (ashift:HI (subreg:HI (match_dup 2) 0)
2939 (zero_extend:SI (match_dup 3)))]
2940 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2942 (define_insn "*iorsi3_e2f"
2943 [(set (match_operand:SI 0 "register_operand" "=r")
2944 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
2946 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2948 "TARGET_H8300H || TARGET_H8300S"
2950 [(set_attr "length" "2")
2951 (set_attr "cc" "clobber")])
2953 (define_insn_and_split "*iorsi3_two_qi_sext"
2954 [(set (match_operand:SI 0 "register_operand" "=r")
2955 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
2956 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
2958 "(TARGET_H8300H || TARGET_H8300S)"
2960 "&& reload_completed"
2962 (ior:HI (zero_extend:HI (match_dup 1))
2963 (ashift:HI (match_dup 4)
2966 (sign_extend:SI (match_dup 3)))]
2967 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
2968 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
2970 (define_insn "*iorsi3_w"
2971 [(set (match_operand:SI 0 "register_operand" "=r,&r")
2972 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
2974 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
2975 "TARGET_H8300H || TARGET_H8300S"
2977 [(set_attr "length" "2,8")
2978 (set_attr "cc" "clobber,clobber")])
2980 (define_insn "*iorsi3_ashift_31"
2981 [(set (match_operand:SI 0 "register_operand" "=&r")
2982 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2984 (match_operand:SI 2 "register_operand" "0")))]
2985 "TARGET_H8300H || TARGET_H8300S"
2986 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
2987 [(set_attr "length" "6")
2988 (set_attr "cc" "set_znv")])
2990 (define_insn "*iorsi3_and_lshiftrt_n_sb"
2991 [(set (match_operand:SI 0 "register_operand" "=r")
2992 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2995 (match_operand:SI 2 "register_operand" "0")))]
2996 "(TARGET_H8300H || TARGET_H8300S)"
2997 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
2998 [(set_attr "length" "8")
2999 (set_attr "cc" "clobber")])
3001 (define_insn "*iorsi3_and_lshiftrt_9_sb"
3002 [(set (match_operand:SI 0 "register_operand" "=r")
3003 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3005 (const_int 4194304))
3006 (match_operand:SI 2 "register_operand" "0")))
3007 (clobber (match_scratch:HI 3 "=&r"))]
3008 "(TARGET_H8300H || TARGET_H8300S)"
3011 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3012 return \"shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3014 return \"rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3016 [(set_attr "length" "10")
3017 (set_attr "cc" "clobber")])
3019 ;; Used to OR the exponent of a float.
3021 (define_insn "*iorsi3_shift"
3022 [(set (match_operand:SI 0 "register_operand" "=r")
3023 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3025 (match_operand:SI 2 "register_operand" "0")))
3026 (clobber (match_scratch:SI 3 "=&r"))]
3027 "TARGET_H8300H || TARGET_H8300S"
3032 [(set (match_operand:SI 0 "register_operand" "")
3033 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3036 (clobber (match_operand:SI 2 "register_operand" ""))])]
3037 "(TARGET_H8300H || TARGET_H8300S)
3039 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3040 && REGNO (operands[0]) != REGNO (operands[1])"
3041 [(parallel [(set (match_dup 3)
3042 (ashift:HI (match_dup 3)
3044 (clobber (scratch:QI))])
3046 (ior:SI (ashift:SI (match_dup 1)
3049 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3053 [(set (match_operand:SI 0 "register_operand" "")
3054 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3057 (clobber (match_operand:SI 2 "register_operand" ""))])]
3058 "(TARGET_H8300H || TARGET_H8300S)
3060 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3061 && REGNO (operands[0]) != REGNO (operands[1]))"
3064 (parallel [(set (match_dup 3)
3065 (ashift:HI (match_dup 3)
3067 (clobber (scratch:QI))])
3069 (ior:SI (ashift:SI (match_dup 2)
3072 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3074 (define_insn "*iorsi2_and_1_lshiftrt_1"
3075 [(set (match_operand:SI 0 "register_operand" "=r")
3076 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3078 (lshiftrt:SI (match_dup 1)
3080 "TARGET_H8300H || TARGET_H8300S"
3081 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
3082 [(set_attr "length" "6")
3083 (set_attr "cc" "clobber")])
3085 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
3086 [(set (match_operand:SI 0 "register_operand" "=r")
3087 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3089 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3091 "(TARGET_H8300H || TARGET_H8300S)"
3093 "&& reload_completed"
3095 (ior:HI (ashift:HI (match_dup 4)
3098 (parallel [(set (match_dup 0)
3099 (ashift:SI (match_dup 0)
3101 (clobber (scratch:QI))])]
3102 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3103 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3105 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
3106 [(set (match_operand:SI 0 "register_operand" "=&r")
3107 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
3109 (const_int 16711680))
3110 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3112 "(TARGET_H8300H || TARGET_H8300S)"
3114 "&& reload_completed"
3116 (ior:HI (zero_extend:HI (match_dup 1))
3117 (ashift:HI (subreg:HI (match_dup 2) 0)
3119 (parallel [(set (match_dup 0)
3120 (ashift:SI (match_dup 0)
3122 (clobber (scratch:QI))])]
3123 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3125 ;; Used to add the exponent of a float.
3127 (define_insn "*addsi3_shift"
3128 [(set (match_operand:SI 0 "register_operand" "=r")
3129 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3130 (const_int 8388608))
3131 (match_operand:SI 2 "register_operand" "0")))
3132 (clobber (match_scratch:SI 3 "=&r"))]
3133 "TARGET_H8300H || TARGET_H8300S"
3138 [(set (match_operand:SI 0 "register_operand" "")
3139 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3140 (const_int 8388608))
3142 (clobber (match_operand:SI 2 "register_operand" ""))])]
3143 "(TARGET_H8300H || TARGET_H8300S)
3145 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3146 && REGNO (operands[0]) != REGNO (operands[1])"
3147 [(parallel [(set (match_dup 3)
3148 (ashift:HI (match_dup 3)
3150 (clobber (scratch:QI))])
3152 (plus:SI (mult:SI (match_dup 1)
3155 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3159 [(set (match_operand:SI 0 "register_operand" "")
3160 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3161 (const_int 8388608))
3163 (clobber (match_operand:SI 2 "register_operand" ""))])]
3164 "(TARGET_H8300H || TARGET_H8300S)
3166 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3167 && REGNO (operands[0]) != REGNO (operands[1]))"
3170 (parallel [(set (match_dup 3)
3171 (ashift:HI (match_dup 3)
3173 (clobber (scratch:QI))])
3175 (plus:SI (mult:SI (match_dup 2)
3178 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3182 (define_insn_and_split "*ashiftsi_sextqi_7"
3183 [(set (match_operand:SI 0 "register_operand" "=r")
3184 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
3186 "(TARGET_H8300H || TARGET_H8300S)"
3188 "&& reload_completed"
3189 [(parallel [(set (match_dup 2)
3190 (ashift:HI (match_dup 2)
3192 (clobber (scratch:QI))])
3194 (sign_extend:SI (match_dup 2)))
3195 (parallel [(set (match_dup 0)
3196 (ashiftrt:SI (match_dup 0)
3198 (clobber (scratch:QI))])]
3199 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3201 ;; Storing a part of HImode to QImode.
3204 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3205 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3209 [(set_attr "cc" "set_znv")
3210 (set_attr "length" "8")])
3212 ;; Storing a part of SImode to QImode.
3215 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3216 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3220 [(set_attr "cc" "set_znv")
3221 (set_attr "length" "8")])
3224 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3225 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3227 (clobber (match_scratch:SI 2 "=&r"))]
3228 "TARGET_H8300H || TARGET_H8300S"
3229 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
3230 [(set_attr "cc" "set_znv")
3231 (set_attr "length" "10")])
3234 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3235 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3237 (clobber (match_scratch:SI 2 "=&r"))]
3238 "TARGET_H8300H || TARGET_H8300S"
3239 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
3240 [(set_attr "cc" "set_znv")
3241 (set_attr "length" "10")])
3243 (define_insn_and_split ""
3245 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3249 (label_ref (match_operand 1 "" ""))
3257 (if_then_else (ge (cc0)
3259 (label_ref (match_dup 1))
3263 (define_insn_and_split ""
3265 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3269 (label_ref (match_operand 1 "" ""))
3277 (if_then_else (lt (cc0)
3279 (label_ref (match_dup 1))
3283 ;; -----------------------------------------------------------------
3284 ;; PEEPHOLE PATTERNS
3285 ;; -----------------------------------------------------------------
3287 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3291 [(set (match_operand:HI 0 "register_operand" "")
3292 (lshiftrt:HI (match_dup 0)
3293 (match_operand:HI 1 "const_int_operand" "")))
3294 (clobber (match_operand:HI 2 "" ""))])
3296 (and:HI (match_dup 0)
3297 (match_operand:HI 3 "const_int_operand" "")))]
3298 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3300 (and:HI (match_dup 0)
3304 (lshiftrt:HI (match_dup 0)
3306 (clobber (match_dup 2))])]
3309 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3313 [(set (match_operand:HI 0 "register_operand" "")
3314 (ashift:HI (match_dup 0)
3315 (match_operand:HI 1 "const_int_operand" "")))
3316 (clobber (match_operand:HI 2 "" ""))])
3318 (and:HI (match_dup 0)
3319 (match_operand:HI 3 "const_int_operand" "")))]
3320 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3322 (and:HI (match_dup 0)
3326 (ashift:HI (match_dup 0)
3328 (clobber (match_dup 2))])]
3331 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3335 [(set (match_operand:SI 0 "register_operand" "")
3336 (lshiftrt:SI (match_dup 0)
3337 (match_operand:SI 1 "const_int_operand" "")))
3338 (clobber (match_operand:SI 2 "" ""))])
3340 (and:SI (match_dup 0)
3341 (match_operand:SI 3 "const_int_operand" "")))]
3342 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3344 (and:SI (match_dup 0)
3348 (lshiftrt:SI (match_dup 0)
3350 (clobber (match_dup 2))])]
3353 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3357 [(set (match_operand:SI 0 "register_operand" "")
3358 (ashift:SI (match_dup 0)
3359 (match_operand:SI 1 "const_int_operand" "")))
3360 (clobber (match_operand:SI 2 "" ""))])
3362 (and:SI (match_dup 0)
3363 (match_operand:SI 3 "const_int_operand" "")))]
3364 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3366 (and:SI (match_dup 0)
3370 (ashift:SI (match_dup 0)
3372 (clobber (match_dup 2))])]
3375 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
3379 [(set (match_operand:SI 0 "register_operand" "")
3380 (lshiftrt:SI (match_dup 0)
3381 (match_operand:SI 1 "const_int_operand" "")))
3382 (clobber (match_operand:SI 2 "" ""))])
3384 (and:SI (match_dup 0)
3385 (match_operand:SI 3 "const_int_operand" "")))]
3386 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
3388 (and:SI (match_dup 0)
3392 (lshiftrt:SI (match_dup 0)
3394 (clobber (match_dup 2))])]
3397 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
3401 [(set (match_operand:SI 0 "register_operand" "")
3402 (ashift:SI (match_dup 0)
3403 (match_operand:SI 1 "const_int_operand" "")))
3404 (clobber (match_operand:SI 2 "" ""))])
3406 (and:SI (match_dup 0)
3407 (match_operand:SI 3 "const_int_operand" "")))]
3408 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
3410 (and:SI (match_dup 0)
3414 (ashift:SI (match_dup 0)
3416 (clobber (match_dup 2))])]
3419 ;; Convert a QImode push into an SImode push so that the
3420 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3423 [(parallel [(set (reg:SI SP_REG)
3424 (plus:SI (reg:SI SP_REG) (const_int -4)))
3425 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
3426 (match_operand:QI 0 "register_operand" ""))])]
3428 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3430 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3432 ;; Convert a HImode push into an SImode push so that the
3433 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3436 [(parallel [(set (reg:SI SP_REG)
3437 (plus:SI (reg:SI SP_REG) (const_int -4)))
3438 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
3439 (match_operand:HI 0 "register_operand" ""))])]
3441 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3443 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3445 ;; Cram four pushes into stm.l.
3448 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3449 (match_operand:SI 0 "register_operand" ""))
3450 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3451 (match_operand:SI 1 "register_operand" ""))
3452 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3453 (match_operand:SI 2 "register_operand" ""))
3454 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3455 (match_operand:SI 3 "register_operand" ""))]
3457 && REGNO (operands[0]) == 0
3458 && REGNO (operands[1]) == 1
3459 && REGNO (operands[2]) == 2
3460 && REGNO (operands[3]) == 3"
3461 [(parallel [(set (reg:SI SP_REG)
3462 (plus:SI (reg:SI SP_REG)
3464 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3466 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3468 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3470 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
3474 ;; Cram three pushes into stm.l.
3477 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3478 (match_operand:SI 0 "register_operand" ""))
3479 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3480 (match_operand:SI 1 "register_operand" ""))
3481 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3482 (match_operand:SI 2 "register_operand" ""))]
3484 && ((REGNO (operands[0]) == 0
3485 && REGNO (operands[1]) == 1
3486 && REGNO (operands[2]) == 2)
3487 || (REGNO (operands[0]) == 4
3488 && REGNO (operands[1]) == 5
3489 && REGNO (operands[2]) == 6))"
3490 [(parallel [(set (reg:SI SP_REG)
3491 (plus:SI (reg:SI SP_REG)
3493 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3495 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3497 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3501 ;; Cram two pushes into stm.l.
3504 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3505 (match_operand:SI 0 "register_operand" ""))
3506 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3507 (match_operand:SI 1 "register_operand" ""))]
3509 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
3510 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
3511 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
3512 [(parallel [(set (reg:SI SP_REG)
3513 (plus:SI (reg:SI SP_REG)
3515 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3517 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3524 ;; add.w r7,r0 (6 bytes)
3529 ;; adds #2,r0 (4 bytes)
3532 [(set (match_operand:HI 0 "register_operand" "")
3533 (match_operand:HI 1 "const_int_operand" ""))
3535 (plus:HI (match_dup 0)
3536 (match_operand:HI 2 "register_operand" "")))]
3537 "REG_P (operands[0]) && REG_P (operands[2])
3538 && REGNO (operands[0]) != REGNO (operands[2])
3539 && (CONST_OK_FOR_J (INTVAL (operands[1]))
3540 || CONST_OK_FOR_L (INTVAL (operands[1]))
3541 || CONST_OK_FOR_N (INTVAL (operands[1])))"
3545 (plus:HI (match_dup 0)
3553 ;; add.l er7,er0 (6 bytes)
3558 ;; adds #4,er0 (4 bytes)
3561 [(set (match_operand:SI 0 "register_operand" "")
3562 (match_operand:SI 1 "const_int_operand" ""))
3564 (plus:SI (match_dup 0)
3565 (match_operand:SI 2 "register_operand" "")))]
3566 "(TARGET_H8300H || TARGET_H8300S)
3567 && REG_P (operands[0]) && REG_P (operands[2])
3568 && REGNO (operands[0]) != REGNO (operands[2])
3569 && (CONST_OK_FOR_L (INTVAL (operands[1]))
3570 || CONST_OK_FOR_N (INTVAL (operands[1])))"
3574 (plus:SI (match_dup 0)
3581 ;; add.l #10,er0 (takes 8 bytes)
3587 ;; add.l er7,er0 (takes 6 bytes)
3590 [(set (match_operand:SI 0 "register_operand" "")
3591 (match_operand:SI 1 "register_operand" ""))
3593 (plus:SI (match_dup 0)
3594 (match_operand:SI 2 "const_int_operand" "")))]
3595 "(TARGET_H8300H || TARGET_H8300S)
3596 && REG_P (operands[0]) && REG_P (operands[1])
3597 && REGNO (operands[0]) != REGNO (operands[1])
3598 && !CONST_OK_FOR_L (INTVAL (operands[2]))
3599 && !CONST_OK_FOR_N (INTVAL (operands[2]))
3600 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
3601 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
3602 || INTVAL (operands[2]) == 0xffff
3603 || INTVAL (operands[2]) == 0xfffe)"
3607 (plus:SI (match_dup 0)
3623 [(set (match_operand:HI 0 "register_operand" "")
3624 (plus:HI (match_dup 0)
3625 (match_operand 1 "incdec_operand" "")))
3629 (if_then_else (match_operator 3 "eqne_operator"
3630 [(cc0) (const_int 0)])
3631 (label_ref (match_operand 2 "" ""))
3633 "TARGET_H8300H || TARGET_H8300S"
3634 [(set (match_operand:HI 0 "register_operand" "")
3635 (unspec:HI [(match_dup 0)
3641 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
3642 (label_ref (match_dup 2))
3646 ;; The SImode version of the previous pattern.
3649 [(set (match_operand:SI 0 "register_operand" "")
3650 (plus:SI (match_dup 0)
3651 (match_operand 1 "incdec_operand" "")))
3655 (if_then_else (match_operator 3 "eqne_operator"
3656 [(cc0) (const_int 0)])
3657 (label_ref (match_operand 2 "" ""))
3659 "TARGET_H8300H || TARGET_H8300S"
3660 [(set (match_operand:SI 0 "register_operand" "")
3661 (unspec:SI [(match_dup 0)
3667 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
3668 (label_ref (match_dup 2))
3673 [(parallel [(set (cc0)
3674 (zero_extract:SI (match_operand:QI 0 "register_operand" "")
3677 (clobber (scratch:QI))])
3679 (if_then_else (match_operator 1 "eqne_operator"
3680 [(cc0) (const_int 0)])
3681 (label_ref (match_operand 2 "" ""))
3683 "(TARGET_H8300H || TARGET_H8300S)"
3687 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
3688 (label_ref (match_dup 2))
3690 "operands[3] = ((GET_CODE (operands[1]) == EQ)
3691 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
3692 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));")
3695 [(set (match_operand:SI 0 "register_operand" "")
3696 (match_operand:SI 1 "general_operand" ""))
3698 (and:SI (match_dup 0)
3700 "(TARGET_H8300H || TARGET_H8300S)
3701 && !reg_overlap_mentioned_p (operands[0], operands[1])
3702 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
3705 (set (strict_low_part (match_dup 2))
3707 "operands[2] = gen_lowpart (QImode, operands[0]);
3708 operands[3] = gen_lowpart (QImode, operands[1]);")
3711 [(set (match_operand:SI 0 "register_operand" "")
3712 (match_operand:SI 1 "memory_operand" ""))
3714 (and:SI (match_dup 0)
3715 (match_operand:SI 2 "const_int_operand" "")))]
3716 "(TARGET_H8300H || TARGET_H8300S)
3717 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))
3718 && (INTVAL (operands[2]) & ~0xffff) == 0
3719 && INTVAL (operands[2]) != 255"
3723 (and:SI (match_dup 0)
3725 "operands[3] = gen_lowpart (HImode, operands[0]);
3726 operands[4] = gen_lowpart (HImode, operands[1]);")
3728 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
3729 ;; the equivalent with shorter sequences. Here is the summary. Cases
3730 ;; are grouped for each define_peephole2.
3732 ;; reg const_int use insn
3733 ;; --------------------------------------------------------
3734 ;; live -2 eq/ne copy and inc.l
3735 ;; live -1 eq/ne copy and inc.l
3736 ;; live 1 eq/ne copy and dec.l
3737 ;; live 2 eq/ne copy and dec.l
3739 ;; dead -2 eq/ne inc.l
3740 ;; dead -1 eq/ne inc.l
3741 ;; dead 1 eq/ne dec.l
3742 ;; dead 2 eq/ne dec.l
3744 ;; dead -131072 eq/ne inc.w and test
3745 ;; dead -65536 eq/ne inc.w and test
3746 ;; dead 65536 eq/ne inc.w and test
3747 ;; dead 131072 eq/ne inc.w and test
3749 ;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
3750 ;; dead 0x0000??00 eq/ne xor.b and test
3751 ;; dead 0x0000ffff eq/ne not.w and test
3753 ;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
3754 ;; dead 0xffff??ff eq/ne xor.b and not.l
3756 ;; dead 1 geu/ltu and.b and test
3757 ;; dead 3 geu/ltu and.b and test
3758 ;; dead 7 geu/ltu and.b and test
3759 ;; dead 15 geu/ltu and.b and test
3760 ;; dead 31 geu/ltu and.b and test
3761 ;; dead 63 geu/ltu and.b and test
3762 ;; dead 127 geu/ltu and.b and test
3763 ;; dead 255 geu/ltu and.b and test
3765 ;; dead 65535 geu/ltu mov.w
3767 ;; For a small constant, it is cheaper to actually do the subtraction
3768 ;; and then test the register.
3772 (compare (match_operand:HI 0 "register_operand" "")
3773 (match_operand:HI 1 "incdec_operand" "")))
3775 (if_then_else (match_operator 3 "eqne_operator"
3776 [(cc0) (const_int 0)])
3777 (label_ref (match_operand 2 "" ""))
3779 "(TARGET_H8300H || TARGET_H8300S)
3780 && peep2_reg_dead_p (1, operands[0])"
3782 (unspec:HI [(match_dup 0)
3788 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
3789 (label_ref (match_dup 2))
3791 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
3793 ;; The SImode version of the previous pattern.
3797 (compare (match_operand:SI 0 "register_operand" "")
3798 (match_operand:SI 1 "incdec_operand" "")))
3800 (if_then_else (match_operator 3 "eqne_operator"
3801 [(cc0) (const_int 0)])
3802 (label_ref (match_operand 2 "" ""))
3804 "(TARGET_H8300H || TARGET_H8300S)
3805 && peep2_reg_dead_p (1, operands[0])"
3807 (unspec:SI [(match_dup 0)
3813 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
3814 (label_ref (match_dup 2))
3816 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
3820 (compare (match_operand:SI 0 "register_operand" "")
3821 (match_operand:SI 1 "const_int_operand" "")))
3823 (if_then_else (match_operator 3 "eqne_operator"
3824 [(cc0) (const_int 0)])
3825 (label_ref (match_operand 2 "" ""))
3827 "(TARGET_H8300H || TARGET_H8300S)
3828 && peep2_reg_dead_p (1, operands[0])
3829 && (INTVAL (operands[1]) == -131072
3830 || INTVAL (operands[1]) == -65536
3831 || INTVAL (operands[1]) == 65536
3832 || INTVAL (operands[1]) == 131072)"
3834 (plus:SI (match_dup 0)
3839 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
3840 (label_ref (match_dup 2))
3842 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
3844 ;; For certain (in)equaltity comparisions against a constant, we can
3845 ;; XOR the register with the constant, and test the register against
3850 (compare (match_operand:SI 0 "register_operand" "")
3851 (match_operand:SI 1 "const_int_operand" "")))
3853 (if_then_else (match_operator 3 "eqne_operator"
3854 [(cc0) (const_int 0)])
3855 (label_ref (match_operand 2 "" ""))
3857 "(TARGET_H8300H || TARGET_H8300S)
3858 && peep2_reg_dead_p (1, operands[0])
3859 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
3860 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
3861 || INTVAL (operands[1]) == 0x0000ffff)
3862 && INTVAL (operands[1]) != 1
3863 && INTVAL (operands[1]) != 2"
3865 (xor:SI (match_dup 0)
3870 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
3871 (label_ref (match_dup 2))
3877 (compare (match_operand:SI 0 "register_operand" "")
3878 (match_operand:SI 1 "const_int_operand" "")))
3880 (if_then_else (match_operator 3 "eqne_operator"
3881 [(cc0) (const_int 0)])
3882 (label_ref (match_operand 2 "" ""))
3884 "(TARGET_H8300H || TARGET_H8300S)
3885 && peep2_reg_dead_p (1, operands[0])
3886 && ((INTVAL (operands[1]) | 0x00ff) == -1
3887 || (INTVAL (operands[1]) | 0xff00) == -1)
3888 && INTVAL (operands[1]) != -1
3889 && INTVAL (operands[1]) != -2"
3891 (xor:SI (match_dup 0)
3894 (not:SI (match_dup 0)))
3898 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
3899 (label_ref (match_dup 2))
3901 "operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);")
3903 ;; Transform A <= 1 to (A & 0xfffffffe) == 0.
3907 (compare (match_operand:SI 0 "register_operand" "")
3908 (match_operand:SI 1 "const_int_operand" "")))
3910 (if_then_else (match_operator 2 "gtuleu_operator"
3911 [(cc0) (const_int 0)])
3912 (label_ref (match_operand 3 "" ""))
3914 "(TARGET_H8300H || TARGET_H8300S)
3915 && peep2_reg_dead_p (1, operands[0])
3916 && (INTVAL (operands[1]) == 1
3917 || INTVAL (operands[1]) == 3
3918 || INTVAL (operands[1]) == 7
3919 || INTVAL (operands[1]) == 15
3920 || INTVAL (operands[1]) == 31
3921 || INTVAL (operands[1]) == 63
3922 || INTVAL (operands[1]) == 127
3923 || INTVAL (operands[1]) == 255)"
3925 (and:SI (match_dup 0)
3930 (if_then_else (match_dup 4)
3931 (label_ref (match_dup 3))
3933 "operands[4] = ((GET_CODE (operands[2]) == GTU) ?
3934 gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx) :
3935 gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx));
3936 operands[5] = GEN_INT (~INTVAL (operands[1]));")
3938 ;; Transform A <= 255 to (A & 0xff00) == 0.
3942 (compare (match_operand:HI 0 "register_operand" "")
3945 (if_then_else (match_operator 1 "gtuleu_operator"
3946 [(cc0) (const_int 0)])
3947 (label_ref (match_operand 2 "" ""))
3949 "TARGET_H8300H || TARGET_H8300S"
3951 (and:HI (match_dup 0)
3954 (if_then_else (match_dup 4)
3955 (label_ref (match_dup 2))
3957 "operands[4] = ((GET_CODE (operands[1]) == GTU) ?
3958 gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx) :
3959 gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx));")
3961 ;; Transform A <= 65535 to (A & 0xffff0000) == 0.
3965 (compare (match_operand:SI 0 "register_operand" "")
3968 (if_then_else (match_operator 1 "gtuleu_operator"
3969 [(cc0) (const_int 0)])
3970 (label_ref (match_operand 2 "" ""))
3972 "TARGET_H8300H || TARGET_H8300S"
3974 (and:SI (match_dup 0)
3975 (const_int -65536)))
3977 (if_then_else (match_dup 4)
3978 (label_ref (match_dup 2))
3980 "operands[4] = ((GET_CODE (operands[1]) == GTU) ?
3981 gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx) :
3982 gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx));")
3984 ;; For constants like -1, -2, 1, 2, it is still cheaper to make a copy
3985 ;; of the register being tested, do the subtraction on the copy, and
3986 ;; then test the copy. We avoid this transformation if we see more
3987 ;; than one copy of the same compare insn.
3990 [(match_scratch:SI 4 "r")
3992 (compare (match_operand:SI 0 "register_operand" "")
3993 (match_operand:SI 1 "incdec_operand" "")))
3995 (if_then_else (match_operator 3 "eqne_operator"
3996 [(cc0) (const_int 0)])
3997 (label_ref (match_operand 2 "" ""))
3999 "(TARGET_H8300H || TARGET_H8300S)
4000 && !peep2_reg_dead_p (1, operands[0])
4001 && !rtx_equal_p (PATTERN (insn),
4002 PATTERN (next_nonnote_insn (next_nonnote_insn (insn))))"
4006 (unspec:SI [(match_dup 4)
4012 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4013 (label_ref (match_dup 2))
4015 "operands[5] = GEN_INT (- INTVAL (operands[1]));")
4017 ;; Narrow the mode of testing if possible.
4020 [(set (match_operand:HI 0 "register_operand" "")
4021 (and:HI (match_dup 0)
4022 (match_operand:HI 1 "const_int_qi_operand" "")))
4026 (if_then_else (match_operator 3 "eqne_operator"
4027 [(cc0) (const_int 0)])
4028 (label_ref (match_operand 2 "" ""))
4030 "peep2_reg_dead_p (2, operands[0])"
4032 (and:QI (match_dup 4)
4037 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4038 (label_ref (match_dup 2))
4040 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
4041 operands[5] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]), QImode));")
4044 [(set (match_operand:SI 0 "register_operand" "")
4045 (and:SI (match_dup 0)
4046 (match_operand:SI 1 "const_int_qi_operand" "")))
4050 (if_then_else (match_operator 3 "eqne_operator"
4051 [(cc0) (const_int 0)])
4052 (label_ref (match_operand 2 "" ""))
4054 "peep2_reg_dead_p (2, operands[0])"
4056 (and:QI (match_dup 4)
4061 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4062 (label_ref (match_dup 2))
4064 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
4065 operands[5] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]), QImode));")
4068 [(set (match_operand:SI 0 "register_operand" "")
4069 (and:SI (match_dup 0)
4070 (match_operand:SI 1 "const_int_hi_operand" "")))
4074 (if_then_else (match_operator 3 "eqne_operator"
4075 [(cc0) (const_int 0)])
4076 (label_ref (match_operand 2 "" ""))
4078 "peep2_reg_dead_p (2, operands[0])"
4080 (and:HI (match_dup 4)
4085 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4086 (label_ref (match_dup 2))
4088 "operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
4089 operands[5] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]), HImode));")
4092 [(set (match_operand:SI 0 "register_operand" "")
4093 (and:SI (match_dup 0)
4094 (match_operand:SI 1 "const_int_qi_operand" "")))
4096 (xor:SI (match_dup 0)
4097 (match_operand:SI 2 "const_int_qi_operand" "")))
4101 (if_then_else (match_operator 4 "eqne_operator"
4102 [(cc0) (const_int 0)])
4103 (label_ref (match_operand 3 "" ""))
4105 "peep2_reg_dead_p (3, operands[0])
4106 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
4108 (and:QI (match_dup 5)
4111 (xor:QI (match_dup 5)
4116 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
4117 (label_ref (match_dup 3))
4119 "operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
4120 operands[6] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]), QImode));
4121 operands[7] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));")