1 ;; GCC machine description for Hitachi H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003 Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;; We compute exact length on each instruction for most of the time.
26 ;; In some case, most notably bit operations that may involve memory
27 ;; operands, the lengths in this file are "worst case".
29 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
30 ;; registers. Right now GCC doesn't expose the "e" half to the
31 ;; compiler, so using add/subs for addhi and subhi is safe. Long
32 ;; term, we want to expose the "e" half to the compiler (gives us 8
33 ;; more 16bit registers). At that point addhi and subhi can't use
36 ;; There's currently no way to have an insv/extzv expander for the H8/300H
37 ;; because word_mode is different for the H8/300 and H8/300H.
39 ;; Shifts/rotates by small constants should be handled by special
40 ;; patterns so we get the length and cc status correct.
42 ;; Bitfield operations no longer accept memory operands. We need
43 ;; to add variants which operate on memory back to the MD.
45 ;; ??? Implement remaining bit ops available on the h8300
47 ;; ----------------------------------------------------------------------
49 ;; ----------------------------------------------------------------------
64 ;; ----------------------------------------------------------------------
66 ;; ----------------------------------------------------------------------
68 (define_attr "cpu" "h8300,h8300h"
69 (const (symbol_ref "cpu_type")))
71 (define_attr "type" "branch,arith"
72 (const_string "arith"))
74 ;; The size of instructions in bytes.
76 (define_attr "length" ""
77 (cond [(eq_attr "type" "branch")
78 (if_then_else (and (ge (minus (match_dup 0) (pc))
80 (le (minus (match_dup 0) (pc))
83 (if_then_else (and (eq_attr "cpu" "h8300h")
84 (and (ge (minus (pc) (match_dup 0))
86 (le (minus (pc) (match_dup 0))
92 ;; Condition code settings.
94 ;; none - insn does not affect cc
95 ;; none_0hit - insn does not affect cc but it does modify operand 0
96 ;; This attribute is used to keep track of when operand 0 changes.
97 ;; See the description of NOTICE_UPDATE_CC for more info.
98 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
99 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
100 ;; compare - compare instruction
101 ;; clobber - value of cc is unknown
103 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
104 (const_string "clobber"))
106 ;; Provide the maximum length of an assembly instruction in an asm
107 ;; statement. The maximum length of 14 bytes is achieved on H8SX.
109 (define_asm_attributes
110 [(set (attr "length")
111 (cond [(ne (symbol_ref "TARGET_H8300") (const_int 0)) (const_int 4)
112 (ne (symbol_ref "TARGET_H8300H") (const_int 0)) (const_int 10)
113 (ne (symbol_ref "TARGET_H8300S") (const_int 0)) (const_int 10)]
116 ;; ----------------------------------------------------------------------
118 ;; ----------------------------------------------------------------------
122 (define_insn "pushqi1_h8300"
123 [(parallel [(set (reg:HI SP_REG)
124 (plus:HI (reg:HI SP_REG) (const_int -2)))
125 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
126 (match_operand:QI 0 "register_operand" "r"))])]
128 && operands[0] != stack_pointer_rtx"
130 [(set_attr "length" "2")
131 (set_attr "cc" "clobber")])
133 (define_insn "pushqi1_h8300hs"
134 [(parallel [(set (reg:SI SP_REG)
135 (plus:SI (reg:SI SP_REG) (const_int -4)))
136 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
137 (match_operand:QI 0 "register_operand" "r"))])]
138 "(TARGET_H8300H || TARGET_H8300S)
139 && operands[0] != stack_pointer_rtx"
141 [(set_attr "length" "4")
142 (set_attr "cc" "clobber")])
144 (define_insn "pushqi1_h8300hs_normal"
145 [(parallel [(set (reg:HI SP_REG)
146 (plus:HI (reg:HI SP_REG) (const_int -4)))
147 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
148 (match_operand:QI 0 "register_operand" "r"))])]
149 "(TARGET_H8300H || TARGET_H8300S)
150 && operands[0] != stack_pointer_rtx"
152 [(set_attr "length" "4")
153 (set_attr "cc" "clobber")])
155 (define_expand "pushqi1"
156 [(use (match_operand:QI 0 "register_operand" ""))]
161 emit_insn (gen_pushqi1_h8300 (operands[0]));
162 else if (!TARGET_NORMAL_MODE)
163 emit_insn (gen_pushqi1_h8300hs (operands[0]));
165 emit_insn (gen_pushqi1_h8300hs_normal (operands[0]));
169 (define_insn "*movqi_h8300"
170 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
171 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
173 && (register_operand (operands[0], QImode)
174 || register_operand (operands[1], QImode))"
182 [(set_attr "length" "2,2,2,2,4,4")
183 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
185 (define_insn "*movqi_h8300hs"
186 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
187 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
188 "(TARGET_H8300H || TARGET_H8300S)
189 && (register_operand (operands[0], QImode)
190 || register_operand (operands[1], QImode))"
198 [(set (attr "length")
199 (symbol_ref "compute_mov_length (operands)"))
200 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
202 (define_expand "movqi"
203 [(set (match_operand:QI 0 "general_operand_dst" "")
204 (match_operand:QI 1 "general_operand_src" ""))]
208 /* One of the ops has to be in a register. */
209 if (!register_operand (operand0, QImode)
210 && !register_operand (operand1, QImode))
212 operands[1] = copy_to_mode_reg (QImode, operand1);
216 (define_insn "movstrictqi"
217 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r,r,r"))
218 (match_operand:QI 1 "general_operand_src" "I,r,n,m"))]
225 [(set (attr "length")
226 (symbol_ref "compute_mov_length (operands)"))
227 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
231 (define_expand "pushhi1_h8300"
232 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
233 (match_operand:HI 0 "register_operand" ""))]
235 && operands[0] != stack_pointer_rtx"
238 (define_insn "pushhi1_h8300hs"
239 [(parallel [(set (reg:SI SP_REG)
240 (plus:SI (reg:SI SP_REG) (const_int -4)))
241 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
242 (match_operand:HI 0 "register_operand" "r"))])]
243 "(TARGET_H8300H || TARGET_H8300S)
244 && operands[0] != stack_pointer_rtx"
246 [(set_attr "length" "4")
247 (set_attr "cc" "clobber")])
249 (define_insn "pushhi1_h8300hs_normal"
250 [(parallel [(set (reg:HI SP_REG)
251 (plus:HI (reg:HI SP_REG) (const_int -4)))
252 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
253 (match_operand:HI 0 "register_operand" "r"))])]
254 "(TARGET_H8300H || TARGET_H8300S)
255 && operands[0] != stack_pointer_rtx"
257 [(set_attr "length" "4")
258 (set_attr "cc" "clobber")])
260 (define_expand "pushhi1"
261 [(use (match_operand:HI 0 "register_operand" ""))]
266 emit_insn (gen_pushhi1_h8300 (operands[0]));
267 else if (!TARGET_NORMAL_MODE)
268 emit_insn (gen_pushhi1_h8300hs (operands[0]));
270 emit_insn (gen_pushhi1_h8300hs_normal (operands[0]));
274 (define_insn "*movhi_h8300"
275 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
276 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
278 && (register_operand (operands[0], HImode)
279 || register_operand (operands[1], HImode))
280 && !(GET_CODE (operands[0]) == MEM
281 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
282 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
283 && GET_CODE (operands[1]) == REG
284 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
292 [(set (attr "length")
293 (symbol_ref "compute_mov_length (operands)"))
294 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
296 (define_insn "*movhi_h8300hs"
297 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
298 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
299 "(TARGET_H8300H || TARGET_H8300S)
300 && (register_operand (operands[0], HImode)
301 || register_operand (operands[1], HImode))"
309 [(set (attr "length")
310 (symbol_ref "compute_mov_length (operands)"))
311 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
313 (define_expand "movhi"
314 [(set (match_operand:HI 0 "general_operand_dst" "")
315 (match_operand:HI 1 "general_operand_src" ""))]
319 /* One of the ops has to be in a register. */
320 if (!register_operand (operand1, HImode)
321 && !register_operand (operand0, HImode))
323 operands[1] = copy_to_mode_reg (HImode, operand1);
327 (define_insn "movstricthi"
328 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r,r"))
329 (match_operand:HI 1 "general_operand_src" "I,r,i,m"))]
336 [(set (attr "length")
337 (symbol_ref "compute_mov_length (operands)"))
338 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
342 (define_expand "movsi"
343 [(set (match_operand:SI 0 "general_operand_dst" "")
344 (match_operand:SI 1 "general_operand_src" ""))]
350 if (do_movsi (operands))
355 /* One of the ops has to be in a register. */
356 if (!register_operand (operand1, SImode)
357 && !register_operand (operand0, SImode))
359 operands[1] = copy_to_mode_reg (SImode, operand1);
364 (define_expand "movsf"
365 [(set (match_operand:SF 0 "general_operand_dst" "")
366 (match_operand:SF 1 "general_operand_src" ""))]
372 if (do_movsi (operands))
377 /* One of the ops has to be in a register. */
378 if (!register_operand (operand1, SFmode)
379 && !register_operand (operand0, SFmode))
381 operands[1] = copy_to_mode_reg (SFmode, operand1);
386 (define_insn "*movsi_h8300"
387 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
388 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
390 && (register_operand (operands[0], SImode)
391 || register_operand (operands[1], SImode))"
394 unsigned int rn = -1;
395 switch (which_alternative)
398 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
400 if (REGNO (operands[0]) < REGNO (operands[1]))
401 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
403 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
405 /* Make sure we don't trample the register we index with. */
406 if (GET_CODE (operands[1]) == MEM)
408 rtx inside = XEXP (operands[1], 0);
413 else if (GET_CODE (inside) == PLUS)
415 rtx lhs = XEXP (inside, 0);
416 rtx rhs = XEXP (inside, 1);
417 if (REG_P (lhs)) rn = REGNO (lhs);
418 if (REG_P (rhs)) rn = REGNO (rhs);
421 if (rn == REGNO (operands[0]))
423 /* Move the second word first. */
424 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
428 if (GET_CODE (operands[1]) == CONST_INT)
430 /* If either half is zero, use sub.w to clear that
432 if ((INTVAL (operands[1]) & 0xffff) == 0)
433 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
434 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
435 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
436 /* If the upper half and the lower half are the same,
437 copy one half to the other. */
438 if ((INTVAL (operands[1]) & 0xffff)
439 == ((INTVAL (operands[1]) >> 16) & 0xffff))
440 return \"mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0\";
442 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
445 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
447 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
449 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
454 [(set (attr "length")
455 (symbol_ref "compute_mov_length (operands)"))
456 (set_attr "cc" "clobber")])
458 (define_insn "*movsf_h8300"
459 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
460 (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))]
462 && (register_operand (operands[0], SFmode)
463 || register_operand (operands[1], SFmode))"
466 /* Copy of the movsi stuff. */
467 unsigned int rn = -1;
468 switch (which_alternative)
471 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
473 if (REGNO (operands[0]) < REGNO (operands[1]))
474 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
476 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
478 /* Make sure we don't trample the register we index with. */
479 if (GET_CODE (operands[1]) == MEM)
481 rtx inside = XEXP (operands[1], 0);
486 else if (GET_CODE (inside) == PLUS)
488 rtx lhs = XEXP (inside, 0);
489 rtx rhs = XEXP (inside, 1);
490 if (REG_P (lhs)) rn = REGNO (lhs);
491 if (REG_P (rhs)) rn = REGNO (rhs);
494 if (rn == REGNO (operands[0]))
495 /* Move the second word first. */
496 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
498 /* Move the first word first. */
499 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
502 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
504 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
506 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
511 [(set (attr "length")
512 (symbol_ref "compute_mov_length (operands)"))
513 (set_attr "cc" "clobber")])
515 (define_insn "*movsi_h8300hs"
516 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
517 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
518 "(TARGET_H8300S || TARGET_H8300H)
519 && (register_operand (operands[0], SImode)
520 || register_operand (operands[1], SImode))
521 && !(GET_CODE (operands[0]) == MEM
522 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
523 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
524 && GET_CODE (operands[1]) == REG
525 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
528 switch (which_alternative)
531 return \"sub.l %S0,%S0\";
535 return \"clrmac\;ldmac %1,macl\";
537 return \"stmac macl,%0\";
539 if (GET_CODE (operands[1]) == CONST_INT)
541 int val = INTVAL (operands[1]);
543 /* Look for constants which can be made by adding an 8-bit
544 number to zero in one of the two low bytes. */
545 if (val == (val & 0xff))
547 operands[1] = GEN_INT ((char) val & 0xff);
548 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
551 if (val == (val & 0xff00))
553 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
554 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
557 /* Look for constants that can be obtained by subs, inc, and
559 switch (val & 0xffffffff)
562 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
564 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
566 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
569 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
571 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
574 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
576 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
579 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
581 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
585 return \"mov.l %S1,%S0\";
587 [(set (attr "length")
588 (symbol_ref "compute_mov_length (operands)"))
589 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
591 (define_insn "*movsf_h8300hs"
592 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
593 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
594 "(TARGET_H8300H || TARGET_H8300S)
595 && (register_operand (operands[0], SFmode)
596 || register_operand (operands[1], SFmode))"
604 [(set (attr "length")
605 (symbol_ref "compute_mov_length (operands)"))
606 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
608 ;; ----------------------------------------------------------------------
610 ;; ----------------------------------------------------------------------
613 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
615 (match_operand 1 "const_int_operand" "n,n")))]
618 [(set_attr "length" "2,4")
619 (set_attr "cc" "set_zn,set_zn")])
622 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
624 (match_operand 1 "const_int_operand" "n")))]
627 [(set_attr "length" "2")
628 (set_attr "cc" "set_zn")])
630 (define_insn_and_split "*tst_extzv_1_n"
632 (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
634 (match_operand 1 "const_int_operand" "n,n,n")))
635 (clobber (match_scratch:QI 2 "=X,X,&r"))]
636 "(TARGET_H8300H || TARGET_H8300S)"
642 && !EXTRA_CONSTRAINT (operands[0], 'U')"
645 (parallel [(set (cc0) (zero_extract:SI (match_dup 2)
648 (clobber (scratch:QI))])]
650 [(set_attr "length" "2,8,10")
651 (set_attr "cc" "set_zn,set_zn,set_zn")])
654 [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
656 (match_operand 1 "const_int_operand" "n")))]
657 "(TARGET_H8300H || TARGET_H8300S)
658 && INTVAL (operands[1]) <= 15"
660 [(set_attr "length" "2")
661 (set_attr "cc" "set_zn")])
663 (define_insn_and_split "*tstsi_upper_bit"
665 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
667 (match_operand 1 "const_int_operand" "n")))
668 (clobber (match_scratch:SI 2 "=&r"))]
669 "(TARGET_H8300H || TARGET_H8300S)
670 && INTVAL (operands[1]) >= 16"
672 "&& reload_completed"
674 (ior:SI (and:SI (match_dup 2)
676 (lshiftrt:SI (match_dup 0)
679 (zero_extract:SI (match_dup 2)
682 "operands[3] = GEN_INT (INTVAL (operands[1]) - 16);")
684 (define_insn "*tstsi_variable_bit"
686 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
688 (and:SI (match_operand:SI 1 "register_operand" "r")
690 "TARGET_H8300H || TARGET_H8300S"
692 [(set_attr "length" "2")
693 (set_attr "cc" "set_zn")])
695 (define_insn_and_split "*tstsi_variable_bit_qi"
697 (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>"))
699 (and:SI (match_operand:SI 1 "register_operand" "r,r,r")
701 (clobber (match_scratch:QI 2 "=X,X,&r"))]
702 "(TARGET_H8300H || TARGET_H8300S)"
708 && !EXTRA_CONSTRAINT (operands[0], 'U')"
711 (parallel [(set (cc0) (zero_extract:SI (zero_extend:SI (match_dup 2))
713 (and:SI (match_dup 1)
715 (clobber (scratch:QI))])]
717 [(set_attr "length" "2,8,10")
718 (set_attr "cc" "set_zn,set_zn,set_zn")])
721 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
724 [(set_attr "length" "2")
725 (set_attr "cc" "set_znv")])
728 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
731 [(set_attr "length" "2")
732 (set_attr "cc" "set_znv")])
734 (define_insn "*tsthi_upper"
736 (and:HI (match_operand:HI 0 "register_operand" "r")
740 [(set_attr "length" "2")
741 (set_attr "cc" "set_znv")])
744 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
745 "TARGET_H8300H || TARGET_H8300S"
747 [(set_attr "length" "2")
748 (set_attr "cc" "set_znv")])
750 (define_insn "*tstsi_upper"
752 (and:SI (match_operand:SI 0 "register_operand" "r")
753 (const_int -65536)))]
756 [(set_attr "length" "2")
757 (set_attr "cc" "set_znv")])
761 (compare (match_operand:QI 0 "register_operand" "r")
762 (match_operand:QI 1 "nonmemory_operand" "rn")))]
765 [(set_attr "length" "2")
766 (set_attr "cc" "compare")])
768 (define_expand "cmphi"
770 (compare (match_operand:HI 0 "register_operand" "")
771 (match_operand:HI 1 "nonmemory_operand" "")))]
775 /* Force operand1 into a register if we're compiling
777 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
778 operands[1] = force_reg (HImode, operands[1]);
781 (define_insn "*cmphi_h8300"
783 (compare (match_operand:HI 0 "register_operand" "r")
784 (match_operand:HI 1 "register_operand" "r")))]
787 [(set_attr "length" "2")
788 (set_attr "cc" "compare")])
790 (define_insn "*cmphi_h8300hs"
792 (compare (match_operand:HI 0 "register_operand" "r,r")
793 (match_operand:HI 1 "nonmemory_operand" "r,n")))]
794 "TARGET_H8300H || TARGET_H8300S"
796 [(set_attr "length" "2,4")
797 (set_attr "cc" "compare,compare")])
801 (compare (match_operand:SI 0 "register_operand" "r,r")
802 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
803 "TARGET_H8300H || TARGET_H8300S"
805 [(set_attr "length" "2,6")
806 (set_attr "cc" "compare,compare")])
808 ;; ----------------------------------------------------------------------
810 ;; ----------------------------------------------------------------------
812 (define_insn "addqi3"
813 [(set (match_operand:QI 0 "register_operand" "=r")
814 (plus:QI (match_operand:QI 1 "register_operand" "%0")
815 (match_operand:QI 2 "nonmemory_operand" "rn")))]
818 [(set_attr "length" "2")
819 (set_attr "cc" "set_zn")])
821 (define_expand "addhi3"
822 [(set (match_operand:HI 0 "register_operand" "")
823 (plus:HI (match_operand:HI 1 "register_operand" "")
824 (match_operand:HI 2 "nonmemory_operand" "")))]
828 (define_insn "*addhi3_h8300"
829 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
830 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
831 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
837 add.b %s2,%s0\;addx %t2,%t0
839 [(set_attr "length" "2,2,2,4,2")
840 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
842 ;; This splitter is very important to make the stack adjustment
843 ;; interrupt-safe. The combination of add.b and addx is unsafe!
845 ;; We apply this split after the peephole2 pass so that we won't end
846 ;; up creating too many adds/subs when a scratch register is
847 ;; available, which is actually a common case because stack unrolling
848 ;; tends to happen immediately after a function call.
851 [(set (match_operand:HI 0 "stack_pointer_operand" "")
852 (plus:HI (match_dup 0)
853 (match_operand 1 "const_int_gt_2_operand" "")))]
854 "TARGET_H8300 && flow2_completed"
856 "split_adds_subs (HImode, operands); DONE;")
859 [(match_scratch:HI 2 "r")
860 (set (match_operand:HI 0 "stack_pointer_operand" "")
861 (plus:HI (match_dup 0)
862 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
867 (plus:HI (match_dup 0)
871 (define_insn "*addhi3_h8300hs"
872 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
873 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
874 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
875 "TARGET_H8300H || TARGET_H8300S"
882 [(set_attr "length" "2,2,2,4,2")
883 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
885 (define_insn "*addhi3_incdec"
886 [(set (match_operand:HI 0 "register_operand" "=r,r")
887 (unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
888 (match_operand:HI 2 "incdec_operand" "M,O")]
890 "TARGET_H8300H || TARGET_H8300S"
894 [(set_attr "length" "2,2")
895 (set_attr "cc" "set_zn,set_zn")])
898 [(set (match_operand:HI 0 "register_operand" "")
899 (plus:HI (match_dup 0)
900 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
903 "split_adds_subs (HImode, operands); DONE;")
905 (define_expand "addsi3"
906 [(set (match_operand:SI 0 "register_operand" "")
907 (plus:SI (match_operand:SI 1 "register_operand" "")
908 (match_operand:SI 2 "nonmemory_operand" "")))]
912 (define_insn "*addsi_h8300"
913 [(set (match_operand:SI 0 "register_operand" "=r,r")
914 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
915 (match_operand:SI 2 "nonmemory_operand" "n,r")))]
917 "* return output_plussi (operands);"
918 [(set (attr "length")
919 (symbol_ref "compute_plussi_length (operands)"))
921 (symbol_ref "compute_plussi_cc (operands)"))])
923 (define_insn "*addsi_h8300hs"
924 [(set (match_operand:SI 0 "register_operand" "=r,r")
925 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
926 (match_operand:SI 2 "nonmemory_operand" "i,r")))]
927 "TARGET_H8300H || TARGET_H8300S"
928 "* return output_plussi (operands);"
929 [(set (attr "length")
930 (symbol_ref "compute_plussi_length (operands)"))
932 (symbol_ref "compute_plussi_cc (operands)"))])
934 (define_insn "*addsi3_incdec"
935 [(set (match_operand:SI 0 "register_operand" "=r,r")
936 (unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
937 (match_operand:SI 2 "incdec_operand" "M,O")]
939 "TARGET_H8300H || TARGET_H8300S"
943 [(set_attr "length" "2,2")
944 (set_attr "cc" "set_zn,set_zn")])
947 [(set (match_operand:SI 0 "register_operand" "")
948 (plus:SI (match_dup 0)
949 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
950 "TARGET_H8300H || TARGET_H8300S"
952 "split_adds_subs (SImode, operands); DONE;")
954 ;; ----------------------------------------------------------------------
955 ;; SUBTRACT INSTRUCTIONS
956 ;; ----------------------------------------------------------------------
958 (define_insn "subqi3"
959 [(set (match_operand:QI 0 "register_operand" "=r")
960 (minus:QI (match_operand:QI 1 "register_operand" "0")
961 (match_operand:QI 2 "register_operand" "r")))]
964 [(set_attr "length" "2")
965 (set_attr "cc" "set_zn")])
967 (define_expand "subhi3"
968 [(set (match_operand:HI 0 "register_operand" "")
969 (minus:HI (match_operand:HI 1 "general_operand" "")
970 (match_operand:HI 2 "nonmemory_operand" "")))]
974 (define_insn "*subhi3_h8300"
975 [(set (match_operand:HI 0 "register_operand" "=r,r")
976 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
977 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
981 add.b %E2,%s0\;addx %F2,%t0"
982 [(set_attr "length" "2,4")
983 (set_attr "cc" "set_zn,clobber")])
985 (define_insn "*subhi3_h8300hs"
986 [(set (match_operand:HI 0 "register_operand" "=r,r")
987 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
988 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
989 "TARGET_H8300H || TARGET_H8300S"
993 [(set_attr "length" "2,4")
994 (set_attr "cc" "set_zn,set_zn")])
996 (define_expand "subsi3"
997 [(set (match_operand:SI 0 "register_operand" "")
998 (minus:SI (match_operand:SI 1 "register_operand" "")
999 (match_operand:SI 2 "nonmemory_operand" "")))]
1003 (define_insn "*subsi3_h8300"
1004 [(set (match_operand:SI 0 "register_operand" "=r")
1005 (minus:SI (match_operand:SI 1 "register_operand" "0")
1006 (match_operand:SI 2 "register_operand" "r")))]
1008 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
1009 [(set_attr "length" "6")
1010 (set_attr "cc" "clobber")])
1012 (define_insn "*subsi3_h8300hs"
1013 [(set (match_operand:SI 0 "register_operand" "=r,r")
1014 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
1015 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
1016 "TARGET_H8300H || TARGET_H8300S"
1020 [(set_attr "length" "2,6")
1021 (set_attr "cc" "set_zn,set_zn")])
1023 ;; ----------------------------------------------------------------------
1024 ;; MULTIPLY INSTRUCTIONS
1025 ;; ----------------------------------------------------------------------
1027 ;; Note that the H8/300 can only handle umulqihi3.
1029 (define_insn "mulqihi3"
1030 [(set (match_operand:HI 0 "register_operand" "=r")
1031 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1032 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1033 "TARGET_H8300H || TARGET_H8300S"
1035 [(set_attr "length" "4")
1036 (set_attr "cc" "set_zn")])
1038 (define_insn "mulhisi3"
1039 [(set (match_operand:SI 0 "register_operand" "=r")
1040 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1041 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1042 "TARGET_H8300H || TARGET_H8300S"
1044 [(set_attr "length" "4")
1045 (set_attr "cc" "set_zn")])
1047 (define_insn "umulqihi3"
1048 [(set (match_operand:HI 0 "register_operand" "=r")
1049 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1050 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1053 [(set_attr "length" "2")
1054 (set_attr "cc" "none_0hit")])
1056 (define_insn "umulhisi3"
1057 [(set (match_operand:SI 0 "register_operand" "=r")
1058 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1059 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1060 "TARGET_H8300H || TARGET_H8300S"
1062 [(set_attr "length" "2")
1063 (set_attr "cc" "none_0hit")])
1065 ;; This is a "bridge" instruction. Combine can't cram enough insns
1066 ;; together to crate a MAC instruction directly, but it can create
1067 ;; this instruction, which then allows combine to create the real
1070 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1071 ;; insn must generate reasonably correct code. Egad.
1073 [(set (match_operand:SI 0 "register_operand" "=a")
1076 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1078 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
1080 "clrmac\;mac @%2+,@%1+"
1081 [(set_attr "length" "6")
1082 (set_attr "cc" "none_0hit")])
1085 [(set (match_operand:SI 0 "register_operand" "=a")
1087 (sign_extend:SI (mem:HI
1088 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1089 (sign_extend:SI (mem:HI
1090 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1091 (match_operand:SI 3 "register_operand" "0")))]
1094 [(set_attr "length" "4")
1095 (set_attr "cc" "none_0hit")])
1097 ;; ----------------------------------------------------------------------
1098 ;; DIVIDE/MOD INSTRUCTIONS
1099 ;; ----------------------------------------------------------------------
1101 (define_insn "udivmodqi4"
1102 [(set (match_operand:QI 0 "register_operand" "=r")
1105 (match_operand:HI 1 "register_operand" "0")
1106 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1107 (set (match_operand:QI 3 "register_operand" "=r")
1111 (zero_extend:HI (match_dup 2)))))]
1115 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1116 return \"divxu.b\\t%X2,%T0\";
1118 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1120 [(set_attr "length" "4")
1121 (set_attr "cc" "clobber")])
1123 (define_insn "divmodqi4"
1124 [(set (match_operand:QI 0 "register_operand" "=r")
1127 (match_operand:HI 1 "register_operand" "0")
1128 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1129 (set (match_operand:QI 3 "register_operand" "=r")
1133 (sign_extend:HI (match_dup 2)))))]
1134 "TARGET_H8300H || TARGET_H8300S"
1137 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1138 return \"divxs.b\\t%X2,%T0\";
1140 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1142 [(set_attr "length" "6")
1143 (set_attr "cc" "clobber")])
1145 (define_insn "udivmodhi4"
1146 [(set (match_operand:HI 0 "register_operand" "=r")
1149 (match_operand:SI 1 "register_operand" "0")
1150 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1151 (set (match_operand:HI 3 "register_operand" "=r")
1155 (zero_extend:SI (match_dup 2)))))]
1156 "TARGET_H8300H || TARGET_H8300S"
1159 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1160 return \"divxu.w\\t%T2,%S0\";
1162 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1164 [(set_attr "length" "4")
1165 (set_attr "cc" "clobber")])
1167 (define_insn "divmodhi4"
1168 [(set (match_operand:HI 0 "register_operand" "=r")
1171 (match_operand:SI 1 "register_operand" "0")
1172 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1173 (set (match_operand:HI 3 "register_operand" "=r")
1177 (sign_extend:SI (match_dup 2)))))]
1178 "TARGET_H8300H || TARGET_H8300S"
1181 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1182 return \"divxs.w\\t%T2,%S0\";
1184 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1186 [(set_attr "length" "6")
1187 (set_attr "cc" "clobber")])
1189 ;; ----------------------------------------------------------------------
1191 ;; ----------------------------------------------------------------------
1193 (define_insn "*andqi3_1"
1194 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1195 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1196 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1197 "register_operand (operands[0], QImode)
1198 || single_zero_operand (operands[2], QImode)"
1202 [(set_attr "length" "2,8")
1203 (set_attr "cc" "set_znv,none_0hit")])
1205 (define_expand "andqi3"
1206 [(set (match_operand:QI 0 "bit_operand" "")
1207 (and:QI (match_operand:QI 1 "bit_operand" "")
1208 (match_operand:QI 2 "nonmemory_operand" "")))]
1212 if (fix_bit_operand (operands, 0, AND))
1216 (define_expand "andhi3"
1217 [(set (match_operand:HI 0 "register_operand" "")
1218 (and:HI (match_operand:HI 1 "register_operand" "")
1219 (match_operand:HI 2 "nonmemory_operand" "")))]
1223 (define_insn "*andorqi3"
1224 [(set (match_operand:QI 0 "register_operand" "=r")
1225 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1226 (match_operand:QI 3 "single_one_operand" "n"))
1227 (match_operand:QI 1 "register_operand" "0")))]
1229 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1230 [(set_attr "length" "6")
1231 (set_attr "cc" "clobber")])
1233 (define_insn "*andorhi3"
1234 [(set (match_operand:HI 0 "register_operand" "=r")
1235 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1236 (match_operand:HI 3 "single_one_operand" "n"))
1237 (match_operand:HI 1 "register_operand" "0")))]
1241 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1242 if (INTVAL (operands[3]) > 128)
1244 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1245 return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\";
1247 return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\";
1249 [(set_attr "length" "6")
1250 (set_attr "cc" "clobber")])
1252 (define_insn "*andorsi3"
1253 [(set (match_operand:SI 0 "register_operand" "=r")
1254 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1255 (match_operand:SI 3 "single_one_operand" "n"))
1256 (match_operand:SI 1 "register_operand" "0")))]
1257 "(INTVAL (operands[3]) & 0xffff) != 0"
1260 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1261 if (INTVAL (operands[3]) > 128)
1263 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1264 return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\";
1266 return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\";
1268 [(set_attr "length" "6")
1269 (set_attr "cc" "clobber")])
1271 (define_insn "*andorsi3_shift_8"
1272 [(set (match_operand:SI 0 "register_operand" "=r")
1273 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1276 (match_operand:SI 1 "register_operand" "0")))]
1279 [(set_attr "length" "2")
1280 (set_attr "cc" "clobber")])
1282 (define_expand "andsi3"
1283 [(set (match_operand:SI 0 "register_operand" "")
1284 (and:SI (match_operand:SI 1 "register_operand" "")
1285 (match_operand:SI 2 "nonmemory_operand" "")))]
1289 ;; ----------------------------------------------------------------------
1291 ;; ----------------------------------------------------------------------
1293 (define_insn "*iorqi3_1"
1294 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1295 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1296 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1297 "register_operand (operands[0], QImode)
1298 || single_one_operand (operands[2], QImode)"
1302 [(set_attr "length" "2,8")
1303 (set_attr "cc" "set_znv,none_0hit")])
1305 (define_expand "iorqi3"
1306 [(set (match_operand:QI 0 "bit_operand" "")
1307 (ior:QI (match_operand:QI 1 "bit_operand" "")
1308 (match_operand:QI 2 "nonmemory_operand" "")))]
1312 if (fix_bit_operand (operands, 1, IOR))
1316 (define_expand "iorhi3"
1317 [(set (match_operand:HI 0 "register_operand" "")
1318 (ior:HI (match_operand:HI 1 "register_operand" "")
1319 (match_operand:HI 2 "nonmemory_operand" "")))]
1323 (define_expand "iorsi3"
1324 [(set (match_operand:SI 0 "register_operand" "")
1325 (ior:SI (match_operand:SI 1 "register_operand" "")
1326 (match_operand:SI 2 "nonmemory_operand" "")))]
1330 ;; ----------------------------------------------------------------------
1332 ;; ----------------------------------------------------------------------
1334 (define_insn "*xorqi3_1"
1335 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1336 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1337 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1338 "register_operand (operands[0], QImode)
1339 || single_one_operand (operands[2], QImode)"
1343 [(set_attr "length" "2,8")
1344 (set_attr "cc" "set_znv,none_0hit")])
1346 (define_expand "xorqi3"
1347 [(set (match_operand:QI 0 "bit_operand" "")
1348 (xor:QI (match_operand:QI 1 "bit_operand" "")
1349 (match_operand:QI 2 "nonmemory_operand" "")))]
1353 if (fix_bit_operand (operands, 1, XOR))
1357 (define_expand "xorhi3"
1358 [(set (match_operand:HI 0 "register_operand" "")
1359 (xor:HI (match_operand:HI 1 "register_operand" "")
1360 (match_operand:HI 2 "nonmemory_operand" "")))]
1364 (define_expand "xorsi3"
1365 [(set (match_operand:SI 0 "register_operand" "")
1366 (xor:SI (match_operand:SI 1 "register_operand" "")
1367 (match_operand:SI 2 "nonmemory_operand" "")))]
1371 ;; ----------------------------------------------------------------------
1372 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1373 ;; ----------------------------------------------------------------------
1375 (define_insn "*logicalhi3"
1376 [(set (match_operand:HI 0 "register_operand" "=r")
1377 (match_operator:HI 3 "bit_operator"
1378 [(match_operand:HI 1 "register_operand" "%0")
1379 (match_operand:HI 2 "nonmemory_operand" "rn")]))]
1381 "* return output_logical_op (HImode, operands);"
1382 [(set (attr "length")
1383 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1385 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1387 (define_insn "*logicalsi3"
1388 [(set (match_operand:SI 0 "register_operand" "=r")
1389 (match_operator:SI 3 "bit_operator"
1390 [(match_operand:SI 1 "register_operand" "%0")
1391 (match_operand:SI 2 "nonmemory_operand" "rn")]))]
1393 "* return output_logical_op (SImode, operands);"
1394 [(set (attr "length")
1395 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1397 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1399 ;; ----------------------------------------------------------------------
1400 ;; NEGATION INSTRUCTIONS
1401 ;; ----------------------------------------------------------------------
1403 (define_insn "negqi2"
1404 [(set (match_operand:QI 0 "register_operand" "=r")
1405 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1408 [(set_attr "length" "2")
1409 (set_attr "cc" "set_zn")])
1411 (define_expand "neghi2"
1412 [(set (match_operand:HI 0 "register_operand" "")
1413 (neg:HI (match_operand:HI 1 "register_operand" "")))]
1419 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1424 (define_expand "neghi2_h8300"
1426 (not:HI (match_operand:HI 1 "register_operand" "")))
1427 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1428 (set (match_operand:HI 0 "register_operand" "")
1431 "operands[2] = gen_reg_rtx (HImode);")
1433 (define_insn "*neghi2_h8300hs"
1434 [(set (match_operand:HI 0 "register_operand" "=r")
1435 (neg:HI (match_operand:HI 1 "register_operand" "0")))]
1436 "TARGET_H8300H || TARGET_H8300S"
1438 [(set_attr "length" "2")
1439 (set_attr "cc" "set_zn")])
1441 (define_expand "negsi2"
1442 [(set (match_operand:SI 0 "register_operand" "")
1443 (neg:SI (match_operand:SI 1 "register_operand" "")))]
1449 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1454 (define_expand "negsi2_h8300"
1456 (not:SI (match_operand:SI 1 "register_operand" "")))
1457 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1458 (set (match_operand:SI 0 "register_operand" "")
1461 "operands[2] = gen_reg_rtx (SImode);")
1463 (define_insn "*negsi2_h8300hs"
1464 [(set (match_operand:SI 0 "register_operand" "=r")
1465 (neg:SI (match_operand:SI 1 "register_operand" "0")))]
1466 "TARGET_H8300H || TARGET_H8300S"
1468 [(set_attr "length" "2")
1469 (set_attr "cc" "set_zn")])
1471 (define_expand "negsf2"
1472 [(set (match_operand:SF 0 "register_operand" "")
1473 (neg:SF (match_operand:SF 1 "register_operand" "")))]
1477 (define_insn "*negsf2_h8300"
1478 [(set (match_operand:SF 0 "register_operand" "=r")
1479 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1482 [(set_attr "cc" "clobber")
1483 (set_attr "length" "2")])
1485 (define_insn "*negsf2_h8300hs"
1486 [(set (match_operand:SF 0 "register_operand" "=r")
1487 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1488 "TARGET_H8300H || TARGET_H8300S"
1489 "xor.w\\t#32768,%e0"
1490 [(set_attr "cc" "clobber")
1491 (set_attr "length" "4")])
1493 ;; ----------------------------------------------------------------------
1494 ;; ABSOLUTE VALUE INSTRUCTIONS
1495 ;; ----------------------------------------------------------------------
1497 (define_expand "abssf2"
1498 [(set (match_operand:SF 0 "register_operand" "")
1499 (abs:SF (match_operand:SF 1 "register_operand" "")))]
1503 (define_insn "*abssf2_h8300"
1504 [(set (match_operand:SF 0 "register_operand" "=r")
1505 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1508 [(set_attr "cc" "clobber")
1509 (set_attr "length" "2")])
1511 (define_insn "*abssf2_h8300hs"
1512 [(set (match_operand:SF 0 "register_operand" "=r")
1513 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1514 "TARGET_H8300H || TARGET_H8300S"
1515 "and.w\\t#32767,%e0"
1516 [(set_attr "cc" "clobber")
1517 (set_attr "length" "4")])
1519 ;; ----------------------------------------------------------------------
1521 ;; ----------------------------------------------------------------------
1523 (define_insn "one_cmplqi2"
1524 [(set (match_operand:QI 0 "register_operand" "=r")
1525 (not:QI (match_operand:QI 1 "register_operand" "0")))]
1528 [(set_attr "length" "2")
1529 (set_attr "cc" "set_znv")])
1531 (define_expand "one_cmplhi2"
1532 [(set (match_operand:HI 0 "register_operand" "=r")
1533 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1537 (define_insn "*one_cmplhi2_h8300"
1538 [(set (match_operand:HI 0 "register_operand" "=r")
1539 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1542 [(set_attr "cc" "clobber")
1543 (set_attr "length" "4")])
1545 (define_insn "*one_cmplhi2_h8300hs"
1546 [(set (match_operand:HI 0 "register_operand" "=r")
1547 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1548 "TARGET_H8300H || TARGET_H8300S"
1550 [(set_attr "cc" "set_znv")
1551 (set_attr "length" "2")])
1553 (define_expand "one_cmplsi2"
1554 [(set (match_operand:SI 0 "register_operand" "=r")
1555 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1559 (define_insn "*one_complsi2_h8300"
1560 [(set (match_operand:SI 0 "register_operand" "=r")
1561 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1563 "not %w0\;not %x0\;not %y0\;not %z0"
1564 [(set_attr "cc" "clobber")
1565 (set_attr "length" "8")])
1567 (define_insn "*one_complsi2_h8300hs"
1568 [(set (match_operand:SI 0 "register_operand" "=r")
1569 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1570 "TARGET_H8300H || TARGET_H8300S"
1572 [(set_attr "cc" "set_znv")
1573 (set_attr "length" "2")])
1575 ;; ----------------------------------------------------------------------
1576 ;; JUMP INSTRUCTIONS
1577 ;; ----------------------------------------------------------------------
1579 ;; Conditional jump instructions
1581 (define_expand "ble"
1583 (if_then_else (le (cc0)
1585 (label_ref (match_operand 0 "" ""))
1590 (define_expand "bleu"
1592 (if_then_else (leu (cc0)
1594 (label_ref (match_operand 0 "" ""))
1599 (define_expand "bge"
1601 (if_then_else (ge (cc0)
1603 (label_ref (match_operand 0 "" ""))
1608 (define_expand "bgeu"
1610 (if_then_else (geu (cc0)
1612 (label_ref (match_operand 0 "" ""))
1617 (define_expand "blt"
1619 (if_then_else (lt (cc0)
1621 (label_ref (match_operand 0 "" ""))
1626 (define_expand "bltu"
1628 (if_then_else (ltu (cc0)
1630 (label_ref (match_operand 0 "" ""))
1635 (define_expand "bgt"
1637 (if_then_else (gt (cc0)
1639 (label_ref (match_operand 0 "" ""))
1644 (define_expand "bgtu"
1646 (if_then_else (gtu (cc0)
1648 (label_ref (match_operand 0 "" ""))
1653 (define_expand "beq"
1655 (if_then_else (eq (cc0)
1657 (label_ref (match_operand 0 "" ""))
1662 (define_expand "bne"
1664 (if_then_else (ne (cc0)
1666 (label_ref (match_operand 0 "" ""))
1671 (define_insn "branch_true"
1673 (if_then_else (match_operator 1 "comparison_operator"
1674 [(cc0) (const_int 0)])
1675 (label_ref (match_operand 0 "" ""))
1680 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1681 && (GET_CODE (operands[1]) == GT
1682 || GET_CODE (operands[1]) == GE
1683 || GET_CODE (operands[1]) == LE
1684 || GET_CODE (operands[1]) == LT))
1686 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1690 if (get_attr_length (insn) == 2)
1691 return \"b%j1 %l0\";
1692 else if (get_attr_length (insn) == 4)
1693 return \"b%j1 %l0:16\";
1695 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1697 [(set_attr "type" "branch")
1698 (set_attr "cc" "none")])
1700 (define_insn "branch_false"
1702 (if_then_else (match_operator 1 "comparison_operator"
1703 [(cc0) (const_int 0)])
1705 (label_ref (match_operand 0 "" ""))))]
1709 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1710 && (GET_CODE (operands[1]) == GT
1711 || GET_CODE (operands[1]) == GE
1712 || GET_CODE (operands[1]) == LE
1713 || GET_CODE (operands[1]) == LT))
1715 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1719 if (get_attr_length (insn) == 2)
1720 return \"b%k1 %l0\";
1721 else if (get_attr_length (insn) == 4)
1722 return \"b%k1 %l0:16\";
1724 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1726 [(set_attr "type" "branch")
1727 (set_attr "cc" "none")])
1729 ;; Unconditional and other jump instructions.
1733 (label_ref (match_operand 0 "" "")))]
1737 if (get_attr_length (insn) == 2)
1739 else if (get_attr_length (insn) == 4)
1740 return \"bra %l0:16\";
1742 return \"jmp @%l0\";
1744 [(set_attr "type" "branch")
1745 (set_attr "cc" "none")])
1747 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1749 (define_expand "tablejump"
1750 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
1751 (use (label_ref (match_operand 1 "" "")))])]
1755 (define_insn "*tablejump_h8300"
1756 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1757 (use (label_ref (match_operand 1 "" "")))]
1760 [(set_attr "cc" "none")
1761 (set_attr "length" "2")])
1763 (define_insn "*tablejump_h8300hs_advanced"
1764 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1765 (use (label_ref (match_operand 1 "" "")))]
1766 "TARGET_H8300H || TARGET_H8300S"
1768 [(set_attr "cc" "none")
1769 (set_attr "length" "2")])
1771 (define_insn "*tablejump_h8300hs_normal"
1772 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1773 (use (label_ref (match_operand 1 "" "")))]
1774 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1776 [(set_attr "cc" "none")
1777 (set_attr "length" "2")])
1779 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1781 (define_expand "indirect_jump"
1782 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1786 (define_insn "*indirect_jump_h8300"
1787 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1790 [(set_attr "cc" "none")
1791 (set_attr "length" "2")])
1793 (define_insn "*indirect_jump_h8300hs_advanced"
1794 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1795 "TARGET_H8300H || TARGET_H8300S"
1797 [(set_attr "cc" "none")
1798 (set_attr "length" "2")])
1800 (define_insn "*indirect_jump_h8300hs_normal"
1801 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1802 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1804 [(set_attr "cc" "none")
1805 (set_attr "length" "2")])
1807 ;; Call subroutine with no return value.
1809 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1812 [(call (match_operand:QI 0 "call_insn_operand" "or")
1813 (match_operand:HI 1 "general_operand" "g"))]
1817 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1818 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1819 return \"jsr\\t@%0:8\";
1821 return \"jsr\\t%0\";
1823 [(set_attr "cc" "clobber")
1824 (set (attr "length")
1825 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1829 ;; Call subroutine, returning value in operand 0
1830 ;; (which must be a hard register).
1832 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1834 (define_insn "call_value"
1835 [(set (match_operand 0 "" "=r")
1836 (call (match_operand:QI 1 "call_insn_operand" "or")
1837 (match_operand:HI 2 "general_operand" "g")))]
1841 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1842 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1843 return \"jsr\\t@%1:8\";
1845 return \"jsr\\t%1\";
1847 [(set_attr "cc" "clobber")
1848 (set (attr "length")
1849 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1857 [(set_attr "cc" "none")
1858 (set_attr "length" "2")])
1860 ;; ----------------------------------------------------------------------
1861 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
1862 ;; ----------------------------------------------------------------------
1864 (define_expand "push_h8300"
1865 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
1866 (match_operand:HI 0 "register_operand" ""))]
1870 (define_expand "push_h8300hs"
1871 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
1872 (match_operand:SI 0 "register_operand" ""))]
1873 "TARGET_H8300H && TARGET_H8300S"
1876 (define_expand "push_h8300hs_normal"
1877 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
1878 (match_operand:SI 0 "register_operand" ""))]
1879 "TARGET_NORMAL_MODE"
1882 (define_expand "pop_h8300"
1883 [(set (match_operand:HI 0 "register_operand" "")
1884 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
1888 (define_expand "pop_h8300hs"
1889 [(set (match_operand:SI 0 "register_operand" "")
1890 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
1891 "TARGET_H8300H && TARGET_H8300S"
1894 (define_expand "pop_h8300hs_normal"
1895 [(set (match_operand:SI 0 "register_operand" "")
1896 (mem:SI (post_inc:HI (reg:HI SP_REG))))]
1897 "TARGET_NORMAL_MODE"
1900 (define_insn "stm_h8300s_2_advanced"
1902 [(set (reg:SI SP_REG)
1903 (plus:SI (reg:SI SP_REG) (const_int -8)))
1904 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1905 (match_operand:SI 0 "register_operand" ""))
1906 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1907 (match_operand:SI 1 "register_operand" ""))])]
1908 "TARGET_H8300S && !TARGET_NORMAL_MODE
1909 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
1910 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
1911 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
1912 "stm.l\\t%S0-%S1,@-er7"
1913 [(set_attr "cc" "none")
1914 (set_attr "length" "4")])
1916 (define_insn "stm_h8300s_2_normal"
1918 [(set (reg:HI SP_REG)
1919 (plus:HI (reg:HI SP_REG) (const_int -8)))
1920 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
1921 (match_operand:SI 0 "register_operand" ""))
1922 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
1923 (match_operand:SI 1 "register_operand" ""))])]
1924 "TARGET_H8300S && TARGET_NORMAL_MODE
1925 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
1926 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
1927 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
1928 "stm.l\\t%S0-%S1,@-er7"
1929 [(set_attr "cc" "none")
1930 (set_attr "length" "4")])
1932 (define_expand "stm_h8300s_2"
1933 [(use (match_operand:SI 0 "register_operand" ""))
1934 (use (match_operand:SI 1 "register_operand" ""))]
1936 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
1937 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
1938 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
1941 if (!TARGET_NORMAL_MODE)
1942 emit_insn (gen_stm_h8300s_2_advanced (operands[0], operands[1]));
1944 emit_insn (gen_stm_h8300s_2_normal (operands[0], operands[1]));
1948 (define_insn "stm_h8300s_3_advanced"
1950 [(set (reg:SI SP_REG)
1951 (plus:SI (reg:SI SP_REG) (const_int -12)))
1952 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1953 (match_operand:SI 0 "register_operand" ""))
1954 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1955 (match_operand:SI 1 "register_operand" ""))
1956 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1957 (match_operand:SI 2 "register_operand" ""))])]
1958 "TARGET_H8300S && !TARGET_NORMAL_MODE
1959 && ((REGNO (operands[0]) == 0
1960 && REGNO (operands[1]) == 1
1961 && REGNO (operands[2]) == 2)
1962 || (REGNO (operands[0]) == 4
1963 && REGNO (operands[1]) == 5
1964 && REGNO (operands[2]) == 6))"
1965 "stm.l\\t%S0-%S2,@-er7"
1966 [(set_attr "cc" "none")
1967 (set_attr "length" "4")])
1969 (define_insn "stm_h8300s_3_normal"
1971 [(set (reg:HI SP_REG)
1972 (plus:HI (reg:HI SP_REG) (const_int -12)))
1973 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
1974 (match_operand:SI 0 "register_operand" ""))
1975 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
1976 (match_operand:SI 1 "register_operand" ""))
1977 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
1978 (match_operand:SI 2 "register_operand" ""))])]
1979 "TARGET_H8300S && TARGET_NORMAL_MODE
1980 && ((REGNO (operands[0]) == 0
1981 && REGNO (operands[1]) == 1
1982 && REGNO (operands[2]) == 2)
1983 || (REGNO (operands[0]) == 4
1984 && REGNO (operands[1]) == 5
1985 && REGNO (operands[2]) == 6))"
1986 "stm.l\\t%S0-%S2,@-er7"
1987 [(set_attr "cc" "none")
1988 (set_attr "length" "4")])
1990 (define_expand "stm_h8300s_3"
1991 [(use (match_operand:SI 0 "register_operand" ""))
1992 (use (match_operand:SI 1 "register_operand" ""))
1993 (use (match_operand:SI 2 "register_operand" ""))]
1995 && ((REGNO (operands[0]) == 0
1996 && REGNO (operands[1]) == 1
1997 && REGNO (operands[2]) == 2)
1998 || (REGNO (operands[0]) == 4
1999 && REGNO (operands[1]) == 5
2000 && REGNO (operands[2]) == 6))"
2003 if (!TARGET_NORMAL_MODE)
2004 emit_insn (gen_stm_h8300s_3_advanced (operands[0], operands[1],
2007 emit_insn (gen_stm_h8300s_3_normal (operands[0], operands[1],
2012 (define_insn "stm_h8300s_4_advanced"
2014 [(set (reg:SI SP_REG)
2015 (plus:SI (reg:SI SP_REG) (const_int -16)))
2016 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
2017 (match_operand:SI 0 "register_operand" ""))
2018 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
2019 (match_operand:SI 1 "register_operand" ""))
2020 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
2021 (match_operand:SI 2 "register_operand" ""))
2022 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
2023 (match_operand:SI 3 "register_operand" ""))])]
2024 "TARGET_H8300S && !TARGET_NORMAL_MODE
2025 && REGNO (operands[0]) == 0
2026 && REGNO (operands[1]) == 1
2027 && REGNO (operands[2]) == 2
2028 && REGNO (operands[3]) == 3"
2029 "stm.l\\t%S0-%S3,@-er7"
2030 [(set_attr "cc" "none")
2031 (set_attr "length" "4")])
2033 (define_insn "stm_h8300s_4_normal"
2035 [(set (reg:HI SP_REG)
2036 (plus:HI (reg:HI SP_REG) (const_int -16)))
2037 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
2038 (match_operand:SI 0 "register_operand" ""))
2039 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
2040 (match_operand:SI 1 "register_operand" ""))
2041 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
2042 (match_operand:SI 2 "register_operand" ""))
2043 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
2044 (match_operand:SI 3 "register_operand" ""))])]
2045 "TARGET_H8300S && TARGET_NORMAL_MODE
2046 && REGNO (operands[0]) == 0
2047 && REGNO (operands[1]) == 1
2048 && REGNO (operands[2]) == 2
2049 && REGNO (operands[3]) == 3"
2050 "stm.l\\t%S0-%S3,@-er7"
2051 [(set_attr "cc" "none")
2052 (set_attr "length" "4")])
2054 (define_expand "stm_h8300s_4"
2055 [(use (match_operand:SI 0 "register_operand" ""))
2056 (use (match_operand:SI 1 "register_operand" ""))
2057 (use (match_operand:SI 2 "register_operand" ""))
2058 (use (match_operand:SI 3 "register_operand" ""))]
2060 && REGNO (operands[0]) == 0
2061 && REGNO (operands[1]) == 1
2062 && REGNO (operands[2]) == 2
2063 && REGNO (operands[3]) == 3"
2066 if (!TARGET_NORMAL_MODE)
2067 emit_insn (gen_stm_h8300s_4_advanced (operands[0], operands[1],
2068 operands[2], operands[3]));
2070 emit_insn (gen_stm_h8300s_4_normal (operands[0], operands[1],
2071 operands[2], operands[3]));
2075 (define_insn "ldm_h8300s_2_advanced"
2077 [(set (reg:SI SP_REG)
2078 (plus:SI (reg:SI SP_REG) (const_int 8)))
2079 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2080 (match_operand:SI 0 "register_operand" ""))
2081 (set (mem:SI (reg:SI SP_REG))
2082 (match_operand:SI 1 "register_operand" ""))])]
2083 "TARGET_H8300S && !TARGET_NORMAL_MODE
2084 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
2085 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
2086 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
2087 "ldm.l\\t@er7+,%S0-%S1"
2088 [(set_attr "cc" "none")
2089 (set_attr "length" "4")])
2091 (define_insn "ldm_h8300s_2_normal"
2093 [(set (reg:SI SP_REG)
2094 (plus:SI (reg:SI SP_REG) (const_int 8)))
2095 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2096 (match_operand:SI 0 "register_operand" ""))
2097 (set (mem:SI (reg:SI SP_REG))
2098 (match_operand:SI 1 "register_operand" ""))])]
2099 "TARGET_H8300S && TARGET_NORMAL_MODE
2100 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
2101 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
2102 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
2103 "ldm.l\\t@er7+,%S0-%S1"
2104 [(set_attr "cc" "none")
2105 (set_attr "length" "4")])
2107 (define_expand "ldm_h8300s_2"
2108 [(use (match_operand:SI 0 "register_operand" ""))
2109 (use (match_operand:SI 1 "register_operand" ""))]
2111 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
2112 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
2113 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
2116 if (!TARGET_NORMAL_MODE)
2117 emit_insn (gen_ldm_h8300s_2_advanced (operands[0], operands[1]));
2119 emit_insn (gen_ldm_h8300s_2_normal (operands[0], operands[1]));
2123 (define_insn "ldm_h8300s_3_advanced"
2125 [(set (reg:SI SP_REG)
2126 (plus:SI (reg:SI SP_REG) (const_int 12)))
2127 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
2128 (match_operand:SI 0 "register_operand" ""))
2129 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2130 (match_operand:SI 1 "register_operand" ""))
2131 (set (mem:SI (reg:SI SP_REG))
2132 (match_operand:SI 2 "register_operand" ""))])]
2133 "TARGET_H8300S && !TARGET_NORMAL_MODE
2134 && ((REGNO (operands[0]) == 0
2135 && REGNO (operands[1]) == 1
2136 && REGNO (operands[2]) == 2)
2137 || (REGNO (operands[0]) == 4
2138 && REGNO (operands[1]) == 5
2139 && REGNO (operands[2]) == 6))"
2140 "ldm.l\\t@er7+,%S0-%S2"
2141 [(set_attr "cc" "none")
2142 (set_attr "length" "4")])
2144 (define_insn "ldm_h8300s_3_normal"
2146 [(set (reg:HI SP_REG)
2147 (plus:HI (reg:HI SP_REG) (const_int 12)))
2148 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 8)))
2149 (match_operand:SI 0 "register_operand" ""))
2150 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2151 (match_operand:SI 1 "register_operand" ""))
2152 (set (mem:SI (reg:HI SP_REG))
2153 (match_operand:SI 2 "register_operand" ""))])]
2154 "TARGET_H8300S && TARGET_NORMAL_MODE
2155 && ((REGNO (operands[0]) == 0
2156 && REGNO (operands[1]) == 1
2157 && REGNO (operands[2]) == 2)
2158 || (REGNO (operands[0]) == 4
2159 && REGNO (operands[1]) == 5
2160 && REGNO (operands[2]) == 6))"
2161 "ldm.l\\t@er7+,%S0-%S2"
2162 [(set_attr "cc" "none")
2163 (set_attr "length" "4")])
2165 (define_expand "ldm_h8300s_3"
2166 [(use (match_operand:SI 0 "register_operand" ""))
2167 (use (match_operand:SI 1 "register_operand" ""))
2168 (use (match_operand:SI 2 "register_operand" ""))]
2170 && ((REGNO (operands[0]) == 0
2171 && REGNO (operands[1]) == 1
2172 && REGNO (operands[2]) == 2)
2173 || (REGNO (operands[0]) == 4
2174 && REGNO (operands[1]) == 5
2175 && REGNO (operands[2]) == 6))"
2178 if (!TARGET_NORMAL_MODE)
2179 emit_insn (gen_ldm_h8300s_3_advanced (operands[0], operands[1],
2182 emit_insn (gen_ldm_h8300s_3_normal (operands[0], operands[1],
2187 (define_insn "ldm_h8300s_4_advanced"
2189 [(set (reg:SI SP_REG)
2190 (plus:SI (reg:SI SP_REG) (const_int 16)))
2191 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 12)))
2192 (match_operand:SI 0 "register_operand" ""))
2193 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
2194 (match_operand:SI 1 "register_operand" ""))
2195 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2196 (match_operand:SI 2 "register_operand" ""))
2197 (set (mem:SI (reg:SI SP_REG))
2198 (match_operand:SI 3 "register_operand" ""))])]
2199 "TARGET_H8300S && !TARGET_NORMAL_MODE
2200 && REGNO (operands[0]) == 0
2201 && REGNO (operands[1]) == 1
2202 && REGNO (operands[2]) == 2
2203 && REGNO (operands[3]) == 3"
2204 "ldm.l\\t@er7+,%S0-%S3"
2205 [(set_attr "cc" "none")
2206 (set_attr "length" "4")])
2208 (define_insn "ldm_h8300s_4_normal"
2210 [(set (reg:HI SP_REG)
2211 (plus:HI (reg:HI SP_REG) (const_int 16)))
2212 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 12)))
2213 (match_operand:SI 0 "register_operand" ""))
2214 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 8)))
2215 (match_operand:SI 1 "register_operand" ""))
2216 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2217 (match_operand:SI 2 "register_operand" ""))
2218 (set (mem:SI (reg:HI SP_REG))
2219 (match_operand:SI 3 "register_operand" ""))])]
2220 "TARGET_H8300S && !TARGET_NORMAL_MODE
2221 && REGNO (operands[0]) == 0
2222 && REGNO (operands[1]) == 1
2223 && REGNO (operands[2]) == 2
2224 && REGNO (operands[3]) == 3"
2225 "ldm.l\\t@er7+,%S0-%S3"
2226 [(set_attr "cc" "none")
2227 (set_attr "length" "4")])
2229 (define_expand "ldm_h8300s_4"
2230 [(use (match_operand:SI 0 "register_operand" ""))
2231 (use (match_operand:SI 1 "register_operand" ""))
2232 (use (match_operand:SI 2 "register_operand" ""))
2233 (use (match_operand:SI 3 "register_operand" ""))]
2234 "TARGET_H8300S && !TARGET_NORMAL_MODE
2235 && REGNO (operands[0]) == 0
2236 && REGNO (operands[1]) == 1
2237 && REGNO (operands[2]) == 2
2238 && REGNO (operands[3]) == 3"
2241 if (!TARGET_NORMAL_MODE)
2242 emit_insn (gen_ldm_h8300s_4_advanced (operands[0], operands[1],
2243 operands[2], operands[3]));
2245 emit_insn (gen_ldm_h8300s_4_normal (operands[0], operands[1],
2246 operands[2], operands[3]));
2250 (define_expand "return"
2252 "h8300_can_use_return_insn_p ()"
2255 (define_insn "*return_1"
2260 if (h8300_current_function_interrupt_function_p ())
2265 [(set_attr "cc" "none")
2266 (set_attr "length" "2")])
2268 (define_expand "prologue"
2271 "h8300_expand_prologue (); DONE;")
2273 (define_expand "epilogue"
2276 "h8300_expand_epilogue ();")
2278 (define_insn "monitor_prologue"
2279 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2284 return \"subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr\";
2285 else if (TARGET_H8300H)
2286 return \"mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr\";
2287 else if (TARGET_H8300S)
2288 return \"stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\";
2291 [(set_attr "length" "20")
2292 (set_attr "cc" "clobber")])
2294 ;; ----------------------------------------------------------------------
2295 ;; EXTEND INSTRUCTIONS
2296 ;; ----------------------------------------------------------------------
2298 (define_expand "zero_extendqihi2"
2299 [(set (match_operand:HI 0 "register_operand" "")
2300 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2304 (define_insn "*zero_extendqihi2_h8300"
2305 [(set (match_operand:HI 0 "register_operand" "=r,r")
2306 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2311 [(set_attr "length" "2,10")
2312 (set_attr "cc" "clobber,clobber")])
2314 (define_insn "*zero_extendqihi2_h8300hs"
2315 [(set (match_operand:HI 0 "register_operand" "=r,r")
2316 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2317 "TARGET_H8300H || TARGET_H8300S"
2321 [(set_attr "length" "2,10")
2322 (set_attr "cc" "set_znv,set_znv")])
2324 ;; Split the zero extension of a general operand (actually a memory
2325 ;; operand) into a load of the operand and the actual zero extension
2326 ;; so that 1) the length will be accurate, and 2) the zero extensions
2327 ;; appearing at the end of basic blocks may be merged.
2330 [(set (match_operand:HI 0 "register_operand" "")
2331 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2336 (zero_extend:HI (match_dup 2)))]
2337 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2339 (define_expand "zero_extendqisi2"
2340 [(set (match_operand:SI 0 "register_operand" "")
2341 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2345 (define_insn "*zero_extendqisi2_h8300"
2346 [(set (match_operand:SI 0 "register_operand" "=r,r")
2347 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2350 mov.b #0,%x0\;sub.w %e0,%e0
2351 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
2352 [(set_attr "length" "4,8")
2353 (set_attr "cc" "clobber,clobber")])
2355 (define_insn "*zero_extendqisi2_h8300hs"
2356 [(set (match_operand:SI 0 "register_operand" "=r,r")
2357 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2358 "TARGET_H8300H || TARGET_H8300S"
2362 [(set (match_operand:SI 0 "register_operand" "")
2363 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2364 "(TARGET_H8300H || TARGET_H8300S)
2365 && reg_overlap_mentioned_p (operands[0], operands[1])
2366 && reload_completed"
2370 (zero_extend:HI (match_dup 2)))
2372 (zero_extend:SI (match_dup 3)))]
2373 "operands[2] = gen_lowpart (QImode, operands[0]);
2374 operands[3] = gen_lowpart (HImode, operands[0]);")
2377 [(set (match_operand:SI 0 "register_operand" "")
2378 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2379 "(TARGET_H8300H || TARGET_H8300S)
2380 && !reg_overlap_mentioned_p (operands[0], operands[1])
2381 && reload_completed"
2384 (set (strict_low_part (match_dup 2))
2386 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2388 (define_expand "zero_extendhisi2"
2389 [(set (match_operand:SI 0 "register_operand" "")
2390 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2394 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
2395 (define_insn "*zero_extendhisi2_h8300"
2396 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2397 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
2401 mov.w %f1,%f0\;sub.w %e0,%e0
2402 mov.w %e1,%f0\;sub.w %e0,%e0"
2403 [(set_attr "length" "2,4,6")
2404 (set_attr "cc" "clobber,clobber,clobber")])
2406 (define_insn "*zero_extendhisi2_h8300hs"
2407 [(set (match_operand:SI 0 "register_operand" "=r")
2408 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2409 "TARGET_H8300H || TARGET_H8300S"
2411 [(set_attr "length" "2")
2412 (set_attr "cc" "set_znv")])
2414 (define_expand "extendqihi2"
2415 [(set (match_operand:HI 0 "register_operand" "")
2416 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
2420 (define_insn "*extendqihi2_h8300"
2421 [(set (match_operand:HI 0 "register_operand" "=r,r")
2422 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2425 bld #7,%s0\;subx %t0,%t0
2426 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
2427 [(set_attr "length" "4,8")
2428 (set_attr "cc" "clobber,clobber")])
2430 (define_insn "*extendqihi2_h8300hs"
2431 [(set (match_operand:HI 0 "register_operand" "=r")
2432 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
2433 "TARGET_H8300H || TARGET_H8300S"
2435 [(set_attr "length" "2")
2436 (set_attr "cc" "set_znv")])
2438 (define_expand "extendqisi2"
2439 [(set (match_operand:SI 0 "register_operand" "")
2440 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2444 (define_insn "*extendqisi2_h8300"
2445 [(set (match_operand:SI 0 "register_operand" "")
2446 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2449 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
2450 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
2451 [(set_attr "length" "8,12")
2452 (set_attr "cc" "clobber,clobber")])
2454 ;; The following pattern is needed because without the pattern, the
2455 ;; combiner would split (sign_extend:SI (reg:QI)) into into two 24-bit
2456 ;; shifts, one ashift and one ashiftrt.
2458 (define_insn_and_split "*extendqisi2_h8300hs"
2459 [(set (match_operand:SI 0 "register_operand" "=r")
2460 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2461 "(TARGET_H8300H || TARGET_H8300S)"
2463 "&& reload_completed"
2465 (sign_extend:HI (match_dup 1)))
2467 (sign_extend:SI (match_dup 2)))]
2468 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2470 (define_expand "extendhisi2"
2471 [(set (match_operand:SI 0 "register_operand" "")
2472 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2476 (define_insn "*extendhisi2_h8300"
2477 [(set (match_operand:SI 0 "register_operand" "=r,r")
2478 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
2481 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
2482 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
2483 [(set_attr "length" "6,10")
2484 (set_attr "cc" "clobber,clobber")])
2486 (define_insn "*extendhisi2_h8300hs"
2487 [(set (match_operand:SI 0 "register_operand" "=r")
2488 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2489 "TARGET_H8300H || TARGET_H8300S"
2491 [(set_attr "length" "2")
2492 (set_attr "cc" "set_znv")])
2494 ;; ----------------------------------------------------------------------
2496 ;; ----------------------------------------------------------------------
2498 ;; We make some attempt to provide real efficient shifting. One example is
2499 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
2500 ;; reg and moving 0 into the former reg.
2502 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2503 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2504 ;; give the optimizer more cracks at the code. However, we wish to do things
2505 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
2506 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
2507 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
2508 ;; to detect cases it can optimize.
2510 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2511 ;; easier "do it at insn emit time" route.
2515 (define_expand "ashlqi3"
2516 [(set (match_operand:QI 0 "register_operand" "")
2517 (ashift:QI (match_operand:QI 1 "register_operand" "")
2518 (match_operand:QI 2 "nonmemory_operand" "")))]
2520 "expand_a_shift (QImode, ASHIFT, operands); DONE;")
2522 (define_expand "ashrqi3"
2523 [(set (match_operand:QI 0 "register_operand" "")
2524 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2525 (match_operand:QI 2 "nonmemory_operand" "")))]
2527 "expand_a_shift (QImode, ASHIFTRT, operands); DONE;")
2529 (define_expand "lshrqi3"
2530 [(set (match_operand:QI 0 "register_operand" "")
2531 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2532 (match_operand:QI 2 "nonmemory_operand" "")))]
2534 "expand_a_shift (QImode, LSHIFTRT, operands); DONE;")
2536 (define_insn "*shiftqi"
2537 [(set (match_operand:QI 0 "register_operand" "=r,r")
2538 (match_operator:QI 3 "nshift_operator"
2539 [ (match_operand:QI 1 "register_operand" "0,0")
2540 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2541 (clobber (match_scratch:QI 4 "=X,&r"))]
2543 "* return output_a_shift (operands);"
2544 [(set (attr "length")
2545 (symbol_ref "compute_a_shift_length (insn, operands)"))
2547 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2551 (define_expand "ashlhi3"
2552 [(set (match_operand:HI 0 "register_operand" "")
2553 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
2554 (match_operand:QI 2 "nonmemory_operand" "")))]
2556 "expand_a_shift (HImode, ASHIFT, operands); DONE;")
2558 (define_expand "lshrhi3"
2559 [(set (match_operand:HI 0 "register_operand" "")
2560 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
2561 (match_operand:QI 2 "nonmemory_operand" "")))]
2563 "expand_a_shift (HImode, LSHIFTRT, operands); DONE;")
2565 (define_expand "ashrhi3"
2566 [(set (match_operand:HI 0 "register_operand" "")
2567 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
2568 (match_operand:QI 2 "nonmemory_operand" "")))]
2570 "expand_a_shift (HImode, ASHIFTRT, operands); DONE;")
2572 (define_insn "*shifthi"
2573 [(set (match_operand:HI 0 "register_operand" "=r,r")
2574 (match_operator:HI 3 "nshift_operator"
2575 [ (match_operand:HI 1 "register_operand" "0,0")
2576 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
2577 (clobber (match_scratch:QI 4 "=X,&r"))]
2579 "* return output_a_shift (operands);"
2580 [(set (attr "length")
2581 (symbol_ref "compute_a_shift_length (insn, operands)"))
2583 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2587 (define_expand "ashlsi3"
2588 [(set (match_operand:SI 0 "register_operand" "")
2589 (ashift:SI (match_operand:SI 1 "general_operand" "")
2590 (match_operand:QI 2 "nonmemory_operand" "")))]
2592 "expand_a_shift (SImode, ASHIFT, operands); DONE;")
2594 (define_expand "lshrsi3"
2595 [(set (match_operand:SI 0 "register_operand" "")
2596 (lshiftrt:SI (match_operand:SI 1 "general_operand" "")
2597 (match_operand:QI 2 "nonmemory_operand" "")))]
2599 "expand_a_shift (SImode, LSHIFTRT, operands); DONE;")
2601 (define_expand "ashrsi3"
2602 [(set (match_operand:SI 0 "register_operand" "")
2603 (ashiftrt:SI (match_operand:SI 1 "general_operand" "")
2604 (match_operand:QI 2 "nonmemory_operand" "")))]
2606 "expand_a_shift (SImode, ASHIFTRT, operands); DONE;")
2608 (define_insn "*shiftsi"
2609 [(set (match_operand:SI 0 "register_operand" "=r,r")
2610 (match_operator:SI 3 "nshift_operator"
2611 [ (match_operand:SI 1 "register_operand" "0,0")
2612 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
2613 (clobber (match_scratch:QI 4 "=X,&r"))]
2615 "* return output_a_shift (operands);"
2616 [(set (attr "length")
2617 (symbol_ref "compute_a_shift_length (insn, operands)"))
2619 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2621 ;; Split a variable shift into a loop. If the register containing
2622 ;; the shift count dies, then we just use that register.
2626 [(set (match_operand 0 "register_operand" "")
2627 (match_operator 2 "nshift_operator"
2629 (match_operand:QI 1 "register_operand" "")]))
2630 (clobber (match_operand:QI 3 "register_operand" ""))])]
2632 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2636 (if_then_else (le (cc0) (const_int 0))
2637 (label_ref (match_dup 5))
2642 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2643 (clobber (scratch:QI))])
2645 (plus:QI (match_dup 1) (const_int -1)))
2649 (if_then_else (ne (cc0) (const_int 0))
2650 (label_ref (match_dup 4))
2653 "operands[4] = gen_label_rtx ();
2654 operands[5] = gen_label_rtx ();")
2658 [(set (match_operand 0 "register_operand" "")
2659 (match_operator 2 "nshift_operator"
2661 (match_operand:QI 1 "register_operand" "")]))
2662 (clobber (match_operand:QI 3 "register_operand" ""))])]
2664 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2670 (if_then_else (le (cc0) (const_int 0))
2671 (label_ref (match_dup 5))
2676 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2677 (clobber (scratch:QI))])
2679 (plus:QI (match_dup 3) (const_int -1)))
2683 (if_then_else (ne (cc0) (const_int 0))
2684 (label_ref (match_dup 4))
2687 "operands[4] = gen_label_rtx ();
2688 operands[5] = gen_label_rtx ();")
2690 ;; ----------------------------------------------------------------------
2692 ;; ----------------------------------------------------------------------
2694 (define_expand "rotlqi3"
2695 [(set (match_operand:QI 0 "register_operand" "")
2696 (rotate:QI (match_operand:QI 1 "register_operand" "")
2697 (match_operand:QI 2 "nonmemory_operand" "")))]
2699 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2701 (define_insn "*rotlqi3_1"
2702 [(set (match_operand:QI 0 "register_operand" "=r")
2703 (rotate:QI (match_operand:QI 1 "register_operand" "0")
2704 (match_operand:QI 2 "immediate_operand" "")))]
2706 "* return output_a_rotate (ROTATE, operands);"
2707 [(set (attr "length")
2708 (symbol_ref "compute_a_rotate_length (operands)"))
2709 (set_attr "cc" "clobber")])
2711 (define_expand "rotlhi3"
2712 [(set (match_operand:HI 0 "register_operand" "")
2713 (rotate:HI (match_operand:HI 1 "register_operand" "")
2714 (match_operand:QI 2 "nonmemory_operand" "")))]
2716 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2718 (define_insn "*rotlhi3_1"
2719 [(set (match_operand:HI 0 "register_operand" "=r")
2720 (rotate:HI (match_operand:HI 1 "register_operand" "0")
2721 (match_operand:QI 2 "immediate_operand" "")))]
2723 "* return output_a_rotate (ROTATE, operands);"
2724 [(set (attr "length")
2725 (symbol_ref "compute_a_rotate_length (operands)"))
2726 (set_attr "cc" "clobber")])
2728 (define_expand "rotlsi3"
2729 [(set (match_operand:SI 0 "register_operand" "")
2730 (rotate:SI (match_operand:SI 1 "register_operand" "")
2731 (match_operand:QI 2 "nonmemory_operand" "")))]
2732 "TARGET_H8300H || TARGET_H8300S"
2733 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2735 (define_insn "*rotlsi3_1"
2736 [(set (match_operand:SI 0 "register_operand" "=r")
2737 (rotate:SI (match_operand:SI 1 "register_operand" "0")
2738 (match_operand:QI 2 "immediate_operand" "")))]
2739 "TARGET_H8300H || TARGET_H8300S"
2740 "* return output_a_rotate (ROTATE, operands);"
2741 [(set (attr "length")
2742 (symbol_ref "compute_a_rotate_length (operands)"))
2743 (set_attr "cc" "clobber")])
2745 ;; -----------------------------------------------------------------
2747 ;; -----------------------------------------------------------------
2748 ;; The H8/300 has given 1/8th of its opcode space to bitfield
2749 ;; instructions so let's use them as well as we can.
2751 ;; You'll never believe all these patterns perform one basic action --
2752 ;; load a bit from the source, optionally invert the bit, then store it
2753 ;; in the destination (which is known to be zero).
2755 ;; Combine obviously need some work to better identify this situation and
2756 ;; canonicalize the form better.
2759 ;; Normal loads with a 16bit destination.
2763 [(set (match_operand:HI 0 "register_operand" "=&r")
2764 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2766 (match_operand:HI 2 "immediate_operand" "n")))]
2768 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
2769 [(set_attr "cc" "clobber")
2770 (set_attr "length" "6")])
2773 ;; Inverted loads with a 16bit destination.
2777 [(set (match_operand:HI 0 "register_operand" "=&r")
2778 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
2779 (match_operand:HI 3 "const_int_operand" "n"))
2781 (match_operand:HI 2 "const_int_operand" "n")))]
2783 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2784 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2785 [(set_attr "cc" "clobber")
2786 (set_attr "length" "8")])
2789 ;; Normal loads with a 32bit destination.
2792 (define_insn "*extzv_1_r_h8300"
2793 [(set (match_operand:SI 0 "register_operand" "=&r")
2794 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2796 (match_operand 2 "const_int_operand" "n")))]
2798 && INTVAL (operands[2]) < 16"
2799 "* return output_simode_bld (0, operands);"
2800 [(set_attr "cc" "clobber")
2801 (set_attr "length" "8")])
2803 (define_insn "*extzv_1_r_h8300hs"
2804 [(set (match_operand:SI 0 "register_operand" "=r,r")
2805 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2807 (match_operand 2 "const_int_operand" "n,n")))]
2808 "(TARGET_H8300H || TARGET_H8300S)
2809 && INTVAL (operands[2]) < 16"
2810 "* return output_simode_bld (0, operands);"
2811 [(set_attr "cc" "set_znv,set_znv")
2812 (set_attr "length" "8,6")])
2815 ;; Inverted loads with a 32bit destination.
2818 (define_insn "*extzv_1_r_inv_h8300"
2819 [(set (match_operand:SI 0 "register_operand" "=&r")
2820 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2821 (match_operand:HI 3 "const_int_operand" "n"))
2823 (match_operand 2 "const_int_operand" "n")))]
2825 && INTVAL (operands[2]) < 16
2826 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2827 "* return output_simode_bld (1, operands);"
2828 [(set_attr "cc" "clobber")
2829 (set_attr "length" "8")])
2831 (define_insn "*extzv_1_r_inv_h8300hs"
2832 [(set (match_operand:SI 0 "register_operand" "=r,r")
2833 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
2834 (match_operand 3 "const_int_operand" "n,n"))
2836 (match_operand 2 "const_int_operand" "n,n")))]
2837 "(TARGET_H8300H || TARGET_H8300S)
2838 && INTVAL (operands[2]) < 16
2839 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2840 "* return output_simode_bld (1, operands);"
2841 [(set_attr "cc" "set_znv,set_znv")
2842 (set_attr "length" "8,6")])
2844 (define_expand "insv"
2845 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2846 (match_operand:HI 1 "general_operand" "")
2847 (match_operand:HI 2 "general_operand" ""))
2848 (match_operand:HI 3 "general_operand" ""))]
2852 /* We only have single bit bit-field instructions. */
2853 if (INTVAL (operands[1]) != 1)
2856 /* For now, we don't allow memory operands. */
2857 if (GET_CODE (operands[0]) == MEM
2858 || GET_CODE (operands[3]) == MEM)
2863 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2865 (match_operand:HI 1 "immediate_operand" "n"))
2866 (match_operand:HI 2 "register_operand" "r"))]
2868 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2869 [(set_attr "cc" "clobber")
2870 (set_attr "length" "4")])
2872 (define_expand "extzv"
2873 [(set (match_operand:HI 0 "register_operand" "")
2874 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2875 (match_operand:HI 2 "general_operand" "")
2876 (match_operand:HI 3 "general_operand" "")))]
2880 /* We only have single bit bit-field instructions. */
2881 if (INTVAL (operands[2]) != 1)
2884 /* For now, we don't allow memory operands. */
2885 if (GET_CODE (operands[1]) == MEM)
2889 ;; BAND, BOR, and BXOR patterns
2892 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2893 (match_operator:HI 4 "bit_operator"
2894 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2896 (match_operand:HI 2 "immediate_operand" "n"))
2897 (match_operand:HI 3 "bit_operand" "0")]))]
2899 "bld %Z2,%Y1\;b%c4 #0,%R0\;bst #0,%R0; bl1"
2900 [(set_attr "cc" "clobber")
2901 (set_attr "length" "6")])
2904 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2905 (match_operator:HI 5 "bit_operator"
2906 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2908 (match_operand:HI 2 "immediate_operand" "n"))
2909 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2911 (match_operand:HI 4 "immediate_operand" "n"))]))]
2913 "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #0,%R0; bl3"
2914 [(set_attr "cc" "clobber")
2915 (set_attr "length" "6")])
2917 ;; -----------------------------------------------------------------
2919 ;; -----------------------------------------------------------------
2923 (define_insn "*insv_si_1_n"
2924 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2926 (match_operand:SI 1 "const_int_operand" "n"))
2927 (match_operand:SI 2 "register_operand" "r"))]
2928 "(TARGET_H8300H || TARGET_H8300S)
2929 && INTVAL (operands[1]) < 16"
2930 "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
2931 [(set_attr "cc" "clobber")
2932 (set_attr "length" "4")])
2934 (define_insn "*insv_si_1_n_lshiftrt"
2935 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2937 (match_operand:SI 1 "const_int_operand" "n"))
2938 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2939 (match_operand:SI 3 "const_int_operand" "n")))]
2940 "(TARGET_H8300H || TARGET_H8300S)
2941 && INTVAL (operands[1]) < 16
2942 && INTVAL (operands[3]) < 16"
2943 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
2944 [(set_attr "cc" "clobber")
2945 (set_attr "length" "4")])
2947 (define_insn "*insv_si_1_n_lshiftrt_16"
2948 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2950 (match_operand:SI 1 "const_int_operand" "n"))
2951 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2953 "(TARGET_H8300H || TARGET_H8300S)
2954 && INTVAL (operands[1]) < 16"
2955 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
2956 [(set_attr "cc" "clobber")
2957 (set_attr "length" "6")])
2959 (define_insn "*insv_si_8_8"
2960 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2963 (match_operand:SI 1 "register_operand" "r"))]
2964 "TARGET_H8300H || TARGET_H8300S"
2966 [(set_attr "cc" "clobber")
2967 (set_attr "length" "2")])
2969 (define_insn "*insv_si_8_8_lshiftrt_8"
2970 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2973 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2975 "TARGET_H8300H || TARGET_H8300S"
2977 [(set_attr "cc" "clobber")
2978 (set_attr "length" "2")])
2982 (define_insn "*extzv_8_8"
2983 [(set (match_operand:SI 0 "register_operand" "=r,r")
2984 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2987 "TARGET_H8300H || TARGET_H8300S"
2989 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
2990 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
2991 [(set_attr "cc" "set_znv,clobber")
2992 (set_attr "length" "6,4")])
2994 (define_insn "*extzv_8_16"
2995 [(set (match_operand:SI 0 "register_operand" "=r")
2996 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2999 "TARGET_H8300H || TARGET_H8300S"
3000 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
3001 [(set_attr "cc" "set_znv")
3002 (set_attr "length" "6")])
3004 (define_insn "*extzv_16_8"
3005 [(set (match_operand:SI 0 "register_operand" "=r")
3006 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3009 (clobber (match_scratch:SI 2 "=&r"))]
3011 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
3012 [(set_attr "length" "8")
3013 (set_attr "cc" "set_znv")])
3015 ;; Extract the exponent of a float.
3017 (define_insn_and_split "*extzv_8_23"
3018 [(set (match_operand:SI 0 "register_operand" "=r")
3019 (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
3022 "(TARGET_H8300H || TARGET_H8300S)"
3024 "&& reload_completed"
3025 [(parallel [(set (match_dup 0)
3026 (ashift:SI (match_dup 0)
3028 (clobber (scratch:QI))])
3029 (parallel [(set (match_dup 0)
3030 (lshiftrt:SI (match_dup 0)
3032 (clobber (scratch:QI))])]
3037 ;; ((SImode) HImode) << 15
3039 (define_insn_and_split "*twoshifts_l16_r1"
3040 [(set (match_operand:SI 0 "register_operand" "=r")
3041 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3043 (const_int 2147450880)))]
3044 "(TARGET_H8300H || TARGET_H8300S)"
3046 "&& reload_completed"
3047 [(parallel [(set (match_dup 0)
3048 (ashift:SI (match_dup 0)
3050 (clobber (scratch:QI))])
3051 (parallel [(set (match_dup 0)
3052 (lshiftrt:SI (match_dup 0)
3054 (clobber (scratch:QI))])]
3057 ;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
3059 (define_insn_and_split "*andsi3_ashift_n_lower"
3060 [(set (match_operand:SI 0 "register_operand" "=r,r")
3061 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
3062 (match_operand:QI 2 "const_int_operand" "S,n"))
3063 (match_operand:SI 3 "const_int_operand" "n,n")))
3064 (clobber (match_scratch:QI 4 "=X,&r"))]
3065 "(TARGET_H8300H || TARGET_H8300S)
3066 && INTVAL (operands[2]) <= 15
3067 && INTVAL (operands[3]) == ((-1 << INTVAL (operands[2])) & 0xffff)"
3069 "&& reload_completed"
3070 [(parallel [(set (match_dup 5)
3071 (ashift:HI (match_dup 5)
3073 (clobber (match_dup 4))])
3075 (zero_extend:SI (match_dup 5)))]
3076 "operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3078 ;; Accept (A >> 30) & 2 and the like.
3080 (define_insn "*andsi3_lshiftrt_n_sb"
3081 [(set (match_operand:SI 0 "register_operand" "=r")
3082 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3083 (match_operand:SI 2 "const_int_operand" "n"))
3084 (match_operand:SI 3 "single_one_operand" "n")))]
3085 "(TARGET_H8300H || TARGET_H8300S)
3086 && exact_log2 (INTVAL (operands[3])) < 16
3087 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
3090 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
3091 return \"shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0\";
3093 [(set_attr "length" "8")
3094 (set_attr "cc" "clobber")])
3096 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
3097 [(set (match_operand:SI 0 "register_operand" "=r")
3098 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3100 (const_int 4194304)))]
3101 "(TARGET_H8300H || TARGET_H8300S)"
3103 "&& reload_completed"
3105 (and:SI (lshiftrt:SI (match_dup 0)
3108 (parallel [(set (match_dup 0)
3109 (ashift:SI (match_dup 0)
3111 (clobber (scratch:QI))])]
3116 (define_insn "*addsi3_upper"
3117 [(set (match_operand:SI 0 "register_operand" "=r")
3118 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3120 (match_operand:SI 2 "register_operand" "0")))]
3121 "TARGET_H8300H || TARGET_H8300S"
3123 [(set_attr "length" "2")
3124 (set_attr "cc" "clobber")])
3126 (define_insn "*addsi3_lshiftrt_16_zexthi"
3127 [(set (match_operand:SI 0 "register_operand" "=r")
3128 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3130 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
3131 "TARGET_H8300H || TARGET_H8300S"
3132 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0"
3133 [(set_attr "cc" "clobber")
3134 (set_attr "length" "6")])
3136 (define_insn_and_split "*addsi3_and_r_1"
3137 [(set (match_operand:SI 0 "register_operand" "=r")
3138 (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
3140 (match_operand:SI 2 "register_operand" "0")))]
3141 "(TARGET_H8300H || TARGET_H8300S)"
3143 "&& reload_completed"
3145 (zero_extract:SI (match_dup 1)
3149 (if_then_else (eq (cc0)
3151 (label_ref (match_dup 3))
3154 (plus:SI (match_dup 2)
3157 "operands[3] = gen_label_rtx ();")
3159 (define_insn_and_split "*addsi3_and_not_r_1"
3160 [(set (match_operand:SI 0 "register_operand" "=r")
3161 (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3163 (match_operand:SI 2 "register_operand" "0")))]
3164 "(TARGET_H8300H || TARGET_H8300S)"
3166 "&& reload_completed"
3168 (zero_extract:SI (match_dup 1)
3172 (if_then_else (ne (cc0)
3174 (label_ref (match_dup 3))
3177 (plus:SI (match_dup 2)
3180 "operands[3] = gen_label_rtx ();")
3184 (define_insn "*ixorhi3_zext"
3185 [(set (match_operand:HI 0 "register_operand" "=r")
3186 (match_operator:HI 1 "iorxor_operator"
3187 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
3188 (match_operand:HI 3 "register_operand" "0")]))]
3191 [(set_attr "cc" "clobber")
3192 (set_attr "length" "2")])
3196 (define_insn "*ixorsi3_zext_qi"
3197 [(set (match_operand:SI 0 "register_operand" "=r")
3198 (match_operator:SI 1 "iorxor_operator"
3199 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
3200 (match_operand:SI 3 "register_operand" "0")]))]
3203 [(set_attr "cc" "clobber")
3204 (set_attr "length" "2")])
3206 (define_insn "*ixorsi3_zext_hi"
3207 [(set (match_operand:SI 0 "register_operand" "=r")
3208 (match_operator:SI 1 "iorxor_operator"
3209 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
3210 (match_operand:SI 3 "register_operand" "0")]))]
3211 "TARGET_H8300H || TARGET_H8300S"
3213 [(set_attr "cc" "clobber")
3214 (set_attr "length" "2")])
3216 (define_insn "*ixorsi3_ashift_16"
3217 [(set (match_operand:SI 0 "register_operand" "=r")
3218 (match_operator:SI 1 "iorxor_operator"
3219 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
3221 (match_operand:SI 3 "register_operand" "0")]))]
3222 "TARGET_H8300H || TARGET_H8300S"
3224 [(set_attr "cc" "clobber")
3225 (set_attr "length" "2")])
3227 (define_insn "*ixorsi3_lshiftrt_16"
3228 [(set (match_operand:SI 0 "register_operand" "=r")
3229 (match_operator:SI 1 "iorxor_operator"
3230 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3232 (match_operand:SI 3 "register_operand" "0")]))]
3233 "TARGET_H8300H || TARGET_H8300S"
3235 [(set_attr "cc" "clobber")
3236 (set_attr "length" "2")])
3240 (define_insn "*iorhi3_ashift_8"
3241 [(set (match_operand:HI 0 "register_operand" "=r")
3242 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
3244 (match_operand:HI 2 "register_operand" "0")))]
3247 [(set_attr "cc" "clobber")
3248 (set_attr "length" "2")])
3250 (define_insn "*iorhi3_lshiftrt_8"
3251 [(set (match_operand:HI 0 "register_operand" "=r")
3252 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3254 (match_operand:HI 2 "register_operand" "0")))]
3257 [(set_attr "cc" "clobber")
3258 (set_attr "length" "2")])
3260 (define_insn "*iorhi3_two_qi"
3261 [(set (match_operand:HI 0 "register_operand" "=r")
3262 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
3263 (ashift:HI (match_operand:HI 2 "register_operand" "r")
3267 [(set_attr "cc" "clobber")
3268 (set_attr "length" "2")])
3270 (define_insn "*iorhi3_two_qi_mem"
3271 [(set (match_operand:HI 0 "register_operand" "=&r")
3272 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
3273 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
3276 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
3277 [(set_attr "cc" "clobber")
3278 (set_attr "length" "16")])
3281 [(set (match_operand:HI 0 "register_operand" "")
3282 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
3283 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
3285 "(TARGET_H8300H || TARGET_H8300S)
3287 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
3290 "operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));")
3294 (define_insn "*iorsi3_two_hi"
3295 [(set (match_operand:SI 0 "register_operand" "=r")
3296 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
3297 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3299 "TARGET_H8300H || TARGET_H8300S"
3301 [(set_attr "cc" "clobber")
3302 (set_attr "length" "2")])
3304 (define_insn_and_split "*iorsi3_two_qi_zext"
3305 [(set (match_operand:SI 0 "register_operand" "=&r")
3306 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
3308 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3310 (const_int 65280))))]
3311 "(TARGET_H8300H || TARGET_H8300S)"
3313 "&& reload_completed"
3315 (ior:HI (zero_extend:HI (match_dup 1))
3316 (ashift:HI (subreg:HI (match_dup 2) 0)
3319 (zero_extend:SI (match_dup 3)))]
3320 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3322 (define_insn "*iorsi3_e2f"
3323 [(set (match_operand:SI 0 "register_operand" "=r")
3324 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3326 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3328 "TARGET_H8300H || TARGET_H8300S"
3330 [(set_attr "length" "2")
3331 (set_attr "cc" "clobber")])
3333 (define_insn_and_split "*iorsi3_two_qi_sext"
3334 [(set (match_operand:SI 0 "register_operand" "=r")
3335 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
3336 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
3338 "(TARGET_H8300H || TARGET_H8300S)"
3340 "&& reload_completed"
3342 (ior:HI (zero_extend:HI (match_dup 1))
3343 (ashift:HI (match_dup 4)
3346 (sign_extend:SI (match_dup 3)))]
3347 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3348 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3350 (define_insn "*iorsi3_w"
3351 [(set (match_operand:SI 0 "register_operand" "=r,&r")
3352 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
3354 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
3355 "TARGET_H8300H || TARGET_H8300S"
3357 [(set_attr "length" "2,8")
3358 (set_attr "cc" "clobber,clobber")])
3360 (define_insn "*iorsi3_ashift_31"
3361 [(set (match_operand:SI 0 "register_operand" "=&r")
3362 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3364 (match_operand:SI 2 "register_operand" "0")))]
3365 "TARGET_H8300H || TARGET_H8300S"
3366 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
3367 [(set_attr "length" "6")
3368 (set_attr "cc" "set_znv")])
3370 (define_insn "*iorsi3_and_ashift"
3371 [(set (match_operand:SI 0 "register_operand" "=r")
3372 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3373 (match_operand:SI 2 "const_int_operand" "n"))
3374 (match_operand:SI 3 "single_one_operand" "n"))
3375 (match_operand:SI 4 "register_operand" "0")))]
3376 "(TARGET_H8300H || TARGET_H8300S)
3377 && (INTVAL (operands[3]) & ~0xffff) == 0"
3380 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3381 - INTVAL (operands[2]));
3382 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3383 operands[2] = srcpos;
3384 operands[3] = dstpos;
3385 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
3387 [(set_attr "length" "6")
3388 (set_attr "cc" "clobber")])
3390 (define_insn "*iorsi3_and_lshiftrt"
3391 [(set (match_operand:SI 0 "register_operand" "=r")
3392 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3393 (match_operand:SI 2 "const_int_operand" "n"))
3394 (match_operand:SI 3 "single_one_operand" "n"))
3395 (match_operand:SI 4 "register_operand" "0")))]
3396 "(TARGET_H8300H || TARGET_H8300S)
3397 && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
3400 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3401 + INTVAL (operands[2]));
3402 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3403 operands[2] = srcpos;
3404 operands[3] = dstpos;
3405 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
3407 [(set_attr "length" "6")
3408 (set_attr "cc" "clobber")])
3410 (define_insn "*iorsi3_zero_extract"
3411 [(set (match_operand:SI 0 "register_operand" "=r")
3412 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3414 (match_operand:SI 2 "const_int_operand" "n"))
3415 (match_operand:SI 3 "register_operand" "0")))]
3416 "(TARGET_H8300H || TARGET_H8300S)
3417 && INTVAL (operands[2]) < 16"
3418 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
3419 [(set_attr "length" "6")
3420 (set_attr "cc" "clobber")])
3422 (define_insn "*iorsi3_and_lshiftrt_n_sb"
3423 [(set (match_operand:SI 0 "register_operand" "=r")
3424 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3427 (match_operand:SI 2 "register_operand" "0")))]
3428 "(TARGET_H8300H || TARGET_H8300S)"
3429 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
3430 [(set_attr "length" "8")
3431 (set_attr "cc" "clobber")])
3433 (define_insn "*iorsi3_and_lshiftrt_9_sb"
3434 [(set (match_operand:SI 0 "register_operand" "=r")
3435 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3437 (const_int 4194304))
3438 (match_operand:SI 2 "register_operand" "0")))
3439 (clobber (match_scratch:HI 3 "=&r"))]
3440 "(TARGET_H8300H || TARGET_H8300S)"
3443 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3444 return \"shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3446 return \"rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3448 [(set_attr "length" "10")
3449 (set_attr "cc" "clobber")])
3451 ;; Used to OR the exponent of a float.
3453 (define_insn "*iorsi3_shift"
3454 [(set (match_operand:SI 0 "register_operand" "=r")
3455 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3457 (match_operand:SI 2 "register_operand" "0")))
3458 (clobber (match_scratch:SI 3 "=&r"))]
3459 "TARGET_H8300H || TARGET_H8300S"
3464 [(set (match_operand:SI 0 "register_operand" "")
3465 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3468 (clobber (match_operand:SI 2 "register_operand" ""))])]
3469 "(TARGET_H8300H || TARGET_H8300S)
3471 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3472 && REGNO (operands[0]) != REGNO (operands[1])"
3473 [(parallel [(set (match_dup 3)
3474 (ashift:HI (match_dup 3)
3476 (clobber (scratch:QI))])
3478 (ior:SI (ashift:SI (match_dup 1)
3481 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3485 [(set (match_operand:SI 0 "register_operand" "")
3486 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3489 (clobber (match_operand:SI 2 "register_operand" ""))])]
3490 "(TARGET_H8300H || TARGET_H8300S)
3492 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3493 && REGNO (operands[0]) != REGNO (operands[1]))"
3496 (parallel [(set (match_dup 3)
3497 (ashift:HI (match_dup 3)
3499 (clobber (scratch:QI))])
3501 (ior:SI (ashift:SI (match_dup 2)
3504 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3506 (define_insn "*iorsi2_and_1_lshiftrt_1"
3507 [(set (match_operand:SI 0 "register_operand" "=r")
3508 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3510 (lshiftrt:SI (match_dup 1)
3512 "TARGET_H8300H || TARGET_H8300S"
3513 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
3514 [(set_attr "length" "6")
3515 (set_attr "cc" "clobber")])
3517 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
3518 [(set (match_operand:SI 0 "register_operand" "=r")
3519 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3521 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3523 "(TARGET_H8300H || TARGET_H8300S)"
3525 "&& reload_completed"
3527 (ior:HI (ashift:HI (match_dup 4)
3530 (parallel [(set (match_dup 0)
3531 (ashift:SI (match_dup 0)
3533 (clobber (scratch:QI))])]
3534 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3535 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3537 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
3538 [(set (match_operand:SI 0 "register_operand" "=&r")
3539 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
3541 (const_int 16711680))
3542 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3544 "(TARGET_H8300H || TARGET_H8300S)"
3546 "&& reload_completed"
3548 (ior:HI (zero_extend:HI (match_dup 1))
3549 (ashift:HI (subreg:HI (match_dup 2) 0)
3551 (parallel [(set (match_dup 0)
3552 (ashift:SI (match_dup 0)
3554 (clobber (scratch:QI))])]
3555 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3557 ;; Used to add the exponent of a float.
3559 (define_insn "*addsi3_shift"
3560 [(set (match_operand:SI 0 "register_operand" "=r")
3561 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3562 (const_int 8388608))
3563 (match_operand:SI 2 "register_operand" "0")))
3564 (clobber (match_scratch:SI 3 "=&r"))]
3565 "TARGET_H8300H || TARGET_H8300S"
3570 [(set (match_operand:SI 0 "register_operand" "")
3571 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3572 (const_int 8388608))
3574 (clobber (match_operand:SI 2 "register_operand" ""))])]
3575 "(TARGET_H8300H || TARGET_H8300S)
3577 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3578 && REGNO (operands[0]) != REGNO (operands[1])"
3579 [(parallel [(set (match_dup 3)
3580 (ashift:HI (match_dup 3)
3582 (clobber (scratch:QI))])
3584 (plus:SI (mult:SI (match_dup 1)
3587 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3591 [(set (match_operand:SI 0 "register_operand" "")
3592 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3593 (const_int 8388608))
3595 (clobber (match_operand:SI 2 "register_operand" ""))])]
3596 "(TARGET_H8300H || TARGET_H8300S)
3598 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3599 && REGNO (operands[0]) != REGNO (operands[1]))"
3602 (parallel [(set (match_dup 3)
3603 (ashift:HI (match_dup 3)
3605 (clobber (scratch:QI))])
3607 (plus:SI (mult:SI (match_dup 2)
3610 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3614 (define_insn_and_split "*ashiftsi_sextqi_7"
3615 [(set (match_operand:SI 0 "register_operand" "=r")
3616 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
3618 "(TARGET_H8300H || TARGET_H8300S)"
3620 "&& reload_completed"
3621 [(parallel [(set (match_dup 2)
3622 (ashift:HI (match_dup 2)
3624 (clobber (scratch:QI))])
3626 (sign_extend:SI (match_dup 2)))
3627 (parallel [(set (match_dup 0)
3628 (ashiftrt:SI (match_dup 0)
3630 (clobber (scratch:QI))])]
3631 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3633 ;; Storing a part of HImode to QImode.
3636 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3637 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3641 [(set_attr "cc" "set_znv")
3642 (set_attr "length" "8")])
3644 ;; Storing a part of SImode to QImode.
3647 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3648 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3652 [(set_attr "cc" "set_znv")
3653 (set_attr "length" "8")])
3656 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3657 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3659 (clobber (match_scratch:SI 2 "=&r"))]
3660 "TARGET_H8300H || TARGET_H8300S"
3661 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
3662 [(set_attr "cc" "set_znv")
3663 (set_attr "length" "10")])
3666 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3667 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3669 (clobber (match_scratch:SI 2 "=&r"))]
3670 "TARGET_H8300H || TARGET_H8300S"
3671 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
3672 [(set_attr "cc" "set_znv")
3673 (set_attr "length" "10")])
3675 (define_insn_and_split ""
3677 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3681 (label_ref (match_operand 1 "" ""))
3689 (if_then_else (ge (cc0)
3691 (label_ref (match_dup 1))
3695 (define_insn_and_split ""
3697 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3701 (label_ref (match_operand 1 "" ""))
3709 (if_then_else (lt (cc0)
3711 (label_ref (match_dup 1))
3715 ;; -----------------------------------------------------------------
3716 ;; PEEPHOLE PATTERNS
3717 ;; -----------------------------------------------------------------
3719 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3723 [(set (match_operand:HI 0 "register_operand" "")
3724 (lshiftrt:HI (match_dup 0)
3725 (match_operand:HI 1 "const_int_operand" "")))
3726 (clobber (match_operand:HI 2 "" ""))])
3728 (and:HI (match_dup 0)
3729 (match_operand:HI 3 "const_int_operand" "")))]
3730 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3732 (and:HI (match_dup 0)
3736 (lshiftrt:HI (match_dup 0)
3738 (clobber (match_dup 2))])]
3741 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3745 [(set (match_operand:HI 0 "register_operand" "")
3746 (ashift:HI (match_dup 0)
3747 (match_operand:HI 1 "const_int_operand" "")))
3748 (clobber (match_operand:HI 2 "" ""))])
3750 (and:HI (match_dup 0)
3751 (match_operand:HI 3 "const_int_operand" "")))]
3752 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3754 (and:HI (match_dup 0)
3758 (ashift:HI (match_dup 0)
3760 (clobber (match_dup 2))])]
3763 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3767 [(set (match_operand:SI 0 "register_operand" "")
3768 (lshiftrt:SI (match_dup 0)
3769 (match_operand:SI 1 "const_int_operand" "")))
3770 (clobber (match_operand:SI 2 "" ""))])
3772 (and:SI (match_dup 0)
3773 (match_operand:SI 3 "const_int_operand" "")))]
3774 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3776 (and:SI (match_dup 0)
3780 (lshiftrt:SI (match_dup 0)
3782 (clobber (match_dup 2))])]
3785 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3789 [(set (match_operand:SI 0 "register_operand" "")
3790 (ashift:SI (match_dup 0)
3791 (match_operand:SI 1 "const_int_operand" "")))
3792 (clobber (match_operand:SI 2 "" ""))])
3794 (and:SI (match_dup 0)
3795 (match_operand:SI 3 "const_int_operand" "")))]
3796 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3798 (and:SI (match_dup 0)
3802 (ashift:SI (match_dup 0)
3804 (clobber (match_dup 2))])]
3807 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
3811 [(set (match_operand:SI 0 "register_operand" "")
3812 (lshiftrt:SI (match_dup 0)
3813 (match_operand:SI 1 "const_int_operand" "")))
3814 (clobber (match_operand:SI 2 "" ""))])
3816 (and:SI (match_dup 0)
3817 (match_operand:SI 3 "const_int_operand" "")))]
3818 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
3820 (and:SI (match_dup 0)
3824 (lshiftrt:SI (match_dup 0)
3826 (clobber (match_dup 2))])]
3829 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
3833 [(set (match_operand:SI 0 "register_operand" "")
3834 (ashift:SI (match_dup 0)
3835 (match_operand:SI 1 "const_int_operand" "")))
3836 (clobber (match_operand:SI 2 "" ""))])
3838 (and:SI (match_dup 0)
3839 (match_operand:SI 3 "const_int_operand" "")))]
3840 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
3842 (and:SI (match_dup 0)
3846 (ashift:SI (match_dup 0)
3848 (clobber (match_dup 2))])]
3851 ;; Convert a QImode push into an SImode push so that the
3852 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3855 [(parallel [(set (reg:SI SP_REG)
3856 (plus:SI (reg:SI SP_REG) (const_int -4)))
3857 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
3858 (match_operand:QI 0 "register_operand" ""))])]
3859 "TARGET_H8300S && !TARGET_NORMAL_MODE"
3860 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3862 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3865 [(parallel [(set (reg:HI SP_REG)
3866 (plus:HI (reg:HI SP_REG) (const_int -4)))
3867 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
3868 (match_operand:QI 0 "register_operand" ""))])]
3869 "TARGET_H8300S && TARGET_NORMAL_MODE"
3870 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3872 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3874 ;; Convert a HImode push into an SImode push so that the
3875 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3878 [(parallel [(set (reg:SI SP_REG)
3879 (plus:SI (reg:SI SP_REG) (const_int -4)))
3880 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
3881 (match_operand:HI 0 "register_operand" ""))])]
3882 "TARGET_H8300S && !TARGET_NORMAL_MODE"
3883 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3885 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3888 [(parallel [(set (reg:HI SP_REG)
3889 (plus:HI (reg:HI SP_REG) (const_int -4)))
3890 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
3891 (match_operand:HI 0 "register_operand" ""))])]
3892 "TARGET_H8300S && TARGET_NORMAL_MODE"
3893 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3895 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3897 ;; Cram four pushes into stm.l.
3900 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3901 (match_operand:SI 0 "register_operand" ""))
3902 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3903 (match_operand:SI 1 "register_operand" ""))
3904 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3905 (match_operand:SI 2 "register_operand" ""))
3906 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3907 (match_operand:SI 3 "register_operand" ""))]
3908 "TARGET_H8300S && !TARGET_NORMAL_MODE
3909 && REGNO (operands[0]) == 0
3910 && REGNO (operands[1]) == 1
3911 && REGNO (operands[2]) == 2
3912 && REGNO (operands[3]) == 3"
3913 [(parallel [(set (reg:SI SP_REG)
3914 (plus:SI (reg:SI SP_REG)
3916 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3918 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3920 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3922 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
3927 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3928 (match_operand:SI 0 "register_operand" ""))
3929 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3930 (match_operand:SI 1 "register_operand" ""))
3931 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3932 (match_operand:SI 2 "register_operand" ""))
3933 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3934 (match_operand:SI 3 "register_operand" ""))]
3935 "TARGET_H8300S && TARGET_NORMAL_MODE
3936 && REGNO (operands[0]) == 0
3937 && REGNO (operands[1]) == 1
3938 && REGNO (operands[2]) == 2
3939 && REGNO (operands[3]) == 3"
3940 [(parallel [(set (reg:HI SP_REG)
3941 (plus:HI (reg:HI SP_REG)
3943 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
3945 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
3947 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
3949 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
3953 ;; Cram three pushes into stm.l.
3956 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3957 (match_operand:SI 0 "register_operand" ""))
3958 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3959 (match_operand:SI 1 "register_operand" ""))
3960 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3961 (match_operand:SI 2 "register_operand" ""))]
3962 "TARGET_H8300S && !TARGET_NORMAL_MODE
3963 && ((REGNO (operands[0]) == 0
3964 && REGNO (operands[1]) == 1
3965 && REGNO (operands[2]) == 2)
3966 || (REGNO (operands[0]) == 4
3967 && REGNO (operands[1]) == 5
3968 && REGNO (operands[2]) == 6))"
3969 [(parallel [(set (reg:SI SP_REG)
3970 (plus:SI (reg:SI SP_REG)
3972 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3974 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3976 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3981 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3982 (match_operand:SI 0 "register_operand" ""))
3983 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3984 (match_operand:SI 1 "register_operand" ""))
3985 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3986 (match_operand:SI 2 "register_operand" ""))]
3987 "TARGET_H8300S && TARGET_NORMAL_MODE
3988 && ((REGNO (operands[0]) == 0
3989 && REGNO (operands[1]) == 1
3990 && REGNO (operands[2]) == 2)
3991 || (REGNO (operands[0]) == 4
3992 && REGNO (operands[1]) == 5
3993 && REGNO (operands[2]) == 6))"
3994 [(parallel [(set (reg:HI SP_REG)
3995 (plus:HI (reg:HI SP_REG)
3997 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
3999 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4001 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4005 ;; Cram two pushes into stm.l.
4008 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4009 (match_operand:SI 0 "register_operand" ""))
4010 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4011 (match_operand:SI 1 "register_operand" ""))]
4012 "TARGET_H8300S && !TARGET_NORMAL_MODE
4013 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
4014 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
4015 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
4016 [(parallel [(set (reg:SI SP_REG)
4017 (plus:SI (reg:SI SP_REG)
4019 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4021 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4026 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4027 (match_operand:SI 0 "register_operand" ""))
4028 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4029 (match_operand:SI 1 "register_operand" ""))]
4030 "TARGET_H8300S && TARGET_NORMAL_MODE
4031 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
4032 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
4033 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
4034 [(parallel [(set (reg:HI SP_REG)
4035 (plus:HI (reg:HI SP_REG)
4037 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4039 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4046 ;; add.w r7,r0 (6 bytes)
4051 ;; adds #2,r0 (4 bytes)
4054 [(set (match_operand:HI 0 "register_operand" "")
4055 (match_operand:HI 1 "const_int_operand" ""))
4057 (plus:HI (match_dup 0)
4058 (match_operand:HI 2 "register_operand" "")))]
4059 "REG_P (operands[0]) && REG_P (operands[2])
4060 && REGNO (operands[0]) != REGNO (operands[2])
4061 && (CONST_OK_FOR_J (INTVAL (operands[1]))
4062 || CONST_OK_FOR_L (INTVAL (operands[1]))
4063 || CONST_OK_FOR_N (INTVAL (operands[1])))"
4067 (plus:HI (match_dup 0)
4075 ;; add.l er7,er0 (6 bytes)
4080 ;; adds #4,er0 (4 bytes)
4083 [(set (match_operand:SI 0 "register_operand" "")
4084 (match_operand:SI 1 "const_int_operand" ""))
4086 (plus:SI (match_dup 0)
4087 (match_operand:SI 2 "register_operand" "")))]
4088 "(TARGET_H8300H || TARGET_H8300S)
4089 && REG_P (operands[0]) && REG_P (operands[2])
4090 && REGNO (operands[0]) != REGNO (operands[2])
4091 && (CONST_OK_FOR_L (INTVAL (operands[1]))
4092 || CONST_OK_FOR_N (INTVAL (operands[1])))"
4096 (plus:SI (match_dup 0)
4103 ;; add.l #10,er0 (takes 8 bytes)
4109 ;; add.l er7,er0 (takes 6 bytes)
4112 [(set (match_operand:SI 0 "register_operand" "")
4113 (match_operand:SI 1 "register_operand" ""))
4115 (plus:SI (match_dup 0)
4116 (match_operand:SI 2 "const_int_operand" "")))]
4117 "(TARGET_H8300H || TARGET_H8300S)
4118 && REG_P (operands[0]) && REG_P (operands[1])
4119 && REGNO (operands[0]) != REGNO (operands[1])
4120 && !CONST_OK_FOR_L (INTVAL (operands[2]))
4121 && !CONST_OK_FOR_N (INTVAL (operands[2]))
4122 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
4123 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
4124 || INTVAL (operands[2]) == 0xffff
4125 || INTVAL (operands[2]) == 0xfffe)"
4129 (plus:SI (match_dup 0)
4145 [(set (match_operand:HI 0 "register_operand" "")
4146 (plus:HI (match_dup 0)
4147 (match_operand 1 "incdec_operand" "")))
4151 (if_then_else (match_operator 3 "eqne_operator"
4152 [(cc0) (const_int 0)])
4153 (label_ref (match_operand 2 "" ""))
4155 "TARGET_H8300H || TARGET_H8300S"
4156 [(set (match_operand:HI 0 "register_operand" "")
4157 (unspec:HI [(match_dup 0)
4163 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4164 (label_ref (match_dup 2))
4168 ;; The SImode version of the previous pattern.
4171 [(set (match_operand:SI 0 "register_operand" "")
4172 (plus:SI (match_dup 0)
4173 (match_operand 1 "incdec_operand" "")))
4177 (if_then_else (match_operator 3 "eqne_operator"
4178 [(cc0) (const_int 0)])
4179 (label_ref (match_operand 2 "" ""))
4181 "TARGET_H8300H || TARGET_H8300S"
4182 [(set (match_operand:SI 0 "register_operand" "")
4183 (unspec:SI [(match_dup 0)
4189 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4190 (label_ref (match_dup 2))
4195 [(parallel [(set (cc0)
4196 (zero_extract:SI (match_operand:QI 0 "register_operand" "")
4199 (clobber (scratch:QI))])
4201 (if_then_else (match_operator 1 "eqne_operator"
4202 [(cc0) (const_int 0)])
4203 (label_ref (match_operand 2 "" ""))
4205 "(TARGET_H8300H || TARGET_H8300S)"
4209 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4210 (label_ref (match_dup 2))
4212 "operands[3] = ((GET_CODE (operands[1]) == EQ)
4213 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
4214 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));")
4216 ;; The next three peephole2's will try to transform
4218 ;; mov.b A,r0l (or mov.l A,er0)
4225 ;; and.b #CST,r0l (if CST is not 255)
4228 [(set (match_operand:QI 0 "register_operand" "")
4229 (match_operand:QI 1 "general_operand" ""))
4230 (set (match_operand:SI 2 "register_operand" "")
4231 (and:SI (match_dup 2)
4233 "(TARGET_H8300H || TARGET_H8300S)
4234 && !reg_overlap_mentioned_p (operands[2], operands[1])
4235 && REGNO (operands[0]) == REGNO (operands[2])"
4238 (set (strict_low_part (match_dup 0))
4243 [(set (match_operand:SI 0 "register_operand" "")
4244 (match_operand:SI 1 "general_operand" ""))
4246 (and:SI (match_dup 0)
4248 "(TARGET_H8300H || TARGET_H8300S)
4249 && !reg_overlap_mentioned_p (operands[0], operands[1])
4250 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
4253 (set (strict_low_part (match_dup 2))
4255 "operands[2] = gen_lowpart (QImode, operands[0]);
4256 operands[3] = gen_lowpart (QImode, operands[1]);")
4259 [(set (match_operand 0 "register_operand" "")
4260 (match_operand 1 "general_operand" ""))
4261 (set (match_operand:SI 2 "register_operand" "")
4262 (and:SI (match_dup 2)
4263 (match_operand:SI 3 "const_int_qi_operand" "")))]
4264 "(TARGET_H8300H || TARGET_H8300S)
4265 && (GET_MODE (operands[0]) == QImode
4266 || GET_MODE (operands[0]) == HImode
4267 || GET_MODE (operands[0]) == SImode)
4268 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4269 && REGNO (operands[0]) == REGNO (operands[2])
4270 && !reg_overlap_mentioned_p (operands[2], operands[1])
4271 && !(GET_MODE (operands[1]) != QImode
4272 && GET_CODE (operands[1]) == MEM
4273 && MEM_VOLATILE_P (operands[1]))"
4276 (set (strict_low_part (match_dup 4))
4279 (and:SI (match_dup 2)
4281 "operands[4] = gen_lowpart (QImode, operands[0]);
4282 operands[5] = gen_lowpart (QImode, operands[1]);
4283 operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));")
4286 [(set (match_operand:SI 0 "register_operand" "")
4287 (match_operand:SI 1 "register_operand" ""))
4289 (and:SI (match_dup 0)
4290 (const_int 65280)))]
4291 "(TARGET_H8300H || TARGET_H8300S)
4292 && !reg_overlap_mentioned_p (operands[0], operands[1])"
4295 (set (zero_extract:SI (match_dup 0)
4298 (lshiftrt:SI (match_dup 1)
4302 ;; If a load of mem:SI is followed by an AND that turns off the upper
4303 ;; half, then we can load mem:HI instead.
4306 [(set (match_operand:SI 0 "register_operand" "")
4307 (match_operand:SI 1 "memory_operand" ""))
4309 (and:SI (match_dup 0)
4310 (match_operand:SI 2 "const_int_operand" "")))]
4311 "(TARGET_H8300H || TARGET_H8300S)
4312 && !MEM_VOLATILE_P (operands[1])
4313 && (INTVAL (operands[2]) & ~0xffff) == 0
4314 && INTVAL (operands[2]) != 255"
4318 (and:SI (match_dup 0)
4320 "operands[3] = gen_lowpart (HImode, operands[0]);
4321 operands[4] = gen_lowpart (HImode, operands[1]);")
4323 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
4324 ;; the equivalent with shorter sequences. Here is the summary. Cases
4325 ;; are grouped for each define_peephole2.
4327 ;; reg const_int use insn
4328 ;; --------------------------------------------------------
4329 ;; dead -2 eq/ne inc.l
4330 ;; dead -1 eq/ne inc.l
4331 ;; dead 1 eq/ne dec.l
4332 ;; dead 2 eq/ne dec.l
4334 ;; dead 1 geu/ltu shar.l
4335 ;; dead 3 (H8S) geu/ltu shar.l
4337 ;; ---- 255 geu/ltu mov.b
4351 (compare (match_operand:HI 0 "register_operand" "")
4352 (match_operand:HI 1 "incdec_operand" "")))
4354 (if_then_else (match_operator 3 "eqne_operator"
4355 [(cc0) (const_int 0)])
4356 (label_ref (match_operand 2 "" ""))
4358 "(TARGET_H8300H || TARGET_H8300S)
4359 && peep2_reg_dead_p (1, operands[0])"
4361 (unspec:HI [(match_dup 0)
4367 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4368 (label_ref (match_dup 2))
4370 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4384 (compare (match_operand:HI 0 "register_operand" "")
4385 (match_operand:HI 1 "const_int_operand" "")))
4387 (if_then_else (match_operator 2 "gtle_operator"
4388 [(cc0) (const_int 0)])
4389 (label_ref (match_operand 3 "" ""))
4391 "(TARGET_H8300H || TARGET_H8300S)
4392 && peep2_reg_dead_p (1, operands[0])
4393 && (INTVAL (operands[1]) == 1
4394 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4395 [(parallel [(set (match_dup 0)
4396 (ashiftrt:HI (match_dup 0)
4398 (clobber (scratch:QI))])
4402 (if_then_else (match_dup 4)
4403 (label_ref (match_dup 3))
4405 "switch (GET_CODE (operands[2]))
4408 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4411 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4414 operands[4] = operands[2];
4417 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4431 (compare (match_operand:HI 0 "register_operand" "")
4434 (if_then_else (match_operator 1 "gtle_operator"
4435 [(cc0) (const_int 0)])
4436 (label_ref (match_operand 2 "" ""))
4438 "TARGET_H8300H || TARGET_H8300S"
4440 (and:HI (match_dup 0)
4443 (if_then_else (match_dup 3)
4444 (label_ref (match_dup 2))
4446 "switch (GET_CODE (operands[1]))
4449 operands[3] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4452 operands[3] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4455 operands[3] = operands[1];
4459 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
4460 ;; the equivalent with shorter sequences. Here is the summary. Cases
4461 ;; are grouped for each define_peephole2.
4463 ;; reg const_int use insn
4464 ;; --------------------------------------------------------
4465 ;; live -2 eq/ne copy and inc.l
4466 ;; live -1 eq/ne copy and inc.l
4467 ;; live 1 eq/ne copy and dec.l
4468 ;; live 2 eq/ne copy and dec.l
4470 ;; dead -2 eq/ne inc.l
4471 ;; dead -1 eq/ne inc.l
4472 ;; dead 1 eq/ne dec.l
4473 ;; dead 2 eq/ne dec.l
4475 ;; dead -131072 eq/ne inc.w and test
4476 ;; dead -65536 eq/ne inc.w and test
4477 ;; dead 65536 eq/ne dec.w and test
4478 ;; dead 131072 eq/ne dec.w and test
4480 ;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
4481 ;; dead 0x0000??00 eq/ne xor.b and test
4482 ;; dead 0x0000ffff eq/ne not.w and test
4484 ;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
4485 ;; dead 0xffff??ff eq/ne xor.b and not.l
4486 ;; dead 0x40000000 (H8S) eq/ne rotl.l and dec.l
4487 ;; dead 0x80000000 eq/ne rotl.l and dec.l
4489 ;; live 1 geu/ltu copy and shar.l
4490 ;; live 3 (H8S) geu/ltu copy and shar.l
4492 ;; dead 1 geu/ltu shar.l
4493 ;; dead 3 (H8S) geu/ltu shar.l
4495 ;; dead 3 (H8/300H) geu/ltu and.b and test
4496 ;; dead 7 geu/ltu and.b and test
4497 ;; dead 15 geu/ltu and.b and test
4498 ;; dead 31 geu/ltu and.b and test
4499 ;; dead 63 geu/ltu and.b and test
4500 ;; dead 127 geu/ltu and.b and test
4501 ;; dead 255 geu/ltu and.b and test
4503 ;; ---- 65535 geu/ltu mov.w
4505 ;; For a small constant, it is cheaper to actually do the subtraction
4506 ;; and then test the register.
4510 (compare (match_operand:SI 0 "register_operand" "")
4511 (match_operand:SI 1 "incdec_operand" "")))
4513 (if_then_else (match_operator 3 "eqne_operator"
4514 [(cc0) (const_int 0)])
4515 (label_ref (match_operand 2 "" ""))
4517 "(TARGET_H8300H || TARGET_H8300S)
4518 && peep2_reg_dead_p (1, operands[0])"
4520 (unspec:SI [(match_dup 0)
4526 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4527 (label_ref (match_dup 2))
4529 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4533 (compare (match_operand:SI 0 "register_operand" "")
4534 (match_operand:SI 1 "const_int_operand" "")))
4536 (if_then_else (match_operator 3 "eqne_operator"
4537 [(cc0) (const_int 0)])
4538 (label_ref (match_operand 2 "" ""))
4540 "(TARGET_H8300H || TARGET_H8300S)
4541 && peep2_reg_dead_p (1, operands[0])
4542 && (INTVAL (operands[1]) == -131072
4543 || INTVAL (operands[1]) == -65536
4544 || INTVAL (operands[1]) == 65536
4545 || INTVAL (operands[1]) == 131072)"
4547 (plus:SI (match_dup 0)
4552 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4553 (label_ref (match_dup 2))
4555 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4557 ;; For certain (in)equality comparisons against a constant, we can
4558 ;; XOR the register with the constant, and test the register against
4563 (compare (match_operand:SI 0 "register_operand" "")
4564 (match_operand:SI 1 "const_int_operand" "")))
4566 (if_then_else (match_operator 3 "eqne_operator"
4567 [(cc0) (const_int 0)])
4568 (label_ref (match_operand 2 "" ""))
4570 "(TARGET_H8300H || TARGET_H8300S)
4571 && peep2_reg_dead_p (1, operands[0])
4572 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
4573 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
4574 || INTVAL (operands[1]) == 0x0000ffff)
4575 && INTVAL (operands[1]) != 1
4576 && INTVAL (operands[1]) != 2"
4578 (xor:SI (match_dup 0)
4583 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4584 (label_ref (match_dup 2))
4590 (compare (match_operand:SI 0 "register_operand" "")
4591 (match_operand:SI 1 "const_int_operand" "")))
4593 (if_then_else (match_operator 3 "eqne_operator"
4594 [(cc0) (const_int 0)])
4595 (label_ref (match_operand 2 "" ""))
4597 "(TARGET_H8300H || TARGET_H8300S)
4598 && peep2_reg_dead_p (1, operands[0])
4599 && ((INTVAL (operands[1]) | 0x00ff) == -1
4600 || (INTVAL (operands[1]) | 0xff00) == -1)
4601 && INTVAL (operands[1]) != -1
4602 && INTVAL (operands[1]) != -2"
4604 (xor:SI (match_dup 0)
4607 (not:SI (match_dup 0)))
4611 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4612 (label_ref (match_dup 2))
4614 "operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);")
4618 (compare (match_operand:SI 0 "register_operand" "")
4619 (match_operand:SI 1 "const_int_operand" "")))
4621 (if_then_else (match_operator 3 "eqne_operator"
4622 [(cc0) (const_int 0)])
4623 (label_ref (match_operand 2 "" ""))
4625 "(TARGET_H8300H || TARGET_H8300S)
4626 && peep2_reg_dead_p (1, operands[0])
4627 && (INTVAL (operands[1]) == -2147483647 - 1
4628 || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
4630 (rotate:SI (match_dup 0)
4633 (unspec:SI [(match_dup 0)
4639 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4640 (label_ref (match_dup 2))
4642 "operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2);")
4655 ;; We avoid this transformation if we see more than one copy of the
4656 ;; same compare insn immediately before this one.
4659 [(match_scratch:SI 4 "r")
4661 (compare (match_operand:SI 0 "register_operand" "")
4662 (match_operand:SI 1 "const_int_operand" "")))
4664 (if_then_else (match_operator 2 "gtle_operator"
4665 [(cc0) (const_int 0)])
4666 (label_ref (match_operand 3 "" ""))
4668 "(TARGET_H8300H || TARGET_H8300S)
4669 && !peep2_reg_dead_p (1, operands[0])
4670 && (INTVAL (operands[1]) == 1
4671 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
4672 && !same_cmp_preceding_p (insn)"
4675 (parallel [(set (match_dup 4)
4676 (ashiftrt:SI (match_dup 4)
4678 (clobber (scratch:QI))])
4682 (if_then_else (match_dup 5)
4683 (label_ref (match_dup 3))
4685 "switch (GET_CODE (operands[2]))
4688 operands[5] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4691 operands[5] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4694 operands[5] = operands[2];
4697 operands[6] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4711 (compare (match_operand:SI 0 "register_operand" "")
4712 (match_operand:SI 1 "const_int_operand" "")))
4714 (if_then_else (match_operator 2 "gtle_operator"
4715 [(cc0) (const_int 0)])
4716 (label_ref (match_operand 3 "" ""))
4718 "(TARGET_H8300H || TARGET_H8300S)
4719 && peep2_reg_dead_p (1, operands[0])
4720 && (INTVAL (operands[1]) == 1
4721 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4722 [(parallel [(set (match_dup 0)
4723 (ashiftrt:SI (match_dup 0)
4725 (clobber (scratch:QI))])
4729 (if_then_else (match_dup 4)
4730 (label_ref (match_dup 3))
4732 "switch (GET_CODE (operands[2]))
4735 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4738 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4741 operands[4] = operands[2];
4744 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4759 (compare (match_operand:SI 0 "register_operand" "")
4760 (match_operand:SI 1 "const_int_operand" "")))
4762 (if_then_else (match_operator 2 "gtle_operator"
4763 [(cc0) (const_int 0)])
4764 (label_ref (match_operand 3 "" ""))
4766 "(TARGET_H8300H || TARGET_H8300S)
4767 && peep2_reg_dead_p (1, operands[0])
4768 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
4769 || INTVAL (operands[1]) == 7
4770 || INTVAL (operands[1]) == 15
4771 || INTVAL (operands[1]) == 31
4772 || INTVAL (operands[1]) == 63
4773 || INTVAL (operands[1]) == 127
4774 || INTVAL (operands[1]) == 255)"
4776 (and:SI (match_dup 0)
4781 (if_then_else (match_dup 4)
4782 (label_ref (match_dup 3))
4784 "switch (GET_CODE (operands[2]))
4787 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4790 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4793 operands[4] = operands[2];
4796 operands[5] = GEN_INT (~INTVAL (operands[1]));")
4798 ;; Transform A <= 65535 to (A & 0xffff0000) == 0.
4802 (compare (match_operand:SI 0 "register_operand" "")
4805 (if_then_else (match_operator 1 "gtle_operator"
4806 [(cc0) (const_int 0)])
4807 (label_ref (match_operand 2 "" ""))
4809 "TARGET_H8300H || TARGET_H8300S"
4811 (and:SI (match_dup 0)
4812 (const_int -65536)))
4814 (if_then_else (match_dup 3)
4815 (label_ref (match_dup 2))
4817 "switch (GET_CODE (operands[1]))
4820 operands[3] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4823 operands[3] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4826 operands[3] = operands[1];
4830 ;; For constants like -1, -2, 1, 2, it is still cheaper to make a copy
4831 ;; of the register being tested, do the subtraction on the copy, and
4832 ;; then test the copy. We avoid this transformation if we see more
4833 ;; than one copy of the same compare insn.
4836 [(match_scratch:SI 4 "r")
4838 (compare (match_operand:SI 0 "register_operand" "")
4839 (match_operand:SI 1 "incdec_operand" "")))
4841 (if_then_else (match_operator 3 "eqne_operator"
4842 [(cc0) (const_int 0)])
4843 (label_ref (match_operand 2 "" ""))
4845 "(TARGET_H8300H || TARGET_H8300S)
4846 && !peep2_reg_dead_p (1, operands[0])
4847 && !same_cmp_following_p (insn)"
4851 (unspec:SI [(match_dup 4)
4857 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4858 (label_ref (match_dup 2))
4860 "operands[5] = GEN_INT (- INTVAL (operands[1]));")
4862 ;; Narrow the mode of testing if possible.
4865 [(set (match_operand:HI 0 "register_operand" "")
4866 (and:HI (match_dup 0)
4867 (match_operand:HI 1 "const_int_qi_operand" "")))
4871 (if_then_else (match_operator 3 "eqne_operator"
4872 [(cc0) (const_int 0)])
4873 (label_ref (match_operand 2 "" ""))
4875 "peep2_reg_dead_p (2, operands[0])"
4877 (and:QI (match_dup 4)
4882 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4883 (label_ref (match_dup 2))
4885 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
4886 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
4889 [(set (match_operand:SI 0 "register_operand" "")
4890 (and:SI (match_dup 0)
4891 (match_operand:SI 1 "const_int_qi_operand" "")))
4895 (if_then_else (match_operator 3 "eqne_operator"
4896 [(cc0) (const_int 0)])
4897 (label_ref (match_operand 2 "" ""))
4899 "peep2_reg_dead_p (2, operands[0])"
4901 (and:QI (match_dup 4)
4906 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4907 (label_ref (match_dup 2))
4909 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
4910 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
4913 [(set (match_operand:SI 0 "register_operand" "")
4914 (and:SI (match_dup 0)
4915 (match_operand:SI 1 "const_int_hi_operand" "")))
4919 (if_then_else (match_operator 3 "eqne_operator"
4920 [(cc0) (const_int 0)])
4921 (label_ref (match_operand 2 "" ""))
4923 "peep2_reg_dead_p (2, operands[0])"
4925 (and:HI (match_dup 4)
4930 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4931 (label_ref (match_dup 2))
4933 "operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
4934 operands[5] = gen_int_mode (INTVAL (operands[1]), HImode);")
4937 [(set (match_operand:SI 0 "register_operand" "")
4938 (and:SI (match_dup 0)
4939 (match_operand:SI 1 "const_int_qi_operand" "")))
4941 (xor:SI (match_dup 0)
4942 (match_operand:SI 2 "const_int_qi_operand" "")))
4946 (if_then_else (match_operator 4 "eqne_operator"
4947 [(cc0) (const_int 0)])
4948 (label_ref (match_operand 3 "" ""))
4950 "peep2_reg_dead_p (3, operands[0])
4951 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
4953 (and:QI (match_dup 5)
4956 (xor:QI (match_dup 5)
4961 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
4962 (label_ref (match_dup 3))
4964 "operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
4965 operands[6] = gen_int_mode (INTVAL (operands[1]), QImode);
4966 operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);")