gcc/config/h8300/h8300.md

   1 ;; GCC machine description for Renesas H8/300
   2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
   3 ;; 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
   4
   5 ;;   Contributed by Steve Chamberlain (sac@cygnus.com),
   6 ;;   Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
   7
   8 ;; This file is part of GCC.
   9
  10 ;; GCC is free software; you can redistribute it and/or modify
  11 ;; it under the terms of the GNU General Public License as published by
  12 ;; the Free Software Foundation; either version 2, or (at your option)
  13 ;; any later version.
  14
  15 ;; GCC is distributed in the hope that it will be useful,
  16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 ;; GNU General Public License for more details.
  19
  20 ;; You should have received a copy of the GNU General Public License
  21 ;; along with GCC; see the file COPYING.  If not, write to
  22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
  23 ;; Boston, MA 02111-1307, USA.
  24
  25 ;; We compute exact length on each instruction for most of the time.
  26 ;; In some case, most notably bit operations that may involve memory
  27 ;; operands, the lengths in this file are "worst case".
  28
  29 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
  30 ;; registers.  Right now GCC doesn't expose the "e" half to the
  31 ;; compiler, so using add/subs for addhi and subhi is safe.  Long
  32 ;; term, we want to expose the "e" half to the compiler (gives us 8
  33 ;; more 16bit registers).  At that point addhi and subhi can't use
  34 ;; adds/subs.
  35
  36 ;; There's currently no way to have an insv/extzv expander for the H8/300H
  37 ;; because word_mode is different for the H8/300 and H8/300H.
  38
  39 ;; Shifts/rotates by small constants should be handled by special
  40 ;; patterns so we get the length and cc status correct.
  41
  42 ;; Bitfield operations no longer accept memory operands.  We need
  43 ;; to add variants which operate on memory back to the MD.
  44
  45 ;; ??? Implement remaining bit ops available on the h8300
  46
  47 ;; ----------------------------------------------------------------------
  48 ;; CONSTANTS
  49 ;; ----------------------------------------------------------------------
  50
  51 (define_constants
  52   [(UNSPEC_INCDEC       0)
  53    (UNSPEC_MONITOR      1)])
  54
  55 (define_constants
  56   [(R0_REG       0)
  57    (SC_REG       3)
  58    (HFP_REG      6)
  59    (SP_REG       7)
  60    (MAC_REG      8)
  61    (AP_REG       9)
  62    (RAP_REG     10)
  63    (FP_REG      11)])
  64
  65 ;; ----------------------------------------------------------------------
  66 ;; ATTRIBUTES
  67 ;; ----------------------------------------------------------------------
  68
  69 (define_attr "cpu" "h8300,h8300h"
  70   (const (symbol_ref "cpu_type")))
  71
  72 (define_attr "type" "branch,arith"
  73   (const_string "arith"))
  74
  75 ;; The size of instructions in bytes.
  76
  77 (define_attr "length" ""
  78   (cond [(eq_attr "type" "branch")
  79          (if_then_else (and (ge (minus (match_dup 0) (pc))
  80                                 (const_int -126))
  81                             (le (minus (match_dup 0) (pc))
  82                                 (const_int 126)))
  83                        (const_int 2)
  84                        (if_then_else (and (eq_attr "cpu" "h8300h")
  85                                           (and (ge (minus (pc) (match_dup 0))
  86                                                    (const_int -32000))
  87                                                (le (minus (pc) (match_dup 0))
  88                                                    (const_int 32000))))
  89                                      (const_int 4)
  90                                      (const_int 6)))]
  91         (const_int 200)))
  92
  93 ;; Condition code settings.
  94 ;;
  95 ;; none - insn does not affect cc
  96 ;; none_0hit - insn does not affect cc but it does modify operand 0
  97 ;;      This attribute is used to keep track of when operand 0 changes.
  98 ;;      See the description of NOTICE_UPDATE_CC for more info.
  99 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
 100 ;; set_zn  - insn sets z,n to usable values; v,c are unknown.
 101 ;; compare - compare instruction
 102 ;; clobber - value of cc is unknown
 103
 104 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
 105   (const_string "clobber"))
 106
 107 ;; Provide the maximum length of an assembly instruction in an asm
 108 ;; statement.  The maximum length of 14 bytes is achieved on H8SX.
 109
 110 (define_asm_attributes
 111   [(set (attr "length")
 112         (cond [(ne (symbol_ref "TARGET_H8300")  (const_int 0)) (const_int 4)
 113                (ne (symbol_ref "TARGET_H8300H") (const_int 0)) (const_int 10)
 114                (ne (symbol_ref "TARGET_H8300S") (const_int 0)) (const_int 10)]
 115               (const_int 14)))])
 116 \f
 117 ;; ----------------------------------------------------------------------
 118 ;; MOVE INSTRUCTIONS
 119 ;; ----------------------------------------------------------------------
 120
 121 ;; movqi
 122
 123 (define_insn "*movqi_h8300"
 124   [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
 125         (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
 126   "TARGET_H8300
 127    && (register_operand (operands[0], QImode)
 128        || register_operand (operands[1], QImode))"
 129   "@
 130    sub.b        %X0,%X0
 131    mov.b        %R1,%X0
 132    mov.b        %X1,%R0
 133    mov.b        %R1,%X0
 134    mov.b        %R1,%X0
 135    mov.b        %X1,%R0"
 136   [(set_attr "length" "2,2,2,2,4,4")
 137    (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
 138
 139 (define_insn "*movqi_h8300hs"
 140   [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
 141         (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
 142   "(TARGET_H8300H || TARGET_H8300S)
 143    && (register_operand (operands[0], QImode)
 144        || register_operand (operands[1], QImode))"
 145   "@
 146    sub.b        %X0,%X0
 147    mov.b        %R1,%X0
 148    mov.b        %X1,%R0
 149    mov.b        %R1,%X0
 150    mov.b        %R1,%X0
 151    mov.b        %X1,%R0"
 152   [(set (attr "length")
 153         (symbol_ref "compute_mov_length (operands)"))
 154    (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
 155
 156 (define_expand "movqi"
 157   [(set (match_operand:QI 0 "general_operand_dst" "")
 158         (match_operand:QI 1 "general_operand_src" ""))]
 159   ""
 160   "
 161 {
 162   /* One of the ops has to be in a register.  */
 163   if (!register_operand (operand0, QImode)
 164       && !register_operand (operand1, QImode))
 165     {
 166       operands[1] = copy_to_mode_reg (QImode, operand1);
 167     }
 168 }")
 169
 170 (define_insn "movstrictqi"
 171   [(set (strict_low_part
 172          (match_operand:QI 0 "register_operand"    "+r,r,r,r,r"))
 173          (match_operand:QI 1 "general_operand_src" " I,r,n,>,m"))]
 174   ""
 175   "@
 176    sub.b        %X0,%X0
 177    mov.b        %X1,%X0
 178    mov.b        %R1,%X0
 179    mov.b        %X1,%X0
 180    mov.b        %R1,%X0"
 181   [(set (attr "length")
 182         (symbol_ref "compute_mov_length (operands)"))
 183    (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
 184
 185 ;; movhi
 186
 187 (define_insn "*movhi_h8300"
 188   [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
 189         (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
 190   "TARGET_H8300
 191    && (register_operand (operands[0], HImode)
 192        || register_operand (operands[1], HImode))
 193    && !(GET_CODE (operands[0]) == MEM
 194         && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
 195         && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
 196         && GET_CODE (operands[1]) == REG
 197         && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
 198   "@
 199    sub.w        %T0,%T0
 200    mov.w        %T1,%T0
 201    mov.w        %T1,%T0
 202    mov.w        %T1,%T0
 203    mov.w        %T1,%T0
 204    mov.w        %T1,%T0"
 205   [(set (attr "length")
 206         (symbol_ref "compute_mov_length (operands)"))
 207    (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
 208
 209 (define_insn "*movhi_h8300hs"
 210   [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
 211         (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
 212   "(TARGET_H8300H || TARGET_H8300S)
 213    && (register_operand (operands[0], HImode)
 214        || register_operand (operands[1], HImode))"
 215   "@
 216    sub.w        %T0,%T0
 217    mov.w        %T1,%T0
 218    mov.w        %T1,%T0
 219    mov.w        %T1,%T0
 220    mov.w        %T1,%T0
 221    mov.w        %T1,%T0"
 222   [(set (attr "length")
 223         (symbol_ref "compute_mov_length (operands)"))
 224    (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
 225
 226 (define_expand "movhi"
 227   [(set (match_operand:HI 0 "general_operand_dst" "")
 228         (match_operand:HI 1 "general_operand_src" ""))]
 229   ""
 230   "
 231 {
 232   /* One of the ops has to be in a register.  */
 233   if (!register_operand (operand1, HImode)
 234       && !register_operand (operand0, HImode))
 235     {
 236       operands[1] = copy_to_mode_reg (HImode, operand1);
 237     }
 238 }")
 239
 240 (define_insn "movstricthi"
 241   [(set (strict_low_part
 242          (match_operand:HI 0 "register_operand"    "+r,r,r,r,r"))
 243          (match_operand:HI 1 "general_operand_src" " I,r,i,>,m"))]
 244   ""
 245   "@
 246    sub.w        %T0,%T0
 247    mov.w        %T1,%T0
 248    mov.w        %T1,%T0
 249    mov.w        %T1,%T0
 250    mov.w        %T1,%T0"
 251   [(set (attr "length")
 252         (symbol_ref "compute_mov_length (operands)"))
 253    (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
 254
 255 ;; movsi
 256
 257 (define_expand "movsi"
 258   [(set (match_operand:SI 0 "general_operand_dst" "")
 259         (match_operand:SI 1 "general_operand_src" ""))]
 260   ""
 261   "
 262 {
 263   if (TARGET_H8300)
 264     {
 265       if (h8300_expand_movsi (operands))
 266         DONE;
 267     }
 268   else
 269     {
 270       /* One of the ops has to be in a register.  */
 271       if (!register_operand (operand1, SImode)
 272           && !register_operand (operand0, SImode))
 273         {
 274           operands[1] = copy_to_mode_reg (SImode, operand1);
 275         }
 276     }
 277 }")
 278
 279 (define_insn "*movsi_h8300"
 280   [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
 281         (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
 282   "TARGET_H8300
 283    && (register_operand (operands[0], SImode)
 284        || register_operand (operands[1], SImode))"
 285   "*
 286 {
 287   unsigned int rn = -1;
 288   switch (which_alternative)
 289     {
 290     case 0:
 291       return \"sub.w    %e0,%e0\;sub.w  %f0,%f0\";
 292     case 1:
 293       if (REGNO (operands[0]) < REGNO (operands[1]))
 294         return \"mov.w  %e1,%e0\;mov.w  %f1,%f0\";
 295       else
 296         return \"mov.w  %f1,%f0\;mov.w  %e1,%e0\";
 297     case 2:
 298       /* Make sure we don't trample the register we index with.  */
 299       if (GET_CODE (operands[1]) == MEM)
 300         {
 301           rtx inside = XEXP (operands[1], 0);
 302           if (REG_P (inside))
 303             {
 304               rn = REGNO (inside);
 305             }
 306           else if (GET_CODE (inside) == PLUS)
 307             {
 308               rtx lhs = XEXP (inside, 0);
 309               rtx rhs = XEXP (inside, 1);
 310               if (REG_P (lhs)) rn = REGNO (lhs);
 311               if (REG_P (rhs)) rn = REGNO (rhs);
 312             }
 313         }
 314       if (rn == REGNO (operands[0]))
 315         {
 316           /* Move the second word first.  */
 317           return \"mov.w        %f1,%f0\;mov.w  %e1,%e0\";
 318         }
 319       else
 320         {
 321           if (GET_CODE (operands[1]) == CONST_INT)
 322             {
 323               /* If either half is zero, use sub.w to clear that
 324                  half.  */
 325               if ((INTVAL (operands[1]) & 0xffff) == 0)
 326                 return \"mov.w  %e1,%e0\;sub.w  %f0,%f0\";
 327               if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
 328                 return \"sub.w  %e0,%e0\;mov.w  %f1,%f0\";
 329               /* If the upper half and the lower half are the same,
 330                  copy one half to the other.  */
 331               if ((INTVAL (operands[1]) & 0xffff)
 332                   == ((INTVAL (operands[1]) >> 16) & 0xffff))
 333                 return \"mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0\";
 334             }
 335           return \"mov.w        %e1,%e0\;mov.w  %f1,%f0\";
 336         }
 337     case 3:
 338       return \"mov.w    %e1,%e0\;mov.w  %f1,%f0\";
 339     case 4:
 340       return \"mov.w    %f1,%T0\;mov.w  %e1,%T0\";
 341     case 5:
 342       return \"mov.w    %T1,%e0\;mov.w  %T1,%f0\";
 343     default:
 344       abort ();
 345     }
 346 }"
 347   [(set (attr "length")
 348         (symbol_ref "compute_mov_length (operands)"))])
 349
 350 (define_insn "*movsi_h8300hs"
 351   [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
 352         (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
 353   "(TARGET_H8300S || TARGET_H8300H)
 354    && (register_operand (operands[0], SImode)
 355        || register_operand (operands[1], SImode))
 356    && !(GET_CODE (operands[0]) == MEM
 357         && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
 358         && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
 359         && GET_CODE (operands[1]) == REG
 360         && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
 361   "*
 362 {
 363   switch (which_alternative)
 364     {
 365     case 0:
 366       return \"sub.l    %S0,%S0\";
 367     case 7:
 368       return \"clrmac\";
 369     case 8:
 370       return \"clrmac\;ldmac %1,macl\";
 371     case 9:
 372       return \"stmac    macl,%0\";
 373     default:
 374       if (GET_CODE (operands[1]) == CONST_INT)
 375         {
 376           int val = INTVAL (operands[1]);
 377
 378           /* Look for constants which can be made by adding an 8-bit
 379              number to zero in one of the two low bytes.  */
 380           if (val == (val & 0xff))
 381             {
 382               operands[1] = GEN_INT ((char) val & 0xff);
 383               return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
 384             }
 385
 386           if (val == (val & 0xff00))
 387             {
 388               operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
 389               return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
 390             }
 391
 392           /* Look for constants that can be obtained by subs, inc, and
 393              dec to 0.  */
 394           switch (val & 0xffffffff)
 395             {
 396             case 0xffffffff:
 397               return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
 398             case 0xfffffffe:
 399               return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
 400             case 0xfffffffc:
 401               return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
 402
 403             case 0x0000ffff:
 404               return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
 405             case 0x0000fffe:
 406               return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
 407
 408             case 0xffff0000:
 409               return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
 410             case 0xfffe0000:
 411               return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
 412
 413             case 0x00010000:
 414               return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
 415             case 0x00020000:
 416               return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
 417             }
 418         }
 419     }
 420    return \"mov.l       %S1,%S0\";
 421 }"
 422   [(set (attr "length")
 423         (symbol_ref "compute_mov_length (operands)"))
 424    (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
 425
 426 (define_expand "movsf"
 427   [(set (match_operand:SF 0 "general_operand_dst" "")
 428         (match_operand:SF 1 "general_operand_src" ""))]
 429   ""
 430   "
 431 {
 432   if (TARGET_H8300)
 433     {
 434       if (h8300_expand_movsi (operands))
 435         DONE;
 436     }
 437   else
 438     {
 439       /* One of the ops has to be in a register.  */
 440       if (!register_operand (operand1, SFmode)
 441           && !register_operand (operand0, SFmode))
 442         {
 443           operands[1] = copy_to_mode_reg (SFmode, operand1);
 444         }
 445     }
 446 }")
 447
 448 (define_insn "*movsf_h8300"
 449   [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
 450         (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))]
 451   "TARGET_H8300
 452    && (register_operand (operands[0], SFmode)
 453        || register_operand (operands[1], SFmode))"
 454   "*
 455 {
 456   /* Copy of the movsi stuff.  */
 457   unsigned int rn = -1;
 458   switch (which_alternative)
 459     {
 460     case 0:
 461       return \"sub.w    %e0,%e0\;sub.w  %f0,%f0\";
 462     case 1:
 463       if (REGNO (operands[0]) < REGNO (operands[1]))
 464         return \"mov.w  %e1,%e0\;mov.w  %f1,%f0\";
 465       else
 466         return \"mov.w  %f1,%f0\;mov.w  %e1,%e0\";
 467     case 2:
 468       /* Make sure we don't trample the register we index with.  */
 469       if (GET_CODE (operands[1]) == MEM)
 470         {
 471           rtx inside = XEXP (operands[1], 0);
 472           if (REG_P (inside))
 473             {
 474               rn = REGNO (inside);
 475             }
 476           else if (GET_CODE (inside) == PLUS)
 477             {
 478               rtx lhs = XEXP (inside, 0);
 479               rtx rhs = XEXP (inside, 1);
 480               if (REG_P (lhs)) rn = REGNO (lhs);
 481               if (REG_P (rhs)) rn = REGNO (rhs);
 482             }
 483         }
 484       if (rn == REGNO (operands[0]))
 485         /* Move the second word first.  */
 486         return \"mov.w  %f1,%f0\;mov.w  %e1,%e0\";
 487       else
 488         /* Move the first word first.  */
 489         return \"mov.w  %e1,%e0\;mov.w  %f1,%f0\";
 490
 491     case 3:
 492       return \"mov.w    %e1,%e0\;mov.w  %f1,%f0\";
 493     case 4:
 494       return \"mov.w    %f1,%T0\;mov.w  %e1,%T0\";
 495     case 5:
 496       return \"mov.w    %T1,%e0\;mov.w  %T1,%f0\";
 497     default:
 498       abort ();
 499     }
 500 }"
 501   [(set (attr "length")
 502         (symbol_ref "compute_mov_length (operands)"))])
 503
 504 (define_insn "*movsf_h8300hs"
 505   [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
 506         (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
 507   "(TARGET_H8300H || TARGET_H8300S)
 508    && (register_operand (operands[0], SFmode)
 509        || register_operand (operands[1], SFmode))"
 510   "@
 511    sub.l        %S0,%S0
 512    mov.l        %S1,%S0
 513    mov.l        %S1,%S0
 514    mov.l        %S1,%S0
 515    mov.l        %S1,%S0
 516    mov.l        %S1,%S0"
 517   [(set (attr "length")
 518         (symbol_ref "compute_mov_length (operands)"))
 519    (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
 520 \f
 521 ;; ----------------------------------------------------------------------
 522 ;; PUSH INSTRUCTIONS
 523 ;; ----------------------------------------------------------------------
 524
 525 (define_insn "pushqi1_h8300"
 526   [(set (reg:HI SP_REG)
 527         (plus:HI (reg:HI SP_REG) (const_int -2)))
 528    (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
 529         (match_operand:QI 0 "register_operand" "r"))]
 530   "TARGET_H8300
 531    && operands[0] != stack_pointer_rtx"
 532   "mov.w\\t%T0,@-r7"
 533   [(set_attr "length" "2")])
 534
 535 (define_insn "pushqi1_h8300hs_advanced"
 536   [(set (reg:SI SP_REG)
 537         (plus:SI (reg:SI SP_REG) (const_int -4)))
 538    (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
 539         (match_operand:QI 0 "register_operand" "r"))]
 540   "(TARGET_H8300H || TARGET_H8300S)
 541    && operands[0] != stack_pointer_rtx"
 542   "mov.l\\t%S0,@-er7"
 543   [(set_attr "length" "4")])
 544
 545 (define_insn "pushqi1_h8300hs_normal"
 546   [(set (reg:HI SP_REG)
 547         (plus:HI (reg:HI SP_REG) (const_int -4)))
 548    (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
 549         (match_operand:QI 0 "register_operand" "r"))]
 550   "(TARGET_H8300H || TARGET_H8300S)
 551    && operands[0] != stack_pointer_rtx"
 552   "mov.l\\t%S0,@-er7"
 553   [(set_attr "length" "4")])
 554
 555 (define_expand "pushqi1"
 556   [(match_operand:QI 0 "register_operand" "")]
 557   ""
 558   "
 559 {
 560   if (TARGET_H8300)
 561     emit_insn (gen_pushqi1_h8300 (operands[0]));
 562   else if (!TARGET_NORMAL_MODE)
 563     emit_insn (gen_pushqi1_h8300hs_advanced (operands[0]));
 564   else
 565     emit_insn (gen_pushqi1_h8300hs_normal (operands[0]));
 566   DONE;
 567 }")
 568
 569 (define_expand "pushhi1_h8300"
 570   [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
 571         (match_operand:HI 0 "register_operand" ""))]
 572   "TARGET_H8300
 573    && operands[0] != stack_pointer_rtx"
 574   "")
 575
 576 (define_insn "pushhi1_h8300hs_advanced"
 577   [(set (reg:SI SP_REG)
 578         (plus:SI (reg:SI SP_REG) (const_int -4)))
 579    (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
 580         (match_operand:HI 0 "register_operand" "r"))]
 581   "(TARGET_H8300H || TARGET_H8300S)
 582    && operands[0] != stack_pointer_rtx"
 583   "mov.l\\t%S0,@-er7"
 584   [(set_attr "length" "4")])
 585
 586 (define_insn "pushhi1_h8300hs_normal"
 587   [(set (reg:HI SP_REG)
 588         (plus:HI (reg:HI SP_REG) (const_int -4)))
 589    (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
 590         (match_operand:HI 0 "register_operand" "r"))]
 591   "(TARGET_H8300H || TARGET_H8300S)
 592    && operands[0] != stack_pointer_rtx"
 593   "mov.l\\t%S0,@-er7"
 594   [(set_attr "length" "4")])
 595
 596 (define_expand "pushhi1"
 597   [(match_operand:HI 0 "register_operand" "")]
 598   ""
 599   "
 600 {
 601   if (TARGET_H8300)
 602     emit_insn (gen_pushhi1_h8300 (operands[0]));
 603   else if (!TARGET_NORMAL_MODE)
 604     emit_insn (gen_pushhi1_h8300hs_advanced (operands[0]));
 605   else
 606     emit_insn (gen_pushhi1_h8300hs_normal (operands[0]));
 607   DONE;
 608 }")
 609 \f
 610 ;; ----------------------------------------------------------------------
 611 ;; TEST INSTRUCTIONS
 612 ;; ----------------------------------------------------------------------
 613
 614 (define_insn ""
 615   [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
 616                                (const_int 1)
 617                                (match_operand 1 "const_int_operand" "n,n")))]
 618   "TARGET_H8300"
 619   "btst %Z1,%Y0"
 620   [(set_attr "length" "2,4")
 621    (set_attr "cc" "set_zn,set_zn")])
 622
 623 (define_insn ""
 624   [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
 625                                (const_int 1)
 626                                (match_operand 1 "const_int_operand" "n")))]
 627   "TARGET_H8300"
 628   "btst %Z1,%Y0"
 629   [(set_attr "length" "2")
 630    (set_attr "cc" "set_zn")])
 631
 632 (define_insn_and_split "*tst_extzv_1_n"
 633   [(set (cc0)
 634         (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
 635                          (const_int 1)
 636                          (match_operand 1 "const_int_operand" "n,n,n")))
 637    (clobber (match_scratch:QI 2 "=X,X,&r"))]
 638   "(TARGET_H8300H || TARGET_H8300S)"
 639   "@
 640    btst\\t%Z1,%Y0
 641    btst\\t%Z1,%Y0
 642    #"
 643   "&& reload_completed
 644    && !EXTRA_CONSTRAINT (operands[0], 'U')"
 645   [(set (match_dup 2)
 646         (match_dup 0))
 647    (parallel [(set (cc0) (zero_extract:SI (match_dup 2)
 648                                           (const_int 1)
 649                                           (match_dup 1)))
 650               (clobber (scratch:QI))])]
 651   ""
 652   [(set_attr "length" "2,8,10")
 653    (set_attr "cc" "set_zn,set_zn,set_zn")])
 654
 655 (define_insn ""
 656   [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
 657                                (const_int 1)
 658                                (match_operand 1 "const_int_operand" "n")))]
 659   "(TARGET_H8300H || TARGET_H8300S)
 660    && INTVAL (operands[1]) <= 15"
 661   "btst %Z1,%Y0"
 662   [(set_attr "length" "2")
 663    (set_attr "cc" "set_zn")])
 664
 665 (define_insn_and_split "*tstsi_upper_bit"
 666   [(set (cc0)
 667         (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
 668                          (const_int 1)
 669                          (match_operand 1 "const_int_operand" "n")))
 670    (clobber (match_scratch:SI 2 "=&r"))]
 671   "(TARGET_H8300H || TARGET_H8300S)
 672    && INTVAL (operands[1]) >= 16"
 673   "#"
 674   "&& reload_completed"
 675   [(set (match_dup 2)
 676         (ior:SI (and:SI (match_dup 2)
 677                         (const_int -65536))
 678                 (lshiftrt:SI (match_dup 0)
 679                              (const_int 16))))
 680    (set (cc0)
 681         (zero_extract:SI (match_dup 2)
 682                          (const_int 1)
 683                          (match_dup 3)))]
 684   "operands[3] = GEN_INT (INTVAL (operands[1]) - 16);")
 685
 686 (define_insn "*tstsi_variable_bit"
 687   [(set (cc0)
 688         (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
 689                          (const_int 1)
 690                          (and:SI (match_operand:SI 1 "register_operand" "r")
 691                                  (const_int 7))))]
 692   "TARGET_H8300H || TARGET_H8300S"
 693   "btst %w1,%w0"
 694   [(set_attr "length" "2")
 695    (set_attr "cc" "set_zn")])
 696
 697 (define_insn_and_split "*tstsi_variable_bit_qi"
 698   [(set (cc0)
 699         (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>"))
 700                          (const_int 1)
 701                          (and:SI (match_operand:SI 1 "register_operand" "r,r,r")
 702                                  (const_int 7))))
 703    (clobber (match_scratch:QI 2 "=X,X,&r"))]
 704   "(TARGET_H8300H || TARGET_H8300S)"
 705   "@
 706    btst\\t%w1,%X0
 707    btst\\t%w1,%X0
 708    #"
 709   "&& reload_completed
 710    && !EXTRA_CONSTRAINT (operands[0], 'U')"
 711   [(set (match_dup 2)
 712         (match_dup 0))
 713    (parallel [(set (cc0) (zero_extract:SI (zero_extend:SI (match_dup 2))
 714                                           (const_int 1)
 715                                           (and:SI (match_dup 1)
 716                                                   (const_int 7))))
 717               (clobber (scratch:QI))])]
 718   ""
 719   [(set_attr "length" "2,8,10")
 720    (set_attr "cc" "set_zn,set_zn,set_zn")])
 721
 722 (define_insn "tstqi"
 723   [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
 724   ""
 725   "mov.b        %X0,%X0"
 726   [(set_attr "length" "2")
 727    (set_attr "cc" "set_znv")])
 728
 729 (define_insn "tsthi"
 730   [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
 731   ""
 732   "mov.w        %T0,%T0"
 733   [(set_attr "length" "2")
 734    (set_attr "cc" "set_znv")])
 735
 736 (define_insn "*tsthi_upper"
 737   [(set (cc0)
 738         (and:HI (match_operand:HI 0 "register_operand" "r")
 739                 (const_int -256)))]
 740   ""
 741   "mov.b        %t0,%t0"
 742   [(set_attr "length" "2")
 743    (set_attr "cc" "set_znv")])
 744
 745 (define_insn "tstsi"
 746   [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
 747   "TARGET_H8300H || TARGET_H8300S"
 748   "mov.l        %S0,%S0"
 749   [(set_attr "length" "2")
 750    (set_attr "cc" "set_znv")])
 751
 752 (define_insn "*tstsi_upper"
 753   [(set (cc0)
 754         (and:SI (match_operand:SI 0 "register_operand" "r")
 755                 (const_int -65536)))]
 756   ""
 757   "mov.w        %e0,%e0"
 758   [(set_attr "length" "2")
 759    (set_attr "cc" "set_znv")])
 760
 761 (define_insn "cmpqi"
 762   [(set (cc0)
 763         (compare (match_operand:QI 0 "register_operand" "r")
 764                  (match_operand:QI 1 "nonmemory_operand" "rn")))]
 765   ""
 766   "cmp.b        %X1,%X0"
 767   [(set_attr "length" "2")
 768    (set_attr "cc" "compare")])
 769
 770 (define_expand "cmphi"
 771   [(set (cc0)
 772         (compare (match_operand:HI 0 "register_operand" "")
 773                  (match_operand:HI 1 "nonmemory_operand" "")))]
 774   ""
 775   "
 776 {
 777   /* Force operand1 into a register if we're compiling
 778      for the H8/300.  */
 779   if (GET_CODE (operands[1]) != REG && TARGET_H8300)
 780     operands[1] = force_reg (HImode, operands[1]);
 781 }")
 782
 783 (define_insn "*cmphi_h8300_znvc"
 784   [(set (cc0)
 785         (compare (match_operand:HI 0 "register_operand" "r")
 786                  (match_operand:HI 1 "register_operand" "r")))]
 787   "TARGET_H8300"
 788   "cmp.w        %T1,%T0"
 789   [(set_attr "length" "2")
 790    (set_attr "cc" "compare")])
 791
 792 (define_insn "*cmphi_h8300hs_znvc"
 793   [(set (cc0)
 794         (compare (match_operand:HI 0 "register_operand" "r,r")
 795                  (match_operand:HI 1 "nonmemory_operand" "r,n")))]
 796   "TARGET_H8300H || TARGET_H8300S"
 797   "cmp.w        %T1,%T0"
 798   [(set_attr "length" "2,4")
 799    (set_attr "cc" "compare,compare")])
 800
 801 (define_insn "cmpsi"
 802   [(set (cc0)
 803         (compare (match_operand:SI 0 "register_operand" "r,r")
 804                  (match_operand:SI 1 "nonmemory_operand" "r,i")))]
 805   "TARGET_H8300H || TARGET_H8300S"
 806   "cmp.l        %S1,%S0"
 807   [(set_attr "length" "2,6")
 808    (set_attr "cc" "compare,compare")])
 809 \f
 810 ;; ----------------------------------------------------------------------
 811 ;; ADD INSTRUCTIONS
 812 ;; ----------------------------------------------------------------------
 813
 814 (define_insn "addqi3"
 815   [(set (match_operand:QI 0 "register_operand" "=r")
 816         (plus:QI (match_operand:QI 1 "register_operand" "%0")
 817                  (match_operand:QI 2 "nonmemory_operand" "rn")))]
 818   ""
 819   "add.b        %X2,%X0"
 820   [(set_attr "length" "2")
 821    (set_attr "cc" "set_zn")])
 822
 823 (define_expand "addhi3"
 824   [(set (match_operand:HI 0 "register_operand" "")
 825         (plus:HI (match_operand:HI 1 "register_operand" "")
 826                  (match_operand:HI 2 "nonmemory_operand" "")))]
 827   ""
 828   "")
 829
 830 (define_insn "*addhi3_h8300"
 831   [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
 832         (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
 833                  (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
 834   "TARGET_H8300"
 835   "@
 836    adds %2,%T0
 837    subs %G2,%T0
 838    add.b        %t2,%t0
 839    add.b        %s2,%s0\;addx   %t2,%t0
 840    add.w        %T2,%T0"
 841   [(set_attr "length" "2,2,2,4,2")
 842    (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
 843
 844 ;; This splitter is very important to make the stack adjustment
 845 ;; interrupt-safe.  The combination of add.b and addx is unsafe!
 846 ;;
 847 ;; We apply this split after the peephole2 pass so that we won't end
 848 ;; up creating too many adds/subs when a scratch register is
 849 ;; available, which is actually a common case because stack unrolling
 850 ;; tends to happen immediately after a function call.
 851
 852 (define_split
 853   [(set (match_operand:HI 0 "stack_pointer_operand" "")
 854         (plus:HI (match_dup 0)
 855                  (match_operand 1 "const_int_gt_2_operand" "")))]
 856   "TARGET_H8300 && flow2_completed"
 857   [(const_int 0)]
 858   "split_adds_subs (HImode, operands); DONE;")
 859
 860 (define_peephole2
 861   [(match_scratch:HI 2 "r")
 862    (set (match_operand:HI 0 "stack_pointer_operand" "")
 863         (plus:HI (match_dup 0)
 864                  (match_operand:HI 1 "const_int_ge_8_operand" "")))]
 865   "TARGET_H8300"
 866   [(set (match_dup 2)
 867         (match_dup 1))
 868    (set (match_dup 0)
 869         (plus:HI (match_dup 0)
 870                  (match_dup 2)))]
 871   "")
 872
 873 (define_insn "*addhi3_h8300hs"
 874   [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
 875         (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
 876                  (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
 877   "TARGET_H8300H || TARGET_H8300S"
 878   "@
 879    adds %2,%S0
 880    subs %G2,%S0
 881    add.b        %t2,%t0
 882    add.w        %T2,%T0
 883    add.w        %T2,%T0"
 884   [(set_attr "length" "2,2,2,4,2")
 885    (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
 886
 887 (define_insn "*addhi3_incdec"
 888   [(set (match_operand:HI 0 "register_operand" "=r,r")
 889         (unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
 890                     (match_operand:HI 2 "incdec_operand" "M,O")]
 891                    UNSPEC_INCDEC))]
 892   "TARGET_H8300H || TARGET_H8300S"
 893   "@
 894    inc.w        %2,%T0
 895    dec.w        %G2,%T0"
 896   [(set_attr "length" "2,2")
 897    (set_attr "cc" "set_zn,set_zn")])
 898
 899 (define_split
 900   [(set (match_operand:HI 0 "register_operand" "")
 901         (plus:HI (match_dup 0)
 902                  (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
 903   ""
 904   [(const_int 0)]
 905   "split_adds_subs (HImode, operands); DONE;")
 906
 907 (define_expand "addsi3"
 908   [(set (match_operand:SI 0 "register_operand" "")
 909         (plus:SI (match_operand:SI 1 "register_operand" "")
 910                  (match_operand:SI 2 "nonmemory_operand" "")))]
 911   ""
 912   "")
 913
 914 (define_insn "*addsi_h8300"
 915   [(set (match_operand:SI 0 "register_operand" "=r,r")
 916         (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
 917                  (match_operand:SI 2 "nonmemory_operand" "n,r")))]
 918   "TARGET_H8300"
 919   "* return output_plussi (operands);"
 920   [(set (attr "length")
 921         (symbol_ref "compute_plussi_length (operands)"))
 922    (set (attr "cc")
 923         (symbol_ref "compute_plussi_cc (operands)"))])
 924
 925 (define_insn "*addsi_h8300hs"
 926   [(set (match_operand:SI 0 "register_operand" "=r,r")
 927         (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
 928                  (match_operand:SI 2 "nonmemory_operand" "i,r")))]
 929   "TARGET_H8300H || TARGET_H8300S"
 930   "* return output_plussi (operands);"
 931   [(set (attr "length")
 932         (symbol_ref "compute_plussi_length (operands)"))
 933    (set (attr "cc")
 934         (symbol_ref "compute_plussi_cc (operands)"))])
 935
 936 (define_insn "*addsi3_incdec"
 937   [(set (match_operand:SI 0 "register_operand" "=r,r")
 938         (unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
 939                     (match_operand:SI 2 "incdec_operand" "M,O")]
 940                    UNSPEC_INCDEC))]
 941   "TARGET_H8300H || TARGET_H8300S"
 942   "@
 943    inc.l        %2,%S0
 944    dec.l        %G2,%S0"
 945   [(set_attr "length" "2,2")
 946    (set_attr "cc" "set_zn,set_zn")])
 947
 948 (define_split
 949   [(set (match_operand:SI 0 "register_operand" "")
 950         (plus:SI (match_dup 0)
 951                  (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
 952   "TARGET_H8300H || TARGET_H8300S"
 953   [(const_int 0)]
 954   "split_adds_subs (SImode, operands); DONE;")
 955
 956 ;; ----------------------------------------------------------------------
 957 ;; SUBTRACT INSTRUCTIONS
 958 ;; ----------------------------------------------------------------------
 959
 960 (define_insn "subqi3"
 961   [(set (match_operand:QI 0 "register_operand" "=r")
 962         (minus:QI (match_operand:QI 1 "register_operand" "0")
 963                   (match_operand:QI 2 "register_operand" "r")))]
 964   ""
 965   "sub.b        %X2,%X0"
 966   [(set_attr "length" "2")
 967    (set_attr "cc" "set_zn")])
 968
 969 (define_expand "subhi3"
 970   [(set (match_operand:HI 0 "register_operand" "")
 971         (minus:HI (match_operand:HI 1 "general_operand" "")
 972                   (match_operand:HI 2 "nonmemory_operand" "")))]
 973   ""
 974   "")
 975
 976 (define_insn "*subhi3_h8300"
 977   [(set (match_operand:HI 0 "register_operand" "=r,r")
 978         (minus:HI (match_operand:HI 1 "general_operand" "0,0")
 979                   (match_operand:HI 2 "nonmemory_operand" "r,n")))]
 980   "TARGET_H8300"
 981   "@
 982    sub.w        %T2,%T0
 983    add.b        %E2,%s0\;addx   %F2,%t0"
 984   [(set_attr "length" "2,4")
 985    (set_attr "cc" "set_zn,clobber")])
 986
 987 (define_insn "*subhi3_h8300hs"
 988   [(set (match_operand:HI 0 "register_operand" "=r,r")
 989         (minus:HI (match_operand:HI 1 "general_operand" "0,0")
 990                   (match_operand:HI 2 "nonmemory_operand" "r,n")))]
 991   "TARGET_H8300H || TARGET_H8300S"
 992   "@
 993    sub.w        %T2,%T0
 994    sub.w        %T2,%T0"
 995   [(set_attr "length" "2,4")
 996    (set_attr "cc" "set_zn,set_zn")])
 997
 998 (define_expand "subsi3"
 999   [(set (match_operand:SI 0 "register_operand" "")
1000         (minus:SI (match_operand:SI 1 "register_operand" "")
1001                   (match_operand:SI 2 "nonmemory_operand" "")))]
1002   ""
1003   "")
1004
1005 (define_insn "*subsi3_h8300"
1006   [(set (match_operand:SI 0 "register_operand" "=r")
1007         (minus:SI (match_operand:SI 1 "register_operand" "0")
1008                   (match_operand:SI 2 "register_operand" "r")))]
1009   "TARGET_H8300"
1010   "sub.w        %f2,%f0\;subx   %y2,%y0\;subx   %z2,%z0"
1011   [(set_attr "length" "6")])
1012
1013 (define_insn "*subsi3_h8300hs"
1014   [(set (match_operand:SI 0 "register_operand" "=r,r")
1015         (minus:SI (match_operand:SI 1 "general_operand" "0,0")
1016                   (match_operand:SI 2 "nonmemory_operand" "r,i")))]
1017   "TARGET_H8300H || TARGET_H8300S"
1018   "@
1019    sub.l        %S2,%S0
1020    sub.l        %S2,%S0"
1021   [(set_attr "length" "2,6")
1022    (set_attr "cc" "set_zn,set_zn")])
1023 \f
1024 ;; ----------------------------------------------------------------------
1025 ;; MULTIPLY INSTRUCTIONS
1026 ;; ----------------------------------------------------------------------
1027
1028 ;; Note that the H8/300 can only handle umulqihi3.
1029
1030 (define_insn "mulqihi3"
1031   [(set (match_operand:HI 0 "register_operand" "=r")
1032         (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1033                  (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1034   "TARGET_H8300H || TARGET_H8300S"
1035   "mulxs.b      %X2,%T0"
1036   [(set_attr "length" "4")
1037    (set_attr "cc" "set_zn")])
1038
1039 (define_insn "mulhisi3"
1040   [(set (match_operand:SI 0 "register_operand" "=r")
1041         (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1042                  (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1043   "TARGET_H8300H || TARGET_H8300S"
1044   "mulxs.w      %T2,%S0"
1045   [(set_attr "length" "4")
1046    (set_attr "cc" "set_zn")])
1047
1048 (define_insn "umulqihi3"
1049   [(set (match_operand:HI 0 "register_operand" "=r")
1050         (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1051                  (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1052   ""
1053   "mulxu        %X2,%T0"
1054   [(set_attr "length" "2")
1055    (set_attr "cc" "none_0hit")])
1056
1057 (define_insn "umulhisi3"
1058   [(set (match_operand:SI 0 "register_operand" "=r")
1059         (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1060                  (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1061   "TARGET_H8300H || TARGET_H8300S"
1062   "mulxu.w      %T2,%S0"
1063   [(set_attr "length" "2")
1064    (set_attr "cc" "none_0hit")])
1065
1066 ;; This is a "bridge" instruction.  Combine can't cram enough insns
1067 ;; together to crate a MAC instruction directly, but it can create
1068 ;; this instruction, which then allows combine to create the real
1069 ;; MAC insn.
1070 ;;
1071 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1072 ;; insn must generate reasonably correct code.  Egad.
1073 (define_insn ""
1074   [(set (match_operand:SI 0 "register_operand" "=a")
1075         (mult:SI
1076           (sign_extend:SI
1077             (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1078           (sign_extend:SI
1079             (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
1080   "TARGET_MAC"
1081   "clrmac\;mac  @%2+,@%1+"
1082   [(set_attr "length" "6")
1083    (set_attr "cc" "none_0hit")])
1084
1085 (define_insn ""
1086   [(set (match_operand:SI 0 "register_operand" "=a")
1087         (plus:SI (mult:SI
1088           (sign_extend:SI (mem:HI
1089             (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1090           (sign_extend:SI (mem:HI
1091             (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1092               (match_operand:SI 3 "register_operand" "0")))]
1093   "TARGET_MAC"
1094   "mac  @%2+,@%1+"
1095   [(set_attr "length" "4")
1096    (set_attr "cc" "none_0hit")])
1097
1098 ;; ----------------------------------------------------------------------
1099 ;; DIVIDE/MOD INSTRUCTIONS
1100 ;; ----------------------------------------------------------------------
1101
1102 (define_insn "udivmodqi4"
1103   [(set (match_operand:QI 0 "register_operand" "=r")
1104         (truncate:QI
1105           (udiv:HI
1106             (match_operand:HI 1 "register_operand" "0")
1107             (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1108    (set (match_operand:QI 3 "register_operand" "=r")
1109         (truncate:QI
1110           (umod:HI
1111             (match_dup 1)
1112             (zero_extend:HI (match_dup 2)))))]
1113   ""
1114   "*
1115 {
1116   if (find_reg_note (insn, REG_UNUSED, operands[3]))
1117     return \"divxu.b\\t%X2,%T0\";
1118   else
1119     return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1120 }"
1121   [(set_attr "length" "4")])
1122
1123 (define_insn "divmodqi4"
1124   [(set (match_operand:QI 0 "register_operand" "=r")
1125         (truncate:QI
1126           (div:HI
1127             (match_operand:HI 1 "register_operand" "0")
1128             (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1129    (set (match_operand:QI 3 "register_operand" "=r")
1130         (truncate:QI
1131           (mod:HI
1132             (match_dup 1)
1133             (sign_extend:HI (match_dup 2)))))]
1134   "TARGET_H8300H || TARGET_H8300S"
1135   "*
1136 {
1137   if (find_reg_note (insn, REG_UNUSED, operands[3]))
1138     return \"divxs.b\\t%X2,%T0\";
1139   else
1140     return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1141 }"
1142   [(set_attr "length" "6")])
1143
1144 (define_insn "udivmodhi4"
1145   [(set (match_operand:HI 0 "register_operand" "=r")
1146         (truncate:HI
1147           (udiv:SI
1148             (match_operand:SI 1 "register_operand" "0")
1149             (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1150    (set (match_operand:HI 3 "register_operand" "=r")
1151         (truncate:HI
1152           (umod:SI
1153             (match_dup 1)
1154             (zero_extend:SI (match_dup 2)))))]
1155   "TARGET_H8300H || TARGET_H8300S"
1156   "*
1157 {
1158   if (find_reg_note (insn, REG_UNUSED, operands[3]))
1159     return \"divxu.w\\t%T2,%S0\";
1160   else
1161     return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1162 }"
1163   [(set_attr "length" "4")])
1164
1165 (define_insn "divmodhi4"
1166   [(set (match_operand:HI 0 "register_operand" "=r")
1167         (truncate:HI
1168           (div:SI
1169             (match_operand:SI 1 "register_operand" "0")
1170             (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1171    (set (match_operand:HI 3 "register_operand" "=r")
1172         (truncate:HI
1173           (mod:SI
1174             (match_dup 1)
1175             (sign_extend:SI (match_dup 2)))))]
1176   "TARGET_H8300H || TARGET_H8300S"
1177   "*
1178 {
1179   if (find_reg_note (insn, REG_UNUSED, operands[3]))
1180     return \"divxs.w\\t%T2,%S0\";
1181   else
1182     return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1183 }"
1184   [(set_attr "length" "6")])
1185 \f
1186 ;; ----------------------------------------------------------------------
1187 ;; AND INSTRUCTIONS
1188 ;; ----------------------------------------------------------------------
1189
1190 (define_insn "andqi3_1"
1191   [(set (match_operand:QI 0 "bit_operand" "=r,U")
1192         (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1193                 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1194   "register_operand (operands[0], QImode)
1195    || single_zero_operand (operands[2], QImode)"
1196   "@
1197    and  %X2,%X0
1198    bclr %W2,%R0"
1199   [(set_attr "length" "2,8")
1200    (set_attr "cc" "set_znv,none_0hit")])
1201
1202 (define_expand "andqi3"
1203   [(set (match_operand:QI 0 "bit_operand" "")
1204         (and:QI (match_operand:QI 1 "bit_operand" "")
1205                 (match_operand:QI 2 "nonmemory_operand" "")))]
1206   ""
1207   "
1208 {
1209   if (fix_bit_operand (operands, AND))
1210     DONE;
1211 }")
1212
1213 (define_expand "andhi3"
1214   [(set (match_operand:HI 0 "register_operand" "")
1215         (and:HI (match_operand:HI 1 "register_operand" "")
1216                 (match_operand:HI 2 "nonmemory_operand" "")))]
1217   ""
1218   "")
1219
1220 (define_insn "*andorqi3"
1221   [(set (match_operand:QI 0 "register_operand" "=r")
1222         (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1223                         (match_operand:QI 3 "single_one_operand" "n"))
1224                 (match_operand:QI 1 "register_operand" "0")))]
1225   ""
1226   "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1227   [(set_attr "length" "6")])
1228
1229 (define_insn "*andorhi3"
1230   [(set (match_operand:HI 0 "register_operand" "=r")
1231         (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1232                         (match_operand:HI 3 "single_one_operand" "n"))
1233                 (match_operand:HI 1 "register_operand" "0")))]
1234   ""
1235   "*
1236 {
1237   operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1238   if (INTVAL (operands[3]) > 128)
1239     {
1240       operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1241       return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\";
1242     }
1243   return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\";
1244 }"
1245   [(set_attr "length" "6")])
1246
1247 (define_insn "*andorsi3"
1248   [(set (match_operand:SI 0 "register_operand" "=r")
1249         (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1250                         (match_operand:SI 3 "single_one_operand" "n"))
1251                 (match_operand:SI 1 "register_operand" "0")))]
1252   "(INTVAL (operands[3]) & 0xffff) != 0"
1253   "*
1254 {
1255   operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1256   if (INTVAL (operands[3]) > 128)
1257     {
1258       operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1259       return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\";
1260     }
1261   return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\";
1262 }"
1263   [(set_attr "length" "6")])
1264
1265 (define_insn "*andorsi3_shift_8"
1266   [(set (match_operand:SI 0 "register_operand" "=r")
1267         (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1268                                    (const_int 8))
1269                         (const_int 65280))
1270                 (match_operand:SI 1 "register_operand" "0")))]
1271   ""
1272   "or.b\\t%w2,%x0"
1273   [(set_attr "length" "2")])
1274
1275 (define_expand "andsi3"
1276   [(set (match_operand:SI 0 "register_operand" "")
1277         (and:SI (match_operand:SI 1 "register_operand" "")
1278                 (match_operand:SI 2 "nonmemory_operand" "")))]
1279   ""
1280   "")
1281
1282 ;; ----------------------------------------------------------------------
1283 ;; OR INSTRUCTIONS
1284 ;; ----------------------------------------------------------------------
1285
1286 (define_insn "iorqi3_1"
1287   [(set (match_operand:QI 0 "bit_operand" "=r,U")
1288         (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1289                 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1290   "register_operand (operands[0], QImode)
1291    || single_one_operand (operands[2], QImode)"
1292   "@
1293    or\\t%X2,%X0
1294    bset\\t%V2,%R0"
1295   [(set_attr "length" "2,8")
1296    (set_attr "cc" "set_znv,none_0hit")])
1297
1298 (define_expand "iorqi3"
1299   [(set (match_operand:QI 0 "bit_operand" "")
1300         (ior:QI (match_operand:QI 1 "bit_operand" "")
1301                 (match_operand:QI 2 "nonmemory_operand" "")))]
1302   ""
1303   "
1304 {
1305   if (fix_bit_operand (operands, IOR))
1306     DONE;
1307 }")
1308
1309 (define_expand "iorhi3"
1310   [(set (match_operand:HI 0 "register_operand" "")
1311         (ior:HI (match_operand:HI 1 "register_operand" "")
1312                 (match_operand:HI 2 "nonmemory_operand" "")))]
1313   ""
1314   "")
1315
1316 (define_expand "iorsi3"
1317   [(set (match_operand:SI 0 "register_operand" "")
1318         (ior:SI (match_operand:SI 1 "register_operand" "")
1319                 (match_operand:SI 2 "nonmemory_operand" "")))]
1320   ""
1321   "")
1322
1323 ;; ----------------------------------------------------------------------
1324 ;; XOR INSTRUCTIONS
1325 ;; ----------------------------------------------------------------------
1326
1327 (define_insn "xorqi3_1"
1328   [(set (match_operand:QI 0 "bit_operand" "=r,U")
1329         (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1330                 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1331   "register_operand (operands[0], QImode)
1332    || single_one_operand (operands[2], QImode)"
1333   "@
1334    xor\\t%X2,%X0
1335    bnot\\t%V2,%R0"
1336   [(set_attr "length" "2,8")
1337    (set_attr "cc" "set_znv,none_0hit")])
1338
1339 (define_expand "xorqi3"
1340   [(set (match_operand:QI 0 "bit_operand" "")
1341         (xor:QI (match_operand:QI 1 "bit_operand" "")
1342                 (match_operand:QI 2 "nonmemory_operand" "")))]
1343   ""
1344   "
1345 {
1346   if (fix_bit_operand (operands, XOR))
1347     DONE;
1348 }")
1349
1350 (define_expand "xorhi3"
1351   [(set (match_operand:HI 0 "register_operand" "")
1352         (xor:HI (match_operand:HI 1 "register_operand" "")
1353                 (match_operand:HI 2 "nonmemory_operand" "")))]
1354   ""
1355   "")
1356
1357 (define_expand "xorsi3"
1358   [(set (match_operand:SI 0 "register_operand" "")
1359         (xor:SI (match_operand:SI 1 "register_operand" "")
1360                 (match_operand:SI 2 "nonmemory_operand" "")))]
1361   ""
1362   "")
1363
1364 ;; ----------------------------------------------------------------------
1365 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1366 ;; ----------------------------------------------------------------------
1367
1368 (define_insn "*logicalhi3"
1369   [(set (match_operand:HI 0 "register_operand" "=r")
1370         (match_operator:HI 3 "bit_operator"
1371           [(match_operand:HI 1 "register_operand" "%0")
1372            (match_operand:HI 2 "nonmemory_operand" "rn")]))]
1373   ""
1374   "* return output_logical_op (HImode, operands);"
1375   [(set (attr "length")
1376         (symbol_ref "compute_logical_op_length (HImode, operands)"))
1377    (set (attr "cc")
1378         (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1379
1380 (define_insn "*logicalsi3"
1381   [(set (match_operand:SI 0 "register_operand" "=r")
1382         (match_operator:SI 3 "bit_operator"
1383           [(match_operand:SI 1 "register_operand" "%0")
1384            (match_operand:SI 2 "nonmemory_operand" "rn")]))]
1385   ""
1386   "* return output_logical_op (SImode, operands);"
1387   [(set (attr "length")
1388         (symbol_ref "compute_logical_op_length (SImode, operands)"))
1389    (set (attr "cc")
1390         (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1391 \f
1392 ;; ----------------------------------------------------------------------
1393 ;; NEGATION INSTRUCTIONS
1394 ;; ----------------------------------------------------------------------
1395
1396 (define_insn "negqi2"
1397   [(set (match_operand:QI 0 "register_operand" "=r")
1398         (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1399   ""
1400   "neg  %X0"
1401   [(set_attr "length" "2")
1402    (set_attr "cc" "set_zn")])
1403
1404 (define_expand "neghi2"
1405   [(set (match_operand:HI 0 "register_operand" "")
1406         (neg:HI (match_operand:HI 1 "register_operand" "")))]
1407   ""
1408   "
1409 {
1410   if (TARGET_H8300)
1411     {
1412       emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1413       DONE;
1414     }
1415 }")
1416
1417 (define_expand "neghi2_h8300"
1418   [(set (match_dup 2)
1419         (not:HI (match_operand:HI 1 "register_operand" "")))
1420    (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1421    (set (match_operand:HI 0 "register_operand" "")
1422         (match_dup 2))]
1423   ""
1424   "operands[2] = gen_reg_rtx (HImode);")
1425
1426 (define_insn "*neghi2_h8300hs"
1427   [(set (match_operand:HI 0 "register_operand" "=r")
1428         (neg:HI (match_operand:HI 1 "register_operand" "0")))]
1429   "TARGET_H8300H || TARGET_H8300S"
1430   "neg  %T0"
1431   [(set_attr "length" "2")
1432    (set_attr "cc" "set_zn")])
1433
1434 (define_expand "negsi2"
1435   [(set (match_operand:SI 0 "register_operand" "")
1436         (neg:SI (match_operand:SI 1 "register_operand" "")))]
1437   ""
1438   "
1439 {
1440   if (TARGET_H8300)
1441     {
1442       emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1443       DONE;
1444     }
1445 }")
1446
1447 (define_expand "negsi2_h8300"
1448   [(set (match_dup 2)
1449         (not:SI (match_operand:SI 1 "register_operand" "")))
1450    (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1451    (set (match_operand:SI 0 "register_operand" "")
1452         (match_dup 2))]
1453   ""
1454   "operands[2] = gen_reg_rtx (SImode);")
1455
1456 (define_insn "*negsi2_h8300hs"
1457   [(set (match_operand:SI 0 "register_operand" "=r")
1458         (neg:SI (match_operand:SI 1 "register_operand" "0")))]
1459   "TARGET_H8300H || TARGET_H8300S"
1460   "neg  %S0"
1461   [(set_attr "length" "2")
1462    (set_attr "cc" "set_zn")])
1463
1464 (define_expand "negsf2"
1465   [(set (match_operand:SF 0 "register_operand" "")
1466         (neg:SF (match_operand:SF 1 "register_operand" "")))]
1467   ""
1468   "")
1469
1470 (define_insn "*negsf2_h8300"
1471   [(set (match_operand:SF 0 "register_operand" "=r")
1472         (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1473   "TARGET_H8300"
1474   "xor.b\\t#128,%z0"
1475   [(set_attr "length" "2")])
1476
1477 (define_insn "*negsf2_h8300hs"
1478   [(set (match_operand:SF 0 "register_operand" "=r")
1479         (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1480   "TARGET_H8300H || TARGET_H8300S"
1481   "xor.w\\t#32768,%e0"
1482   [(set_attr "length" "4")])
1483 \f
1484 ;; ----------------------------------------------------------------------
1485 ;; ABSOLUTE VALUE INSTRUCTIONS
1486 ;; ----------------------------------------------------------------------
1487
1488 (define_expand "abssf2"
1489   [(set (match_operand:SF 0 "register_operand" "")
1490         (abs:SF (match_operand:SF 1 "register_operand" "")))]
1491   ""
1492   "")
1493
1494 (define_insn "*abssf2_h8300"
1495   [(set (match_operand:SF 0 "register_operand" "=r")
1496         (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1497   "TARGET_H8300"
1498   "and.b\\t#127,%z0"
1499   [(set_attr "length" "2")])
1500
1501 (define_insn "*abssf2_h8300hs"
1502   [(set (match_operand:SF 0 "register_operand" "=r")
1503         (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1504   "TARGET_H8300H || TARGET_H8300S"
1505   "and.w\\t#32767,%e0"
1506   [(set_attr "length" "4")])
1507 \f
1508 ;; ----------------------------------------------------------------------
1509 ;; NOT INSTRUCTIONS
1510 ;; ----------------------------------------------------------------------
1511
1512 (define_insn "one_cmplqi2"
1513   [(set (match_operand:QI 0 "register_operand" "=r")
1514         (not:QI (match_operand:QI 1 "register_operand" "0")))]
1515   ""
1516   "not  %X0"
1517   [(set_attr "length" "2")
1518    (set_attr "cc" "set_znv")])
1519
1520 (define_expand "one_cmplhi2"
1521   [(set (match_operand:HI 0 "register_operand" "=r")
1522         (not:HI (match_operand:HI 1 "register_operand" "0")))]
1523   ""
1524   "")
1525
1526 (define_insn "*one_cmplhi2_h8300"
1527   [(set (match_operand:HI 0 "register_operand" "=r")
1528         (not:HI (match_operand:HI 1 "register_operand" "0")))]
1529   "TARGET_H8300"
1530   "not  %s0\;not        %t0"
1531   [(set_attr "length" "4")])
1532
1533 (define_insn "*one_cmplhi2_h8300hs"
1534   [(set (match_operand:HI 0 "register_operand" "=r")
1535         (not:HI (match_operand:HI 1 "register_operand" "0")))]
1536   "TARGET_H8300H || TARGET_H8300S"
1537   "not  %T0"
1538   [(set_attr "cc" "set_znv")
1539    (set_attr "length" "2")])
1540
1541 (define_expand "one_cmplsi2"
1542   [(set (match_operand:SI 0 "register_operand" "=r")
1543         (not:SI (match_operand:SI 1 "register_operand" "0")))]
1544   ""
1545   "")
1546
1547 (define_insn "*one_cmplsi2_h8300"
1548   [(set (match_operand:SI 0 "register_operand" "=r")
1549         (not:SI (match_operand:SI 1 "register_operand" "0")))]
1550   "TARGET_H8300"
1551   "not  %w0\;not        %x0\;not        %y0\;not        %z0"
1552   [(set_attr "length" "8")])
1553
1554 (define_insn "*one_cmplsi2_h8300hs"
1555   [(set (match_operand:SI 0 "register_operand" "=r")
1556         (not:SI (match_operand:SI 1 "register_operand" "0")))]
1557   "TARGET_H8300H || TARGET_H8300S"
1558   "not  %S0"
1559   [(set_attr "cc" "set_znv")
1560    (set_attr "length" "2")])
1561 \f
1562 ;; ----------------------------------------------------------------------
1563 ;; JUMP INSTRUCTIONS
1564 ;; ----------------------------------------------------------------------
1565
1566 ;; Conditional jump instructions
1567
1568 (define_expand "ble"
1569   [(match_operand 0 "" "")]
1570   ""
1571   "h8300_expand_branch (LE, operands[0]); DONE;")
1572
1573 (define_expand "bleu"
1574   [(match_operand 0 "" "")]
1575   ""
1576   "h8300_expand_branch (LEU, operands[0]); DONE;")
1577
1578 (define_expand "bge"
1579   [(match_operand 0 "" "")]
1580   ""
1581   "h8300_expand_branch (GE, operands[0]); DONE;")
1582
1583 (define_expand "bgeu"
1584   [(match_operand 0 "" "")]
1585   ""
1586   "h8300_expand_branch (GEU, operands[0]); DONE;")
1587
1588 (define_expand "blt"
1589   [(match_operand 0 "" "")]
1590   ""
1591   "h8300_expand_branch (LT, operands[0]); DONE;")
1592
1593 (define_expand "bltu"
1594   [(match_operand 0 "" "")]
1595   ""
1596   "h8300_expand_branch (LTU, operands[0]); DONE;")
1597
1598 (define_expand "bgt"
1599   [(match_operand 0 "" "")]
1600   ""
1601   "h8300_expand_branch (GT, operands[0]); DONE;")
1602
1603 (define_expand "bgtu"
1604   [(match_operand 0 "" "")]
1605   ""
1606   "h8300_expand_branch (GTU, operands[0]); DONE;")
1607
1608 (define_expand "beq"
1609   [(match_operand 0 "" "")]
1610   ""
1611   "h8300_expand_branch (EQ, operands[0]); DONE;")
1612
1613 (define_expand "bne"
1614   [(match_operand 0 "" "")]
1615   ""
1616   "h8300_expand_branch (NE, operands[0]); DONE;")
1617
1618 (define_insn "branch_true"
1619   [(set (pc)
1620         (if_then_else (match_operator 1 "comparison_operator"
1621                                       [(cc0) (const_int 0)])
1622                       (label_ref (match_operand 0 "" ""))
1623                       (pc)))]
1624   ""
1625   "*
1626 {
1627   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1628       && (GET_CODE (operands[1]) == GT
1629           || GET_CODE (operands[1]) == GE
1630           || GET_CODE (operands[1]) == LE
1631           || GET_CODE (operands[1]) == LT))
1632     {
1633       cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1634       return 0;
1635     }
1636
1637   if (get_attr_length (insn) == 2)
1638     return \"b%j1       %l0\";
1639   else if (get_attr_length (insn) == 4)
1640     return \"b%j1       %l0:16\";
1641   else
1642     return \"b%k1       .Lh8BR%=\;jmp   @%l0\\n.Lh8BR%=:\";
1643 }"
1644  [(set_attr "type" "branch")
1645    (set_attr "cc" "none")])
1646
1647 (define_insn "branch_false"
1648   [(set (pc)
1649         (if_then_else (match_operator 1 "comparison_operator"
1650                                       [(cc0) (const_int 0)])
1651                       (pc)
1652                       (label_ref (match_operand 0 "" ""))))]
1653   ""
1654   "*
1655 {
1656   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1657       && (GET_CODE (operands[1]) == GT
1658           || GET_CODE (operands[1]) == GE
1659           || GET_CODE (operands[1]) == LE
1660           || GET_CODE (operands[1]) == LT))
1661     {
1662       cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1663       return 0;
1664     }
1665
1666   if (get_attr_length (insn) == 2)
1667     return \"b%k1       %l0\";
1668   else if (get_attr_length (insn) == 4)
1669     return \"b%k1       %l0:16\";
1670   else
1671     return \"b%j1       .Lh8BR%=\;jmp   @%l0\\n.Lh8BR%=:\";
1672 }"
1673   [(set_attr "type" "branch")
1674    (set_attr "cc" "none")])
1675
1676 ;; Unconditional and other jump instructions.
1677
1678 (define_insn "jump"
1679   [(set (pc)
1680         (label_ref (match_operand 0 "" "")))]
1681   ""
1682   "*
1683 {
1684   if (get_attr_length (insn) == 2)
1685     return \"bra        %l0\";
1686   else if (get_attr_length (insn) == 4)
1687     return \"bra        %l0:16\";
1688   else
1689     return \"jmp        @%l0\";
1690 }"
1691   [(set_attr "type" "branch")
1692    (set_attr "cc" "none")])
1693
1694 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1695
1696 (define_expand "tablejump"
1697   [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
1698               (use (label_ref (match_operand 1 "" "")))])]
1699   ""
1700   "")
1701
1702 (define_insn "*tablejump_h8300"
1703   [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1704    (use (label_ref (match_operand 1 "" "")))]
1705   "TARGET_H8300"
1706   "jmp  @%0"
1707   [(set_attr "cc" "none")
1708    (set_attr "length" "2")])
1709
1710 (define_insn "*tablejump_h8300hs_advanced"
1711   [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1712    (use (label_ref (match_operand 1 "" "")))]
1713   "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
1714   "jmp  @%0"
1715   [(set_attr "cc" "none")
1716    (set_attr "length" "2")])
1717
1718 (define_insn "*tablejump_h8300hs_normal"
1719   [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1720    (use (label_ref (match_operand 1 "" "")))]
1721   "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1722   "jmp @%S0"
1723   [(set_attr "cc" "none")
1724    (set_attr "length" "2")])
1725
1726 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1727
1728 (define_expand "indirect_jump"
1729   [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1730   ""
1731   "")
1732
1733 (define_insn "*indirect_jump_h8300"
1734   [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1735   "TARGET_H8300"
1736   "jmp  @%0"
1737   [(set_attr "cc" "none")
1738    (set_attr "length" "2")])
1739
1740 (define_insn "*indirect_jump_h8300hs_advanced"
1741   [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1742   "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
1743   "jmp @%0"
1744   [(set_attr "cc" "none")
1745    (set_attr "length" "2")])
1746
1747 (define_insn "*indirect_jump_h8300hs_normal"
1748   [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1749   "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1750   "jmp @%S0"
1751   [(set_attr "cc" "none")
1752    (set_attr "length" "2")])
1753
1754 ;; Call subroutine with no return value.
1755
1756 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1757
1758 (define_insn "call"
1759   [(call (match_operand:QI 0 "call_insn_operand" "or")
1760          (match_operand:HI 1 "general_operand" "g"))]
1761   ""
1762   "*
1763 {
1764   if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1765       && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1766     return \"jsr\\t@%0:8\";
1767   else
1768     return \"jsr\\t%0\";
1769 }"
1770   [(set (attr "length")
1771         (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1772                       (const_int 2)
1773                       (const_int 4)))])
1774
1775 ;; Call subroutine, returning value in operand 0
1776 ;; (which must be a hard register).
1777
1778 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1779
1780 (define_insn "call_value"
1781   [(set (match_operand 0 "" "=r")
1782         (call (match_operand:QI 1 "call_insn_operand" "or")
1783               (match_operand:HI 2 "general_operand" "g")))]
1784   ""
1785   "*
1786 {
1787   if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1788       && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1789     return \"jsr\\t@%1:8\";
1790   else
1791     return \"jsr\\t%1\";
1792 }"
1793   [(set (attr "length")
1794         (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1795                       (const_int 2)
1796                       (const_int 4)))])
1797
1798 (define_insn "nop"
1799   [(const_int 0)]
1800   ""
1801   "nop"
1802   [(set_attr "cc" "none")
1803    (set_attr "length" "2")])
1804 \f
1805 ;; ----------------------------------------------------------------------
1806 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
1807 ;; ----------------------------------------------------------------------
1808
1809 (define_expand "push_h8300"
1810   [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
1811         (match_operand:HI 0 "register_operand" ""))]
1812   "TARGET_H8300"
1813   "")
1814
1815 (define_expand "push_h8300hs_advanced"
1816   [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
1817         (match_operand:SI 0 "register_operand" ""))]
1818   "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
1819   "")
1820
1821 (define_expand "push_h8300hs_normal"
1822   [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
1823         (match_operand:SI 0 "register_operand" ""))]
1824   "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
1825   "")
1826
1827 (define_expand "pop_h8300"
1828   [(set (match_operand:HI 0 "register_operand" "")
1829         (mem:HI (post_inc:HI (reg:HI SP_REG))))]
1830   "TARGET_H8300"
1831   "")
1832
1833 (define_expand "pop_h8300hs_advanced"
1834   [(set (match_operand:SI 0 "register_operand" "")
1835         (mem:SI (post_inc:SI (reg:SI SP_REG))))]
1836   "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
1837   "")
1838
1839 (define_expand "pop_h8300hs_normal"
1840   [(set (match_operand:SI 0 "register_operand" "")
1841         (mem:SI (post_inc:HI (reg:HI SP_REG))))]
1842   "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
1843   "")
1844
1845 (define_insn "stm_h8300s_2_advanced"
1846   [(set (reg:SI SP_REG)
1847         (plus:SI (reg:SI SP_REG) (const_int -8)))
1848    (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1849         (match_operand:SI 0 "register_operand" ""))
1850    (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1851         (match_operand:SI 1 "register_operand" ""))]
1852   "TARGET_H8300S && !TARGET_NORMAL_MODE
1853    && h8300_regs_ok_for_stm (2, operands)"
1854   "stm.l\\t%S0-%S1,@-er7"
1855   [(set_attr "cc" "none")
1856    (set_attr "length" "4")])
1857
1858 (define_insn "stm_h8300s_2_normal"
1859   [(set (reg:HI SP_REG)
1860         (plus:HI (reg:HI SP_REG) (const_int -8)))
1861    (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
1862         (match_operand:SI 0 "register_operand" ""))
1863    (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
1864         (match_operand:SI 1 "register_operand" ""))]
1865   "TARGET_H8300S && TARGET_NORMAL_MODE
1866    && h8300_regs_ok_for_stm (2, operands)"
1867   "stm.l\\t%S0-%S1,@-er7"
1868   [(set_attr "cc" "none")
1869    (set_attr "length" "4")])
1870
1871 (define_expand "stm_h8300s_2"
1872   [(match_operand:SI 0 "register_operand" "")
1873    (match_operand:SI 1 "register_operand" "")]
1874   "TARGET_H8300S
1875    && h8300_regs_ok_for_stm (2, operands)"
1876   "
1877 {
1878   if (!TARGET_NORMAL_MODE)
1879     emit_insn (gen_stm_h8300s_2_advanced (operands[0], operands[1]));
1880   else
1881     emit_insn (gen_stm_h8300s_2_normal (operands[0], operands[1]));
1882   DONE;
1883 }")
1884
1885 (define_insn "stm_h8300s_3_advanced"
1886   [(set (reg:SI SP_REG)
1887         (plus:SI (reg:SI SP_REG) (const_int -12)))
1888    (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1889         (match_operand:SI 0 "register_operand" ""))
1890    (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1891         (match_operand:SI 1 "register_operand" ""))
1892    (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1893         (match_operand:SI 2 "register_operand" ""))]
1894   "TARGET_H8300S && !TARGET_NORMAL_MODE
1895    && h8300_regs_ok_for_stm (3, operands)"
1896   "stm.l\\t%S0-%S2,@-er7"
1897   [(set_attr "cc" "none")
1898    (set_attr "length" "4")])
1899
1900 (define_insn "stm_h8300s_3_normal"
1901   [(set (reg:HI SP_REG)
1902         (plus:HI (reg:HI SP_REG) (const_int -12)))
1903    (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
1904         (match_operand:SI 0 "register_operand" ""))
1905    (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
1906         (match_operand:SI 1 "register_operand" ""))
1907    (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
1908         (match_operand:SI 2 "register_operand" ""))]
1909   "TARGET_H8300S && TARGET_NORMAL_MODE
1910    && h8300_regs_ok_for_stm (3, operands)"
1911   "stm.l\\t%S0-%S2,@-er7"
1912   [(set_attr "cc" "none")
1913    (set_attr "length" "4")])
1914
1915 (define_expand "stm_h8300s_3"
1916   [(match_operand:SI 0 "register_operand" "")
1917    (match_operand:SI 1 "register_operand" "")
1918    (match_operand:SI 2 "register_operand" "")]
1919   "TARGET_H8300S
1920    && h8300_regs_ok_for_stm (3, operands)"
1921   "
1922 {
1923   if (!TARGET_NORMAL_MODE)
1924     emit_insn (gen_stm_h8300s_3_advanced (operands[0], operands[1],
1925                                           operands[2]));
1926   else
1927     emit_insn (gen_stm_h8300s_3_normal (operands[0], operands[1],
1928                                         operands[2]));
1929   DONE;
1930 }")
1931
1932 (define_insn "stm_h8300s_4_advanced"
1933   [(set (reg:SI SP_REG)
1934         (plus:SI (reg:SI SP_REG) (const_int -16)))
1935    (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1936         (match_operand:SI 0 "register_operand" ""))
1937    (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1938         (match_operand:SI 1 "register_operand" ""))
1939    (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1940         (match_operand:SI 2 "register_operand" ""))
1941    (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
1942         (match_operand:SI 3 "register_operand" ""))]
1943   "TARGET_H8300S && !TARGET_NORMAL_MODE
1944    && h8300_regs_ok_for_stm (4, operands)"
1945   "stm.l\\t%S0-%S3,@-er7"
1946   [(set_attr "cc" "none")
1947    (set_attr "length" "4")])
1948
1949 (define_insn "stm_h8300s_4_normal"
1950   [(set (reg:HI SP_REG)
1951         (plus:HI (reg:HI SP_REG) (const_int -16)))
1952    (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
1953         (match_operand:SI 0 "register_operand" ""))
1954    (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
1955         (match_operand:SI 1 "register_operand" ""))
1956    (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
1957         (match_operand:SI 2 "register_operand" ""))
1958    (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
1959         (match_operand:SI 3 "register_operand" ""))]
1960   "TARGET_H8300S && TARGET_NORMAL_MODE
1961    && h8300_regs_ok_for_stm (4, operands)"
1962   "stm.l\\t%S0-%S3,@-er7"
1963   [(set_attr "cc" "none")
1964    (set_attr "length" "4")])
1965
1966 (define_expand "stm_h8300s_4"
1967   [(match_operand:SI 0 "register_operand" "")
1968    (match_operand:SI 1 "register_operand" "")
1969    (match_operand:SI 2 "register_operand" "")
1970    (match_operand:SI 3 "register_operand" "")]
1971   "TARGET_H8300S
1972    && h8300_regs_ok_for_stm (4, operands)"
1973   "
1974 {
1975   if (!TARGET_NORMAL_MODE)
1976     emit_insn (gen_stm_h8300s_4_advanced (operands[0], operands[1],
1977                                           operands[2], operands[3]));
1978   else
1979     emit_insn (gen_stm_h8300s_4_normal (operands[0], operands[1],
1980                                         operands[2], operands[3]));
1981   DONE;
1982 }")
1983
1984 (define_insn "ldm_h8300s_2_advanced"
1985   [(set (reg:SI SP_REG)
1986         (plus:SI (reg:SI SP_REG) (const_int 8)))
1987    (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
1988         (match_operand:SI 0 "register_operand" ""))
1989    (set (mem:SI (reg:SI SP_REG))
1990         (match_operand:SI 1 "register_operand" ""))]
1991   "TARGET_H8300S && !TARGET_NORMAL_MODE
1992    && h8300_regs_ok_for_stm (2, operands)"
1993   "ldm.l\\t@er7+,%S0-%S1"
1994   [(set_attr "cc" "none")
1995    (set_attr "length" "4")])
1996
1997 (define_insn "ldm_h8300s_2_normal"
1998   [(set (reg:HI SP_REG)
1999         (plus:HI (reg:HI SP_REG) (const_int 8)))
2000    (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2001         (match_operand:SI 0 "register_operand" ""))
2002    (set (mem:SI (reg:HI SP_REG))
2003         (match_operand:SI 1 "register_operand" ""))]
2004   "TARGET_H8300S && TARGET_NORMAL_MODE
2005    && h8300_regs_ok_for_stm (2, operands)"
2006   "ldm.l\\t@er7+,%S0-%S1"
2007   [(set_attr "cc" "none")
2008    (set_attr "length" "4")])
2009
2010 (define_expand "ldm_h8300s_2"
2011   [(match_operand:SI 0 "register_operand" "")
2012    (match_operand:SI 1 "register_operand" "")]
2013   "TARGET_H8300S
2014    && h8300_regs_ok_for_stm (2, operands)"
2015   "
2016 {
2017   if (!TARGET_NORMAL_MODE)
2018     emit_insn (gen_ldm_h8300s_2_advanced (operands[0], operands[1]));
2019   else
2020     emit_insn (gen_ldm_h8300s_2_normal (operands[0], operands[1]));
2021   DONE;
2022 }")
2023
2024 (define_insn "ldm_h8300s_3_advanced"
2025   [(set (reg:SI SP_REG)
2026         (plus:SI (reg:SI SP_REG) (const_int 12)))
2027    (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
2028         (match_operand:SI 0 "register_operand" ""))
2029    (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2030         (match_operand:SI 1 "register_operand" ""))
2031    (set (mem:SI (reg:SI SP_REG))
2032         (match_operand:SI 2 "register_operand" ""))]
2033   "TARGET_H8300S && !TARGET_NORMAL_MODE
2034    && h8300_regs_ok_for_stm (3, operands)"
2035   "ldm.l\\t@er7+,%S0-%S2"
2036   [(set_attr "cc" "none")
2037    (set_attr "length" "4")])
2038
2039 (define_insn "ldm_h8300s_3_normal"
2040   [(set (reg:HI SP_REG)
2041         (plus:HI (reg:HI SP_REG) (const_int 12)))
2042    (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 8)))
2043         (match_operand:SI 0 "register_operand" ""))
2044    (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2045         (match_operand:SI 1 "register_operand" ""))
2046    (set (mem:SI (reg:HI SP_REG))
2047         (match_operand:SI 2 "register_operand" ""))]
2048   "TARGET_H8300S && TARGET_NORMAL_MODE
2049    && h8300_regs_ok_for_stm (3, operands)"
2050   "ldm.l\\t@er7+,%S0-%S2"
2051   [(set_attr "cc" "none")
2052    (set_attr "length" "4")])
2053
2054 (define_expand "ldm_h8300s_3"
2055   [(match_operand:SI 0 "register_operand" "")
2056    (match_operand:SI 1 "register_operand" "")
2057    (match_operand:SI 2 "register_operand" "")]
2058   "TARGET_H8300S
2059    && h8300_regs_ok_for_stm (3, operands)"
2060   "
2061 {
2062   if (!TARGET_NORMAL_MODE)
2063     emit_insn (gen_ldm_h8300s_3_advanced (operands[0], operands[1],
2064                                           operands[2]));
2065   else
2066     emit_insn (gen_ldm_h8300s_3_normal (operands[0], operands[1],
2067                                         operands[2]));
2068   DONE;
2069 }")
2070
2071 (define_insn "ldm_h8300s_4_advanced"
2072   [(set (reg:SI SP_REG)
2073         (plus:SI (reg:SI SP_REG) (const_int 16)))
2074    (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 12)))
2075         (match_operand:SI 0 "register_operand" ""))
2076    (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
2077         (match_operand:SI 1 "register_operand" ""))
2078    (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2079         (match_operand:SI 2 "register_operand" ""))
2080    (set (mem:SI (reg:SI SP_REG))
2081         (match_operand:SI 3 "register_operand" ""))]
2082   "TARGET_H8300S && !TARGET_NORMAL_MODE
2083    && h8300_regs_ok_for_stm (4, operands)"
2084   "ldm.l\\t@er7+,%S0-%S3"
2085   [(set_attr "cc" "none")
2086    (set_attr "length" "4")])
2087
2088 (define_insn "ldm_h8300s_4_normal"
2089   [(set (reg:HI SP_REG)
2090         (plus:HI (reg:HI SP_REG) (const_int 16)))
2091    (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 12)))
2092         (match_operand:SI 0 "register_operand" ""))
2093    (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 8)))
2094         (match_operand:SI 1 "register_operand" ""))
2095    (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2096         (match_operand:SI 2 "register_operand" ""))
2097    (set (mem:SI (reg:HI SP_REG))
2098         (match_operand:SI 3 "register_operand" ""))]
2099   "TARGET_H8300S && TARGET_NORMAL_MODE
2100    && h8300_regs_ok_for_stm (4, operands)"
2101   "ldm.l\\t@er7+,%S0-%S3"
2102   [(set_attr "cc" "none")
2103    (set_attr "length" "4")])
2104
2105 (define_expand "ldm_h8300s_4"
2106   [(match_operand:SI 0 "register_operand" "")
2107    (match_operand:SI 1 "register_operand" "")
2108    (match_operand:SI 2 "register_operand" "")
2109    (match_operand:SI 3 "register_operand" "")]
2110   "TARGET_H8300S
2111    && h8300_regs_ok_for_stm (4, operands)"
2112   "
2113 {
2114   if (!TARGET_NORMAL_MODE)
2115     emit_insn (gen_ldm_h8300s_4_advanced (operands[0], operands[1],
2116                                           operands[2], operands[3]));
2117   else
2118     emit_insn (gen_ldm_h8300s_4_normal (operands[0], operands[1],
2119                                         operands[2], operands[3]));
2120   DONE;
2121 }")
2122
2123 (define_expand "return"
2124   [(return)]
2125   "h8300_can_use_return_insn_p ()"
2126   "")
2127
2128 (define_insn "*return_1"
2129   [(return)]
2130   "reload_completed"
2131   "*
2132 {
2133   if (h8300_current_function_interrupt_function_p ())
2134     return \"rte\";
2135   else
2136     return \"rts\";
2137 }"
2138   [(set_attr "cc" "none")
2139    (set_attr "length" "2")])
2140
2141 (define_expand "prologue"
2142   [(const_int 0)]
2143   ""
2144   "h8300_expand_prologue (); DONE;")
2145
2146 (define_expand "epilogue"
2147   [(return)]
2148   ""
2149   "h8300_expand_epilogue ();")
2150
2151 (define_insn "monitor_prologue"
2152   [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2153   ""
2154   "*
2155 {
2156   if (TARGET_H8300)
2157     return \"subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr\";
2158   else if (TARGET_H8300H)
2159     return \"mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr\";
2160   else if (TARGET_H8300S)
2161     return \"stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\";
2162     abort ();
2163 }"
2164   [(set_attr "length" "20")])
2165 \f
2166 ;; ----------------------------------------------------------------------
2167 ;; EXTEND INSTRUCTIONS
2168 ;; ----------------------------------------------------------------------
2169
2170 (define_expand "zero_extendqihi2"
2171   [(set (match_operand:HI 0 "register_operand" "")
2172         (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2173   ""
2174   "")
2175
2176 (define_insn "*zero_extendqihi2_h8300"
2177   [(set (match_operand:HI 0 "register_operand" "=r,r")
2178         (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2179   "TARGET_H8300"
2180   "@
2181   mov.b #0,%t0
2182   #"
2183   [(set_attr "length" "2,10")])
2184
2185 (define_insn "*zero_extendqihi2_h8300hs"
2186   [(set (match_operand:HI 0 "register_operand" "=r,r")
2187         (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2188   "TARGET_H8300H || TARGET_H8300S"
2189   "@
2190   extu.w        %T0
2191   #"
2192   [(set_attr "length" "2,10")
2193    (set_attr "cc" "set_znv,set_znv")])
2194
2195 ;; Split the zero extension of a general operand (actually a memory
2196 ;; operand) into a load of the operand and the actual zero extension
2197 ;; so that 1) the length will be accurate, and 2) the zero extensions
2198 ;; appearing at the end of basic blocks may be merged.
2199
2200 (define_split
2201   [(set (match_operand:HI 0 "register_operand" "")
2202         (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2203   "reload_completed"
2204   [(set (match_dup 2)
2205         (match_dup 1))
2206    (set (match_dup 0)
2207         (zero_extend:HI (match_dup 2)))]
2208   "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2209
2210 (define_expand "zero_extendqisi2"
2211   [(set (match_operand:SI 0 "register_operand" "")
2212         (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2213   ""
2214   "")
2215
2216 (define_insn "*zero_extendqisi2_h8300"
2217   [(set (match_operand:SI 0 "register_operand" "=r,r")
2218         (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2219   "TARGET_H8300"
2220   "@
2221   mov.b #0,%x0\;sub.w   %e0,%e0
2222   mov.b %R1,%w0\;mov.b  #0,%x0\;sub.w   %e0,%e0"
2223   [(set_attr "length" "4,8")])
2224
2225 (define_insn "*zero_extendqisi2_h8300hs"
2226   [(set (match_operand:SI 0 "register_operand" "=r,r")
2227         (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2228   "TARGET_H8300H || TARGET_H8300S"
2229   "#")
2230
2231 (define_split
2232   [(set (match_operand:SI 0 "register_operand" "")
2233         (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2234   "(TARGET_H8300H || TARGET_H8300S)
2235    && reg_overlap_mentioned_p (operands[0], operands[1])
2236    && reload_completed"
2237   [(set (match_dup 2)
2238         (match_dup 1))
2239    (set (match_dup 3)
2240         (zero_extend:HI (match_dup 2)))
2241    (set (match_dup 0)
2242         (zero_extend:SI (match_dup 3)))]
2243   "operands[2] = gen_lowpart (QImode, operands[0]);
2244    operands[3] = gen_lowpart (HImode, operands[0]);")
2245
2246 (define_split
2247   [(set (match_operand:SI 0 "register_operand" "")
2248         (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2249   "(TARGET_H8300H || TARGET_H8300S)
2250    && !reg_overlap_mentioned_p (operands[0], operands[1])
2251    && reload_completed"
2252   [(set (match_dup 0)
2253         (const_int 0))
2254    (set (strict_low_part (match_dup 2))
2255         (match_dup 1))]
2256   "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2257
2258 (define_expand "zero_extendhisi2"
2259   [(set (match_operand:SI 0 "register_operand" "")
2260         (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2261   ""
2262   "")
2263
2264 ;; %e prints the high part of a CONST_INT, not the low part.  Arggh.
2265 (define_insn "*zero_extendhisi2_h8300"
2266   [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2267         (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
2268   "TARGET_H8300"
2269   "@
2270   sub.w %e0,%e0
2271   mov.w %f1,%f0\;sub.w  %e0,%e0
2272   mov.w %e1,%f0\;sub.w  %e0,%e0"
2273   [(set_attr "length" "2,4,6")])
2274
2275 (define_insn "*zero_extendhisi2_h8300hs"
2276   [(set (match_operand:SI 0 "register_operand" "=r")
2277         (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2278   "TARGET_H8300H || TARGET_H8300S"
2279   "extu.l       %S0"
2280   [(set_attr "length" "2")
2281    (set_attr "cc" "set_znv")])
2282
2283 (define_expand "extendqihi2"
2284   [(set (match_operand:HI 0 "register_operand" "")
2285         (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
2286   ""
2287   "")
2288
2289 (define_insn "*extendqihi2_h8300"
2290   [(set (match_operand:HI 0 "register_operand" "=r,r")
2291         (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2292   "TARGET_H8300"
2293   "@
2294   bld   #7,%s0\;subx    %t0,%t0
2295   mov.b %R1,%s0\;bld    #7,%s0\;subx    %t0,%t0"
2296   [(set_attr "length" "4,8")])
2297
2298 (define_insn "*extendqihi2_h8300hs"
2299   [(set (match_operand:HI 0 "register_operand" "=r")
2300         (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
2301   "TARGET_H8300H || TARGET_H8300S"
2302   "exts.w       %T0"
2303   [(set_attr "length" "2")
2304    (set_attr "cc" "set_znv")])
2305
2306 (define_expand "extendqisi2"
2307   [(set (match_operand:SI 0 "register_operand" "")
2308         (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2309   ""
2310   "")
2311
2312 (define_insn "*extendqisi2_h8300"
2313   [(set (match_operand:SI 0 "register_operand" "=r,r")
2314         (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2315   "TARGET_H8300"
2316   "@
2317   bld   #7,%w0\;subx    %x0,%x0\;subx   %y0,%y0\;subx   %z0,%z0
2318   mov.b %R1,%w0\;bld    #7,%w0\;subx    %x0,%x0\;subx   %y0,%y0\;subx   %z0,%z0"
2319   [(set_attr "length" "8,12")])
2320
2321 ;; The following pattern is needed because without the pattern, the
2322 ;; combiner would split (sign_extend:SI (reg:QI)) into into two 24-bit
2323 ;; shifts, one ashift and one ashiftrt.
2324
2325 (define_insn_and_split "*extendqisi2_h8300hs"
2326   [(set (match_operand:SI 0 "register_operand" "=r")
2327         (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2328   "(TARGET_H8300H || TARGET_H8300S)"
2329   "#"
2330   "&& reload_completed"
2331   [(set (match_dup 2)
2332         (sign_extend:HI (match_dup 1)))
2333    (set (match_dup 0)
2334         (sign_extend:SI (match_dup 2)))]
2335   "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2336
2337 (define_expand "extendhisi2"
2338   [(set (match_operand:SI 0 "register_operand" "")
2339         (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2340   ""
2341   "")
2342
2343 (define_insn "*extendhisi2_h8300"
2344   [(set (match_operand:SI 0 "register_operand" "=r,r")
2345         (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
2346   "TARGET_H8300"
2347   "@
2348   bld   #7,%x0\;subx    %y0,%y0\;subx   %z0,%z0
2349   mov.w %T1,%f0\;bld    #7,%x0\;subx    %y0,%y0\;subx   %z0,%z0"
2350   [(set_attr "length" "6,10")])
2351
2352 (define_insn "*extendhisi2_h8300hs"
2353   [(set (match_operand:SI 0 "register_operand" "=r")
2354         (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2355   "TARGET_H8300H || TARGET_H8300S"
2356   "exts.l       %S0"
2357   [(set_attr "length" "2")
2358    (set_attr "cc" "set_znv")])
2359 \f
2360 ;; ----------------------------------------------------------------------
2361 ;; SHIFTS
2362 ;; ----------------------------------------------------------------------
2363 ;;
2364 ;; We make some attempt to provide real efficient shifting.  One example is
2365 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
2366 ;; reg and moving 0 into the former reg.
2367 ;;
2368 ;; We also try to achieve this in a uniform way.  IE: We don't try to achieve
2369 ;; this in both rtl and at insn emit time.  Ideally, we'd use rtl as that would
2370 ;; give the optimizer more cracks at the code.  However, we wish to do things
2371 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
2372 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
2373 ;; 16 bit rotates.  Also, if we emit complicated rtl, combine may not be able
2374 ;; to detect cases it can optimize.
2375 ;;
2376 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2377 ;; easier "do it at insn emit time" route.
2378
2379 ;; QI BIT SHIFTS
2380
2381 (define_expand "ashlqi3"
2382   [(set (match_operand:QI 0 "register_operand" "")
2383         (ashift:QI (match_operand:QI 1 "register_operand" "")
2384                    (match_operand:QI 2 "nonmemory_operand" "")))]
2385   ""
2386   "expand_a_shift (QImode, ASHIFT, operands); DONE;")
2387
2388 (define_expand "ashrqi3"
2389   [(set (match_operand:QI 0 "register_operand" "")
2390         (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2391                      (match_operand:QI 2 "nonmemory_operand" "")))]
2392   ""
2393   "expand_a_shift (QImode, ASHIFTRT, operands); DONE;")
2394
2395 (define_expand "lshrqi3"
2396   [(set (match_operand:QI 0 "register_operand" "")
2397         (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2398                      (match_operand:QI 2 "nonmemory_operand" "")))]
2399   ""
2400   "expand_a_shift (QImode, LSHIFTRT, operands); DONE;")
2401
2402 (define_insn "*shiftqi"
2403   [(set (match_operand:QI 0 "register_operand" "=r,r")
2404         (match_operator:QI 3 "nshift_operator"
2405                         [ (match_operand:QI 1 "register_operand" "0,0")
2406                           (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2407    (clobber (match_scratch:QI 4 "=X,&r"))]
2408   ""
2409   "* return output_a_shift (operands);"
2410   [(set (attr "length")
2411         (symbol_ref "compute_a_shift_length (insn, operands)"))
2412    (set (attr "cc")
2413         (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2414
2415 ;; HI BIT SHIFTS
2416
2417 (define_expand "ashlhi3"
2418   [(set (match_operand:HI 0 "register_operand" "")
2419         (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
2420                    (match_operand:QI 2 "nonmemory_operand" "")))]
2421   ""
2422   "expand_a_shift (HImode, ASHIFT, operands); DONE;")
2423
2424 (define_expand "lshrhi3"
2425   [(set (match_operand:HI 0 "register_operand" "")
2426         (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
2427                      (match_operand:QI 2 "nonmemory_operand" "")))]
2428   ""
2429   "expand_a_shift (HImode, LSHIFTRT, operands); DONE;")
2430
2431 (define_expand "ashrhi3"
2432   [(set (match_operand:HI 0 "register_operand" "")
2433         (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
2434                      (match_operand:QI 2 "nonmemory_operand" "")))]
2435   ""
2436   "expand_a_shift (HImode, ASHIFTRT, operands); DONE;")
2437
2438 (define_insn "*shifthi"
2439   [(set (match_operand:HI 0 "register_operand" "=r,r")
2440         (match_operator:HI 3 "nshift_operator"
2441                         [ (match_operand:HI 1 "register_operand" "0,0")
2442                           (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
2443    (clobber (match_scratch:QI 4 "=X,&r"))]
2444   ""
2445   "* return output_a_shift (operands);"
2446   [(set (attr "length")
2447         (symbol_ref "compute_a_shift_length (insn, operands)"))
2448    (set (attr "cc")
2449         (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2450
2451 ;;  SI BIT SHIFTS
2452
2453 (define_expand "ashlsi3"
2454   [(set (match_operand:SI 0 "register_operand" "")
2455         (ashift:SI (match_operand:SI 1 "general_operand" "")
2456                    (match_operand:QI 2 "nonmemory_operand" "")))]
2457   ""
2458   "expand_a_shift (SImode, ASHIFT, operands); DONE;")
2459
2460 (define_expand "lshrsi3"
2461   [(set (match_operand:SI 0 "register_operand" "")
2462         (lshiftrt:SI (match_operand:SI 1 "general_operand" "")
2463                      (match_operand:QI 2 "nonmemory_operand" "")))]
2464   ""
2465   "expand_a_shift (SImode, LSHIFTRT, operands); DONE;")
2466
2467 (define_expand "ashrsi3"
2468   [(set (match_operand:SI 0 "register_operand" "")
2469         (ashiftrt:SI (match_operand:SI 1 "general_operand" "")
2470                      (match_operand:QI 2 "nonmemory_operand" "")))]
2471   ""
2472   "expand_a_shift (SImode, ASHIFTRT, operands); DONE;")
2473
2474 (define_insn "*shiftsi"
2475   [(set (match_operand:SI 0 "register_operand" "=r,r")
2476         (match_operator:SI 3 "nshift_operator"
2477                         [ (match_operand:SI 1 "register_operand" "0,0")
2478                           (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
2479    (clobber (match_scratch:QI 4 "=X,&r"))]
2480   ""
2481   "* return output_a_shift (operands);"
2482   [(set (attr "length")
2483         (symbol_ref "compute_a_shift_length (insn, operands)"))
2484    (set (attr "cc")
2485         (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2486
2487 ;; Split a variable shift into a loop.  If the register containing
2488 ;; the shift count dies, then we just use that register.
2489
2490 (define_split
2491   [(set (match_operand 0 "register_operand" "")
2492         (match_operator 2 "nshift_operator"
2493                         [(match_dup 0)
2494                          (match_operand:QI 1 "register_operand" "")]))
2495    (clobber (match_operand:QI 3 "register_operand" ""))]
2496   "flow2_completed
2497    && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2498   [(set (cc0)
2499         (match_dup 1))
2500    (set (pc)
2501         (if_then_else (le (cc0) (const_int 0))
2502                       (label_ref (match_dup 5))
2503                       (pc)))
2504    (match_dup 4)
2505    (parallel
2506      [(set (match_dup 0)
2507            (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2508       (clobber (scratch:QI))])
2509    (set (match_dup 1)
2510         (plus:QI (match_dup 1) (const_int -1)))
2511    (set (cc0)
2512         (match_dup 1))
2513    (set (pc)
2514         (if_then_else (ne (cc0) (const_int 0))
2515                       (label_ref (match_dup 4))
2516                       (pc)))
2517    (match_dup 5)]
2518   "operands[4] = gen_label_rtx ();
2519    operands[5] = gen_label_rtx ();")
2520
2521 (define_split
2522   [(set (match_operand 0 "register_operand" "")
2523         (match_operator 2 "nshift_operator"
2524                         [(match_dup 0)
2525                          (match_operand:QI 1 "register_operand" "")]))
2526    (clobber (match_operand:QI 3 "register_operand" ""))]
2527   "flow2_completed
2528    && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2529   [(set (match_dup 3)
2530         (match_dup 1))
2531    (set (cc0)
2532         (match_dup 3))
2533    (set (pc)
2534         (if_then_else (le (cc0) (const_int 0))
2535                       (label_ref (match_dup 5))
2536                       (pc)))
2537    (match_dup 4)
2538    (parallel
2539      [(set (match_dup 0)
2540            (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2541       (clobber (scratch:QI))])
2542    (set (match_dup 3)
2543         (plus:QI (match_dup 3) (const_int -1)))
2544    (set (cc0)
2545         (match_dup 3))
2546    (set (pc)
2547         (if_then_else (ne (cc0) (const_int 0))
2548                       (label_ref (match_dup 4))
2549                       (pc)))
2550    (match_dup 5)]
2551   "operands[4] = gen_label_rtx ();
2552    operands[5] = gen_label_rtx ();")
2553 \f
2554 ;; ----------------------------------------------------------------------
2555 ;; ROTATIONS
2556 ;; ----------------------------------------------------------------------
2557
2558 (define_expand "rotlqi3"
2559   [(set (match_operand:QI 0 "register_operand" "")
2560         (rotate:QI (match_operand:QI 1 "register_operand" "")
2561                    (match_operand:QI 2 "nonmemory_operand" "")))]
2562   ""
2563   "if (expand_a_rotate (operands)) DONE; else FAIL;")
2564
2565 (define_insn "rotlqi3_1"
2566   [(set (match_operand:QI 0 "register_operand" "=r")
2567         (rotate:QI (match_operand:QI 1 "register_operand" "0")
2568                    (match_operand:QI 2 "immediate_operand" "")))]
2569   ""
2570   "* return output_a_rotate (ROTATE, operands);"
2571   [(set (attr "length")
2572         (symbol_ref "compute_a_rotate_length (operands)"))])
2573
2574 (define_expand "rotlhi3"
2575   [(set (match_operand:HI 0 "register_operand" "")
2576         (rotate:HI (match_operand:HI 1 "register_operand" "")
2577                    (match_operand:QI 2 "nonmemory_operand" "")))]
2578   ""
2579   "if (expand_a_rotate (operands)) DONE; else FAIL;")
2580
2581 (define_insn "rotlhi3_1"
2582   [(set (match_operand:HI 0 "register_operand" "=r")
2583         (rotate:HI (match_operand:HI 1 "register_operand" "0")
2584                    (match_operand:QI 2 "immediate_operand" "")))]
2585   ""
2586   "* return output_a_rotate (ROTATE, operands);"
2587   [(set (attr "length")
2588         (symbol_ref "compute_a_rotate_length (operands)"))])
2589
2590 (define_expand "rotlsi3"
2591   [(set (match_operand:SI 0 "register_operand" "")
2592         (rotate:SI (match_operand:SI 1 "register_operand" "")
2593                    (match_operand:QI 2 "nonmemory_operand" "")))]
2594   "TARGET_H8300H || TARGET_H8300S"
2595   "if (expand_a_rotate (operands)) DONE; else FAIL;")
2596
2597 (define_insn "rotlsi3_1"
2598   [(set (match_operand:SI 0 "register_operand" "=r")
2599         (rotate:SI (match_operand:SI 1 "register_operand" "0")
2600                    (match_operand:QI 2 "immediate_operand" "")))]
2601   "TARGET_H8300H || TARGET_H8300S"
2602   "* return output_a_rotate (ROTATE, operands);"
2603   [(set (attr "length")
2604         (symbol_ref "compute_a_rotate_length (operands)"))])
2605 \f
2606 ;; -----------------------------------------------------------------
2607 ;; BIT FIELDS
2608 ;; -----------------------------------------------------------------
2609 ;; The H8/300 has given 1/8th of its opcode space to bitfield
2610 ;; instructions so let's use them as well as we can.
2611
2612 ;; You'll never believe all these patterns perform one basic action --
2613 ;; load a bit from the source, optionally invert the bit, then store it
2614 ;; in the destination (which is known to be zero).
2615 ;;
2616 ;; Combine obviously need some work to better identify this situation and
2617 ;; canonicalize the form better.
2618
2619 ;;
2620 ;; Normal loads with a 16bit destination.
2621 ;;
2622
2623 (define_insn ""
2624   [(set (match_operand:HI 0 "register_operand" "=&r")
2625         (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2626                          (const_int 1)
2627                          (match_operand:HI 2 "immediate_operand" "n")))]
2628   "TARGET_H8300"
2629   "sub.w        %0,%0\;bld      %Z2,%Y1\;bst    #0,%X0"
2630   [(set_attr "length" "6")])
2631
2632 ;;
2633 ;; Inverted loads with a 16bit destination.
2634 ;;
2635
2636 (define_insn ""
2637   [(set (match_operand:HI 0 "register_operand" "=&r")
2638         (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
2639                                  (match_operand:HI 3 "const_int_operand" "n"))
2640                          (const_int 1)
2641                          (match_operand:HI 2 "const_int_operand" "n")))]
2642   "TARGET_H8300
2643    && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2644   "sub.w        %0,%0\;bild     %Z2,%Y1\;bst    #0,%X0"
2645   [(set_attr "length" "8")])
2646
2647 ;;
2648 ;; Normal loads with a 32bit destination.
2649 ;;
2650
2651 (define_insn "*extzv_1_r_h8300"
2652   [(set (match_operand:SI 0 "register_operand" "=&r")
2653         (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2654                          (const_int 1)
2655                          (match_operand 2 "const_int_operand" "n")))]
2656   "TARGET_H8300
2657    && INTVAL (operands[2]) < 16"
2658   "* return output_simode_bld (0, operands);"
2659   [(set_attr "length" "8")])
2660
2661 (define_insn "*extzv_1_r_h8300hs"
2662   [(set (match_operand:SI 0 "register_operand" "=r,r")
2663         (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2664                          (const_int 1)
2665                          (match_operand 2 "const_int_operand" "n,n")))]
2666   "(TARGET_H8300H || TARGET_H8300S)
2667    && INTVAL (operands[2]) < 16"
2668   "* return output_simode_bld (0, operands);"
2669   [(set_attr "cc" "set_znv,set_znv")
2670    (set_attr "length" "8,6")])
2671
2672 ;;
2673 ;; Inverted loads with a 32bit destination.
2674 ;;
2675
2676 (define_insn "*extzv_1_r_inv_h8300"
2677   [(set (match_operand:SI 0 "register_operand" "=&r")
2678         (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2679                                  (match_operand:HI 3 "const_int_operand" "n"))
2680                          (const_int 1)
2681                          (match_operand 2 "const_int_operand" "n")))]
2682   "TARGET_H8300
2683    && INTVAL (operands[2]) < 16
2684    && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2685   "* return output_simode_bld (1, operands);"
2686   [(set_attr "length" "8")])
2687
2688 (define_insn "*extzv_1_r_inv_h8300hs"
2689   [(set (match_operand:SI 0 "register_operand" "=r,r")
2690         (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
2691                                  (match_operand 3 "const_int_operand" "n,n"))
2692                          (const_int 1)
2693                          (match_operand 2 "const_int_operand" "n,n")))]
2694   "(TARGET_H8300H || TARGET_H8300S)
2695    && INTVAL (operands[2]) < 16
2696    && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2697   "* return output_simode_bld (1, operands);"
2698   [(set_attr "cc" "set_znv,set_znv")
2699    (set_attr "length" "8,6")])
2700
2701 (define_expand "insv"
2702   [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2703                          (match_operand:HI 1 "general_operand" "")
2704                          (match_operand:HI 2 "general_operand" ""))
2705         (match_operand:HI 3 "general_operand" ""))]
2706   "TARGET_H8300"
2707   "
2708 {
2709   /* We only have single bit bit-field instructions.  */
2710   if (INTVAL (operands[1]) != 1)
2711     FAIL;
2712
2713   /* For now, we don't allow memory operands.  */
2714   if (GET_CODE (operands[0]) == MEM
2715       || GET_CODE (operands[3]) == MEM)
2716     FAIL;
2717 }")
2718
2719 (define_insn ""
2720   [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2721                          (const_int 1)
2722                          (match_operand:HI 1 "immediate_operand" "n"))
2723         (match_operand:HI 2 "register_operand" "r"))]
2724   ""
2725   "bld  #0,%R2\;bst     %Z1,%Y0 ; i1"
2726   [(set_attr "length" "4")])
2727
2728 (define_expand "extzv"
2729   [(set (match_operand:HI 0 "register_operand" "")
2730         (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2731                          (match_operand:HI 2 "general_operand" "")
2732                          (match_operand:HI 3 "general_operand" "")))]
2733   "TARGET_H8300"
2734   "
2735 {
2736   /* We only have single bit bit-field instructions.  */
2737   if (INTVAL (operands[2]) != 1)
2738     FAIL;
2739
2740   /* For now, we don't allow memory operands.  */
2741   if (GET_CODE (operands[1]) == MEM)
2742     FAIL;
2743 }")
2744
2745 ;; BAND, BOR, and BXOR patterns
2746
2747 (define_insn ""
2748   [(set (match_operand:HI 0 "bit_operand" "=Ur")
2749         (match_operator:HI 4 "bit_operator"
2750            [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2751                              (const_int 1)
2752                              (match_operand:HI 2 "immediate_operand" "n"))
2753             (match_operand:HI 3 "bit_operand" "0")]))]
2754   ""
2755   "bld  %Z2,%Y1\;b%c4   #0,%R0\;bst     #0,%R0; bl1"
2756   [(set_attr "length" "6")])
2757
2758 (define_insn ""
2759   [(set (match_operand:HI 0 "bit_operand" "=Ur")
2760         (match_operator:HI 5 "bit_operator"
2761            [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2762                              (const_int 1)
2763                              (match_operand:HI 2 "immediate_operand" "n"))
2764             (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2765                              (const_int 1)
2766                              (match_operand:HI 4 "immediate_operand" "n"))]))]
2767   ""
2768   "bld  %Z2,%Y1\;b%c5   %Z4,%Y3\;bst    #0,%R0; bl3"
2769   [(set_attr "length" "6")])
2770 \f
2771 ;; -----------------------------------------------------------------
2772 ;; COMBINE PATTERNS
2773 ;; -----------------------------------------------------------------
2774
2775 ;; insv:SI
2776
2777 (define_insn "*insv_si_1_n"
2778   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2779                          (const_int 1)
2780                          (match_operand:SI 1 "const_int_operand" "n"))
2781         (match_operand:SI 2 "register_operand" "r"))]
2782   "(TARGET_H8300H || TARGET_H8300S)
2783    && INTVAL (operands[1]) < 16"
2784   "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
2785   [(set_attr "length" "4")])
2786
2787 (define_insn "*insv_si_1_n_lshiftrt"
2788   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2789                          (const_int 1)
2790                          (match_operand:SI 1 "const_int_operand" "n"))
2791         (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2792                      (match_operand:SI 3 "const_int_operand" "n")))]
2793   "(TARGET_H8300H || TARGET_H8300S)
2794    && INTVAL (operands[1]) < 16
2795    && INTVAL (operands[3]) < 16"
2796   "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
2797   [(set_attr "length" "4")])
2798
2799 (define_insn "*insv_si_1_n_lshiftrt_16"
2800   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2801                          (const_int 1)
2802                          (match_operand:SI 1 "const_int_operand" "n"))
2803         (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2804                      (const_int 16)))]
2805   "(TARGET_H8300H || TARGET_H8300S)
2806    && INTVAL (operands[1]) < 16"
2807   "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
2808   [(set_attr "length" "6")])
2809
2810 (define_insn "*insv_si_8_8"
2811   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2812                          (const_int 8)
2813                          (const_int 8))
2814         (match_operand:SI 1 "register_operand" "r"))]
2815   "TARGET_H8300H || TARGET_H8300S"
2816   "mov.b\\t%w1,%x0"
2817   [(set_attr "length" "2")])
2818
2819 (define_insn "*insv_si_8_8_lshiftrt_8"
2820   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2821                          (const_int 8)
2822                          (const_int 8))
2823         (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2824                      (const_int 8)))]
2825   "TARGET_H8300H || TARGET_H8300S"
2826   "mov.b\\t%x1,%x0"
2827   [(set_attr "length" "2")])
2828
2829 ;; extzv:SI
2830
2831 (define_insn "*extzv_8_8"
2832   [(set (match_operand:SI 0 "register_operand" "=r,r")
2833         (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2834                          (const_int 8)
2835                          (const_int 8)))]
2836   "TARGET_H8300H || TARGET_H8300S"
2837   "@
2838    mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
2839    sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
2840   [(set_attr "cc" "set_znv,clobber")
2841    (set_attr "length" "6,4")])
2842
2843 (define_insn "*extzv_8_16"
2844   [(set (match_operand:SI 0 "register_operand" "=r")
2845         (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2846                          (const_int 8)
2847                          (const_int 16)))]
2848   "TARGET_H8300H || TARGET_H8300S"
2849   "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
2850   [(set_attr "cc" "set_znv")
2851    (set_attr "length" "6")])
2852
2853 (define_insn "*extzv_16_8"
2854   [(set (match_operand:SI 0 "register_operand" "=r")
2855         (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2856                          (const_int 16)
2857                          (const_int 8)))
2858    (clobber (match_scratch:SI 2 "=&r"))]
2859   "TARGET_H8300H"
2860   "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
2861   [(set_attr "length" "8")
2862    (set_attr "cc" "set_znv")])
2863
2864 ;; Extract the exponent of a float.
2865
2866 (define_insn_and_split "*extzv_8_23"
2867   [(set (match_operand:SI 0 "register_operand" "=r")
2868         (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
2869                          (const_int 8)
2870                          (const_int 23)))]
2871   "(TARGET_H8300H || TARGET_H8300S)"
2872   "#"
2873   "&& reload_completed"
2874   [(parallel [(set (match_dup 0)
2875                    (ashift:SI (match_dup 0)
2876                               (const_int 1)))
2877               (clobber (scratch:QI))])
2878    (parallel [(set (match_dup 0)
2879                    (lshiftrt:SI (match_dup 0)
2880                                 (const_int 24)))
2881               (clobber (scratch:QI))])]
2882   "")
2883
2884 ;; and:SI
2885
2886 ;; ((SImode) HImode) << 15
2887
2888 (define_insn_and_split "*twoshifts_l16_r1"
2889   [(set (match_operand:SI 0 "register_operand" "=r")
2890         (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2891                            (const_int 15))
2892                 (const_int 2147450880)))]
2893   "(TARGET_H8300H || TARGET_H8300S)"
2894   "#"
2895   "&& reload_completed"
2896   [(parallel [(set (match_dup 0)
2897                    (ashift:SI (match_dup 0)
2898                               (const_int 16)))
2899               (clobber (scratch:QI))])
2900    (parallel [(set (match_dup 0)
2901                    (lshiftrt:SI (match_dup 0)
2902                                 (const_int 1)))
2903               (clobber (scratch:QI))])]
2904   "")
2905
2906 ;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
2907
2908 (define_insn_and_split "*andsi3_ashift_n_lower"
2909   [(set (match_operand:SI 0 "register_operand" "=r,r")
2910         (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
2911                            (match_operand:QI 2 "const_int_operand" "S,n"))
2912                 (match_operand:SI 3 "const_int_operand" "n,n")))
2913    (clobber (match_scratch:QI 4 "=X,&r"))]
2914   "(TARGET_H8300H || TARGET_H8300S)
2915    && INTVAL (operands[2]) <= 15
2916    && INTVAL (operands[3]) == ((-1 << INTVAL (operands[2])) & 0xffff)"
2917   "#"
2918   "&& reload_completed"
2919   [(parallel [(set (match_dup 5)
2920                    (ashift:HI (match_dup 5)
2921                               (match_dup 2)))
2922               (clobber (match_dup 4))])
2923    (set (match_dup 0)
2924         (zero_extend:SI (match_dup 5)))]
2925   "operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2926
2927 ;; Accept (A >> 30) & 2 and the like.
2928
2929 (define_insn "*andsi3_lshiftrt_n_sb"
2930   [(set (match_operand:SI 0 "register_operand" "=r")
2931         (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
2932                              (match_operand:SI 2 "const_int_operand" "n"))
2933                 (match_operand:SI 3 "single_one_operand" "n")))]
2934   "(TARGET_H8300H || TARGET_H8300S)
2935    && exact_log2 (INTVAL (operands[3])) < 16
2936    && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
2937   "*
2938 {
2939   operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
2940   return \"shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0\";
2941 }"
2942   [(set_attr "length" "8")])
2943
2944 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
2945   [(set (match_operand:SI 0 "register_operand" "=r")
2946         (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
2947                              (const_int 9))
2948                 (const_int 4194304)))]
2949   "(TARGET_H8300H || TARGET_H8300S)"
2950   "#"
2951   "&& reload_completed"
2952   [(set (match_dup 0)
2953         (and:SI (lshiftrt:SI (match_dup 0)
2954                              (const_int 25))
2955                 (const_int 64)))
2956    (parallel [(set (match_dup 0)
2957                    (ashift:SI (match_dup 0)
2958                               (const_int 16)))
2959               (clobber (scratch:QI))])]
2960   "")
2961
2962 ;; plus:SI
2963
2964 (define_insn "*addsi3_upper"
2965   [(set (match_operand:SI 0 "register_operand" "=r")
2966         (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
2967                           (const_int 65536))
2968                  (match_operand:SI 2 "register_operand" "0")))]
2969   "TARGET_H8300H || TARGET_H8300S"
2970   "add.w\\t%f1,%e0"
2971   [(set_attr "length" "2")])
2972
2973 (define_insn "*addsi3_lshiftrt_16_zexthi"
2974   [(set (match_operand:SI 0 "register_operand" "=r")
2975         (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2976                               (const_int 16))
2977                  (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
2978   "TARGET_H8300H || TARGET_H8300S"
2979   "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0"
2980   [(set_attr "length" "6")])
2981
2982 (define_insn_and_split "*addsi3_and_r_1"
2983   [(set (match_operand:SI 0 "register_operand" "=r")
2984         (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
2985                          (const_int 1))
2986                  (match_operand:SI 2 "register_operand" "0")))]
2987   "(TARGET_H8300H || TARGET_H8300S)"
2988   "#"
2989   "&& reload_completed"
2990   [(set (cc0)
2991         (zero_extract:SI (match_dup 1)
2992                          (const_int 1)
2993                          (const_int 0)))
2994    (set (pc)
2995         (if_then_else (eq (cc0)
2996                           (const_int 0))
2997                       (label_ref (match_dup 3))
2998                       (pc)))
2999    (set (match_dup 2)
3000         (plus:SI (match_dup 2)
3001                  (const_int 1)))
3002    (match_dup 3)]
3003   "operands[3] = gen_label_rtx ();")
3004
3005 (define_insn_and_split "*addsi3_and_not_r_1"
3006   [(set (match_operand:SI 0 "register_operand" "=r")
3007         (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3008                          (const_int 1))
3009                  (match_operand:SI 2 "register_operand" "0")))]
3010   "(TARGET_H8300H || TARGET_H8300S)"
3011   "#"
3012   "&& reload_completed"
3013   [(set (cc0)
3014         (zero_extract:SI (match_dup 1)
3015                          (const_int 1)
3016                          (const_int 0)))
3017    (set (pc)
3018         (if_then_else (ne (cc0)
3019                           (const_int 0))
3020                       (label_ref (match_dup 3))
3021                       (pc)))
3022    (set (match_dup 2)
3023         (plus:SI (match_dup 2)
3024                  (const_int 1)))
3025    (match_dup 3)]
3026   "operands[3] = gen_label_rtx ();")
3027
3028 ;; [ix]or:HI
3029
3030 (define_insn "*ixorhi3_zext"
3031   [(set (match_operand:HI 0 "register_operand" "=r")
3032         (match_operator:HI 1 "iorxor_operator"
3033           [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
3034            (match_operand:HI 3 "register_operand" "0")]))]
3035   ""
3036   "%c1.b\\t%X2,%s0"
3037   [(set_attr "length" "2")])
3038
3039 ;; [ix]or:SI
3040
3041 (define_insn "*ixorsi3_zext_qi"
3042   [(set (match_operand:SI 0 "register_operand" "=r")
3043         (match_operator:SI 1 "iorxor_operator"
3044           [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
3045            (match_operand:SI 3 "register_operand" "0")]))]
3046   ""
3047   "%c1.b\\t%X2,%w0"
3048   [(set_attr "length" "2")])
3049
3050 (define_insn "*ixorsi3_zext_hi"
3051   [(set (match_operand:SI 0 "register_operand" "=r")
3052         (match_operator:SI 1 "iorxor_operator"
3053           [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
3054            (match_operand:SI 3 "register_operand" "0")]))]
3055   "TARGET_H8300H || TARGET_H8300S"
3056   "%c1.w\\t%T2,%f0"
3057   [(set_attr "length" "2")])
3058
3059 (define_insn "*ixorsi3_ashift_16"
3060   [(set (match_operand:SI 0 "register_operand" "=r")
3061         (match_operator:SI 1 "iorxor_operator"
3062           [(ashift:SI (match_operand:SI 2 "register_operand" "r")
3063                       (const_int 16))
3064            (match_operand:SI 3 "register_operand" "0")]))]
3065   "TARGET_H8300H || TARGET_H8300S"
3066   "%c1.w\\t%f2,%e0"
3067   [(set_attr "length" "2")])
3068
3069 (define_insn "*ixorsi3_lshiftrt_16"
3070   [(set (match_operand:SI 0 "register_operand" "=r")
3071         (match_operator:SI 1 "iorxor_operator"
3072           [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3073                         (const_int 16))
3074            (match_operand:SI 3 "register_operand" "0")]))]
3075   "TARGET_H8300H || TARGET_H8300S"
3076   "%c1.w\\t%e2,%f0"
3077   [(set_attr "length" "2")])
3078
3079 ;; ior:HI
3080
3081 (define_insn "*iorhi3_ashift_8"
3082   [(set (match_operand:HI 0 "register_operand" "=r")
3083         (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
3084                            (const_int 8))
3085                 (match_operand:HI 2 "register_operand" "0")))]
3086   ""
3087   "or.b\\t%s1,%t0"
3088   [(set_attr "length" "2")])
3089
3090 (define_insn "*iorhi3_lshiftrt_8"
3091   [(set (match_operand:HI 0 "register_operand" "=r")
3092         (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3093                              (const_int 8))
3094                 (match_operand:HI 2 "register_operand" "0")))]
3095   ""
3096   "or.b\\t%t1,%s0"
3097   [(set_attr "length" "2")])
3098
3099 (define_insn "*iorhi3_two_qi"
3100   [(set (match_operand:HI 0 "register_operand" "=r")
3101         (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
3102                 (ashift:HI (match_operand:HI 2 "register_operand" "r")
3103                            (const_int 8))))]
3104   ""
3105   "mov.b\\t%s2,%t0"
3106   [(set_attr "length" "2")])
3107
3108 (define_insn "*iorhi3_two_qi_mem"
3109   [(set (match_operand:HI 0 "register_operand" "=&r")
3110         (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
3111                 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
3112                            (const_int 8))))]
3113   ""
3114   "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
3115   [(set_attr "length" "16")])
3116
3117 (define_split
3118   [(set (match_operand:HI 0 "register_operand" "")
3119         (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
3120                 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
3121                            (const_int 8))))]
3122   "(TARGET_H8300H || TARGET_H8300S)
3123    && reload_completed
3124    && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
3125   [(set (match_dup 0)
3126         (match_dup 3))]
3127   "operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));")
3128
3129 ;; ior:SI
3130
3131 (define_insn "*iorsi3_two_hi"
3132   [(set (match_operand:SI 0 "register_operand" "=r")
3133         (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
3134                 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3135                            (const_int 16))))]
3136   "TARGET_H8300H || TARGET_H8300S"
3137   "mov.w\\t%f2,%e0"
3138   [(set_attr "length" "2")])
3139
3140 (define_insn_and_split "*iorsi3_two_qi_zext"
3141   [(set (match_operand:SI 0 "register_operand" "=&r")
3142         (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
3143
3144                 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3145                                    (const_int 8))
3146                         (const_int 65280))))]
3147   "(TARGET_H8300H || TARGET_H8300S)"
3148   "#"
3149   "&& reload_completed"
3150   [(set (match_dup 3)
3151         (ior:HI (zero_extend:HI (match_dup 1))
3152                 (ashift:HI (subreg:HI (match_dup 2) 0)
3153                            (const_int 8))))
3154    (set (match_dup 0)
3155         (zero_extend:SI (match_dup 3)))]
3156   "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3157
3158 (define_insn "*iorsi3_e2f"
3159   [(set (match_operand:SI 0 "register_operand" "=r")
3160         (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3161                         (const_int -65536))
3162                 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3163                              (const_int 16))))]
3164   "TARGET_H8300H || TARGET_H8300S"
3165   "mov.w\\t%e2,%f0"
3166   [(set_attr "length" "2")])
3167
3168 (define_insn_and_split "*iorsi3_two_qi_sext"
3169   [(set (match_operand:SI 0 "register_operand" "=r")
3170         (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
3171                 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
3172                            (const_int 8))))]
3173   "(TARGET_H8300H || TARGET_H8300S)"
3174   "#"
3175   "&& reload_completed"
3176   [(set (match_dup 3)
3177         (ior:HI (zero_extend:HI (match_dup 1))
3178                 (ashift:HI (match_dup 4)
3179                            (const_int 8))))
3180    (set (match_dup 0)
3181         (sign_extend:SI (match_dup 3)))]
3182   "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3183    operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3184
3185 (define_insn "*iorsi3_w"
3186   [(set (match_operand:SI 0 "register_operand" "=r,&r")
3187         (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
3188                         (const_int -256))
3189                 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
3190   "TARGET_H8300H || TARGET_H8300S"
3191   "mov.b\\t%X2,%w0"
3192   [(set_attr "length" "2,8")])
3193
3194 (define_insn "*iorsi3_ashift_31"
3195   [(set (match_operand:SI 0 "register_operand" "=&r")
3196         (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3197                            (const_int 31))
3198                 (match_operand:SI 2 "register_operand" "0")))]
3199   "TARGET_H8300H || TARGET_H8300S"
3200   "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
3201   [(set_attr "length" "6")
3202    (set_attr "cc" "set_znv")])
3203
3204 (define_insn "*iorsi3_and_ashift"
3205   [(set (match_operand:SI 0 "register_operand" "=r")
3206         (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3207                                    (match_operand:SI 2 "const_int_operand" "n"))
3208                         (match_operand:SI 3 "single_one_operand" "n"))
3209                 (match_operand:SI 4 "register_operand" "0")))]
3210   "(TARGET_H8300H || TARGET_H8300S)
3211    && (INTVAL (operands[3]) & ~0xffff) == 0"
3212   "*
3213 {
3214   rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3215                         - INTVAL (operands[2]));
3216   rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3217   operands[2] = srcpos;
3218   operands[3] = dstpos;
3219   return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
3220 }"
3221   [(set_attr "length" "6")])
3222
3223 (define_insn "*iorsi3_and_lshiftrt"
3224   [(set (match_operand:SI 0 "register_operand" "=r")
3225         (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3226                                      (match_operand:SI 2 "const_int_operand" "n"))
3227                         (match_operand:SI 3 "single_one_operand" "n"))
3228                 (match_operand:SI 4 "register_operand" "0")))]
3229   "(TARGET_H8300H || TARGET_H8300S)
3230    && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
3231   "*
3232 {
3233   rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3234                         + INTVAL (operands[2]));
3235   rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3236   operands[2] = srcpos;
3237   operands[3] = dstpos;
3238   return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
3239 }"
3240   [(set_attr "length" "6")])
3241
3242 (define_insn "*iorsi3_zero_extract"
3243   [(set (match_operand:SI 0 "register_operand" "=r")
3244         (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3245                                  (const_int 1)
3246                                  (match_operand:SI 2 "const_int_operand" "n"))
3247                 (match_operand:SI 3 "register_operand" "0")))]
3248   "(TARGET_H8300H || TARGET_H8300S)
3249    && INTVAL (operands[2]) < 16"
3250   "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
3251   [(set_attr "length" "6")])
3252
3253 (define_insn "*iorsi3_and_lshiftrt_n_sb"
3254   [(set (match_operand:SI 0 "register_operand" "=r")
3255         (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3256                                      (const_int 30))
3257                         (const_int 2))
3258                 (match_operand:SI 2 "register_operand" "0")))]
3259   "(TARGET_H8300H || TARGET_H8300S)"
3260   "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
3261   [(set_attr "length" "8")])
3262
3263 (define_insn "*iorsi3_and_lshiftrt_9_sb"
3264   [(set (match_operand:SI 0 "register_operand" "=r")
3265         (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3266                                      (const_int 9))
3267                         (const_int 4194304))
3268                 (match_operand:SI 2 "register_operand" "0")))
3269    (clobber (match_scratch:HI 3 "=&r"))]
3270   "(TARGET_H8300H || TARGET_H8300S)"
3271   "*
3272 {
3273   if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3274     return \"shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3275   else
3276     return \"rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3277 }"
3278   [(set_attr "length" "10")])
3279
3280 ;; Used to OR the exponent of a float.
3281
3282 (define_insn "*iorsi3_shift"
3283   [(set (match_operand:SI 0 "register_operand" "=r")
3284         (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3285                            (const_int 23))
3286                 (match_operand:SI 2 "register_operand" "0")))
3287    (clobber (match_scratch:SI 3 "=&r"))]
3288   "TARGET_H8300H || TARGET_H8300S"
3289   "#")
3290
3291 (define_split
3292   [(set (match_operand:SI 0 "register_operand" "")
3293         (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3294                            (const_int 23))
3295                 (match_dup 0)))
3296    (clobber (match_operand:SI 2 "register_operand" ""))]
3297   "(TARGET_H8300H || TARGET_H8300S)
3298    && flow2_completed
3299    && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3300    && REGNO (operands[0]) != REGNO (operands[1])"
3301   [(parallel [(set (match_dup 3)
3302                    (ashift:HI (match_dup 3)
3303                               (const_int 7)))
3304               (clobber (scratch:QI))])
3305    (set (match_dup 0)
3306         (ior:SI (ashift:SI (match_dup 1)
3307                            (const_int 16))
3308                 (match_dup 0)))]
3309   "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3310
3311 (define_split
3312   [(set (match_operand:SI 0 "register_operand" "")
3313         (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3314                            (const_int 23))
3315                 (match_dup 0)))
3316    (clobber (match_operand:SI 2 "register_operand" ""))]
3317   "(TARGET_H8300H || TARGET_H8300S)
3318    && flow2_completed
3319    && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3320         && REGNO (operands[0]) != REGNO (operands[1]))"
3321   [(set (match_dup 2)
3322         (match_dup 1))
3323    (parallel [(set (match_dup 3)
3324                    (ashift:HI (match_dup 3)
3325                               (const_int 7)))
3326               (clobber (scratch:QI))])
3327    (set (match_dup 0)
3328         (ior:SI (ashift:SI (match_dup 2)
3329                            (const_int 16))
3330                 (match_dup 0)))]
3331   "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3332
3333 (define_insn "*iorsi2_and_1_lshiftrt_1"
3334   [(set (match_operand:SI 0 "register_operand" "=r")
3335         (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3336                         (const_int 1))
3337                 (lshiftrt:SI (match_dup 1)
3338                              (const_int 1))))]
3339   "TARGET_H8300H || TARGET_H8300S"
3340   "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
3341   [(set_attr "length" "6")])
3342
3343 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
3344   [(set (match_operand:SI 0 "register_operand" "=r")
3345         (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3346                            (const_int 16))
3347                 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3348                            (const_int 24))))]
3349   "(TARGET_H8300H || TARGET_H8300S)"
3350   "#"
3351   "&& reload_completed"
3352   [(set (match_dup 3)
3353         (ior:HI (ashift:HI (match_dup 4)
3354                            (const_int 8))
3355                 (match_dup 3)))
3356    (parallel [(set (match_dup 0)
3357                    (ashift:SI (match_dup 0)
3358                               (const_int 16)))
3359               (clobber (scratch:QI))])]
3360   "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3361    operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3362
3363 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
3364   [(set (match_operand:SI 0 "register_operand" "=&r")
3365         (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
3366                                    (const_int 16))
3367                         (const_int 16711680))
3368                 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3369                            (const_int 24))))]
3370   "(TARGET_H8300H || TARGET_H8300S)"
3371   "#"
3372   "&& reload_completed"
3373   [(set (match_dup 3)
3374         (ior:HI (zero_extend:HI (match_dup 1))
3375                 (ashift:HI (subreg:HI (match_dup 2) 0)
3376                            (const_int 8))))
3377    (parallel [(set (match_dup 0)
3378                    (ashift:SI (match_dup 0)
3379                               (const_int 16)))
3380               (clobber (scratch:QI))])]
3381   "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3382
3383 ;; Used to add the exponent of a float.
3384
3385 (define_insn "*addsi3_shift"
3386   [(set (match_operand:SI 0 "register_operand" "=r")
3387         (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3388                           (const_int 8388608))
3389                  (match_operand:SI 2 "register_operand" "0")))
3390    (clobber (match_scratch:SI 3 "=&r"))]
3391   "TARGET_H8300H || TARGET_H8300S"
3392   "#")
3393
3394 (define_split
3395   [(set (match_operand:SI 0 "register_operand" "")
3396         (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3397                           (const_int 8388608))
3398                  (match_dup 0)))
3399    (clobber (match_operand:SI 2 "register_operand" ""))]
3400   "(TARGET_H8300H || TARGET_H8300S)
3401    && flow2_completed
3402    && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3403    && REGNO (operands[0]) != REGNO (operands[1])"
3404   [(parallel [(set (match_dup 3)
3405                    (ashift:HI (match_dup 3)
3406                               (const_int 7)))
3407               (clobber (scratch:QI))])
3408    (set (match_dup 0)
3409         (plus:SI (mult:SI (match_dup 1)
3410                           (const_int 65536))
3411                  (match_dup 0)))]
3412   "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3413
3414 (define_split
3415   [(set (match_operand:SI 0 "register_operand" "")
3416         (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3417                           (const_int 8388608))
3418                  (match_dup 0)))
3419    (clobber (match_operand:SI 2 "register_operand" ""))]
3420   "(TARGET_H8300H || TARGET_H8300S)
3421    && flow2_completed
3422    && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3423         && REGNO (operands[0]) != REGNO (operands[1]))"
3424   [(set (match_dup 2)
3425         (match_dup 1))
3426    (parallel [(set (match_dup 3)
3427                    (ashift:HI (match_dup 3)
3428                               (const_int 7)))
3429               (clobber (scratch:QI))])
3430    (set (match_dup 0)
3431         (plus:SI (mult:SI (match_dup 2)
3432                           (const_int 65536))
3433                  (match_dup 0)))]
3434   "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3435
3436 ;; ashift:SI
3437
3438 (define_insn_and_split "*ashiftsi_sextqi_7"
3439   [(set (match_operand:SI 0 "register_operand" "=r")
3440         (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
3441                    (const_int 7)))]
3442   "(TARGET_H8300H || TARGET_H8300S)"
3443   "#"
3444   "&& reload_completed"
3445   [(parallel [(set (match_dup 2)
3446                    (ashift:HI (match_dup 2)
3447                               (const_int 8)))
3448               (clobber (scratch:QI))])
3449    (set (match_dup 0)
3450         (sign_extend:SI (match_dup 2)))
3451    (parallel [(set (match_dup 0)
3452                    (ashiftrt:SI (match_dup 0)
3453                                 (const_int 1)))
3454               (clobber (scratch:QI))])]
3455   "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3456
3457 ;; Storing a part of HImode to QImode.
3458
3459 (define_insn ""
3460   [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3461         (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3462                                 (const_int 8)) 1))]
3463   ""
3464   "mov.b\\t%t1,%R0"
3465   [(set_attr "cc" "set_znv")
3466    (set_attr "length" "8")])
3467
3468 ;; Storing a part of SImode to QImode.
3469
3470 (define_insn ""
3471   [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3472         (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3473                                 (const_int 8)) 3))]
3474   ""
3475   "mov.b\\t%x1,%R0"
3476   [(set_attr "cc" "set_znv")
3477    (set_attr "length" "8")])
3478
3479 (define_insn ""
3480   [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3481         (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3482                                 (const_int 16)) 3))
3483    (clobber (match_scratch:SI 2 "=&r"))]
3484   "TARGET_H8300H || TARGET_H8300S"
3485   "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
3486   [(set_attr "cc" "set_znv")
3487    (set_attr "length" "10")])
3488
3489 (define_insn ""
3490   [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3491         (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3492                                 (const_int 24)) 3))
3493    (clobber (match_scratch:SI 2 "=&r"))]
3494   "TARGET_H8300H || TARGET_H8300S"
3495   "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
3496   [(set_attr "cc" "set_znv")
3497    (set_attr "length" "10")])
3498
3499 (define_insn_and_split ""
3500   [(set (pc)
3501         (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3502                                            (const_int 1)
3503                                            (const_int 7))
3504                           (const_int 0))
3505                       (label_ref (match_operand 1 "" ""))
3506                       (pc)))]
3507   ""
3508   "#"
3509   ""
3510   [(set (cc0)
3511         (match_dup 0))
3512    (set (pc)
3513         (if_then_else (ge (cc0)
3514                           (const_int 0))
3515                       (label_ref (match_dup 1))
3516                       (pc)))]
3517   "")
3518
3519 (define_insn_and_split ""
3520   [(set (pc)
3521         (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3522                                            (const_int 1)
3523                                            (const_int 7))
3524                           (const_int 0))
3525                       (label_ref (match_operand 1 "" ""))
3526                       (pc)))]
3527   ""
3528   "#"
3529   ""
3530   [(set (cc0)
3531         (match_dup 0))
3532    (set (pc)
3533         (if_then_else (lt (cc0)
3534                           (const_int 0))
3535                       (label_ref (match_dup 1))
3536                       (pc)))]
3537   "")
3538 \f
3539 ;; -----------------------------------------------------------------
3540 ;; PEEPHOLE PATTERNS
3541 ;; -----------------------------------------------------------------
3542
3543 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3544
3545 (define_peephole2
3546   [(parallel [(set (match_operand:HI 0 "register_operand" "")
3547                    (lshiftrt:HI (match_dup 0)
3548                                 (match_operand:HI 1 "const_int_operand" "")))
3549               (clobber (match_operand:HI 2 "" ""))])
3550    (set (match_dup 0)
3551         (and:HI (match_dup 0)
3552                 (match_operand:HI 3 "const_int_operand" "")))]
3553   "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3554   [(set (match_dup 0)
3555         (and:HI (match_dup 0)
3556                 (const_int 255)))
3557    (parallel
3558      [(set (match_dup 0)
3559            (lshiftrt:HI (match_dup 0)
3560                         (match_dup 1)))
3561       (clobber (match_dup 2))])]
3562   "")
3563
3564 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3565
3566 (define_peephole2
3567   [(parallel [(set (match_operand:HI 0 "register_operand" "")
3568                    (ashift:HI (match_dup 0)
3569                               (match_operand:HI 1 "const_int_operand" "")))
3570               (clobber (match_operand:HI 2 "" ""))])
3571    (set (match_dup 0)
3572         (and:HI (match_dup 0)
3573                 (match_operand:HI 3 "const_int_operand" "")))]
3574   "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3575   [(set (match_dup 0)
3576         (and:HI (match_dup 0)
3577                 (const_int 255)))
3578    (parallel
3579      [(set (match_dup 0)
3580            (ashift:HI (match_dup 0)
3581                       (match_dup 1)))
3582       (clobber (match_dup 2))])]
3583   "")
3584
3585 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3586
3587 (define_peephole2
3588   [(parallel [(set (match_operand:SI 0 "register_operand" "")
3589                    (lshiftrt:SI (match_dup 0)
3590                                 (match_operand:SI 1 "const_int_operand" "")))
3591               (clobber (match_operand:SI 2 "" ""))])
3592    (set (match_dup 0)
3593         (and:SI (match_dup 0)
3594                 (match_operand:SI 3 "const_int_operand" "")))]
3595   "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3596   [(set (match_dup 0)
3597         (and:SI (match_dup 0)
3598                 (const_int 255)))
3599    (parallel
3600      [(set (match_dup 0)
3601            (lshiftrt:SI (match_dup 0)
3602                         (match_dup 1)))
3603       (clobber (match_dup 2))])]
3604   "")
3605
3606 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3607
3608 (define_peephole2
3609   [(parallel [(set (match_operand:SI 0 "register_operand" "")
3610                    (ashift:SI (match_dup 0)
3611                               (match_operand:SI 1 "const_int_operand" "")))
3612               (clobber (match_operand:SI 2 "" ""))])
3613    (set (match_dup 0)
3614         (and:SI (match_dup 0)
3615                 (match_operand:SI 3 "const_int_operand" "")))]
3616   "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3617   [(set (match_dup 0)
3618         (and:SI (match_dup 0)
3619                 (const_int 255)))
3620    (parallel
3621      [(set (match_dup 0)
3622            (ashift:SI (match_dup 0)
3623                       (match_dup 1)))
3624       (clobber (match_dup 2))])]
3625   "")
3626
3627 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
3628
3629 (define_peephole2
3630   [(parallel [(set (match_operand:SI 0 "register_operand" "")
3631                    (lshiftrt:SI (match_dup 0)
3632                                 (match_operand:SI 1 "const_int_operand" "")))
3633               (clobber (match_operand:SI 2 "" ""))])
3634    (set (match_dup 0)
3635         (and:SI (match_dup 0)
3636                 (match_operand:SI 3 "const_int_operand" "")))]
3637   "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
3638   [(set (match_dup 0)
3639         (and:SI (match_dup 0)
3640                 (const_int 65535)))
3641    (parallel
3642      [(set (match_dup 0)
3643            (lshiftrt:SI (match_dup 0)
3644                         (match_dup 1)))
3645       (clobber (match_dup 2))])]
3646   "")
3647
3648 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
3649
3650 (define_peephole2
3651   [(parallel [(set (match_operand:SI 0 "register_operand" "")
3652                    (ashift:SI (match_dup 0)
3653                               (match_operand:SI 1 "const_int_operand" "")))
3654               (clobber (match_operand:SI 2 "" ""))])
3655    (set (match_dup 0)
3656         (and:SI (match_dup 0)
3657                 (match_operand:SI 3 "const_int_operand" "")))]
3658   "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
3659   [(set (match_dup 0)
3660         (and:SI (match_dup 0)
3661                 (const_int 65535)))
3662    (parallel
3663      [(set (match_dup 0)
3664            (ashift:SI (match_dup 0)
3665                       (match_dup 1)))
3666       (clobber (match_dup 2))])]
3667   "")
3668
3669 ;; Convert a QImode push into an SImode push so that the
3670 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3671
3672 (define_peephole2
3673   [(parallel [(set (reg:SI SP_REG)
3674                    (plus:SI (reg:SI SP_REG) (const_int -4)))
3675               (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
3676                    (match_operand:QI 0 "register_operand" ""))])]
3677   "TARGET_H8300S && !TARGET_NORMAL_MODE"
3678   [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3679         (match_dup 0))]
3680   "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3681
3682 (define_peephole2
3683   [(parallel [(set (reg:HI SP_REG)
3684                    (plus:HI (reg:HI SP_REG) (const_int -4)))
3685               (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
3686                    (match_operand:QI 0 "register_operand" ""))])]
3687   "TARGET_H8300S && TARGET_NORMAL_MODE"
3688   [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3689         (match_dup 0))]
3690   "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3691
3692 ;; Convert a HImode push into an SImode push so that the
3693 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3694
3695 (define_peephole2
3696   [(parallel [(set (reg:SI SP_REG)
3697                    (plus:SI (reg:SI SP_REG) (const_int -4)))
3698               (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
3699                    (match_operand:HI 0 "register_operand" ""))])]
3700   "TARGET_H8300S && !TARGET_NORMAL_MODE"
3701   [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3702         (match_dup 0))]
3703   "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3704
3705 (define_peephole2
3706   [(parallel [(set (reg:HI SP_REG)
3707                    (plus:HI (reg:HI SP_REG) (const_int -4)))
3708               (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
3709                    (match_operand:HI 0 "register_operand" ""))])]
3710   "TARGET_H8300S && TARGET_NORMAL_MODE"
3711   [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3712         (match_dup 0))]
3713   "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3714
3715 ;; Cram four pushes into stm.l.
3716
3717 (define_peephole2
3718   [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3719         (match_operand:SI 0 "register_operand" ""))
3720    (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3721         (match_operand:SI 1 "register_operand" ""))
3722    (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3723         (match_operand:SI 2 "register_operand" ""))
3724    (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3725         (match_operand:SI 3 "register_operand" ""))]
3726   "TARGET_H8300S && !TARGET_NORMAL_MODE
3727    && h8300_regs_ok_for_stm (4, operands)"
3728   [(parallel [(set (reg:SI SP_REG)
3729                    (plus:SI (reg:SI SP_REG)
3730                             (const_int -16)))
3731               (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3732                    (match_dup 0))
3733               (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3734                    (match_dup 1))
3735               (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3736                    (match_dup 2))
3737               (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
3738                    (match_dup 3))])]
3739   "")
3740
3741 (define_peephole2
3742   [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3743         (match_operand:SI 0 "register_operand" ""))
3744    (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3745         (match_operand:SI 1 "register_operand" ""))
3746    (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3747         (match_operand:SI 2 "register_operand" ""))
3748    (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3749         (match_operand:SI 3 "register_operand" ""))]
3750   "TARGET_H8300S && TARGET_NORMAL_MODE
3751    && h8300_regs_ok_for_stm (4, operands)"
3752   [(parallel [(set (reg:HI SP_REG)
3753                    (plus:HI (reg:HI SP_REG)
3754                             (const_int -16)))
3755               (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
3756                    (match_dup 0))
3757               (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
3758                    (match_dup 1))
3759               (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
3760                    (match_dup 2))
3761               (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
3762                    (match_dup 3))])]
3763   "")
3764
3765 ;; Cram three pushes into stm.l.
3766
3767 (define_peephole2
3768   [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3769         (match_operand:SI 0 "register_operand" ""))
3770    (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3771         (match_operand:SI 1 "register_operand" ""))
3772    (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3773         (match_operand:SI 2 "register_operand" ""))]
3774   "TARGET_H8300S && !TARGET_NORMAL_MODE
3775    && h8300_regs_ok_for_stm (3, operands)"
3776   [(parallel [(set (reg:SI SP_REG)
3777                    (plus:SI (reg:SI SP_REG)
3778                             (const_int -12)))
3779               (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3780                    (match_dup 0))
3781               (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3782                    (match_dup 1))
3783               (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3784                    (match_dup 2))])]
3785   "")
3786
3787 (define_peephole2
3788   [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3789         (match_operand:SI 0 "register_operand" ""))
3790    (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3791         (match_operand:SI 1 "register_operand" ""))
3792    (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3793         (match_operand:SI 2 "register_operand" ""))]
3794   "TARGET_H8300S && TARGET_NORMAL_MODE
3795    && h8300_regs_ok_for_stm (3, operands)"
3796   [(parallel [(set (reg:HI SP_REG)
3797                    (plus:HI (reg:HI SP_REG)
3798                             (const_int -12)))
3799               (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
3800                    (match_dup 0))
3801               (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
3802                    (match_dup 1))
3803               (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
3804                    (match_dup 2))])]
3805   "")
3806
3807 ;; Cram two pushes into stm.l.
3808
3809 (define_peephole2
3810   [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3811         (match_operand:SI 0 "register_operand" ""))
3812    (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3813         (match_operand:SI 1 "register_operand" ""))]
3814   "TARGET_H8300S && !TARGET_NORMAL_MODE
3815    && h8300_regs_ok_for_stm (2, operands)"
3816   [(parallel [(set (reg:SI SP_REG)
3817                    (plus:SI (reg:SI SP_REG)
3818                             (const_int -8)))
3819               (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3820                    (match_dup 0))
3821               (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3822                    (match_dup 1))])]
3823   "")
3824
3825 (define_peephole2
3826   [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3827         (match_operand:SI 0 "register_operand" ""))
3828    (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3829         (match_operand:SI 1 "register_operand" ""))]
3830   "TARGET_H8300S && TARGET_NORMAL_MODE
3831    && h8300_regs_ok_for_stm (2, operands)"
3832   [(parallel [(set (reg:HI SP_REG)
3833                    (plus:HI (reg:HI SP_REG)
3834                             (const_int -8)))
3835               (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
3836                    (match_dup 0))
3837               (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
3838                    (match_dup 1))])]
3839   "")
3840
3841 ;; Turn
3842 ;;
3843 ;;   mov.w #2,r0
3844 ;;   add.w r7,r0  (6 bytes)
3845 ;;
3846 ;; into
3847 ;;
3848 ;;   mov.w r7,r0
3849 ;;   adds  #2,r0  (4 bytes)
3850
3851 (define_peephole2
3852   [(set (match_operand:HI 0 "register_operand" "")
3853         (match_operand:HI 1 "const_int_operand" ""))
3854    (set (match_dup 0)
3855         (plus:HI (match_dup 0)
3856                  (match_operand:HI 2 "register_operand" "")))]
3857   "REG_P (operands[0]) && REG_P (operands[2])
3858    && REGNO (operands[0]) != REGNO (operands[2])
3859    && (CONST_OK_FOR_J (INTVAL (operands[1]))
3860        || CONST_OK_FOR_L (INTVAL (operands[1]))
3861        || CONST_OK_FOR_N (INTVAL (operands[1])))"
3862   [(set (match_dup 0)
3863         (match_dup 2))
3864    (set (match_dup 0)
3865         (plus:HI (match_dup 0)
3866                  (match_dup 1)))]
3867   "")
3868
3869 ;; Turn
3870 ;;
3871 ;;   sub.l  er0,er0
3872 ;;   add.b  #4,r0l
3873 ;;   add.l  er7,er0  (6 bytes)
3874 ;;
3875 ;; into
3876 ;;
3877 ;;   mov.l  er7,er0
3878 ;;   adds   #4,er0   (4 bytes)
3879
3880 (define_peephole2
3881   [(set (match_operand:SI 0 "register_operand" "")
3882         (match_operand:SI 1 "const_int_operand" ""))
3883    (set (match_dup 0)
3884         (plus:SI (match_dup 0)
3885                  (match_operand:SI 2 "register_operand" "")))]
3886   "(TARGET_H8300H || TARGET_H8300S)
3887    && REG_P (operands[0]) && REG_P (operands[2])
3888    && REGNO (operands[0]) != REGNO (operands[2])
3889    && (CONST_OK_FOR_L (INTVAL (operands[1]))
3890        || CONST_OK_FOR_N (INTVAL (operands[1])))"
3891   [(set (match_dup 0)
3892         (match_dup 2))
3893    (set (match_dup 0)
3894         (plus:SI (match_dup 0)
3895                  (match_dup 1)))]
3896   "")
3897
3898 ;; Turn
3899 ;;
3900 ;;   mov.l er7,er0
3901 ;;   add.l #10,er0  (takes 8 bytes)
3902 ;;
3903 ;; into
3904 ;;
3905 ;;   sub.l er0,er0
3906 ;;   add.b #10,r0l
3907 ;;   add.l er7,er0  (takes 6 bytes)
3908
3909 (define_peephole2
3910   [(set (match_operand:SI 0 "register_operand" "")
3911         (match_operand:SI 1 "register_operand" ""))
3912    (set (match_dup 0)
3913         (plus:SI (match_dup 0)
3914                  (match_operand:SI 2 "const_int_operand" "")))]
3915   "(TARGET_H8300H || TARGET_H8300S)
3916    && REG_P (operands[0]) && REG_P (operands[1])
3917    && REGNO (operands[0]) != REGNO (operands[1])
3918    && !CONST_OK_FOR_L (INTVAL (operands[2]))
3919    && !CONST_OK_FOR_N (INTVAL (operands[2]))
3920    && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
3921        || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
3922        || INTVAL (operands[2]) == 0xffff
3923        || INTVAL (operands[2]) == 0xfffe)"
3924   [(set (match_dup 0)
3925         (match_dup 2))
3926    (set (match_dup 0)
3927         (plus:SI (match_dup 0)
3928                  (match_dup 1)))]
3929   "")
3930
3931 ;; Turn
3932 ;;
3933 ;;   subs   #1,er4
3934 ;;   mov.w  r4,r4
3935 ;;   bne    .L2028
3936 ;;
3937 ;; into
3938 ;;
3939 ;;   dec.w  #1,r4
3940 ;;   bne    .L2028
3941
3942 (define_peephole2
3943   [(set (match_operand:HI 0 "register_operand" "")
3944         (plus:HI (match_dup 0)
3945                  (match_operand 1 "incdec_operand" "")))
3946    (set (cc0)
3947         (match_dup 0))
3948    (set (pc)
3949         (if_then_else (match_operator 3 "eqne_operator"
3950                         [(cc0) (const_int 0)])
3951                       (label_ref (match_operand 2 "" ""))
3952                       (pc)))]
3953   "TARGET_H8300H || TARGET_H8300S"
3954   [(set (match_operand:HI 0 "register_operand" "")
3955         (unspec:HI [(match_dup 0)
3956                     (match_dup 1)]
3957                    UNSPEC_INCDEC))
3958    (set (cc0)
3959         (match_dup 0))
3960    (set (pc)
3961         (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
3962                       (label_ref (match_dup 2))
3963                       (pc)))]
3964   "")
3965
3966 ;; The SImode version of the previous pattern.
3967
3968 (define_peephole2
3969   [(set (match_operand:SI 0 "register_operand" "")
3970         (plus:SI (match_dup 0)
3971                  (match_operand 1 "incdec_operand" "")))
3972    (set (cc0)
3973         (match_dup 0))
3974    (set (pc)
3975         (if_then_else (match_operator 3 "eqne_operator"
3976                         [(cc0) (const_int 0)])
3977                       (label_ref (match_operand 2 "" ""))
3978                       (pc)))]
3979   "TARGET_H8300H || TARGET_H8300S"
3980   [(set (match_operand:SI 0 "register_operand" "")
3981         (unspec:SI [(match_dup 0)
3982                     (match_dup 1)]
3983                    UNSPEC_INCDEC))
3984    (set (cc0)
3985         (match_dup 0))
3986    (set (pc)
3987         (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
3988                       (label_ref (match_dup 2))
3989                       (pc)))]
3990   "")
3991
3992 (define_peephole2
3993   [(parallel [(set (cc0)
3994                    (zero_extract:SI (match_operand:QI 0 "register_operand" "")
3995                                     (const_int 1)
3996                                     (const_int 7)))
3997               (clobber (scratch:QI))])
3998    (set (pc)
3999         (if_then_else (match_operator 1 "eqne_operator"
4000                         [(cc0) (const_int 0)])
4001                       (label_ref (match_operand 2 "" ""))
4002                       (pc)))]
4003   "(TARGET_H8300H || TARGET_H8300S)"
4004   [(set (cc0)
4005         (match_dup 0))
4006    (set (pc)
4007         (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4008                       (label_ref (match_dup 2))
4009                       (pc)))]
4010   "operands[3] = ((GET_CODE (operands[1]) == EQ)
4011                   ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
4012                   : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));")
4013
4014 ;; The next three peephole2's will try to transform
4015 ;;
4016 ;;   mov.b A,r0l    (or mov.l A,er0)
4017 ;;   and.l #CST,er0
4018 ;;
4019 ;; into
4020 ;;
4021 ;;   sub.l er0
4022 ;;   mov.b A,r0l
4023 ;;   and.b #CST,r0l (if CST is not 255)
4024
4025 (define_peephole2
4026   [(set (match_operand:QI 0 "register_operand" "")
4027         (match_operand:QI 1 "general_operand" ""))
4028    (set (match_operand:SI 2 "register_operand" "")
4029         (and:SI (match_dup 2)
4030                 (const_int 255)))]
4031   "(TARGET_H8300H || TARGET_H8300S)
4032    && !reg_overlap_mentioned_p (operands[2], operands[1])
4033    && REGNO (operands[0]) == REGNO (operands[2])"
4034   [(set (match_dup 2)
4035         (const_int 0))
4036    (set (strict_low_part (match_dup 0))
4037         (match_dup 1))]
4038   "")
4039
4040 (define_peephole2
4041   [(set (match_operand:SI 0 "register_operand" "")
4042         (match_operand:SI 1 "general_operand" ""))
4043    (set (match_dup 0)
4044         (and:SI (match_dup 0)
4045                 (const_int 255)))]
4046   "(TARGET_H8300H || TARGET_H8300S)
4047    && !reg_overlap_mentioned_p (operands[0], operands[1])
4048    && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
4049   [(set (match_dup 0)
4050         (const_int 0))
4051    (set (strict_low_part (match_dup 2))
4052         (match_dup 3))]
4053   "operands[2] = gen_lowpart (QImode, operands[0]);
4054    operands[3] = gen_lowpart (QImode, operands[1]);")
4055
4056 (define_peephole2
4057   [(set (match_operand 0 "register_operand" "")
4058         (match_operand 1 "general_operand" ""))
4059    (set (match_operand:SI 2 "register_operand" "")
4060         (and:SI (match_dup 2)
4061                 (match_operand:SI 3 "const_int_qi_operand" "")))]
4062   "(TARGET_H8300H || TARGET_H8300S)
4063    && (GET_MODE (operands[0]) == QImode
4064        || GET_MODE (operands[0]) == HImode
4065        || GET_MODE (operands[0]) == SImode)
4066    && GET_MODE (operands[0]) == GET_MODE (operands[1])
4067    && REGNO (operands[0]) == REGNO (operands[2])
4068    && !reg_overlap_mentioned_p (operands[2], operands[1])
4069    && !(GET_MODE (operands[1]) != QImode
4070         && GET_CODE (operands[1]) == MEM
4071         && MEM_VOLATILE_P (operands[1]))"
4072   [(set (match_dup 2)
4073         (const_int 0))
4074    (set (strict_low_part (match_dup 4))
4075         (match_dup 5))
4076    (set (match_dup 2)
4077         (and:SI (match_dup 2)
4078                 (match_dup 6)))]
4079   "operands[4] = gen_lowpart (QImode, operands[0]);
4080    operands[5] = gen_lowpart (QImode, operands[1]);
4081    operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));")
4082
4083 (define_peephole2
4084   [(set (match_operand:SI 0 "register_operand" "")
4085         (match_operand:SI 1 "register_operand" ""))
4086    (set (match_dup 0)
4087         (and:SI (match_dup 0)
4088                 (const_int 65280)))]
4089   "(TARGET_H8300H || TARGET_H8300S)
4090    && !reg_overlap_mentioned_p (operands[0], operands[1])"
4091   [(set (match_dup 0)
4092         (const_int 0))
4093    (set (zero_extract:SI (match_dup 0)
4094                          (const_int 8)
4095                          (const_int 8))
4096         (lshiftrt:SI (match_dup 1)
4097                      (const_int 8)))]
4098   "")
4099
4100 ;; If a load of mem:SI is followed by an AND that turns off the upper
4101 ;; half, then we can load mem:HI instead.
4102
4103 (define_peephole2
4104   [(set (match_operand:SI 0 "register_operand" "")
4105         (match_operand:SI 1 "memory_operand" ""))
4106    (set (match_dup 0)
4107         (and:SI (match_dup 0)
4108                 (match_operand:SI 2 "const_int_operand" "")))]
4109   "(TARGET_H8300H || TARGET_H8300S)
4110    && !MEM_VOLATILE_P (operands[1])
4111    && (INTVAL (operands[2]) & ~0xffff) == 0
4112    && INTVAL (operands[2]) != 255"
4113   [(set (match_dup 3)
4114         (match_dup 4))
4115    (set (match_dup 0)
4116         (and:SI (match_dup 0)
4117                 (match_dup 2)))]
4118   "operands[3] = gen_lowpart (HImode, operands[0]);
4119    operands[4] = gen_lowpart (HImode, operands[1]);")
4120
4121 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
4122 ;; the equivalent with shorter sequences.  Here is the summary.  Cases
4123 ;; are grouped for each define_peephole2.
4124 ;;
4125 ;; reg  const_int                   use     insn
4126 ;; --------------------------------------------------------
4127 ;; dead    -2                       eq/ne   inc.l
4128 ;; dead    -1                       eq/ne   inc.l
4129 ;; dead     1                       eq/ne   dec.l
4130 ;; dead     2                       eq/ne   dec.l
4131 ;;
4132 ;; dead     1                       ge/lt shar.l
4133 ;; dead     3 (H8S)                 ge/lt shar.l
4134 ;;
4135 ;; dead     1                       geu/ltu shar.l
4136 ;; dead     3 (H8S)                 geu/ltu shar.l
4137 ;;
4138 ;; ----   255                       ge/lt mov.b
4139 ;;
4140 ;; ----   255                       geu/ltu mov.b
4141
4142 ;; Transform
4143 ;;
4144 ;;      cmp.w   #1,r0
4145 ;;      bne     .L1
4146 ;;
4147 ;; into
4148 ;;
4149 ;;      dec.w   #1,r0
4150 ;;      bne     .L1
4151
4152 (define_peephole2
4153   [(set (cc0)
4154         (compare (match_operand:HI 0 "register_operand" "")
4155                  (match_operand:HI 1 "incdec_operand" "")))
4156    (set (pc)
4157         (if_then_else (match_operator 3 "eqne_operator"
4158                         [(cc0) (const_int 0)])
4159                       (label_ref (match_operand 2 "" ""))
4160                       (pc)))]
4161   "(TARGET_H8300H || TARGET_H8300S)
4162    && peep2_reg_dead_p (1, operands[0])"
4163   [(set (match_dup 0)
4164         (unspec:HI [(match_dup 0)
4165                     (match_dup 4)]
4166                    UNSPEC_INCDEC))
4167    (set (cc0)
4168         (match_dup 0))
4169    (set (pc)
4170         (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4171                       (label_ref (match_dup 2))
4172                       (pc)))]
4173   "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4174
4175 ;; Transform
4176 ;;
4177 ;;      cmp.w   #1,r0
4178 ;;      bgt     .L1
4179 ;;
4180 ;; into
4181 ;;
4182 ;;      shar.w  r0
4183 ;;      bgt     .L1
4184
4185 (define_peephole2
4186   [(set (cc0)
4187         (compare (match_operand:HI 0 "register_operand" "")
4188                  (match_operand:HI 1 "const_int_operand" "")))
4189    (set (pc)
4190         (if_then_else (match_operator 2 "gtle_operator"
4191                         [(cc0) (const_int 0)])
4192                       (label_ref (match_operand 3 "" ""))
4193                       (pc)))]
4194   "(TARGET_H8300H || TARGET_H8300S)
4195    && peep2_reg_dead_p (1, operands[0])
4196    && (INTVAL (operands[1]) == 1
4197         || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4198   [(parallel [(set (match_dup 0)
4199                    (ashiftrt:HI (match_dup 0)
4200                                 (match_dup 4)))
4201               (clobber (scratch:QI))])
4202    (set (cc0)
4203         (match_dup 0))
4204    (set (pc)
4205         (if_then_else (match_dup 2)
4206                       (label_ref (match_dup 3))
4207                       (pc)))]
4208   "operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4209
4210 ;; Transform
4211 ;;
4212 ;;      cmp.w   #1,r0
4213 ;;      bhi     .L1
4214 ;;
4215 ;; into
4216 ;;
4217 ;;      shar.w  r0
4218 ;;      bne     .L1
4219
4220 (define_peephole2
4221   [(set (cc0)
4222         (compare (match_operand:HI 0 "register_operand" "")
4223                  (match_operand:HI 1 "const_int_operand" "")))
4224    (set (pc)
4225         (if_then_else (match_operator 2 "gtuleu_operator"
4226                         [(cc0) (const_int 0)])
4227                       (label_ref (match_operand 3 "" ""))
4228                       (pc)))]
4229   "(TARGET_H8300H || TARGET_H8300S)
4230    && peep2_reg_dead_p (1, operands[0])
4231    && (INTVAL (operands[1]) == 1
4232         || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4233   [(parallel [(set (match_dup 0)
4234                    (ashiftrt:HI (match_dup 0)
4235                                 (match_dup 4)))
4236               (clobber (scratch:QI))])
4237    (set (cc0)
4238         (match_dup 0))
4239    (set (pc)
4240         (if_then_else (match_dup 5)
4241                       (label_ref (match_dup 3))
4242                       (pc)))]
4243 {
4244   operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
4245   operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
4246                                 VOIDmode,
4247                                 cc0_rtx,
4248                                 const0_rtx);
4249 })
4250
4251 ;; Transform
4252 ;;
4253 ;;      cmp.w   #255,r0
4254 ;;      bgt     .L1
4255 ;;
4256 ;; into
4257 ;;
4258 ;;      mov.b   r0h,r0h
4259 ;;      bgt     .L1
4260
4261 (define_peephole2
4262   [(set (cc0)
4263         (compare (match_operand:HI 0 "register_operand" "")
4264                  (const_int 255)))
4265    (set (pc)
4266         (if_then_else (match_operator 1 "gtle_operator"
4267                         [(cc0) (const_int 0)])
4268                       (label_ref (match_operand 2 "" ""))
4269                       (pc)))]
4270   "TARGET_H8300H || TARGET_H8300S"
4271   [(set (cc0)
4272         (and:HI (match_dup 0)
4273                 (const_int -256)))
4274    (set (pc)
4275         (if_then_else (match_dup 1)
4276                       (label_ref (match_dup 2))
4277                       (pc)))]
4278   "")
4279
4280 ;; Transform
4281 ;;
4282 ;;      cmp.w   #255,r0
4283 ;;      bhi     .L1
4284 ;;
4285 ;; into
4286 ;;
4287 ;;      mov.b   r0h,r0h
4288 ;;      bne     .L1
4289
4290 (define_peephole2
4291   [(set (cc0)
4292         (compare (match_operand:HI 0 "register_operand" "")
4293                  (const_int 255)))
4294    (set (pc)
4295         (if_then_else (match_operator 1 "gtuleu_operator"
4296                         [(cc0) (const_int 0)])
4297                       (label_ref (match_operand 2 "" ""))
4298                       (pc)))]
4299   "TARGET_H8300H || TARGET_H8300S"
4300   [(set (cc0)
4301         (and:HI (match_dup 0)
4302                 (const_int -256)))
4303    (set (pc)
4304         (if_then_else (match_dup 3)
4305                       (label_ref (match_dup 2))
4306                       (pc)))]
4307 {
4308   operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
4309                                 VOIDmode,
4310                                 cc0_rtx,
4311                                 const0_rtx);
4312 })
4313
4314 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
4315 ;; the equivalent with shorter sequences.  Here is the summary.  Cases
4316 ;; are grouped for each define_peephole2.
4317 ;;
4318 ;; reg  const_int                   use     insn
4319 ;; --------------------------------------------------------
4320 ;; live    -2                       eq/ne   copy and inc.l
4321 ;; live    -1                       eq/ne   copy and inc.l
4322 ;; live     1                       eq/ne   copy and dec.l
4323 ;; live     2                       eq/ne   copy and dec.l
4324 ;;
4325 ;; dead    -2                       eq/ne   inc.l
4326 ;; dead    -1                       eq/ne   inc.l
4327 ;; dead     1                       eq/ne   dec.l
4328 ;; dead     2                       eq/ne   dec.l
4329 ;;
4330 ;; dead -131072                     eq/ne   inc.w and test
4331 ;; dead  -65536                     eq/ne   inc.w and test
4332 ;; dead   65536                     eq/ne   dec.w and test
4333 ;; dead  131072                     eq/ne   dec.w and test
4334 ;;
4335 ;; dead 0x000000?? except 1 and 2   eq/ne   xor.b and test
4336 ;; dead 0x0000??00                  eq/ne   xor.b and test
4337 ;; dead 0x0000ffff                  eq/ne   not.w and test
4338 ;;
4339 ;; dead 0xffffff?? except -1 and -2 eq/ne   xor.b and not.l
4340 ;; dead 0xffff??ff                  eq/ne   xor.b and not.l
4341 ;; dead 0x40000000 (H8S)            eq/ne   rotl.l and dec.l
4342 ;; dead 0x80000000                  eq/ne   rotl.l and dec.l
4343 ;;
4344 ;; live     1                       ge/lt copy and shar.l
4345 ;; live     3 (H8S)                 ge/lt copy and shar.l
4346 ;;
4347 ;; live     1                       geu/ltu copy and shar.l
4348 ;; live     3 (H8S)                 geu/ltu copy and shar.l
4349 ;;
4350 ;; dead     1                       ge/lt shar.l
4351 ;; dead     3 (H8S)                 ge/lt shar.l
4352 ;;
4353 ;; dead     1                       geu/ltu shar.l
4354 ;; dead     3 (H8S)                 geu/ltu shar.l
4355 ;;
4356 ;; dead     3 (H8/300H)             ge/lt and.b and test
4357 ;; dead     7                       ge/lt and.b and test
4358 ;; dead    15                       ge/lt and.b and test
4359 ;; dead    31                       ge/lt and.b and test
4360 ;; dead    63                       ge/lt and.b and test
4361 ;; dead   127                       ge/lt and.b and test
4362 ;; dead   255                       ge/lt and.b and test
4363 ;;
4364 ;; dead     3 (H8/300H)             geu/ltu and.b and test
4365 ;; dead     7                       geu/ltu and.b and test
4366 ;; dead    15                       geu/ltu and.b and test
4367 ;; dead    31                       geu/ltu and.b and test
4368 ;; dead    63                       geu/ltu and.b and test
4369 ;; dead   127                       geu/ltu and.b and test
4370 ;; dead   255                       geu/ltu and.b and test
4371 ;;
4372 ;; ---- 65535                       ge/lt mov.w
4373 ;;
4374 ;; ---- 65535                       geu/ltu mov.w
4375
4376 ;; Transform
4377 ;;
4378 ;;      cmp.l   #1,er0
4379 ;;      beq     .L1
4380 ;;
4381 ;; into
4382 ;;
4383 ;;      dec.l   #1,er0
4384 ;;      beq     .L1
4385
4386 (define_peephole2
4387   [(set (cc0)
4388         (compare (match_operand:SI 0 "register_operand" "")
4389                  (match_operand:SI 1 "incdec_operand" "")))
4390    (set (pc)
4391         (if_then_else (match_operator 3 "eqne_operator"
4392                         [(cc0) (const_int 0)])
4393                       (label_ref (match_operand 2 "" ""))
4394                       (pc)))]
4395   "(TARGET_H8300H || TARGET_H8300S)
4396    && peep2_reg_dead_p (1, operands[0])"
4397   [(set (match_dup 0)
4398         (unspec:SI [(match_dup 0)
4399                     (match_dup 4)]
4400                    UNSPEC_INCDEC))
4401    (set (cc0)
4402         (match_dup 0))
4403    (set (pc)
4404         (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4405                       (label_ref (match_dup 2))
4406                       (pc)))]
4407   "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4408
4409 ;; Transform
4410 ;;
4411 ;;      cmp.l   #65536,er0
4412 ;;      beq     .L1
4413 ;;
4414 ;; into
4415 ;;
4416 ;;      dec.l   #1,e0
4417 ;;      beq     .L1
4418
4419 (define_peephole2
4420   [(set (cc0)
4421         (compare (match_operand:SI 0 "register_operand" "")
4422                  (match_operand:SI 1 "const_int_operand" "")))
4423    (set (pc)
4424         (if_then_else (match_operator 3 "eqne_operator"
4425                         [(cc0) (const_int 0)])
4426                       (label_ref (match_operand 2 "" ""))
4427                       (pc)))]
4428   "(TARGET_H8300H || TARGET_H8300S)
4429    && peep2_reg_dead_p (1, operands[0])
4430    && (INTVAL (operands[1]) == -131072
4431        || INTVAL (operands[1]) == -65536
4432        || INTVAL (operands[1]) == 65536
4433        || INTVAL (operands[1]) == 131072)"
4434   [(set (match_dup 0)
4435         (plus:SI (match_dup 0)
4436                  (match_dup 4)))
4437    (set (cc0)
4438         (match_dup 0))
4439    (set (pc)
4440         (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4441                       (label_ref (match_dup 2))
4442                       (pc)))]
4443   "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4444
4445 ;; Transform
4446 ;;
4447 ;;      cmp.l   #100,er0
4448 ;;      beq     .L1
4449 ;;
4450 ;; into
4451 ;;
4452 ;;      xor.b   #100,er0
4453 ;;      mov.l   er0,er0
4454 ;;      beq     .L1
4455
4456 (define_peephole2
4457   [(set (cc0)
4458         (compare (match_operand:SI 0 "register_operand" "")
4459                  (match_operand:SI 1 "const_int_operand" "")))
4460    (set (pc)
4461         (if_then_else (match_operator 3 "eqne_operator"
4462                         [(cc0) (const_int 0)])
4463                       (label_ref (match_operand 2 "" ""))
4464                       (pc)))]
4465   "(TARGET_H8300H || TARGET_H8300S)
4466    && peep2_reg_dead_p (1, operands[0])
4467    && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
4468        || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
4469        || INTVAL (operands[1]) == 0x0000ffff)
4470    && INTVAL (operands[1]) != 1
4471    && INTVAL (operands[1]) != 2"
4472   [(set (match_dup 0)
4473         (xor:SI (match_dup 0)
4474                 (match_dup 1)))
4475    (set (cc0)
4476         (match_dup 0))
4477    (set (pc)
4478         (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4479                       (label_ref (match_dup 2))
4480                       (pc)))]
4481   "")
4482
4483 ;; Transform
4484 ;;
4485 ;;      cmp.l   #-100,er0
4486 ;;      beq     .L1
4487 ;;
4488 ;; into
4489 ;;
4490 ;;      xor.b   #99,er0
4491 ;;      not.l   er0
4492 ;;      beq     .L1
4493
4494 (define_peephole2
4495   [(set (cc0)
4496         (compare (match_operand:SI 0 "register_operand" "")
4497                  (match_operand:SI 1 "const_int_operand" "")))
4498    (set (pc)
4499         (if_then_else (match_operator 3 "eqne_operator"
4500                         [(cc0) (const_int 0)])
4501                       (label_ref (match_operand 2 "" ""))
4502                       (pc)))]
4503   "(TARGET_H8300H || TARGET_H8300S)
4504    && peep2_reg_dead_p (1, operands[0])
4505    && ((INTVAL (operands[1]) | 0x00ff) == -1
4506         || (INTVAL (operands[1]) | 0xff00) == -1)
4507    && INTVAL (operands[1]) != -1
4508    && INTVAL (operands[1]) != -2"
4509   [(set (match_dup 0)
4510         (xor:SI (match_dup 0)
4511                 (match_dup 4)))
4512    (set (match_dup 0)
4513         (not:SI (match_dup 0)))
4514    (set (cc0)
4515         (match_dup 0))
4516    (set (pc)
4517         (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4518                       (label_ref (match_dup 2))
4519                       (pc)))]
4520   "operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);")
4521
4522 ;; Transform
4523 ;;
4524 ;;      cmp.l   #-2147483648,er0
4525 ;;      beq     .L1
4526 ;;
4527 ;; into
4528 ;;
4529 ;;      rotl.l  er0
4530 ;;      dec.l   #1,er0
4531 ;;      beq     .L1
4532
4533 (define_peephole2
4534   [(set (cc0)
4535         (compare (match_operand:SI 0 "register_operand" "")
4536                  (match_operand:SI 1 "const_int_operand" "")))
4537    (set (pc)
4538         (if_then_else (match_operator 3 "eqne_operator"
4539                         [(cc0) (const_int 0)])
4540                       (label_ref (match_operand 2 "" ""))
4541                       (pc)))]
4542   "(TARGET_H8300H || TARGET_H8300S)
4543    && peep2_reg_dead_p (1, operands[0])
4544    && (INTVAL (operands[1]) == -2147483647 - 1
4545        || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
4546   [(set (match_dup 0)
4547         (rotate:SI (match_dup 0)
4548                    (match_dup 4)))
4549    (set (match_dup 0)
4550         (unspec:SI [(match_dup 0)
4551                     (const_int -1)]
4552                    UNSPEC_INCDEC))
4553    (set (cc0)
4554         (match_dup 0))
4555    (set (pc)
4556         (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4557                       (label_ref (match_dup 2))
4558                       (pc)))]
4559   "operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2);")
4560
4561 ;; Transform
4562 ;;
4563 ;;      cmp.l   #1,er0
4564 ;;      bgt     .L1
4565 ;;
4566 ;; into
4567 ;;
4568 ;;      mov.l   er0,er1
4569 ;;      shar.l  er1
4570 ;;      bgt     .L1
4571
4572 ;; We avoid this transformation if we see more than one copy of the
4573 ;; same compare insn immediately before this one.
4574
4575 (define_peephole2
4576   [(match_scratch:SI 4 "r")
4577    (set (cc0)
4578         (compare (match_operand:SI 0 "register_operand" "")
4579                  (match_operand:SI 1 "const_int_operand" "")))
4580    (set (pc)
4581         (if_then_else (match_operator 2 "gtle_operator"
4582                         [(cc0) (const_int 0)])
4583                       (label_ref (match_operand 3 "" ""))
4584                       (pc)))]
4585   "(TARGET_H8300H || TARGET_H8300S)
4586    && !peep2_reg_dead_p (1, operands[0])
4587    && (INTVAL (operands[1]) == 1
4588         || (TARGET_H8300S && INTVAL (operands[1]) == 3))
4589    && !same_cmp_preceding_p (insn)"
4590   [(set (match_dup 4)
4591         (match_dup 0))
4592    (parallel [(set (match_dup 4)
4593                    (ashiftrt:SI (match_dup 4)
4594                                 (match_dup 5)))
4595               (clobber (scratch:QI))])
4596    (set (cc0)
4597         (match_dup 4))
4598    (set (pc)
4599         (if_then_else (match_dup 2)
4600                       (label_ref (match_dup 3))
4601                       (pc)))]
4602   "operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4603
4604 ;; Transform
4605 ;;
4606 ;;      cmp.l   #1,er0
4607 ;;      bhi     .L1
4608 ;;
4609 ;; into
4610 ;;
4611 ;;      mov.l   er0,er1
4612 ;;      shar.l  er1
4613 ;;      bne     .L1
4614
4615 ;; We avoid this transformation if we see more than one copy of the
4616 ;; same compare insn immediately before this one.
4617
4618 (define_peephole2
4619   [(match_scratch:SI 4 "r")
4620    (set (cc0)
4621         (compare (match_operand:SI 0 "register_operand" "")
4622                  (match_operand:SI 1 "const_int_operand" "")))
4623    (set (pc)
4624         (if_then_else (match_operator 2 "gtuleu_operator"
4625                         [(cc0) (const_int 0)])
4626                       (label_ref (match_operand 3 "" ""))
4627                       (pc)))]
4628   "(TARGET_H8300H || TARGET_H8300S)
4629    && !peep2_reg_dead_p (1, operands[0])
4630    && (INTVAL (operands[1]) == 1
4631         || (TARGET_H8300S && INTVAL (operands[1]) == 3))
4632    && !same_cmp_preceding_p (insn)"
4633   [(set (match_dup 4)
4634         (match_dup 0))
4635    (parallel [(set (match_dup 4)
4636                    (ashiftrt:SI (match_dup 4)
4637                                 (match_dup 5)))
4638               (clobber (scratch:QI))])
4639    (set (cc0)
4640         (match_dup 4))
4641    (set (pc)
4642         (if_then_else (match_dup 6)
4643                       (label_ref (match_dup 3))
4644                       (pc)))]
4645 {
4646   operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
4647   operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
4648                                 VOIDmode,
4649                                 cc0_rtx,
4650                                 const0_rtx);
4651 })
4652
4653 ;; Transform
4654 ;;
4655 ;;      cmp.l   #1,er0
4656 ;;      bgt     .L1
4657 ;;
4658 ;; into
4659 ;;
4660 ;;      shar.l  er0
4661 ;;      bgt     .L1
4662
4663 (define_peephole2
4664   [(set (cc0)
4665         (compare (match_operand:SI 0 "register_operand" "")
4666                  (match_operand:SI 1 "const_int_operand" "")))
4667    (set (pc)
4668         (if_then_else (match_operator 2 "gtle_operator"
4669                         [(cc0) (const_int 0)])
4670                       (label_ref (match_operand 3 "" ""))
4671                       (pc)))]
4672   "(TARGET_H8300H || TARGET_H8300S)
4673    && peep2_reg_dead_p (1, operands[0])
4674    && (INTVAL (operands[1]) == 1
4675         || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4676   [(parallel [(set (match_dup 0)
4677                    (ashiftrt:SI (match_dup 0)
4678                                 (match_dup 4)))
4679               (clobber (scratch:QI))])
4680    (set (cc0)
4681         (match_dup 0))
4682    (set (pc)
4683         (if_then_else (match_dup 2)
4684                       (label_ref (match_dup 3))
4685                       (pc)))]
4686   "operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4687
4688 ;; Transform
4689 ;;
4690 ;;      cmp.l   #1,er0
4691 ;;      bhi     .L1
4692 ;;
4693 ;; into
4694 ;;
4695 ;;      shar.l  er0
4696 ;;      bne     .L1
4697
4698 (define_peephole2
4699   [(set (cc0)
4700         (compare (match_operand:SI 0 "register_operand" "")
4701                  (match_operand:SI 1 "const_int_operand" "")))
4702    (set (pc)
4703         (if_then_else (match_operator 2 "gtuleu_operator"
4704                         [(cc0) (const_int 0)])
4705                       (label_ref (match_operand 3 "" ""))
4706                       (pc)))]
4707   "(TARGET_H8300H || TARGET_H8300S)
4708    && peep2_reg_dead_p (1, operands[0])
4709    && (INTVAL (operands[1]) == 1
4710         || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4711   [(parallel [(set (match_dup 0)
4712                    (ashiftrt:SI (match_dup 0)
4713                                 (match_dup 4)))
4714               (clobber (scratch:QI))])
4715    (set (cc0)
4716         (match_dup 0))
4717    (set (pc)
4718         (if_then_else (match_dup 5)
4719                       (label_ref (match_dup 3))
4720                       (pc)))]
4721 {
4722   operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
4723   operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
4724                                 VOIDmode,
4725                                 cc0_rtx,
4726                                 const0_rtx);
4727 })
4728
4729 ;; Transform
4730 ;;
4731 ;;      cmp.l   #15,er0
4732 ;;      bgt     .L1
4733 ;;
4734 ;; into
4735 ;;
4736 ;;      and     #240,r0l
4737 ;;      mov.l   er0,er0
4738 ;;      bgt     .L1
4739
4740 (define_peephole2
4741   [(set (cc0)
4742         (compare (match_operand:SI 0 "register_operand" "")
4743                  (match_operand:SI 1 "const_int_operand" "")))
4744    (set (pc)
4745         (if_then_else (match_operator 2 "gtle_operator"
4746                         [(cc0) (const_int 0)])
4747                       (label_ref (match_operand 3 "" ""))
4748                       (pc)))]
4749   "(TARGET_H8300H || TARGET_H8300S)
4750    && peep2_reg_dead_p (1, operands[0])
4751    && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
4752        || INTVAL (operands[1]) == 7
4753        || INTVAL (operands[1]) == 15
4754        || INTVAL (operands[1]) == 31
4755        || INTVAL (operands[1]) == 63
4756        || INTVAL (operands[1]) == 127
4757        || INTVAL (operands[1]) == 255)"
4758   [(set (match_dup 0)
4759         (and:SI (match_dup 0)
4760                 (match_dup 4)))
4761    (set (cc0)
4762         (match_dup 0))
4763    (set (pc)
4764         (if_then_else (match_dup 2)
4765                       (label_ref (match_dup 3))
4766                       (pc)))]
4767   "operands[4] = GEN_INT (~INTVAL (operands[1]));")
4768
4769 ;; Transform
4770 ;;
4771 ;;      cmp.l   #15,er0
4772 ;;      bhi     .L1
4773 ;;
4774 ;; into
4775 ;;
4776 ;;      and     #240,r0l
4777 ;;      mov.l   er0,er0
4778 ;;      bne     .L1
4779
4780 (define_peephole2
4781   [(set (cc0)
4782         (compare (match_operand:SI 0 "register_operand" "")
4783                  (match_operand:SI 1 "const_int_operand" "")))
4784    (set (pc)
4785         (if_then_else (match_operator 2 "gtuleu_operator"
4786                         [(cc0) (const_int 0)])
4787                       (label_ref (match_operand 3 "" ""))
4788                       (pc)))]
4789   "(TARGET_H8300H || TARGET_H8300S)
4790    && peep2_reg_dead_p (1, operands[0])
4791    && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
4792        || INTVAL (operands[1]) == 7
4793        || INTVAL (operands[1]) == 15
4794        || INTVAL (operands[1]) == 31
4795        || INTVAL (operands[1]) == 63
4796        || INTVAL (operands[1]) == 127
4797        || INTVAL (operands[1]) == 255)"
4798   [(set (match_dup 0)
4799         (and:SI (match_dup 0)
4800                 (match_dup 4)))
4801    (set (cc0)
4802         (match_dup 0))
4803    (set (pc)
4804         (if_then_else (match_dup 5)
4805                       (label_ref (match_dup 3))
4806                       (pc)))]
4807 {
4808   operands[4] = GEN_INT (~INTVAL (operands[1]));
4809   operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
4810                                 VOIDmode,
4811                                 cc0_rtx,
4812                                 const0_rtx);
4813 })
4814
4815 ;; Transform
4816 ;;
4817 ;;      cmp.l   #65535,er0
4818 ;;      bgt     .L1
4819 ;;
4820 ;; into
4821 ;;
4822 ;;      mov.l   e0,e0
4823 ;;      bgt     .L1
4824
4825 (define_peephole2
4826   [(set (cc0)
4827         (compare (match_operand:SI 0 "register_operand" "")
4828                  (const_int 65535)))
4829    (set (pc)
4830         (if_then_else (match_operator 1 "gtle_operator"
4831                         [(cc0) (const_int 0)])
4832                       (label_ref (match_operand 2 "" ""))
4833                       (pc)))]
4834   "TARGET_H8300H || TARGET_H8300S"
4835   [(set (cc0)
4836         (and:SI (match_dup 0)
4837                 (const_int -65536)))
4838    (set (pc)
4839         (if_then_else (match_dup 1)
4840                       (label_ref (match_dup 2))
4841                       (pc)))]
4842   "")
4843
4844 ;; Transform
4845 ;;
4846 ;;      cmp.l   #65535,er0
4847 ;;      bhi     .L1
4848 ;;
4849 ;; into
4850 ;;
4851 ;;      mov.l   e0,e0
4852 ;;      bne     .L1
4853
4854 (define_peephole2
4855   [(set (cc0)
4856         (compare (match_operand:SI 0 "register_operand" "")
4857                  (const_int 65535)))
4858    (set (pc)
4859         (if_then_else (match_operator 1 "gtuleu_operator"
4860                         [(cc0) (const_int 0)])
4861                       (label_ref (match_operand 2 "" ""))
4862                       (pc)))]
4863   "TARGET_H8300H || TARGET_H8300S"
4864   [(set (cc0)
4865         (and:SI (match_dup 0)
4866                 (const_int -65536)))
4867    (set (pc)
4868         (if_then_else (match_dup 3)
4869                       (label_ref (match_dup 2))
4870                       (pc)))]
4871 {
4872   operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
4873                                 VOIDmode,
4874                                 cc0_rtx,
4875                                 const0_rtx);
4876 })
4877
4878 ;; Transform
4879 ;;
4880 ;;      cmp.l   #1,er0
4881 ;;      beq     .L1
4882 ;;
4883 ;; into
4884 ;;
4885 ;;      mov.l   er0,er1
4886 ;;      dec.l   #1,er1
4887 ;;      beq     .L1
4888
4889 ;; We avoid this transformation if we see more than one copy of the
4890 ;; same compare insn.
4891
4892 (define_peephole2
4893   [(match_scratch:SI 4 "r")
4894    (set (cc0)
4895         (compare (match_operand:SI 0 "register_operand" "")
4896                  (match_operand:SI 1 "incdec_operand" "")))
4897    (set (pc)
4898         (if_then_else (match_operator 3 "eqne_operator"
4899                         [(cc0) (const_int 0)])
4900                       (label_ref (match_operand 2 "" ""))
4901                       (pc)))]
4902   "(TARGET_H8300H || TARGET_H8300S)
4903    && !peep2_reg_dead_p (1, operands[0])
4904    && !same_cmp_following_p (insn)"
4905   [(set (match_dup 4)
4906         (match_dup 0))
4907    (set (match_dup 4)
4908         (unspec:SI [(match_dup 4)
4909                     (match_dup 5)]
4910                    UNSPEC_INCDEC))
4911    (set (cc0)
4912         (match_dup 4))
4913    (set (pc)
4914         (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4915                       (label_ref (match_dup 2))
4916                       (pc)))]
4917   "operands[5] = GEN_INT (- INTVAL (operands[1]));")
4918
4919 ;; Narrow the mode of testing if possible.
4920
4921 (define_peephole2
4922   [(set (match_operand:HI 0 "register_operand" "")
4923         (and:HI (match_dup 0)
4924                 (match_operand:HI 1 "const_int_qi_operand" "")))
4925    (set (cc0)
4926         (match_dup 0))
4927    (set (pc)
4928         (if_then_else (match_operator 3 "eqne_operator"
4929                         [(cc0) (const_int 0)])
4930                       (label_ref (match_operand 2 "" ""))
4931                       (pc)))]
4932   "peep2_reg_dead_p (2, operands[0])"
4933   [(set (match_dup 4)
4934         (and:QI (match_dup 4)
4935                 (match_dup 5)))
4936    (set (cc0)
4937         (match_dup 4))
4938    (set (pc)
4939         (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4940                       (label_ref (match_dup 2))
4941                       (pc)))]
4942   "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
4943    operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
4944
4945 (define_peephole2
4946   [(set (match_operand:SI 0 "register_operand" "")
4947         (and:SI (match_dup 0)
4948                 (match_operand:SI 1 "const_int_qi_operand" "")))
4949    (set (cc0)
4950         (match_dup 0))
4951    (set (pc)
4952         (if_then_else (match_operator 3 "eqne_operator"
4953                         [(cc0) (const_int 0)])
4954                       (label_ref (match_operand 2 "" ""))
4955                       (pc)))]
4956   "peep2_reg_dead_p (2, operands[0])"
4957   [(set (match_dup 4)
4958         (and:QI (match_dup 4)
4959                 (match_dup 5)))
4960    (set (cc0)
4961         (match_dup 4))
4962    (set (pc)
4963         (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4964                       (label_ref (match_dup 2))
4965                       (pc)))]
4966   "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
4967    operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
4968
4969 (define_peephole2
4970   [(set (match_operand:SI 0 "register_operand" "")
4971         (and:SI (match_dup 0)
4972                 (match_operand:SI 1 "const_int_hi_operand" "")))
4973    (set (cc0)
4974         (match_dup 0))
4975    (set (pc)
4976         (if_then_else (match_operator 3 "eqne_operator"
4977                         [(cc0) (const_int 0)])
4978                       (label_ref (match_operand 2 "" ""))
4979                       (pc)))]
4980   "peep2_reg_dead_p (2, operands[0])"
4981   [(set (match_dup 4)
4982         (and:HI (match_dup 4)
4983                 (match_dup 5)))
4984    (set (cc0)
4985         (match_dup 4))
4986    (set (pc)
4987         (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4988                       (label_ref (match_dup 2))
4989                       (pc)))]
4990   "operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
4991    operands[5] = gen_int_mode (INTVAL (operands[1]), HImode);")
4992
4993 (define_peephole2
4994   [(set (match_operand:SI 0 "register_operand" "")
4995         (and:SI (match_dup 0)
4996                 (match_operand:SI 1 "const_int_qi_operand" "")))
4997    (set (match_dup 0)
4998         (xor:SI (match_dup 0)
4999                 (match_operand:SI 2 "const_int_qi_operand" "")))
5000    (set (cc0)
5001         (match_dup 0))
5002    (set (pc)
5003         (if_then_else (match_operator 4 "eqne_operator"
5004                         [(cc0) (const_int 0)])
5005                       (label_ref (match_operand 3 "" ""))
5006                       (pc)))]
5007   "peep2_reg_dead_p (3, operands[0])
5008    && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
5009   [(set (match_dup 5)
5010         (and:QI (match_dup 5)
5011                 (match_dup 6)))
5012    (set (match_dup 5)
5013         (xor:QI (match_dup 5)
5014                 (match_dup 7)))
5015    (set (cc0)
5016         (match_dup 5))
5017    (set (pc)
5018         (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
5019                       (label_ref (match_dup 3))
5020                       (pc)))]
5021   "operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
5022    operands[6] = gen_int_mode (INTVAL (operands[1]), QImode);
5023    operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);")
5024
5025 ;; These triggers right at the end of allocation of locals in the
5026 ;; prologue (and possibly at other places).
5027
5028 ;; stack adjustment of -4, generate one push
5029 ;;
5030 ;; before : 6 bytes, 10 clocks
5031 ;; after  : 4 bytes, 10 clocks
5032
5033 (define_peephole2
5034   [(set (reg:SI SP_REG)
5035         (plus:SI (reg:SI SP_REG)
5036                  (const_int -4)))
5037    (set (mem:SI (reg:SI SP_REG))
5038         (match_operand:SI 0 "register_operand" ""))]
5039   "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
5040    && REGNO (operands[0]) != SP_REG"
5041   [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
5042         (match_dup 0))]
5043   "")
5044
5045 ;; stack adjustment of -12, generate one push
5046 ;;
5047 ;; before : 10 bytes, 14 clocks
5048 ;; after  :  8 bytes, 14 clocks
5049
5050 (define_peephole2
5051   [(set (reg:SI SP_REG)
5052         (plus:SI (reg:SI SP_REG)
5053                  (const_int -12)))
5054    (set (mem:SI (reg:SI SP_REG))
5055         (match_operand:SI 0 "register_operand" ""))]
5056   "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
5057    && REGNO (operands[0]) != SP_REG"
5058   [(set (reg:SI SP_REG)
5059         (plus:SI (reg:SI SP_REG)
5060                  (const_int -4)))
5061    (set (reg:SI SP_REG)
5062         (plus:SI (reg:SI SP_REG)
5063                  (const_int -4)))
5064    (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
5065         (match_dup 0))]
5066   "")