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h8300.c (fix_bit_operand): Don't generate insns by hand.
[gcc.git] / gcc / config / h8300 / h8300.md
1 ;; GCC machine description for Renesas H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7
8 ;; This file is part of GCC.
9
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; any later version.
14
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
19
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
24
25 ;; We compute exact length on each instruction for most of the time.
26 ;; In some case, most notably bit operations that may involve memory
27 ;; operands, the lengths in this file are "worst case".
28
29 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
30 ;; registers. Right now GCC doesn't expose the "e" half to the
31 ;; compiler, so using add/subs for addhi and subhi is safe. Long
32 ;; term, we want to expose the "e" half to the compiler (gives us 8
33 ;; more 16bit registers). At that point addhi and subhi can't use
34 ;; adds/subs.
35
36 ;; There's currently no way to have an insv/extzv expander for the H8/300H
37 ;; because word_mode is different for the H8/300 and H8/300H.
38
39 ;; Shifts/rotates by small constants should be handled by special
40 ;; patterns so we get the length and cc status correct.
41
42 ;; Bitfield operations no longer accept memory operands. We need
43 ;; to add variants which operate on memory back to the MD.
44
45 ;; ??? Implement remaining bit ops available on the h8300
46
47 ;; ----------------------------------------------------------------------
48 ;; CONSTANTS
49 ;; ----------------------------------------------------------------------
50
51 (define_constants
52 [(UNSPEC_INCDEC 0)
53 (UNSPEC_MONITOR 1)])
54
55 (define_constants
56 [(R0_REG 0)
57 (SC_REG 3)
58 (HFP_REG 6)
59 (SP_REG 7)
60 (MAC_REG 8)
61 (AP_REG 9)
62 (RAP_REG 10)
63 (FP_REG 11)])
64
65 ;; ----------------------------------------------------------------------
66 ;; ATTRIBUTES
67 ;; ----------------------------------------------------------------------
68
69 (define_attr "cpu" "h8300,h8300h"
70 (const (symbol_ref "cpu_type")))
71
72 (define_attr "type" "branch,arith"
73 (const_string "arith"))
74
75 ;; The size of instructions in bytes.
76
77 (define_attr "length" ""
78 (cond [(eq_attr "type" "branch")
79 (if_then_else (and (ge (minus (match_dup 0) (pc))
80 (const_int -126))
81 (le (minus (match_dup 0) (pc))
82 (const_int 126)))
83 (const_int 2)
84 (if_then_else (and (eq_attr "cpu" "h8300h")
85 (and (ge (minus (pc) (match_dup 0))
86 (const_int -32000))
87 (le (minus (pc) (match_dup 0))
88 (const_int 32000))))
89 (const_int 4)
90 (const_int 6)))]
91 (const_int 200)))
92
93 ;; Condition code settings.
94 ;;
95 ;; none - insn does not affect cc
96 ;; none_0hit - insn does not affect cc but it does modify operand 0
97 ;; This attribute is used to keep track of when operand 0 changes.
98 ;; See the description of NOTICE_UPDATE_CC for more info.
99 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
100 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
101 ;; compare - compare instruction
102 ;; clobber - value of cc is unknown
103
104 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
105 (const_string "clobber"))
106
107 ;; Provide the maximum length of an assembly instruction in an asm
108 ;; statement. The maximum length of 14 bytes is achieved on H8SX.
109
110 (define_asm_attributes
111 [(set (attr "length")
112 (cond [(ne (symbol_ref "TARGET_H8300") (const_int 0)) (const_int 4)
113 (ne (symbol_ref "TARGET_H8300H") (const_int 0)) (const_int 10)
114 (ne (symbol_ref "TARGET_H8300S") (const_int 0)) (const_int 10)]
115 (const_int 14)))])
116 \f
117 ;; ----------------------------------------------------------------------
118 ;; MOVE INSTRUCTIONS
119 ;; ----------------------------------------------------------------------
120
121 ;; movqi
122
123 (define_insn "pushqi1_h8300"
124 [(set (reg:HI SP_REG)
125 (plus:HI (reg:HI SP_REG) (const_int -2)))
126 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
127 (match_operand:QI 0 "register_operand" "r"))]
128 "TARGET_H8300
129 && operands[0] != stack_pointer_rtx"
130 "mov.w\\t%T0,@-r7"
131 [(set_attr "length" "2")])
132
133 (define_insn "pushqi1_h8300hs"
134 [(set (reg:SI SP_REG)
135 (plus:SI (reg:SI SP_REG) (const_int -4)))
136 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
137 (match_operand:QI 0 "register_operand" "r"))]
138 "(TARGET_H8300H || TARGET_H8300S)
139 && operands[0] != stack_pointer_rtx"
140 "mov.l\\t%S0,@-er7"
141 [(set_attr "length" "4")])
142
143 (define_insn "pushqi1_h8300hs_normal"
144 [(set (reg:HI SP_REG)
145 (plus:HI (reg:HI SP_REG) (const_int -4)))
146 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
147 (match_operand:QI 0 "register_operand" "r"))]
148 "(TARGET_H8300H || TARGET_H8300S)
149 && operands[0] != stack_pointer_rtx"
150 "mov.l\\t%S0,@-er7"
151 [(set_attr "length" "4")])
152
153 (define_expand "pushqi1"
154 [(match_operand:QI 0 "register_operand" "")]
155 ""
156 "
157 {
158 if (TARGET_H8300)
159 emit_insn (gen_pushqi1_h8300 (operands[0]));
160 else if (!TARGET_NORMAL_MODE)
161 emit_insn (gen_pushqi1_h8300hs (operands[0]));
162 else
163 emit_insn (gen_pushqi1_h8300hs_normal (operands[0]));
164 DONE;
165 }")
166
167 (define_insn "*movqi_h8300"
168 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
169 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
170 "TARGET_H8300
171 && (register_operand (operands[0], QImode)
172 || register_operand (operands[1], QImode))"
173 "@
174 sub.b %X0,%X0
175 mov.b %R1,%X0
176 mov.b %X1,%R0
177 mov.b %R1,%X0
178 mov.b %R1,%X0
179 mov.b %X1,%R0"
180 [(set_attr "length" "2,2,2,2,4,4")
181 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
182
183 (define_insn "*movqi_h8300hs"
184 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
185 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
186 "(TARGET_H8300H || TARGET_H8300S)
187 && (register_operand (operands[0], QImode)
188 || register_operand (operands[1], QImode))"
189 "@
190 sub.b %X0,%X0
191 mov.b %R1,%X0
192 mov.b %X1,%R0
193 mov.b %R1,%X0
194 mov.b %R1,%X0
195 mov.b %X1,%R0"
196 [(set (attr "length")
197 (symbol_ref "compute_mov_length (operands)"))
198 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
199
200 (define_expand "movqi"
201 [(set (match_operand:QI 0 "general_operand_dst" "")
202 (match_operand:QI 1 "general_operand_src" ""))]
203 ""
204 "
205 {
206 /* One of the ops has to be in a register. */
207 if (!register_operand (operand0, QImode)
208 && !register_operand (operand1, QImode))
209 {
210 operands[1] = copy_to_mode_reg (QImode, operand1);
211 }
212 }")
213
214 (define_insn "movstrictqi"
215 [(set (strict_low_part
216 (match_operand:QI 0 "register_operand" "+r,r,r,r,r"))
217 (match_operand:QI 1 "general_operand_src" " I,r,n,>,m"))]
218 ""
219 "@
220 sub.b %X0,%X0
221 mov.b %X1,%X0
222 mov.b %R1,%X0
223 mov.b %X1,%X0
224 mov.b %R1,%X0"
225 [(set (attr "length")
226 (symbol_ref "compute_mov_length (operands)"))
227 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
228
229 ;; movhi
230
231 (define_expand "pushhi1_h8300"
232 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
233 (match_operand:HI 0 "register_operand" ""))]
234 "TARGET_H8300
235 && operands[0] != stack_pointer_rtx"
236 "")
237
238 (define_insn "pushhi1_h8300hs"
239 [(set (reg:SI SP_REG)
240 (plus:SI (reg:SI SP_REG) (const_int -4)))
241 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
242 (match_operand:HI 0 "register_operand" "r"))]
243 "(TARGET_H8300H || TARGET_H8300S)
244 && operands[0] != stack_pointer_rtx"
245 "mov.l\\t%S0,@-er7"
246 [(set_attr "length" "4")])
247
248 (define_insn "pushhi1_h8300hs_normal"
249 [(set (reg:HI SP_REG)
250 (plus:HI (reg:HI SP_REG) (const_int -4)))
251 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
252 (match_operand:HI 0 "register_operand" "r"))]
253 "(TARGET_H8300H || TARGET_H8300S)
254 && operands[0] != stack_pointer_rtx"
255 "mov.l\\t%S0,@-er7"
256 [(set_attr "length" "4")])
257
258 (define_expand "pushhi1"
259 [(match_operand:HI 0 "register_operand" "")]
260 ""
261 "
262 {
263 if (TARGET_H8300)
264 emit_insn (gen_pushhi1_h8300 (operands[0]));
265 else if (!TARGET_NORMAL_MODE)
266 emit_insn (gen_pushhi1_h8300hs (operands[0]));
267 else
268 emit_insn (gen_pushhi1_h8300hs_normal (operands[0]));
269 DONE;
270 }")
271
272 (define_insn "*movhi_h8300"
273 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
274 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
275 "TARGET_H8300
276 && (register_operand (operands[0], HImode)
277 || register_operand (operands[1], HImode))
278 && !(GET_CODE (operands[0]) == MEM
279 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
280 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
281 && GET_CODE (operands[1]) == REG
282 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
283 "@
284 sub.w %T0,%T0
285 mov.w %T1,%T0
286 mov.w %T1,%T0
287 mov.w %T1,%T0
288 mov.w %T1,%T0
289 mov.w %T1,%T0"
290 [(set (attr "length")
291 (symbol_ref "compute_mov_length (operands)"))
292 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
293
294 (define_insn "*movhi_h8300hs"
295 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
296 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
297 "(TARGET_H8300H || TARGET_H8300S)
298 && (register_operand (operands[0], HImode)
299 || register_operand (operands[1], HImode))"
300 "@
301 sub.w %T0,%T0
302 mov.w %T1,%T0
303 mov.w %T1,%T0
304 mov.w %T1,%T0
305 mov.w %T1,%T0
306 mov.w %T1,%T0"
307 [(set (attr "length")
308 (symbol_ref "compute_mov_length (operands)"))
309 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
310
311 (define_expand "movhi"
312 [(set (match_operand:HI 0 "general_operand_dst" "")
313 (match_operand:HI 1 "general_operand_src" ""))]
314 ""
315 "
316 {
317 /* One of the ops has to be in a register. */
318 if (!register_operand (operand1, HImode)
319 && !register_operand (operand0, HImode))
320 {
321 operands[1] = copy_to_mode_reg (HImode, operand1);
322 }
323 }")
324
325 (define_insn "movstricthi"
326 [(set (strict_low_part
327 (match_operand:HI 0 "register_operand" "+r,r,r,r,r"))
328 (match_operand:HI 1 "general_operand_src" " I,r,i,>,m"))]
329 ""
330 "@
331 sub.w %T0,%T0
332 mov.w %T1,%T0
333 mov.w %T1,%T0
334 mov.w %T1,%T0
335 mov.w %T1,%T0"
336 [(set (attr "length")
337 (symbol_ref "compute_mov_length (operands)"))
338 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
339
340 ;; movsi
341
342 (define_expand "movsi"
343 [(set (match_operand:SI 0 "general_operand_dst" "")
344 (match_operand:SI 1 "general_operand_src" ""))]
345 ""
346 "
347 {
348 if (TARGET_H8300)
349 {
350 if (h8300_expand_movsi (operands))
351 DONE;
352 }
353 else
354 {
355 /* One of the ops has to be in a register. */
356 if (!register_operand (operand1, SImode)
357 && !register_operand (operand0, SImode))
358 {
359 operands[1] = copy_to_mode_reg (SImode, operand1);
360 }
361 }
362 }")
363
364 (define_expand "movsf"
365 [(set (match_operand:SF 0 "general_operand_dst" "")
366 (match_operand:SF 1 "general_operand_src" ""))]
367 ""
368 "
369 {
370 if (TARGET_H8300)
371 {
372 if (h8300_expand_movsi (operands))
373 DONE;
374 }
375 else
376 {
377 /* One of the ops has to be in a register. */
378 if (!register_operand (operand1, SFmode)
379 && !register_operand (operand0, SFmode))
380 {
381 operands[1] = copy_to_mode_reg (SFmode, operand1);
382 }
383 }
384 }")
385
386 (define_insn "*movsi_h8300"
387 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
388 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
389 "TARGET_H8300
390 && (register_operand (operands[0], SImode)
391 || register_operand (operands[1], SImode))"
392 "*
393 {
394 unsigned int rn = -1;
395 switch (which_alternative)
396 {
397 case 0:
398 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
399 case 1:
400 if (REGNO (operands[0]) < REGNO (operands[1]))
401 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
402 else
403 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
404 case 2:
405 /* Make sure we don't trample the register we index with. */
406 if (GET_CODE (operands[1]) == MEM)
407 {
408 rtx inside = XEXP (operands[1], 0);
409 if (REG_P (inside))
410 {
411 rn = REGNO (inside);
412 }
413 else if (GET_CODE (inside) == PLUS)
414 {
415 rtx lhs = XEXP (inside, 0);
416 rtx rhs = XEXP (inside, 1);
417 if (REG_P (lhs)) rn = REGNO (lhs);
418 if (REG_P (rhs)) rn = REGNO (rhs);
419 }
420 }
421 if (rn == REGNO (operands[0]))
422 {
423 /* Move the second word first. */
424 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
425 }
426 else
427 {
428 if (GET_CODE (operands[1]) == CONST_INT)
429 {
430 /* If either half is zero, use sub.w to clear that
431 half. */
432 if ((INTVAL (operands[1]) & 0xffff) == 0)
433 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
434 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
435 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
436 /* If the upper half and the lower half are the same,
437 copy one half to the other. */
438 if ((INTVAL (operands[1]) & 0xffff)
439 == ((INTVAL (operands[1]) >> 16) & 0xffff))
440 return \"mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0\";
441 }
442 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
443 }
444 case 3:
445 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
446 case 4:
447 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
448 case 5:
449 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
450 default:
451 abort ();
452 }
453 }"
454 [(set (attr "length")
455 (symbol_ref "compute_mov_length (operands)"))])
456
457 (define_insn "*movsf_h8300"
458 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
459 (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))]
460 "TARGET_H8300
461 && (register_operand (operands[0], SFmode)
462 || register_operand (operands[1], SFmode))"
463 "*
464 {
465 /* Copy of the movsi stuff. */
466 unsigned int rn = -1;
467 switch (which_alternative)
468 {
469 case 0:
470 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
471 case 1:
472 if (REGNO (operands[0]) < REGNO (operands[1]))
473 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
474 else
475 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
476 case 2:
477 /* Make sure we don't trample the register we index with. */
478 if (GET_CODE (operands[1]) == MEM)
479 {
480 rtx inside = XEXP (operands[1], 0);
481 if (REG_P (inside))
482 {
483 rn = REGNO (inside);
484 }
485 else if (GET_CODE (inside) == PLUS)
486 {
487 rtx lhs = XEXP (inside, 0);
488 rtx rhs = XEXP (inside, 1);
489 if (REG_P (lhs)) rn = REGNO (lhs);
490 if (REG_P (rhs)) rn = REGNO (rhs);
491 }
492 }
493 if (rn == REGNO (operands[0]))
494 /* Move the second word first. */
495 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
496 else
497 /* Move the first word first. */
498 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
499
500 case 3:
501 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
502 case 4:
503 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
504 case 5:
505 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
506 default:
507 abort ();
508 }
509 }"
510 [(set (attr "length")
511 (symbol_ref "compute_mov_length (operands)"))])
512
513 (define_insn "*movsi_h8300hs"
514 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
515 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
516 "(TARGET_H8300S || TARGET_H8300H)
517 && (register_operand (operands[0], SImode)
518 || register_operand (operands[1], SImode))
519 && !(GET_CODE (operands[0]) == MEM
520 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
521 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
522 && GET_CODE (operands[1]) == REG
523 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
524 "*
525 {
526 switch (which_alternative)
527 {
528 case 0:
529 return \"sub.l %S0,%S0\";
530 case 7:
531 return \"clrmac\";
532 case 8:
533 return \"clrmac\;ldmac %1,macl\";
534 case 9:
535 return \"stmac macl,%0\";
536 default:
537 if (GET_CODE (operands[1]) == CONST_INT)
538 {
539 int val = INTVAL (operands[1]);
540
541 /* Look for constants which can be made by adding an 8-bit
542 number to zero in one of the two low bytes. */
543 if (val == (val & 0xff))
544 {
545 operands[1] = GEN_INT ((char) val & 0xff);
546 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
547 }
548
549 if (val == (val & 0xff00))
550 {
551 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
552 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
553 }
554
555 /* Look for constants that can be obtained by subs, inc, and
556 dec to 0. */
557 switch (val & 0xffffffff)
558 {
559 case 0xffffffff:
560 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
561 case 0xfffffffe:
562 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
563 case 0xfffffffc:
564 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
565
566 case 0x0000ffff:
567 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
568 case 0x0000fffe:
569 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
570
571 case 0xffff0000:
572 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
573 case 0xfffe0000:
574 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
575
576 case 0x00010000:
577 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
578 case 0x00020000:
579 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
580 }
581 }
582 }
583 return \"mov.l %S1,%S0\";
584 }"
585 [(set (attr "length")
586 (symbol_ref "compute_mov_length (operands)"))
587 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
588
589 (define_insn "*movsf_h8300hs"
590 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
591 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
592 "(TARGET_H8300H || TARGET_H8300S)
593 && (register_operand (operands[0], SFmode)
594 || register_operand (operands[1], SFmode))"
595 "@
596 sub.l %S0,%S0
597 mov.l %S1,%S0
598 mov.l %S1,%S0
599 mov.l %S1,%S0
600 mov.l %S1,%S0
601 mov.l %S1,%S0"
602 [(set (attr "length")
603 (symbol_ref "compute_mov_length (operands)"))
604 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
605 \f
606 ;; ----------------------------------------------------------------------
607 ;; TEST INSTRUCTIONS
608 ;; ----------------------------------------------------------------------
609
610 (define_insn ""
611 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
612 (const_int 1)
613 (match_operand 1 "const_int_operand" "n,n")))]
614 "TARGET_H8300"
615 "btst %Z1,%Y0"
616 [(set_attr "length" "2,4")
617 (set_attr "cc" "set_zn,set_zn")])
618
619 (define_insn ""
620 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
621 (const_int 1)
622 (match_operand 1 "const_int_operand" "n")))]
623 "TARGET_H8300"
624 "btst %Z1,%Y0"
625 [(set_attr "length" "2")
626 (set_attr "cc" "set_zn")])
627
628 (define_insn_and_split "*tst_extzv_1_n"
629 [(set (cc0)
630 (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
631 (const_int 1)
632 (match_operand 1 "const_int_operand" "n,n,n")))
633 (clobber (match_scratch:QI 2 "=X,X,&r"))]
634 "(TARGET_H8300H || TARGET_H8300S)"
635 "@
636 btst\\t%Z1,%Y0
637 btst\\t%Z1,%Y0
638 #"
639 "&& reload_completed
640 && !EXTRA_CONSTRAINT (operands[0], 'U')"
641 [(set (match_dup 2)
642 (match_dup 0))
643 (parallel [(set (cc0) (zero_extract:SI (match_dup 2)
644 (const_int 1)
645 (match_dup 1)))
646 (clobber (scratch:QI))])]
647 ""
648 [(set_attr "length" "2,8,10")
649 (set_attr "cc" "set_zn,set_zn,set_zn")])
650
651 (define_insn ""
652 [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
653 (const_int 1)
654 (match_operand 1 "const_int_operand" "n")))]
655 "(TARGET_H8300H || TARGET_H8300S)
656 && INTVAL (operands[1]) <= 15"
657 "btst %Z1,%Y0"
658 [(set_attr "length" "2")
659 (set_attr "cc" "set_zn")])
660
661 (define_insn_and_split "*tstsi_upper_bit"
662 [(set (cc0)
663 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
664 (const_int 1)
665 (match_operand 1 "const_int_operand" "n")))
666 (clobber (match_scratch:SI 2 "=&r"))]
667 "(TARGET_H8300H || TARGET_H8300S)
668 && INTVAL (operands[1]) >= 16"
669 "#"
670 "&& reload_completed"
671 [(set (match_dup 2)
672 (ior:SI (and:SI (match_dup 2)
673 (const_int -65536))
674 (lshiftrt:SI (match_dup 0)
675 (const_int 16))))
676 (set (cc0)
677 (zero_extract:SI (match_dup 2)
678 (const_int 1)
679 (match_dup 3)))]
680 "operands[3] = GEN_INT (INTVAL (operands[1]) - 16);")
681
682 (define_insn "*tstsi_variable_bit"
683 [(set (cc0)
684 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
685 (const_int 1)
686 (and:SI (match_operand:SI 1 "register_operand" "r")
687 (const_int 7))))]
688 "TARGET_H8300H || TARGET_H8300S"
689 "btst %w1,%w0"
690 [(set_attr "length" "2")
691 (set_attr "cc" "set_zn")])
692
693 (define_insn_and_split "*tstsi_variable_bit_qi"
694 [(set (cc0)
695 (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>"))
696 (const_int 1)
697 (and:SI (match_operand:SI 1 "register_operand" "r,r,r")
698 (const_int 7))))
699 (clobber (match_scratch:QI 2 "=X,X,&r"))]
700 "(TARGET_H8300H || TARGET_H8300S)"
701 "@
702 btst\\t%w1,%X0
703 btst\\t%w1,%X0
704 #"
705 "&& reload_completed
706 && !EXTRA_CONSTRAINT (operands[0], 'U')"
707 [(set (match_dup 2)
708 (match_dup 0))
709 (parallel [(set (cc0) (zero_extract:SI (zero_extend:SI (match_dup 2))
710 (const_int 1)
711 (and:SI (match_dup 1)
712 (const_int 7))))
713 (clobber (scratch:QI))])]
714 ""
715 [(set_attr "length" "2,8,10")
716 (set_attr "cc" "set_zn,set_zn,set_zn")])
717
718 (define_insn "tstqi"
719 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
720 ""
721 "mov.b %X0,%X0"
722 [(set_attr "length" "2")
723 (set_attr "cc" "set_znv")])
724
725 (define_insn "tsthi"
726 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
727 ""
728 "mov.w %T0,%T0"
729 [(set_attr "length" "2")
730 (set_attr "cc" "set_znv")])
731
732 (define_insn "*tsthi_upper"
733 [(set (cc0)
734 (and:HI (match_operand:HI 0 "register_operand" "r")
735 (const_int -256)))]
736 ""
737 "mov.b %t0,%t0"
738 [(set_attr "length" "2")
739 (set_attr "cc" "set_znv")])
740
741 (define_insn "tstsi"
742 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
743 "TARGET_H8300H || TARGET_H8300S"
744 "mov.l %S0,%S0"
745 [(set_attr "length" "2")
746 (set_attr "cc" "set_znv")])
747
748 (define_insn "*tstsi_upper"
749 [(set (cc0)
750 (and:SI (match_operand:SI 0 "register_operand" "r")
751 (const_int -65536)))]
752 ""
753 "mov.w %e0,%e0"
754 [(set_attr "length" "2")
755 (set_attr "cc" "set_znv")])
756
757 (define_insn "cmpqi"
758 [(set (cc0)
759 (compare (match_operand:QI 0 "register_operand" "r")
760 (match_operand:QI 1 "nonmemory_operand" "rn")))]
761 ""
762 "cmp.b %X1,%X0"
763 [(set_attr "length" "2")
764 (set_attr "cc" "compare")])
765
766 (define_expand "cmphi"
767 [(set (cc0)
768 (compare (match_operand:HI 0 "register_operand" "")
769 (match_operand:HI 1 "nonmemory_operand" "")))]
770 ""
771 "
772 {
773 /* Force operand1 into a register if we're compiling
774 for the H8/300. */
775 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
776 operands[1] = force_reg (HImode, operands[1]);
777 }")
778
779 (define_insn "*cmphi_h8300"
780 [(set (cc0)
781 (compare (match_operand:HI 0 "register_operand" "r")
782 (match_operand:HI 1 "register_operand" "r")))]
783 "TARGET_H8300"
784 "cmp.w %T1,%T0"
785 [(set_attr "length" "2")
786 (set_attr "cc" "compare")])
787
788 (define_insn "*cmphi_h8300hs"
789 [(set (cc0)
790 (compare (match_operand:HI 0 "register_operand" "r,r")
791 (match_operand:HI 1 "nonmemory_operand" "r,n")))]
792 "TARGET_H8300H || TARGET_H8300S"
793 "cmp.w %T1,%T0"
794 [(set_attr "length" "2,4")
795 (set_attr "cc" "compare,compare")])
796
797 (define_insn "cmpsi"
798 [(set (cc0)
799 (compare (match_operand:SI 0 "register_operand" "r,r")
800 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
801 "TARGET_H8300H || TARGET_H8300S"
802 "cmp.l %S1,%S0"
803 [(set_attr "length" "2,6")
804 (set_attr "cc" "compare,compare")])
805 \f
806 ;; ----------------------------------------------------------------------
807 ;; ADD INSTRUCTIONS
808 ;; ----------------------------------------------------------------------
809
810 (define_insn "addqi3"
811 [(set (match_operand:QI 0 "register_operand" "=r")
812 (plus:QI (match_operand:QI 1 "register_operand" "%0")
813 (match_operand:QI 2 "nonmemory_operand" "rn")))]
814 ""
815 "add.b %X2,%X0"
816 [(set_attr "length" "2")
817 (set_attr "cc" "set_zn")])
818
819 (define_expand "addhi3"
820 [(set (match_operand:HI 0 "register_operand" "")
821 (plus:HI (match_operand:HI 1 "register_operand" "")
822 (match_operand:HI 2 "nonmemory_operand" "")))]
823 ""
824 "")
825
826 (define_insn "*addhi3_h8300"
827 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
828 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
829 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
830 "TARGET_H8300"
831 "@
832 adds %2,%T0
833 subs %G2,%T0
834 add.b %t2,%t0
835 add.b %s2,%s0\;addx %t2,%t0
836 add.w %T2,%T0"
837 [(set_attr "length" "2,2,2,4,2")
838 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
839
840 ;; This splitter is very important to make the stack adjustment
841 ;; interrupt-safe. The combination of add.b and addx is unsafe!
842 ;;
843 ;; We apply this split after the peephole2 pass so that we won't end
844 ;; up creating too many adds/subs when a scratch register is
845 ;; available, which is actually a common case because stack unrolling
846 ;; tends to happen immediately after a function call.
847
848 (define_split
849 [(set (match_operand:HI 0 "stack_pointer_operand" "")
850 (plus:HI (match_dup 0)
851 (match_operand 1 "const_int_gt_2_operand" "")))]
852 "TARGET_H8300 && flow2_completed"
853 [(const_int 0)]
854 "split_adds_subs (HImode, operands); DONE;")
855
856 (define_peephole2
857 [(match_scratch:HI 2 "r")
858 (set (match_operand:HI 0 "stack_pointer_operand" "")
859 (plus:HI (match_dup 0)
860 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
861 "TARGET_H8300"
862 [(set (match_dup 2)
863 (match_dup 1))
864 (set (match_dup 0)
865 (plus:HI (match_dup 0)
866 (match_dup 2)))]
867 "")
868
869 (define_insn "*addhi3_h8300hs"
870 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
871 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
872 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
873 "TARGET_H8300H || TARGET_H8300S"
874 "@
875 adds %2,%S0
876 subs %G2,%S0
877 add.b %t2,%t0
878 add.w %T2,%T0
879 add.w %T2,%T0"
880 [(set_attr "length" "2,2,2,4,2")
881 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
882
883 (define_insn "*addhi3_incdec"
884 [(set (match_operand:HI 0 "register_operand" "=r,r")
885 (unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
886 (match_operand:HI 2 "incdec_operand" "M,O")]
887 UNSPEC_INCDEC))]
888 "TARGET_H8300H || TARGET_H8300S"
889 "@
890 inc.w %2,%T0
891 dec.w %G2,%T0"
892 [(set_attr "length" "2,2")
893 (set_attr "cc" "set_zn,set_zn")])
894
895 (define_split
896 [(set (match_operand:HI 0 "register_operand" "")
897 (plus:HI (match_dup 0)
898 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
899 ""
900 [(const_int 0)]
901 "split_adds_subs (HImode, operands); DONE;")
902
903 (define_expand "addsi3"
904 [(set (match_operand:SI 0 "register_operand" "")
905 (plus:SI (match_operand:SI 1 "register_operand" "")
906 (match_operand:SI 2 "nonmemory_operand" "")))]
907 ""
908 "")
909
910 (define_insn "*addsi_h8300"
911 [(set (match_operand:SI 0 "register_operand" "=r,r")
912 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
913 (match_operand:SI 2 "nonmemory_operand" "n,r")))]
914 "TARGET_H8300"
915 "* return output_plussi (operands);"
916 [(set (attr "length")
917 (symbol_ref "compute_plussi_length (operands)"))
918 (set (attr "cc")
919 (symbol_ref "compute_plussi_cc (operands)"))])
920
921 (define_insn "*addsi_h8300hs"
922 [(set (match_operand:SI 0 "register_operand" "=r,r")
923 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
924 (match_operand:SI 2 "nonmemory_operand" "i,r")))]
925 "TARGET_H8300H || TARGET_H8300S"
926 "* return output_plussi (operands);"
927 [(set (attr "length")
928 (symbol_ref "compute_plussi_length (operands)"))
929 (set (attr "cc")
930 (symbol_ref "compute_plussi_cc (operands)"))])
931
932 (define_insn "*addsi3_incdec"
933 [(set (match_operand:SI 0 "register_operand" "=r,r")
934 (unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
935 (match_operand:SI 2 "incdec_operand" "M,O")]
936 UNSPEC_INCDEC))]
937 "TARGET_H8300H || TARGET_H8300S"
938 "@
939 inc.l %2,%S0
940 dec.l %G2,%S0"
941 [(set_attr "length" "2,2")
942 (set_attr "cc" "set_zn,set_zn")])
943
944 (define_split
945 [(set (match_operand:SI 0 "register_operand" "")
946 (plus:SI (match_dup 0)
947 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
948 "TARGET_H8300H || TARGET_H8300S"
949 [(const_int 0)]
950 "split_adds_subs (SImode, operands); DONE;")
951
952 ;; ----------------------------------------------------------------------
953 ;; SUBTRACT INSTRUCTIONS
954 ;; ----------------------------------------------------------------------
955
956 (define_insn "subqi3"
957 [(set (match_operand:QI 0 "register_operand" "=r")
958 (minus:QI (match_operand:QI 1 "register_operand" "0")
959 (match_operand:QI 2 "register_operand" "r")))]
960 ""
961 "sub.b %X2,%X0"
962 [(set_attr "length" "2")
963 (set_attr "cc" "set_zn")])
964
965 (define_expand "subhi3"
966 [(set (match_operand:HI 0 "register_operand" "")
967 (minus:HI (match_operand:HI 1 "general_operand" "")
968 (match_operand:HI 2 "nonmemory_operand" "")))]
969 ""
970 "")
971
972 (define_insn "*subhi3_h8300"
973 [(set (match_operand:HI 0 "register_operand" "=r,r")
974 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
975 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
976 "TARGET_H8300"
977 "@
978 sub.w %T2,%T0
979 add.b %E2,%s0\;addx %F2,%t0"
980 [(set_attr "length" "2,4")
981 (set_attr "cc" "set_zn,clobber")])
982
983 (define_insn "*subhi3_h8300hs"
984 [(set (match_operand:HI 0 "register_operand" "=r,r")
985 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
986 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
987 "TARGET_H8300H || TARGET_H8300S"
988 "@
989 sub.w %T2,%T0
990 sub.w %T2,%T0"
991 [(set_attr "length" "2,4")
992 (set_attr "cc" "set_zn,set_zn")])
993
994 (define_expand "subsi3"
995 [(set (match_operand:SI 0 "register_operand" "")
996 (minus:SI (match_operand:SI 1 "register_operand" "")
997 (match_operand:SI 2 "nonmemory_operand" "")))]
998 ""
999 "")
1000
1001 (define_insn "*subsi3_h8300"
1002 [(set (match_operand:SI 0 "register_operand" "=r")
1003 (minus:SI (match_operand:SI 1 "register_operand" "0")
1004 (match_operand:SI 2 "register_operand" "r")))]
1005 "TARGET_H8300"
1006 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
1007 [(set_attr "length" "6")])
1008
1009 (define_insn "*subsi3_h8300hs"
1010 [(set (match_operand:SI 0 "register_operand" "=r,r")
1011 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
1012 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
1013 "TARGET_H8300H || TARGET_H8300S"
1014 "@
1015 sub.l %S2,%S0
1016 sub.l %S2,%S0"
1017 [(set_attr "length" "2,6")
1018 (set_attr "cc" "set_zn,set_zn")])
1019 \f
1020 ;; ----------------------------------------------------------------------
1021 ;; MULTIPLY INSTRUCTIONS
1022 ;; ----------------------------------------------------------------------
1023
1024 ;; Note that the H8/300 can only handle umulqihi3.
1025
1026 (define_insn "mulqihi3"
1027 [(set (match_operand:HI 0 "register_operand" "=r")
1028 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1029 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1030 "TARGET_H8300H || TARGET_H8300S"
1031 "mulxs.b %X2,%T0"
1032 [(set_attr "length" "4")
1033 (set_attr "cc" "set_zn")])
1034
1035 (define_insn "mulhisi3"
1036 [(set (match_operand:SI 0 "register_operand" "=r")
1037 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1038 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1039 "TARGET_H8300H || TARGET_H8300S"
1040 "mulxs.w %T2,%S0"
1041 [(set_attr "length" "4")
1042 (set_attr "cc" "set_zn")])
1043
1044 (define_insn "umulqihi3"
1045 [(set (match_operand:HI 0 "register_operand" "=r")
1046 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1047 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1048 ""
1049 "mulxu %X2,%T0"
1050 [(set_attr "length" "2")
1051 (set_attr "cc" "none_0hit")])
1052
1053 (define_insn "umulhisi3"
1054 [(set (match_operand:SI 0 "register_operand" "=r")
1055 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1056 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1057 "TARGET_H8300H || TARGET_H8300S"
1058 "mulxu.w %T2,%S0"
1059 [(set_attr "length" "2")
1060 (set_attr "cc" "none_0hit")])
1061
1062 ;; This is a "bridge" instruction. Combine can't cram enough insns
1063 ;; together to crate a MAC instruction directly, but it can create
1064 ;; this instruction, which then allows combine to create the real
1065 ;; MAC insn.
1066 ;;
1067 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1068 ;; insn must generate reasonably correct code. Egad.
1069 (define_insn ""
1070 [(set (match_operand:SI 0 "register_operand" "=a")
1071 (mult:SI
1072 (sign_extend:SI
1073 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1074 (sign_extend:SI
1075 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
1076 "TARGET_MAC"
1077 "clrmac\;mac @%2+,@%1+"
1078 [(set_attr "length" "6")
1079 (set_attr "cc" "none_0hit")])
1080
1081 (define_insn ""
1082 [(set (match_operand:SI 0 "register_operand" "=a")
1083 (plus:SI (mult:SI
1084 (sign_extend:SI (mem:HI
1085 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1086 (sign_extend:SI (mem:HI
1087 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1088 (match_operand:SI 3 "register_operand" "0")))]
1089 "TARGET_MAC"
1090 "mac @%2+,@%1+"
1091 [(set_attr "length" "4")
1092 (set_attr "cc" "none_0hit")])
1093
1094 ;; ----------------------------------------------------------------------
1095 ;; DIVIDE/MOD INSTRUCTIONS
1096 ;; ----------------------------------------------------------------------
1097
1098 (define_insn "udivmodqi4"
1099 [(set (match_operand:QI 0 "register_operand" "=r")
1100 (truncate:QI
1101 (udiv:HI
1102 (match_operand:HI 1 "register_operand" "0")
1103 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1104 (set (match_operand:QI 3 "register_operand" "=r")
1105 (truncate:QI
1106 (umod:HI
1107 (match_dup 1)
1108 (zero_extend:HI (match_dup 2)))))]
1109 ""
1110 "*
1111 {
1112 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1113 return \"divxu.b\\t%X2,%T0\";
1114 else
1115 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1116 }"
1117 [(set_attr "length" "4")])
1118
1119 (define_insn "divmodqi4"
1120 [(set (match_operand:QI 0 "register_operand" "=r")
1121 (truncate:QI
1122 (div:HI
1123 (match_operand:HI 1 "register_operand" "0")
1124 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1125 (set (match_operand:QI 3 "register_operand" "=r")
1126 (truncate:QI
1127 (mod:HI
1128 (match_dup 1)
1129 (sign_extend:HI (match_dup 2)))))]
1130 "TARGET_H8300H || TARGET_H8300S"
1131 "*
1132 {
1133 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1134 return \"divxs.b\\t%X2,%T0\";
1135 else
1136 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1137 }"
1138 [(set_attr "length" "6")])
1139
1140 (define_insn "udivmodhi4"
1141 [(set (match_operand:HI 0 "register_operand" "=r")
1142 (truncate:HI
1143 (udiv:SI
1144 (match_operand:SI 1 "register_operand" "0")
1145 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1146 (set (match_operand:HI 3 "register_operand" "=r")
1147 (truncate:HI
1148 (umod:SI
1149 (match_dup 1)
1150 (zero_extend:SI (match_dup 2)))))]
1151 "TARGET_H8300H || TARGET_H8300S"
1152 "*
1153 {
1154 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1155 return \"divxu.w\\t%T2,%S0\";
1156 else
1157 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1158 }"
1159 [(set_attr "length" "4")])
1160
1161 (define_insn "divmodhi4"
1162 [(set (match_operand:HI 0 "register_operand" "=r")
1163 (truncate:HI
1164 (div:SI
1165 (match_operand:SI 1 "register_operand" "0")
1166 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1167 (set (match_operand:HI 3 "register_operand" "=r")
1168 (truncate:HI
1169 (mod:SI
1170 (match_dup 1)
1171 (sign_extend:SI (match_dup 2)))))]
1172 "TARGET_H8300H || TARGET_H8300S"
1173 "*
1174 {
1175 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1176 return \"divxs.w\\t%T2,%S0\";
1177 else
1178 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1179 }"
1180 [(set_attr "length" "6")])
1181 \f
1182 ;; ----------------------------------------------------------------------
1183 ;; AND INSTRUCTIONS
1184 ;; ----------------------------------------------------------------------
1185
1186 (define_insn "andqi3_1"
1187 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1188 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1189 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1190 "register_operand (operands[0], QImode)
1191 || single_zero_operand (operands[2], QImode)"
1192 "@
1193 and %X2,%X0
1194 bclr %W2,%R0"
1195 [(set_attr "length" "2,8")
1196 (set_attr "cc" "set_znv,none_0hit")])
1197
1198 (define_expand "andqi3"
1199 [(set (match_operand:QI 0 "bit_operand" "")
1200 (and:QI (match_operand:QI 1 "bit_operand" "")
1201 (match_operand:QI 2 "nonmemory_operand" "")))]
1202 ""
1203 "
1204 {
1205 if (fix_bit_operand (operands, 0, AND))
1206 DONE;
1207 }")
1208
1209 (define_expand "andhi3"
1210 [(set (match_operand:HI 0 "register_operand" "")
1211 (and:HI (match_operand:HI 1 "register_operand" "")
1212 (match_operand:HI 2 "nonmemory_operand" "")))]
1213 ""
1214 "")
1215
1216 (define_insn "*andorqi3"
1217 [(set (match_operand:QI 0 "register_operand" "=r")
1218 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1219 (match_operand:QI 3 "single_one_operand" "n"))
1220 (match_operand:QI 1 "register_operand" "0")))]
1221 ""
1222 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1223 [(set_attr "length" "6")])
1224
1225 (define_insn "*andorhi3"
1226 [(set (match_operand:HI 0 "register_operand" "=r")
1227 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1228 (match_operand:HI 3 "single_one_operand" "n"))
1229 (match_operand:HI 1 "register_operand" "0")))]
1230 ""
1231 "*
1232 {
1233 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1234 if (INTVAL (operands[3]) > 128)
1235 {
1236 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1237 return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\";
1238 }
1239 return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\";
1240 }"
1241 [(set_attr "length" "6")])
1242
1243 (define_insn "*andorsi3"
1244 [(set (match_operand:SI 0 "register_operand" "=r")
1245 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1246 (match_operand:SI 3 "single_one_operand" "n"))
1247 (match_operand:SI 1 "register_operand" "0")))]
1248 "(INTVAL (operands[3]) & 0xffff) != 0"
1249 "*
1250 {
1251 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1252 if (INTVAL (operands[3]) > 128)
1253 {
1254 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1255 return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\";
1256 }
1257 return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\";
1258 }"
1259 [(set_attr "length" "6")])
1260
1261 (define_insn "*andorsi3_shift_8"
1262 [(set (match_operand:SI 0 "register_operand" "=r")
1263 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1264 (const_int 8))
1265 (const_int 65280))
1266 (match_operand:SI 1 "register_operand" "0")))]
1267 ""
1268 "or.b\\t%w2,%x0"
1269 [(set_attr "length" "2")])
1270
1271 (define_expand "andsi3"
1272 [(set (match_operand:SI 0 "register_operand" "")
1273 (and:SI (match_operand:SI 1 "register_operand" "")
1274 (match_operand:SI 2 "nonmemory_operand" "")))]
1275 ""
1276 "")
1277
1278 ;; ----------------------------------------------------------------------
1279 ;; OR INSTRUCTIONS
1280 ;; ----------------------------------------------------------------------
1281
1282 (define_insn "iorqi3_1"
1283 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1284 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1285 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1286 "register_operand (operands[0], QImode)
1287 || single_one_operand (operands[2], QImode)"
1288 "@
1289 or\\t%X2,%X0
1290 bset\\t%V2,%R0"
1291 [(set_attr "length" "2,8")
1292 (set_attr "cc" "set_znv,none_0hit")])
1293
1294 (define_expand "iorqi3"
1295 [(set (match_operand:QI 0 "bit_operand" "")
1296 (ior:QI (match_operand:QI 1 "bit_operand" "")
1297 (match_operand:QI 2 "nonmemory_operand" "")))]
1298 ""
1299 "
1300 {
1301 if (fix_bit_operand (operands, 1, IOR))
1302 DONE;
1303 }")
1304
1305 (define_expand "iorhi3"
1306 [(set (match_operand:HI 0 "register_operand" "")
1307 (ior:HI (match_operand:HI 1 "register_operand" "")
1308 (match_operand:HI 2 "nonmemory_operand" "")))]
1309 ""
1310 "")
1311
1312 (define_expand "iorsi3"
1313 [(set (match_operand:SI 0 "register_operand" "")
1314 (ior:SI (match_operand:SI 1 "register_operand" "")
1315 (match_operand:SI 2 "nonmemory_operand" "")))]
1316 ""
1317 "")
1318
1319 ;; ----------------------------------------------------------------------
1320 ;; XOR INSTRUCTIONS
1321 ;; ----------------------------------------------------------------------
1322
1323 (define_insn "xorqi3_1"
1324 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1325 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1326 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1327 "register_operand (operands[0], QImode)
1328 || single_one_operand (operands[2], QImode)"
1329 "@
1330 xor\\t%X2,%X0
1331 bnot\\t%V2,%R0"
1332 [(set_attr "length" "2,8")
1333 (set_attr "cc" "set_znv,none_0hit")])
1334
1335 (define_expand "xorqi3"
1336 [(set (match_operand:QI 0 "bit_operand" "")
1337 (xor:QI (match_operand:QI 1 "bit_operand" "")
1338 (match_operand:QI 2 "nonmemory_operand" "")))]
1339 ""
1340 "
1341 {
1342 if (fix_bit_operand (operands, 1, XOR))
1343 DONE;
1344 }")
1345
1346 (define_expand "xorhi3"
1347 [(set (match_operand:HI 0 "register_operand" "")
1348 (xor:HI (match_operand:HI 1 "register_operand" "")
1349 (match_operand:HI 2 "nonmemory_operand" "")))]
1350 ""
1351 "")
1352
1353 (define_expand "xorsi3"
1354 [(set (match_operand:SI 0 "register_operand" "")
1355 (xor:SI (match_operand:SI 1 "register_operand" "")
1356 (match_operand:SI 2 "nonmemory_operand" "")))]
1357 ""
1358 "")
1359
1360 ;; ----------------------------------------------------------------------
1361 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1362 ;; ----------------------------------------------------------------------
1363
1364 (define_insn "*logicalhi3"
1365 [(set (match_operand:HI 0 "register_operand" "=r")
1366 (match_operator:HI 3 "bit_operator"
1367 [(match_operand:HI 1 "register_operand" "%0")
1368 (match_operand:HI 2 "nonmemory_operand" "rn")]))]
1369 ""
1370 "* return output_logical_op (HImode, operands);"
1371 [(set (attr "length")
1372 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1373 (set (attr "cc")
1374 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1375
1376 (define_insn "*logicalsi3"
1377 [(set (match_operand:SI 0 "register_operand" "=r")
1378 (match_operator:SI 3 "bit_operator"
1379 [(match_operand:SI 1 "register_operand" "%0")
1380 (match_operand:SI 2 "nonmemory_operand" "rn")]))]
1381 ""
1382 "* return output_logical_op (SImode, operands);"
1383 [(set (attr "length")
1384 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1385 (set (attr "cc")
1386 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1387 \f
1388 ;; ----------------------------------------------------------------------
1389 ;; NEGATION INSTRUCTIONS
1390 ;; ----------------------------------------------------------------------
1391
1392 (define_insn "negqi2"
1393 [(set (match_operand:QI 0 "register_operand" "=r")
1394 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1395 ""
1396 "neg %X0"
1397 [(set_attr "length" "2")
1398 (set_attr "cc" "set_zn")])
1399
1400 (define_expand "neghi2"
1401 [(set (match_operand:HI 0 "register_operand" "")
1402 (neg:HI (match_operand:HI 1 "register_operand" "")))]
1403 ""
1404 "
1405 {
1406 if (TARGET_H8300)
1407 {
1408 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1409 DONE;
1410 }
1411 }")
1412
1413 (define_expand "neghi2_h8300"
1414 [(set (match_dup 2)
1415 (not:HI (match_operand:HI 1 "register_operand" "")))
1416 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1417 (set (match_operand:HI 0 "register_operand" "")
1418 (match_dup 2))]
1419 ""
1420 "operands[2] = gen_reg_rtx (HImode);")
1421
1422 (define_insn "*neghi2_h8300hs"
1423 [(set (match_operand:HI 0 "register_operand" "=r")
1424 (neg:HI (match_operand:HI 1 "register_operand" "0")))]
1425 "TARGET_H8300H || TARGET_H8300S"
1426 "neg %T0"
1427 [(set_attr "length" "2")
1428 (set_attr "cc" "set_zn")])
1429
1430 (define_expand "negsi2"
1431 [(set (match_operand:SI 0 "register_operand" "")
1432 (neg:SI (match_operand:SI 1 "register_operand" "")))]
1433 ""
1434 "
1435 {
1436 if (TARGET_H8300)
1437 {
1438 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1439 DONE;
1440 }
1441 }")
1442
1443 (define_expand "negsi2_h8300"
1444 [(set (match_dup 2)
1445 (not:SI (match_operand:SI 1 "register_operand" "")))
1446 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1447 (set (match_operand:SI 0 "register_operand" "")
1448 (match_dup 2))]
1449 ""
1450 "operands[2] = gen_reg_rtx (SImode);")
1451
1452 (define_insn "*negsi2_h8300hs"
1453 [(set (match_operand:SI 0 "register_operand" "=r")
1454 (neg:SI (match_operand:SI 1 "register_operand" "0")))]
1455 "TARGET_H8300H || TARGET_H8300S"
1456 "neg %S0"
1457 [(set_attr "length" "2")
1458 (set_attr "cc" "set_zn")])
1459
1460 (define_expand "negsf2"
1461 [(set (match_operand:SF 0 "register_operand" "")
1462 (neg:SF (match_operand:SF 1 "register_operand" "")))]
1463 ""
1464 "")
1465
1466 (define_insn "*negsf2_h8300"
1467 [(set (match_operand:SF 0 "register_operand" "=r")
1468 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1469 "TARGET_H8300"
1470 "xor.b\\t#128,%z0"
1471 [(set_attr "length" "2")])
1472
1473 (define_insn "*negsf2_h8300hs"
1474 [(set (match_operand:SF 0 "register_operand" "=r")
1475 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1476 "TARGET_H8300H || TARGET_H8300S"
1477 "xor.w\\t#32768,%e0"
1478 [(set_attr "length" "4")])
1479 \f
1480 ;; ----------------------------------------------------------------------
1481 ;; ABSOLUTE VALUE INSTRUCTIONS
1482 ;; ----------------------------------------------------------------------
1483
1484 (define_expand "abssf2"
1485 [(set (match_operand:SF 0 "register_operand" "")
1486 (abs:SF (match_operand:SF 1 "register_operand" "")))]
1487 ""
1488 "")
1489
1490 (define_insn "*abssf2_h8300"
1491 [(set (match_operand:SF 0 "register_operand" "=r")
1492 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1493 "TARGET_H8300"
1494 "and.b\\t#127,%z0"
1495 [(set_attr "length" "2")])
1496
1497 (define_insn "*abssf2_h8300hs"
1498 [(set (match_operand:SF 0 "register_operand" "=r")
1499 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1500 "TARGET_H8300H || TARGET_H8300S"
1501 "and.w\\t#32767,%e0"
1502 [(set_attr "length" "4")])
1503 \f
1504 ;; ----------------------------------------------------------------------
1505 ;; NOT INSTRUCTIONS
1506 ;; ----------------------------------------------------------------------
1507
1508 (define_insn "one_cmplqi2"
1509 [(set (match_operand:QI 0 "register_operand" "=r")
1510 (not:QI (match_operand:QI 1 "register_operand" "0")))]
1511 ""
1512 "not %X0"
1513 [(set_attr "length" "2")
1514 (set_attr "cc" "set_znv")])
1515
1516 (define_expand "one_cmplhi2"
1517 [(set (match_operand:HI 0 "register_operand" "=r")
1518 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1519 ""
1520 "")
1521
1522 (define_insn "*one_cmplhi2_h8300"
1523 [(set (match_operand:HI 0 "register_operand" "=r")
1524 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1525 "TARGET_H8300"
1526 "not %s0\;not %t0"
1527 [(set_attr "length" "4")])
1528
1529 (define_insn "*one_cmplhi2_h8300hs"
1530 [(set (match_operand:HI 0 "register_operand" "=r")
1531 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1532 "TARGET_H8300H || TARGET_H8300S"
1533 "not %T0"
1534 [(set_attr "cc" "set_znv")
1535 (set_attr "length" "2")])
1536
1537 (define_expand "one_cmplsi2"
1538 [(set (match_operand:SI 0 "register_operand" "=r")
1539 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1540 ""
1541 "")
1542
1543 (define_insn "*one_complsi2_h8300"
1544 [(set (match_operand:SI 0 "register_operand" "=r")
1545 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1546 "TARGET_H8300"
1547 "not %w0\;not %x0\;not %y0\;not %z0"
1548 [(set_attr "length" "8")])
1549
1550 (define_insn "*one_complsi2_h8300hs"
1551 [(set (match_operand:SI 0 "register_operand" "=r")
1552 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1553 "TARGET_H8300H || TARGET_H8300S"
1554 "not %S0"
1555 [(set_attr "cc" "set_znv")
1556 (set_attr "length" "2")])
1557 \f
1558 ;; ----------------------------------------------------------------------
1559 ;; JUMP INSTRUCTIONS
1560 ;; ----------------------------------------------------------------------
1561
1562 ;; Conditional jump instructions
1563
1564 (define_expand "ble"
1565 [(set (pc)
1566 (if_then_else (le (cc0)
1567 (const_int 0))
1568 (label_ref (match_operand 0 "" ""))
1569 (pc)))]
1570 ""
1571 "")
1572
1573 (define_expand "bleu"
1574 [(set (pc)
1575 (if_then_else (leu (cc0)
1576 (const_int 0))
1577 (label_ref (match_operand 0 "" ""))
1578 (pc)))]
1579 ""
1580 "")
1581
1582 (define_expand "bge"
1583 [(set (pc)
1584 (if_then_else (ge (cc0)
1585 (const_int 0))
1586 (label_ref (match_operand 0 "" ""))
1587 (pc)))]
1588 ""
1589 "")
1590
1591 (define_expand "bgeu"
1592 [(set (pc)
1593 (if_then_else (geu (cc0)
1594 (const_int 0))
1595 (label_ref (match_operand 0 "" ""))
1596 (pc)))]
1597 ""
1598 "")
1599
1600 (define_expand "blt"
1601 [(set (pc)
1602 (if_then_else (lt (cc0)
1603 (const_int 0))
1604 (label_ref (match_operand 0 "" ""))
1605 (pc)))]
1606 ""
1607 "")
1608
1609 (define_expand "bltu"
1610 [(set (pc)
1611 (if_then_else (ltu (cc0)
1612 (const_int 0))
1613 (label_ref (match_operand 0 "" ""))
1614 (pc)))]
1615 ""
1616 "")
1617
1618 (define_expand "bgt"
1619 [(set (pc)
1620 (if_then_else (gt (cc0)
1621 (const_int 0))
1622 (label_ref (match_operand 0 "" ""))
1623 (pc)))]
1624 ""
1625 "")
1626
1627 (define_expand "bgtu"
1628 [(set (pc)
1629 (if_then_else (gtu (cc0)
1630 (const_int 0))
1631 (label_ref (match_operand 0 "" ""))
1632 (pc)))]
1633 ""
1634 "")
1635
1636 (define_expand "beq"
1637 [(set (pc)
1638 (if_then_else (eq (cc0)
1639 (const_int 0))
1640 (label_ref (match_operand 0 "" ""))
1641 (pc)))]
1642 ""
1643 "")
1644
1645 (define_expand "bne"
1646 [(set (pc)
1647 (if_then_else (ne (cc0)
1648 (const_int 0))
1649 (label_ref (match_operand 0 "" ""))
1650 (pc)))]
1651 ""
1652 "")
1653
1654 (define_insn "branch_true"
1655 [(set (pc)
1656 (if_then_else (match_operator 1 "comparison_operator"
1657 [(cc0) (const_int 0)])
1658 (label_ref (match_operand 0 "" ""))
1659 (pc)))]
1660 ""
1661 "*
1662 {
1663 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1664 && (GET_CODE (operands[1]) == GT
1665 || GET_CODE (operands[1]) == GE
1666 || GET_CODE (operands[1]) == LE
1667 || GET_CODE (operands[1]) == LT))
1668 {
1669 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1670 return 0;
1671 }
1672
1673 if (get_attr_length (insn) == 2)
1674 return \"b%j1 %l0\";
1675 else if (get_attr_length (insn) == 4)
1676 return \"b%j1 %l0:16\";
1677 else
1678 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1679 }"
1680 [(set_attr "type" "branch")
1681 (set_attr "cc" "none")])
1682
1683 (define_insn "branch_false"
1684 [(set (pc)
1685 (if_then_else (match_operator 1 "comparison_operator"
1686 [(cc0) (const_int 0)])
1687 (pc)
1688 (label_ref (match_operand 0 "" ""))))]
1689 ""
1690 "*
1691 {
1692 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1693 && (GET_CODE (operands[1]) == GT
1694 || GET_CODE (operands[1]) == GE
1695 || GET_CODE (operands[1]) == LE
1696 || GET_CODE (operands[1]) == LT))
1697 {
1698 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1699 return 0;
1700 }
1701
1702 if (get_attr_length (insn) == 2)
1703 return \"b%k1 %l0\";
1704 else if (get_attr_length (insn) == 4)
1705 return \"b%k1 %l0:16\";
1706 else
1707 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1708 }"
1709 [(set_attr "type" "branch")
1710 (set_attr "cc" "none")])
1711
1712 ;; Unconditional and other jump instructions.
1713
1714 (define_insn "jump"
1715 [(set (pc)
1716 (label_ref (match_operand 0 "" "")))]
1717 ""
1718 "*
1719 {
1720 if (get_attr_length (insn) == 2)
1721 return \"bra %l0\";
1722 else if (get_attr_length (insn) == 4)
1723 return \"bra %l0:16\";
1724 else
1725 return \"jmp @%l0\";
1726 }"
1727 [(set_attr "type" "branch")
1728 (set_attr "cc" "none")])
1729
1730 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1731
1732 (define_expand "tablejump"
1733 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
1734 (use (label_ref (match_operand 1 "" "")))])]
1735 ""
1736 "")
1737
1738 (define_insn "*tablejump_h8300"
1739 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1740 (use (label_ref (match_operand 1 "" "")))]
1741 "TARGET_H8300"
1742 "jmp @%0"
1743 [(set_attr "cc" "none")
1744 (set_attr "length" "2")])
1745
1746 (define_insn "*tablejump_h8300hs_advanced"
1747 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1748 (use (label_ref (match_operand 1 "" "")))]
1749 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
1750 "jmp @%0"
1751 [(set_attr "cc" "none")
1752 (set_attr "length" "2")])
1753
1754 (define_insn "*tablejump_h8300hs_normal"
1755 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1756 (use (label_ref (match_operand 1 "" "")))]
1757 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1758 "jmp @%S0"
1759 [(set_attr "cc" "none")
1760 (set_attr "length" "2")])
1761
1762 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1763
1764 (define_expand "indirect_jump"
1765 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1766 ""
1767 "")
1768
1769 (define_insn "*indirect_jump_h8300"
1770 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1771 "TARGET_H8300"
1772 "jmp @%0"
1773 [(set_attr "cc" "none")
1774 (set_attr "length" "2")])
1775
1776 (define_insn "*indirect_jump_h8300hs_advanced"
1777 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1778 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
1779 "jmp @%0"
1780 [(set_attr "cc" "none")
1781 (set_attr "length" "2")])
1782
1783 (define_insn "*indirect_jump_h8300hs_normal"
1784 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1785 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1786 "jmp @%S0"
1787 [(set_attr "cc" "none")
1788 (set_attr "length" "2")])
1789
1790 ;; Call subroutine with no return value.
1791
1792 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1793
1794 (define_insn "call"
1795 [(call (match_operand:QI 0 "call_insn_operand" "or")
1796 (match_operand:HI 1 "general_operand" "g"))]
1797 ""
1798 "*
1799 {
1800 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1801 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1802 return \"jsr\\t@%0:8\";
1803 else
1804 return \"jsr\\t%0\";
1805 }"
1806 [(set (attr "length")
1807 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1808 (const_int 2)
1809 (const_int 4)))])
1810
1811 ;; Call subroutine, returning value in operand 0
1812 ;; (which must be a hard register).
1813
1814 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1815
1816 (define_insn "call_value"
1817 [(set (match_operand 0 "" "=r")
1818 (call (match_operand:QI 1 "call_insn_operand" "or")
1819 (match_operand:HI 2 "general_operand" "g")))]
1820 ""
1821 "*
1822 {
1823 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1824 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1825 return \"jsr\\t@%1:8\";
1826 else
1827 return \"jsr\\t%1\";
1828 }"
1829 [(set (attr "length")
1830 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1831 (const_int 2)
1832 (const_int 4)))])
1833
1834 (define_insn "nop"
1835 [(const_int 0)]
1836 ""
1837 "nop"
1838 [(set_attr "cc" "none")
1839 (set_attr "length" "2")])
1840 \f
1841 ;; ----------------------------------------------------------------------
1842 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
1843 ;; ----------------------------------------------------------------------
1844
1845 (define_expand "push_h8300"
1846 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
1847 (match_operand:HI 0 "register_operand" ""))]
1848 "TARGET_H8300"
1849 "")
1850
1851 (define_expand "push_h8300hs_advanced"
1852 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
1853 (match_operand:SI 0 "register_operand" ""))]
1854 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
1855 "")
1856
1857 (define_expand "push_h8300hs_normal"
1858 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
1859 (match_operand:SI 0 "register_operand" ""))]
1860 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
1861 "")
1862
1863 (define_expand "pop_h8300"
1864 [(set (match_operand:HI 0 "register_operand" "")
1865 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
1866 "TARGET_H8300"
1867 "")
1868
1869 (define_expand "pop_h8300hs_advanced"
1870 [(set (match_operand:SI 0 "register_operand" "")
1871 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
1872 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
1873 "")
1874
1875 (define_expand "pop_h8300hs_normal"
1876 [(set (match_operand:SI 0 "register_operand" "")
1877 (mem:SI (post_inc:HI (reg:HI SP_REG))))]
1878 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
1879 "")
1880
1881 (define_insn "stm_h8300s_2_advanced"
1882 [(set (reg:SI SP_REG)
1883 (plus:SI (reg:SI SP_REG) (const_int -8)))
1884 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1885 (match_operand:SI 0 "register_operand" ""))
1886 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1887 (match_operand:SI 1 "register_operand" ""))]
1888 "TARGET_H8300S && !TARGET_NORMAL_MODE
1889 && h8300_regs_ok_for_stm (2, operands)"
1890 "stm.l\\t%S0-%S1,@-er7"
1891 [(set_attr "cc" "none")
1892 (set_attr "length" "4")])
1893
1894 (define_insn "stm_h8300s_2_normal"
1895 [(set (reg:HI SP_REG)
1896 (plus:HI (reg:HI SP_REG) (const_int -8)))
1897 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
1898 (match_operand:SI 0 "register_operand" ""))
1899 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
1900 (match_operand:SI 1 "register_operand" ""))]
1901 "TARGET_H8300S && TARGET_NORMAL_MODE
1902 && h8300_regs_ok_for_stm (2, operands)"
1903 "stm.l\\t%S0-%S1,@-er7"
1904 [(set_attr "cc" "none")
1905 (set_attr "length" "4")])
1906
1907 (define_expand "stm_h8300s_2"
1908 [(match_operand:SI 0 "register_operand" "")
1909 (match_operand:SI 1 "register_operand" "")]
1910 "TARGET_H8300S
1911 && h8300_regs_ok_for_stm (2, operands)"
1912 "
1913 {
1914 if (!TARGET_NORMAL_MODE)
1915 emit_insn (gen_stm_h8300s_2_advanced (operands[0], operands[1]));
1916 else
1917 emit_insn (gen_stm_h8300s_2_normal (operands[0], operands[1]));
1918 DONE;
1919 }")
1920
1921 (define_insn "stm_h8300s_3_advanced"
1922 [(set (reg:SI SP_REG)
1923 (plus:SI (reg:SI SP_REG) (const_int -12)))
1924 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1925 (match_operand:SI 0 "register_operand" ""))
1926 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1927 (match_operand:SI 1 "register_operand" ""))
1928 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1929 (match_operand:SI 2 "register_operand" ""))]
1930 "TARGET_H8300S && !TARGET_NORMAL_MODE
1931 && h8300_regs_ok_for_stm (3, operands)"
1932 "stm.l\\t%S0-%S2,@-er7"
1933 [(set_attr "cc" "none")
1934 (set_attr "length" "4")])
1935
1936 (define_insn "stm_h8300s_3_normal"
1937 [(set (reg:HI SP_REG)
1938 (plus:HI (reg:HI SP_REG) (const_int -12)))
1939 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
1940 (match_operand:SI 0 "register_operand" ""))
1941 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
1942 (match_operand:SI 1 "register_operand" ""))
1943 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
1944 (match_operand:SI 2 "register_operand" ""))]
1945 "TARGET_H8300S && TARGET_NORMAL_MODE
1946 && h8300_regs_ok_for_stm (3, operands)"
1947 "stm.l\\t%S0-%S2,@-er7"
1948 [(set_attr "cc" "none")
1949 (set_attr "length" "4")])
1950
1951 (define_expand "stm_h8300s_3"
1952 [(match_operand:SI 0 "register_operand" "")
1953 (match_operand:SI 1 "register_operand" "")
1954 (match_operand:SI 2 "register_operand" "")]
1955 "TARGET_H8300S
1956 && h8300_regs_ok_for_stm (3, operands)"
1957 "
1958 {
1959 if (!TARGET_NORMAL_MODE)
1960 emit_insn (gen_stm_h8300s_3_advanced (operands[0], operands[1],
1961 operands[2]));
1962 else
1963 emit_insn (gen_stm_h8300s_3_normal (operands[0], operands[1],
1964 operands[2]));
1965 DONE;
1966 }")
1967
1968 (define_insn "stm_h8300s_4_advanced"
1969 [(set (reg:SI SP_REG)
1970 (plus:SI (reg:SI SP_REG) (const_int -16)))
1971 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1972 (match_operand:SI 0 "register_operand" ""))
1973 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1974 (match_operand:SI 1 "register_operand" ""))
1975 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1976 (match_operand:SI 2 "register_operand" ""))
1977 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
1978 (match_operand:SI 3 "register_operand" ""))]
1979 "TARGET_H8300S && !TARGET_NORMAL_MODE
1980 && h8300_regs_ok_for_stm (4, operands)"
1981 "stm.l\\t%S0-%S3,@-er7"
1982 [(set_attr "cc" "none")
1983 (set_attr "length" "4")])
1984
1985 (define_insn "stm_h8300s_4_normal"
1986 [(set (reg:HI SP_REG)
1987 (plus:HI (reg:HI SP_REG) (const_int -16)))
1988 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
1989 (match_operand:SI 0 "register_operand" ""))
1990 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
1991 (match_operand:SI 1 "register_operand" ""))
1992 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
1993 (match_operand:SI 2 "register_operand" ""))
1994 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
1995 (match_operand:SI 3 "register_operand" ""))]
1996 "TARGET_H8300S && TARGET_NORMAL_MODE
1997 && h8300_regs_ok_for_stm (4, operands)"
1998 "stm.l\\t%S0-%S3,@-er7"
1999 [(set_attr "cc" "none")
2000 (set_attr "length" "4")])
2001
2002 (define_expand "stm_h8300s_4"
2003 [(match_operand:SI 0 "register_operand" "")
2004 (match_operand:SI 1 "register_operand" "")
2005 (match_operand:SI 2 "register_operand" "")
2006 (match_operand:SI 3 "register_operand" "")]
2007 "TARGET_H8300S
2008 && h8300_regs_ok_for_stm (4, operands)"
2009 "
2010 {
2011 if (!TARGET_NORMAL_MODE)
2012 emit_insn (gen_stm_h8300s_4_advanced (operands[0], operands[1],
2013 operands[2], operands[3]));
2014 else
2015 emit_insn (gen_stm_h8300s_4_normal (operands[0], operands[1],
2016 operands[2], operands[3]));
2017 DONE;
2018 }")
2019
2020 (define_insn "ldm_h8300s_2_advanced"
2021 [(set (reg:SI SP_REG)
2022 (plus:SI (reg:SI SP_REG) (const_int 8)))
2023 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2024 (match_operand:SI 0 "register_operand" ""))
2025 (set (mem:SI (reg:SI SP_REG))
2026 (match_operand:SI 1 "register_operand" ""))]
2027 "TARGET_H8300S && !TARGET_NORMAL_MODE
2028 && h8300_regs_ok_for_stm (2, operands)"
2029 "ldm.l\\t@er7+,%S0-%S1"
2030 [(set_attr "cc" "none")
2031 (set_attr "length" "4")])
2032
2033 (define_insn "ldm_h8300s_2_normal"
2034 [(set (reg:HI SP_REG)
2035 (plus:HI (reg:HI SP_REG) (const_int 8)))
2036 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2037 (match_operand:SI 0 "register_operand" ""))
2038 (set (mem:SI (reg:HI SP_REG))
2039 (match_operand:SI 1 "register_operand" ""))]
2040 "TARGET_H8300S && TARGET_NORMAL_MODE
2041 && h8300_regs_ok_for_stm (2, operands)"
2042 "ldm.l\\t@er7+,%S0-%S1"
2043 [(set_attr "cc" "none")
2044 (set_attr "length" "4")])
2045
2046 (define_expand "ldm_h8300s_2"
2047 [(match_operand:SI 0 "register_operand" "")
2048 (match_operand:SI 1 "register_operand" "")]
2049 "TARGET_H8300S
2050 && h8300_regs_ok_for_stm (2, operands)"
2051 "
2052 {
2053 if (!TARGET_NORMAL_MODE)
2054 emit_insn (gen_ldm_h8300s_2_advanced (operands[0], operands[1]));
2055 else
2056 emit_insn (gen_ldm_h8300s_2_normal (operands[0], operands[1]));
2057 DONE;
2058 }")
2059
2060 (define_insn "ldm_h8300s_3_advanced"
2061 [(set (reg:SI SP_REG)
2062 (plus:SI (reg:SI SP_REG) (const_int 12)))
2063 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
2064 (match_operand:SI 0 "register_operand" ""))
2065 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2066 (match_operand:SI 1 "register_operand" ""))
2067 (set (mem:SI (reg:SI SP_REG))
2068 (match_operand:SI 2 "register_operand" ""))]
2069 "TARGET_H8300S && !TARGET_NORMAL_MODE
2070 && h8300_regs_ok_for_stm (3, operands)"
2071 "ldm.l\\t@er7+,%S0-%S2"
2072 [(set_attr "cc" "none")
2073 (set_attr "length" "4")])
2074
2075 (define_insn "ldm_h8300s_3_normal"
2076 [(set (reg:HI SP_REG)
2077 (plus:HI (reg:HI SP_REG) (const_int 12)))
2078 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 8)))
2079 (match_operand:SI 0 "register_operand" ""))
2080 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2081 (match_operand:SI 1 "register_operand" ""))
2082 (set (mem:SI (reg:HI SP_REG))
2083 (match_operand:SI 2 "register_operand" ""))]
2084 "TARGET_H8300S && TARGET_NORMAL_MODE
2085 && h8300_regs_ok_for_stm (3, operands)"
2086 "ldm.l\\t@er7+,%S0-%S2"
2087 [(set_attr "cc" "none")
2088 (set_attr "length" "4")])
2089
2090 (define_expand "ldm_h8300s_3"
2091 [(match_operand:SI 0 "register_operand" "")
2092 (match_operand:SI 1 "register_operand" "")
2093 (match_operand:SI 2 "register_operand" "")]
2094 "TARGET_H8300S
2095 && h8300_regs_ok_for_stm (3, operands)"
2096 "
2097 {
2098 if (!TARGET_NORMAL_MODE)
2099 emit_insn (gen_ldm_h8300s_3_advanced (operands[0], operands[1],
2100 operands[2]));
2101 else
2102 emit_insn (gen_ldm_h8300s_3_normal (operands[0], operands[1],
2103 operands[2]));
2104 DONE;
2105 }")
2106
2107 (define_insn "ldm_h8300s_4_advanced"
2108 [(set (reg:SI SP_REG)
2109 (plus:SI (reg:SI SP_REG) (const_int 16)))
2110 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 12)))
2111 (match_operand:SI 0 "register_operand" ""))
2112 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
2113 (match_operand:SI 1 "register_operand" ""))
2114 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2115 (match_operand:SI 2 "register_operand" ""))
2116 (set (mem:SI (reg:SI SP_REG))
2117 (match_operand:SI 3 "register_operand" ""))]
2118 "TARGET_H8300S && !TARGET_NORMAL_MODE
2119 && h8300_regs_ok_for_stm (4, operands)"
2120 "ldm.l\\t@er7+,%S0-%S3"
2121 [(set_attr "cc" "none")
2122 (set_attr "length" "4")])
2123
2124 (define_insn "ldm_h8300s_4_normal"
2125 [(set (reg:HI SP_REG)
2126 (plus:HI (reg:HI SP_REG) (const_int 16)))
2127 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 12)))
2128 (match_operand:SI 0 "register_operand" ""))
2129 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 8)))
2130 (match_operand:SI 1 "register_operand" ""))
2131 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2132 (match_operand:SI 2 "register_operand" ""))
2133 (set (mem:SI (reg:HI SP_REG))
2134 (match_operand:SI 3 "register_operand" ""))]
2135 "TARGET_H8300S && !TARGET_NORMAL_MODE
2136 && h8300_regs_ok_for_stm (4, operands)"
2137 "ldm.l\\t@er7+,%S0-%S3"
2138 [(set_attr "cc" "none")
2139 (set_attr "length" "4")])
2140
2141 (define_expand "ldm_h8300s_4"
2142 [(match_operand:SI 0 "register_operand" "")
2143 (match_operand:SI 1 "register_operand" "")
2144 (match_operand:SI 2 "register_operand" "")
2145 (match_operand:SI 3 "register_operand" "")]
2146 "TARGET_H8300S && !TARGET_NORMAL_MODE
2147 && h8300_regs_ok_for_stm (4, operands)"
2148 "
2149 {
2150 if (!TARGET_NORMAL_MODE)
2151 emit_insn (gen_ldm_h8300s_4_advanced (operands[0], operands[1],
2152 operands[2], operands[3]));
2153 else
2154 emit_insn (gen_ldm_h8300s_4_normal (operands[0], operands[1],
2155 operands[2], operands[3]));
2156 DONE;
2157 }")
2158
2159 (define_expand "return"
2160 [(return)]
2161 "h8300_can_use_return_insn_p ()"
2162 "")
2163
2164 (define_insn "*return_1"
2165 [(return)]
2166 "reload_completed"
2167 "*
2168 {
2169 if (h8300_current_function_interrupt_function_p ())
2170 return \"rte\";
2171 else
2172 return \"rts\";
2173 }"
2174 [(set_attr "cc" "none")
2175 (set_attr "length" "2")])
2176
2177 (define_expand "prologue"
2178 [(const_int 0)]
2179 ""
2180 "h8300_expand_prologue (); DONE;")
2181
2182 (define_expand "epilogue"
2183 [(return)]
2184 ""
2185 "h8300_expand_epilogue ();")
2186
2187 (define_insn "monitor_prologue"
2188 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2189 ""
2190 "*
2191 {
2192 if (TARGET_H8300)
2193 return \"subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr\";
2194 else if (TARGET_H8300H)
2195 return \"mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr\";
2196 else if (TARGET_H8300S)
2197 return \"stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\";
2198 abort ();
2199 }"
2200 [(set_attr "length" "20")])
2201 \f
2202 ;; ----------------------------------------------------------------------
2203 ;; EXTEND INSTRUCTIONS
2204 ;; ----------------------------------------------------------------------
2205
2206 (define_expand "zero_extendqihi2"
2207 [(set (match_operand:HI 0 "register_operand" "")
2208 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2209 ""
2210 "")
2211
2212 (define_insn "*zero_extendqihi2_h8300"
2213 [(set (match_operand:HI 0 "register_operand" "=r,r")
2214 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2215 "TARGET_H8300"
2216 "@
2217 mov.b #0,%t0
2218 #"
2219 [(set_attr "length" "2,10")])
2220
2221 (define_insn "*zero_extendqihi2_h8300hs"
2222 [(set (match_operand:HI 0 "register_operand" "=r,r")
2223 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2224 "TARGET_H8300H || TARGET_H8300S"
2225 "@
2226 extu.w %T0
2227 #"
2228 [(set_attr "length" "2,10")
2229 (set_attr "cc" "set_znv,set_znv")])
2230
2231 ;; Split the zero extension of a general operand (actually a memory
2232 ;; operand) into a load of the operand and the actual zero extension
2233 ;; so that 1) the length will be accurate, and 2) the zero extensions
2234 ;; appearing at the end of basic blocks may be merged.
2235
2236 (define_split
2237 [(set (match_operand:HI 0 "register_operand" "")
2238 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2239 "reload_completed"
2240 [(set (match_dup 2)
2241 (match_dup 1))
2242 (set (match_dup 0)
2243 (zero_extend:HI (match_dup 2)))]
2244 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2245
2246 (define_expand "zero_extendqisi2"
2247 [(set (match_operand:SI 0 "register_operand" "")
2248 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2249 ""
2250 "")
2251
2252 (define_insn "*zero_extendqisi2_h8300"
2253 [(set (match_operand:SI 0 "register_operand" "=r,r")
2254 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2255 "TARGET_H8300"
2256 "@
2257 mov.b #0,%x0\;sub.w %e0,%e0
2258 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
2259 [(set_attr "length" "4,8")])
2260
2261 (define_insn "*zero_extendqisi2_h8300hs"
2262 [(set (match_operand:SI 0 "register_operand" "=r,r")
2263 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2264 "TARGET_H8300H || TARGET_H8300S"
2265 "#")
2266
2267 (define_split
2268 [(set (match_operand:SI 0 "register_operand" "")
2269 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2270 "(TARGET_H8300H || TARGET_H8300S)
2271 && reg_overlap_mentioned_p (operands[0], operands[1])
2272 && reload_completed"
2273 [(set (match_dup 2)
2274 (match_dup 1))
2275 (set (match_dup 3)
2276 (zero_extend:HI (match_dup 2)))
2277 (set (match_dup 0)
2278 (zero_extend:SI (match_dup 3)))]
2279 "operands[2] = gen_lowpart (QImode, operands[0]);
2280 operands[3] = gen_lowpart (HImode, operands[0]);")
2281
2282 (define_split
2283 [(set (match_operand:SI 0 "register_operand" "")
2284 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2285 "(TARGET_H8300H || TARGET_H8300S)
2286 && !reg_overlap_mentioned_p (operands[0], operands[1])
2287 && reload_completed"
2288 [(set (match_dup 0)
2289 (const_int 0))
2290 (set (strict_low_part (match_dup 2))
2291 (match_dup 1))]
2292 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2293
2294 (define_expand "zero_extendhisi2"
2295 [(set (match_operand:SI 0 "register_operand" "")
2296 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2297 ""
2298 "")
2299
2300 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
2301 (define_insn "*zero_extendhisi2_h8300"
2302 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2303 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
2304 "TARGET_H8300"
2305 "@
2306 sub.w %e0,%e0
2307 mov.w %f1,%f0\;sub.w %e0,%e0
2308 mov.w %e1,%f0\;sub.w %e0,%e0"
2309 [(set_attr "length" "2,4,6")])
2310
2311 (define_insn "*zero_extendhisi2_h8300hs"
2312 [(set (match_operand:SI 0 "register_operand" "=r")
2313 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2314 "TARGET_H8300H || TARGET_H8300S"
2315 "extu.l %S0"
2316 [(set_attr "length" "2")
2317 (set_attr "cc" "set_znv")])
2318
2319 (define_expand "extendqihi2"
2320 [(set (match_operand:HI 0 "register_operand" "")
2321 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
2322 ""
2323 "")
2324
2325 (define_insn "*extendqihi2_h8300"
2326 [(set (match_operand:HI 0 "register_operand" "=r,r")
2327 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2328 "TARGET_H8300"
2329 "@
2330 bld #7,%s0\;subx %t0,%t0
2331 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
2332 [(set_attr "length" "4,8")])
2333
2334 (define_insn "*extendqihi2_h8300hs"
2335 [(set (match_operand:HI 0 "register_operand" "=r")
2336 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
2337 "TARGET_H8300H || TARGET_H8300S"
2338 "exts.w %T0"
2339 [(set_attr "length" "2")
2340 (set_attr "cc" "set_znv")])
2341
2342 (define_expand "extendqisi2"
2343 [(set (match_operand:SI 0 "register_operand" "")
2344 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2345 ""
2346 "")
2347
2348 (define_insn "*extendqisi2_h8300"
2349 [(set (match_operand:SI 0 "register_operand" "")
2350 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2351 "TARGET_H8300"
2352 "@
2353 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
2354 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
2355 [(set_attr "length" "8,12")])
2356
2357 ;; The following pattern is needed because without the pattern, the
2358 ;; combiner would split (sign_extend:SI (reg:QI)) into into two 24-bit
2359 ;; shifts, one ashift and one ashiftrt.
2360
2361 (define_insn_and_split "*extendqisi2_h8300hs"
2362 [(set (match_operand:SI 0 "register_operand" "=r")
2363 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2364 "(TARGET_H8300H || TARGET_H8300S)"
2365 "#"
2366 "&& reload_completed"
2367 [(set (match_dup 2)
2368 (sign_extend:HI (match_dup 1)))
2369 (set (match_dup 0)
2370 (sign_extend:SI (match_dup 2)))]
2371 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2372
2373 (define_expand "extendhisi2"
2374 [(set (match_operand:SI 0 "register_operand" "")
2375 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2376 ""
2377 "")
2378
2379 (define_insn "*extendhisi2_h8300"
2380 [(set (match_operand:SI 0 "register_operand" "=r,r")
2381 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
2382 "TARGET_H8300"
2383 "@
2384 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
2385 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
2386 [(set_attr "length" "6,10")])
2387
2388 (define_insn "*extendhisi2_h8300hs"
2389 [(set (match_operand:SI 0 "register_operand" "=r")
2390 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2391 "TARGET_H8300H || TARGET_H8300S"
2392 "exts.l %S0"
2393 [(set_attr "length" "2")
2394 (set_attr "cc" "set_znv")])
2395 \f
2396 ;; ----------------------------------------------------------------------
2397 ;; SHIFTS
2398 ;; ----------------------------------------------------------------------
2399 ;;
2400 ;; We make some attempt to provide real efficient shifting. One example is
2401 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
2402 ;; reg and moving 0 into the former reg.
2403 ;;
2404 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2405 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2406 ;; give the optimizer more cracks at the code. However, we wish to do things
2407 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
2408 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
2409 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
2410 ;; to detect cases it can optimize.
2411 ;;
2412 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2413 ;; easier "do it at insn emit time" route.
2414
2415 ;; QI BIT SHIFTS
2416
2417 (define_expand "ashlqi3"
2418 [(set (match_operand:QI 0 "register_operand" "")
2419 (ashift:QI (match_operand:QI 1 "register_operand" "")
2420 (match_operand:QI 2 "nonmemory_operand" "")))]
2421 ""
2422 "expand_a_shift (QImode, ASHIFT, operands); DONE;")
2423
2424 (define_expand "ashrqi3"
2425 [(set (match_operand:QI 0 "register_operand" "")
2426 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2427 (match_operand:QI 2 "nonmemory_operand" "")))]
2428 ""
2429 "expand_a_shift (QImode, ASHIFTRT, operands); DONE;")
2430
2431 (define_expand "lshrqi3"
2432 [(set (match_operand:QI 0 "register_operand" "")
2433 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2434 (match_operand:QI 2 "nonmemory_operand" "")))]
2435 ""
2436 "expand_a_shift (QImode, LSHIFTRT, operands); DONE;")
2437
2438 (define_insn "*shiftqi"
2439 [(set (match_operand:QI 0 "register_operand" "=r,r")
2440 (match_operator:QI 3 "nshift_operator"
2441 [ (match_operand:QI 1 "register_operand" "0,0")
2442 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2443 (clobber (match_scratch:QI 4 "=X,&r"))]
2444 ""
2445 "* return output_a_shift (operands);"
2446 [(set (attr "length")
2447 (symbol_ref "compute_a_shift_length (insn, operands)"))
2448 (set (attr "cc")
2449 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2450
2451 ;; HI BIT SHIFTS
2452
2453 (define_expand "ashlhi3"
2454 [(set (match_operand:HI 0 "register_operand" "")
2455 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
2456 (match_operand:QI 2 "nonmemory_operand" "")))]
2457 ""
2458 "expand_a_shift (HImode, ASHIFT, operands); DONE;")
2459
2460 (define_expand "lshrhi3"
2461 [(set (match_operand:HI 0 "register_operand" "")
2462 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
2463 (match_operand:QI 2 "nonmemory_operand" "")))]
2464 ""
2465 "expand_a_shift (HImode, LSHIFTRT, operands); DONE;")
2466
2467 (define_expand "ashrhi3"
2468 [(set (match_operand:HI 0 "register_operand" "")
2469 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
2470 (match_operand:QI 2 "nonmemory_operand" "")))]
2471 ""
2472 "expand_a_shift (HImode, ASHIFTRT, operands); DONE;")
2473
2474 (define_insn "*shifthi"
2475 [(set (match_operand:HI 0 "register_operand" "=r,r")
2476 (match_operator:HI 3 "nshift_operator"
2477 [ (match_operand:HI 1 "register_operand" "0,0")
2478 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
2479 (clobber (match_scratch:QI 4 "=X,&r"))]
2480 ""
2481 "* return output_a_shift (operands);"
2482 [(set (attr "length")
2483 (symbol_ref "compute_a_shift_length (insn, operands)"))
2484 (set (attr "cc")
2485 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2486
2487 ;; SI BIT SHIFTS
2488
2489 (define_expand "ashlsi3"
2490 [(set (match_operand:SI 0 "register_operand" "")
2491 (ashift:SI (match_operand:SI 1 "general_operand" "")
2492 (match_operand:QI 2 "nonmemory_operand" "")))]
2493 ""
2494 "expand_a_shift (SImode, ASHIFT, operands); DONE;")
2495
2496 (define_expand "lshrsi3"
2497 [(set (match_operand:SI 0 "register_operand" "")
2498 (lshiftrt:SI (match_operand:SI 1 "general_operand" "")
2499 (match_operand:QI 2 "nonmemory_operand" "")))]
2500 ""
2501 "expand_a_shift (SImode, LSHIFTRT, operands); DONE;")
2502
2503 (define_expand "ashrsi3"
2504 [(set (match_operand:SI 0 "register_operand" "")
2505 (ashiftrt:SI (match_operand:SI 1 "general_operand" "")
2506 (match_operand:QI 2 "nonmemory_operand" "")))]
2507 ""
2508 "expand_a_shift (SImode, ASHIFTRT, operands); DONE;")
2509
2510 (define_insn "*shiftsi"
2511 [(set (match_operand:SI 0 "register_operand" "=r,r")
2512 (match_operator:SI 3 "nshift_operator"
2513 [ (match_operand:SI 1 "register_operand" "0,0")
2514 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
2515 (clobber (match_scratch:QI 4 "=X,&r"))]
2516 ""
2517 "* return output_a_shift (operands);"
2518 [(set (attr "length")
2519 (symbol_ref "compute_a_shift_length (insn, operands)"))
2520 (set (attr "cc")
2521 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2522
2523 ;; Split a variable shift into a loop. If the register containing
2524 ;; the shift count dies, then we just use that register.
2525
2526 (define_split
2527 [(set (match_operand 0 "register_operand" "")
2528 (match_operator 2 "nshift_operator"
2529 [(match_dup 0)
2530 (match_operand:QI 1 "register_operand" "")]))
2531 (clobber (match_operand:QI 3 "register_operand" ""))]
2532 "flow2_completed
2533 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2534 [(set (cc0)
2535 (match_dup 1))
2536 (set (pc)
2537 (if_then_else (le (cc0) (const_int 0))
2538 (label_ref (match_dup 5))
2539 (pc)))
2540 (match_dup 4)
2541 (parallel
2542 [(set (match_dup 0)
2543 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2544 (clobber (scratch:QI))])
2545 (set (match_dup 1)
2546 (plus:QI (match_dup 1) (const_int -1)))
2547 (set (cc0)
2548 (match_dup 1))
2549 (set (pc)
2550 (if_then_else (ne (cc0) (const_int 0))
2551 (label_ref (match_dup 4))
2552 (pc)))
2553 (match_dup 5)]
2554 "operands[4] = gen_label_rtx ();
2555 operands[5] = gen_label_rtx ();")
2556
2557 (define_split
2558 [(set (match_operand 0 "register_operand" "")
2559 (match_operator 2 "nshift_operator"
2560 [(match_dup 0)
2561 (match_operand:QI 1 "register_operand" "")]))
2562 (clobber (match_operand:QI 3 "register_operand" ""))]
2563 "flow2_completed
2564 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2565 [(set (match_dup 3)
2566 (match_dup 1))
2567 (set (cc0)
2568 (match_dup 3))
2569 (set (pc)
2570 (if_then_else (le (cc0) (const_int 0))
2571 (label_ref (match_dup 5))
2572 (pc)))
2573 (match_dup 4)
2574 (parallel
2575 [(set (match_dup 0)
2576 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2577 (clobber (scratch:QI))])
2578 (set (match_dup 3)
2579 (plus:QI (match_dup 3) (const_int -1)))
2580 (set (cc0)
2581 (match_dup 3))
2582 (set (pc)
2583 (if_then_else (ne (cc0) (const_int 0))
2584 (label_ref (match_dup 4))
2585 (pc)))
2586 (match_dup 5)]
2587 "operands[4] = gen_label_rtx ();
2588 operands[5] = gen_label_rtx ();")
2589 \f
2590 ;; ----------------------------------------------------------------------
2591 ;; ROTATIONS
2592 ;; ----------------------------------------------------------------------
2593
2594 (define_expand "rotlqi3"
2595 [(set (match_operand:QI 0 "register_operand" "")
2596 (rotate:QI (match_operand:QI 1 "register_operand" "")
2597 (match_operand:QI 2 "nonmemory_operand" "")))]
2598 ""
2599 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2600
2601 (define_insn "*rotlqi3_1"
2602 [(set (match_operand:QI 0 "register_operand" "=r")
2603 (rotate:QI (match_operand:QI 1 "register_operand" "0")
2604 (match_operand:QI 2 "immediate_operand" "")))]
2605 ""
2606 "* return output_a_rotate (ROTATE, operands);"
2607 [(set (attr "length")
2608 (symbol_ref "compute_a_rotate_length (operands)"))])
2609
2610 (define_expand "rotlhi3"
2611 [(set (match_operand:HI 0 "register_operand" "")
2612 (rotate:HI (match_operand:HI 1 "register_operand" "")
2613 (match_operand:QI 2 "nonmemory_operand" "")))]
2614 ""
2615 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2616
2617 (define_insn "*rotlhi3_1"
2618 [(set (match_operand:HI 0 "register_operand" "=r")
2619 (rotate:HI (match_operand:HI 1 "register_operand" "0")
2620 (match_operand:QI 2 "immediate_operand" "")))]
2621 ""
2622 "* return output_a_rotate (ROTATE, operands);"
2623 [(set (attr "length")
2624 (symbol_ref "compute_a_rotate_length (operands)"))])
2625
2626 (define_expand "rotlsi3"
2627 [(set (match_operand:SI 0 "register_operand" "")
2628 (rotate:SI (match_operand:SI 1 "register_operand" "")
2629 (match_operand:QI 2 "nonmemory_operand" "")))]
2630 "TARGET_H8300H || TARGET_H8300S"
2631 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2632
2633 (define_insn "*rotlsi3_1"
2634 [(set (match_operand:SI 0 "register_operand" "=r")
2635 (rotate:SI (match_operand:SI 1 "register_operand" "0")
2636 (match_operand:QI 2 "immediate_operand" "")))]
2637 "TARGET_H8300H || TARGET_H8300S"
2638 "* return output_a_rotate (ROTATE, operands);"
2639 [(set (attr "length")
2640 (symbol_ref "compute_a_rotate_length (operands)"))])
2641 \f
2642 ;; -----------------------------------------------------------------
2643 ;; BIT FIELDS
2644 ;; -----------------------------------------------------------------
2645 ;; The H8/300 has given 1/8th of its opcode space to bitfield
2646 ;; instructions so let's use them as well as we can.
2647
2648 ;; You'll never believe all these patterns perform one basic action --
2649 ;; load a bit from the source, optionally invert the bit, then store it
2650 ;; in the destination (which is known to be zero).
2651 ;;
2652 ;; Combine obviously need some work to better identify this situation and
2653 ;; canonicalize the form better.
2654
2655 ;;
2656 ;; Normal loads with a 16bit destination.
2657 ;;
2658
2659 (define_insn ""
2660 [(set (match_operand:HI 0 "register_operand" "=&r")
2661 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2662 (const_int 1)
2663 (match_operand:HI 2 "immediate_operand" "n")))]
2664 "TARGET_H8300"
2665 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
2666 [(set_attr "length" "6")])
2667
2668 ;;
2669 ;; Inverted loads with a 16bit destination.
2670 ;;
2671
2672 (define_insn ""
2673 [(set (match_operand:HI 0 "register_operand" "=&r")
2674 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
2675 (match_operand:HI 3 "const_int_operand" "n"))
2676 (const_int 1)
2677 (match_operand:HI 2 "const_int_operand" "n")))]
2678 "TARGET_H8300
2679 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2680 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2681 [(set_attr "length" "8")])
2682
2683 ;;
2684 ;; Normal loads with a 32bit destination.
2685 ;;
2686
2687 (define_insn "*extzv_1_r_h8300"
2688 [(set (match_operand:SI 0 "register_operand" "=&r")
2689 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2690 (const_int 1)
2691 (match_operand 2 "const_int_operand" "n")))]
2692 "TARGET_H8300
2693 && INTVAL (operands[2]) < 16"
2694 "* return output_simode_bld (0, operands);"
2695 [(set_attr "length" "8")])
2696
2697 (define_insn "*extzv_1_r_h8300hs"
2698 [(set (match_operand:SI 0 "register_operand" "=r,r")
2699 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2700 (const_int 1)
2701 (match_operand 2 "const_int_operand" "n,n")))]
2702 "(TARGET_H8300H || TARGET_H8300S)
2703 && INTVAL (operands[2]) < 16"
2704 "* return output_simode_bld (0, operands);"
2705 [(set_attr "cc" "set_znv,set_znv")
2706 (set_attr "length" "8,6")])
2707
2708 ;;
2709 ;; Inverted loads with a 32bit destination.
2710 ;;
2711
2712 (define_insn "*extzv_1_r_inv_h8300"
2713 [(set (match_operand:SI 0 "register_operand" "=&r")
2714 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2715 (match_operand:HI 3 "const_int_operand" "n"))
2716 (const_int 1)
2717 (match_operand 2 "const_int_operand" "n")))]
2718 "TARGET_H8300
2719 && INTVAL (operands[2]) < 16
2720 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2721 "* return output_simode_bld (1, operands);"
2722 [(set_attr "length" "8")])
2723
2724 (define_insn "*extzv_1_r_inv_h8300hs"
2725 [(set (match_operand:SI 0 "register_operand" "=r,r")
2726 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
2727 (match_operand 3 "const_int_operand" "n,n"))
2728 (const_int 1)
2729 (match_operand 2 "const_int_operand" "n,n")))]
2730 "(TARGET_H8300H || TARGET_H8300S)
2731 && INTVAL (operands[2]) < 16
2732 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2733 "* return output_simode_bld (1, operands);"
2734 [(set_attr "cc" "set_znv,set_znv")
2735 (set_attr "length" "8,6")])
2736
2737 (define_expand "insv"
2738 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2739 (match_operand:HI 1 "general_operand" "")
2740 (match_operand:HI 2 "general_operand" ""))
2741 (match_operand:HI 3 "general_operand" ""))]
2742 "TARGET_H8300"
2743 "
2744 {
2745 /* We only have single bit bit-field instructions. */
2746 if (INTVAL (operands[1]) != 1)
2747 FAIL;
2748
2749 /* For now, we don't allow memory operands. */
2750 if (GET_CODE (operands[0]) == MEM
2751 || GET_CODE (operands[3]) == MEM)
2752 FAIL;
2753 }")
2754
2755 (define_insn ""
2756 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2757 (const_int 1)
2758 (match_operand:HI 1 "immediate_operand" "n"))
2759 (match_operand:HI 2 "register_operand" "r"))]
2760 ""
2761 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2762 [(set_attr "length" "4")])
2763
2764 (define_expand "extzv"
2765 [(set (match_operand:HI 0 "register_operand" "")
2766 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2767 (match_operand:HI 2 "general_operand" "")
2768 (match_operand:HI 3 "general_operand" "")))]
2769 "TARGET_H8300"
2770 "
2771 {
2772 /* We only have single bit bit-field instructions. */
2773 if (INTVAL (operands[2]) != 1)
2774 FAIL;
2775
2776 /* For now, we don't allow memory operands. */
2777 if (GET_CODE (operands[1]) == MEM)
2778 FAIL;
2779 }")
2780
2781 ;; BAND, BOR, and BXOR patterns
2782
2783 (define_insn ""
2784 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2785 (match_operator:HI 4 "bit_operator"
2786 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2787 (const_int 1)
2788 (match_operand:HI 2 "immediate_operand" "n"))
2789 (match_operand:HI 3 "bit_operand" "0")]))]
2790 ""
2791 "bld %Z2,%Y1\;b%c4 #0,%R0\;bst #0,%R0; bl1"
2792 [(set_attr "length" "6")])
2793
2794 (define_insn ""
2795 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2796 (match_operator:HI 5 "bit_operator"
2797 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2798 (const_int 1)
2799 (match_operand:HI 2 "immediate_operand" "n"))
2800 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2801 (const_int 1)
2802 (match_operand:HI 4 "immediate_operand" "n"))]))]
2803 ""
2804 "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #0,%R0; bl3"
2805 [(set_attr "length" "6")])
2806 \f
2807 ;; -----------------------------------------------------------------
2808 ;; COMBINE PATTERNS
2809 ;; -----------------------------------------------------------------
2810
2811 ;; insv:SI
2812
2813 (define_insn "*insv_si_1_n"
2814 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2815 (const_int 1)
2816 (match_operand:SI 1 "const_int_operand" "n"))
2817 (match_operand:SI 2 "register_operand" "r"))]
2818 "(TARGET_H8300H || TARGET_H8300S)
2819 && INTVAL (operands[1]) < 16"
2820 "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
2821 [(set_attr "length" "4")])
2822
2823 (define_insn "*insv_si_1_n_lshiftrt"
2824 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2825 (const_int 1)
2826 (match_operand:SI 1 "const_int_operand" "n"))
2827 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2828 (match_operand:SI 3 "const_int_operand" "n")))]
2829 "(TARGET_H8300H || TARGET_H8300S)
2830 && INTVAL (operands[1]) < 16
2831 && INTVAL (operands[3]) < 16"
2832 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
2833 [(set_attr "length" "4")])
2834
2835 (define_insn "*insv_si_1_n_lshiftrt_16"
2836 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2837 (const_int 1)
2838 (match_operand:SI 1 "const_int_operand" "n"))
2839 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2840 (const_int 16)))]
2841 "(TARGET_H8300H || TARGET_H8300S)
2842 && INTVAL (operands[1]) < 16"
2843 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
2844 [(set_attr "length" "6")])
2845
2846 (define_insn "*insv_si_8_8"
2847 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2848 (const_int 8)
2849 (const_int 8))
2850 (match_operand:SI 1 "register_operand" "r"))]
2851 "TARGET_H8300H || TARGET_H8300S"
2852 "mov.b\\t%w1,%x0"
2853 [(set_attr "length" "2")])
2854
2855 (define_insn "*insv_si_8_8_lshiftrt_8"
2856 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2857 (const_int 8)
2858 (const_int 8))
2859 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2860 (const_int 8)))]
2861 "TARGET_H8300H || TARGET_H8300S"
2862 "mov.b\\t%x1,%x0"
2863 [(set_attr "length" "2")])
2864
2865 ;; extzv:SI
2866
2867 (define_insn "*extzv_8_8"
2868 [(set (match_operand:SI 0 "register_operand" "=r,r")
2869 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2870 (const_int 8)
2871 (const_int 8)))]
2872 "TARGET_H8300H || TARGET_H8300S"
2873 "@
2874 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
2875 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
2876 [(set_attr "cc" "set_znv,clobber")
2877 (set_attr "length" "6,4")])
2878
2879 (define_insn "*extzv_8_16"
2880 [(set (match_operand:SI 0 "register_operand" "=r")
2881 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2882 (const_int 8)
2883 (const_int 16)))]
2884 "TARGET_H8300H || TARGET_H8300S"
2885 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
2886 [(set_attr "cc" "set_znv")
2887 (set_attr "length" "6")])
2888
2889 (define_insn "*extzv_16_8"
2890 [(set (match_operand:SI 0 "register_operand" "=r")
2891 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2892 (const_int 16)
2893 (const_int 8)))
2894 (clobber (match_scratch:SI 2 "=&r"))]
2895 "TARGET_H8300H"
2896 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
2897 [(set_attr "length" "8")
2898 (set_attr "cc" "set_znv")])
2899
2900 ;; Extract the exponent of a float.
2901
2902 (define_insn_and_split "*extzv_8_23"
2903 [(set (match_operand:SI 0 "register_operand" "=r")
2904 (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
2905 (const_int 8)
2906 (const_int 23)))]
2907 "(TARGET_H8300H || TARGET_H8300S)"
2908 "#"
2909 "&& reload_completed"
2910 [(parallel [(set (match_dup 0)
2911 (ashift:SI (match_dup 0)
2912 (const_int 1)))
2913 (clobber (scratch:QI))])
2914 (parallel [(set (match_dup 0)
2915 (lshiftrt:SI (match_dup 0)
2916 (const_int 24)))
2917 (clobber (scratch:QI))])]
2918 "")
2919
2920 ;; and:SI
2921
2922 ;; ((SImode) HImode) << 15
2923
2924 (define_insn_and_split "*twoshifts_l16_r1"
2925 [(set (match_operand:SI 0 "register_operand" "=r")
2926 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2927 (const_int 15))
2928 (const_int 2147450880)))]
2929 "(TARGET_H8300H || TARGET_H8300S)"
2930 "#"
2931 "&& reload_completed"
2932 [(parallel [(set (match_dup 0)
2933 (ashift:SI (match_dup 0)
2934 (const_int 16)))
2935 (clobber (scratch:QI))])
2936 (parallel [(set (match_dup 0)
2937 (lshiftrt:SI (match_dup 0)
2938 (const_int 1)))
2939 (clobber (scratch:QI))])]
2940 "")
2941
2942 ;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
2943
2944 (define_insn_and_split "*andsi3_ashift_n_lower"
2945 [(set (match_operand:SI 0 "register_operand" "=r,r")
2946 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
2947 (match_operand:QI 2 "const_int_operand" "S,n"))
2948 (match_operand:SI 3 "const_int_operand" "n,n")))
2949 (clobber (match_scratch:QI 4 "=X,&r"))]
2950 "(TARGET_H8300H || TARGET_H8300S)
2951 && INTVAL (operands[2]) <= 15
2952 && INTVAL (operands[3]) == ((-1 << INTVAL (operands[2])) & 0xffff)"
2953 "#"
2954 "&& reload_completed"
2955 [(parallel [(set (match_dup 5)
2956 (ashift:HI (match_dup 5)
2957 (match_dup 2)))
2958 (clobber (match_dup 4))])
2959 (set (match_dup 0)
2960 (zero_extend:SI (match_dup 5)))]
2961 "operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2962
2963 ;; Accept (A >> 30) & 2 and the like.
2964
2965 (define_insn "*andsi3_lshiftrt_n_sb"
2966 [(set (match_operand:SI 0 "register_operand" "=r")
2967 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
2968 (match_operand:SI 2 "const_int_operand" "n"))
2969 (match_operand:SI 3 "single_one_operand" "n")))]
2970 "(TARGET_H8300H || TARGET_H8300S)
2971 && exact_log2 (INTVAL (operands[3])) < 16
2972 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
2973 "*
2974 {
2975 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
2976 return \"shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0\";
2977 }"
2978 [(set_attr "length" "8")])
2979
2980 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
2981 [(set (match_operand:SI 0 "register_operand" "=r")
2982 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
2983 (const_int 9))
2984 (const_int 4194304)))]
2985 "(TARGET_H8300H || TARGET_H8300S)"
2986 "#"
2987 "&& reload_completed"
2988 [(set (match_dup 0)
2989 (and:SI (lshiftrt:SI (match_dup 0)
2990 (const_int 25))
2991 (const_int 64)))
2992 (parallel [(set (match_dup 0)
2993 (ashift:SI (match_dup 0)
2994 (const_int 16)))
2995 (clobber (scratch:QI))])]
2996 "")
2997
2998 ;; plus:SI
2999
3000 (define_insn "*addsi3_upper"
3001 [(set (match_operand:SI 0 "register_operand" "=r")
3002 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3003 (const_int 65536))
3004 (match_operand:SI 2 "register_operand" "0")))]
3005 "TARGET_H8300H || TARGET_H8300S"
3006 "add.w\\t%f1,%e0"
3007 [(set_attr "length" "2")])
3008
3009 (define_insn "*addsi3_lshiftrt_16_zexthi"
3010 [(set (match_operand:SI 0 "register_operand" "=r")
3011 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3012 (const_int 16))
3013 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
3014 "TARGET_H8300H || TARGET_H8300S"
3015 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0"
3016 [(set_attr "length" "6")])
3017
3018 (define_insn_and_split "*addsi3_and_r_1"
3019 [(set (match_operand:SI 0 "register_operand" "=r")
3020 (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
3021 (const_int 1))
3022 (match_operand:SI 2 "register_operand" "0")))]
3023 "(TARGET_H8300H || TARGET_H8300S)"
3024 "#"
3025 "&& reload_completed"
3026 [(set (cc0)
3027 (zero_extract:SI (match_dup 1)
3028 (const_int 1)
3029 (const_int 0)))
3030 (set (pc)
3031 (if_then_else (eq (cc0)
3032 (const_int 0))
3033 (label_ref (match_dup 3))
3034 (pc)))
3035 (set (match_dup 2)
3036 (plus:SI (match_dup 2)
3037 (const_int 1)))
3038 (match_dup 3)]
3039 "operands[3] = gen_label_rtx ();")
3040
3041 (define_insn_and_split "*addsi3_and_not_r_1"
3042 [(set (match_operand:SI 0 "register_operand" "=r")
3043 (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3044 (const_int 1))
3045 (match_operand:SI 2 "register_operand" "0")))]
3046 "(TARGET_H8300H || TARGET_H8300S)"
3047 "#"
3048 "&& reload_completed"
3049 [(set (cc0)
3050 (zero_extract:SI (match_dup 1)
3051 (const_int 1)
3052 (const_int 0)))
3053 (set (pc)
3054 (if_then_else (ne (cc0)
3055 (const_int 0))
3056 (label_ref (match_dup 3))
3057 (pc)))
3058 (set (match_dup 2)
3059 (plus:SI (match_dup 2)
3060 (const_int 1)))
3061 (match_dup 3)]
3062 "operands[3] = gen_label_rtx ();")
3063
3064 ;; [ix]or:HI
3065
3066 (define_insn "*ixorhi3_zext"
3067 [(set (match_operand:HI 0 "register_operand" "=r")
3068 (match_operator:HI 1 "iorxor_operator"
3069 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
3070 (match_operand:HI 3 "register_operand" "0")]))]
3071 ""
3072 "%c1.b\\t%X2,%s0"
3073 [(set_attr "length" "2")])
3074
3075 ;; [ix]or:SI
3076
3077 (define_insn "*ixorsi3_zext_qi"
3078 [(set (match_operand:SI 0 "register_operand" "=r")
3079 (match_operator:SI 1 "iorxor_operator"
3080 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
3081 (match_operand:SI 3 "register_operand" "0")]))]
3082 ""
3083 "%c1.b\\t%X2,%w0"
3084 [(set_attr "length" "2")])
3085
3086 (define_insn "*ixorsi3_zext_hi"
3087 [(set (match_operand:SI 0 "register_operand" "=r")
3088 (match_operator:SI 1 "iorxor_operator"
3089 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
3090 (match_operand:SI 3 "register_operand" "0")]))]
3091 "TARGET_H8300H || TARGET_H8300S"
3092 "%c1.w\\t%T2,%f0"
3093 [(set_attr "length" "2")])
3094
3095 (define_insn "*ixorsi3_ashift_16"
3096 [(set (match_operand:SI 0 "register_operand" "=r")
3097 (match_operator:SI 1 "iorxor_operator"
3098 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
3099 (const_int 16))
3100 (match_operand:SI 3 "register_operand" "0")]))]
3101 "TARGET_H8300H || TARGET_H8300S"
3102 "%c1.w\\t%f2,%e0"
3103 [(set_attr "length" "2")])
3104
3105 (define_insn "*ixorsi3_lshiftrt_16"
3106 [(set (match_operand:SI 0 "register_operand" "=r")
3107 (match_operator:SI 1 "iorxor_operator"
3108 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3109 (const_int 16))
3110 (match_operand:SI 3 "register_operand" "0")]))]
3111 "TARGET_H8300H || TARGET_H8300S"
3112 "%c1.w\\t%e2,%f0"
3113 [(set_attr "length" "2")])
3114
3115 ;; ior:HI
3116
3117 (define_insn "*iorhi3_ashift_8"
3118 [(set (match_operand:HI 0 "register_operand" "=r")
3119 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
3120 (const_int 8))
3121 (match_operand:HI 2 "register_operand" "0")))]
3122 ""
3123 "or.b\\t%s1,%t0"
3124 [(set_attr "length" "2")])
3125
3126 (define_insn "*iorhi3_lshiftrt_8"
3127 [(set (match_operand:HI 0 "register_operand" "=r")
3128 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3129 (const_int 8))
3130 (match_operand:HI 2 "register_operand" "0")))]
3131 ""
3132 "or.b\\t%t1,%s0"
3133 [(set_attr "length" "2")])
3134
3135 (define_insn "*iorhi3_two_qi"
3136 [(set (match_operand:HI 0 "register_operand" "=r")
3137 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
3138 (ashift:HI (match_operand:HI 2 "register_operand" "r")
3139 (const_int 8))))]
3140 ""
3141 "mov.b\\t%s2,%t0"
3142 [(set_attr "length" "2")])
3143
3144 (define_insn "*iorhi3_two_qi_mem"
3145 [(set (match_operand:HI 0 "register_operand" "=&r")
3146 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
3147 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
3148 (const_int 8))))]
3149 ""
3150 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
3151 [(set_attr "length" "16")])
3152
3153 (define_split
3154 [(set (match_operand:HI 0 "register_operand" "")
3155 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
3156 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
3157 (const_int 8))))]
3158 "(TARGET_H8300H || TARGET_H8300S)
3159 && reload_completed
3160 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
3161 [(set (match_dup 0)
3162 (match_dup 3))]
3163 "operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));")
3164
3165 ;; ior:SI
3166
3167 (define_insn "*iorsi3_two_hi"
3168 [(set (match_operand:SI 0 "register_operand" "=r")
3169 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
3170 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3171 (const_int 16))))]
3172 "TARGET_H8300H || TARGET_H8300S"
3173 "mov.w\\t%f2,%e0"
3174 [(set_attr "length" "2")])
3175
3176 (define_insn_and_split "*iorsi3_two_qi_zext"
3177 [(set (match_operand:SI 0 "register_operand" "=&r")
3178 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
3179
3180 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3181 (const_int 8))
3182 (const_int 65280))))]
3183 "(TARGET_H8300H || TARGET_H8300S)"
3184 "#"
3185 "&& reload_completed"
3186 [(set (match_dup 3)
3187 (ior:HI (zero_extend:HI (match_dup 1))
3188 (ashift:HI (subreg:HI (match_dup 2) 0)
3189 (const_int 8))))
3190 (set (match_dup 0)
3191 (zero_extend:SI (match_dup 3)))]
3192 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3193
3194 (define_insn "*iorsi3_e2f"
3195 [(set (match_operand:SI 0 "register_operand" "=r")
3196 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3197 (const_int -65536))
3198 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3199 (const_int 16))))]
3200 "TARGET_H8300H || TARGET_H8300S"
3201 "mov.w\\t%e2,%f0"
3202 [(set_attr "length" "2")])
3203
3204 (define_insn_and_split "*iorsi3_two_qi_sext"
3205 [(set (match_operand:SI 0 "register_operand" "=r")
3206 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
3207 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
3208 (const_int 8))))]
3209 "(TARGET_H8300H || TARGET_H8300S)"
3210 "#"
3211 "&& reload_completed"
3212 [(set (match_dup 3)
3213 (ior:HI (zero_extend:HI (match_dup 1))
3214 (ashift:HI (match_dup 4)
3215 (const_int 8))))
3216 (set (match_dup 0)
3217 (sign_extend:SI (match_dup 3)))]
3218 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3219 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3220
3221 (define_insn "*iorsi3_w"
3222 [(set (match_operand:SI 0 "register_operand" "=r,&r")
3223 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
3224 (const_int -256))
3225 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
3226 "TARGET_H8300H || TARGET_H8300S"
3227 "mov.b\\t%X2,%w0"
3228 [(set_attr "length" "2,8")])
3229
3230 (define_insn "*iorsi3_ashift_31"
3231 [(set (match_operand:SI 0 "register_operand" "=&r")
3232 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3233 (const_int 31))
3234 (match_operand:SI 2 "register_operand" "0")))]
3235 "TARGET_H8300H || TARGET_H8300S"
3236 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
3237 [(set_attr "length" "6")
3238 (set_attr "cc" "set_znv")])
3239
3240 (define_insn "*iorsi3_and_ashift"
3241 [(set (match_operand:SI 0 "register_operand" "=r")
3242 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3243 (match_operand:SI 2 "const_int_operand" "n"))
3244 (match_operand:SI 3 "single_one_operand" "n"))
3245 (match_operand:SI 4 "register_operand" "0")))]
3246 "(TARGET_H8300H || TARGET_H8300S)
3247 && (INTVAL (operands[3]) & ~0xffff) == 0"
3248 "*
3249 {
3250 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3251 - INTVAL (operands[2]));
3252 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3253 operands[2] = srcpos;
3254 operands[3] = dstpos;
3255 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
3256 }"
3257 [(set_attr "length" "6")])
3258
3259 (define_insn "*iorsi3_and_lshiftrt"
3260 [(set (match_operand:SI 0 "register_operand" "=r")
3261 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3262 (match_operand:SI 2 "const_int_operand" "n"))
3263 (match_operand:SI 3 "single_one_operand" "n"))
3264 (match_operand:SI 4 "register_operand" "0")))]
3265 "(TARGET_H8300H || TARGET_H8300S)
3266 && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
3267 "*
3268 {
3269 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3270 + INTVAL (operands[2]));
3271 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3272 operands[2] = srcpos;
3273 operands[3] = dstpos;
3274 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
3275 }"
3276 [(set_attr "length" "6")])
3277
3278 (define_insn "*iorsi3_zero_extract"
3279 [(set (match_operand:SI 0 "register_operand" "=r")
3280 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3281 (const_int 1)
3282 (match_operand:SI 2 "const_int_operand" "n"))
3283 (match_operand:SI 3 "register_operand" "0")))]
3284 "(TARGET_H8300H || TARGET_H8300S)
3285 && INTVAL (operands[2]) < 16"
3286 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
3287 [(set_attr "length" "6")])
3288
3289 (define_insn "*iorsi3_and_lshiftrt_n_sb"
3290 [(set (match_operand:SI 0 "register_operand" "=r")
3291 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3292 (const_int 30))
3293 (const_int 2))
3294 (match_operand:SI 2 "register_operand" "0")))]
3295 "(TARGET_H8300H || TARGET_H8300S)"
3296 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
3297 [(set_attr "length" "8")])
3298
3299 (define_insn "*iorsi3_and_lshiftrt_9_sb"
3300 [(set (match_operand:SI 0 "register_operand" "=r")
3301 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3302 (const_int 9))
3303 (const_int 4194304))
3304 (match_operand:SI 2 "register_operand" "0")))
3305 (clobber (match_scratch:HI 3 "=&r"))]
3306 "(TARGET_H8300H || TARGET_H8300S)"
3307 "*
3308 {
3309 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3310 return \"shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3311 else
3312 return \"rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3313 }"
3314 [(set_attr "length" "10")])
3315
3316 ;; Used to OR the exponent of a float.
3317
3318 (define_insn "*iorsi3_shift"
3319 [(set (match_operand:SI 0 "register_operand" "=r")
3320 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3321 (const_int 23))
3322 (match_operand:SI 2 "register_operand" "0")))
3323 (clobber (match_scratch:SI 3 "=&r"))]
3324 "TARGET_H8300H || TARGET_H8300S"
3325 "#")
3326
3327 (define_split
3328 [(set (match_operand:SI 0 "register_operand" "")
3329 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3330 (const_int 23))
3331 (match_dup 0)))
3332 (clobber (match_operand:SI 2 "register_operand" ""))]
3333 "(TARGET_H8300H || TARGET_H8300S)
3334 && flow2_completed
3335 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3336 && REGNO (operands[0]) != REGNO (operands[1])"
3337 [(parallel [(set (match_dup 3)
3338 (ashift:HI (match_dup 3)
3339 (const_int 7)))
3340 (clobber (scratch:QI))])
3341 (set (match_dup 0)
3342 (ior:SI (ashift:SI (match_dup 1)
3343 (const_int 16))
3344 (match_dup 0)))]
3345 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3346
3347 (define_split
3348 [(set (match_operand:SI 0 "register_operand" "")
3349 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3350 (const_int 23))
3351 (match_dup 0)))
3352 (clobber (match_operand:SI 2 "register_operand" ""))]
3353 "(TARGET_H8300H || TARGET_H8300S)
3354 && flow2_completed
3355 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3356 && REGNO (operands[0]) != REGNO (operands[1]))"
3357 [(set (match_dup 2)
3358 (match_dup 1))
3359 (parallel [(set (match_dup 3)
3360 (ashift:HI (match_dup 3)
3361 (const_int 7)))
3362 (clobber (scratch:QI))])
3363 (set (match_dup 0)
3364 (ior:SI (ashift:SI (match_dup 2)
3365 (const_int 16))
3366 (match_dup 0)))]
3367 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3368
3369 (define_insn "*iorsi2_and_1_lshiftrt_1"
3370 [(set (match_operand:SI 0 "register_operand" "=r")
3371 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3372 (const_int 1))
3373 (lshiftrt:SI (match_dup 1)
3374 (const_int 1))))]
3375 "TARGET_H8300H || TARGET_H8300S"
3376 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
3377 [(set_attr "length" "6")])
3378
3379 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
3380 [(set (match_operand:SI 0 "register_operand" "=r")
3381 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3382 (const_int 16))
3383 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3384 (const_int 24))))]
3385 "(TARGET_H8300H || TARGET_H8300S)"
3386 "#"
3387 "&& reload_completed"
3388 [(set (match_dup 3)
3389 (ior:HI (ashift:HI (match_dup 4)
3390 (const_int 8))
3391 (match_dup 3)))
3392 (parallel [(set (match_dup 0)
3393 (ashift:SI (match_dup 0)
3394 (const_int 16)))
3395 (clobber (scratch:QI))])]
3396 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3397 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3398
3399 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
3400 [(set (match_operand:SI 0 "register_operand" "=&r")
3401 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
3402 (const_int 16))
3403 (const_int 16711680))
3404 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3405 (const_int 24))))]
3406 "(TARGET_H8300H || TARGET_H8300S)"
3407 "#"
3408 "&& reload_completed"
3409 [(set (match_dup 3)
3410 (ior:HI (zero_extend:HI (match_dup 1))
3411 (ashift:HI (subreg:HI (match_dup 2) 0)
3412 (const_int 8))))
3413 (parallel [(set (match_dup 0)
3414 (ashift:SI (match_dup 0)
3415 (const_int 16)))
3416 (clobber (scratch:QI))])]
3417 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3418
3419 ;; Used to add the exponent of a float.
3420
3421 (define_insn "*addsi3_shift"
3422 [(set (match_operand:SI 0 "register_operand" "=r")
3423 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3424 (const_int 8388608))
3425 (match_operand:SI 2 "register_operand" "0")))
3426 (clobber (match_scratch:SI 3 "=&r"))]
3427 "TARGET_H8300H || TARGET_H8300S"
3428 "#")
3429
3430 (define_split
3431 [(set (match_operand:SI 0 "register_operand" "")
3432 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3433 (const_int 8388608))
3434 (match_dup 0)))
3435 (clobber (match_operand:SI 2 "register_operand" ""))]
3436 "(TARGET_H8300H || TARGET_H8300S)
3437 && flow2_completed
3438 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3439 && REGNO (operands[0]) != REGNO (operands[1])"
3440 [(parallel [(set (match_dup 3)
3441 (ashift:HI (match_dup 3)
3442 (const_int 7)))
3443 (clobber (scratch:QI))])
3444 (set (match_dup 0)
3445 (plus:SI (mult:SI (match_dup 1)
3446 (const_int 65536))
3447 (match_dup 0)))]
3448 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3449
3450 (define_split
3451 [(set (match_operand:SI 0 "register_operand" "")
3452 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3453 (const_int 8388608))
3454 (match_dup 0)))
3455 (clobber (match_operand:SI 2 "register_operand" ""))]
3456 "(TARGET_H8300H || TARGET_H8300S)
3457 && flow2_completed
3458 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3459 && REGNO (operands[0]) != REGNO (operands[1]))"
3460 [(set (match_dup 2)
3461 (match_dup 1))
3462 (parallel [(set (match_dup 3)
3463 (ashift:HI (match_dup 3)
3464 (const_int 7)))
3465 (clobber (scratch:QI))])
3466 (set (match_dup 0)
3467 (plus:SI (mult:SI (match_dup 2)
3468 (const_int 65536))
3469 (match_dup 0)))]
3470 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3471
3472 ;; ashift:SI
3473
3474 (define_insn_and_split "*ashiftsi_sextqi_7"
3475 [(set (match_operand:SI 0 "register_operand" "=r")
3476 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
3477 (const_int 7)))]
3478 "(TARGET_H8300H || TARGET_H8300S)"
3479 "#"
3480 "&& reload_completed"
3481 [(parallel [(set (match_dup 2)
3482 (ashift:HI (match_dup 2)
3483 (const_int 8)))
3484 (clobber (scratch:QI))])
3485 (set (match_dup 0)
3486 (sign_extend:SI (match_dup 2)))
3487 (parallel [(set (match_dup 0)
3488 (ashiftrt:SI (match_dup 0)
3489 (const_int 1)))
3490 (clobber (scratch:QI))])]
3491 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3492
3493 ;; Storing a part of HImode to QImode.
3494
3495 (define_insn ""
3496 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3497 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3498 (const_int 8)) 1))]
3499 ""
3500 "mov.b\\t%t1,%R0"
3501 [(set_attr "cc" "set_znv")
3502 (set_attr "length" "8")])
3503
3504 ;; Storing a part of SImode to QImode.
3505
3506 (define_insn ""
3507 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3508 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3509 (const_int 8)) 3))]
3510 ""
3511 "mov.b\\t%x1,%R0"
3512 [(set_attr "cc" "set_znv")
3513 (set_attr "length" "8")])
3514
3515 (define_insn ""
3516 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3517 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3518 (const_int 16)) 3))
3519 (clobber (match_scratch:SI 2 "=&r"))]
3520 "TARGET_H8300H || TARGET_H8300S"
3521 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
3522 [(set_attr "cc" "set_znv")
3523 (set_attr "length" "10")])
3524
3525 (define_insn ""
3526 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3527 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3528 (const_int 24)) 3))
3529 (clobber (match_scratch:SI 2 "=&r"))]
3530 "TARGET_H8300H || TARGET_H8300S"
3531 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
3532 [(set_attr "cc" "set_znv")
3533 (set_attr "length" "10")])
3534
3535 (define_insn_and_split ""
3536 [(set (pc)
3537 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3538 (const_int 1)
3539 (const_int 7))
3540 (const_int 0))
3541 (label_ref (match_operand 1 "" ""))
3542 (pc)))]
3543 ""
3544 "#"
3545 ""
3546 [(set (cc0)
3547 (match_dup 0))
3548 (set (pc)
3549 (if_then_else (ge (cc0)
3550 (const_int 0))
3551 (label_ref (match_dup 1))
3552 (pc)))]
3553 "")
3554
3555 (define_insn_and_split ""
3556 [(set (pc)
3557 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3558 (const_int 1)
3559 (const_int 7))
3560 (const_int 0))
3561 (label_ref (match_operand 1 "" ""))
3562 (pc)))]
3563 ""
3564 "#"
3565 ""
3566 [(set (cc0)
3567 (match_dup 0))
3568 (set (pc)
3569 (if_then_else (lt (cc0)
3570 (const_int 0))
3571 (label_ref (match_dup 1))
3572 (pc)))]
3573 "")
3574 \f
3575 ;; -----------------------------------------------------------------
3576 ;; PEEPHOLE PATTERNS
3577 ;; -----------------------------------------------------------------
3578
3579 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3580
3581 (define_peephole2
3582 [(parallel
3583 [(set (match_operand:HI 0 "register_operand" "")
3584 (lshiftrt:HI (match_dup 0)
3585 (match_operand:HI 1 "const_int_operand" "")))
3586 (clobber (match_operand:HI 2 "" ""))])
3587 (set (match_dup 0)
3588 (and:HI (match_dup 0)
3589 (match_operand:HI 3 "const_int_operand" "")))]
3590 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3591 [(set (match_dup 0)
3592 (and:HI (match_dup 0)
3593 (const_int 255)))
3594 (parallel
3595 [(set (match_dup 0)
3596 (lshiftrt:HI (match_dup 0)
3597 (match_dup 1)))
3598 (clobber (match_dup 2))])]
3599 "")
3600
3601 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3602
3603 (define_peephole2
3604 [(parallel
3605 [(set (match_operand:HI 0 "register_operand" "")
3606 (ashift:HI (match_dup 0)
3607 (match_operand:HI 1 "const_int_operand" "")))
3608 (clobber (match_operand:HI 2 "" ""))])
3609 (set (match_dup 0)
3610 (and:HI (match_dup 0)
3611 (match_operand:HI 3 "const_int_operand" "")))]
3612 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3613 [(set (match_dup 0)
3614 (and:HI (match_dup 0)
3615 (const_int 255)))
3616 (parallel
3617 [(set (match_dup 0)
3618 (ashift:HI (match_dup 0)
3619 (match_dup 1)))
3620 (clobber (match_dup 2))])]
3621 "")
3622
3623 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3624
3625 (define_peephole2
3626 [(parallel
3627 [(set (match_operand:SI 0 "register_operand" "")
3628 (lshiftrt:SI (match_dup 0)
3629 (match_operand:SI 1 "const_int_operand" "")))
3630 (clobber (match_operand:SI 2 "" ""))])
3631 (set (match_dup 0)
3632 (and:SI (match_dup 0)
3633 (match_operand:SI 3 "const_int_operand" "")))]
3634 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3635 [(set (match_dup 0)
3636 (and:SI (match_dup 0)
3637 (const_int 255)))
3638 (parallel
3639 [(set (match_dup 0)
3640 (lshiftrt:SI (match_dup 0)
3641 (match_dup 1)))
3642 (clobber (match_dup 2))])]
3643 "")
3644
3645 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3646
3647 (define_peephole2
3648 [(parallel
3649 [(set (match_operand:SI 0 "register_operand" "")
3650 (ashift:SI (match_dup 0)
3651 (match_operand:SI 1 "const_int_operand" "")))
3652 (clobber (match_operand:SI 2 "" ""))])
3653 (set (match_dup 0)
3654 (and:SI (match_dup 0)
3655 (match_operand:SI 3 "const_int_operand" "")))]
3656 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3657 [(set (match_dup 0)
3658 (and:SI (match_dup 0)
3659 (const_int 255)))
3660 (parallel
3661 [(set (match_dup 0)
3662 (ashift:SI (match_dup 0)
3663 (match_dup 1)))
3664 (clobber (match_dup 2))])]
3665 "")
3666
3667 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
3668
3669 (define_peephole2
3670 [(parallel
3671 [(set (match_operand:SI 0 "register_operand" "")
3672 (lshiftrt:SI (match_dup 0)
3673 (match_operand:SI 1 "const_int_operand" "")))
3674 (clobber (match_operand:SI 2 "" ""))])
3675 (set (match_dup 0)
3676 (and:SI (match_dup 0)
3677 (match_operand:SI 3 "const_int_operand" "")))]
3678 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
3679 [(set (match_dup 0)
3680 (and:SI (match_dup 0)
3681 (const_int 65535)))
3682 (parallel
3683 [(set (match_dup 0)
3684 (lshiftrt:SI (match_dup 0)
3685 (match_dup 1)))
3686 (clobber (match_dup 2))])]
3687 "")
3688
3689 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
3690
3691 (define_peephole2
3692 [(parallel
3693 [(set (match_operand:SI 0 "register_operand" "")
3694 (ashift:SI (match_dup 0)
3695 (match_operand:SI 1 "const_int_operand" "")))
3696 (clobber (match_operand:SI 2 "" ""))])
3697 (set (match_dup 0)
3698 (and:SI (match_dup 0)
3699 (match_operand:SI 3 "const_int_operand" "")))]
3700 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
3701 [(set (match_dup 0)
3702 (and:SI (match_dup 0)
3703 (const_int 65535)))
3704 (parallel
3705 [(set (match_dup 0)
3706 (ashift:SI (match_dup 0)
3707 (match_dup 1)))
3708 (clobber (match_dup 2))])]
3709 "")
3710
3711 ;; Convert a QImode push into an SImode push so that the
3712 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3713
3714 (define_peephole2
3715 [(parallel [(set (reg:SI SP_REG)
3716 (plus:SI (reg:SI SP_REG) (const_int -4)))
3717 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
3718 (match_operand:QI 0 "register_operand" ""))])]
3719 "TARGET_H8300S && !TARGET_NORMAL_MODE"
3720 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3721 (match_dup 0))]
3722 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3723
3724 (define_peephole2
3725 [(parallel [(set (reg:HI SP_REG)
3726 (plus:HI (reg:HI SP_REG) (const_int -4)))
3727 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
3728 (match_operand:QI 0 "register_operand" ""))])]
3729 "TARGET_H8300S && TARGET_NORMAL_MODE"
3730 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3731 (match_dup 0))]
3732 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3733
3734 ;; Convert a HImode push into an SImode push so that the
3735 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3736
3737 (define_peephole2
3738 [(parallel [(set (reg:SI SP_REG)
3739 (plus:SI (reg:SI SP_REG) (const_int -4)))
3740 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
3741 (match_operand:HI 0 "register_operand" ""))])]
3742 "TARGET_H8300S && !TARGET_NORMAL_MODE"
3743 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3744 (match_dup 0))]
3745 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3746
3747 (define_peephole2
3748 [(parallel [(set (reg:HI SP_REG)
3749 (plus:HI (reg:HI SP_REG) (const_int -4)))
3750 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
3751 (match_operand:HI 0 "register_operand" ""))])]
3752 "TARGET_H8300S && TARGET_NORMAL_MODE"
3753 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3754 (match_dup 0))]
3755 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3756
3757 ;; Cram four pushes into stm.l.
3758
3759 (define_peephole2
3760 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3761 (match_operand:SI 0 "register_operand" ""))
3762 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3763 (match_operand:SI 1 "register_operand" ""))
3764 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3765 (match_operand:SI 2 "register_operand" ""))
3766 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3767 (match_operand:SI 3 "register_operand" ""))]
3768 "TARGET_H8300S && !TARGET_NORMAL_MODE
3769 && REGNO (operands[0]) == 0
3770 && REGNO (operands[1]) == 1
3771 && REGNO (operands[2]) == 2
3772 && REGNO (operands[3]) == 3"
3773 [(parallel [(set (reg:SI SP_REG)
3774 (plus:SI (reg:SI SP_REG)
3775 (const_int -16)))
3776 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3777 (match_dup 0))
3778 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3779 (match_dup 1))
3780 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3781 (match_dup 2))
3782 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
3783 (match_dup 3))])]
3784 "")
3785
3786 (define_peephole2
3787 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3788 (match_operand:SI 0 "register_operand" ""))
3789 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3790 (match_operand:SI 1 "register_operand" ""))
3791 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3792 (match_operand:SI 2 "register_operand" ""))
3793 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3794 (match_operand:SI 3 "register_operand" ""))]
3795 "TARGET_H8300S && TARGET_NORMAL_MODE
3796 && REGNO (operands[0]) == 0
3797 && REGNO (operands[1]) == 1
3798 && REGNO (operands[2]) == 2
3799 && REGNO (operands[3]) == 3"
3800 [(parallel [(set (reg:HI SP_REG)
3801 (plus:HI (reg:HI SP_REG)
3802 (const_int -16)))
3803 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
3804 (match_dup 0))
3805 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
3806 (match_dup 1))
3807 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
3808 (match_dup 2))
3809 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
3810 (match_dup 3))])]
3811 "")
3812
3813 ;; Cram three pushes into stm.l.
3814
3815 (define_peephole2
3816 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3817 (match_operand:SI 0 "register_operand" ""))
3818 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3819 (match_operand:SI 1 "register_operand" ""))
3820 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3821 (match_operand:SI 2 "register_operand" ""))]
3822 "TARGET_H8300S && !TARGET_NORMAL_MODE
3823 && ((REGNO (operands[0]) == 0
3824 && REGNO (operands[1]) == 1
3825 && REGNO (operands[2]) == 2)
3826 || (REGNO (operands[0]) == 4
3827 && REGNO (operands[1]) == 5
3828 && REGNO (operands[2]) == 6))"
3829 [(parallel [(set (reg:SI SP_REG)
3830 (plus:SI (reg:SI SP_REG)
3831 (const_int -12)))
3832 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3833 (match_dup 0))
3834 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3835 (match_dup 1))
3836 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3837 (match_dup 2))])]
3838 "")
3839
3840 (define_peephole2
3841 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3842 (match_operand:SI 0 "register_operand" ""))
3843 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3844 (match_operand:SI 1 "register_operand" ""))
3845 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3846 (match_operand:SI 2 "register_operand" ""))]
3847 "TARGET_H8300S && TARGET_NORMAL_MODE
3848 && ((REGNO (operands[0]) == 0
3849 && REGNO (operands[1]) == 1
3850 && REGNO (operands[2]) == 2)
3851 || (REGNO (operands[0]) == 4
3852 && REGNO (operands[1]) == 5
3853 && REGNO (operands[2]) == 6))"
3854 [(parallel [(set (reg:HI SP_REG)
3855 (plus:HI (reg:HI SP_REG)
3856 (const_int -12)))
3857 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
3858 (match_dup 0))
3859 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
3860 (match_dup 1))
3861 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
3862 (match_dup 2))])]
3863 "")
3864
3865 ;; Cram two pushes into stm.l.
3866
3867 (define_peephole2
3868 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3869 (match_operand:SI 0 "register_operand" ""))
3870 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3871 (match_operand:SI 1 "register_operand" ""))]
3872 "TARGET_H8300S && !TARGET_NORMAL_MODE
3873 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
3874 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
3875 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
3876 [(parallel [(set (reg:SI SP_REG)
3877 (plus:SI (reg:SI SP_REG)
3878 (const_int -8)))
3879 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3880 (match_dup 0))
3881 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3882 (match_dup 1))])]
3883 "")
3884
3885 (define_peephole2
3886 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3887 (match_operand:SI 0 "register_operand" ""))
3888 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3889 (match_operand:SI 1 "register_operand" ""))]
3890 "TARGET_H8300S && TARGET_NORMAL_MODE
3891 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
3892 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
3893 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
3894 [(parallel [(set (reg:HI SP_REG)
3895 (plus:HI (reg:HI SP_REG)
3896 (const_int -8)))
3897 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
3898 (match_dup 0))
3899 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
3900 (match_dup 1))])]
3901 "")
3902
3903 ;; Turn
3904 ;;
3905 ;; mov.w #2,r0
3906 ;; add.w r7,r0 (6 bytes)
3907 ;;
3908 ;; into
3909 ;;
3910 ;; mov.w r7,r0
3911 ;; adds #2,r0 (4 bytes)
3912
3913 (define_peephole2
3914 [(set (match_operand:HI 0 "register_operand" "")
3915 (match_operand:HI 1 "const_int_operand" ""))
3916 (set (match_dup 0)
3917 (plus:HI (match_dup 0)
3918 (match_operand:HI 2 "register_operand" "")))]
3919 "REG_P (operands[0]) && REG_P (operands[2])
3920 && REGNO (operands[0]) != REGNO (operands[2])
3921 && (CONST_OK_FOR_J (INTVAL (operands[1]))
3922 || CONST_OK_FOR_L (INTVAL (operands[1]))
3923 || CONST_OK_FOR_N (INTVAL (operands[1])))"
3924 [(set (match_dup 0)
3925 (match_dup 2))
3926 (set (match_dup 0)
3927 (plus:HI (match_dup 0)
3928 (match_dup 1)))]
3929 "")
3930
3931 ;; Turn
3932 ;;
3933 ;; sub.l er0,er0
3934 ;; add.b #4,r0l
3935 ;; add.l er7,er0 (6 bytes)
3936 ;;
3937 ;; into
3938 ;;
3939 ;; mov.l er7,er0
3940 ;; adds #4,er0 (4 bytes)
3941
3942 (define_peephole2
3943 [(set (match_operand:SI 0 "register_operand" "")
3944 (match_operand:SI 1 "const_int_operand" ""))
3945 (set (match_dup 0)
3946 (plus:SI (match_dup 0)
3947 (match_operand:SI 2 "register_operand" "")))]
3948 "(TARGET_H8300H || TARGET_H8300S)
3949 && REG_P (operands[0]) && REG_P (operands[2])
3950 && REGNO (operands[0]) != REGNO (operands[2])
3951 && (CONST_OK_FOR_L (INTVAL (operands[1]))
3952 || CONST_OK_FOR_N (INTVAL (operands[1])))"
3953 [(set (match_dup 0)
3954 (match_dup 2))
3955 (set (match_dup 0)
3956 (plus:SI (match_dup 0)
3957 (match_dup 1)))]
3958 "")
3959
3960 ;; Turn
3961 ;;
3962 ;; mov.l er7,er0
3963 ;; add.l #10,er0 (takes 8 bytes)
3964 ;;
3965 ;; into
3966 ;;
3967 ;; sub.l er0,er0
3968 ;; add.b #10,r0l
3969 ;; add.l er7,er0 (takes 6 bytes)
3970
3971 (define_peephole2
3972 [(set (match_operand:SI 0 "register_operand" "")
3973 (match_operand:SI 1 "register_operand" ""))
3974 (set (match_dup 0)
3975 (plus:SI (match_dup 0)
3976 (match_operand:SI 2 "const_int_operand" "")))]
3977 "(TARGET_H8300H || TARGET_H8300S)
3978 && REG_P (operands[0]) && REG_P (operands[1])
3979 && REGNO (operands[0]) != REGNO (operands[1])
3980 && !CONST_OK_FOR_L (INTVAL (operands[2]))
3981 && !CONST_OK_FOR_N (INTVAL (operands[2]))
3982 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
3983 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
3984 || INTVAL (operands[2]) == 0xffff
3985 || INTVAL (operands[2]) == 0xfffe)"
3986 [(set (match_dup 0)
3987 (match_dup 2))
3988 (set (match_dup 0)
3989 (plus:SI (match_dup 0)
3990 (match_dup 1)))]
3991 "")
3992
3993 ;; Turn
3994 ;;
3995 ;; subs #1,er4
3996 ;; mov.w r4,r4
3997 ;; bne .L2028
3998 ;;
3999 ;; into
4000 ;;
4001 ;; dec.w #1,r4
4002 ;; bne .L2028
4003
4004 (define_peephole2
4005 [(set (match_operand:HI 0 "register_operand" "")
4006 (plus:HI (match_dup 0)
4007 (match_operand 1 "incdec_operand" "")))
4008 (set (cc0)
4009 (match_dup 0))
4010 (set (pc)
4011 (if_then_else (match_operator 3 "eqne_operator"
4012 [(cc0) (const_int 0)])
4013 (label_ref (match_operand 2 "" ""))
4014 (pc)))]
4015 "TARGET_H8300H || TARGET_H8300S"
4016 [(set (match_operand:HI 0 "register_operand" "")
4017 (unspec:HI [(match_dup 0)
4018 (match_dup 1)]
4019 UNSPEC_INCDEC))
4020 (set (cc0)
4021 (match_dup 0))
4022 (set (pc)
4023 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4024 (label_ref (match_dup 2))
4025 (pc)))]
4026 "")
4027
4028 ;; The SImode version of the previous pattern.
4029
4030 (define_peephole2
4031 [(set (match_operand:SI 0 "register_operand" "")
4032 (plus:SI (match_dup 0)
4033 (match_operand 1 "incdec_operand" "")))
4034 (set (cc0)
4035 (match_dup 0))
4036 (set (pc)
4037 (if_then_else (match_operator 3 "eqne_operator"
4038 [(cc0) (const_int 0)])
4039 (label_ref (match_operand 2 "" ""))
4040 (pc)))]
4041 "TARGET_H8300H || TARGET_H8300S"
4042 [(set (match_operand:SI 0 "register_operand" "")
4043 (unspec:SI [(match_dup 0)
4044 (match_dup 1)]
4045 UNSPEC_INCDEC))
4046 (set (cc0)
4047 (match_dup 0))
4048 (set (pc)
4049 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4050 (label_ref (match_dup 2))
4051 (pc)))]
4052 "")
4053
4054 (define_peephole2
4055 [(parallel [(set (cc0)
4056 (zero_extract:SI (match_operand:QI 0 "register_operand" "")
4057 (const_int 1)
4058 (const_int 7)))
4059 (clobber (scratch:QI))])
4060 (set (pc)
4061 (if_then_else (match_operator 1 "eqne_operator"
4062 [(cc0) (const_int 0)])
4063 (label_ref (match_operand 2 "" ""))
4064 (pc)))]
4065 "(TARGET_H8300H || TARGET_H8300S)"
4066 [(set (cc0)
4067 (match_dup 0))
4068 (set (pc)
4069 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4070 (label_ref (match_dup 2))
4071 (pc)))]
4072 "operands[3] = ((GET_CODE (operands[1]) == EQ)
4073 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
4074 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));")
4075
4076 ;; The next three peephole2's will try to transform
4077 ;;
4078 ;; mov.b A,r0l (or mov.l A,er0)
4079 ;; and.l #CST,er0
4080 ;;
4081 ;; into
4082 ;;
4083 ;; sub.l er0
4084 ;; mov.b A,r0l
4085 ;; and.b #CST,r0l (if CST is not 255)
4086
4087 (define_peephole2
4088 [(set (match_operand:QI 0 "register_operand" "")
4089 (match_operand:QI 1 "general_operand" ""))
4090 (set (match_operand:SI 2 "register_operand" "")
4091 (and:SI (match_dup 2)
4092 (const_int 255)))]
4093 "(TARGET_H8300H || TARGET_H8300S)
4094 && !reg_overlap_mentioned_p (operands[2], operands[1])
4095 && REGNO (operands[0]) == REGNO (operands[2])"
4096 [(set (match_dup 2)
4097 (const_int 0))
4098 (set (strict_low_part (match_dup 0))
4099 (match_dup 1))]
4100 "")
4101
4102 (define_peephole2
4103 [(set (match_operand:SI 0 "register_operand" "")
4104 (match_operand:SI 1 "general_operand" ""))
4105 (set (match_dup 0)
4106 (and:SI (match_dup 0)
4107 (const_int 255)))]
4108 "(TARGET_H8300H || TARGET_H8300S)
4109 && !reg_overlap_mentioned_p (operands[0], operands[1])
4110 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
4111 [(set (match_dup 0)
4112 (const_int 0))
4113 (set (strict_low_part (match_dup 2))
4114 (match_dup 3))]
4115 "operands[2] = gen_lowpart (QImode, operands[0]);
4116 operands[3] = gen_lowpart (QImode, operands[1]);")
4117
4118 (define_peephole2
4119 [(set (match_operand 0 "register_operand" "")
4120 (match_operand 1 "general_operand" ""))
4121 (set (match_operand:SI 2 "register_operand" "")
4122 (and:SI (match_dup 2)
4123 (match_operand:SI 3 "const_int_qi_operand" "")))]
4124 "(TARGET_H8300H || TARGET_H8300S)
4125 && (GET_MODE (operands[0]) == QImode
4126 || GET_MODE (operands[0]) == HImode
4127 || GET_MODE (operands[0]) == SImode)
4128 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4129 && REGNO (operands[0]) == REGNO (operands[2])
4130 && !reg_overlap_mentioned_p (operands[2], operands[1])
4131 && !(GET_MODE (operands[1]) != QImode
4132 && GET_CODE (operands[1]) == MEM
4133 && MEM_VOLATILE_P (operands[1]))"
4134 [(set (match_dup 2)
4135 (const_int 0))
4136 (set (strict_low_part (match_dup 4))
4137 (match_dup 5))
4138 (set (match_dup 2)
4139 (and:SI (match_dup 2)
4140 (match_dup 6)))]
4141 "operands[4] = gen_lowpart (QImode, operands[0]);
4142 operands[5] = gen_lowpart (QImode, operands[1]);
4143 operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));")
4144
4145 (define_peephole2
4146 [(set (match_operand:SI 0 "register_operand" "")
4147 (match_operand:SI 1 "register_operand" ""))
4148 (set (match_dup 0)
4149 (and:SI (match_dup 0)
4150 (const_int 65280)))]
4151 "(TARGET_H8300H || TARGET_H8300S)
4152 && !reg_overlap_mentioned_p (operands[0], operands[1])"
4153 [(set (match_dup 0)
4154 (const_int 0))
4155 (set (zero_extract:SI (match_dup 0)
4156 (const_int 8)
4157 (const_int 8))
4158 (lshiftrt:SI (match_dup 1)
4159 (const_int 8)))]
4160 "")
4161
4162 ;; If a load of mem:SI is followed by an AND that turns off the upper
4163 ;; half, then we can load mem:HI instead.
4164
4165 (define_peephole2
4166 [(set (match_operand:SI 0 "register_operand" "")
4167 (match_operand:SI 1 "memory_operand" ""))
4168 (set (match_dup 0)
4169 (and:SI (match_dup 0)
4170 (match_operand:SI 2 "const_int_operand" "")))]
4171 "(TARGET_H8300H || TARGET_H8300S)
4172 && !MEM_VOLATILE_P (operands[1])
4173 && (INTVAL (operands[2]) & ~0xffff) == 0
4174 && INTVAL (operands[2]) != 255"
4175 [(set (match_dup 3)
4176 (match_dup 4))
4177 (set (match_dup 0)
4178 (and:SI (match_dup 0)
4179 (match_dup 2)))]
4180 "operands[3] = gen_lowpart (HImode, operands[0]);
4181 operands[4] = gen_lowpart (HImode, operands[1]);")
4182
4183 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
4184 ;; the equivalent with shorter sequences. Here is the summary. Cases
4185 ;; are grouped for each define_peephole2.
4186 ;;
4187 ;; reg const_int use insn
4188 ;; --------------------------------------------------------
4189 ;; dead -2 eq/ne inc.l
4190 ;; dead -1 eq/ne inc.l
4191 ;; dead 1 eq/ne dec.l
4192 ;; dead 2 eq/ne dec.l
4193 ;;
4194 ;; dead 1 geu/ltu shar.l
4195 ;; dead 3 (H8S) geu/ltu shar.l
4196 ;;
4197 ;; ---- 255 geu/ltu mov.b
4198
4199 ;; Transform
4200 ;;
4201 ;; cmp.w #1,r0
4202 ;; bne .L1
4203 ;;
4204 ;; into
4205 ;;
4206 ;; dec.w #1,r0
4207 ;; bne .L1
4208
4209 (define_peephole2
4210 [(set (cc0)
4211 (compare (match_operand:HI 0 "register_operand" "")
4212 (match_operand:HI 1 "incdec_operand" "")))
4213 (set (pc)
4214 (if_then_else (match_operator 3 "eqne_operator"
4215 [(cc0) (const_int 0)])
4216 (label_ref (match_operand 2 "" ""))
4217 (pc)))]
4218 "(TARGET_H8300H || TARGET_H8300S)
4219 && peep2_reg_dead_p (1, operands[0])"
4220 [(set (match_dup 0)
4221 (unspec:HI [(match_dup 0)
4222 (match_dup 4)]
4223 UNSPEC_INCDEC))
4224 (set (cc0)
4225 (match_dup 0))
4226 (set (pc)
4227 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4228 (label_ref (match_dup 2))
4229 (pc)))]
4230 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4231
4232 ;; Transform
4233 ;;
4234 ;; cmp.w #1,r0
4235 ;; bhi .L1
4236 ;;
4237 ;; into
4238 ;;
4239 ;; shar.w r0
4240 ;; bne .L1
4241
4242 (define_peephole2
4243 [(set (cc0)
4244 (compare (match_operand:HI 0 "register_operand" "")
4245 (match_operand:HI 1 "const_int_operand" "")))
4246 (set (pc)
4247 (if_then_else (match_operator 2 "gtle_operator"
4248 [(cc0) (const_int 0)])
4249 (label_ref (match_operand 3 "" ""))
4250 (pc)))]
4251 "(TARGET_H8300H || TARGET_H8300S)
4252 && peep2_reg_dead_p (1, operands[0])
4253 && (INTVAL (operands[1]) == 1
4254 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4255 [(parallel [(set (match_dup 0)
4256 (ashiftrt:HI (match_dup 0)
4257 (match_dup 5)))
4258 (clobber (scratch:QI))])
4259 (set (cc0)
4260 (match_dup 0))
4261 (set (pc)
4262 (if_then_else (match_dup 4)
4263 (label_ref (match_dup 3))
4264 (pc)))]
4265 "switch (GET_CODE (operands[2]))
4266 {
4267 case GTU:
4268 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4269 break;
4270 case LEU:
4271 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4272 break;
4273 default:
4274 operands[4] = operands[2];
4275 break;
4276 }
4277 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4278
4279 ;; Transform
4280 ;;
4281 ;; cmp.w #255,r0
4282 ;; bhi .L1
4283 ;;
4284 ;; into
4285 ;;
4286 ;; mov.b r0h,r0h
4287 ;; bne .L1
4288
4289 (define_peephole2
4290 [(set (cc0)
4291 (compare (match_operand:HI 0 "register_operand" "")
4292 (const_int 255)))
4293 (set (pc)
4294 (if_then_else (match_operator 1 "gtle_operator"
4295 [(cc0) (const_int 0)])
4296 (label_ref (match_operand 2 "" ""))
4297 (pc)))]
4298 "TARGET_H8300H || TARGET_H8300S"
4299 [(set (cc0)
4300 (and:HI (match_dup 0)
4301 (const_int -256)))
4302 (set (pc)
4303 (if_then_else (match_dup 3)
4304 (label_ref (match_dup 2))
4305 (pc)))]
4306 "switch (GET_CODE (operands[1]))
4307 {
4308 case GTU:
4309 operands[3] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4310 break;
4311 case LEU:
4312 operands[3] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4313 break;
4314 default:
4315 operands[3] = operands[1];
4316 break;
4317 }")
4318
4319 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
4320 ;; the equivalent with shorter sequences. Here is the summary. Cases
4321 ;; are grouped for each define_peephole2.
4322 ;;
4323 ;; reg const_int use insn
4324 ;; --------------------------------------------------------
4325 ;; live -2 eq/ne copy and inc.l
4326 ;; live -1 eq/ne copy and inc.l
4327 ;; live 1 eq/ne copy and dec.l
4328 ;; live 2 eq/ne copy and dec.l
4329 ;;
4330 ;; dead -2 eq/ne inc.l
4331 ;; dead -1 eq/ne inc.l
4332 ;; dead 1 eq/ne dec.l
4333 ;; dead 2 eq/ne dec.l
4334 ;;
4335 ;; dead -131072 eq/ne inc.w and test
4336 ;; dead -65536 eq/ne inc.w and test
4337 ;; dead 65536 eq/ne dec.w and test
4338 ;; dead 131072 eq/ne dec.w and test
4339 ;;
4340 ;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
4341 ;; dead 0x0000??00 eq/ne xor.b and test
4342 ;; dead 0x0000ffff eq/ne not.w and test
4343 ;;
4344 ;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
4345 ;; dead 0xffff??ff eq/ne xor.b and not.l
4346 ;; dead 0x40000000 (H8S) eq/ne rotl.l and dec.l
4347 ;; dead 0x80000000 eq/ne rotl.l and dec.l
4348 ;;
4349 ;; live 1 geu/ltu copy and shar.l
4350 ;; live 3 (H8S) geu/ltu copy and shar.l
4351 ;;
4352 ;; dead 1 geu/ltu shar.l
4353 ;; dead 3 (H8S) geu/ltu shar.l
4354 ;;
4355 ;; dead 3 (H8/300H) geu/ltu and.b and test
4356 ;; dead 7 geu/ltu and.b and test
4357 ;; dead 15 geu/ltu and.b and test
4358 ;; dead 31 geu/ltu and.b and test
4359 ;; dead 63 geu/ltu and.b and test
4360 ;; dead 127 geu/ltu and.b and test
4361 ;; dead 255 geu/ltu and.b and test
4362 ;;
4363 ;; ---- 65535 geu/ltu mov.w
4364
4365 ;; For a small constant, it is cheaper to actually do the subtraction
4366 ;; and then test the register.
4367
4368 (define_peephole2
4369 [(set (cc0)
4370 (compare (match_operand:SI 0 "register_operand" "")
4371 (match_operand:SI 1 "incdec_operand" "")))
4372 (set (pc)
4373 (if_then_else (match_operator 3 "eqne_operator"
4374 [(cc0) (const_int 0)])
4375 (label_ref (match_operand 2 "" ""))
4376 (pc)))]
4377 "(TARGET_H8300H || TARGET_H8300S)
4378 && peep2_reg_dead_p (1, operands[0])"
4379 [(set (match_dup 0)
4380 (unspec:SI [(match_dup 0)
4381 (match_dup 4)]
4382 UNSPEC_INCDEC))
4383 (set (cc0)
4384 (match_dup 0))
4385 (set (pc)
4386 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4387 (label_ref (match_dup 2))
4388 (pc)))]
4389 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4390
4391 (define_peephole2
4392 [(set (cc0)
4393 (compare (match_operand:SI 0 "register_operand" "")
4394 (match_operand:SI 1 "const_int_operand" "")))
4395 (set (pc)
4396 (if_then_else (match_operator 3 "eqne_operator"
4397 [(cc0) (const_int 0)])
4398 (label_ref (match_operand 2 "" ""))
4399 (pc)))]
4400 "(TARGET_H8300H || TARGET_H8300S)
4401 && peep2_reg_dead_p (1, operands[0])
4402 && (INTVAL (operands[1]) == -131072
4403 || INTVAL (operands[1]) == -65536
4404 || INTVAL (operands[1]) == 65536
4405 || INTVAL (operands[1]) == 131072)"
4406 [(set (match_dup 0)
4407 (plus:SI (match_dup 0)
4408 (match_dup 4)))
4409 (set (cc0)
4410 (match_dup 0))
4411 (set (pc)
4412 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4413 (label_ref (match_dup 2))
4414 (pc)))]
4415 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4416
4417 ;; For certain (in)equality comparisons against a constant, we can
4418 ;; XOR the register with the constant, and test the register against
4419 ;; 0.
4420
4421 (define_peephole2
4422 [(set (cc0)
4423 (compare (match_operand:SI 0 "register_operand" "")
4424 (match_operand:SI 1 "const_int_operand" "")))
4425 (set (pc)
4426 (if_then_else (match_operator 3 "eqne_operator"
4427 [(cc0) (const_int 0)])
4428 (label_ref (match_operand 2 "" ""))
4429 (pc)))]
4430 "(TARGET_H8300H || TARGET_H8300S)
4431 && peep2_reg_dead_p (1, operands[0])
4432 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
4433 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
4434 || INTVAL (operands[1]) == 0x0000ffff)
4435 && INTVAL (operands[1]) != 1
4436 && INTVAL (operands[1]) != 2"
4437 [(set (match_dup 0)
4438 (xor:SI (match_dup 0)
4439 (match_dup 1)))
4440 (set (cc0)
4441 (match_dup 0))
4442 (set (pc)
4443 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4444 (label_ref (match_dup 2))
4445 (pc)))]
4446 "")
4447
4448 (define_peephole2
4449 [(set (cc0)
4450 (compare (match_operand:SI 0 "register_operand" "")
4451 (match_operand:SI 1 "const_int_operand" "")))
4452 (set (pc)
4453 (if_then_else (match_operator 3 "eqne_operator"
4454 [(cc0) (const_int 0)])
4455 (label_ref (match_operand 2 "" ""))
4456 (pc)))]
4457 "(TARGET_H8300H || TARGET_H8300S)
4458 && peep2_reg_dead_p (1, operands[0])
4459 && ((INTVAL (operands[1]) | 0x00ff) == -1
4460 || (INTVAL (operands[1]) | 0xff00) == -1)
4461 && INTVAL (operands[1]) != -1
4462 && INTVAL (operands[1]) != -2"
4463 [(set (match_dup 0)
4464 (xor:SI (match_dup 0)
4465 (match_dup 4)))
4466 (set (match_dup 0)
4467 (not:SI (match_dup 0)))
4468 (set (cc0)
4469 (match_dup 0))
4470 (set (pc)
4471 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4472 (label_ref (match_dup 2))
4473 (pc)))]
4474 "operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);")
4475
4476 (define_peephole2
4477 [(set (cc0)
4478 (compare (match_operand:SI 0 "register_operand" "")
4479 (match_operand:SI 1 "const_int_operand" "")))
4480 (set (pc)
4481 (if_then_else (match_operator 3 "eqne_operator"
4482 [(cc0) (const_int 0)])
4483 (label_ref (match_operand 2 "" ""))
4484 (pc)))]
4485 "(TARGET_H8300H || TARGET_H8300S)
4486 && peep2_reg_dead_p (1, operands[0])
4487 && (INTVAL (operands[1]) == -2147483647 - 1
4488 || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
4489 [(set (match_dup 0)
4490 (rotate:SI (match_dup 0)
4491 (match_dup 4)))
4492 (set (match_dup 0)
4493 (unspec:SI [(match_dup 0)
4494 (const_int -1)]
4495 UNSPEC_INCDEC))
4496 (set (cc0)
4497 (match_dup 0))
4498 (set (pc)
4499 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4500 (label_ref (match_dup 2))
4501 (pc)))]
4502 "operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2);")
4503
4504 ;; Transform
4505 ;;
4506 ;; cmp.l #1,er0
4507 ;; bhi .L1
4508 ;;
4509 ;; into
4510 ;;
4511 ;; mov.l er0,er1
4512 ;; shar.l er1
4513 ;; bne .L1
4514
4515 ;; We avoid this transformation if we see more than one copy of the
4516 ;; same compare insn immediately before this one.
4517
4518 (define_peephole2
4519 [(match_scratch:SI 4 "r")
4520 (set (cc0)
4521 (compare (match_operand:SI 0 "register_operand" "")
4522 (match_operand:SI 1 "const_int_operand" "")))
4523 (set (pc)
4524 (if_then_else (match_operator 2 "gtle_operator"
4525 [(cc0) (const_int 0)])
4526 (label_ref (match_operand 3 "" ""))
4527 (pc)))]
4528 "(TARGET_H8300H || TARGET_H8300S)
4529 && !peep2_reg_dead_p (1, operands[0])
4530 && (INTVAL (operands[1]) == 1
4531 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
4532 && !same_cmp_preceding_p (insn)"
4533 [(set (match_dup 4)
4534 (match_dup 0))
4535 (parallel [(set (match_dup 4)
4536 (ashiftrt:SI (match_dup 4)
4537 (match_dup 6)))
4538 (clobber (scratch:QI))])
4539 (set (cc0)
4540 (match_dup 4))
4541 (set (pc)
4542 (if_then_else (match_dup 5)
4543 (label_ref (match_dup 3))
4544 (pc)))]
4545 "switch (GET_CODE (operands[2]))
4546 {
4547 case GTU:
4548 operands[5] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4549 break;
4550 case LEU:
4551 operands[5] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4552 break;
4553 default:
4554 operands[5] = operands[2];
4555 break;
4556 }
4557 operands[6] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4558
4559 ;; Transform
4560 ;;
4561 ;; cmp.l #1,er0
4562 ;; bhi .L1
4563 ;;
4564 ;; into
4565 ;;
4566 ;; shar.l er0
4567 ;; bne .L1
4568
4569 (define_peephole2
4570 [(set (cc0)
4571 (compare (match_operand:SI 0 "register_operand" "")
4572 (match_operand:SI 1 "const_int_operand" "")))
4573 (set (pc)
4574 (if_then_else (match_operator 2 "gtle_operator"
4575 [(cc0) (const_int 0)])
4576 (label_ref (match_operand 3 "" ""))
4577 (pc)))]
4578 "(TARGET_H8300H || TARGET_H8300S)
4579 && peep2_reg_dead_p (1, operands[0])
4580 && (INTVAL (operands[1]) == 1
4581 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4582 [(parallel [(set (match_dup 0)
4583 (ashiftrt:SI (match_dup 0)
4584 (match_dup 5)))
4585 (clobber (scratch:QI))])
4586 (set (cc0)
4587 (match_dup 0))
4588 (set (pc)
4589 (if_then_else (match_dup 4)
4590 (label_ref (match_dup 3))
4591 (pc)))]
4592 "switch (GET_CODE (operands[2]))
4593 {
4594 case GTU:
4595 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4596 break;
4597 case LEU:
4598 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4599 break;
4600 default:
4601 operands[4] = operands[2];
4602 break;
4603 }
4604 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4605
4606 ;; Transform
4607 ;;
4608 ;; cmp.l #15,er0
4609 ;; bhi .L1
4610 ;;
4611 ;; into
4612 ;;
4613 ;; and #240,r0l
4614 ;; mov.l er0,er0
4615 ;; bne .L1
4616
4617 (define_peephole2
4618 [(set (cc0)
4619 (compare (match_operand:SI 0 "register_operand" "")
4620 (match_operand:SI 1 "const_int_operand" "")))
4621 (set (pc)
4622 (if_then_else (match_operator 2 "gtle_operator"
4623 [(cc0) (const_int 0)])
4624 (label_ref (match_operand 3 "" ""))
4625 (pc)))]
4626 "(TARGET_H8300H || TARGET_H8300S)
4627 && peep2_reg_dead_p (1, operands[0])
4628 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
4629 || INTVAL (operands[1]) == 7
4630 || INTVAL (operands[1]) == 15
4631 || INTVAL (operands[1]) == 31
4632 || INTVAL (operands[1]) == 63
4633 || INTVAL (operands[1]) == 127
4634 || INTVAL (operands[1]) == 255)"
4635 [(set (match_dup 0)
4636 (and:SI (match_dup 0)
4637 (match_dup 5)))
4638 (set (cc0)
4639 (match_dup 0))
4640 (set (pc)
4641 (if_then_else (match_dup 4)
4642 (label_ref (match_dup 3))
4643 (pc)))]
4644 "switch (GET_CODE (operands[2]))
4645 {
4646 case GTU:
4647 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4648 break;
4649 case LEU:
4650 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4651 break;
4652 default:
4653 operands[4] = operands[2];
4654 break;
4655 }
4656 operands[5] = GEN_INT (~INTVAL (operands[1]));")
4657
4658 ;; Transform A <= 65535 to (A & 0xffff0000) == 0.
4659
4660 (define_peephole2
4661 [(set (cc0)
4662 (compare (match_operand:SI 0 "register_operand" "")
4663 (const_int 65535)))
4664 (set (pc)
4665 (if_then_else (match_operator 1 "gtle_operator"
4666 [(cc0) (const_int 0)])
4667 (label_ref (match_operand 2 "" ""))
4668 (pc)))]
4669 "TARGET_H8300H || TARGET_H8300S"
4670 [(set (cc0)
4671 (and:SI (match_dup 0)
4672 (const_int -65536)))
4673 (set (pc)
4674 (if_then_else (match_dup 3)
4675 (label_ref (match_dup 2))
4676 (pc)))]
4677 "switch (GET_CODE (operands[1]))
4678 {
4679 case GTU:
4680 operands[3] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4681 break;
4682 case LEU:
4683 operands[3] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4684 break;
4685 default:
4686 operands[3] = operands[1];
4687 break;
4688 }")
4689
4690 ;; For constants like -1, -2, 1, 2, it is still cheaper to make a copy
4691 ;; of the register being tested, do the subtraction on the copy, and
4692 ;; then test the copy. We avoid this transformation if we see more
4693 ;; than one copy of the same compare insn.
4694
4695 (define_peephole2
4696 [(match_scratch:SI 4 "r")
4697 (set (cc0)
4698 (compare (match_operand:SI 0 "register_operand" "")
4699 (match_operand:SI 1 "incdec_operand" "")))
4700 (set (pc)
4701 (if_then_else (match_operator 3 "eqne_operator"
4702 [(cc0) (const_int 0)])
4703 (label_ref (match_operand 2 "" ""))
4704 (pc)))]
4705 "(TARGET_H8300H || TARGET_H8300S)
4706 && !peep2_reg_dead_p (1, operands[0])
4707 && !same_cmp_following_p (insn)"
4708 [(set (match_dup 4)
4709 (match_dup 0))
4710 (set (match_dup 4)
4711 (unspec:SI [(match_dup 4)
4712 (match_dup 5)]
4713 UNSPEC_INCDEC))
4714 (set (cc0)
4715 (match_dup 4))
4716 (set (pc)
4717 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4718 (label_ref (match_dup 2))
4719 (pc)))]
4720 "operands[5] = GEN_INT (- INTVAL (operands[1]));")
4721
4722 ;; Narrow the mode of testing if possible.
4723
4724 (define_peephole2
4725 [(set (match_operand:HI 0 "register_operand" "")
4726 (and:HI (match_dup 0)
4727 (match_operand:HI 1 "const_int_qi_operand" "")))
4728 (set (cc0)
4729 (match_dup 0))
4730 (set (pc)
4731 (if_then_else (match_operator 3 "eqne_operator"
4732 [(cc0) (const_int 0)])
4733 (label_ref (match_operand 2 "" ""))
4734 (pc)))]
4735 "peep2_reg_dead_p (2, operands[0])"
4736 [(set (match_dup 4)
4737 (and:QI (match_dup 4)
4738 (match_dup 5)))
4739 (set (cc0)
4740 (match_dup 4))
4741 (set (pc)
4742 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4743 (label_ref (match_dup 2))
4744 (pc)))]
4745 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
4746 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
4747
4748 (define_peephole2
4749 [(set (match_operand:SI 0 "register_operand" "")
4750 (and:SI (match_dup 0)
4751 (match_operand:SI 1 "const_int_qi_operand" "")))
4752 (set (cc0)
4753 (match_dup 0))
4754 (set (pc)
4755 (if_then_else (match_operator 3 "eqne_operator"
4756 [(cc0) (const_int 0)])
4757 (label_ref (match_operand 2 "" ""))
4758 (pc)))]
4759 "peep2_reg_dead_p (2, operands[0])"
4760 [(set (match_dup 4)
4761 (and:QI (match_dup 4)
4762 (match_dup 5)))
4763 (set (cc0)
4764 (match_dup 4))
4765 (set (pc)
4766 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4767 (label_ref (match_dup 2))
4768 (pc)))]
4769 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
4770 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
4771
4772 (define_peephole2
4773 [(set (match_operand:SI 0 "register_operand" "")
4774 (and:SI (match_dup 0)
4775 (match_operand:SI 1 "const_int_hi_operand" "")))
4776 (set (cc0)
4777 (match_dup 0))
4778 (set (pc)
4779 (if_then_else (match_operator 3 "eqne_operator"
4780 [(cc0) (const_int 0)])
4781 (label_ref (match_operand 2 "" ""))
4782 (pc)))]
4783 "peep2_reg_dead_p (2, operands[0])"
4784 [(set (match_dup 4)
4785 (and:HI (match_dup 4)
4786 (match_dup 5)))
4787 (set (cc0)
4788 (match_dup 4))
4789 (set (pc)
4790 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4791 (label_ref (match_dup 2))
4792 (pc)))]
4793 "operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
4794 operands[5] = gen_int_mode (INTVAL (operands[1]), HImode);")
4795
4796 (define_peephole2
4797 [(set (match_operand:SI 0 "register_operand" "")
4798 (and:SI (match_dup 0)
4799 (match_operand:SI 1 "const_int_qi_operand" "")))
4800 (set (match_dup 0)
4801 (xor:SI (match_dup 0)
4802 (match_operand:SI 2 "const_int_qi_operand" "")))
4803 (set (cc0)
4804 (match_dup 0))
4805 (set (pc)
4806 (if_then_else (match_operator 4 "eqne_operator"
4807 [(cc0) (const_int 0)])
4808 (label_ref (match_operand 3 "" ""))
4809 (pc)))]
4810 "peep2_reg_dead_p (3, operands[0])
4811 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
4812 [(set (match_dup 5)
4813 (and:QI (match_dup 5)
4814 (match_dup 6)))
4815 (set (match_dup 5)
4816 (xor:QI (match_dup 5)
4817 (match_dup 7)))
4818 (set (cc0)
4819 (match_dup 5))
4820 (set (pc)
4821 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
4822 (label_ref (match_dup 3))
4823 (pc)))]
4824 "operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
4825 operands[6] = gen_int_mode (INTVAL (operands[1]), QImode);
4826 operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);")
4827
4828 ;; These triggers right at the end of allocation of locals in the
4829 ;; prologue (and possibly at other places).
4830
4831 ;; stack adjustment of -4, generate one push
4832 ;;
4833 ;; before : 6 bytes, 10 clocks
4834 ;; after : 4 bytes, 10 clocks
4835
4836 (define_peephole2
4837 [(set (reg:SI SP_REG)
4838 (plus:SI (reg:SI SP_REG)
4839 (const_int -4)))
4840 (set (mem:SI (reg:SI SP_REG))
4841 (match_operand:SI 0 "register_operand" ""))]
4842 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
4843 && REGNO (operands[0]) != SP_REG"
4844 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4845 (match_dup 0))]
4846 "")
4847
4848 ;; stack adjustment of -12, generate one push
4849 ;;
4850 ;; before : 10 bytes, 14 clocks
4851 ;; after : 8 bytes, 14 clocks
4852
4853 (define_peephole2
4854 [(set (reg:SI SP_REG)
4855 (plus:SI (reg:SI SP_REG)
4856 (const_int -12)))
4857 (set (mem:SI (reg:SI SP_REG))
4858 (match_operand:SI 0 "register_operand" ""))]
4859 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
4860 && REGNO (operands[0]) != SP_REG"
4861 [(set (reg:SI SP_REG)
4862 (plus:SI (reg:SI SP_REG)
4863 (const_int -4)))
4864 (set (reg:SI SP_REG)
4865 (plus:SI (reg:SI SP_REG)
4866 (const_int -4)))
4867 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4868 (match_dup 0))]
4869 "")