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h8300.md (pushqi1_h8300hs): Revert my patch today.
[gcc.git] / gcc / config / h8300 / h8300.md
1 ;; GCC machine description for Hitachi H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003 Free Software Foundation, Inc.
4
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7
8 ;; This file is part of GCC.
9
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; any later version.
14
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
19
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
24
25 ;; We compute exact length on each instruction for most of the time.
26 ;; In some case, most notably bit operations that may involve memory
27 ;; operands, the lengths in this file are "worst case".
28
29 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
30 ;; registers. Right now GCC doesn't expose the "e" half to the
31 ;; compiler, so using add/subs for addhi and subhi is safe. Long
32 ;; term, we want to expose the "e" half to the compiler (gives us 8
33 ;; more 16bit registers). At that point addhi and subhi can't use
34 ;; adds/subs.
35
36 ;; There's currently no way to have an insv/extzv expander for the H8/300H
37 ;; because word_mode is different for the H8/300 and H8/300H.
38
39 ;; Shifts/rotates by small constants should be handled by special
40 ;; patterns so we get the length and cc status correct.
41
42 ;; Bitfield operations no longer accept memory operands. We need
43 ;; to add variants which operate on memory back to the MD.
44
45 ;; ??? Implement remaining bit ops available on the h8300
46
47 ;; ----------------------------------------------------------------------
48 ;; CONSTANTS
49 ;; ----------------------------------------------------------------------
50
51 (define_constants
52 [(UNSPEC_INCDEC 0)
53 (UNSPEC_MONITOR 1)])
54
55 (define_constants
56 [(SC_REG 3)
57 (FP_REG 6)
58 (SP_REG 7)
59 (MAC_REG 8)
60 (AP_REG 9)
61 (RAP_REG 10)])
62
63 ;; ----------------------------------------------------------------------
64 ;; ATTRIBUTES
65 ;; ----------------------------------------------------------------------
66
67 (define_attr "cpu" "h8300,h8300h"
68 (const (symbol_ref "cpu_type")))
69
70 (define_attr "type" "branch,arith"
71 (const_string "arith"))
72
73 ;; The size of instructions in bytes.
74
75 (define_attr "length" ""
76 (cond [(eq_attr "type" "branch")
77 (if_then_else (and (ge (minus (match_dup 0) (pc))
78 (const_int -126))
79 (le (minus (match_dup 0) (pc))
80 (const_int 126)))
81 (const_int 2)
82 (if_then_else (and (eq_attr "cpu" "h8300h")
83 (and (ge (minus (pc) (match_dup 0))
84 (const_int -32000))
85 (le (minus (pc) (match_dup 0))
86 (const_int 32000))))
87 (const_int 4)
88 (const_int 6)))]
89 (const_int 200)))
90
91 ;; Condition code settings.
92 ;;
93 ;; none - insn does not affect cc
94 ;; none_0hit - insn does not affect cc but it does modify operand 0
95 ;; This attribute is used to keep track of when operand 0 changes.
96 ;; See the description of NOTICE_UPDATE_CC for more info.
97 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
98 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
99 ;; compare - compare instruction
100 ;; clobber - value of cc is unknown
101
102 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
103 (const_string "clobber"))
104 \f
105 ;; ----------------------------------------------------------------------
106 ;; MOVE INSTRUCTIONS
107 ;; ----------------------------------------------------------------------
108
109 ;; movqi
110
111 (define_insn "pushqi1_h8300"
112 [(parallel [(set (reg:HI SP_REG)
113 (plus:HI (reg:HI SP_REG) (const_int -2)))
114 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
115 (match_operand:QI 0 "register_operand" "r"))])]
116 "TARGET_H8300
117 && REGNO (operands[0]) != SP_REG"
118 "mov.w\\t%T0,@-r7"
119 [(set_attr "length" "2")
120 (set_attr "cc" "clobber")])
121
122 (define_insn "pushqi1_h8300hs"
123 [(parallel [(set (reg:SI SP_REG)
124 (plus:SI (reg:SI SP_REG) (const_int -4)))
125 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
126 (match_operand:QI 0 "register_operand" "r"))])]
127 "(TARGET_H8300H || TARGET_H8300S)
128 && REGNO (operands[0]) != SP_REG"
129 "mov.l\\t%S0,@-er7"
130 [(set_attr "length" "4")
131 (set_attr "cc" "clobber")])
132
133 (define_expand "pushqi1"
134 [(use (match_operand:QI 0 "register_operand" ""))]
135 ""
136 "
137 {
138 if (TARGET_H8300)
139 emit_insn (gen_pushqi1_h8300 (operands[0]));
140 else
141 emit_insn (gen_pushqi1_h8300hs (operands[0]));
142 DONE;
143 }")
144
145 (define_insn "*movqi_h8300"
146 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
147 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
148 "TARGET_H8300
149 && (register_operand (operands[0], QImode)
150 || register_operand (operands[1], QImode))"
151 "@
152 sub.b %X0,%X0
153 mov.b %R1,%X0
154 mov.b %X1,%R0
155 mov.b %R1,%X0
156 mov.b %R1,%X0
157 mov.b %X1,%R0"
158 [(set_attr "length" "2,2,2,2,4,4")
159 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
160
161 (define_insn "*movqi_h8300hs"
162 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
163 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
164 "(TARGET_H8300H || TARGET_H8300S)
165 && (register_operand (operands[0], QImode)
166 || register_operand (operands[1], QImode))"
167 "@
168 sub.b %X0,%X0
169 mov.b %R1,%X0
170 mov.b %X1,%R0
171 mov.b %R1,%X0
172 mov.b %R1,%X0
173 mov.b %X1,%R0"
174 [(set (attr "length")
175 (symbol_ref "compute_mov_length (operands)"))
176 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
177
178 (define_expand "movqi"
179 [(set (match_operand:QI 0 "general_operand_dst" "")
180 (match_operand:QI 1 "general_operand_src" ""))]
181 ""
182 "
183 {
184 /* One of the ops has to be in a register. */
185 if (!register_operand (operand0, QImode)
186 && !register_operand (operand1, QImode))
187 {
188 operands[1] = copy_to_mode_reg (QImode, operand1);
189 }
190 }")
191
192 (define_insn "movstrictqi"
193 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r,r,r"))
194 (match_operand:QI 1 "general_operand_src" "I,r,n,m"))]
195 ""
196 "@
197 sub.b %X0,%X0
198 mov.b %X1,%X0
199 mov.b %R1,%X0
200 mov.b %R1,%X0"
201 [(set (attr "length")
202 (symbol_ref "compute_mov_length (operands)"))
203 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
204
205 ;; movhi
206
207 (define_expand "pushhi1_h8300"
208 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
209 (match_operand:HI 0 "register_operand" ""))]
210 "TARGET_H8300
211 && REGNO (operands[0]) != SP_REG"
212 "")
213
214 (define_insn "pushhi1_h8300hs"
215 [(parallel [(set (reg:SI SP_REG)
216 (plus:SI (reg:SI SP_REG) (const_int -4)))
217 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
218 (match_operand:HI 0 "register_operand" "r"))])]
219 "(TARGET_H8300H || TARGET_H8300S)
220 && REGNO (operands[0]) != SP_REG"
221 "mov.l\\t%S0,@-er7"
222 [(set_attr "length" "4")
223 (set_attr "cc" "clobber")])
224
225 (define_expand "pushhi1"
226 [(use (match_operand:HI 0 "register_operand" ""))]
227 ""
228 "
229 {
230 if (TARGET_H8300)
231 emit_insn (gen_pushhi1_h8300 (operands[0]));
232 else
233 emit_insn (gen_pushhi1_h8300hs (operands[0]));
234 DONE;
235 }")
236
237 (define_insn "*movhi_h8300"
238 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
239 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
240 "TARGET_H8300
241 && (register_operand (operands[0], HImode)
242 || register_operand (operands[1], HImode))
243 && !(GET_CODE (operands[0]) == MEM
244 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
245 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
246 && GET_CODE (operands[1]) == REG
247 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
248 "@
249 sub.w %T0,%T0
250 mov.w %T1,%T0
251 mov.w %T1,%T0
252 mov.w %T1,%T0
253 mov.w %T1,%T0
254 mov.w %T1,%T0"
255 [(set (attr "length")
256 (symbol_ref "compute_mov_length (operands)"))
257 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
258
259 (define_insn "*movhi_h8300hs"
260 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
261 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
262 "(TARGET_H8300H || TARGET_H8300S)
263 && (register_operand (operands[0], HImode)
264 || register_operand (operands[1], HImode))"
265 "@
266 sub.w %T0,%T0
267 mov.w %T1,%T0
268 mov.w %T1,%T0
269 mov.w %T1,%T0
270 mov.w %T1,%T0
271 mov.w %T1,%T0"
272 [(set (attr "length")
273 (symbol_ref "compute_mov_length (operands)"))
274 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
275
276 (define_expand "movhi"
277 [(set (match_operand:HI 0 "general_operand_dst" "")
278 (match_operand:HI 1 "general_operand_src" ""))]
279 ""
280 "
281 {
282 /* One of the ops has to be in a register. */
283 if (!register_operand (operand1, HImode)
284 && !register_operand (operand0, HImode))
285 {
286 operands[1] = copy_to_mode_reg (HImode, operand1);
287 }
288 }")
289
290 (define_insn "movstricthi"
291 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r,r"))
292 (match_operand:HI 1 "general_operand_src" "I,r,i,m"))]
293 ""
294 "@
295 sub.w %T0,%T0
296 mov.w %T1,%T0
297 mov.w %T1,%T0
298 mov.w %T1,%T0"
299 [(set (attr "length")
300 (symbol_ref "compute_mov_length (operands)"))
301 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
302
303 ;; movsi
304
305 (define_expand "movsi"
306 [(set (match_operand:SI 0 "general_operand_dst" "")
307 (match_operand:SI 1 "general_operand_src" ""))]
308 ""
309 "
310 {
311 if (TARGET_H8300)
312 {
313 if (do_movsi (operands))
314 DONE;
315 }
316 else
317 {
318 /* One of the ops has to be in a register. */
319 if (!register_operand (operand1, SImode)
320 && !register_operand (operand0, SImode))
321 {
322 operands[1] = copy_to_mode_reg (SImode, operand1);
323 }
324 }
325 }")
326
327 (define_expand "movsf"
328 [(set (match_operand:SF 0 "general_operand_dst" "")
329 (match_operand:SF 1 "general_operand_src" ""))]
330 ""
331 "
332 {
333 if (TARGET_H8300)
334 {
335 if (do_movsi (operands))
336 DONE;
337 }
338 else
339 {
340 /* One of the ops has to be in a register. */
341 if (!register_operand (operand1, SFmode)
342 && !register_operand (operand0, SFmode))
343 {
344 operands[1] = copy_to_mode_reg (SFmode, operand1);
345 }
346 }
347 }")
348
349 (define_insn "*movsi_h8300"
350 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
351 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
352 "TARGET_H8300
353 && (register_operand (operands[0], SImode)
354 || register_operand (operands[1], SImode))"
355 "*
356 {
357 unsigned int rn = -1;
358 switch (which_alternative)
359 {
360 case 0:
361 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
362 case 1:
363 if (REGNO (operands[0]) < REGNO (operands[1]))
364 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
365 else
366 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
367 case 2:
368 /* Make sure we don't trample the register we index with. */
369 if (GET_CODE (operands[1]) == MEM)
370 {
371 rtx inside = XEXP (operands[1], 0);
372 if (REG_P (inside))
373 {
374 rn = REGNO (inside);
375 }
376 else if (GET_CODE (inside) == PLUS)
377 {
378 rtx lhs = XEXP (inside, 0);
379 rtx rhs = XEXP (inside, 1);
380 if (REG_P (lhs)) rn = REGNO (lhs);
381 if (REG_P (rhs)) rn = REGNO (rhs);
382 }
383 }
384 if (rn == REGNO (operands[0]))
385 {
386 /* Move the second word first. */
387 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
388 }
389 else
390 {
391 if (GET_CODE (operands[1]) == CONST_INT)
392 {
393 /* If either half is zero, use sub.w to clear that
394 half. */
395 if ((INTVAL (operands[1]) & 0xffff) == 0)
396 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
397 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
398 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
399 /* If the upper half and the lower half are the same,
400 copy one half to the other. */
401 if ((INTVAL (operands[1]) & 0xffff)
402 == ((INTVAL (operands[1]) >> 16) & 0xffff))
403 return \"mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0\";
404 }
405 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
406 }
407 case 3:
408 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
409 case 4:
410 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
411 case 5:
412 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
413 default:
414 abort ();
415 }
416 }"
417 [(set (attr "length")
418 (symbol_ref "compute_mov_length (operands)"))
419 (set_attr "cc" "clobber")])
420
421 (define_insn "*movsf_h8300"
422 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
423 (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))]
424 "TARGET_H8300
425 && (register_operand (operands[0], SFmode)
426 || register_operand (operands[1], SFmode))"
427 "*
428 {
429 /* Copy of the movsi stuff. */
430 unsigned int rn = -1;
431 switch (which_alternative)
432 {
433 case 0:
434 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
435 case 1:
436 if (REGNO (operands[0]) < REGNO (operands[1]))
437 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
438 else
439 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
440 case 2:
441 /* Make sure we don't trample the register we index with. */
442 if (GET_CODE (operands[1]) == MEM)
443 {
444 rtx inside = XEXP (operands[1], 0);
445 if (REG_P (inside))
446 {
447 rn = REGNO (inside);
448 }
449 else if (GET_CODE (inside) == PLUS)
450 {
451 rtx lhs = XEXP (inside, 0);
452 rtx rhs = XEXP (inside, 1);
453 if (REG_P (lhs)) rn = REGNO (lhs);
454 if (REG_P (rhs)) rn = REGNO (rhs);
455 }
456 }
457 if (rn == REGNO (operands[0]))
458 /* Move the second word first. */
459 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
460 else
461 /* Move the first word first. */
462 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
463
464 case 3:
465 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
466 case 4:
467 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
468 case 5:
469 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
470 default:
471 abort ();
472 }
473 }"
474 [(set (attr "length")
475 (symbol_ref "compute_mov_length (operands)"))
476 (set_attr "cc" "clobber")])
477
478 (define_insn "*movsi_h8300hs"
479 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
480 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
481 "(TARGET_H8300S || TARGET_H8300H)
482 && (register_operand (operands[0], SImode)
483 || register_operand (operands[1], SImode))
484 && !(GET_CODE (operands[0]) == MEM
485 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
486 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
487 && GET_CODE (operands[1]) == REG
488 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
489 "*
490 {
491 switch (which_alternative)
492 {
493 case 0:
494 return \"sub.l %S0,%S0\";
495 case 7:
496 return \"clrmac\";
497 case 8:
498 return \"clrmac\;ldmac %1,macl\";
499 case 9:
500 return \"stmac macl,%0\";
501 default:
502 if (GET_CODE (operands[1]) == CONST_INT)
503 {
504 int val = INTVAL (operands[1]);
505
506 /* Look for constants which can be made by adding an 8-bit
507 number to zero in one of the two low bytes. */
508 if (val == (val & 0xff))
509 {
510 operands[1] = GEN_INT ((char) val & 0xff);
511 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
512 }
513
514 if (val == (val & 0xff00))
515 {
516 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
517 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
518 }
519
520 /* Look for constants that can be obtained by subs, inc, and
521 dec to 0. */
522 switch (val & 0xffffffff)
523 {
524 case 0xffffffff:
525 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
526 case 0xfffffffe:
527 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
528 case 0xfffffffc:
529 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
530
531 case 0x0000ffff:
532 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
533 case 0x0000fffe:
534 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
535
536 case 0xffff0000:
537 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
538 case 0xfffe0000:
539 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
540
541 case 0x00010000:
542 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
543 case 0x00020000:
544 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
545 }
546 }
547 }
548 return \"mov.l %S1,%S0\";
549 }"
550 [(set (attr "length")
551 (symbol_ref "compute_mov_length (operands)"))
552 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
553
554 (define_insn "*movsf_h8300h"
555 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
556 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
557 "(TARGET_H8300H || TARGET_H8300S)
558 && (register_operand (operands[0], SFmode)
559 || register_operand (operands[1], SFmode))"
560 "@
561 sub.l %S0,%S0
562 mov.l %S1,%S0
563 mov.l %S1,%S0
564 mov.l %S1,%S0
565 mov.l %S1,%S0
566 mov.l %S1,%S0"
567 [(set (attr "length")
568 (symbol_ref "compute_mov_length (operands)"))
569 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
570 \f
571 ;; ----------------------------------------------------------------------
572 ;; TEST INSTRUCTIONS
573 ;; ----------------------------------------------------------------------
574
575 (define_insn ""
576 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
577 (const_int 1)
578 (match_operand 1 "const_int_operand" "n,n")))]
579 "TARGET_H8300"
580 "btst %Z1,%Y0"
581 [(set_attr "length" "2,4")
582 (set_attr "cc" "set_zn,set_zn")])
583
584 (define_insn ""
585 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
586 (const_int 1)
587 (match_operand 1 "const_int_operand" "n")))]
588 "TARGET_H8300"
589 "btst %Z1,%Y0"
590 [(set_attr "length" "2")
591 (set_attr "cc" "set_zn")])
592
593 (define_insn "*tst_extzv_1_n"
594 [(set (cc0)
595 (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
596 (const_int 1)
597 (match_operand 1 "const_int_operand" "n,n,n")))
598 (clobber (match_scratch:QI 2 "=X,X,&r"))]
599 "(TARGET_H8300H || TARGET_H8300S)"
600 "@
601 btst\\t%Z1,%Y0
602 btst\\t%Z1,%Y0
603 #"
604 [(set_attr "length" "2,8,10")
605 (set_attr "cc" "set_zn,set_zn,set_zn")])
606
607 (define_split
608 [(set (cc0)
609 (zero_extract:SI (match_operand:QI 0 "general_operand" "")
610 (const_int 1)
611 (match_operand 1 "const_int_operand" "")))
612 (clobber (match_operand:QI 2 "register_operand" ""))]
613 "(TARGET_H8300H || TARGET_H8300S)
614 && reload_completed
615 && !EXTRA_CONSTRAINT (operands[0], 'U')"
616 [(set (match_dup 2)
617 (match_dup 0))
618 (parallel [(set (cc0) (zero_extract:SI (match_dup 2)
619 (const_int 1)
620 (match_dup 1)))
621 (clobber (scratch:QI))])]
622 "")
623
624 (define_insn ""
625 [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
626 (const_int 1)
627 (match_operand 1 "const_int_operand" "n")))]
628 "(TARGET_H8300H || TARGET_H8300S)
629 && INTVAL (operands[1]) <= 15"
630 "btst %Z1,%Y0"
631 [(set_attr "length" "2")
632 (set_attr "cc" "set_zn")])
633
634 (define_insn_and_split "*tstsi_upper_bit"
635 [(set (cc0)
636 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
637 (const_int 1)
638 (match_operand 1 "const_int_operand" "n")))
639 (clobber (match_scratch:SI 2 "=&r"))]
640 "(TARGET_H8300H || TARGET_H8300S)
641 && INTVAL (operands[1]) >= 16"
642 "#"
643 "&& reload_completed"
644 [(set (match_dup 2)
645 (ior:SI (and:SI (match_dup 2)
646 (const_int -65536))
647 (lshiftrt:SI (match_dup 0)
648 (const_int 16))))
649 (set (cc0)
650 (zero_extract:SI (match_dup 2)
651 (const_int 1)
652 (match_dup 3)))]
653 "operands[3] = GEN_INT (INTVAL (operands[1]) - 16);")
654
655 (define_insn ""
656 [(set (cc0)
657 (and:HI (match_operand:HI 0 "register_operand" "r")
658 (match_operand:HI 1 "single_one_operand" "n")))]
659 ""
660 "*
661 {
662 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
663 if (INTVAL (operands[1]) > 128)
664 {
665 operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
666 return \"btst\\t%V1,%t0\";
667 }
668 return \"btst\\t%V1,%s0\";
669 }"
670 [(set_attr "length" "2")
671 (set_attr "cc" "set_zn")])
672
673 (define_insn ""
674 [(set (cc0)
675 (and:SI (match_operand:SI 0 "register_operand" "r")
676 (match_operand:SI 1 "single_one_operand" "n")))]
677 "(TARGET_H8300H || TARGET_H8300S)
678 && (INTVAL (operands[1]) & 0xffff) != 0"
679 "*
680 {
681 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
682 if (INTVAL (operands[1]) > 128)
683 {
684 operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
685 return \"btst\\t%V1,%x0\";
686 }
687 return \"btst\\t%V1,%w0\";
688 }"
689 [(set_attr "length" "2")
690 (set_attr "cc" "set_zn")])
691
692 (define_insn "tstqi"
693 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
694 ""
695 "mov.b %X0,%X0"
696 [(set_attr "length" "2")
697 (set_attr "cc" "set_znv")])
698
699 (define_insn "tsthi"
700 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
701 ""
702 "mov.w %T0,%T0"
703 [(set_attr "length" "2")
704 (set_attr "cc" "set_znv")])
705
706 (define_insn ""
707 [(set (cc0)
708 (and:HI (match_operand:HI 0 "register_operand" "r")
709 (const_int -256)))]
710 ""
711 "mov.b %t0,%t0"
712 [(set_attr "length" "2")
713 (set_attr "cc" "set_znv")])
714
715 (define_insn "tstsi"
716 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
717 "TARGET_H8300H || TARGET_H8300S"
718 "mov.l %S0,%S0"
719 [(set_attr "length" "2")
720 (set_attr "cc" "set_znv")])
721
722 (define_insn ""
723 [(set (cc0)
724 (and:SI (match_operand:SI 0 "register_operand" "r")
725 (const_int -65536)))]
726 ""
727 "mov.w %e0,%e0"
728 [(set_attr "length" "2")
729 (set_attr "cc" "set_znv")])
730
731 (define_insn "cmpqi"
732 [(set (cc0)
733 (compare (match_operand:QI 0 "register_operand" "r")
734 (match_operand:QI 1 "nonmemory_operand" "rn")))]
735 ""
736 "cmp.b %X1,%X0"
737 [(set_attr "length" "2")
738 (set_attr "cc" "compare")])
739
740 (define_expand "cmphi"
741 [(set (cc0)
742 (compare (match_operand:HI 0 "register_operand" "")
743 (match_operand:HI 1 "nonmemory_operand" "")))]
744 ""
745 "
746 {
747 /* Force operand1 into a register if we're compiling
748 for the H8/300. */
749 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
750 operands[1] = force_reg (HImode, operands[1]);
751 }")
752
753 (define_insn "*cmphi_h8300"
754 [(set (cc0)
755 (compare (match_operand:HI 0 "register_operand" "r")
756 (match_operand:HI 1 "register_operand" "r")))]
757 "TARGET_H8300"
758 "cmp.w %T1,%T0"
759 [(set_attr "length" "2")
760 (set_attr "cc" "compare")])
761
762 (define_insn "*cmphi_h8300hs"
763 [(set (cc0)
764 (compare (match_operand:HI 0 "register_operand" "r,r")
765 (match_operand:HI 1 "nonmemory_operand" "r,n")))]
766 "TARGET_H8300H || TARGET_H8300S"
767 "cmp.w %T1,%T0"
768 [(set_attr "length" "2,4")
769 (set_attr "cc" "compare,compare")])
770
771 (define_insn "cmpsi"
772 [(set (cc0)
773 (compare (match_operand:SI 0 "register_operand" "r,r")
774 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
775 "TARGET_H8300H || TARGET_H8300S"
776 "cmp.l %S1,%S0"
777 [(set_attr "length" "2,6")
778 (set_attr "cc" "compare,compare")])
779 \f
780 ;; ----------------------------------------------------------------------
781 ;; ADD INSTRUCTIONS
782 ;; ----------------------------------------------------------------------
783
784 (define_insn "addqi3"
785 [(set (match_operand:QI 0 "register_operand" "=r")
786 (plus:QI (match_operand:QI 1 "register_operand" "%0")
787 (match_operand:QI 2 "nonmemory_operand" "rn")))]
788 ""
789 "add.b %X2,%X0"
790 [(set_attr "length" "2")
791 (set_attr "cc" "set_zn")])
792
793 (define_expand "addhi3"
794 [(set (match_operand:HI 0 "register_operand" "")
795 (plus:HI (match_operand:HI 1 "register_operand" "")
796 (match_operand:HI 2 "nonmemory_operand" "")))]
797 ""
798 "")
799
800 (define_insn "*addhi3_h8300"
801 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
802 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
803 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
804 "TARGET_H8300"
805 "@
806 adds %2,%T0
807 subs %G2,%T0
808 add.b %t2,%t0
809 add.b %s2,%s0\;addx %t2,%t0
810 add.w %T2,%T0"
811 [(set_attr "length" "2,2,2,4,2")
812 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
813
814 ;; This splitter is very important to make the stack adjustment
815 ;; interrupt-safe. The combination of add.b and addx is unsafe!
816 ;;
817 ;; We apply this split after the peephole2 pass so that we won't end
818 ;; up creating too many adds/subs when a scratch register is
819 ;; available, which is actually a common case because stack unrolling
820 ;; tends to happen immediately after a function call.
821
822 (define_split
823 [(set (match_operand:HI 0 "stack_pointer_operand" "")
824 (plus:HI (match_dup 0)
825 (match_operand 1 "const_int_gt_2_operand" "")))]
826 "TARGET_H8300 && flow2_completed"
827 [(const_int 0)]
828 "split_adds_subs (HImode, operands); DONE;")
829
830 (define_peephole2
831 [(match_scratch:HI 2 "r")
832 (set (match_operand:HI 0 "stack_pointer_operand" "")
833 (plus:HI (match_dup 0)
834 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
835 "TARGET_H8300"
836 [(set (match_dup 2)
837 (match_dup 1))
838 (set (match_dup 0)
839 (plus:HI (match_dup 0)
840 (match_dup 2)))]
841 "")
842
843 (define_insn "*addhi3_h8300hs"
844 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
845 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
846 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
847 "TARGET_H8300H || TARGET_H8300S"
848 "@
849 adds %2,%S0
850 subs %G2,%S0
851 add.b %t2,%t0
852 add.w %T2,%T0
853 add.w %T2,%T0"
854 [(set_attr "length" "2,2,2,4,2")
855 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
856
857 (define_insn "*addhi3_incdec"
858 [(set (match_operand:HI 0 "register_operand" "=r,r")
859 (unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
860 (match_operand:HI 2 "incdec_operand" "M,O")]
861 UNSPEC_INCDEC))]
862 "TARGET_H8300H || TARGET_H8300S"
863 "@
864 inc.w %2,%T0
865 dec.w %G2,%T0"
866 [(set_attr "length" "2,2")
867 (set_attr "cc" "set_zn,set_zn")])
868
869 (define_split
870 [(set (match_operand:HI 0 "register_operand" "")
871 (plus:HI (match_dup 0)
872 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
873 ""
874 [(const_int 0)]
875 "split_adds_subs (HImode, operands); DONE;")
876
877 (define_expand "addsi3"
878 [(set (match_operand:SI 0 "register_operand" "")
879 (plus:SI (match_operand:SI 1 "register_operand" "")
880 (match_operand:SI 2 "nonmemory_operand" "")))]
881 ""
882 "")
883
884 (define_insn "addsi_h8300"
885 [(set (match_operand:SI 0 "register_operand" "=r,r")
886 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
887 (match_operand:SI 2 "nonmemory_operand" "n,r")))]
888 "TARGET_H8300"
889 "* return output_plussi (operands);"
890 [(set (attr "length")
891 (symbol_ref "compute_plussi_length (operands)"))
892 (set (attr "cc")
893 (symbol_ref "compute_plussi_cc (operands)"))])
894
895 (define_insn "addsi_h8300h"
896 [(set (match_operand:SI 0 "register_operand" "=r,r")
897 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
898 (match_operand:SI 2 "nonmemory_operand" "i,r")))]
899 "TARGET_H8300H || TARGET_H8300S"
900 "* return output_plussi (operands);"
901 [(set (attr "length")
902 (symbol_ref "compute_plussi_length (operands)"))
903 (set (attr "cc")
904 (symbol_ref "compute_plussi_cc (operands)"))])
905
906 (define_insn "*addsi3_incdec"
907 [(set (match_operand:SI 0 "register_operand" "=r,r")
908 (unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
909 (match_operand:SI 2 "incdec_operand" "M,O")]
910 UNSPEC_INCDEC))]
911 "TARGET_H8300H || TARGET_H8300S"
912 "@
913 inc.l %2,%S0
914 dec.l %G2,%S0"
915 [(set_attr "length" "2,2")
916 (set_attr "cc" "set_zn,set_zn")])
917
918 (define_split
919 [(set (match_operand:SI 0 "register_operand" "")
920 (plus:SI (match_dup 0)
921 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
922 "TARGET_H8300H || TARGET_H8300S"
923 [(const_int 0)]
924 "split_adds_subs (SImode, operands); DONE;")
925
926 ;; ----------------------------------------------------------------------
927 ;; SUBTRACT INSTRUCTIONS
928 ;; ----------------------------------------------------------------------
929
930 (define_insn "subqi3"
931 [(set (match_operand:QI 0 "register_operand" "=r")
932 (minus:QI (match_operand:QI 1 "register_operand" "0")
933 (match_operand:QI 2 "register_operand" "r")))]
934 ""
935 "sub.b %X2,%X0"
936 [(set_attr "length" "2")
937 (set_attr "cc" "set_zn")])
938
939 (define_expand "subhi3"
940 [(set (match_operand:HI 0 "register_operand" "")
941 (minus:HI (match_operand:HI 1 "general_operand" "")
942 (match_operand:HI 2 "nonmemory_operand" "")))]
943 ""
944 "")
945
946 (define_insn ""
947 [(set (match_operand:HI 0 "register_operand" "=r,&r")
948 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
949 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
950 "TARGET_H8300"
951 "@
952 sub.w %T2,%T0
953 add.b %E2,%s0\;addx %F2,%t0"
954 [(set_attr "length" "2,4")
955 (set_attr "cc" "set_zn,clobber")])
956
957 (define_insn ""
958 [(set (match_operand:HI 0 "register_operand" "=r,&r")
959 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
960 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
961 "TARGET_H8300H || TARGET_H8300S"
962 "@
963 sub.w %T2,%T0
964 sub.w %T2,%T0"
965 [(set_attr "length" "2,4")
966 (set_attr "cc" "set_zn,set_zn")])
967
968 (define_expand "subsi3"
969 [(set (match_operand:SI 0 "register_operand" "")
970 (minus:SI (match_operand:SI 1 "register_operand" "")
971 (match_operand:SI 2 "nonmemory_operand" "")))]
972 ""
973 "")
974
975 (define_insn "subsi3_h8300"
976 [(set (match_operand:SI 0 "register_operand" "=r")
977 (minus:SI (match_operand:SI 1 "register_operand" "0")
978 (match_operand:SI 2 "register_operand" "r")))]
979 "TARGET_H8300"
980 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
981 [(set_attr "length" "6")
982 (set_attr "cc" "clobber")])
983
984 (define_insn "subsi3_h8300h"
985 [(set (match_operand:SI 0 "register_operand" "=r,r")
986 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
987 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
988 "TARGET_H8300H || TARGET_H8300S"
989 "@
990 sub.l %S2,%S0
991 sub.l %S2,%S0"
992 [(set_attr "length" "2,6")
993 (set_attr "cc" "set_zn,set_zn")])
994 \f
995 ;; ----------------------------------------------------------------------
996 ;; MULTIPLY INSTRUCTIONS
997 ;; ----------------------------------------------------------------------
998
999 ;; Note that the H8/300 can only handle umulqihi3.
1000
1001 (define_insn "mulqihi3"
1002 [(set (match_operand:HI 0 "register_operand" "=r")
1003 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1004 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1005 "TARGET_H8300H || TARGET_H8300S"
1006 "mulxs.b %X2,%T0"
1007 [(set_attr "length" "4")
1008 (set_attr "cc" "set_zn")])
1009
1010 (define_insn "mulhisi3"
1011 [(set (match_operand:SI 0 "register_operand" "=r")
1012 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1013 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1014 "TARGET_H8300H || TARGET_H8300S"
1015 "mulxs.w %T2,%S0"
1016 [(set_attr "length" "4")
1017 (set_attr "cc" "set_zn")])
1018
1019 (define_insn "umulqihi3"
1020 [(set (match_operand:HI 0 "register_operand" "=r")
1021 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1022 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1023 ""
1024 "mulxu %X2,%T0"
1025 [(set_attr "length" "2")
1026 (set_attr "cc" "none_0hit")])
1027
1028 (define_insn "umulhisi3"
1029 [(set (match_operand:SI 0 "register_operand" "=r")
1030 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1031 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1032 "TARGET_H8300H || TARGET_H8300S"
1033 "mulxu.w %T2,%S0"
1034 [(set_attr "length" "2")
1035 (set_attr "cc" "none_0hit")])
1036
1037 ;; This is a "bridge" instruction. Combine can't cram enough insns
1038 ;; together to crate a MAC instruction directly, but it can create
1039 ;; this instruction, which then allows combine to create the real
1040 ;; MAC insn.
1041 ;;
1042 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1043 ;; insn must generate reasonably correct code. Egad.
1044 (define_insn ""
1045 [(set (match_operand:SI 0 "register_operand" "=a")
1046 (mult:SI
1047 (sign_extend:SI
1048 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1049 (sign_extend:SI
1050 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
1051 "TARGET_MAC"
1052 "clrmac\;mac @%2+,@%1+"
1053 [(set_attr "length" "6")
1054 (set_attr "cc" "none_0hit")])
1055
1056 (define_insn ""
1057 [(set (match_operand:SI 0 "register_operand" "=a")
1058 (plus:SI (mult:SI
1059 (sign_extend:SI (mem:HI
1060 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1061 (sign_extend:SI (mem:HI
1062 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1063 (match_operand:SI 3 "register_operand" "0")))]
1064 "TARGET_MAC"
1065 "mac @%2+,@%1+"
1066 [(set_attr "length" "4")
1067 (set_attr "cc" "none_0hit")])
1068
1069 ;; ----------------------------------------------------------------------
1070 ;; DIVIDE/MOD INSTRUCTIONS
1071 ;; ----------------------------------------------------------------------
1072
1073 (define_insn "udivmodqi4"
1074 [(set (match_operand:QI 0 "register_operand" "=r")
1075 (truncate:QI
1076 (udiv:HI
1077 (match_operand:HI 1 "register_operand" "0")
1078 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1079 (set (match_operand:QI 3 "register_operand" "=r")
1080 (truncate:QI
1081 (umod:HI
1082 (match_dup 1)
1083 (zero_extend:HI (match_dup 2)))))]
1084 ""
1085 "*
1086 {
1087 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1088 return \"divxu.b\\t%X2,%T0\";
1089 else
1090 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1091 }"
1092 [(set_attr "length" "4")
1093 (set_attr "cc" "clobber")])
1094
1095 (define_insn "divmodqi4"
1096 [(set (match_operand:QI 0 "register_operand" "=r")
1097 (truncate:QI
1098 (div:HI
1099 (match_operand:HI 1 "register_operand" "0")
1100 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1101 (set (match_operand:QI 3 "register_operand" "=r")
1102 (truncate:QI
1103 (mod:HI
1104 (match_dup 1)
1105 (sign_extend:HI (match_dup 2)))))]
1106 "TARGET_H8300H || TARGET_H8300S"
1107 "*
1108 {
1109 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1110 return \"divxs.b\\t%X2,%T0\";
1111 else
1112 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1113 }"
1114 [(set_attr "length" "6")
1115 (set_attr "cc" "clobber")])
1116
1117 (define_insn "udivmodhi4"
1118 [(set (match_operand:HI 0 "register_operand" "=r")
1119 (truncate:HI
1120 (udiv:SI
1121 (match_operand:SI 1 "register_operand" "0")
1122 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1123 (set (match_operand:HI 3 "register_operand" "=r")
1124 (truncate:HI
1125 (umod:SI
1126 (match_dup 1)
1127 (zero_extend:SI (match_dup 2)))))]
1128 "TARGET_H8300H || TARGET_H8300S"
1129 "*
1130 {
1131 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1132 return \"divxu.w\\t%T2,%S0\";
1133 else
1134 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1135 }"
1136 [(set_attr "length" "4")
1137 (set_attr "cc" "clobber")])
1138
1139 (define_insn "divmodhi4"
1140 [(set (match_operand:HI 0 "register_operand" "=r")
1141 (truncate:HI
1142 (div:SI
1143 (match_operand:SI 1 "register_operand" "0")
1144 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1145 (set (match_operand:HI 3 "register_operand" "=r")
1146 (truncate:HI
1147 (mod:SI
1148 (match_dup 1)
1149 (sign_extend:SI (match_dup 2)))))]
1150 "TARGET_H8300H || TARGET_H8300S"
1151 "*
1152 {
1153 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1154 return \"divxs.w\\t%T2,%S0\";
1155 else
1156 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1157 }"
1158 [(set_attr "length" "6")
1159 (set_attr "cc" "clobber")])
1160 \f
1161 ;; ----------------------------------------------------------------------
1162 ;; AND INSTRUCTIONS
1163 ;; ----------------------------------------------------------------------
1164
1165 (define_insn ""
1166 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1167 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1168 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1169 "register_operand (operands[0], QImode)
1170 || single_zero_operand (operands[2], QImode)"
1171 "@
1172 and %X2,%X0
1173 bclr %W2,%R0"
1174 [(set_attr "length" "2,8")
1175 (set_attr "cc" "set_znv,none_0hit")])
1176
1177 (define_expand "andqi3"
1178 [(set (match_operand:QI 0 "bit_operand" "")
1179 (and:QI (match_operand:QI 1 "bit_operand" "")
1180 (match_operand:QI 2 "nonmemory_operand" "")))]
1181 ""
1182 "
1183 {
1184 if (fix_bit_operand (operands, 0, AND))
1185 DONE;
1186 }")
1187
1188 (define_expand "andhi3"
1189 [(set (match_operand:HI 0 "register_operand" "")
1190 (and:HI (match_operand:HI 1 "register_operand" "")
1191 (match_operand:HI 2 "nonmemory_operand" "")))]
1192 ""
1193 "")
1194
1195 (define_insn "*andorqi3"
1196 [(set (match_operand:QI 0 "register_operand" "=r")
1197 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1198 (match_operand:QI 3 "single_one_operand" "n"))
1199 (match_operand:QI 1 "register_operand" "0")))]
1200 ""
1201 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1202 [(set_attr "length" "6")
1203 (set_attr "cc" "clobber")])
1204
1205 (define_insn "*andorhi3"
1206 [(set (match_operand:HI 0 "register_operand" "=r")
1207 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1208 (match_operand:HI 3 "single_one_operand" "n"))
1209 (match_operand:HI 1 "register_operand" "0")))]
1210 ""
1211 "*
1212 {
1213 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1214 if (INTVAL (operands[3]) > 128)
1215 {
1216 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1217 return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\";
1218 }
1219 return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\";
1220 }"
1221 [(set_attr "length" "6")
1222 (set_attr "cc" "clobber")])
1223
1224 (define_insn "*andorsi3"
1225 [(set (match_operand:SI 0 "register_operand" "=r")
1226 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1227 (match_operand:SI 3 "single_one_operand" "n"))
1228 (match_operand:SI 1 "register_operand" "0")))]
1229 "(INTVAL (operands[3]) & 0xffff) != 0"
1230 "*
1231 {
1232 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1233 if (INTVAL (operands[3]) > 128)
1234 {
1235 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1236 return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\";
1237 }
1238 return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\";
1239 }"
1240 [(set_attr "length" "6")
1241 (set_attr "cc" "clobber")])
1242
1243 (define_insn "*andorsi3_shift_8"
1244 [(set (match_operand:SI 0 "register_operand" "=r")
1245 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1246 (const_int 8))
1247 (const_int 65280))
1248 (match_operand:SI 1 "register_operand" "0")))]
1249 ""
1250 "or.b\\t%w2,%x0"
1251 [(set_attr "length" "2")
1252 (set_attr "cc" "clobber")])
1253
1254 (define_expand "andsi3"
1255 [(set (match_operand:SI 0 "register_operand" "")
1256 (and:SI (match_operand:SI 1 "register_operand" "")
1257 (match_operand:SI 2 "nonmemory_operand" "")))]
1258 ""
1259 "")
1260
1261 ;; ----------------------------------------------------------------------
1262 ;; OR INSTRUCTIONS
1263 ;; ----------------------------------------------------------------------
1264
1265 (define_insn ""
1266 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1267 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1268 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1269 "register_operand (operands[0], QImode)
1270 || single_one_operand (operands[2], QImode)"
1271 "@
1272 or\\t%X2,%X0
1273 bset\\t%V2,%R0"
1274 [(set_attr "length" "2,8")
1275 (set_attr "cc" "set_znv,none_0hit")])
1276
1277 (define_expand "iorqi3"
1278 [(set (match_operand:QI 0 "bit_operand" "")
1279 (ior:QI (match_operand:QI 1 "bit_operand" "")
1280 (match_operand:QI 2 "nonmemory_operand" "")))]
1281 ""
1282 "
1283 {
1284 if (fix_bit_operand (operands, 1, IOR))
1285 DONE;
1286 }")
1287
1288 (define_expand "iorhi3"
1289 [(set (match_operand:HI 0 "register_operand" "")
1290 (ior:HI (match_operand:HI 1 "register_operand" "")
1291 (match_operand:HI 2 "nonmemory_operand" "")))]
1292 ""
1293 "")
1294
1295 (define_expand "iorsi3"
1296 [(set (match_operand:SI 0 "register_operand" "")
1297 (ior:SI (match_operand:SI 1 "register_operand" "")
1298 (match_operand:SI 2 "nonmemory_operand" "")))]
1299 ""
1300 "")
1301
1302 ;; ----------------------------------------------------------------------
1303 ;; XOR INSTRUCTIONS
1304 ;; ----------------------------------------------------------------------
1305
1306 (define_insn ""
1307 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1308 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1309 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1310 "register_operand (operands[0], QImode)
1311 || single_one_operand (operands[2], QImode)"
1312 "@
1313 xor\\t%X2,%X0
1314 bnot\\t%V2,%R0"
1315 [(set_attr "length" "2,8")
1316 (set_attr "cc" "set_znv,none_0hit")])
1317
1318 (define_expand "xorqi3"
1319 [(set (match_operand:QI 0 "bit_operand" "")
1320 (xor:QI (match_operand:QI 1 "bit_operand" "")
1321 (match_operand:QI 2 "nonmemory_operand" "")))]
1322 ""
1323 "
1324 {
1325 if (fix_bit_operand (operands, 1, XOR))
1326 DONE;
1327 }")
1328
1329 (define_expand "xorhi3"
1330 [(set (match_operand:HI 0 "register_operand" "")
1331 (xor:HI (match_operand:HI 1 "register_operand" "")
1332 (match_operand:HI 2 "nonmemory_operand" "")))]
1333 ""
1334 "")
1335
1336 (define_expand "xorsi3"
1337 [(set (match_operand:SI 0 "register_operand" "")
1338 (xor:SI (match_operand:SI 1 "register_operand" "")
1339 (match_operand:SI 2 "nonmemory_operand" "")))]
1340 ""
1341 "")
1342
1343 ;; ----------------------------------------------------------------------
1344 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1345 ;; ----------------------------------------------------------------------
1346
1347 (define_insn ""
1348 [(set (match_operand:HI 0 "register_operand" "=r")
1349 (match_operator:HI 3 "bit_operator"
1350 [(match_operand:HI 1 "register_operand" "%0")
1351 (match_operand:HI 2 "nonmemory_operand" "rn")]))]
1352 ""
1353 "* return output_logical_op (HImode, operands);"
1354 [(set (attr "length")
1355 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1356 (set (attr "cc")
1357 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1358
1359 (define_insn ""
1360 [(set (match_operand:SI 0 "register_operand" "=r")
1361 (match_operator:SI 3 "bit_operator"
1362 [(match_operand:SI 1 "register_operand" "%0")
1363 (match_operand:SI 2 "nonmemory_operand" "rn")]))]
1364 ""
1365 "* return output_logical_op (SImode, operands);"
1366 [(set (attr "length")
1367 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1368 (set (attr "cc")
1369 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1370 \f
1371 ;; ----------------------------------------------------------------------
1372 ;; NEGATION INSTRUCTIONS
1373 ;; ----------------------------------------------------------------------
1374
1375 (define_insn "negqi2"
1376 [(set (match_operand:QI 0 "register_operand" "=r")
1377 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1378 ""
1379 "neg %X0"
1380 [(set_attr "length" "2")
1381 (set_attr "cc" "set_zn")])
1382
1383 (define_expand "neghi2"
1384 [(set (match_operand:HI 0 "register_operand" "")
1385 (neg:HI (match_operand:HI 1 "register_operand" "")))]
1386 ""
1387 "
1388 {
1389 if (TARGET_H8300)
1390 {
1391 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1392 DONE;
1393 }
1394 }")
1395
1396 (define_expand "neghi2_h8300"
1397 [(set (match_dup 2)
1398 (not:HI (match_operand:HI 1 "register_operand" "")))
1399 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1400 (set (match_operand:HI 0 "register_operand" "")
1401 (match_dup 2))]
1402 ""
1403 "operands[2] = gen_reg_rtx (HImode);")
1404
1405 (define_insn "neghi2_h8300h"
1406 [(set (match_operand:HI 0 "register_operand" "=r")
1407 (neg:HI (match_operand:HI 1 "register_operand" "0")))]
1408 "TARGET_H8300H || TARGET_H8300S"
1409 "neg %T0"
1410 [(set_attr "length" "2")
1411 (set_attr "cc" "set_zn")])
1412
1413 (define_expand "negsi2"
1414 [(set (match_operand:SI 0 "register_operand" "")
1415 (neg:SI (match_operand:SI 1 "register_operand" "")))]
1416 ""
1417 "
1418 {
1419 if (TARGET_H8300)
1420 {
1421 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1422 DONE;
1423 }
1424 }")
1425
1426 (define_expand "negsi2_h8300"
1427 [(set (match_dup 2)
1428 (not:SI (match_operand:SI 1 "register_operand" "")))
1429 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1430 (set (match_operand:SI 0 "register_operand" "")
1431 (match_dup 2))]
1432 ""
1433 "operands[2] = gen_reg_rtx (SImode);")
1434
1435 (define_insn "negsi2_h8300h"
1436 [(set (match_operand:SI 0 "register_operand" "=r")
1437 (neg:SI (match_operand:SI 1 "register_operand" "0")))]
1438 "TARGET_H8300H || TARGET_H8300S"
1439 "neg %S0"
1440 [(set_attr "length" "2")
1441 (set_attr "cc" "set_zn")])
1442
1443 (define_expand "negsf2"
1444 [(set (match_operand:SF 0 "register_operand" "")
1445 (neg:SF (match_operand:SF 1 "register_operand" "")))]
1446 ""
1447 "")
1448
1449 (define_insn "*negsf2_h8300"
1450 [(set (match_operand:SF 0 "register_operand" "=r")
1451 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1452 "TARGET_H8300"
1453 "xor.b\\t#128,%z0"
1454 [(set_attr "cc" "clobber")
1455 (set_attr "length" "2")])
1456
1457 (define_insn "*negsf2_h8300hs"
1458 [(set (match_operand:SF 0 "register_operand" "=r")
1459 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1460 "TARGET_H8300H || TARGET_H8300S"
1461 "xor.w\\t#32768,%e0"
1462 [(set_attr "cc" "clobber")
1463 (set_attr "length" "4")])
1464 \f
1465 ;; ----------------------------------------------------------------------
1466 ;; ABSOLUTE VALUE INSTRUCTIONS
1467 ;; ----------------------------------------------------------------------
1468
1469 (define_expand "abssf2"
1470 [(set (match_operand:SF 0 "register_operand" "")
1471 (abs:SF (match_operand:SF 1 "register_operand" "")))]
1472 ""
1473 "")
1474
1475 (define_insn "*abssf2_h8300"
1476 [(set (match_operand:SF 0 "register_operand" "=r")
1477 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1478 "TARGET_H8300"
1479 "and.b\\t#127,%z0"
1480 [(set_attr "cc" "clobber")
1481 (set_attr "length" "2")])
1482
1483 (define_insn "*abssf2_h8300hs"
1484 [(set (match_operand:SF 0 "register_operand" "=r")
1485 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1486 "TARGET_H8300H || TARGET_H8300S"
1487 "and.w\\t#32767,%e0"
1488 [(set_attr "cc" "clobber")
1489 (set_attr "length" "4")])
1490 \f
1491 ;; ----------------------------------------------------------------------
1492 ;; NOT INSTRUCTIONS
1493 ;; ----------------------------------------------------------------------
1494
1495 (define_insn "one_cmplqi2"
1496 [(set (match_operand:QI 0 "register_operand" "=r")
1497 (not:QI (match_operand:QI 1 "register_operand" "0")))]
1498 ""
1499 "not %X0"
1500 [(set_attr "length" "2")
1501 (set_attr "cc" "set_znv")])
1502
1503 (define_expand "one_cmplhi2"
1504 [(set (match_operand:HI 0 "register_operand" "=r")
1505 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1506 ""
1507 "")
1508
1509 (define_insn ""
1510 [(set (match_operand:HI 0 "register_operand" "=r")
1511 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1512 "TARGET_H8300"
1513 "not %s0\;not %t0"
1514 [(set_attr "cc" "clobber")
1515 (set_attr "length" "4")])
1516
1517 (define_insn ""
1518 [(set (match_operand:HI 0 "register_operand" "=r")
1519 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1520 "TARGET_H8300H || TARGET_H8300S"
1521 "not %T0"
1522 [(set_attr "cc" "set_znv")
1523 (set_attr "length" "2")])
1524
1525 (define_expand "one_cmplsi2"
1526 [(set (match_operand:SI 0 "register_operand" "=r")
1527 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1528 ""
1529 "")
1530
1531 (define_insn ""
1532 [(set (match_operand:SI 0 "register_operand" "=r")
1533 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1534 "TARGET_H8300"
1535 "not %w0\;not %x0\;not %y0\;not %z0"
1536 [(set_attr "cc" "clobber")
1537 (set_attr "length" "8")])
1538
1539 (define_insn ""
1540 [(set (match_operand:SI 0 "register_operand" "=r")
1541 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1542 "TARGET_H8300H || TARGET_H8300S"
1543 "not %S0"
1544 [(set_attr "cc" "set_znv")
1545 (set_attr "length" "2")])
1546 \f
1547 ;; ----------------------------------------------------------------------
1548 ;; JUMP INSTRUCTIONS
1549 ;; ----------------------------------------------------------------------
1550
1551 ;; Conditional jump instructions
1552
1553 (define_expand "ble"
1554 [(set (pc)
1555 (if_then_else (le (cc0)
1556 (const_int 0))
1557 (label_ref (match_operand 0 "" ""))
1558 (pc)))]
1559 ""
1560 "")
1561
1562 (define_expand "bleu"
1563 [(set (pc)
1564 (if_then_else (leu (cc0)
1565 (const_int 0))
1566 (label_ref (match_operand 0 "" ""))
1567 (pc)))]
1568 ""
1569 "")
1570
1571 (define_expand "bge"
1572 [(set (pc)
1573 (if_then_else (ge (cc0)
1574 (const_int 0))
1575 (label_ref (match_operand 0 "" ""))
1576 (pc)))]
1577 ""
1578 "")
1579
1580 (define_expand "bgeu"
1581 [(set (pc)
1582 (if_then_else (geu (cc0)
1583 (const_int 0))
1584 (label_ref (match_operand 0 "" ""))
1585 (pc)))]
1586 ""
1587 "")
1588
1589 (define_expand "blt"
1590 [(set (pc)
1591 (if_then_else (lt (cc0)
1592 (const_int 0))
1593 (label_ref (match_operand 0 "" ""))
1594 (pc)))]
1595 ""
1596 "")
1597
1598 (define_expand "bltu"
1599 [(set (pc)
1600 (if_then_else (ltu (cc0)
1601 (const_int 0))
1602 (label_ref (match_operand 0 "" ""))
1603 (pc)))]
1604 ""
1605 "")
1606
1607 (define_expand "bgt"
1608 [(set (pc)
1609 (if_then_else (gt (cc0)
1610 (const_int 0))
1611 (label_ref (match_operand 0 "" ""))
1612 (pc)))]
1613 ""
1614 "")
1615
1616 (define_expand "bgtu"
1617 [(set (pc)
1618 (if_then_else (gtu (cc0)
1619 (const_int 0))
1620 (label_ref (match_operand 0 "" ""))
1621 (pc)))]
1622 ""
1623 "")
1624
1625 (define_expand "beq"
1626 [(set (pc)
1627 (if_then_else (eq (cc0)
1628 (const_int 0))
1629 (label_ref (match_operand 0 "" ""))
1630 (pc)))]
1631 ""
1632 "")
1633
1634 (define_expand "bne"
1635 [(set (pc)
1636 (if_then_else (ne (cc0)
1637 (const_int 0))
1638 (label_ref (match_operand 0 "" ""))
1639 (pc)))]
1640 ""
1641 "")
1642
1643 (define_insn "branch_true"
1644 [(set (pc)
1645 (if_then_else (match_operator 1 "comparison_operator"
1646 [(cc0) (const_int 0)])
1647 (label_ref (match_operand 0 "" ""))
1648 (pc)))]
1649 ""
1650 "*
1651 {
1652 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1653 && (GET_CODE (operands[1]) == GT
1654 || GET_CODE (operands[1]) == GE
1655 || GET_CODE (operands[1]) == LE
1656 || GET_CODE (operands[1]) == LT))
1657 {
1658 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1659 return 0;
1660 }
1661
1662 if (get_attr_length (insn) == 2)
1663 return \"b%j1 %l0\";
1664 else if (get_attr_length (insn) == 4)
1665 return \"b%j1 %l0:16\";
1666 else
1667 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1668 }"
1669 [(set_attr "type" "branch")
1670 (set_attr "cc" "none")])
1671
1672 (define_insn "branch_false"
1673 [(set (pc)
1674 (if_then_else (match_operator 1 "comparison_operator"
1675 [(cc0) (const_int 0)])
1676 (pc)
1677 (label_ref (match_operand 0 "" ""))))]
1678 ""
1679 "*
1680 {
1681 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1682 && (GET_CODE (operands[1]) == GT
1683 || GET_CODE (operands[1]) == GE
1684 || GET_CODE (operands[1]) == LE
1685 || GET_CODE (operands[1]) == LT))
1686 {
1687 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1688 return 0;
1689 }
1690
1691 if (get_attr_length (insn) == 2)
1692 return \"b%k1 %l0\";
1693 else if (get_attr_length (insn) == 4)
1694 return \"b%k1 %l0:16\";
1695 else
1696 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1697 }"
1698 [(set_attr "type" "branch")
1699 (set_attr "cc" "none")])
1700
1701 ;; Unconditional and other jump instructions.
1702
1703 (define_insn "jump"
1704 [(set (pc)
1705 (label_ref (match_operand 0 "" "")))]
1706 ""
1707 "*
1708 {
1709 if (get_attr_length (insn) == 2)
1710 return \"bra %l0\";
1711 else if (get_attr_length (insn) == 4)
1712 return \"bra %l0:16\";
1713 else
1714 return \"jmp @%l0\";
1715 }"
1716 [(set_attr "type" "branch")
1717 (set_attr "cc" "none")])
1718
1719 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1720
1721 (define_expand "tablejump"
1722 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
1723 (use (label_ref (match_operand 1 "" "")))])]
1724 ""
1725 "")
1726
1727 (define_insn "tablejump_h8300"
1728 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1729 (use (label_ref (match_operand 1 "" "")))]
1730 "TARGET_H8300"
1731 "jmp @%0"
1732 [(set_attr "cc" "none")
1733 (set_attr "length" "2")])
1734
1735 (define_insn "tablejump_h8300h"
1736 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1737 (use (label_ref (match_operand 1 "" "")))]
1738 "TARGET_H8300H || TARGET_H8300S"
1739 "jmp @%0"
1740 [(set_attr "cc" "none")
1741 (set_attr "length" "2")])
1742
1743 (define_insn "tablejump_normal_mode"
1744 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1745 (use (label_ref (match_operand 1 "" "")))]
1746 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1747 "jmp @%S0"
1748 [(set_attr "cc" "none")
1749 (set_attr "length" "2")])
1750
1751 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1752
1753 (define_expand "indirect_jump"
1754 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1755 ""
1756 "")
1757
1758 (define_insn "indirect_jump_h8300"
1759 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1760 "TARGET_H8300"
1761 "jmp @%0"
1762 [(set_attr "cc" "none")
1763 (set_attr "length" "2")])
1764
1765 (define_insn "indirect_jump_h8300h"
1766 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1767 "TARGET_H8300H || TARGET_H8300S"
1768 "jmp @%0"
1769 [(set_attr "cc" "none")
1770 (set_attr "length" "2")])
1771
1772 (define_insn "indirect_jump_normal_mode"
1773 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1774 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1775 "jmp @%S0"
1776 [(set_attr "cc" "none")
1777 (set_attr "length" "2")])
1778
1779 ;; Call subroutine with no return value.
1780
1781 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1782
1783 (define_insn "call"
1784 [(call (match_operand:QI 0 "call_insn_operand" "or")
1785 (match_operand:HI 1 "general_operand" "g"))]
1786 ""
1787 "*
1788 {
1789 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1790 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1791 return \"jsr\\t@%0:8\";
1792 else
1793 return \"jsr\\t%0\";
1794 }"
1795 [(set_attr "cc" "clobber")
1796 (set (attr "length")
1797 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1798 (const_int 2)
1799 (const_int 4)))])
1800
1801 ;; Call subroutine, returning value in operand 0
1802 ;; (which must be a hard register).
1803
1804 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1805
1806 (define_insn "call_value"
1807 [(set (match_operand 0 "" "=r")
1808 (call (match_operand:QI 1 "call_insn_operand" "or")
1809 (match_operand:HI 2 "general_operand" "g")))]
1810 ""
1811 "*
1812 {
1813 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1814 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1815 return \"jsr\\t@%1:8\";
1816 else
1817 return \"jsr\\t%1\";
1818 }"
1819 [(set_attr "cc" "clobber")
1820 (set (attr "length")
1821 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1822 (const_int 2)
1823 (const_int 4)))])
1824
1825 (define_insn "nop"
1826 [(const_int 0)]
1827 ""
1828 "nop"
1829 [(set_attr "cc" "none")
1830 (set_attr "length" "2")])
1831 \f
1832 ;; ----------------------------------------------------------------------
1833 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
1834 ;; ----------------------------------------------------------------------
1835
1836 (define_expand "push_h8300"
1837 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
1838 (match_operand:HI 0 "register_operand" "=r"))]
1839
1840 "TARGET_H8300"
1841 "")
1842
1843 (define_expand "push_h8300hs"
1844 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
1845 (match_operand:SI 0 "register_operand" "=r"))]
1846 "TARGET_H8300H && TARGET_H8300S"
1847 "")
1848
1849 (define_expand "pop_h8300"
1850 [(set (match_operand:HI 0 "register_operand" "=r")
1851 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
1852 "TARGET_H8300"
1853 "")
1854
1855 (define_expand "pop_h8300hs"
1856 [(set (match_operand:SI 0 "register_operand" "=r")
1857 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
1858 "TARGET_H8300H && TARGET_H8300S"
1859 "")
1860
1861 (define_insn "stm_h8300s_2"
1862 [(parallel
1863 [(set (reg:SI SP_REG)
1864 (plus:SI (reg:SI SP_REG) (const_int -8)))
1865 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1866 (match_operand:SI 0 "register_operand" ""))
1867 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1868 (match_operand:SI 1 "register_operand" ""))])]
1869 "TARGET_H8300S
1870 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
1871 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
1872 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
1873 "stm.l\\t%S0-%S1,@-er7"
1874 [(set_attr "cc" "none")
1875 (set_attr "length" "4")])
1876
1877 (define_insn "stm_h8300s_3"
1878 [(parallel
1879 [(set (reg:SI SP_REG)
1880 (plus:SI (reg:SI SP_REG) (const_int -12)))
1881 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1882 (match_operand:SI 0 "register_operand" ""))
1883 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1884 (match_operand:SI 1 "register_operand" ""))
1885 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1886 (match_operand:SI 2 "register_operand" ""))])]
1887 "TARGET_H8300S
1888 && ((REGNO (operands[0]) == 0
1889 && REGNO (operands[1]) == 1
1890 && REGNO (operands[2]) == 2)
1891 || (REGNO (operands[0]) == 4
1892 && REGNO (operands[1]) == 5
1893 && REGNO (operands[2]) == 6))"
1894 "stm.l\\t%S0-%S2,@-er7"
1895 [(set_attr "cc" "none")
1896 (set_attr "length" "4")])
1897
1898 (define_insn "stm_h8300s_4"
1899 [(parallel
1900 [(set (reg:SI SP_REG)
1901 (plus:SI (reg:SI SP_REG) (const_int -16)))
1902 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1903 (match_operand:SI 0 "register_operand" ""))
1904 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1905 (match_operand:SI 1 "register_operand" ""))
1906 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1907 (match_operand:SI 2 "register_operand" ""))
1908 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
1909 (match_operand:SI 3 "register_operand" ""))])]
1910 "TARGET_H8300S
1911 && REGNO (operands[0]) == 0
1912 && REGNO (operands[1]) == 1
1913 && REGNO (operands[2]) == 2
1914 && REGNO (operands[3]) == 3"
1915 "stm.l\\t%S0-%S3,@-er7"
1916 [(set_attr "cc" "none")
1917 (set_attr "length" "4")])
1918
1919 (define_insn "ldm_h8300s_2"
1920 [(parallel
1921 [(set (reg:SI SP_REG)
1922 (plus:SI (reg:SI SP_REG) (const_int 8)))
1923 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
1924 (match_operand:SI 0 "register_operand" ""))
1925 (set (mem:SI (reg:SI SP_REG))
1926 (match_operand:SI 1 "register_operand" ""))])]
1927 "TARGET_H8300S
1928 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
1929 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
1930 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
1931 "ldm.l\\t@er7+,%S0-%S1"
1932 [(set_attr "cc" "none")
1933 (set_attr "length" "4")])
1934
1935 (define_insn "ldm_h8300s_3"
1936 [(parallel
1937 [(set (reg:SI SP_REG)
1938 (plus:SI (reg:SI SP_REG) (const_int 12)))
1939 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
1940 (match_operand:SI 0 "register_operand" ""))
1941 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
1942 (match_operand:SI 1 "register_operand" ""))
1943 (set (mem:SI (reg:SI SP_REG))
1944 (match_operand:SI 2 "register_operand" ""))])]
1945 "TARGET_H8300S
1946 && ((REGNO (operands[0]) == 0
1947 && REGNO (operands[1]) == 1
1948 && REGNO (operands[2]) == 2)
1949 || (REGNO (operands[0]) == 4
1950 && REGNO (operands[1]) == 5
1951 && REGNO (operands[2]) == 6))"
1952 "ldm.l\\t@er7+,%S0-%S2"
1953 [(set_attr "cc" "none")
1954 (set_attr "length" "4")])
1955
1956 (define_insn "ldm_h8300s_4"
1957 [(parallel
1958 [(set (reg:SI SP_REG)
1959 (plus:SI (reg:SI SP_REG) (const_int 16)))
1960 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 12)))
1961 (match_operand:SI 0 "register_operand" ""))
1962 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
1963 (match_operand:SI 1 "register_operand" ""))
1964 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
1965 (match_operand:SI 2 "register_operand" ""))
1966 (set (mem:SI (reg:SI SP_REG))
1967 (match_operand:SI 3 "register_operand" ""))])]
1968 "TARGET_H8300S
1969 && REGNO (operands[0]) == 0
1970 && REGNO (operands[1]) == 1
1971 && REGNO (operands[2]) == 2
1972 && REGNO (operands[3]) == 3"
1973 "ldm.l\\t@er7+,%S0-%S3"
1974 [(set_attr "cc" "none")
1975 (set_attr "length" "4")])
1976
1977 (define_expand "return"
1978 [(return)]
1979 "h8300_can_use_return_insn_p ()"
1980 "")
1981
1982 (define_insn "*return_1"
1983 [(return)]
1984 "reload_completed"
1985 "*
1986 {
1987 if (h8300_current_function_interrupt_function_p ())
1988 return \"rte\";
1989 else
1990 return \"rts\";
1991 }"
1992 [(set_attr "cc" "none")
1993 (set_attr "length" "2")])
1994
1995 (define_expand "prologue"
1996 [(const_int 0)]
1997 ""
1998 "h8300_expand_prologue (); DONE;")
1999
2000 (define_expand "epilogue"
2001 [(return)]
2002 ""
2003 "h8300_expand_epilogue ();")
2004
2005 (define_insn "monitor_prologue"
2006 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2007 ""
2008 "*
2009 {
2010 if (TARGET_H8300)
2011 return \"subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr\";
2012 else if (TARGET_H8300H)
2013 return \"mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr\";
2014 else if (TARGET_H8300S)
2015 return \"stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\";
2016 abort ();
2017 }"
2018 [(set_attr "length" "20")
2019 (set_attr "cc" "clobber")])
2020 \f
2021 ;; ----------------------------------------------------------------------
2022 ;; EXTEND INSTRUCTIONS
2023 ;; ----------------------------------------------------------------------
2024
2025 (define_expand "zero_extendqihi2"
2026 [(set (match_operand:HI 0 "register_operand" "")
2027 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2028 ""
2029 "")
2030
2031 (define_insn "*zero_extendqihi2_h8300"
2032 [(set (match_operand:HI 0 "register_operand" "=r,r")
2033 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2034 "TARGET_H8300"
2035 "@
2036 mov.b #0,%t0
2037 #"
2038 [(set_attr "length" "2,10")
2039 (set_attr "cc" "clobber,clobber")])
2040
2041 (define_insn "*zero_extendqihi2_h8300hs"
2042 [(set (match_operand:HI 0 "register_operand" "=r,r")
2043 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2044 "TARGET_H8300H || TARGET_H8300S"
2045 "@
2046 extu.w %T0
2047 #"
2048 [(set_attr "length" "2,10")
2049 (set_attr "cc" "set_znv,set_znv")])
2050
2051 ;; Split the zero extension of a general operand (actually a memory
2052 ;; operand) into a load of the operand and the actual zero extension
2053 ;; so that 1) the length will be accurate, and 2) the zero extensions
2054 ;; appearing at the end of basic blocks may be merged.
2055
2056 (define_split
2057 [(set (match_operand:HI 0 "register_operand" "")
2058 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2059 "reload_completed"
2060 [(set (match_dup 2)
2061 (match_dup 1))
2062 (set (match_dup 0)
2063 (zero_extend:HI (match_dup 2)))]
2064 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2065
2066 (define_expand "zero_extendqisi2"
2067 [(set (match_operand:SI 0 "register_operand" "")
2068 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2069 ""
2070 "")
2071
2072 (define_insn "*zero_extendqisi2_h8300"
2073 [(set (match_operand:SI 0 "register_operand" "=r,r")
2074 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2075 "TARGET_H8300"
2076 "@
2077 mov.b #0,%x0\;sub.w %e0,%e0
2078 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
2079 [(set_attr "length" "4,8")
2080 (set_attr "cc" "clobber,clobber")])
2081
2082 (define_insn "*zero_extendqisi2_h8300hs"
2083 [(set (match_operand:SI 0 "register_operand" "=r,r")
2084 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2085 "TARGET_H8300H || TARGET_H8300S"
2086 "#")
2087
2088 (define_split
2089 [(set (match_operand:SI 0 "register_operand" "")
2090 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2091 "(TARGET_H8300H || TARGET_H8300S)
2092 && reg_overlap_mentioned_p (operands[0], operands[1])
2093 && reload_completed"
2094 [(set (match_dup 2)
2095 (match_dup 1))
2096 (set (match_dup 3)
2097 (zero_extend:HI (match_dup 2)))
2098 (set (match_dup 0)
2099 (zero_extend:SI (match_dup 3)))]
2100 "operands[2] = gen_lowpart (QImode, operands[0]);
2101 operands[3] = gen_lowpart (HImode, operands[0]);")
2102
2103 (define_split
2104 [(set (match_operand:SI 0 "register_operand" "")
2105 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2106 "(TARGET_H8300H || TARGET_H8300S)
2107 && !reg_overlap_mentioned_p (operands[0], operands[1])
2108 && reload_completed"
2109 [(set (match_dup 0)
2110 (const_int 0))
2111 (set (strict_low_part (match_dup 2))
2112 (match_dup 1))]
2113 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2114
2115 (define_expand "zero_extendhisi2"
2116 [(set (match_operand:SI 0 "register_operand" "")
2117 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2118 ""
2119 "")
2120
2121 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
2122 (define_insn "*zero_extendhisi2_h8300"
2123 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2124 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
2125 "TARGET_H8300"
2126 "@
2127 sub.w %e0,%e0
2128 mov.w %f1,%f0\;sub.w %e0,%e0
2129 mov.w %e1,%f0\;sub.w %e0,%e0"
2130 [(set_attr "length" "2,4,6")
2131 (set_attr "cc" "clobber,clobber,clobber")])
2132
2133 (define_insn ""
2134 [(set (match_operand:SI 0 "register_operand" "=r")
2135 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2136 "TARGET_H8300H || TARGET_H8300S"
2137 "extu.l %S0"
2138 [(set_attr "length" "2")
2139 (set_attr "cc" "set_znv")])
2140
2141 (define_expand "extendqihi2"
2142 [(set (match_operand:HI 0 "register_operand" "")
2143 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
2144 ""
2145 "")
2146
2147 (define_insn ""
2148 [(set (match_operand:HI 0 "register_operand" "=r,r")
2149 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2150 "TARGET_H8300"
2151 "@
2152 bld #7,%s0\;subx %t0,%t0
2153 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
2154 [(set_attr "length" "4,8")
2155 (set_attr "cc" "clobber,clobber")])
2156
2157 (define_insn ""
2158 [(set (match_operand:HI 0 "register_operand" "=r")
2159 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
2160 "TARGET_H8300H || TARGET_H8300S"
2161 "exts.w %T0"
2162 [(set_attr "length" "2")
2163 (set_attr "cc" "set_znv")])
2164
2165 (define_expand "extendqisi2"
2166 [(set (match_operand:SI 0 "register_operand" "=r,r")
2167 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2168 ""
2169 "")
2170
2171 (define_insn "*extendqisi2_h8300"
2172 [(set (match_operand:SI 0 "register_operand" "")
2173 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2174 "TARGET_H8300"
2175 "@
2176 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
2177 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
2178 [(set_attr "length" "8,12")
2179 (set_attr "cc" "clobber,clobber")])
2180
2181 ;; The following pattern is needed because without the pattern, the
2182 ;; combiner would split (sign_extend:SI (reg:QI)) into into two 24-bit
2183 ;; shifts, one ashift and one ashiftrt.
2184
2185 (define_insn_and_split "*extendqisi2_h8300hs"
2186 [(set (match_operand:SI 0 "register_operand" "=r")
2187 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2188 "(TARGET_H8300H || TARGET_H8300S)"
2189 "#"
2190 "&& reload_completed"
2191 [(set (match_dup 2)
2192 (sign_extend:HI (match_dup 1)))
2193 (set (match_dup 0)
2194 (sign_extend:SI (match_dup 2)))]
2195 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2196
2197 (define_expand "extendhisi2"
2198 [(set (match_operand:SI 0 "register_operand" "")
2199 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2200 ""
2201 "")
2202
2203 (define_insn "*extendhisi2_h8300"
2204 [(set (match_operand:SI 0 "register_operand" "=r,r")
2205 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
2206 "TARGET_H8300"
2207 "@
2208 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
2209 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
2210 [(set_attr "length" "6,10")
2211 (set_attr "cc" "clobber,clobber")])
2212
2213 (define_insn ""
2214 [(set (match_operand:SI 0 "register_operand" "=r")
2215 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2216 "TARGET_H8300H || TARGET_H8300S"
2217 "exts.l %S0"
2218 [(set_attr "length" "2")
2219 (set_attr "cc" "set_znv")])
2220 \f
2221 ;; ----------------------------------------------------------------------
2222 ;; SHIFTS
2223 ;; ----------------------------------------------------------------------
2224 ;;
2225 ;; We make some attempt to provide real efficient shifting. One example is
2226 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
2227 ;; reg and moving 0 into the former reg.
2228 ;;
2229 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2230 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2231 ;; give the optimizer more cracks at the code. However, we wish to do things
2232 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
2233 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
2234 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
2235 ;; to detect cases it can optimize.
2236 ;;
2237 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2238 ;; easier "do it at insn emit time" route.
2239
2240 ;; QI BIT SHIFTS
2241
2242 (define_expand "ashlqi3"
2243 [(set (match_operand:QI 0 "register_operand" "")
2244 (ashift:QI (match_operand:QI 1 "register_operand" "")
2245 (match_operand:QI 2 "nonmemory_operand" "")))]
2246 ""
2247 "expand_a_shift (QImode, ASHIFT, operands); DONE;")
2248
2249 (define_expand "ashrqi3"
2250 [(set (match_operand:QI 0 "register_operand" "")
2251 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2252 (match_operand:QI 2 "nonmemory_operand" "")))]
2253 ""
2254 "expand_a_shift (QImode, ASHIFTRT, operands); DONE;")
2255
2256 (define_expand "lshrqi3"
2257 [(set (match_operand:QI 0 "register_operand" "")
2258 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2259 (match_operand:QI 2 "nonmemory_operand" "")))]
2260 ""
2261 "expand_a_shift (QImode, LSHIFTRT, operands); DONE;")
2262
2263 (define_insn ""
2264 [(set (match_operand:QI 0 "register_operand" "=r,r")
2265 (match_operator:QI 3 "nshift_operator"
2266 [ (match_operand:QI 1 "register_operand" "0,0")
2267 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2268 (clobber (match_scratch:QI 4 "=X,&r"))]
2269 ""
2270 "* return output_a_shift (operands);"
2271 [(set (attr "length")
2272 (symbol_ref "compute_a_shift_length (insn, operands)"))
2273 (set (attr "cc")
2274 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2275
2276 ;; HI BIT SHIFTS
2277
2278 (define_expand "ashlhi3"
2279 [(set (match_operand:HI 0 "register_operand" "")
2280 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
2281 (match_operand:QI 2 "nonmemory_operand" "")))]
2282 ""
2283 "expand_a_shift (HImode, ASHIFT, operands); DONE;")
2284
2285 (define_expand "lshrhi3"
2286 [(set (match_operand:HI 0 "register_operand" "")
2287 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
2288 (match_operand:QI 2 "nonmemory_operand" "")))]
2289 ""
2290 "expand_a_shift (HImode, LSHIFTRT, operands); DONE;")
2291
2292 (define_expand "ashrhi3"
2293 [(set (match_operand:HI 0 "register_operand" "")
2294 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
2295 (match_operand:QI 2 "nonmemory_operand" "")))]
2296 ""
2297 "expand_a_shift (HImode, ASHIFTRT, operands); DONE;")
2298
2299 (define_insn ""
2300 [(set (match_operand:HI 0 "register_operand" "=r,r")
2301 (match_operator:HI 3 "nshift_operator"
2302 [ (match_operand:HI 1 "register_operand" "0,0")
2303 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
2304 (clobber (match_scratch:QI 4 "=X,&r"))]
2305 ""
2306 "* return output_a_shift (operands);"
2307 [(set (attr "length")
2308 (symbol_ref "compute_a_shift_length (insn, operands)"))
2309 (set (attr "cc")
2310 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2311
2312 ;; SI BIT SHIFTS
2313
2314 (define_expand "ashlsi3"
2315 [(set (match_operand:SI 0 "register_operand" "")
2316 (ashift:SI (match_operand:SI 1 "general_operand" "")
2317 (match_operand:QI 2 "nonmemory_operand" "")))]
2318 ""
2319 "expand_a_shift (SImode, ASHIFT, operands); DONE;")
2320
2321 (define_expand "lshrsi3"
2322 [(set (match_operand:SI 0 "register_operand" "")
2323 (lshiftrt:SI (match_operand:SI 1 "general_operand" "")
2324 (match_operand:QI 2 "nonmemory_operand" "")))]
2325 ""
2326 "expand_a_shift (SImode, LSHIFTRT, operands); DONE;")
2327
2328 (define_expand "ashrsi3"
2329 [(set (match_operand:SI 0 "register_operand" "")
2330 (ashiftrt:SI (match_operand:SI 1 "general_operand" "")
2331 (match_operand:QI 2 "nonmemory_operand" "")))]
2332 ""
2333 "expand_a_shift (SImode, ASHIFTRT, operands); DONE;")
2334
2335 (define_insn ""
2336 [(set (match_operand:SI 0 "register_operand" "=r,r")
2337 (match_operator:SI 3 "nshift_operator"
2338 [ (match_operand:SI 1 "register_operand" "0,0")
2339 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
2340 (clobber (match_scratch:QI 4 "=X,&r"))]
2341 ""
2342 "* return output_a_shift (operands);"
2343 [(set (attr "length")
2344 (symbol_ref "compute_a_shift_length (insn, operands)"))
2345 (set (attr "cc")
2346 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2347
2348 ;; Split a variable shift into a loop. If the register containing
2349 ;; the shift count dies, then we just use that register.
2350
2351 (define_split
2352 [(parallel
2353 [(set (match_operand 0 "register_operand" "")
2354 (match_operator 2 "nshift_operator"
2355 [(match_dup 0)
2356 (match_operand:QI 1 "register_operand" "")]))
2357 (clobber (match_operand:QI 3 "register_operand" ""))])]
2358 "flow2_completed
2359 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2360 [(set (cc0)
2361 (match_dup 1))
2362 (set (pc)
2363 (if_then_else (le (cc0) (const_int 0))
2364 (label_ref (match_dup 5))
2365 (pc)))
2366 (match_dup 4)
2367 (parallel
2368 [(set (match_dup 0)
2369 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2370 (clobber (scratch:QI))])
2371 (set (match_dup 1)
2372 (plus:QI (match_dup 1) (const_int -1)))
2373 (set (cc0)
2374 (match_dup 1))
2375 (set (pc)
2376 (if_then_else (ne (cc0) (const_int 0))
2377 (label_ref (match_dup 4))
2378 (pc)))
2379 (match_dup 5)]
2380 "operands[4] = gen_label_rtx ();
2381 operands[5] = gen_label_rtx ();")
2382
2383 (define_split
2384 [(parallel
2385 [(set (match_operand 0 "register_operand" "")
2386 (match_operator 2 "nshift_operator"
2387 [(match_dup 0)
2388 (match_operand:QI 1 "register_operand" "")]))
2389 (clobber (match_operand:QI 3 "register_operand" ""))])]
2390 "flow2_completed
2391 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2392 [(set (match_dup 3)
2393 (match_dup 1))
2394 (set (cc0)
2395 (match_dup 3))
2396 (set (pc)
2397 (if_then_else (le (cc0) (const_int 0))
2398 (label_ref (match_dup 5))
2399 (pc)))
2400 (match_dup 4)
2401 (parallel
2402 [(set (match_dup 0)
2403 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2404 (clobber (scratch:QI))])
2405 (set (match_dup 3)
2406 (plus:QI (match_dup 3) (const_int -1)))
2407 (set (cc0)
2408 (match_dup 3))
2409 (set (pc)
2410 (if_then_else (ne (cc0) (const_int 0))
2411 (label_ref (match_dup 4))
2412 (pc)))
2413 (match_dup 5)]
2414 "operands[4] = gen_label_rtx ();
2415 operands[5] = gen_label_rtx ();")
2416 \f
2417 ;; ----------------------------------------------------------------------
2418 ;; ROTATIONS
2419 ;; ----------------------------------------------------------------------
2420
2421 (define_expand "rotlqi3"
2422 [(set (match_operand:QI 0 "register_operand" "")
2423 (rotate:QI (match_operand:QI 1 "register_operand" "")
2424 (match_operand:QI 2 "nonmemory_operand" "")))]
2425 ""
2426 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2427
2428 (define_insn "*rotlqi3_1"
2429 [(set (match_operand:QI 0 "register_operand" "=r")
2430 (rotate:QI (match_operand:QI 1 "register_operand" "0")
2431 (match_operand:QI 2 "immediate_operand" "")))]
2432 ""
2433 "* return output_a_rotate (ROTATE, operands);"
2434 [(set (attr "length")
2435 (symbol_ref "compute_a_rotate_length (operands)"))
2436 (set_attr "cc" "clobber")])
2437
2438 (define_expand "rotlhi3"
2439 [(set (match_operand:HI 0 "register_operand" "")
2440 (rotate:HI (match_operand:HI 1 "register_operand" "")
2441 (match_operand:QI 2 "nonmemory_operand" "")))]
2442 ""
2443 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2444
2445 (define_insn "*rotlhi3_1"
2446 [(set (match_operand:HI 0 "register_operand" "=r")
2447 (rotate:HI (match_operand:HI 1 "register_operand" "0")
2448 (match_operand:QI 2 "immediate_operand" "")))]
2449 ""
2450 "* return output_a_rotate (ROTATE, operands);"
2451 [(set (attr "length")
2452 (symbol_ref "compute_a_rotate_length (operands)"))
2453 (set_attr "cc" "clobber")])
2454
2455 (define_expand "rotlsi3"
2456 [(set (match_operand:SI 0 "register_operand" "")
2457 (rotate:SI (match_operand:SI 1 "register_operand" "")
2458 (match_operand:QI 2 "nonmemory_operand" "")))]
2459 "TARGET_H8300H || TARGET_H8300S"
2460 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2461
2462 (define_insn "*rotlsi3_1"
2463 [(set (match_operand:SI 0 "register_operand" "=r")
2464 (rotate:SI (match_operand:SI 1 "register_operand" "0")
2465 (match_operand:QI 2 "immediate_operand" "")))]
2466 "TARGET_H8300H || TARGET_H8300S"
2467 "* return output_a_rotate (ROTATE, operands);"
2468 [(set (attr "length")
2469 (symbol_ref "compute_a_rotate_length (operands)"))
2470 (set_attr "cc" "clobber")])
2471 \f
2472 ;; -----------------------------------------------------------------
2473 ;; BIT FIELDS
2474 ;; -----------------------------------------------------------------
2475 ;; The H8/300 has given 1/8th of its opcode space to bitfield
2476 ;; instructions so let's use them as well as we can.
2477
2478 ;; You'll never believe all these patterns perform one basic action --
2479 ;; load a bit from the source, optionally invert the bit, then store it
2480 ;; in the destination (which is known to be zero).
2481 ;;
2482 ;; Combine obviously need some work to better identify this situation and
2483 ;; canonicalize the form better.
2484
2485 ;;
2486 ;; Normal loads with a 16bit destination.
2487 ;;
2488
2489 (define_insn ""
2490 [(set (match_operand:HI 0 "register_operand" "=&r")
2491 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2492 (const_int 1)
2493 (match_operand:HI 2 "immediate_operand" "n")))]
2494 "TARGET_H8300"
2495 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
2496 [(set_attr "cc" "clobber")
2497 (set_attr "length" "6")])
2498
2499 ;;
2500 ;; Inverted loads with a 16bit destination.
2501 ;;
2502
2503 (define_insn ""
2504 [(set (match_operand:HI 0 "register_operand" "=&r")
2505 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
2506 (match_operand:HI 3 "const_int_operand" "n"))
2507 (const_int 1)
2508 (match_operand:HI 2 "const_int_operand" "n")))]
2509 "TARGET_H8300
2510 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2511 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2512 [(set_attr "cc" "clobber")
2513 (set_attr "length" "8")])
2514
2515 ;;
2516 ;; Normal loads with a 32bit destination.
2517 ;;
2518
2519 (define_insn "*extzv_1_r_h8300"
2520 [(set (match_operand:SI 0 "register_operand" "=&r")
2521 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2522 (const_int 1)
2523 (match_operand 2 "const_int_operand" "n")))]
2524 "TARGET_H8300
2525 && INTVAL (operands[2]) < 16"
2526 "* return output_simode_bld (0, operands);"
2527 [(set_attr "cc" "clobber")
2528 (set_attr "length" "8")])
2529
2530 (define_insn "*extzv_1_r_h8300hs"
2531 [(set (match_operand:SI 0 "register_operand" "=r,r")
2532 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2533 (const_int 1)
2534 (match_operand 2 "const_int_operand" "n,n")))]
2535 "(TARGET_H8300H || TARGET_H8300S)
2536 && INTVAL (operands[2]) < 16"
2537 "* return output_simode_bld (0, operands);"
2538 [(set_attr "cc" "set_znv,set_znv")
2539 (set_attr "length" "8,6")])
2540
2541 ;;
2542 ;; Inverted loads with a 32bit destination.
2543 ;;
2544
2545 (define_insn "*extzv_1_r_inv_h8300"
2546 [(set (match_operand:SI 0 "register_operand" "=&r")
2547 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2548 (match_operand:HI 3 "const_int_operand" "n"))
2549 (const_int 1)
2550 (match_operand 2 "const_int_operand" "n")))]
2551 "TARGET_H8300
2552 && INTVAL (operands[2]) < 16
2553 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2554 "* return output_simode_bld (1, operands);"
2555 [(set_attr "cc" "clobber")
2556 (set_attr "length" "8")])
2557
2558 (define_insn "*extzv_1_r_inv_h8300hs"
2559 [(set (match_operand:SI 0 "register_operand" "=r,r")
2560 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
2561 (match_operand 3 "const_int_operand" "n,n"))
2562 (const_int 1)
2563 (match_operand 2 "const_int_operand" "n,n")))]
2564 "(TARGET_H8300H || TARGET_H8300S)
2565 && INTVAL (operands[2]) < 16
2566 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2567 "* return output_simode_bld (1, operands);"
2568 [(set_attr "cc" "set_znv,set_znv")
2569 (set_attr "length" "8,6")])
2570
2571 (define_expand "insv"
2572 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2573 (match_operand:HI 1 "general_operand" "")
2574 (match_operand:HI 2 "general_operand" ""))
2575 (match_operand:HI 3 "general_operand" ""))]
2576 "TARGET_H8300"
2577 "
2578 {
2579 /* We only have single bit bit-field instructions. */
2580 if (INTVAL (operands[1]) != 1)
2581 FAIL;
2582
2583 /* For now, we don't allow memory operands. */
2584 if (GET_CODE (operands[0]) == MEM
2585 || GET_CODE (operands[3]) == MEM)
2586 FAIL;
2587 }")
2588
2589 (define_insn ""
2590 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2591 (const_int 1)
2592 (match_operand:HI 1 "immediate_operand" "n"))
2593 (match_operand:HI 2 "register_operand" "r"))]
2594 ""
2595 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2596 [(set_attr "cc" "clobber")
2597 (set_attr "length" "4")])
2598
2599 (define_expand "extzv"
2600 [(set (match_operand:HI 0 "register_operand" "")
2601 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2602 (match_operand:HI 2 "general_operand" "")
2603 (match_operand:HI 3 "general_operand" "")))]
2604 "TARGET_H8300"
2605 "
2606 {
2607 /* We only have single bit bit-field instructions. */
2608 if (INTVAL (operands[2]) != 1)
2609 FAIL;
2610
2611 /* For now, we don't allow memory operands. */
2612 if (GET_CODE (operands[1]) == MEM)
2613 FAIL;
2614 }")
2615
2616 ;; BAND, BOR, and BXOR patterns
2617
2618 (define_insn ""
2619 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2620 (match_operator:HI 4 "bit_operator"
2621 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2622 (const_int 1)
2623 (match_operand:HI 2 "immediate_operand" "n"))
2624 (match_operand:HI 3 "bit_operand" "0")]))]
2625 ""
2626 "bld %Z2,%Y1\;b%c4 #0,%R0\;bst #0,%R0; bl1"
2627 [(set_attr "cc" "clobber")
2628 (set_attr "length" "6")])
2629
2630 (define_insn ""
2631 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2632 (match_operator:HI 5 "bit_operator"
2633 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2634 (const_int 1)
2635 (match_operand:HI 2 "immediate_operand" "n"))
2636 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2637 (const_int 1)
2638 (match_operand:HI 4 "immediate_operand" "n"))]))]
2639 ""
2640 "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #0,%R0; bl3"
2641 [(set_attr "cc" "clobber")
2642 (set_attr "length" "6")])
2643 \f
2644 ;; -----------------------------------------------------------------
2645 ;; COMBINE PATTERNS
2646 ;; -----------------------------------------------------------------
2647
2648 ;; insv:SI
2649
2650 (define_insn "*insv_si_1_n"
2651 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2652 (const_int 1)
2653 (match_operand:SI 1 "const_int_operand" "n"))
2654 (match_operand:SI 2 "register_operand" "r"))]
2655 "(TARGET_H8300H || TARGET_H8300S)
2656 && INTVAL (operands[1]) < 16"
2657 "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
2658 [(set_attr "cc" "clobber")
2659 (set_attr "length" "4")])
2660
2661 (define_insn "*insv_si_1_n_lshiftrt"
2662 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2663 (const_int 1)
2664 (match_operand:SI 1 "const_int_operand" "n"))
2665 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2666 (match_operand:SI 3 "const_int_operand" "n")))]
2667 "(TARGET_H8300H || TARGET_H8300S)
2668 && INTVAL (operands[1]) < 16
2669 && INTVAL (operands[3]) < 16"
2670 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
2671 [(set_attr "cc" "clobber")
2672 (set_attr "length" "4")])
2673
2674 (define_insn "*insv_si_1_n_lshiftrt_16"
2675 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2676 (const_int 1)
2677 (match_operand:SI 1 "const_int_operand" "n"))
2678 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2679 (const_int 16)))]
2680 "(TARGET_H8300H || TARGET_H8300S)
2681 && INTVAL (operands[1]) < 16"
2682 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
2683 [(set_attr "cc" "clobber")
2684 (set_attr "length" "6")])
2685
2686 (define_insn "*insv_si_8_8"
2687 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2688 (const_int 8)
2689 (const_int 8))
2690 (match_operand:SI 1 "register_operand" "r"))]
2691 "TARGET_H8300H || TARGET_H8300S"
2692 "mov.b\\t%w1,%x0"
2693 [(set_attr "cc" "clobber")
2694 (set_attr "length" "2")])
2695
2696 (define_insn "*insv_si_8_8_lshiftrt_8"
2697 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2698 (const_int 8)
2699 (const_int 8))
2700 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2701 (const_int 8)))]
2702 "TARGET_H8300H || TARGET_H8300S"
2703 "mov.b\\t%x1,%x0"
2704 [(set_attr "cc" "clobber")
2705 (set_attr "length" "2")])
2706
2707 ;; extzv:SI
2708
2709 (define_insn "*extzv_8_8"
2710 [(set (match_operand:SI 0 "register_operand" "=r,r")
2711 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2712 (const_int 8)
2713 (const_int 8)))]
2714 "TARGET_H8300H || TARGET_H8300S"
2715 "@
2716 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
2717 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
2718 [(set_attr "cc" "set_znv,clobber")
2719 (set_attr "length" "6,4")])
2720
2721 (define_insn "*extzv_8_16"
2722 [(set (match_operand:SI 0 "register_operand" "=r")
2723 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2724 (const_int 8)
2725 (const_int 16)))]
2726 "TARGET_H8300H || TARGET_H8300S"
2727 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
2728 [(set_attr "cc" "set_znv")
2729 (set_attr "length" "6")])
2730
2731 (define_insn "*extzv_16_8"
2732 [(set (match_operand:SI 0 "register_operand" "=r")
2733 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2734 (const_int 16)
2735 (const_int 8)))
2736 (clobber (match_scratch:SI 2 "=&r"))]
2737 "TARGET_H8300H"
2738 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
2739 [(set_attr "length" "8")
2740 (set_attr "cc" "set_znv")])
2741
2742 ;; Extract the exponent of a float.
2743
2744 (define_insn_and_split "*extzv_8_23"
2745 [(set (match_operand:SI 0 "register_operand" "=r")
2746 (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
2747 (const_int 8)
2748 (const_int 23)))]
2749 "(TARGET_H8300H || TARGET_H8300S)"
2750 "#"
2751 "&& reload_completed"
2752 [(parallel [(set (match_dup 0)
2753 (ashift:SI (match_dup 0)
2754 (const_int 1)))
2755 (clobber (scratch:QI))])
2756 (parallel [(set (match_dup 0)
2757 (lshiftrt:SI (match_dup 0)
2758 (const_int 24)))
2759 (clobber (scratch:QI))])]
2760 "")
2761
2762 ;; and:SI
2763
2764 ;; ((SImode) HImode) << 15
2765
2766 (define_insn_and_split "*twoshifts_l16_r1"
2767 [(set (match_operand:SI 0 "register_operand" "=r")
2768 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2769 (const_int 15))
2770 (const_int 2147450880)))]
2771 "(TARGET_H8300H || TARGET_H8300S)"
2772 "#"
2773 "&& reload_completed"
2774 [(parallel [(set (match_dup 0)
2775 (ashift:SI (match_dup 0)
2776 (const_int 16)))
2777 (clobber (scratch:QI))])
2778 (parallel [(set (match_dup 0)
2779 (lshiftrt:SI (match_dup 0)
2780 (const_int 1)))
2781 (clobber (scratch:QI))])]
2782 "")
2783
2784 ;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
2785
2786 (define_insn_and_split "*andsi3_ashift_n_lower"
2787 [(set (match_operand:SI 0 "register_operand" "=r,r")
2788 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
2789 (match_operand:QI 2 "const_int_operand" "S,n"))
2790 (match_operand:SI 3 "const_int_operand" "n,n")))
2791 (clobber (match_scratch:QI 4 "=X,&r"))]
2792 "(TARGET_H8300H || TARGET_H8300S)
2793 && INTVAL (operands[2]) <= 15
2794 && INTVAL (operands[3]) == ((-1 << INTVAL (operands[2])) & 0xffff)"
2795 "#"
2796 "&& reload_completed"
2797 [(parallel [(set (match_dup 5)
2798 (ashift:HI (match_dup 5)
2799 (match_dup 2)))
2800 (clobber (match_dup 4))])
2801 (set (match_dup 0)
2802 (zero_extend:SI (match_dup 5)))]
2803 "operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2804
2805 ;; Accept (A >> 30) & 2 and the like.
2806
2807 (define_insn "*andsi3_lshiftrt_n_sb"
2808 [(set (match_operand:SI 0 "register_operand" "=r")
2809 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
2810 (match_operand:SI 2 "const_int_operand" "n"))
2811 (match_operand:SI 3 "single_one_operand" "n")))]
2812 "(TARGET_H8300H || TARGET_H8300S)
2813 && exact_log2 (INTVAL (operands[3])) < 16
2814 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
2815 "*
2816 {
2817 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
2818 return \"shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0\";
2819 }"
2820 [(set_attr "length" "8")
2821 (set_attr "cc" "clobber")])
2822
2823 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
2824 [(set (match_operand:SI 0 "register_operand" "=r")
2825 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
2826 (const_int 9))
2827 (const_int 4194304)))]
2828 "(TARGET_H8300H || TARGET_H8300S)"
2829 "#"
2830 "&& reload_completed"
2831 [(set (match_dup 0)
2832 (and:SI (lshiftrt:SI (match_dup 0)
2833 (const_int 25))
2834 (const_int 64)))
2835 (parallel [(set (match_dup 0)
2836 (ashift:SI (match_dup 0)
2837 (const_int 16)))
2838 (clobber (scratch:QI))])]
2839 "")
2840
2841 ;; plus:SI
2842
2843 (define_insn "*addsi3_upper"
2844 [(set (match_operand:SI 0 "register_operand" "=r")
2845 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
2846 (const_int 65536))
2847 (match_operand:SI 2 "register_operand" "0")))]
2848 "TARGET_H8300H || TARGET_H8300S"
2849 "add.w\\t%f1,%e0"
2850 [(set_attr "length" "2")
2851 (set_attr "cc" "clobber")])
2852
2853 (define_insn "*addsi3_lshiftrt_16_zexthi"
2854 [(set (match_operand:SI 0 "register_operand" "=r")
2855 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2856 (const_int 16))
2857 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
2858 "TARGET_H8300H || TARGET_H8300S"
2859 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0"
2860 [(set_attr "cc" "clobber")
2861 (set_attr "length" "6")])
2862
2863 (define_insn_and_split "*addsi3_and_r_1"
2864 [(set (match_operand:SI 0 "register_operand" "=r")
2865 (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
2866 (const_int 1))
2867 (match_operand:SI 2 "register_operand" "0")))]
2868 "(TARGET_H8300H || TARGET_H8300S)"
2869 "#"
2870 "&& reload_completed"
2871 [(set (cc0)
2872 (zero_extract:SI (match_dup 1)
2873 (const_int 1)
2874 (const_int 0)))
2875 (set (pc)
2876 (if_then_else (eq (cc0)
2877 (const_int 0))
2878 (label_ref (match_dup 3))
2879 (pc)))
2880 (set (match_dup 2)
2881 (plus:SI (match_dup 2)
2882 (const_int 1)))
2883 (match_dup 3)]
2884 "operands[3] = gen_label_rtx ();")
2885
2886 (define_insn_and_split "*addsi3_and_not_r_1"
2887 [(set (match_operand:SI 0 "register_operand" "=r")
2888 (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
2889 (const_int 1))
2890 (match_operand:SI 2 "register_operand" "0")))]
2891 "(TARGET_H8300H || TARGET_H8300S)"
2892 "#"
2893 "&& reload_completed"
2894 [(set (cc0)
2895 (zero_extract:SI (match_dup 1)
2896 (const_int 1)
2897 (const_int 0)))
2898 (set (pc)
2899 (if_then_else (ne (cc0)
2900 (const_int 0))
2901 (label_ref (match_dup 3))
2902 (pc)))
2903 (set (match_dup 2)
2904 (plus:SI (match_dup 2)
2905 (const_int 1)))
2906 (match_dup 3)]
2907 "operands[3] = gen_label_rtx ();")
2908
2909 ;; [ix]or:HI
2910
2911 (define_insn "*ixorhi3_zext"
2912 [(set (match_operand:HI 0 "register_operand" "=r")
2913 (match_operator:HI 1 "iorxor_operator"
2914 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
2915 (match_operand:HI 3 "register_operand" "0")]))]
2916 ""
2917 "%c1.b\\t%X2,%s0"
2918 [(set_attr "cc" "clobber")
2919 (set_attr "length" "2")])
2920
2921 ;; [ix]or:SI
2922
2923 (define_insn "*ixorsi3_zext_qi"
2924 [(set (match_operand:SI 0 "register_operand" "=r")
2925 (match_operator:SI 1 "iorxor_operator"
2926 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
2927 (match_operand:SI 3 "register_operand" "0")]))]
2928 ""
2929 "%c1.b\\t%X2,%w0"
2930 [(set_attr "cc" "clobber")
2931 (set_attr "length" "2")])
2932
2933 (define_insn "*ixorsi3_zext_hi"
2934 [(set (match_operand:SI 0 "register_operand" "=r")
2935 (match_operator:SI 1 "iorxor_operator"
2936 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
2937 (match_operand:SI 3 "register_operand" "0")]))]
2938 "TARGET_H8300H || TARGET_H8300S"
2939 "%c1.w\\t%T2,%f0"
2940 [(set_attr "cc" "clobber")
2941 (set_attr "length" "2")])
2942
2943 (define_insn "*ixorsi3_ashift_16"
2944 [(set (match_operand:SI 0 "register_operand" "=r")
2945 (match_operator:SI 1 "iorxor_operator"
2946 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
2947 (const_int 16))
2948 (match_operand:SI 3 "register_operand" "0")]))]
2949 "TARGET_H8300H || TARGET_H8300S"
2950 "%c1.w\\t%f2,%e0"
2951 [(set_attr "cc" "clobber")
2952 (set_attr "length" "2")])
2953
2954 (define_insn "*ixorsi3_lshiftrt_16"
2955 [(set (match_operand:SI 0 "register_operand" "=r")
2956 (match_operator:SI 1 "iorxor_operator"
2957 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2958 (const_int 16))
2959 (match_operand:SI 3 "register_operand" "0")]))]
2960 "TARGET_H8300H || TARGET_H8300S"
2961 "%c1.w\\t%e2,%f0"
2962 [(set_attr "cc" "clobber")
2963 (set_attr "length" "2")])
2964
2965 ;; ior:HI
2966
2967 (define_insn "*iorhi3_ashift_8"
2968 [(set (match_operand:HI 0 "register_operand" "=r")
2969 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
2970 (const_int 8))
2971 (match_operand:HI 2 "register_operand" "0")))]
2972 ""
2973 "or.b\\t%s1,%t0"
2974 [(set_attr "cc" "clobber")
2975 (set_attr "length" "2")])
2976
2977 (define_insn "*iorhi3_lshiftrt_8"
2978 [(set (match_operand:HI 0 "register_operand" "=r")
2979 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
2980 (const_int 8))
2981 (match_operand:HI 2 "register_operand" "0")))]
2982 ""
2983 "or.b\\t%t1,%s0"
2984 [(set_attr "cc" "clobber")
2985 (set_attr "length" "2")])
2986
2987 (define_insn "*iorhi3_two_qi"
2988 [(set (match_operand:HI 0 "register_operand" "=r")
2989 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
2990 (ashift:HI (match_operand:HI 2 "register_operand" "r")
2991 (const_int 8))))]
2992 ""
2993 "mov.b\\t%s2,%t0"
2994 [(set_attr "cc" "clobber")
2995 (set_attr "length" "2")])
2996
2997 (define_insn "*iorhi3_two_qi_mem"
2998 [(set (match_operand:HI 0 "register_operand" "=&r")
2999 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
3000 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
3001 (const_int 8))))]
3002 ""
3003 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
3004 [(set_attr "cc" "clobber")
3005 (set_attr "length" "16")])
3006
3007 (define_split
3008 [(set (match_operand:HI 0 "register_operand" "")
3009 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
3010 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
3011 (const_int 8))))]
3012 "(TARGET_H8300H || TARGET_H8300S)
3013 && reload_completed
3014 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
3015 [(set (match_dup 0)
3016 (match_dup 3))]
3017 "operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));")
3018
3019 ;; ior:SI
3020
3021 (define_insn "*iorsi3_two_hi"
3022 [(set (match_operand:SI 0 "register_operand" "=r")
3023 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
3024 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3025 (const_int 16))))]
3026 "TARGET_H8300H || TARGET_H8300S"
3027 "mov.w\\t%f2,%e0"
3028 [(set_attr "cc" "clobber")
3029 (set_attr "length" "2")])
3030
3031 (define_insn_and_split "*iorsi3_two_qi_zext"
3032 [(set (match_operand:SI 0 "register_operand" "=&r")
3033 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
3034
3035 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3036 (const_int 8))
3037 (const_int 65280))))]
3038 "(TARGET_H8300H || TARGET_H8300S)"
3039 "#"
3040 "&& reload_completed"
3041 [(set (match_dup 3)
3042 (ior:HI (zero_extend:HI (match_dup 1))
3043 (ashift:HI (subreg:HI (match_dup 2) 0)
3044 (const_int 8))))
3045 (set (match_dup 0)
3046 (zero_extend:SI (match_dup 3)))]
3047 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3048
3049 (define_insn "*iorsi3_e2f"
3050 [(set (match_operand:SI 0 "register_operand" "=r")
3051 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3052 (const_int -65536))
3053 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3054 (const_int 16))))]
3055 "TARGET_H8300H || TARGET_H8300S"
3056 "mov.w\\t%e2,%f0"
3057 [(set_attr "length" "2")
3058 (set_attr "cc" "clobber")])
3059
3060 (define_insn_and_split "*iorsi3_two_qi_sext"
3061 [(set (match_operand:SI 0 "register_operand" "=r")
3062 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
3063 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
3064 (const_int 8))))]
3065 "(TARGET_H8300H || TARGET_H8300S)"
3066 "#"
3067 "&& reload_completed"
3068 [(set (match_dup 3)
3069 (ior:HI (zero_extend:HI (match_dup 1))
3070 (ashift:HI (match_dup 4)
3071 (const_int 8))))
3072 (set (match_dup 0)
3073 (sign_extend:SI (match_dup 3)))]
3074 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3075 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3076
3077 (define_insn "*iorsi3_w"
3078 [(set (match_operand:SI 0 "register_operand" "=r,&r")
3079 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
3080 (const_int -256))
3081 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
3082 "TARGET_H8300H || TARGET_H8300S"
3083 "mov.b\\t%X2,%w0"
3084 [(set_attr "length" "2,8")
3085 (set_attr "cc" "clobber,clobber")])
3086
3087 (define_insn "*iorsi3_ashift_31"
3088 [(set (match_operand:SI 0 "register_operand" "=&r")
3089 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3090 (const_int 31))
3091 (match_operand:SI 2 "register_operand" "0")))]
3092 "TARGET_H8300H || TARGET_H8300S"
3093 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
3094 [(set_attr "length" "6")
3095 (set_attr "cc" "set_znv")])
3096
3097 (define_insn "*iorsi3_and_ashift"
3098 [(set (match_operand:SI 0 "register_operand" "=r")
3099 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3100 (match_operand:SI 2 "const_int_operand" "n"))
3101 (match_operand:SI 3 "single_one_operand" "n"))
3102 (match_operand:SI 4 "register_operand" "0")))]
3103 "(TARGET_H8300H || TARGET_H8300S)
3104 && (INTVAL (operands[3]) & ~0xffff) == 0"
3105 "*
3106 {
3107 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3108 - INTVAL (operands[2]));
3109 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3110 operands[2] = srcpos;
3111 operands[3] = dstpos;
3112 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
3113 }"
3114 [(set_attr "length" "6")
3115 (set_attr "cc" "clobber")])
3116
3117 (define_insn "*iorsi3_and_lshiftrt"
3118 [(set (match_operand:SI 0 "register_operand" "=r")
3119 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3120 (match_operand:SI 2 "const_int_operand" "n"))
3121 (match_operand:SI 3 "single_one_operand" "n"))
3122 (match_operand:SI 4 "register_operand" "0")))]
3123 "(TARGET_H8300H || TARGET_H8300S)
3124 && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
3125 "*
3126 {
3127 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3128 + INTVAL (operands[2]));
3129 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3130 operands[2] = srcpos;
3131 operands[3] = dstpos;
3132 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
3133 }"
3134 [(set_attr "length" "6")
3135 (set_attr "cc" "clobber")])
3136
3137 (define_insn "*iorsi3_zero_extract"
3138 [(set (match_operand:SI 0 "register_operand" "=r")
3139 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3140 (const_int 1)
3141 (match_operand:SI 2 "const_int_operand" "n"))
3142 (match_operand:SI 3 "register_operand" "0")))]
3143 "(TARGET_H8300H || TARGET_H8300S)
3144 && INTVAL (operands[2]) < 16"
3145 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
3146 [(set_attr "length" "6")
3147 (set_attr "cc" "clobber")])
3148
3149 (define_insn "*iorsi3_and_lshiftrt_n_sb"
3150 [(set (match_operand:SI 0 "register_operand" "=r")
3151 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3152 (const_int 30))
3153 (const_int 2))
3154 (match_operand:SI 2 "register_operand" "0")))]
3155 "(TARGET_H8300H || TARGET_H8300S)"
3156 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
3157 [(set_attr "length" "8")
3158 (set_attr "cc" "clobber")])
3159
3160 (define_insn "*iorsi3_and_lshiftrt_9_sb"
3161 [(set (match_operand:SI 0 "register_operand" "=r")
3162 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3163 (const_int 9))
3164 (const_int 4194304))
3165 (match_operand:SI 2 "register_operand" "0")))
3166 (clobber (match_scratch:HI 3 "=&r"))]
3167 "(TARGET_H8300H || TARGET_H8300S)"
3168 "*
3169 {
3170 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3171 return \"shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3172 else
3173 return \"rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3174 }"
3175 [(set_attr "length" "10")
3176 (set_attr "cc" "clobber")])
3177
3178 ;; Used to OR the exponent of a float.
3179
3180 (define_insn "*iorsi3_shift"
3181 [(set (match_operand:SI 0 "register_operand" "=r")
3182 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3183 (const_int 23))
3184 (match_operand:SI 2 "register_operand" "0")))
3185 (clobber (match_scratch:SI 3 "=&r"))]
3186 "TARGET_H8300H || TARGET_H8300S"
3187 "#")
3188
3189 (define_split
3190 [(parallel
3191 [(set (match_operand:SI 0 "register_operand" "")
3192 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3193 (const_int 23))
3194 (match_dup 0)))
3195 (clobber (match_operand:SI 2 "register_operand" ""))])]
3196 "(TARGET_H8300H || TARGET_H8300S)
3197 && flow2_completed
3198 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3199 && REGNO (operands[0]) != REGNO (operands[1])"
3200 [(parallel [(set (match_dup 3)
3201 (ashift:HI (match_dup 3)
3202 (const_int 7)))
3203 (clobber (scratch:QI))])
3204 (set (match_dup 0)
3205 (ior:SI (ashift:SI (match_dup 1)
3206 (const_int 16))
3207 (match_dup 0)))]
3208 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3209
3210 (define_split
3211 [(parallel
3212 [(set (match_operand:SI 0 "register_operand" "")
3213 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3214 (const_int 23))
3215 (match_dup 0)))
3216 (clobber (match_operand:SI 2 "register_operand" ""))])]
3217 "(TARGET_H8300H || TARGET_H8300S)
3218 && flow2_completed
3219 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3220 && REGNO (operands[0]) != REGNO (operands[1]))"
3221 [(set (match_dup 2)
3222 (match_dup 1))
3223 (parallel [(set (match_dup 3)
3224 (ashift:HI (match_dup 3)
3225 (const_int 7)))
3226 (clobber (scratch:QI))])
3227 (set (match_dup 0)
3228 (ior:SI (ashift:SI (match_dup 2)
3229 (const_int 16))
3230 (match_dup 0)))]
3231 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3232
3233 (define_insn "*iorsi2_and_1_lshiftrt_1"
3234 [(set (match_operand:SI 0 "register_operand" "=r")
3235 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3236 (const_int 1))
3237 (lshiftrt:SI (match_dup 1)
3238 (const_int 1))))]
3239 "TARGET_H8300H || TARGET_H8300S"
3240 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
3241 [(set_attr "length" "6")
3242 (set_attr "cc" "clobber")])
3243
3244 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
3245 [(set (match_operand:SI 0 "register_operand" "=r")
3246 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3247 (const_int 16))
3248 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3249 (const_int 24))))]
3250 "(TARGET_H8300H || TARGET_H8300S)"
3251 "#"
3252 "&& reload_completed"
3253 [(set (match_dup 3)
3254 (ior:HI (ashift:HI (match_dup 4)
3255 (const_int 8))
3256 (match_dup 3)))
3257 (parallel [(set (match_dup 0)
3258 (ashift:SI (match_dup 0)
3259 (const_int 16)))
3260 (clobber (scratch:QI))])]
3261 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3262 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3263
3264 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
3265 [(set (match_operand:SI 0 "register_operand" "=&r")
3266 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
3267 (const_int 16))
3268 (const_int 16711680))
3269 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3270 (const_int 24))))]
3271 "(TARGET_H8300H || TARGET_H8300S)"
3272 "#"
3273 "&& reload_completed"
3274 [(set (match_dup 3)
3275 (ior:HI (zero_extend:HI (match_dup 1))
3276 (ashift:HI (subreg:HI (match_dup 2) 0)
3277 (const_int 8))))
3278 (parallel [(set (match_dup 0)
3279 (ashift:SI (match_dup 0)
3280 (const_int 16)))
3281 (clobber (scratch:QI))])]
3282 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3283
3284 ;; Used to add the exponent of a float.
3285
3286 (define_insn "*addsi3_shift"
3287 [(set (match_operand:SI 0 "register_operand" "=r")
3288 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3289 (const_int 8388608))
3290 (match_operand:SI 2 "register_operand" "0")))
3291 (clobber (match_scratch:SI 3 "=&r"))]
3292 "TARGET_H8300H || TARGET_H8300S"
3293 "#")
3294
3295 (define_split
3296 [(parallel
3297 [(set (match_operand:SI 0 "register_operand" "")
3298 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3299 (const_int 8388608))
3300 (match_dup 0)))
3301 (clobber (match_operand:SI 2 "register_operand" ""))])]
3302 "(TARGET_H8300H || TARGET_H8300S)
3303 && flow2_completed
3304 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3305 && REGNO (operands[0]) != REGNO (operands[1])"
3306 [(parallel [(set (match_dup 3)
3307 (ashift:HI (match_dup 3)
3308 (const_int 7)))
3309 (clobber (scratch:QI))])
3310 (set (match_dup 0)
3311 (plus:SI (mult:SI (match_dup 1)
3312 (const_int 65536))
3313 (match_dup 0)))]
3314 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3315
3316 (define_split
3317 [(parallel
3318 [(set (match_operand:SI 0 "register_operand" "")
3319 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3320 (const_int 8388608))
3321 (match_dup 0)))
3322 (clobber (match_operand:SI 2 "register_operand" ""))])]
3323 "(TARGET_H8300H || TARGET_H8300S)
3324 && flow2_completed
3325 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3326 && REGNO (operands[0]) != REGNO (operands[1]))"
3327 [(set (match_dup 2)
3328 (match_dup 1))
3329 (parallel [(set (match_dup 3)
3330 (ashift:HI (match_dup 3)
3331 (const_int 7)))
3332 (clobber (scratch:QI))])
3333 (set (match_dup 0)
3334 (plus:SI (mult:SI (match_dup 2)
3335 (const_int 65536))
3336 (match_dup 0)))]
3337 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3338
3339 ;; ashift:SI
3340
3341 (define_insn_and_split "*ashiftsi_sextqi_7"
3342 [(set (match_operand:SI 0 "register_operand" "=r")
3343 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
3344 (const_int 7)))]
3345 "(TARGET_H8300H || TARGET_H8300S)"
3346 "#"
3347 "&& reload_completed"
3348 [(parallel [(set (match_dup 2)
3349 (ashift:HI (match_dup 2)
3350 (const_int 8)))
3351 (clobber (scratch:QI))])
3352 (set (match_dup 0)
3353 (sign_extend:SI (match_dup 2)))
3354 (parallel [(set (match_dup 0)
3355 (ashiftrt:SI (match_dup 0)
3356 (const_int 1)))
3357 (clobber (scratch:QI))])]
3358 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3359
3360 ;; Storing a part of HImode to QImode.
3361
3362 (define_insn ""
3363 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3364 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3365 (const_int 8)) 1))]
3366 ""
3367 "mov.b\\t%t1,%R0"
3368 [(set_attr "cc" "set_znv")
3369 (set_attr "length" "8")])
3370
3371 ;; Storing a part of SImode to QImode.
3372
3373 (define_insn ""
3374 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3375 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3376 (const_int 8)) 3))]
3377 ""
3378 "mov.b\\t%x1,%R0"
3379 [(set_attr "cc" "set_znv")
3380 (set_attr "length" "8")])
3381
3382 (define_insn ""
3383 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3384 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3385 (const_int 16)) 3))
3386 (clobber (match_scratch:SI 2 "=&r"))]
3387 "TARGET_H8300H || TARGET_H8300S"
3388 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
3389 [(set_attr "cc" "set_znv")
3390 (set_attr "length" "10")])
3391
3392 (define_insn ""
3393 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3394 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3395 (const_int 24)) 3))
3396 (clobber (match_scratch:SI 2 "=&r"))]
3397 "TARGET_H8300H || TARGET_H8300S"
3398 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
3399 [(set_attr "cc" "set_znv")
3400 (set_attr "length" "10")])
3401
3402 (define_insn_and_split ""
3403 [(set (pc)
3404 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3405 (const_int 1)
3406 (const_int 7))
3407 (const_int 0))
3408 (label_ref (match_operand 1 "" ""))
3409 (pc)))]
3410 ""
3411 "#"
3412 ""
3413 [(set (cc0)
3414 (match_dup 0))
3415 (set (pc)
3416 (if_then_else (ge (cc0)
3417 (const_int 0))
3418 (label_ref (match_dup 1))
3419 (pc)))]
3420 "")
3421
3422 (define_insn_and_split ""
3423 [(set (pc)
3424 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3425 (const_int 1)
3426 (const_int 7))
3427 (const_int 0))
3428 (label_ref (match_operand 1 "" ""))
3429 (pc)))]
3430 ""
3431 "#"
3432 ""
3433 [(set (cc0)
3434 (match_dup 0))
3435 (set (pc)
3436 (if_then_else (lt (cc0)
3437 (const_int 0))
3438 (label_ref (match_dup 1))
3439 (pc)))]
3440 "")
3441 \f
3442 ;; -----------------------------------------------------------------
3443 ;; PEEPHOLE PATTERNS
3444 ;; -----------------------------------------------------------------
3445
3446 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3447
3448 (define_peephole2
3449 [(parallel
3450 [(set (match_operand:HI 0 "register_operand" "")
3451 (lshiftrt:HI (match_dup 0)
3452 (match_operand:HI 1 "const_int_operand" "")))
3453 (clobber (match_operand:HI 2 "" ""))])
3454 (set (match_dup 0)
3455 (and:HI (match_dup 0)
3456 (match_operand:HI 3 "const_int_operand" "")))]
3457 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3458 [(set (match_dup 0)
3459 (and:HI (match_dup 0)
3460 (const_int 255)))
3461 (parallel
3462 [(set (match_dup 0)
3463 (lshiftrt:HI (match_dup 0)
3464 (match_dup 1)))
3465 (clobber (match_dup 2))])]
3466 "")
3467
3468 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3469
3470 (define_peephole2
3471 [(parallel
3472 [(set (match_operand:HI 0 "register_operand" "")
3473 (ashift:HI (match_dup 0)
3474 (match_operand:HI 1 "const_int_operand" "")))
3475 (clobber (match_operand:HI 2 "" ""))])
3476 (set (match_dup 0)
3477 (and:HI (match_dup 0)
3478 (match_operand:HI 3 "const_int_operand" "")))]
3479 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3480 [(set (match_dup 0)
3481 (and:HI (match_dup 0)
3482 (const_int 255)))
3483 (parallel
3484 [(set (match_dup 0)
3485 (ashift:HI (match_dup 0)
3486 (match_dup 1)))
3487 (clobber (match_dup 2))])]
3488 "")
3489
3490 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3491
3492 (define_peephole2
3493 [(parallel
3494 [(set (match_operand:SI 0 "register_operand" "")
3495 (lshiftrt:SI (match_dup 0)
3496 (match_operand:SI 1 "const_int_operand" "")))
3497 (clobber (match_operand:SI 2 "" ""))])
3498 (set (match_dup 0)
3499 (and:SI (match_dup 0)
3500 (match_operand:SI 3 "const_int_operand" "")))]
3501 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3502 [(set (match_dup 0)
3503 (and:SI (match_dup 0)
3504 (const_int 255)))
3505 (parallel
3506 [(set (match_dup 0)
3507 (lshiftrt:SI (match_dup 0)
3508 (match_dup 1)))
3509 (clobber (match_dup 2))])]
3510 "")
3511
3512 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3513
3514 (define_peephole2
3515 [(parallel
3516 [(set (match_operand:SI 0 "register_operand" "")
3517 (ashift:SI (match_dup 0)
3518 (match_operand:SI 1 "const_int_operand" "")))
3519 (clobber (match_operand:SI 2 "" ""))])
3520 (set (match_dup 0)
3521 (and:SI (match_dup 0)
3522 (match_operand:SI 3 "const_int_operand" "")))]
3523 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3524 [(set (match_dup 0)
3525 (and:SI (match_dup 0)
3526 (const_int 255)))
3527 (parallel
3528 [(set (match_dup 0)
3529 (ashift:SI (match_dup 0)
3530 (match_dup 1)))
3531 (clobber (match_dup 2))])]
3532 "")
3533
3534 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
3535
3536 (define_peephole2
3537 [(parallel
3538 [(set (match_operand:SI 0 "register_operand" "")
3539 (lshiftrt:SI (match_dup 0)
3540 (match_operand:SI 1 "const_int_operand" "")))
3541 (clobber (match_operand:SI 2 "" ""))])
3542 (set (match_dup 0)
3543 (and:SI (match_dup 0)
3544 (match_operand:SI 3 "const_int_operand" "")))]
3545 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
3546 [(set (match_dup 0)
3547 (and:SI (match_dup 0)
3548 (const_int 65535)))
3549 (parallel
3550 [(set (match_dup 0)
3551 (lshiftrt:SI (match_dup 0)
3552 (match_dup 1)))
3553 (clobber (match_dup 2))])]
3554 "")
3555
3556 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
3557
3558 (define_peephole2
3559 [(parallel
3560 [(set (match_operand:SI 0 "register_operand" "")
3561 (ashift:SI (match_dup 0)
3562 (match_operand:SI 1 "const_int_operand" "")))
3563 (clobber (match_operand:SI 2 "" ""))])
3564 (set (match_dup 0)
3565 (and:SI (match_dup 0)
3566 (match_operand:SI 3 "const_int_operand" "")))]
3567 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
3568 [(set (match_dup 0)
3569 (and:SI (match_dup 0)
3570 (const_int 65535)))
3571 (parallel
3572 [(set (match_dup 0)
3573 (ashift:SI (match_dup 0)
3574 (match_dup 1)))
3575 (clobber (match_dup 2))])]
3576 "")
3577
3578 ;; Convert a QImode push into an SImode push so that the
3579 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3580
3581 (define_peephole2
3582 [(parallel [(set (reg:SI SP_REG)
3583 (plus:SI (reg:SI SP_REG) (const_int -4)))
3584 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
3585 (match_operand:QI 0 "register_operand" ""))])]
3586 "TARGET_H8300S"
3587 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3588 (match_dup 0))]
3589 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3590
3591 ;; Convert a HImode push into an SImode push so that the
3592 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3593
3594 (define_peephole2
3595 [(parallel [(set (reg:SI SP_REG)
3596 (plus:SI (reg:SI SP_REG) (const_int -4)))
3597 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
3598 (match_operand:HI 0 "register_operand" ""))])]
3599 "TARGET_H8300S"
3600 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3601 (match_dup 0))]
3602 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3603
3604 ;; Cram four pushes into stm.l.
3605
3606 (define_peephole2
3607 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3608 (match_operand:SI 0 "register_operand" ""))
3609 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3610 (match_operand:SI 1 "register_operand" ""))
3611 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3612 (match_operand:SI 2 "register_operand" ""))
3613 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3614 (match_operand:SI 3 "register_operand" ""))]
3615 "TARGET_H8300S
3616 && REGNO (operands[0]) == 0
3617 && REGNO (operands[1]) == 1
3618 && REGNO (operands[2]) == 2
3619 && REGNO (operands[3]) == 3"
3620 [(parallel [(set (reg:SI SP_REG)
3621 (plus:SI (reg:SI SP_REG)
3622 (const_int -16)))
3623 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3624 (match_dup 0))
3625 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3626 (match_dup 1))
3627 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3628 (match_dup 2))
3629 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
3630 (match_dup 3))])]
3631 "")
3632
3633 ;; Cram three pushes into stm.l.
3634
3635 (define_peephole2
3636 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3637 (match_operand:SI 0 "register_operand" ""))
3638 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3639 (match_operand:SI 1 "register_operand" ""))
3640 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3641 (match_operand:SI 2 "register_operand" ""))]
3642 "TARGET_H8300S
3643 && ((REGNO (operands[0]) == 0
3644 && REGNO (operands[1]) == 1
3645 && REGNO (operands[2]) == 2)
3646 || (REGNO (operands[0]) == 4
3647 && REGNO (operands[1]) == 5
3648 && REGNO (operands[2]) == 6))"
3649 [(parallel [(set (reg:SI SP_REG)
3650 (plus:SI (reg:SI SP_REG)
3651 (const_int -12)))
3652 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3653 (match_dup 0))
3654 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3655 (match_dup 1))
3656 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3657 (match_dup 2))])]
3658 "")
3659
3660 ;; Cram two pushes into stm.l.
3661
3662 (define_peephole2
3663 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3664 (match_operand:SI 0 "register_operand" ""))
3665 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3666 (match_operand:SI 1 "register_operand" ""))]
3667 "TARGET_H8300S
3668 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
3669 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
3670 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
3671 [(parallel [(set (reg:SI SP_REG)
3672 (plus:SI (reg:SI SP_REG)
3673 (const_int -8)))
3674 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3675 (match_dup 0))
3676 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3677 (match_dup 1))])]
3678 "")
3679
3680 ;; Turn
3681 ;;
3682 ;; mov.w #2,r0
3683 ;; add.w r7,r0 (6 bytes)
3684 ;;
3685 ;; into
3686 ;;
3687 ;; mov.w r7,r0
3688 ;; adds #2,r0 (4 bytes)
3689
3690 (define_peephole2
3691 [(set (match_operand:HI 0 "register_operand" "")
3692 (match_operand:HI 1 "const_int_operand" ""))
3693 (set (match_dup 0)
3694 (plus:HI (match_dup 0)
3695 (match_operand:HI 2 "register_operand" "")))]
3696 "REG_P (operands[0]) && REG_P (operands[2])
3697 && REGNO (operands[0]) != REGNO (operands[2])
3698 && (CONST_OK_FOR_J (INTVAL (operands[1]))
3699 || CONST_OK_FOR_L (INTVAL (operands[1]))
3700 || CONST_OK_FOR_N (INTVAL (operands[1])))"
3701 [(set (match_dup 0)
3702 (match_dup 2))
3703 (set (match_dup 0)
3704 (plus:HI (match_dup 0)
3705 (match_dup 1)))]
3706 "")
3707
3708 ;; Turn
3709 ;;
3710 ;; sub.l er0,er0
3711 ;; add.b #4,r0l
3712 ;; add.l er7,er0 (6 bytes)
3713 ;;
3714 ;; into
3715 ;;
3716 ;; mov.l er7,er0
3717 ;; adds #4,er0 (4 bytes)
3718
3719 (define_peephole2
3720 [(set (match_operand:SI 0 "register_operand" "")
3721 (match_operand:SI 1 "const_int_operand" ""))
3722 (set (match_dup 0)
3723 (plus:SI (match_dup 0)
3724 (match_operand:SI 2 "register_operand" "")))]
3725 "(TARGET_H8300H || TARGET_H8300S)
3726 && REG_P (operands[0]) && REG_P (operands[2])
3727 && REGNO (operands[0]) != REGNO (operands[2])
3728 && (CONST_OK_FOR_L (INTVAL (operands[1]))
3729 || CONST_OK_FOR_N (INTVAL (operands[1])))"
3730 [(set (match_dup 0)
3731 (match_dup 2))
3732 (set (match_dup 0)
3733 (plus:SI (match_dup 0)
3734 (match_dup 1)))]
3735 "")
3736
3737 ;; Turn
3738 ;;
3739 ;; mov.l er7,er0
3740 ;; add.l #10,er0 (takes 8 bytes)
3741 ;;
3742 ;; into
3743 ;;
3744 ;; sub.l er0,er0
3745 ;; add.b #10,r0l
3746 ;; add.l er7,er0 (takes 6 bytes)
3747
3748 (define_peephole2
3749 [(set (match_operand:SI 0 "register_operand" "")
3750 (match_operand:SI 1 "register_operand" ""))
3751 (set (match_dup 0)
3752 (plus:SI (match_dup 0)
3753 (match_operand:SI 2 "const_int_operand" "")))]
3754 "(TARGET_H8300H || TARGET_H8300S)
3755 && REG_P (operands[0]) && REG_P (operands[1])
3756 && REGNO (operands[0]) != REGNO (operands[1])
3757 && !CONST_OK_FOR_L (INTVAL (operands[2]))
3758 && !CONST_OK_FOR_N (INTVAL (operands[2]))
3759 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
3760 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
3761 || INTVAL (operands[2]) == 0xffff
3762 || INTVAL (operands[2]) == 0xfffe)"
3763 [(set (match_dup 0)
3764 (match_dup 2))
3765 (set (match_dup 0)
3766 (plus:SI (match_dup 0)
3767 (match_dup 1)))]
3768 "")
3769
3770 ;; Turn
3771 ;;
3772 ;; subs #1,er4
3773 ;; mov.w r4,r4
3774 ;; bne .L2028
3775 ;;
3776 ;; into
3777 ;;
3778 ;; dec.w #1,r4
3779 ;; bne .L2028
3780
3781 (define_peephole2
3782 [(set (match_operand:HI 0 "register_operand" "")
3783 (plus:HI (match_dup 0)
3784 (match_operand 1 "incdec_operand" "")))
3785 (set (cc0)
3786 (match_dup 0))
3787 (set (pc)
3788 (if_then_else (match_operator 3 "eqne_operator"
3789 [(cc0) (const_int 0)])
3790 (label_ref (match_operand 2 "" ""))
3791 (pc)))]
3792 "TARGET_H8300H || TARGET_H8300S"
3793 [(set (match_operand:HI 0 "register_operand" "")
3794 (unspec:HI [(match_dup 0)
3795 (match_dup 1)]
3796 UNSPEC_INCDEC))
3797 (set (cc0)
3798 (match_dup 0))
3799 (set (pc)
3800 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
3801 (label_ref (match_dup 2))
3802 (pc)))]
3803 "")
3804
3805 ;; The SImode version of the previous pattern.
3806
3807 (define_peephole2
3808 [(set (match_operand:SI 0 "register_operand" "")
3809 (plus:SI (match_dup 0)
3810 (match_operand 1 "incdec_operand" "")))
3811 (set (cc0)
3812 (match_dup 0))
3813 (set (pc)
3814 (if_then_else (match_operator 3 "eqne_operator"
3815 [(cc0) (const_int 0)])
3816 (label_ref (match_operand 2 "" ""))
3817 (pc)))]
3818 "TARGET_H8300H || TARGET_H8300S"
3819 [(set (match_operand:SI 0 "register_operand" "")
3820 (unspec:SI [(match_dup 0)
3821 (match_dup 1)]
3822 UNSPEC_INCDEC))
3823 (set (cc0)
3824 (match_dup 0))
3825 (set (pc)
3826 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
3827 (label_ref (match_dup 2))
3828 (pc)))]
3829 "")
3830
3831 (define_peephole2
3832 [(parallel [(set (cc0)
3833 (zero_extract:SI (match_operand:QI 0 "register_operand" "")
3834 (const_int 1)
3835 (const_int 7)))
3836 (clobber (scratch:QI))])
3837 (set (pc)
3838 (if_then_else (match_operator 1 "eqne_operator"
3839 [(cc0) (const_int 0)])
3840 (label_ref (match_operand 2 "" ""))
3841 (pc)))]
3842 "(TARGET_H8300H || TARGET_H8300S)"
3843 [(set (cc0)
3844 (match_dup 0))
3845 (set (pc)
3846 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
3847 (label_ref (match_dup 2))
3848 (pc)))]
3849 "operands[3] = ((GET_CODE (operands[1]) == EQ)
3850 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
3851 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));")
3852
3853 ;; The next three peephole2's will try to transform
3854 ;;
3855 ;; mov.b A,r0l (or mov.l A,er0)
3856 ;; and.l #CST,er0
3857 ;;
3858 ;; into
3859 ;;
3860 ;; sub.l er0
3861 ;; mov.b A,r0l
3862 ;; and.b #CST,r0l (if CST is not 255)
3863
3864 (define_peephole2
3865 [(set (match_operand:QI 0 "register_operand" "")
3866 (match_operand:QI 1 "general_operand" ""))
3867 (set (match_operand:SI 2 "register_operand" "")
3868 (and:SI (match_dup 2)
3869 (const_int 255)))]
3870 "(TARGET_H8300H || TARGET_H8300S)
3871 && !reg_overlap_mentioned_p (operands[2], operands[1])
3872 && REGNO (operands[0]) == REGNO (operands[2])"
3873 [(set (match_dup 2)
3874 (const_int 0))
3875 (set (strict_low_part (match_dup 0))
3876 (match_dup 1))]
3877 "")
3878
3879 (define_peephole2
3880 [(set (match_operand:SI 0 "register_operand" "")
3881 (match_operand:SI 1 "general_operand" ""))
3882 (set (match_dup 0)
3883 (and:SI (match_dup 0)
3884 (const_int 255)))]
3885 "(TARGET_H8300H || TARGET_H8300S)
3886 && !reg_overlap_mentioned_p (operands[0], operands[1])
3887 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
3888 [(set (match_dup 0)
3889 (const_int 0))
3890 (set (strict_low_part (match_dup 2))
3891 (match_dup 3))]
3892 "operands[2] = gen_lowpart (QImode, operands[0]);
3893 operands[3] = gen_lowpart (QImode, operands[1]);")
3894
3895 (define_peephole2
3896 [(set (match_operand 0 "register_operand" "")
3897 (match_operand 1 "general_operand" ""))
3898 (set (match_operand:SI 2 "register_operand" "")
3899 (and:SI (match_dup 2)
3900 (match_operand:SI 3 "const_int_qi_operand" "")))]
3901 "(TARGET_H8300H || TARGET_H8300S)
3902 && (GET_MODE (operands[0]) == QImode
3903 || GET_MODE (operands[0]) == HImode
3904 || GET_MODE (operands[0]) == SImode)
3905 && GET_MODE (operands[0]) == GET_MODE (operands[1])
3906 && REGNO (operands[0]) == REGNO (operands[2])
3907 && !reg_overlap_mentioned_p (operands[2], operands[1])
3908 && !(GET_MODE (operands[1]) != QImode
3909 && GET_CODE (operands[1]) == MEM
3910 && MEM_VOLATILE_P (operands[1]))"
3911 [(set (match_dup 2)
3912 (const_int 0))
3913 (set (strict_low_part (match_dup 4))
3914 (match_dup 5))
3915 (set (match_dup 2)
3916 (and:SI (match_dup 2)
3917 (match_dup 6)))]
3918 "operands[4] = gen_lowpart (QImode, operands[0]);
3919 operands[5] = gen_lowpart (QImode, operands[1]);
3920 operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));")
3921
3922 (define_peephole2
3923 [(set (match_operand:SI 0 "register_operand" "")
3924 (match_operand:SI 1 "register_operand" ""))
3925 (set (match_dup 0)
3926 (and:SI (match_dup 0)
3927 (const_int 65280)))]
3928 "(TARGET_H8300H || TARGET_H8300S)
3929 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3930 [(set (match_dup 0)
3931 (const_int 0))
3932 (set (zero_extract:SI (match_dup 0)
3933 (const_int 8)
3934 (const_int 8))
3935 (lshiftrt:SI (match_dup 1)
3936 (const_int 8)))]
3937 "")
3938
3939 ;; If a load of mem:SI is followed by an AND that turns off the upper
3940 ;; half, then we can load mem:HI instead.
3941
3942 (define_peephole2
3943 [(set (match_operand:SI 0 "register_operand" "")
3944 (match_operand:SI 1 "memory_operand" ""))
3945 (set (match_dup 0)
3946 (and:SI (match_dup 0)
3947 (match_operand:SI 2 "const_int_operand" "")))]
3948 "(TARGET_H8300H || TARGET_H8300S)
3949 && !MEM_VOLATILE_P (operands[1])
3950 && (INTVAL (operands[2]) & ~0xffff) == 0
3951 && INTVAL (operands[2]) != 255"
3952 [(set (match_dup 3)
3953 (match_dup 4))
3954 (set (match_dup 0)
3955 (and:SI (match_dup 0)
3956 (match_dup 2)))]
3957 "operands[3] = gen_lowpart (HImode, operands[0]);
3958 operands[4] = gen_lowpart (HImode, operands[1]);")
3959
3960 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
3961 ;; the equivalent with shorter sequences. Here is the summary. Cases
3962 ;; are grouped for each define_peephole2.
3963 ;;
3964 ;; reg const_int use insn
3965 ;; --------------------------------------------------------
3966 ;; dead -2 eq/ne inc.l
3967 ;; dead -1 eq/ne inc.l
3968 ;; dead 1 eq/ne dec.l
3969 ;; dead 2 eq/ne dec.l
3970 ;;
3971 ;; dead 1 geu/ltu shar.l
3972 ;; dead 3 (H8S) geu/ltu shar.l
3973 ;;
3974 ;; ---- 255 geu/ltu mov.b
3975
3976 ;; Transform
3977 ;;
3978 ;; cmp.w #1,r0
3979 ;; bne .L1
3980 ;;
3981 ;; into
3982 ;;
3983 ;; dec.w #1,r0
3984 ;; bne .L1
3985
3986 (define_peephole2
3987 [(set (cc0)
3988 (compare (match_operand:HI 0 "register_operand" "")
3989 (match_operand:HI 1 "incdec_operand" "")))
3990 (set (pc)
3991 (if_then_else (match_operator 3 "eqne_operator"
3992 [(cc0) (const_int 0)])
3993 (label_ref (match_operand 2 "" ""))
3994 (pc)))]
3995 "(TARGET_H8300H || TARGET_H8300S)
3996 && peep2_reg_dead_p (1, operands[0])"
3997 [(set (match_dup 0)
3998 (unspec:HI [(match_dup 0)
3999 (match_dup 4)]
4000 UNSPEC_INCDEC))
4001 (set (cc0)
4002 (match_dup 0))
4003 (set (pc)
4004 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4005 (label_ref (match_dup 2))
4006 (pc)))]
4007 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4008
4009 ;; Transform
4010 ;;
4011 ;; cmp.w #1,r0
4012 ;; bhi .L1
4013 ;;
4014 ;; into
4015 ;;
4016 ;; shar.w r0
4017 ;; bne .L1
4018
4019 (define_peephole2
4020 [(set (cc0)
4021 (compare (match_operand:HI 0 "register_operand" "")
4022 (match_operand:HI 1 "const_int_operand" "")))
4023 (set (pc)
4024 (if_then_else (match_operator 2 "gtle_operator"
4025 [(cc0) (const_int 0)])
4026 (label_ref (match_operand 3 "" ""))
4027 (pc)))]
4028 "(TARGET_H8300H || TARGET_H8300S)
4029 && peep2_reg_dead_p (1, operands[0])
4030 && (INTVAL (operands[1]) == 1
4031 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4032 [(parallel [(set (match_dup 0)
4033 (ashiftrt:HI (match_dup 0)
4034 (match_dup 5)))
4035 (clobber (scratch:QI))])
4036 (set (cc0)
4037 (match_dup 0))
4038 (set (pc)
4039 (if_then_else (match_dup 4)
4040 (label_ref (match_dup 3))
4041 (pc)))]
4042 "switch (GET_CODE (operands[2]))
4043 {
4044 case GTU:
4045 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4046 break;
4047 case LEU:
4048 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4049 break;
4050 default:
4051 operands[4] = operands[2];
4052 break;
4053 }
4054 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4055
4056 ;; Transform
4057 ;;
4058 ;; cmp.w #255,r0
4059 ;; bhi .L1
4060 ;;
4061 ;; into
4062 ;;
4063 ;; mov.b r0h,r0h
4064 ;; bne .L1
4065
4066 (define_peephole2
4067 [(set (cc0)
4068 (compare (match_operand:HI 0 "register_operand" "")
4069 (const_int 255)))
4070 (set (pc)
4071 (if_then_else (match_operator 1 "gtle_operator"
4072 [(cc0) (const_int 0)])
4073 (label_ref (match_operand 2 "" ""))
4074 (pc)))]
4075 "TARGET_H8300H || TARGET_H8300S"
4076 [(set (cc0)
4077 (and:HI (match_dup 0)
4078 (const_int -256)))
4079 (set (pc)
4080 (if_then_else (match_dup 3)
4081 (label_ref (match_dup 2))
4082 (pc)))]
4083 "switch (GET_CODE (operands[1]))
4084 {
4085 case GTU:
4086 operands[3] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4087 break;
4088 case LEU:
4089 operands[3] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4090 break;
4091 default:
4092 operands[3] = operands[1];
4093 break;
4094 }")
4095
4096 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
4097 ;; the equivalent with shorter sequences. Here is the summary. Cases
4098 ;; are grouped for each define_peephole2.
4099 ;;
4100 ;; reg const_int use insn
4101 ;; --------------------------------------------------------
4102 ;; live -2 eq/ne copy and inc.l
4103 ;; live -1 eq/ne copy and inc.l
4104 ;; live 1 eq/ne copy and dec.l
4105 ;; live 2 eq/ne copy and dec.l
4106 ;;
4107 ;; dead -2 eq/ne inc.l
4108 ;; dead -1 eq/ne inc.l
4109 ;; dead 1 eq/ne dec.l
4110 ;; dead 2 eq/ne dec.l
4111 ;;
4112 ;; dead -131072 eq/ne inc.w and test
4113 ;; dead -65536 eq/ne inc.w and test
4114 ;; dead 65536 eq/ne dec.w and test
4115 ;; dead 131072 eq/ne dec.w and test
4116 ;;
4117 ;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
4118 ;; dead 0x0000??00 eq/ne xor.b and test
4119 ;; dead 0x0000ffff eq/ne not.w and test
4120 ;;
4121 ;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
4122 ;; dead 0xffff??ff eq/ne xor.b and not.l
4123 ;;
4124 ;; live 1 geu/ltu copy and shar.l
4125 ;; live 3 (H8S) geu/ltu copy and shar.l
4126 ;;
4127 ;; dead 1 geu/ltu shar.l
4128 ;; dead 3 (H8S) geu/ltu shar.l
4129 ;;
4130 ;; dead 3 (H8/300H) geu/ltu and.b and test
4131 ;; dead 7 geu/ltu and.b and test
4132 ;; dead 15 geu/ltu and.b and test
4133 ;; dead 31 geu/ltu and.b and test
4134 ;; dead 63 geu/ltu and.b and test
4135 ;; dead 127 geu/ltu and.b and test
4136 ;; dead 255 geu/ltu and.b and test
4137 ;;
4138 ;; dead 65535 geu/ltu mov.w
4139
4140 ;; For a small constant, it is cheaper to actually do the subtraction
4141 ;; and then test the register.
4142
4143 (define_peephole2
4144 [(set (cc0)
4145 (compare (match_operand:SI 0 "register_operand" "")
4146 (match_operand:SI 1 "incdec_operand" "")))
4147 (set (pc)
4148 (if_then_else (match_operator 3 "eqne_operator"
4149 [(cc0) (const_int 0)])
4150 (label_ref (match_operand 2 "" ""))
4151 (pc)))]
4152 "(TARGET_H8300H || TARGET_H8300S)
4153 && peep2_reg_dead_p (1, operands[0])"
4154 [(set (match_dup 0)
4155 (unspec:SI [(match_dup 0)
4156 (match_dup 4)]
4157 UNSPEC_INCDEC))
4158 (set (cc0)
4159 (match_dup 0))
4160 (set (pc)
4161 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4162 (label_ref (match_dup 2))
4163 (pc)))]
4164 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4165
4166 (define_peephole2
4167 [(set (cc0)
4168 (compare (match_operand:SI 0 "register_operand" "")
4169 (match_operand:SI 1 "const_int_operand" "")))
4170 (set (pc)
4171 (if_then_else (match_operator 3 "eqne_operator"
4172 [(cc0) (const_int 0)])
4173 (label_ref (match_operand 2 "" ""))
4174 (pc)))]
4175 "(TARGET_H8300H || TARGET_H8300S)
4176 && peep2_reg_dead_p (1, operands[0])
4177 && (INTVAL (operands[1]) == -131072
4178 || INTVAL (operands[1]) == -65536
4179 || INTVAL (operands[1]) == 65536
4180 || INTVAL (operands[1]) == 131072)"
4181 [(set (match_dup 0)
4182 (plus:SI (match_dup 0)
4183 (match_dup 4)))
4184 (set (cc0)
4185 (match_dup 0))
4186 (set (pc)
4187 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4188 (label_ref (match_dup 2))
4189 (pc)))]
4190 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4191
4192 ;; For certain (in)equality comparisons against a constant, we can
4193 ;; XOR the register with the constant, and test the register against
4194 ;; 0.
4195
4196 (define_peephole2
4197 [(set (cc0)
4198 (compare (match_operand:SI 0 "register_operand" "")
4199 (match_operand:SI 1 "const_int_operand" "")))
4200 (set (pc)
4201 (if_then_else (match_operator 3 "eqne_operator"
4202 [(cc0) (const_int 0)])
4203 (label_ref (match_operand 2 "" ""))
4204 (pc)))]
4205 "(TARGET_H8300H || TARGET_H8300S)
4206 && peep2_reg_dead_p (1, operands[0])
4207 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
4208 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
4209 || INTVAL (operands[1]) == 0x0000ffff)
4210 && INTVAL (operands[1]) != 1
4211 && INTVAL (operands[1]) != 2"
4212 [(set (match_dup 0)
4213 (xor:SI (match_dup 0)
4214 (match_dup 1)))
4215 (set (cc0)
4216 (match_dup 0))
4217 (set (pc)
4218 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4219 (label_ref (match_dup 2))
4220 (pc)))]
4221 "")
4222
4223 (define_peephole2
4224 [(set (cc0)
4225 (compare (match_operand:SI 0 "register_operand" "")
4226 (match_operand:SI 1 "const_int_operand" "")))
4227 (set (pc)
4228 (if_then_else (match_operator 3 "eqne_operator"
4229 [(cc0) (const_int 0)])
4230 (label_ref (match_operand 2 "" ""))
4231 (pc)))]
4232 "(TARGET_H8300H || TARGET_H8300S)
4233 && peep2_reg_dead_p (1, operands[0])
4234 && ((INTVAL (operands[1]) | 0x00ff) == -1
4235 || (INTVAL (operands[1]) | 0xff00) == -1)
4236 && INTVAL (operands[1]) != -1
4237 && INTVAL (operands[1]) != -2"
4238 [(set (match_dup 0)
4239 (xor:SI (match_dup 0)
4240 (match_dup 4)))
4241 (set (match_dup 0)
4242 (not:SI (match_dup 0)))
4243 (set (cc0)
4244 (match_dup 0))
4245 (set (pc)
4246 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4247 (label_ref (match_dup 2))
4248 (pc)))]
4249 "operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);")
4250
4251 ;; Transform
4252 ;;
4253 ;; cmp.l #1,er0
4254 ;; bhi .L1
4255 ;;
4256 ;; into
4257 ;;
4258 ;; mov.l er0,er1
4259 ;; shar.l er1
4260 ;; bne .L1
4261
4262 ;; We avoid this transformation if we see more than one copy of the
4263 ;; same compare insn immediately before this one.
4264
4265 (define_peephole2
4266 [(match_scratch:SI 4 "r")
4267 (set (cc0)
4268 (compare (match_operand:SI 0 "register_operand" "")
4269 (match_operand:SI 1 "const_int_operand" "")))
4270 (set (pc)
4271 (if_then_else (match_operator 2 "gtle_operator"
4272 [(cc0) (const_int 0)])
4273 (label_ref (match_operand 3 "" ""))
4274 (pc)))]
4275 "(TARGET_H8300H || TARGET_H8300S)
4276 && !peep2_reg_dead_p (1, operands[0])
4277 && (INTVAL (operands[1]) == 1
4278 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
4279 && !same_cmp_preceding_p (insn)"
4280 [(set (match_dup 4)
4281 (match_dup 0))
4282 (parallel [(set (match_dup 4)
4283 (ashiftrt:SI (match_dup 4)
4284 (match_dup 6)))
4285 (clobber (scratch:QI))])
4286 (set (cc0)
4287 (match_dup 4))
4288 (set (pc)
4289 (if_then_else (match_dup 5)
4290 (label_ref (match_dup 3))
4291 (pc)))]
4292 "switch (GET_CODE (operands[2]))
4293 {
4294 case GTU:
4295 operands[5] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4296 break;
4297 case LEU:
4298 operands[5] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4299 break;
4300 default:
4301 operands[5] = operands[2];
4302 break;
4303 }
4304 operands[6] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4305
4306 ;; Transform
4307 ;;
4308 ;; cmp.l #1,er0
4309 ;; bhi .L1
4310 ;;
4311 ;; into
4312 ;;
4313 ;; shar.l er0
4314 ;; bne .L1
4315
4316 (define_peephole2
4317 [(set (cc0)
4318 (compare (match_operand:SI 0 "register_operand" "")
4319 (match_operand:SI 1 "const_int_operand" "")))
4320 (set (pc)
4321 (if_then_else (match_operator 2 "gtle_operator"
4322 [(cc0) (const_int 0)])
4323 (label_ref (match_operand 3 "" ""))
4324 (pc)))]
4325 "(TARGET_H8300H || TARGET_H8300S)
4326 && peep2_reg_dead_p (1, operands[0])
4327 && (INTVAL (operands[1]) == 1
4328 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4329 [(parallel [(set (match_dup 0)
4330 (ashiftrt:SI (match_dup 0)
4331 (match_dup 5)))
4332 (clobber (scratch:QI))])
4333 (set (cc0)
4334 (match_dup 0))
4335 (set (pc)
4336 (if_then_else (match_dup 4)
4337 (label_ref (match_dup 3))
4338 (pc)))]
4339 "switch (GET_CODE (operands[2]))
4340 {
4341 case GTU:
4342 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4343 break;
4344 case LEU:
4345 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4346 break;
4347 default:
4348 operands[4] = operands[2];
4349 break;
4350 }
4351 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4352
4353 ;; Transform
4354 ;;
4355 ;; cmp.l #15,er0
4356 ;; bhi .L1
4357 ;;
4358 ;; into
4359 ;;
4360 ;; and #240,r0l
4361 ;; mov.l er0,er0
4362 ;; bne .L1
4363
4364 (define_peephole2
4365 [(set (cc0)
4366 (compare (match_operand:SI 0 "register_operand" "")
4367 (match_operand:SI 1 "const_int_operand" "")))
4368 (set (pc)
4369 (if_then_else (match_operator 2 "gtle_operator"
4370 [(cc0) (const_int 0)])
4371 (label_ref (match_operand 3 "" ""))
4372 (pc)))]
4373 "(TARGET_H8300H || TARGET_H8300S)
4374 && peep2_reg_dead_p (1, operands[0])
4375 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
4376 || INTVAL (operands[1]) == 7
4377 || INTVAL (operands[1]) == 15
4378 || INTVAL (operands[1]) == 31
4379 || INTVAL (operands[1]) == 63
4380 || INTVAL (operands[1]) == 127
4381 || INTVAL (operands[1]) == 255)"
4382 [(set (match_dup 0)
4383 (and:SI (match_dup 0)
4384 (match_dup 5)))
4385 (set (cc0)
4386 (match_dup 0))
4387 (set (pc)
4388 (if_then_else (match_dup 4)
4389 (label_ref (match_dup 3))
4390 (pc)))]
4391 "switch (GET_CODE (operands[2]))
4392 {
4393 case GTU:
4394 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4395 break;
4396 case LEU:
4397 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4398 break;
4399 default:
4400 operands[4] = operands[2];
4401 break;
4402 }
4403 operands[5] = GEN_INT (~INTVAL (operands[1]));")
4404
4405 ;; Transform A <= 65535 to (A & 0xffff0000) == 0.
4406
4407 (define_peephole2
4408 [(set (cc0)
4409 (compare (match_operand:SI 0 "register_operand" "")
4410 (const_int 65535)))
4411 (set (pc)
4412 (if_then_else (match_operator 1 "gtle_operator"
4413 [(cc0) (const_int 0)])
4414 (label_ref (match_operand 2 "" ""))
4415 (pc)))]
4416 "TARGET_H8300H || TARGET_H8300S"
4417 [(set (cc0)
4418 (and:SI (match_dup 0)
4419 (const_int -65536)))
4420 (set (pc)
4421 (if_then_else (match_dup 3)
4422 (label_ref (match_dup 2))
4423 (pc)))]
4424 "switch (GET_CODE (operands[1]))
4425 {
4426 case GTU:
4427 operands[3] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4428 break;
4429 case LEU:
4430 operands[3] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4431 break;
4432 default:
4433 operands[3] = operands[1];
4434 break;
4435 }")
4436
4437 ;; For constants like -1, -2, 1, 2, it is still cheaper to make a copy
4438 ;; of the register being tested, do the subtraction on the copy, and
4439 ;; then test the copy. We avoid this transformation if we see more
4440 ;; than one copy of the same compare insn.
4441
4442 (define_peephole2
4443 [(match_scratch:SI 4 "r")
4444 (set (cc0)
4445 (compare (match_operand:SI 0 "register_operand" "")
4446 (match_operand:SI 1 "incdec_operand" "")))
4447 (set (pc)
4448 (if_then_else (match_operator 3 "eqne_operator"
4449 [(cc0) (const_int 0)])
4450 (label_ref (match_operand 2 "" ""))
4451 (pc)))]
4452 "(TARGET_H8300H || TARGET_H8300S)
4453 && !peep2_reg_dead_p (1, operands[0])
4454 && !rtx_equal_p (PATTERN (insn),
4455 PATTERN (next_nonnote_insn (next_nonnote_insn (insn))))"
4456 [(set (match_dup 4)
4457 (match_dup 0))
4458 (set (match_dup 4)
4459 (unspec:SI [(match_dup 4)
4460 (match_dup 5)]
4461 UNSPEC_INCDEC))
4462 (set (cc0)
4463 (match_dup 4))
4464 (set (pc)
4465 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4466 (label_ref (match_dup 2))
4467 (pc)))]
4468 "operands[5] = GEN_INT (- INTVAL (operands[1]));")
4469
4470 ;; Narrow the mode of testing if possible.
4471
4472 (define_peephole2
4473 [(set (match_operand:HI 0 "register_operand" "")
4474 (and:HI (match_dup 0)
4475 (match_operand:HI 1 "const_int_qi_operand" "")))
4476 (set (cc0)
4477 (match_dup 0))
4478 (set (pc)
4479 (if_then_else (match_operator 3 "eqne_operator"
4480 [(cc0) (const_int 0)])
4481 (label_ref (match_operand 2 "" ""))
4482 (pc)))]
4483 "peep2_reg_dead_p (2, operands[0])"
4484 [(set (match_dup 4)
4485 (and:QI (match_dup 4)
4486 (match_dup 5)))
4487 (set (cc0)
4488 (match_dup 4))
4489 (set (pc)
4490 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4491 (label_ref (match_dup 2))
4492 (pc)))]
4493 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
4494 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
4495
4496 (define_peephole2
4497 [(set (match_operand:SI 0 "register_operand" "")
4498 (and:SI (match_dup 0)
4499 (match_operand:SI 1 "const_int_qi_operand" "")))
4500 (set (cc0)
4501 (match_dup 0))
4502 (set (pc)
4503 (if_then_else (match_operator 3 "eqne_operator"
4504 [(cc0) (const_int 0)])
4505 (label_ref (match_operand 2 "" ""))
4506 (pc)))]
4507 "peep2_reg_dead_p (2, operands[0])"
4508 [(set (match_dup 4)
4509 (and:QI (match_dup 4)
4510 (match_dup 5)))
4511 (set (cc0)
4512 (match_dup 4))
4513 (set (pc)
4514 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4515 (label_ref (match_dup 2))
4516 (pc)))]
4517 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
4518 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
4519
4520 (define_peephole2
4521 [(set (match_operand:SI 0 "register_operand" "")
4522 (and:SI (match_dup 0)
4523 (match_operand:SI 1 "const_int_hi_operand" "")))
4524 (set (cc0)
4525 (match_dup 0))
4526 (set (pc)
4527 (if_then_else (match_operator 3 "eqne_operator"
4528 [(cc0) (const_int 0)])
4529 (label_ref (match_operand 2 "" ""))
4530 (pc)))]
4531 "peep2_reg_dead_p (2, operands[0])"
4532 [(set (match_dup 4)
4533 (and:HI (match_dup 4)
4534 (match_dup 5)))
4535 (set (cc0)
4536 (match_dup 4))
4537 (set (pc)
4538 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4539 (label_ref (match_dup 2))
4540 (pc)))]
4541 "operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
4542 operands[5] = gen_int_mode (INTVAL (operands[1]), HImode);")
4543
4544 (define_peephole2
4545 [(set (match_operand:SI 0 "register_operand" "")
4546 (and:SI (match_dup 0)
4547 (match_operand:SI 1 "const_int_qi_operand" "")))
4548 (set (match_dup 0)
4549 (xor:SI (match_dup 0)
4550 (match_operand:SI 2 "const_int_qi_operand" "")))
4551 (set (cc0)
4552 (match_dup 0))
4553 (set (pc)
4554 (if_then_else (match_operator 4 "eqne_operator"
4555 [(cc0) (const_int 0)])
4556 (label_ref (match_operand 3 "" ""))
4557 (pc)))]
4558 "peep2_reg_dead_p (3, operands[0])
4559 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
4560 [(set (match_dup 5)
4561 (and:QI (match_dup 5)
4562 (match_dup 6)))
4563 (set (match_dup 5)
4564 (xor:QI (match_dup 5)
4565 (match_dup 7)))
4566 (set (cc0)
4567 (match_dup 5))
4568 (set (pc)
4569 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
4570 (label_ref (match_dup 3))
4571 (pc)))]
4572 "operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
4573 operands[6] = gen_int_mode (INTVAL (operands[1]), QImode);
4574 operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);")