1 ;;- Machine description for GNU compiler -- System/370 version.
2 ;; Copyright (C) 1989, 93, 94, 95, 97-99, 2000 Free Software Foundation, Inc.
3 ;; Contributed by Jan Stein (jan@cd.chalmers.se).
4 ;; Modified for OS/390 LanguageEnvironment C by Dave Pitts (dpitts@cozx.com)
5 ;; Lots of Bug Fixes & Enhancements by Linas Vepstas (linas@linas.org)
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;; =======================================================================
25 ;; Condition codes for some of the instructions (in particular, for
26 ;; add, sub, shift, abs, etc. are handled with the cpp macro NOTICE_UPDATE_CC
28 ;; Special constraints for 370 machine description:
30 ;; a -- Any address register from 1 to 15.
31 ;; d -- Any register from 0 to 15.
32 ;; I -- An 8-bit constant (0..255).
33 ;; J -- A 12-bit constant (0..4095).
34 ;; K -- A 16-bit constant (-32768..32767).
35 ;; R -- a valid S operand in an RS, SI or SS instruction, or register
36 ;; S -- a valid S operand in an RS, SI or SS instruction
39 ;; When defining an instruction, e.g. the movsi pattern:
42 ;; [(set (match_operand:SI 0 "r_or_s_operand" "=dm,d,dm")
43 ;; (match_operand:SI 1 "r_or_s_operand" "diR,dim,*fF"))]
45 ;; The "r_or_s_operand" predicate is used to recognize the instruction;
46 ;; however, it is not further used to enforce a constraint at later stages.
47 ;; Thus, for example, although "r_or_s_operand" bars operands of the form
48 ;; base+index+displacement, such operands can none-the-less show up during
49 ;; post-instruction-recog processing: thus, for example, garbage like
50 ;; MVC 152(4,r13),0(r5,r13) might be generated if both op0 and op1 are
51 ;; mem operands. To avoid this, use the S constraint.
54 ;; Special formats used for outputting 370 instructions.
56 ;; %B -- Print a constant byte integer.
57 ;; %H -- Print a signed 16-bit constant.
58 ;; %K -- Print a signed 16-bit constant signed-extended to 32-bits.
59 ;; %L -- Print least significant word of a CONST_DOUBLE.
60 ;; %M -- Print most significant word of a CONST_DOUBLE.
61 ;; %N -- Print next register (second word of a DImode reg).
62 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
63 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
64 ;; %X -- Print a constant byte integer in hex.
65 ;; %W -- Print a signed 32-bit int sign-extended to 64-bits.
67 ;; We have a special constraint for pattern matching.
69 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
71 ;; r_or_s_operand -- Matches a register or a valid S operand in a RS, SI
72 ;; or SS type instruction or a register
74 ;; For MVS C/370 we use the following stack locations for:
76 ;; 136 - internal function result buffer
77 ;; 140 - numeric conversion buffer
78 ;; 144 - pointer to internal function result buffer
79 ;; 148 - start of automatic variables and function arguments
81 ;; To support programs larger than a page, 4096 bytes, PAGE_REGISTER points
82 ;; to a page origin table, all internal labels are generated to reload the
83 ;; BASE_REGISTER knowing what page it is on and all branch instructions go
84 ;; directly to the target if it is known that the target is on the current
85 ;; page (essentially backward references). All forward references and off
86 ;; page references are handled by loading the address of target into a
87 ;; register and branching indirectly.
89 ;; Some *di patterns have been commented out per advice from RMS, as gcc
90 ;; will generate the right things to do.
92 ;; See the note in i370.h about register 14, clobbering it, and optimization.
93 ;; Basically, using clobber in egcs-1.1.1 will ruin ability to optimize around
94 ;; branches, so don't do it.
96 ;; We use the "length" attirbute to store the max possible code size of an
97 ;; insn. We use this length to estimate the length of forward branches, to
98 ;; determine if they're on page or off.
100 (define_attr "length" "" (const_int 0))
103 ;;- Test instructions.
107 ; tstdi instruction pattern(s).
112 (match_operand:DI 0 "register_operand" "d"))]
117 mvs_check_page (0, 4, 0);
118 return \"SRDA %0,0\";
120 [(set_attr "length" "4")]
124 ; tstsi instruction pattern(s).
129 (match_operand:SI 0 "register_operand" "d"))]
134 mvs_check_page (0, 2, 0);
135 return \"LTR %0,%0\";
137 [(set_attr "length" "2")]
141 ; tsthi instruction pattern(s).
146 (match_operand:HI 0 "register_operand" "d"))]
151 mvs_check_page (0, 4, 2);
152 return \"CH %0,=H'0'\";
154 [(set_attr "length" "4")]
158 ; tstqi instruction pattern(s).
163 (match_operand:QI 0 "r_or_s_operand" "dm"))]
164 "unsigned_jump_follows_p (insn)"
168 if (REG_P (operands[0]))
170 /* an unsigned compare to zero is always zero/not-zero... */
171 mvs_check_page (0, 4, 4);
172 return \"N %0,=X'000000FF'\";
174 mvs_check_page (0, 4, 0);
177 [(set_attr "length" "4")]
182 (match_operand:QI 0 "register_operand" "d"))]
187 if (unsigned_jump_follows_p (insn))
189 /* an unsigned compare to zero is always zero/not-zero... */
190 mvs_check_page (0, 4, 4);
191 return \"N %0,=X'000000FF'\";
193 mvs_check_page (0, 8, 0);
194 return \"SLL %0,24\;SRA %0,24\";
196 [(set_attr "length" "8")]
200 ; tstdf instruction pattern(s).
205 (match_operand:DF 0 "general_operand" "f"))]
210 mvs_check_page (0, 2, 0);
211 return \"LTDR %0,%0\";
213 [(set_attr "length" "2")]
217 ; tstsf instruction pattern(s).
222 (match_operand:SF 0 "general_operand" "f"))]
227 mvs_check_page (0, 2, 0);
228 return \"LTER %0,%0\";
230 [(set_attr "length" "2")]
234 ;;- Compare instructions.
238 ; cmpdi instruction pattern(s).
241 ;(define_insn "cmpdi"
243 ; (compare (match_operand:DI 0 "register_operand" "d")
244 ; (match_operand:DI 1 "general_operand" "")))]
248 ; check_label_emit ();
249 ; if (REG_P (operands[1]))
251 ; mvs_check_page (0, 8, 0);
252 ; if (unsigned_jump_follows_p (insn))
253 ; return \"CLR %0,%1\;BNE *+6\;CLR %N0,%N1\";
254 ; return \"CR %0,%1\;BNE *+6\;CLR %N0,%N1\";
256 ; mvs_check_page (0, 12, 0);
257 ; if (unsigned_jump_follows_p (insn))
258 ; return \"CL %0,%M1\;BNE *+8\;CL %N0,%L1\";
259 ; return \"C %0,%M1\;BNE *+8\;CL %N0,%L1\";
263 ; cmpsi instruction pattern(s).
268 (compare (match_operand:SI 0 "register_operand" "d")
269 (match_operand:SI 1 "general_operand" "md")))]
274 if (REG_P (operands[1]))
276 mvs_check_page (0, 2, 0);
277 if (unsigned_jump_follows_p (insn))
278 return \"CLR %0,%1\";
281 if (GET_CODE (operands[1]) == CONST_INT)
283 mvs_check_page (0, 4, 4);
284 if (unsigned_jump_follows_p (insn))
285 return \"CL %0,=F'%c1'\";
286 return \"C %0,=F'%c1'\";
288 mvs_check_page (0, 4, 0);
289 if (unsigned_jump_follows_p (insn))
293 [(set_attr "length" "4")]
297 ; cmphi instruction pattern(s).
300 ; depricate constraint d because it takes multiple instructions
301 ; and a memeory access ...
304 (compare (match_operand:HI 0 "register_operand" "d")
305 (match_operand:HI 1 "general_operand" "???dim")))]
310 if (REG_P (operands[1]))
312 mvs_check_page (0, 8, 0);
313 if (unsigned_jump_follows_p (insn))
314 return \"STH %1,140(,13)\;CLM %0,3,140(13)\";
315 return \"STH %1,140(,13)\;CH %0,140(,13)\";
317 if (GET_CODE (operands[1]) == CONST_INT)
319 mvs_check_page (0, 4, 0);
320 return \"CH %0,%H1\";
322 mvs_check_page (0, 4, 0);
325 [(set_attr "length" "8")]
329 ; cmpqi instruction pattern(s).
334 (compare (match_operand:QI 0 "r_or_s_operand" "dS")
335 (match_operand:QI 1 "r_or_s_operand" "diS")))]
336 "unsigned_jump_follows_p (insn)"
340 if (REG_P (operands[0]))
342 if (REG_P (operands[1]))
344 mvs_check_page (0, 8, 0);
345 return \"STC %1,140(,13)\;CLM %0,1,140(13)\";
347 if (GET_CODE (operands[1]) == CONST_INT)
349 mvs_check_page (0, 4, 1);
350 return \"CLM %0,1,=X'%X1'\";
352 mvs_check_page (0, 4, 0);
353 return \"CLM %0,1,%1\";
355 else if (GET_CODE (operands[0]) == CONST_INT)
357 cc_status.flags |= CC_REVERSED;
358 if (REG_P (operands[1]))
360 mvs_check_page (0, 4, 1);
361 return \"CLM %1,1,=X'%X0'\";
363 mvs_check_page (0, 4, 0);
364 return \"CLI %1,%B0\";
366 if (GET_CODE (operands[1]) == CONST_INT)
368 mvs_check_page (0, 4, 0);
369 return \"CLI %0,%B1\";
371 if (GET_CODE (operands[1]) == MEM)
373 mvs_check_page (0, 6, 0);
374 return \"CLC %O0(1,%R0),%1\";
376 cc_status.flags |= CC_REVERSED;
377 mvs_check_page (0, 4, 0);
378 return \"CLM %1,1,%0\";
380 [(set_attr "length" "8")]
385 (compare (match_operand:QI 0 "register_operand" "d")
386 (match_operand:QI 1 "general_operand" "di")))]
391 if (unsigned_jump_follows_p (insn))
393 if (GET_CODE (operands[1]) == CONST_INT)
395 mvs_check_page (0, 4, 1);
396 return \"CLM %0,1,=X'%X1'\";
398 if (!(REG_P (operands[1])))
400 mvs_check_page (0, 4, 0);
401 return \"CLM %0,1,%1\";
403 mvs_check_page (0, 8, 0);
404 return \"STC %1,140(,13)\;CLM %0,1,140(13)\";
406 if (REG_P (operands[1]))
408 mvs_check_page (0, 18, 0);
409 return \"SLL %0,24\;SRA %0,24\;SLL %1,24\;SRA %1,24\;CR %0,%1\";
411 mvs_check_page (0, 12, 0);
412 return \"SLL %0,24\;SRA %0,24\;C %0,%1\";
414 [(set_attr "length" "18")]
418 ; cmpdf instruction pattern(s).
423 (compare (match_operand:DF 0 "general_operand" "f,mF")
424 (match_operand:DF 1 "general_operand" "fmF,f")))]
429 if (FP_REG_P (operands[0]))
431 if (FP_REG_P (operands[1]))
433 mvs_check_page (0, 2, 0);
434 return \"CDR %0,%1\";
436 mvs_check_page (0, 4, 0);
439 cc_status.flags |= CC_REVERSED;
440 mvs_check_page (0, 4, 0);
443 [(set_attr "length" "4")]
447 ; cmpsf instruction pattern(s).
452 (compare (match_operand:SF 0 "general_operand" "f,mF")
453 (match_operand:SF 1 "general_operand" "fmF,f")))]
458 if (FP_REG_P (operands[0]))
460 if (FP_REG_P (operands[1]))
462 mvs_check_page (0, 2, 0);
463 return \"CER %0,%1\";
465 mvs_check_page (0, 4, 0);
468 cc_status.flags |= CC_REVERSED;
469 mvs_check_page (0, 4, 0);
472 [(set_attr "length" "4")]
476 ; cmpstrsi instruction pattern(s).
479 (define_expand "cmpstrsi"
480 [(set (match_operand:SI 0 "general_operand" "")
481 (compare (match_operand:BLK 1 "general_operand" "")
482 (match_operand:BLK 2 "general_operand" "")))
483 (use (match_operand:SI 3 "general_operand" ""))
484 (use (match_operand:SI 4 "" ""))]
490 op1 = XEXP (operands[1], 0);
491 if (GET_CODE (op1) == REG
492 || (GET_CODE (op1) == PLUS && GET_CODE (XEXP (op1, 0)) == REG
493 && GET_CODE (XEXP (op1, 1)) == CONST_INT
494 && (unsigned) INTVAL (XEXP (op1, 1)) < 4096))
500 op1 = gen_rtx_MEM (BLKmode, copy_to_mode_reg (SImode, op1));
503 op2 = XEXP (operands[2], 0);
504 if (GET_CODE (op2) == REG
505 || (GET_CODE (op2) == PLUS && GET_CODE (XEXP (op2, 0)) == REG
506 && GET_CODE (XEXP (op2, 1)) == CONST_INT
507 && (unsigned) INTVAL (XEXP (op2, 1)) < 4096))
513 op2 = gen_rtx_MEM (BLKmode, copy_to_mode_reg (SImode, op2));
516 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
518 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
519 gen_rtx_SET (VOIDmode, operands[0],
520 gen_rtx_COMPARE (VOIDmode, op1, op2)),
521 gen_rtx_USE (VOIDmode, operands[3]))));
525 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
526 rtx reg1 = gen_reg_rtx (DImode);
527 rtx reg2 = gen_reg_rtx (DImode);
528 rtx result = operands[0];
529 rtx mem1 = operands[1];
530 rtx mem2 = operands[2];
531 rtx len = operands[3];
532 if (!CONSTANT_P (len))
533 len = force_reg (SImode, len);
535 /* Load up the address+length pairs. */
536 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
537 emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 0),
538 force_operand (XEXP (mem1, 0), NULL_RTX));
539 emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 1), len);
541 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg2));
542 emit_move_insn (gen_rtx_SUBREG (SImode, reg2, 0),
543 force_operand (XEXP (mem2, 0), NULL_RTX));
544 emit_move_insn (gen_rtx_SUBREG (SImode, reg2, 1), len);
547 emit_insn (gen_cmpstrsi_1 (result, reg1, reg2));
552 ; Compare a block that is less than 256 bytes in length.
555 [(set (match_operand:SI 0 "register_operand" "=d")
556 (compare (match_operand:BLK 1 "s_operand" "m")
557 (match_operand:BLK 2 "s_operand" "m")))
558 (use (match_operand:QI 3 "immediate_operand" "I"))]
559 "((unsigned) INTVAL (operands[3]) < 256)"
563 mvs_check_page (0, 22, 0);
564 return \"LA %0,%1\;CLC %O1(%c3,%R1),%2\;BH *+12\;BL *+6\;SLR %0,%0\;LNR %0,%0\";
566 [(set_attr "length" "22")]
569 ; Compare a block that is larger than 255 bytes in length.
571 (define_insn "cmpstrsi_1"
572 [(set (match_operand:SI 0 "register_operand" "+d")
574 (mem:BLK (subreg:SI (match_operand:DI 1 "register_operand" "+d") 0))
575 (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "+d") 0))))
578 (clobber (match_dup 1))
579 (clobber (match_dup 2))]
584 mvs_check_page (0, 18, 0);
585 return \"LA %0,1(0,0)\;CLCL %1,%2\;BH *+12\;BL *+6\;SLR %0,%0\;LNR %0,%0\";
587 [(set_attr "length" "18")]
591 ;;- Move instructions.
595 ; movdi instruction pattern(s).
599 ;; [(set (match_operand:DI 0 "r_or_s_operand" "=dm")
600 ;; (match_operand:DI 1 "r_or_s_operand" "dim*fF"))]
601 [(set (match_operand:DI 0 "r_or_s_operand" "=dS,m")
602 (match_operand:DI 1 "r_or_s_operand" "diS*fF,d*fF"))]
604 "TARGET_CHAR_INSTRUCTIONS"
608 if (REG_P (operands[0]))
610 if (FP_REG_P (operands[1]))
612 mvs_check_page (0, 8, 0);
613 return \"STD %1,140(,13)\;LM %0,%N0,140(13)\";
615 if (REG_P (operands[1]))
617 mvs_check_page (0, 4, 0);
618 return \"LR %0,%1\;LR %N0,%N1\";
620 if (operands[1] == const0_rtx)
623 mvs_check_page (0, 4, 0);
624 return \"SLR %0,%0\;SLR %N0,%N0\";
626 if (GET_CODE (operands[1]) == CONST_INT
627 && (unsigned) INTVAL (operands[1]) < 4096)
630 mvs_check_page (0, 6, 0);
631 return \"SLR %0,%0\;LA %N0,%c1(0,0)\";
633 if (GET_CODE (operands[1]) == CONST_INT)
635 CC_STATUS_SET (operands[0], operands[1]);
636 mvs_check_page (0, 8, 0);
637 return \"L %0,%1\;SRDA %0,32\";
639 mvs_check_page (0, 4, 0);
640 return \"LM %0,%N0,%1\";
642 else if (FP_REG_P (operands[1]))
644 mvs_check_page (0, 4, 0);
645 return \"STD %1,%0\";
647 else if (REG_P (operands[1]))
649 mvs_check_page (0, 4, 0);
650 /* can't use stm otherwise stm r6,r7,0(r10,r13) can happen */
651 return \"STM %1,%N1,%0\";
652 /* return \"ST %1,%0\;ST %N1,4+%0\"; */
654 mvs_check_page (0, 6, 0);
655 return \"MVC %O0(8,%R0),%W1\";
657 [(set_attr "length" "8")]
661 ;; [(set (match_operand:DI 0 "general_operand" "=d,dm")
662 ;; (match_operand:DI 1 "general_operand" "dimF,*fd"))]
663 [(set (match_operand:DI 0 "general_operand" "=d,dm")
664 (match_operand:DI 1 "r_or_s_operand" "diSF,*fd"))]
669 if (REG_P (operands[0]))
671 if (FP_REG_P (operands[1]))
673 mvs_check_page (0, 8, 0);
674 return \"STD %1,140(,13)\;LM %0,%N0,140(13)\";
676 if (REG_P (operands[1]))
678 mvs_check_page (0, 4, 0);
679 return \"LR %0,%1\;LR %N0,%N1\";
681 if (operands[1] == const0_rtx)
684 mvs_check_page (0, 4, 0);
685 return \"SLR %0,%0\;SLR %N0,%N0\";
687 if (GET_CODE (operands[1]) == CONST_INT
688 && (unsigned) INTVAL (operands[1]) < 4096)
691 mvs_check_page (0, 6, 0);
692 return \"SLR %0,%0\;LA %N0,%c1(0,0)\";
694 if (GET_CODE (operands[1]) == CONST_INT)
696 CC_STATUS_SET (operands[0], operands[1]);
697 mvs_check_page (0, 8, 0);
698 return \"L %0,%1\;SRDA %0,32\";
700 mvs_check_page (0, 4, 0);
701 return \"LM %0,%N0,%1\";
703 else if (FP_REG_P (operands[1]))
705 mvs_check_page (0, 4, 0);
706 return \"STD %1,%0\";
708 else if (REG_P (operands[1]))
710 /* hack alert -- for some reason, %N0 doesn't work
711 * when the mem ref is e.g. 168(r13,r1) ...
712 * add 4 and pray for the best .. */
713 mvs_check_page (0, 8, 0);
714 return \"ST %1,%0\;ST %N1,4+%N0\";
716 /* this is almost certainly not what is desired, let it break ... */
717 mvs_check_page (0, 8, 0);
718 return \"xxxST %1,%0\;ST %N1,%N0\";
720 [(set_attr "length" "8")]
723 ;; we have got to provide a movdi alternative that will go from
724 ;; register to memory & back in its full glory. However, we try to
725 ;; discourage its use by listing this alternative last.
726 ;; The problem is that the instructions above only provide
727 ;; S-form style (base + displacement) mem access, while the
728 ;; below provvides the full (base+index+displacement) RX-form.
729 ;; These are rarely needed, but when needed they're needed.
732 [(set (match_operand:DI 0 "general_operand" "=d,???m")
733 (match_operand:DI 1 "general_operand" "???m,d"))]
739 if (REG_P (operands[0]))
741 mvs_check_page (0, 8, 0);
742 return \"L %0,%1\;L %N0,4+%N1\";
744 else if (REG_P (operands[1]))
746 mvs_check_page (0, 8, 0);
747 return \"ST %1,%0\;ST %N1,4+%N0\";
749 mvs_check_page (0, 6, 0);
750 /* should never get here ... */
751 return \"xxxxxxMVC %O0(8,%R0),%W1\";
753 [(set_attr "length" "8")]
757 ; movsi instruction pattern(s).
761 ;; [(set (match_operand:SI 0 "r_or_s_operand" "=dm,d,dm")
762 ;; (match_operand:SI 1 "r_or_s_operand" "diR,dim,*fF"))]
763 [(set (match_operand:SI 0 "r_or_s_operand" "=d,dS,dm")
764 (match_operand:SI 1 "general_operand" "dim,diS,di*fF"))]
766 "TARGET_CHAR_INSTRUCTIONS"
770 if (REG_P (operands[0]))
772 if (FP_REG_P (operands[1]))
774 mvs_check_page (0, 8, 0);
775 return \"STE %1,140(,13)\;L %0,140(,13)\";
777 if (REG_P (operands[1]))
779 mvs_check_page (0, 2, 0);
782 if (operands[1] == const0_rtx)
785 mvs_check_page (0, 2, 0);
786 return \"SLR %0,%0\";
788 if (GET_CODE (operands[1]) == CONST_INT
789 && (unsigned) INTVAL (operands[1]) < 4096)
791 mvs_check_page (0, 4, 0);
792 return \"LA %0,%c1(0,0)\";
794 mvs_check_page (0, 4, 0);
797 else if (FP_REG_P (operands[1]))
799 mvs_check_page (0, 4, 0);
800 return \"STE %1,%0\";
802 else if (REG_P (operands[1]))
804 mvs_check_page (0, 4, 0);
807 mvs_check_page (0, 6, 0);
808 return \"MVC %O0(4,%R0),%1\";
810 [(set_attr "length" "8")]
814 [(set (match_operand:SI 0 "general_operand" "=d,dm")
815 (match_operand:SI 1 "general_operand" "dimF,*fd"))]
820 if (REG_P (operands[0]))
822 if (FP_REG_P (operands[1]))
824 mvs_check_page (0, 8, 0);
825 return \"STE %1,140(,13)\;L %0,140(,13)\";
827 if (REG_P (operands[1]))
829 mvs_check_page (0, 2, 0);
832 if (operands[1] == const0_rtx)
835 mvs_check_page (0, 2, 0);
836 return \"SLR %0,%0\";
838 if (GET_CODE (operands[1]) == CONST_INT
839 && (unsigned) INTVAL (operands[1]) < 4096)
841 mvs_check_page (0, 4, 0);
842 return \"LA %0,%c1(0,0)\";
844 mvs_check_page (0, 4, 0);
847 else if (FP_REG_P (operands[1]))
849 mvs_check_page (0, 4, 0);
850 return \"STE %1,%0\";
852 mvs_check_page (0, 4, 0);
855 [(set_attr "length" "8")]
858 ;(define_expand "movsi"
859 ; [(set (match_operand:SI 0 "general_operand" "=d,dm")
860 ; (match_operand:SI 1 "general_operand" "dimF,*fd"))]
867 ; if (GET_CODE (op0) == CONST
868 ; && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SYMBOL_REF
869 ; && SYMBOL_REF_FLAG (XEXP (XEXP (op0, 0), 0)))
871 ; op0 = gen_rtx_MEM (SImode, copy_to_mode_reg (SImode, XEXP (op0, 0)));
875 ; if (GET_CODE (op1) == CONST
876 ; && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF
877 ; && SYMBOL_REF_FLAG (XEXP (XEXP (op1, 0), 0)))
879 ; op1 = gen_rtx_MEM (SImode, copy_to_mode_reg (SImode, XEXP (op1, 0)));
882 ; emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
887 ; movhi instruction pattern(s).
891 [(set (match_operand:HI 0 "r_or_s_operand" "=g")
892 (match_operand:HI 1 "r_or_s_operand" "g"))]
893 "TARGET_CHAR_INSTRUCTIONS"
897 if (REG_P (operands[0]))
899 if (REG_P (operands[1]))
901 mvs_check_page (0, 2, 0);
904 if (operands[1] == const0_rtx)
907 mvs_check_page (0, 2, 0);
908 return \"SLR %0,%0\";
910 if (GET_CODE (operands[1]) == CONST_INT
911 && (unsigned) INTVAL (operands[1]) < 4096)
913 mvs_check_page (0, 4, 0);
914 return \"LA %0,%c1(0,0)\";
916 if (GET_CODE (operands[1]) == CONST_INT)
918 mvs_check_page (0, 4, 0);
919 return \"LH %0,%H1\";
921 mvs_check_page (0, 4, 0);
924 else if (REG_P (operands[1]))
926 mvs_check_page (0, 4, 0);
927 return \"STH %1,%0\";
929 if (GET_CODE (operands[1]) == CONST_INT)
931 mvs_check_page (0, 6, 0);
932 return \"MVC %O0(2,%R0),%H1\";
934 mvs_check_page (0, 6, 0);
935 return \"MVC %O0(2,%R0),%1\";
937 [(set_attr "length" "6")]
941 [(set (match_operand:HI 0 "general_operand" "=d,m")
942 (match_operand:HI 1 "general_operand" "g,d"))]
947 if (REG_P (operands[0]))
949 if (REG_P (operands[1]))
951 mvs_check_page (0, 2, 0);
954 if (operands[1] == const0_rtx)
957 mvs_check_page (0, 2, 0);
958 return \"SLR %0,%0\";
960 if (GET_CODE (operands[1]) == CONST_INT
961 && (unsigned) INTVAL (operands[1]) < 4096)
963 mvs_check_page (0, 4, 0);
964 return \"LA %0,%c1(0,0)\";
966 if (GET_CODE (operands[1]) == CONST_INT)
968 mvs_check_page (0, 4, 0);
969 return \"LH %0,%H1\";
971 mvs_check_page (0, 4, 0);
974 mvs_check_page (0, 4, 0);
975 return \"STH %1,%0\";
977 [(set_attr "length" "4")]
981 ; movqi instruction pattern(s).
985 [(set (match_operand:QI 0 "r_or_s_operand" "=g")
986 (match_operand:QI 1 "r_or_s_operand" "g"))]
987 "TARGET_CHAR_INSTRUCTIONS"
991 if (REG_P (operands[0]))
993 if (REG_P (operands[1]))
995 mvs_check_page (0, 2, 0);
998 if (operands[1] == const0_rtx)
1001 mvs_check_page (0, 2, 0);
1002 return \"SLR %0,%0\";
1004 if (GET_CODE (operands[1]) == CONST_INT)
1006 if ((INTVAL (operands[1]) >= 0)
1007 && (unsigned) INTVAL (operands[1]) < 4096)
1009 mvs_check_page (0, 4, 0);
1010 return \"LA %0,%c1(0,0)\";
1012 mvs_check_page (0, 4, 0);
1013 return \"L %0,=F'%c1'\";
1015 mvs_check_page (0, 4, 0);
1016 return \"IC %0,%1\";
1018 else if (REG_P (operands[1]))
1020 mvs_check_page (0, 4, 0);
1021 return \"STC %1,%0\";
1023 else if (GET_CODE (operands[1]) == CONST_INT)
1025 mvs_check_page (0, 4, 0);
1026 return \"MVI %0,%B1\";
1028 mvs_check_page (0, 6, 0);
1029 return \"MVC %O0(1,%R0),%1\";
1031 [(set_attr "length" "6")]
1034 (define_insn "movqi"
1035 [(set (match_operand:QI 0 "general_operand" "=d,m")
1036 (match_operand:QI 1 "general_operand" "g,d"))]
1040 check_label_emit ();
1041 if (REG_P (operands[0]))
1043 if (REG_P (operands[1]))
1045 mvs_check_page (0, 2, 0);
1046 return \"LR %0,%1\";
1048 if (operands[1] == const0_rtx)
1051 mvs_check_page (0, 2, 0);
1052 return \"SLR %0,%0\";
1054 if (GET_CODE (operands[1]) == CONST_INT)
1056 if ((INTVAL (operands[1]) >= 0)
1057 && (unsigned) INTVAL (operands[1]) < 4096)
1059 mvs_check_page (0, 4, 0);
1060 return \"LA %0,%c1(0,0)\";
1062 mvs_check_page (0, 4, 0);
1063 return \"L %0,=F'%c1'\";
1065 mvs_check_page (0, 4, 0);
1066 return \"IC %0,%1\";
1068 mvs_check_page (0, 4, 0);
1069 return \"STC %1,%0\";
1071 [(set_attr "length" "4")]
1075 ; movstrictqi instruction pattern(s).
1078 (define_insn "movstrictqi"
1079 [(set (strict_low_part (match_operand:QI 0 "general_operand" "=d"))
1080 (match_operand:QI 1 "general_operand" "g"))]
1084 check_label_emit ();
1085 if (REG_P (operands[1]))
1087 mvs_check_page (0, 8, 0);
1088 return \"STC %1,140(,13)\;IC %0,140(,13)\";
1090 mvs_check_page (0, 4, 0);
1091 return \"IC %0,%1\";
1093 [(set_attr "length" "8")]
1097 ; movstricthi instruction pattern(s).
1101 [(set (strict_low_part (match_operand:HI 0 "register_operand" "=d"))
1102 (match_operand:HI 1 "r_or_s_operand" "g"))]
1106 check_label_emit ();
1107 if (REG_P (operands[1]))
1109 mvs_check_page (0, 8, 0);
1110 return \"STH %1,140(,13)\;ICM %0,3,140(13)\";
1112 else if (GET_CODE (operands[1]) == CONST_INT)
1114 mvs_check_page (0, 4, 0);
1115 return \"ICM %0,3,%H1\";
1117 mvs_check_page (0, 4, 0);
1118 return \"ICM %0,3,%1\";
1120 [(set_attr "length" "8")]
1123 (define_insn "movstricthi"
1124 [(set (strict_low_part (match_operand:HI 0 "general_operand" "=dm"))
1125 (match_operand:HI 1 "general_operand" "d"))]
1129 check_label_emit ();
1130 if (REG_P (operands[0]))
1132 mvs_check_page (0, 8, 0);
1133 return \"STH %1,140(,13)\;ICM %0,3,140(13)\";
1135 mvs_check_page (0, 4, 0);
1136 return \"STH %1,%0\";
1138 [(set_attr "length" "8")]
1142 ; movdf instruction pattern(s).
1146 ;; [(set (match_operand:DF 0 "r_or_s_operand" "=fm,fm,*dm")
1147 ;; (match_operand:DF 1 "r_or_s_operand" "fmF,*dm,fmF"))]
1148 [(set (match_operand:DF 0 "general_operand" "=f,m,fS,*dS,???d")
1149 (match_operand:DF 1 "general_operand" "fmF,fF,*dS,fSF,???d"))]
1151 "TARGET_CHAR_INSTRUCTIONS"
1154 check_label_emit ();
1155 if (FP_REG_P (operands[0]))
1157 if (FP_REG_P (operands[1]))
1159 mvs_check_page (0, 2, 0);
1160 return \"LDR %0,%1\";
1162 if (REG_P (operands[1]))
1164 mvs_check_page (0, 8, 0);
1165 return \"STM %1,%N1,140(13)\;LD %0,140(,13)\";
1167 if (operands[1] == const0_rtx)
1169 CC_STATUS_SET (operands[0], operands[1]);
1170 mvs_check_page (0, 2, 0);
1171 return \"SDR %0,%0\";
1173 mvs_check_page (0, 4, 0);
1174 return \"LD %0,%1\";
1176 if (REG_P (operands[0]))
1178 if (FP_REG_P (operands[1]))
1180 mvs_check_page (0, 12, 0);
1181 return \"STD %1,140(,13)\;LM %0,%N0,140(13)\";
1183 if (REG_P (operands[1]))
1185 mvs_check_page (0, 4, 0);
1186 return \"LR %0,%1\;LR %N0,%N1\";
1188 mvs_check_page (0, 4, 0);
1189 return \"LM %0,%N0,%1\";
1191 else if (FP_REG_P (operands[1]))
1193 mvs_check_page (0, 4, 0);
1194 return \"STD %1,%0\";
1196 else if (REG_P (operands[1]))
1198 mvs_check_page (0, 4, 0);
1199 return \"STM %1,%N1,%0\";
1201 mvs_check_page (0, 6, 0);
1202 return \"MVC %O0(8,%R0),%W1\";
1204 [(set_attr "length" "12")]
1207 (define_insn "movdf"
1208 ;; [(set (match_operand:DF 0 "general_operand" "=f,fm,m,*d")
1209 ;; (match_operand:DF 1 "general_operand" "fmF,*d,f,fmF"))]
1210 [(set (match_operand:DF 0 "general_operand" "=f,m,fS,*d,???d")
1211 (match_operand:DF 1 "general_operand" "fmF,f,*d,SfF,???d"))]
1216 check_label_emit ();
1217 if (FP_REG_P (operands[0]))
1219 if (FP_REG_P (operands[1]))
1221 mvs_check_page (0, 2, 0);
1222 return \"LDR %0,%1\";
1224 if (REG_P (operands[1]))
1226 mvs_check_page (0, 8, 0);
1227 return \"STM %1,%N1,140(13)\;LD %0,140(,13)\";
1229 if (operands[1] == const0_rtx)
1231 CC_STATUS_SET (operands[0], operands[1]);
1232 mvs_check_page (0, 2, 0);
1233 return \"SDR %0,%0\";
1235 mvs_check_page (0, 4, 0);
1236 return \"LD %0,%1\";
1238 else if (REG_P (operands[0]))
1240 if (FP_REG_P (operands[1]))
1242 mvs_check_page (0, 12, 0);
1243 return \"STD %1,140(,13)\;LM %0,%N0,140(13)\";
1245 if (REG_P (operands[1]))
1247 mvs_check_page (0, 4, 0);
1248 return \"LR %0,%1\;LR %N0,%N1\";
1250 mvs_check_page (0, 4, 0);
1251 return \"LM %0,%N0,%1\";
1253 else if (FP_REG_P (operands[1]))
1255 mvs_check_page (0, 4, 0);
1256 return \"STD %1,%0\";
1258 mvs_check_page (0, 4, 0);
1259 return \"STM %1,%N1,%0\";
1261 [(set_attr "length" "12")]
1265 ; movsf instruction pattern(s).
1269 ;; [(set (match_operand:SF 0 "r_or_s_operand" "=fm,fm,*dm")
1270 ;; (match_operand:SF 1 "r_or_s_operand" "fmF,*dm,fmF"))]
1271 ;; [(set (match_operand:SF 0 "general_operand" "=f,m,fm,*d,S")
1272 ;; (match_operand:SF 1 "general_operand" "fmF,fF,*d,fmF,S"))]
1273 [(set (match_operand:SF 0 "general_operand" "=f*d,fm,S,???d")
1274 (match_operand:SF 1 "general_operand" "fmF,fF*d,S,???d"))]
1276 "TARGET_CHAR_INSTRUCTIONS"
1279 check_label_emit ();
1280 if (FP_REG_P (operands[0]))
1282 if (FP_REG_P (operands[1]))
1284 mvs_check_page (0, 2, 0);
1285 return \"LER %0,%1\";
1287 if (REG_P (operands[1]))
1289 mvs_check_page (0, 8, 0);
1290 return \"ST %1,140(,13)\;LE %0,140(,13)\";
1292 if (operands[1] == const0_rtx)
1294 CC_STATUS_SET (operands[0], operands[1]);
1295 mvs_check_page (0, 2, 0);
1296 return \"SER %0,%0\";
1298 mvs_check_page (0, 4, 0);
1299 return \"LE %0,%1\";
1301 else if (REG_P (operands[0]))
1303 if (FP_REG_P (operands[1]))
1305 mvs_check_page (0, 8, 0);
1306 return \"STE %1,140(,13)\;L %0,140(,13)\";
1308 if (REG_P (operands[1]))
1310 mvs_check_page (0, 2, 0);
1311 return \"LR %0,%1\";
1313 mvs_check_page (0, 4, 0);
1316 else if (FP_REG_P (operands[1]))
1318 mvs_check_page (0, 4, 0);
1319 return \"STE %1,%0\";
1321 else if (REG_P (operands[1]))
1323 mvs_check_page (0, 4, 0);
1324 return \"ST %1,%0\";
1326 mvs_check_page (0, 6, 0);
1327 return \"MVC %O0(4,%R0),%1\";
1329 [(set_attr "length" "8")]
1332 (define_insn "movsf"
1333 [(set (match_operand:SF 0 "general_operand" "=f,fm,m,*d")
1334 (match_operand:SF 1 "general_operand" "fmF,*d,f,fmF"))]
1338 check_label_emit ();
1339 if (FP_REG_P (operands[0]))
1341 if (FP_REG_P (operands[1]))
1343 mvs_check_page (0, 2, 0);
1344 return \"LER %0,%1\";
1346 if (REG_P (operands[1]))
1348 mvs_check_page (0, 8, 0);
1349 return \"ST %1,140(,13)\;LE %0,140(,13)\";
1351 if (operands[1] == const0_rtx)
1353 CC_STATUS_SET (operands[0], operands[1]);
1354 mvs_check_page (0, 2, 0);
1355 return \"SER %0,%0\";
1357 mvs_check_page (0, 4, 0);
1358 return \"LE %0,%1\";
1360 else if (REG_P (operands[0]))
1362 if (FP_REG_P (operands[1]))
1364 mvs_check_page (0, 8, 0);
1365 return \"STE %1,140(,13)\;L %0,140(,13)\";
1367 mvs_check_page (0, 4, 0);
1370 else if (FP_REG_P (operands[1]))
1372 mvs_check_page (0, 4, 0);
1373 return \"STE %1,%0\";
1375 mvs_check_page (0, 4, 0);
1376 return \"ST %1,%0\";
1378 [(set_attr "length" "8")]
1382 ; clrstrsi instruction pattern(s).
1383 ; memset a block of bytes to zero.
1384 ; block must be less than 16M (24 bits) in length
1386 (define_expand "clrstrsi"
1387 [(set (match_operand:BLK 0 "general_operand" "g")
1389 (use (match_operand:SI 1 "general_operand" ""))
1390 (match_operand 2 "" "")]
1395 XXX bogus, i think, unless change_address has a side effet we need
1398 op0 = XEXP (operands[0], 0);
1399 if (GET_CODE (op0) == REG
1400 || (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 0)) == REG
1401 && GET_CODE (XEXP (op0, 1)) == CONST_INT
1402 && (unsigned) INTVAL (XEXP (op0, 1)) < 4096))
1405 op0 = change_address (operands[0], VOIDmode,
1406 copy_to_mode_reg (SImode, op0));
1410 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1411 rtx reg1 = gen_reg_rtx (DImode);
1412 rtx reg2 = gen_reg_rtx (DImode);
1413 rtx mem1 = operands[0];
1414 rtx zippo = gen_rtx_CONST_INT (SImode, 0);
1415 rtx len = operands[1];
1416 if (!CONSTANT_P (len))
1417 len = force_reg (SImode, len);
1419 /* Load up the address+length pairs. */
1420 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
1421 emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 0),
1422 force_operand (XEXP (mem1, 0), NULL_RTX));
1423 emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 1), len);
1425 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg2));
1426 emit_move_insn (gen_rtx_SUBREG (SImode, reg2, 0), zippo);
1427 emit_move_insn (gen_rtx_SUBREG (SImode, reg2, 1), zippo);
1430 emit_insn (gen_movstrsi_1 (reg1, reg2));
1436 ; movstrsi instruction pattern(s).
1437 ; block must be less than 16M (24 bits) in length
1439 (define_expand "movstrsi"
1440 [(set (match_operand:BLK 0 "general_operand" "")
1441 (match_operand:BLK 1 "general_operand" ""))
1442 (use (match_operand:SI 2 "general_operand" ""))
1443 (match_operand 3 "" "")]
1449 op0 = XEXP (operands[0], 0);
1450 if (GET_CODE (op0) == REG
1451 || (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 0)) == REG
1452 && GET_CODE (XEXP (op0, 1)) == CONST_INT
1453 && (unsigned) INTVAL (XEXP (op0, 1)) < 4096))
1456 op0 = change_address (operands[0], VOIDmode,
1457 copy_to_mode_reg (SImode, op0));
1459 op1 = XEXP (operands[1], 0);
1460 if (GET_CODE (op1) == REG
1461 || (GET_CODE (op1) == PLUS && GET_CODE (XEXP (op1, 0)) == REG
1462 && GET_CODE (XEXP (op1, 1)) == CONST_INT
1463 && (unsigned) INTVAL (XEXP (op1, 1)) < 4096))
1466 op1 = change_address (operands[1], VOIDmode,
1467 copy_to_mode_reg (SImode, op1));
1469 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 256)
1470 emit_insn (gen_rtx_PARALLEL (VOIDmode,
1472 gen_rtx_SET (VOIDmode, op0, op1),
1473 gen_rtx_USE (VOIDmode, operands[2]))));
1477 /* implementation provided by Richard Henderson <rth@cygnus.com> */
1478 rtx reg1 = gen_reg_rtx (DImode);
1479 rtx reg2 = gen_reg_rtx (DImode);
1480 rtx mem1 = operands[0];
1481 rtx mem2 = operands[1];
1482 rtx len = operands[2];
1483 if (!CONSTANT_P (len))
1484 len = force_reg (SImode, len);
1486 /* Load up the address+length pairs. */
1487 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
1488 emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 0),
1489 force_operand (XEXP (mem1, 0), NULL_RTX));
1490 emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 1), len);
1492 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg2));
1493 emit_move_insn (gen_rtx_SUBREG (SImode, reg2, 0),
1494 force_operand (XEXP (mem2, 0), NULL_RTX));
1495 emit_move_insn (gen_rtx_SUBREG (SImode, reg2, 1), len);
1498 emit_insn (gen_movstrsi_1 (reg1, reg2));
1503 ; Move a block that is less than 256 bytes in length.
1506 [(set (match_operand:BLK 0 "s_operand" "=m")
1507 (match_operand:BLK 1 "s_operand" "m"))
1508 (use (match_operand 2 "immediate_operand" "I"))]
1509 "((unsigned) INTVAL (operands[2]) < 256)"
1512 check_label_emit ();
1513 mvs_check_page (0, 6, 0);
1514 return \"MVC %O0(%c2,%R0),%1\";
1516 [(set_attr "length" "6")]
1519 ; Move a block that is larger than 255 bytes in length.
1521 (define_insn "movstrsi_1"
1522 [(set (mem:BLK (subreg:SI (match_operand:DI 0 "register_operand" "+d") 0))
1523 (mem:BLK (subreg:SI (match_operand:DI 1 "register_operand" "+d") 0)))
1526 (clobber (match_dup 0))
1527 (clobber (match_dup 1))]
1531 check_label_emit ();
1532 mvs_check_page (0, 2, 0);
1533 return \"MVCL %0,%1\";
1535 [(set_attr "length" "2")]
1539 ;;- Conversion instructions.
1543 ; extendsidi2 instruction pattern(s).
1546 (define_expand "extendsidi2"
1547 [(set (match_operand:DI 0 "register_operand" "=d")
1548 (sign_extend:DI (match_operand:SI 1 "general_operand" "")))]
1552 if (GET_CODE (operands[1]) != CONST_INT)
1554 emit_insn (gen_rtx_SET (VOIDmode,
1555 operand_subword (operands[0], 0, 1, DImode), operands[1]));
1556 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
1557 gen_rtx_ASHIFTRT (DImode, operands[0],
1558 gen_rtx_CONST_INT (SImode, 32))));
1562 if (INTVAL (operands[1]) < 0)
1564 emit_insn (gen_rtx_SET (VOIDmode,
1565 operand_subword (operands[0], 0, 1, DImode),
1566 gen_rtx_CONST_INT (SImode, -1)));
1570 emit_insn (gen_rtx_SET (VOIDmode,
1571 operand_subword (operands[0], 0, 1, DImode),
1572 gen_rtx_CONST_INT (SImode, 0)));
1574 emit_insn (gen_rtx_SET (VOIDmode, gen_lowpart (SImode, operands[0]),
1581 ; extendhisi2 instruction pattern(s).
1584 (define_insn "extendhisi2"
1585 [(set (match_operand:SI 0 "general_operand" "=d,m")
1586 (sign_extend:SI (match_operand:HI 1 "general_operand" "g,d")))]
1590 check_label_emit ();
1591 if (REG_P (operands[0]))
1593 if (REG_P (operands[1]))
1595 if (REGNO (operands[0]) != REGNO (operands[1]))
1597 mvs_check_page (0, 10, 0);
1598 return \"LR %0,%1\;SLL %0,16\;SRA %0,16\";
1601 return \"\"; /* Should be empty. 16-bits regs are always 32-bits. */
1603 if (operands[1] == const0_rtx)
1606 mvs_check_page (0, 2, 0);
1607 return \"SLR %0,%0\";
1609 if (GET_CODE (operands[1]) == CONST_INT
1610 && (unsigned) INTVAL (operands[1]) < 4096)
1612 mvs_check_page (0, 4, 0);
1613 return \"LA %0,%c1(0,0)\";
1615 if (GET_CODE (operands[1]) == CONST_INT)
1617 mvs_check_page (0, 4, 0);
1618 return \"LH %0,%H1\";
1620 mvs_check_page (0, 4, 0);
1621 return \"LH %0,%1\";
1623 mvs_check_page (0, 12, 0);
1624 return \"SLL %1,16\;SRA %1,16\;ST %1,%0\";
1626 [(set_attr "length" "12")]
1630 ; extendqisi2 instruction pattern(s).
1633 (define_insn "extendqisi2"
1634 [(set (match_operand:SI 0 "general_operand" "=d")
1635 (sign_extend:SI (match_operand:QI 1 "general_operand" "0mi")))]
1639 check_label_emit ();
1640 CC_STATUS_SET (operands[0], operands[1]);
1641 if (REG_P (operands[1]))
1643 mvs_check_page (0, 8, 0);
1644 return \"SLL %0,24\;SRA %0,24\";
1646 if (s_operand (operands[1], GET_MODE (operands[1])))
1648 mvs_check_page (0, 8, 0);
1649 return \"ICM %0,8,%1\;SRA %0,24\";
1651 mvs_check_page (0, 12, 0);
1652 return \"IC %0,%1\;SLL %0,24\;SRA %0,24\";
1654 [(set_attr "length" "12")]
1658 ; extendqihi2 instruction pattern(s).
1661 (define_insn "extendqihi2"
1662 [(set (match_operand:HI 0 "general_operand" "=d")
1663 (sign_extend:HI (match_operand:QI 1 "general_operand" "0m")))]
1667 check_label_emit ();
1668 CC_STATUS_SET (operands[0], operands[1]);
1669 if (REG_P (operands[1]))
1671 mvs_check_page (0, 8, 0);
1672 return \"SLL %0,24\;SRA %0,24\";
1674 if (s_operand (operands[1], GET_MODE (operands[1])))
1676 mvs_check_page (0, 8, 0);
1677 return \"ICM %0,8,%1\;SRA %0,24\";
1679 mvs_check_page (0, 12, 0);
1680 return \"IC %0,%1\;SLL %0,24\;SRA %0,24\";
1682 [(set_attr "length" "12")]
1686 ; zero_extendsidi2 instruction pattern(s).
1689 (define_expand "zero_extendsidi2"
1690 [(set (match_operand:DI 0 "register_operand" "=d")
1691 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))]
1695 emit_insn (gen_rtx_SET (VOIDmode,
1696 operand_subword (operands[0], 0, 1, DImode), operands[1]));
1697 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
1698 gen_rtx_LSHIFTRT (DImode, operands[0],
1699 gen_rtx_CONST_INT (SImode, 32))));
1704 ; zero_extendhisi2 instruction pattern(s).
1707 (define_insn "zero_extendhisi2"
1708 [(set (match_operand:SI 0 "general_operand" "=d")
1709 (zero_extend:SI (match_operand:HI 1 "general_operand" "0")))]
1713 check_label_emit ();
1714 /* AND only sets zero/not-zero bits not the arithmetic bits ... */
1716 mvs_check_page (0, 4, 4);
1717 return \"N %1,=X'0000FFFF'\";
1719 [(set_attr "length" "4")]
1723 ; zero_extendqisi2 instruction pattern(s).
1726 (define_insn "zero_extendqisi2"
1727 [(set (match_operand:SI 0 "general_operand" "=d,&d")
1728 (zero_extend:SI (match_operand:QI 1 "general_operand" "0i,m")))]
1732 check_label_emit ();
1733 if (REG_P (operands[1]))
1735 /* AND only sets zero/not-zero bits not the arithmetic bits ... */
1737 mvs_check_page (0, 4, 4);
1738 return \"N %0,=X'000000FF'\";
1740 if (GET_CODE (operands[1]) == CONST_INT)
1742 mvs_check_page (0, 4, 0);
1743 return \"LA %0,%c1(0,0)\";
1746 mvs_check_page (0, 8, 0);
1747 return \"SLR %0,%0\;IC %0,%1\";
1749 [(set_attr "length" "8")]
1753 ; zero_extendqihi2 instruction pattern(s).
1756 (define_insn "zero_extendqihi2"
1757 [(set (match_operand:HI 0 "general_operand" "=d,&d")
1758 (zero_extend:HI (match_operand:QI 1 "general_operand" "0i,m")))]
1762 check_label_emit ();
1763 if (REG_P (operands[1]))
1765 /* AND only sets zero/not-zero bits not the arithmetic bits ... */
1767 mvs_check_page (0, 4, 4);
1768 return \"N %0,=X'000000FF'\";
1770 if (GET_CODE (operands[1]) == CONST_INT)
1772 mvs_check_page (0, 4, 0);
1773 return \"LA %0,%c1(0,0)\";
1776 mvs_check_page (0, 8, 0);
1777 return \"SLR %0,%0\;IC %0,%1\";
1779 [(set_attr "length" "8")]
1783 ; truncsihi2 instruction pattern(s).
1786 (define_insn "truncsihi2"
1787 [(set (match_operand:HI 0 "general_operand" "=d,m")
1788 (truncate:HI (match_operand:SI 1 "general_operand" "0,d")))]
1792 check_label_emit ();
1793 if (REG_P (operands[0]))
1795 CC_STATUS_SET (operands[0], operands[1]);
1796 mvs_check_page (0, 8, 0);
1797 return \"SLL %0,16\;SRA %0,16\";
1799 mvs_check_page (0, 4, 0);
1800 return \"STH %1,%0\";
1802 [(set_attr "length" "8")]
1806 ; fix_truncdfsi2 instruction pattern(s).
1809 (define_insn "fix_truncdfsi2"
1810 [(set (match_operand:SI 0 "general_operand" "=d")
1811 (fix:SI (truncate:DF (match_operand:DF 1 "general_operand" "+f"))))
1812 (clobber (reg:DF 16))]
1816 check_label_emit ();
1818 if (REGNO (operands[1]) == 16)
1820 mvs_check_page (0, 12, 8);
1821 return \"AD 0,=XL8'4F08000000000000'\;STD 0,140(,13)\;L %0,144(,13)\";
1823 mvs_check_page (0, 14, 8);
1824 return \"LDR 0,%1\;AD 0,=XL8'4F08000000000000'\;STD 0,140(,13)\;L %0,144(,13)\";
1826 [(set_attr "length" "14")]
1830 ; floatsidf2 instruction pattern(s).
1833 (define_insn "floatsidf2"
1834 [(set (match_operand:DF 0 "general_operand" "=f")
1835 (float:DF (match_operand:SI 1 "general_operand" "d")))]
1839 check_label_emit ();
1841 mvs_check_page (0, 16, 8);
1842 return \"ST %1,144(,13)\;XI 144(13),128\;LD %0,140(,13)\;SD %0,=XL8'4E00000080000000'\";
1844 [(set_attr "length" "16")]
1848 ; truncdfsf2 instruction pattern(s).
1851 (define_insn "truncdfsf2"
1852 [(set (match_operand:SF 0 "general_operand" "=f")
1853 (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
1857 check_label_emit ();
1858 mvs_check_page (0, 2, 0);
1859 return \"LRER %0,%1\";
1861 [(set_attr "length" "2")]
1865 ; extendsfdf2 instruction pattern(s).
1868 (define_insn "extendsfdf2"
1869 [(set (match_operand:DF 0 "general_operand" "=f")
1870 (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
1874 check_label_emit ();
1875 CC_STATUS_SET (0, const0_rtx);
1876 if (FP_REG_P (operands[1]))
1878 if (REGNO (operands[0]) == REGNO (operands[1]))
1880 mvs_check_page (0, 10, 0);
1881 return \"STE %1,140(,13)\;SDR %0,%0\;LE %0,140(,13)\";
1883 mvs_check_page (0, 4, 0);
1884 return \"SDR %0,%0\;LER %0,%1\";
1886 mvs_check_page (0, 6, 0);
1887 return \"SDR %0,%0\;LE %0,%1\";
1889 [(set_attr "length" "10")]
1893 ;;- Add instructions.
1897 ; adddi3 instruction pattern(s).
1900 ;(define_expand "adddi3"
1901 ; [(set (match_operand:DI 0 "general_operand" "")
1902 ; (plus:DI (match_operand:DI 1 "general_operand" "")
1903 ; (match_operand:DI 2 "general_operand" "")))]
1907 ; rtx label = gen_label_rtx ();
1908 ; rtx op0_high = operand_subword (operands[0], 0, 1, DImode);
1909 ; rtx op0_low = gen_lowpart (SImode, operands[0]);
1911 ; emit_insn (gen_rtx_SET (VOIDmode, op0_high,
1912 ; gen_rtx_PLUS (SImode,
1913 ; operand_subword (operands[1], 0, 1, DImode),
1914 ; operand_subword (operands[2], 0, 1, DImode))));
1915 ; emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
1916 ; gen_rtx_SET (VOIDmode, op0_low,
1917 ; gen_rtx_PLUS (SImode, gen_lowpart (SImode, operands[1]),
1918 ; gen_lowpart (SImode, operands[2]))),
1919 ; gen_rtx_USE (VOIDmode, gen_rtx_LABEL_REF (VOIDmode, label)))));
1920 ; emit_insn (gen_rtx_SET (VOIDmode, op0_high,
1921 ; gen_rtx_PLUS (SImode, op0_high,
1922 ; gen_rtx_CONST_INT (SImode, 1))));
1923 ; emit_label (label);
1928 [(set (match_operand:SI 0 "general_operand" "=d")
1929 (plus:SI (match_operand:SI 1 "general_operand" "%0")
1930 (match_operand:SI 2 "general_operand" "g")))
1931 (use (label_ref (match_operand 3 "" "")))
1932 ; (clobber (reg:SI 14))
1939 check_label_emit ();
1940 onpage = mvs_check_label (CODE_LABEL_NUMBER (operands[3]));
1941 if (REG_P (operands[2]))
1945 mvs_check_page (0, 8, 4);
1946 return \"ALR %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
1948 if (mvs_check_page (0, 6, 0))
1950 mvs_check_page (0, 2, 4);
1951 return \"ALR %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
1953 return \"ALR %0,%2\;BC 12,%l3\";
1957 mvs_check_page (0, 10, 4);
1958 return \"AL %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
1960 if (mvs_check_page (0, 8 ,0))
1962 mvs_check_page (0, 2, 4);
1963 return \"AL %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
1965 return \"AL %0,%2\;BC 12,%l3\";
1967 [(set_attr "length" "10")]
1971 ; addsi3 instruction pattern(s).
1973 ; The following insn is used when it is known that operand one is an address,
1974 ; frame, stack or argument pointer, and operand two is a constant that is
1975 ; small enough to fit in the displacement field.
1976 ; Notice that we can't allow the frame pointer to used as a normal register
1977 ; because of this insn.
1981 [(set (match_operand:SI 0 "register_operand" "=d")
1982 (plus:SI (match_operand:SI 1 "general_operand" "%a")
1983 (match_operand:SI 2 "immediate_operand" "J")))]
1984 "((REGNO (operands[1]) == FRAME_POINTER_REGNUM || REGNO (operands[1]) == ARG_POINTER_REGNUM || REGNO (operands[1]) == STACK_POINTER_REGNUM) && (unsigned) INTVAL (operands[2]) < 4096)"
1987 check_label_emit ();
1988 CC_STATUS_INIT; /* add assumes CC but LA doesnt set CC */
1989 mvs_check_page (0, 4, 0);
1990 return \"LA %0,%c2(,%1)\";
1992 [(set_attr "length" "4")]
1995 ; This insn handles additions that are relative to the frame pointer.
1998 [(set (match_operand:SI 0 "register_operand" "=d")
1999 (plus:SI (match_operand:SI 1 "register_operand" "%a")
2000 (match_operand:SI 2 "immediate_operand" "i")))]
2001 "REGNO (operands[1]) == FRAME_POINTER_REGNUM"
2004 check_label_emit ();
2005 if ((unsigned) INTVAL (operands[2]) < 4096)
2007 CC_STATUS_INIT; /* add assumes CC but LA doesnt set CC */
2008 mvs_check_page (0, 4, 0);
2009 return \"LA %0,%c2(,%1)\";
2011 if (REGNO (operands[1]) == REGNO (operands[0]))
2014 mvs_check_page (0, 4, 0);
2017 mvs_check_page (0, 6, 0);
2018 return \"L %0,%2\;AR %0,%1\";
2020 [(set_attr "length" "6")]
2024 ;; The CC status bits for the arithmetic instructions are handled
2025 ;; in the NOTICE_UPDATE_CC macro (yeah???) and so they do not need
2026 ;; to be set below. They only need to be invalidated if *not* set
2027 ;; (e.g. by BCTR) ... yeah I think that's right ...
2030 (define_insn "addsi3"
2031 [(set (match_operand:SI 0 "general_operand" "=d")
2032 (plus:SI (match_operand:SI 1 "general_operand" "%0")
2033 (match_operand:SI 2 "general_operand" "g")))]
2037 check_label_emit ();
2038 if (REG_P (operands[2]))
2040 mvs_check_page (0, 2, 0);
2041 return \"AR %0,%2\";
2043 if (GET_CODE (operands[2]) == CONST_INT)
2045 if (INTVAL (operands[2]) == -1)
2047 CC_STATUS_INIT; /* add assumes CC but BCTR doesnt set CC */
2048 mvs_check_page (0, 2, 0);
2049 return \"BCTR %0,0\";
2052 mvs_check_page (0, 4, 0);
2055 [(set_attr "length" "4")]
2059 ; addhi3 instruction pattern(s).
2062 (define_insn "addhi3"
2063 [(set (match_operand:HI 0 "general_operand" "=d")
2064 (plus:HI (match_operand:HI 1 "general_operand" "%0")
2065 (match_operand:HI 2 "general_operand" "dmi")))]
2069 check_label_emit ();
2070 if (REG_P (operands[2]))
2072 mvs_check_page (0, 8, 0);
2073 return \"STH %2,140(,13)\;AH %0,140(,13)\";
2075 if (GET_CODE (operands[2]) == CONST_INT)
2077 if (INTVAL (operands[2]) == -1)
2079 CC_STATUS_INIT; /* add assumes CC but BCTR doesnt set CC */
2080 mvs_check_page (0, 2, 0);
2081 return \"BCTR %0,0\";
2083 mvs_check_page (0, 4, 0);
2084 return \"AH %0,%H2\";
2086 mvs_check_page (0, 4, 0);
2087 return \"AH %0,%2\";
2089 [(set_attr "length" "8")]
2093 ; addqi3 instruction pattern(s).
2096 (define_insn "addqi3"
2097 [(set (match_operand:QI 0 "general_operand" "=d")
2098 (plus:QI (match_operand:QI 1 "general_operand" "%a")
2099 (match_operand:QI 2 "general_operand" "ai")))]
2103 check_label_emit ();
2104 CC_STATUS_INIT; /* add assumes CC but LA doesnt set CC */
2105 mvs_check_page (0, 4, 0);
2106 if (REG_P (operands[2]))
2107 return \"LA %0,0(%1,%2)\";
2108 return \"LA %0,%B2(,%1)\";
2110 [(set_attr "length" "4")]
2114 ; adddf3 instruction pattern(s).
2117 (define_insn "adddf3"
2118 [(set (match_operand:DF 0 "general_operand" "=f")
2119 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2120 (match_operand:DF 2 "general_operand" "fmF")))]
2124 check_label_emit ();
2125 if (FP_REG_P (operands[2]))
2127 mvs_check_page (0, 2, 0);
2128 return \"ADR %0,%2\";
2130 mvs_check_page (0, 4, 0);
2131 return \"AD %0,%2\";
2133 [(set_attr "length" "4")]
2137 ; addsf3 instruction pattern(s).
2140 (define_insn "addsf3"
2141 [(set (match_operand:SF 0 "general_operand" "=f")
2142 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2143 (match_operand:SF 2 "general_operand" "fmF")))]
2147 check_label_emit ();
2148 if (FP_REG_P (operands[2]))
2150 mvs_check_page (0, 2, 0);
2151 return \"AER %0,%2\";
2153 mvs_check_page (0, 4, 0);
2154 return \"AE %0,%2\";
2156 [(set_attr "length" "4")]
2160 ;;- Subtract instructions.
2164 ; subdi3 instruction pattern(s).
2167 ;(define_expand "subdi3"
2168 ; [(set (match_operand:DI 0 "general_operand" "")
2169 ; (minus:DI (match_operand:DI 1 "general_operand" "")
2170 ; (match_operand:DI 2 "general_operand" "")))]
2174 ; rtx label = gen_label_rtx ();
2175 ; rtx op0_high = operand_subword (operands[0], 0, 1, DImode);
2176 ; rtx op0_low = gen_lowpart (SImode, operands[0]);
2178 ; emit_insn (gen_rtx_SET (VOIDmode, op0_high,
2179 ; gen_rtx_MINUS (SImode,
2180 ; operand_subword (operands[1], 0, 1, DImode),
2181 ; operand_subword (operands[2], 0, 1, DImode))));
2182 ; emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
2183 ; gen_rtx_SET (VOIDmode, op0_low,
2184 ; gen_rtx_MINUS (SImode,
2185 ; gen_lowpart (SImode, operands[1]),
2186 ; gen_lowpart (SImode, operands[2]))),
2187 ; gen_rtx_USE (VOIDmode,
2188 ; gen_rtx_LABEL_REF (VOIDmode, label)))));
2189 ; emit_insn (gen_rtx_SET (VOIDmode, op0_high,
2190 ; gen_rtx_MINUS (SImode, op0_high,
2191 ; gen_rtx_CONST_INT (SImode, 1))));
2192 ; emit_label (label);
2197 [(set (match_operand:SI 0 "general_operand" "=d")
2198 (minus:SI (match_operand:SI 1 "general_operand" "0")
2199 (match_operand:SI 2 "general_operand" "g")))
2200 (use (label_ref (match_operand 3 "" "")))
2201 ; (clobber (reg:SI 14))
2208 check_label_emit ();
2210 onpage = mvs_check_label (CODE_LABEL_NUMBER (operands[3]));
2211 if (REG_P (operands[2]))
2215 mvs_check_page (0, 8, 4);
2216 return \"SLR %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
2218 if (mvs_check_page (0, 6, 0))
2220 mvs_check_page (0, 2, 4);
2221 return \"SLR %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
2223 return \"SLR %0,%2\;BC 12,%l3\";
2227 mvs_check_page (0, 10, 4);
2228 return \"SL %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
2230 if (mvs_check_page (0, 8, 0))
2232 mvs_check_page (0, 2, 4);
2233 return \"SL %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
2235 return \"SL %0,%2\;BC 12,%l3\";
2237 [(set_attr "length" "10")]
2241 ; subsi3 instruction pattern(s).
2244 (define_insn "subsi3"
2245 [(set (match_operand:SI 0 "general_operand" "=d")
2246 (minus:SI (match_operand:SI 1 "general_operand" "0")
2247 (match_operand:SI 2 "general_operand" "g")))]
2251 check_label_emit ();
2252 if (REG_P (operands[2]))
2254 mvs_check_page (0, 2, 0);
2255 return \"SR %0,%2\";
2257 if (operands[2] == const1_rtx)
2259 CC_STATUS_INIT; /* subtract assumes CC but BCTR doesnt set CC */
2260 mvs_check_page (0, 2, 0);
2261 return \"BCTR %0,0\";
2263 mvs_check_page (0, 4, 0);
2266 [(set_attr "length" "4")]
2270 ; subhi3 instruction pattern(s).
2273 (define_insn "subhi3"
2274 [(set (match_operand:HI 0 "general_operand" "=d")
2275 (minus:HI (match_operand:HI 1 "general_operand" "0")
2276 (match_operand:HI 2 "general_operand" "g")))]
2280 check_label_emit ();
2281 if (REG_P (operands[2]))
2283 mvs_check_page (0, 8, 0);
2284 return \"STH %2,140(,13)\;SH %0,140(,13)\";
2286 if (operands[2] == const1_rtx)
2288 CC_STATUS_INIT; /* subtract assumes CC but BCTR doesnt set CC */
2289 mvs_check_page (0, 2, 0);
2290 return \"BCTR %0,0\";
2292 if (GET_CODE (operands[2]) == CONST_INT)
2294 mvs_check_page (0, 4, 0);
2295 return \"SH %0,%H2\";
2297 mvs_check_page (0, 4, 0);
2298 return \"SH %0,%2\";
2300 [(set_attr "length" "8")]
2304 ; subqi3 instruction pattern(s).
2307 (define_expand "subqi3"
2308 [(set (match_operand:QI 0 "general_operand" "=d")
2309 (minus:QI (match_operand:QI 1 "general_operand" "0")
2310 (match_operand:QI 2 "general_operand" "di")))]
2314 if (REG_P (operands[2]))
2316 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2317 gen_rtx_MINUS (QImode, operands[1], operands[2])));
2321 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2322 gen_rtx_PLUS (QImode, operands[1],
2323 negate_rtx (QImode, operands[2]))));
2329 [(set (match_operand:QI 0 "register_operand" "=d")
2330 (minus:QI (match_operand:QI 1 "register_operand" "0")
2331 (match_operand:QI 2 "register_operand" "d")))]
2335 check_label_emit ();
2336 mvs_check_page (0, 2, 0);
2337 return \"SR %0,%2\";
2339 [(set_attr "length" "2")]
2343 ; subdf3 instruction pattern(s).
2346 (define_insn "subdf3"
2347 [(set (match_operand:DF 0 "general_operand" "=f")
2348 (minus:DF (match_operand:DF 1 "general_operand" "0")
2349 (match_operand:DF 2 "general_operand" "fmF")))]
2353 check_label_emit ();
2354 if (FP_REG_P (operands[2]))
2356 mvs_check_page (0, 2, 0);
2357 return \"SDR %0,%2\";
2359 mvs_check_page (0, 4, 0);
2360 return \"SD %0,%2\";
2362 [(set_attr "length" "4")]
2366 ; subsf3 instruction pattern(s).
2369 (define_insn "subsf3"
2370 [(set (match_operand:SF 0 "general_operand" "=f")
2371 (minus:SF (match_operand:SF 1 "general_operand" "0")
2372 (match_operand:SF 2 "general_operand" "fmF")))]
2376 check_label_emit ();
2377 if (FP_REG_P (operands[2]))
2379 mvs_check_page (0, 2, 0);
2380 return \"SER %0,%2\";
2382 mvs_check_page (0, 4, 0);
2383 return \"SE %0,%2\";
2385 [(set_attr "length" "4")]
2389 ;;- Multiply instructions.
2393 ; mulsi3 instruction pattern(s).
2396 (define_expand "mulsi3"
2397 [(set (match_operand:SI 0 "general_operand" "")
2398 (mult:SI (match_operand:SI 1 "general_operand" "")
2399 (match_operand:SI 2 "general_operand" "")))]
2403 if (GET_CODE (operands[1]) == CONST_INT
2404 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K'))
2406 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2407 gen_rtx_MULT (SImode, operands[2], operands[1])));
2409 else if (GET_CODE (operands[2]) == CONST_INT
2410 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))
2412 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2413 gen_rtx_MULT (SImode, operands[1], operands[2])));
2417 rtx r = gen_reg_rtx (DImode);
2419 /* XXX trouble. Below we generate some rtx's that model what
2420 * is really supposed to happen with multiply on the 370/390
2421 * hardware, and that is all well & god. However, during optimization
2422 * it can happen that the two operands are exchanged (after all,
2423 * multiplication is commutitive), in which case the doubleword
2424 * ends up in memory and everything is hosed. The gen_reg_rtx
2425 * should have kept it in a reg ... We hack around this
2426 * below, in the M/MR isntruction pattern, and constrain it to
2427 * \"di\" instead of \"g\". But this still ends up with lots & lots of
2428 * movement between registers & memory and is an awful waste.
2429 * Dunno how to untwist it elegantly; but it seems to work for now.
2431 emit_insn (gen_rtx_SET (VOIDmode,
2432 gen_rtx_SUBREG (SImode, r, 1), operands[1]));
2433 emit_insn (gen_rtx_SET (VOIDmode, r,
2434 gen_rtx_MULT (SImode, r, operands[2])));
2435 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2436 gen_rtx_SUBREG (SImode, r, 1)));
2442 [(set (match_operand:SI 0 "general_operand" "=d")
2443 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2444 (match_operand:SI 2 "immediate_operand" "K")))]
2448 check_label_emit ();
2449 mvs_check_page (0, 4, 0);
2450 return \"MH %0,%H2\";
2452 [(set_attr "length" "4")]
2455 ;; XXX see comments in mulsi above.
2457 [(set (match_operand:DI 0 "register_operand" "=d")
2458 (mult:DI (match_operand:DI 1 "general_operand" "%0")
2459 ;; XXX see above (match_operand:SI 2 "general_operand" "g")))]
2460 (match_operand:SI 2 "general_operand" "di")))]
2464 check_label_emit ();
2465 if (REG_P (operands[2]))
2467 mvs_check_page (0, 2, 0);
2468 return \"MR %0,%2\";
2470 mvs_check_page (0, 4, 0);
2473 [(set_attr "length" "4")]
2477 ; muldf3 instruction pattern(s).
2480 (define_insn "muldf3"
2481 [(set (match_operand:DF 0 "general_operand" "=f")
2482 (mult:DF (match_operand:DF 1 "general_operand" "%0")
2483 (match_operand:DF 2 "general_operand" "fmF")))]
2487 check_label_emit ();
2488 if (FP_REG_P (operands[2]))
2490 mvs_check_page (0, 2, 0);
2491 return \"MDR %0,%2\";
2493 mvs_check_page (0, 4, 0);
2494 return \"MD %0,%2\";
2496 [(set_attr "length" "4")]
2500 ; mulsf3 instruction pattern(s).
2503 (define_insn "mulsf3"
2504 [(set (match_operand:SF 0 "general_operand" "=f")
2505 (mult:SF (match_operand:SF 1 "general_operand" "%0")
2506 (match_operand:SF 2 "general_operand" "fmF")))]
2510 check_label_emit ();
2511 if (FP_REG_P (operands[2]))
2513 mvs_check_page (0, 2, 0);
2514 return \"MER %0,%2\";
2516 mvs_check_page (0, 4, 0);
2517 return \"ME %0,%2\";
2519 [(set_attr "length" "4")]
2523 ;;- Divide instructions.
2527 ; divsi3 instruction pattern(s).
2530 (define_expand "divsi3"
2531 [(set (match_operand:SI 0 "general_operand" "")
2532 (div:SI (match_operand:SI 1 "general_operand" "")
2533 (match_operand:SI 2 "general_operand" "")))]
2537 rtx r = gen_reg_rtx (DImode);
2539 emit_insn (gen_extendsidi2 (r, operands[1]));
2540 emit_insn (gen_rtx_SET (VOIDmode, r,
2541 gen_rtx_DIV (SImode, r, operands[2])));
2542 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2543 gen_rtx_SUBREG (SImode, r, 1)));
2549 ; udivsi3 instruction pattern(s).
2552 (define_expand "udivsi3"
2553 [(set (match_operand:SI 0 "general_operand" "")
2554 (udiv:SI (match_operand:SI 1 "general_operand" "")
2555 (match_operand:SI 2 "general_operand" "")))]
2559 rtx dr = gen_reg_rtx (DImode);
2560 rtx dr_0 = gen_rtx_SUBREG (SImode, dr, 0);
2561 rtx dr_1 = gen_rtx_SUBREG (SImode, dr, 1);
2564 if (GET_CODE (operands[2]) == CONST_INT)
2566 if (INTVAL (operands[2]) > 0)
2568 emit_insn (gen_zero_extendsidi2 (dr, operands[1]));
2569 emit_insn (gen_rtx_SET (VOIDmode, dr,
2570 gen_rtx_DIV (SImode, dr, operands[2])));
2574 rtx label1 = gen_label_rtx ();
2576 emit_insn (gen_rtx_SET (VOIDmode, dr_0, operands[1]));
2577 emit_insn (gen_rtx_SET (VOIDmode, dr_1, const0_rtx));
2578 emit_insn (gen_cmpsi (dr_0, operands[2]));
2579 emit_jump_insn (gen_bltu (label1));
2580 emit_insn (gen_rtx_SET (VOIDmode, dr_1, const1_rtx));
2581 emit_label (label1);
2586 rtx label1 = gen_label_rtx ();
2587 rtx label2 = gen_label_rtx ();
2588 rtx label3 = gen_label_rtx ();
2589 rtx sr = gen_reg_rtx (SImode);
2591 emit_insn (gen_rtx_SET (VOIDmode, dr_0, operands[1]));
2592 emit_insn (gen_rtx_SET (VOIDmode, sr, operands[2]));
2593 emit_insn (gen_rtx_SET (VOIDmode, dr_1, const0_rtx));
2594 emit_insn (gen_cmpsi (sr, dr_0));
2595 emit_jump_insn (gen_bgtu (label3));
2596 emit_insn (gen_cmpsi (sr, const1_rtx));
2597 emit_jump_insn (gen_blt (label2));
2598 emit_insn (gen_cmpsi (sr, const1_rtx));
2599 emit_jump_insn (gen_beq (label1));
2600 emit_insn (gen_rtx_SET (VOIDmode, dr,
2601 gen_rtx_LSHIFTRT (DImode, dr,
2602 gen_rtx_CONST_INT (SImode, 32))));
2603 emit_insn (gen_rtx_SET (VOIDmode, dr,
2604 gen_rtx_DIV (SImode, dr, sr)));
2605 emit_jump_insn (gen_jump (label3));
2606 emit_label (label1);
2607 emit_insn (gen_rtx_SET (VOIDmode, dr_1, dr_0));
2608 emit_jump_insn (gen_jump (label3));
2609 emit_label (label2);
2610 emit_insn (gen_rtx_SET (VOIDmode, dr_1, const1_rtx));
2611 emit_label (label3);
2613 emit_insn (gen_rtx_SET (VOIDmode, operands[0], dr_1));
2618 ; This is used by divsi3 & udivsi3.
2621 [(set (match_operand:DI 0 "register_operand" "=d")
2622 (div:DI (match_operand:DI 1 "register_operand" "0")
2623 (match_operand:SI 2 "general_operand" "dm")))]
2627 check_label_emit ();
2628 if (REG_P (operands[2]))
2630 mvs_check_page (0, 2, 0);
2631 return \"DR %0,%2\";
2633 mvs_check_page (0, 4, 0);
2636 [(set_attr "length" "4")]
2640 ; divdf3 instruction pattern(s).
2643 (define_insn "divdf3"
2644 [(set (match_operand:DF 0 "general_operand" "=f")
2645 (div:DF (match_operand:DF 1 "general_operand" "0")
2646 (match_operand:DF 2 "general_operand" "fmF")))]
2650 check_label_emit ();
2651 if (FP_REG_P (operands[2]))
2653 mvs_check_page (0, 2, 0);
2654 return \"DDR %0,%2\";
2656 mvs_check_page (0, 4, 0);
2657 return \"DD %0,%2\";
2659 [(set_attr "length" "4")]
2663 ; divsf3 instruction pattern(s).
2666 (define_insn "divsf3"
2667 [(set (match_operand:SF 0 "general_operand" "=f")
2668 (div:SF (match_operand:SF 1 "general_operand" "0")
2669 (match_operand:SF 2 "general_operand" "fmF")))]
2673 check_label_emit ();
2674 if (FP_REG_P (operands[2]))
2676 mvs_check_page (0, 2, 0);
2677 return \"DER %0,%2\";
2679 mvs_check_page (0, 4, 0);
2680 return \"DE %0,%2\";
2682 [(set_attr "length" "4")]
2686 ;;- Modulo instructions.
2690 ; modsi3 instruction pattern(s).
2693 (define_expand "modsi3"
2694 [(set (match_operand:SI 0 "general_operand" "")
2695 (mod:SI (match_operand:SI 1 "general_operand" "")
2696 (match_operand:SI 2 "general_operand" "")))]
2700 rtx r = gen_reg_rtx (DImode);
2702 emit_insn (gen_extendsidi2 (r, operands[1]));
2703 emit_insn (gen_rtx_SET (VOIDmode, r,
2704 gen_rtx_MOD (SImode, r, operands[2])));
2705 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2706 gen_rtx_SUBREG (SImode, r, 0)));
2711 ; umodsi3 instruction pattern(s).
2714 (define_expand "umodsi3"
2715 [(set (match_operand:SI 0 "general_operand" "")
2716 (umod:SI (match_operand:SI 1 "general_operand" "")
2717 (match_operand:SI 2 "general_operand" "")))]
2721 rtx dr = gen_reg_rtx (DImode);
2722 rtx dr_0 = gen_rtx_SUBREG (SImode, dr, 0);
2724 emit_insn (gen_rtx_SET (VOIDmode, dr_0, operands[1]));
2726 if (GET_CODE (operands[2]) == CONST_INT)
2728 if (INTVAL (operands[2]) > 0)
2730 emit_insn (gen_rtx_SET (VOIDmode, dr,
2731 gen_rtx_LSHIFTRT (DImode, dr,
2732 gen_rtx_CONST_INT (SImode, 32))));
2733 emit_insn (gen_rtx_SET (VOIDmode, dr,
2734 gen_rtx_MOD (SImode, dr, operands[2])));
2738 rtx label1 = gen_label_rtx ();
2739 rtx sr = gen_reg_rtx (SImode);
2741 emit_insn (gen_rtx_SET (VOIDmode, sr, operands[2]));
2742 emit_insn (gen_cmpsi (dr_0, sr));
2743 emit_jump_insn (gen_bltu (label1));
2744 emit_insn (gen_rtx_SET (VOIDmode, sr, gen_rtx_ABS (SImode, sr)));
2745 emit_insn (gen_rtx_SET (VOIDmode, dr_0,
2746 gen_rtx_PLUS (SImode, dr_0, sr)));
2747 emit_label (label1);
2752 rtx label1 = gen_label_rtx ();
2753 rtx label2 = gen_label_rtx ();
2754 rtx label3 = gen_label_rtx ();
2755 rtx sr = gen_reg_rtx (SImode);
2757 emit_insn (gen_rtx_SET (VOIDmode, dr_0, operands[1]));
2758 emit_insn (gen_rtx_SET (VOIDmode, sr, operands[2]));
2759 emit_insn (gen_cmpsi (sr, dr_0));
2760 emit_jump_insn (gen_bgtu (label3));
2761 emit_insn (gen_cmpsi (sr, const1_rtx));
2762 emit_jump_insn (gen_blt (label2));
2763 emit_insn (gen_cmpsi (sr, const1_rtx));
2764 emit_jump_insn (gen_beq (label1));
2765 emit_insn (gen_rtx_SET (VOIDmode, dr,
2766 gen_rtx_LSHIFTRT (DImode, dr,
2767 gen_rtx_CONST_INT (SImode, 32))));
2768 emit_insn (gen_rtx_SET (VOIDmode, dr, gen_rtx_MOD (SImode, dr, sr)));
2769 emit_jump_insn (gen_jump (label3));
2770 emit_label (label1);
2771 emit_insn (gen_rtx_SET (VOIDmode, dr_0, const0_rtx));
2772 emit_jump_insn (gen_jump (label3));
2773 emit_label (label2);
2774 emit_insn (gen_rtx_SET (VOIDmode, dr_0,
2775 gen_rtx_MINUS (SImode, dr_0, sr)));
2776 emit_label (label3);
2779 emit_insn (gen_rtx_SET (VOIDmode, operands[0], dr_0));
2784 ; This is used by modsi3 & umodsi3.
2787 [(set (match_operand:DI 0 "register_operand" "=d")
2788 (mod:DI (match_operand:DI 1 "register_operand" "0")
2789 (match_operand:SI 2 "general_operand" "dm")))]
2793 check_label_emit ();
2794 if (REG_P (operands[2]))
2796 mvs_check_page (0, 2, 0);
2797 return \"DR %0,%2\";
2799 mvs_check_page (0, 4, 0);
2802 [(set_attr "length" "4")]
2806 ;;- And instructions.
2810 ; anddi3 instruction pattern(s).
2813 ;(define_expand "anddi3"
2814 ; [(set (match_operand:DI 0 "general_operand" "")
2815 ; (and:DI (match_operand:DI 1 "general_operand" "")
2816 ; (match_operand:DI 2 "general_operand" "")))]
2822 ; emit_insn (gen_andsi3 (operand_subword (operands[0], 0, 1, DImode),
2823 ; operand_subword (operands[1], 0, 1, DImode),
2824 ; operand_subword (operands[2], 0, 1, DImode)));
2825 ; emit_insn (gen_andsi3 (gen_lowpart (SImode, operands[0]),
2826 ; gen_lowpart (SImode, operands[1]),
2827 ; gen_lowpart (SImode, operands[2])));
2832 ; andsi3 instruction pattern(s).
2836 [(set (match_operand:SI 0 "r_or_s_operand" "=d,m")
2837 (and:SI (match_operand:SI 1 "r_or_s_operand" "%0,0")
2838 (match_operand:SI 2 "r_or_s_operand" "g,mi")))]
2839 "TARGET_CHAR_INSTRUCTIONS"
2842 check_label_emit ();
2843 CC_STATUS_INIT; /* and sets CC but not how we want it */
2844 if (REG_P (operands[2]))
2846 mvs_check_page (0, 2, 0);
2847 return \"NR %0,%2\";
2849 if (REG_P (operands[0]))
2851 mvs_check_page (0, 4, 0);
2854 mvs_check_page (0, 6, 0);
2855 return \"NC %O0(4,%R0),%2\";
2857 [(set_attr "length" "6")]
2860 (define_insn "andsi3"
2861 [(set (match_operand:SI 0 "general_operand" "=d")
2862 (and:SI (match_operand:SI 1 "general_operand" "%0")
2863 (match_operand:SI 2 "general_operand" "g")))]
2867 check_label_emit ();
2868 CC_STATUS_INIT; /* and sets CC but not how we want it */
2869 if (REG_P (operands[2]))
2871 mvs_check_page (0, 2, 0);
2872 return \"NR %0,%2\";
2874 mvs_check_page (0, 4, 0);
2877 [(set_attr "length" "4")]
2881 ; andhi3 instruction pattern(s).
2885 [(set (match_operand:HI 0 "r_or_s_operand" "=d,m")
2886 (and:HI (match_operand:HI 1 "r_or_s_operand" "%0,0")
2887 (match_operand:HI 2 "r_or_s_operand" "di,mi")))]
2888 "TARGET_CHAR_INSTRUCTIONS"
2891 check_label_emit ();
2892 CC_STATUS_INIT; /* and sets CC but not how we want it */
2893 if (REG_P (operands[2]))
2895 mvs_check_page (0, 2, 0);
2896 return \"NR %0,%2\";
2898 if (REG_P (operands[0]))
2900 /* %K2 == sign extend operand to 32 bits so that CH works */
2901 mvs_check_page (0, 4, 0);
2902 if (GET_CODE (operands[2]) == CONST_INT)
2903 return \"N %0,%K2\";
2906 if (GET_CODE (operands[2]) == CONST_INT)
2908 mvs_check_page (0, 6, 0);
2909 return \"NC %O0(2,%R0),%H2\";
2911 mvs_check_page (0, 6, 0);
2912 return \"NC %O0(2,%R0),%2\";
2914 [(set_attr "length" "6")]
2917 (define_insn "andhi3"
2918 [(set (match_operand:HI 0 "general_operand" "=d")
2919 (and:HI (match_operand:HI 1 "general_operand" "%0")
2920 (match_operand:HI 2 "general_operand" "di")))]
2924 check_label_emit ();
2925 CC_STATUS_INIT; /* and sets CC but not how we want it */
2926 if (GET_CODE (operands[2]) == CONST_INT)
2928 /* %K2 == sign extend operand to 32 bits so that CH works */
2929 mvs_check_page (0, 4, 0);
2930 return \"N %0,%K2\";
2932 mvs_check_page (0, 2, 0);
2933 return \"NR %0,%2\";
2935 [(set_attr "length" "4")]
2939 ; andqi3 instruction pattern(s).
2943 [(set (match_operand:QI 0 "r_or_s_operand" "=d,m")
2944 (and:QI (match_operand:QI 1 "r_or_s_operand" "%0,0")
2945 (match_operand:QI 2 "r_or_s_operand" "di,mi")))]
2946 "TARGET_CHAR_INSTRUCTIONS"
2949 check_label_emit ();
2950 CC_STATUS_INIT; /* and sets CC but not how we want it */
2951 if (REG_P (operands[2]))
2953 mvs_check_page (0, 2, 0);
2954 return \"NR %0,%2\";
2956 if (REG_P (operands[0]))
2958 mvs_check_page (0, 4, 0);
2961 if (GET_CODE (operands[2]) == CONST_INT)
2963 mvs_check_page (0, 4, 0);
2964 return \"NI %0,%B2\";
2966 mvs_check_page (0, 6, 0);
2967 return \"NC %O0(1,%R0),%2\";
2969 [(set_attr "length" "6")]
2972 (define_insn "andqi3"
2973 [(set (match_operand:QI 0 "general_operand" "=d")
2974 (and:QI (match_operand:QI 1 "general_operand" "%0")
2975 (match_operand:QI 2 "general_operand" "di")))]
2979 check_label_emit ();
2980 CC_STATUS_INIT; /* and sets CC but not how we want it */
2981 if (GET_CODE (operands[2]) == CONST_INT)
2983 mvs_check_page (0, 4, 0);
2986 mvs_check_page (0, 2, 0);
2987 return \"NR %0,%2\";
2989 [(set_attr "length" "4")]
2993 ;;- Bit set (inclusive or) instructions.
2997 ; iordi3 instruction pattern(s).
3000 ;(define_expand "iordi3"
3001 ; [(set (match_operand:DI 0 "general_operand" "")
3002 ; (ior:DI (match_operand:DI 1 "general_operand" "")
3003 ; (match_operand:DI 2 "general_operand" "")))]
3009 ; emit_insn (gen_iorsi3 (operand_subword (operands[0], 0, 1, DImode),
3010 ; operand_subword (operands[1], 0, 1, DImode),
3011 ; operand_subword (operands[2], 0, 1, DImode)));
3012 ; emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]),
3013 ; gen_lowpart (SImode, operands[1]),
3014 ; gen_lowpart (SImode, operands[2])));
3019 ; iorsi3 instruction pattern(s).
3023 [(set (match_operand:SI 0 "r_or_s_operand" "=d,m")
3024 (ior:SI (match_operand:SI 1 "r_or_s_operand" "%0,0")
3025 (match_operand:SI 2 "r_or_s_operand" "g,Si")))]
3026 "TARGET_CHAR_INSTRUCTIONS"
3029 check_label_emit ();
3030 CC_STATUS_INIT; /* OR sets CC but not how we want it */
3031 if (REG_P (operands[2]))
3033 mvs_check_page (0, 2, 0);
3034 return \"OR %0,%2\";
3036 if (REG_P (operands[0]))
3038 mvs_check_page (0, 4, 0);
3041 mvs_check_page (0, 6, 0);
3042 return \"OC %O0(4,%R0),%2\";
3044 [(set_attr "length" "6")]
3047 (define_insn "iorsi3"
3048 [(set (match_operand:SI 0 "general_operand" "=d")
3049 (ior:SI (match_operand:SI 1 "general_operand" "%0")
3050 (match_operand:SI 2 "general_operand" "g")))]
3054 check_label_emit ();
3055 CC_STATUS_INIT; /* OR sets CC but not how we want it */
3056 if (REG_P (operands[2]))
3058 mvs_check_page (0, 2, 0);
3059 return \"OR %0,%2\";
3061 mvs_check_page (0, 4, 0);
3064 [(set_attr "length" "4")]
3068 ; iorhi3 instruction pattern(s).
3072 [(set (match_operand:HI 0 "r_or_s_operand" "=d,m")
3073 (ior:HI (match_operand:HI 1 "r_or_s_operand" "%0,0")
3074 (match_operand:HI 2 "r_or_s_operand" "di,mi")))]
3075 "TARGET_CHAR_INSTRUCTIONS"
3078 check_label_emit ();
3079 CC_STATUS_INIT; /* OR sets CC but not how we want it */
3080 if (REG_P (operands[2]))
3082 mvs_check_page (0, 2, 0);
3083 return \"OR %0,%2\";
3085 if (REG_P (operands[0]))
3087 mvs_check_page (0, 4, 0);
3090 if (GET_CODE (operands[2]) == CONST_INT)
3092 mvs_check_page (0, 6, 0);
3093 return \"OC %O0(2,%R0),%H2\";
3095 mvs_check_page (0, 6, 0);
3096 return \"OC %O0(2,%R0),%2\";
3098 [(set_attr "length" "6")]
3101 (define_insn "iorhi3"
3102 [(set (match_operand:HI 0 "general_operand" "=d")
3103 (ior:HI (match_operand:HI 1 "general_operand" "%0")
3104 (match_operand:HI 2 "general_operand" "di")))]
3108 check_label_emit ();
3109 CC_STATUS_INIT; /* OR sets CC but not how we want it */
3110 if (GET_CODE (operands[2]) == CONST_INT)
3112 mvs_check_page (0, 4, 0);
3115 mvs_check_page (0, 2, 0);
3116 return \"OR %0,%2\";
3118 [(set_attr "length" "4")]
3122 ; iorqi3 instruction pattern(s).
3126 [(set (match_operand:QI 0 "r_or_s_operand" "=d,m")
3127 (ior:QI (match_operand:QI 1 "r_or_s_operand" "%0,0")
3128 (match_operand:QI 2 "r_or_s_operand" "di,mi")))]
3129 "TARGET_CHAR_INSTRUCTIONS"
3132 check_label_emit ();
3133 CC_STATUS_INIT; /* OR sets CC but not how we want it */
3134 if (REG_P (operands[2]))
3136 mvs_check_page (0, 2, 0);
3137 return \"OR %0,%2\";
3139 if (REG_P (operands[0]))
3141 mvs_check_page (0, 4, 0);
3144 if (GET_CODE (operands[2]) == CONST_INT)
3146 mvs_check_page (0, 4, 0);
3147 return \"OI %0,%B2\";
3149 mvs_check_page (0, 6, 0);
3150 return \"OC %O0(1,%R0),%2\";
3152 [(set_attr "length" "6")]
3155 (define_insn "iorqi3"
3156 [(set (match_operand:QI 0 "general_operand" "=d")
3157 (ior:QI (match_operand:QI 1 "general_operand" "%0")
3158 (match_operand:QI 2 "general_operand" "di")))]
3162 check_label_emit ();
3163 CC_STATUS_INIT; /* OR sets CC but not how we want it */
3164 if (GET_CODE (operands[2]) == CONST_INT)
3166 mvs_check_page (0, 4, 0);
3169 mvs_check_page (0, 2, 0);
3170 return \"OR %0,%2\";
3172 [(set_attr "length" "4")]
3176 ;;- Xor instructions.
3180 ; xordi3 instruction pattern(s).
3183 ;(define_expand "xordi3"
3184 ; [(set (match_operand:DI 0 "general_operand" "")
3185 ; (xor:DI (match_operand:DI 1 "general_operand" "")
3186 ; (match_operand:DI 2 "general_operand" "")))]
3192 ; emit_insn (gen_xorsi3 (operand_subword (operands[0], 0, 1, DImode),
3193 ; operand_subword (operands[1], 0, 1, DImode),
3194 ; operand_subword (operands[2], 0, 1, DImode)));
3195 ; emit_insn (gen_xorsi3 (gen_lowpart (SImode, operands[0]),
3196 ; gen_lowpart (SImode, operands[1]),
3197 ; gen_lowpart (SImode, operands[2])));
3202 ; xorsi3 instruction pattern(s).
3206 [(set (match_operand:SI 0 "r_or_s_operand" "=d,m")
3207 (xor:SI (match_operand:SI 1 "r_or_s_operand" "%0,0")
3208 (match_operand:SI 2 "r_or_s_operand" "g,mi")))]
3209 "TARGET_CHAR_INSTRUCTIONS"
3212 check_label_emit ();
3213 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3214 if (REG_P (operands[2]))
3216 mvs_check_page (0, 2, 0);
3217 return \"XR %0,%2\";
3219 if (REG_P (operands[0]))
3221 mvs_check_page (0, 4, 0);
3224 mvs_check_page (0, 6, 0);
3225 return \"XC %O0(4,%R0),%2\";
3227 [(set_attr "length" "6")]
3230 (define_insn "xorsi3"
3231 [(set (match_operand:SI 0 "general_operand" "=d")
3232 (xor:SI (match_operand:SI 1 "general_operand" "%0")
3233 (match_operand:SI 2 "general_operand" "g")))]
3237 check_label_emit ();
3238 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3239 if (REG_P (operands[2]))
3241 mvs_check_page (0, 2, 0);
3242 return \"XR %0,%2\";
3244 mvs_check_page (0, 4, 0);
3247 [(set_attr "length" "4")]
3251 ; xorhi3 instruction pattern(s).
3255 [(set (match_operand:HI 0 "r_or_s_operand" "=d,m")
3256 (xor:HI (match_operand:HI 1 "r_or_s_operand" "%0,0")
3257 (match_operand:HI 2 "r_or_s_operand" "di,mi")))]
3258 "TARGET_CHAR_INSTRUCTIONS"
3261 check_label_emit ();
3262 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3263 if (REG_P (operands[2]))
3265 mvs_check_page (0, 2, 0);
3266 return \"XR %0,%2\";
3268 if (REG_P (operands[0]))
3270 mvs_check_page (0, 4, 0);
3271 return \"X %0,%H2\";
3273 if (GET_CODE (operands[2]) == CONST_INT)
3275 mvs_check_page (0, 6, 0);
3276 return \"XC %O0(2,%R0),%H2\";
3278 mvs_check_page (0, 6, 0);
3279 return \"XC %O0(2,%R0),%2\";
3281 [(set_attr "length" "6")]
3284 (define_insn "xorhi3"
3285 [(set (match_operand:HI 0 "general_operand" "=d")
3286 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3287 (match_operand:HI 2 "general_operand" "di")))]
3291 check_label_emit ();
3292 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3293 if (GET_CODE (operands[2]) == CONST_INT)
3295 mvs_check_page (0, 4, 0);
3296 return \"X %0,%H2\";
3298 mvs_check_page (0, 2, 0);
3299 return \"XR %0,%2\";
3301 [(set_attr "length" "4")]
3305 ; xorqi3 instruction pattern(s).
3309 [(set (match_operand:QI 0 "r_or_s_operand" "=d,m")
3310 (xor:QI (match_operand:QI 1 "r_or_s_operand" "%0,0")
3311 (match_operand:QI 2 "r_or_s_operand" "di,mi")))]
3312 "TARGET_CHAR_INSTRUCTIONS"
3315 check_label_emit ();
3316 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3317 if (REG_P (operands[2]))
3319 mvs_check_page (0, 2, 0);
3320 return \"XR %0,%2\";
3322 if (REG_P (operands[0]))
3324 mvs_check_page (0, 4, 0);
3327 if (GET_CODE (operands[2]) == CONST_INT)
3329 mvs_check_page (0, 4, 0);
3330 return \"XI %0,%B2\";
3332 mvs_check_page (0, 6, 0);
3333 return \"XC %O0(1,%R0),%2\";
3335 [(set_attr "length" "6")]
3338 (define_insn "xorqi3"
3339 [(set (match_operand:QI 0 "general_operand" "=d")
3340 (xor:QI (match_operand:QI 1 "general_operand" "%0")
3341 (match_operand:QI 2 "general_operand" "di")))]
3345 check_label_emit ();
3346 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3347 if (GET_CODE (operands[2]) == CONST_INT)
3349 mvs_check_page (0, 4, 0);
3352 mvs_check_page (0, 2, 0);
3353 return \"XR %0,%2\";
3355 [(set_attr "length" "4")]
3359 ;;- Negate instructions.
3363 ; negsi2 instruction pattern(s).
3366 (define_insn "negsi2"
3367 [(set (match_operand:SI 0 "general_operand" "=d")
3368 (neg:SI (match_operand:SI 1 "general_operand" "d")))]
3372 check_label_emit ();
3373 mvs_check_page (0, 2, 0);
3374 return \"LCR %0,%1\";
3376 [(set_attr "length" "2")]
3380 ; neghi2 instruction pattern(s).
3383 (define_insn "neghi2"
3384 [(set (match_operand:HI 0 "general_operand" "=d")
3385 (neg:HI (match_operand:HI 1 "general_operand" "d")))]
3389 check_label_emit ();
3390 mvs_check_page (0, 10, 0);
3391 return \"SLL %1,16\;SRA %1,16\;LCR %0,%1\";
3393 [(set_attr "length" "10")]
3397 ; negdf2 instruction pattern(s).
3400 (define_insn "negdf2"
3401 [(set (match_operand:DF 0 "general_operand" "=f")
3402 (neg:DF (match_operand:DF 1 "general_operand" "f")))]
3406 check_label_emit ();
3407 mvs_check_page (0, 2, 0);
3408 return \"LCDR %0,%1\";
3410 [(set_attr "length" "2")]
3414 ; negsf2 instruction pattern(s).
3417 (define_insn "negsf2"
3418 [(set (match_operand:SF 0 "general_operand" "=f")
3419 (neg:SF (match_operand:SF 1 "general_operand" "f")))]
3423 check_label_emit ();
3424 mvs_check_page (0, 2, 0);
3425 return \"LCER %0,%1\";
3427 [(set_attr "length" "2")]
3431 ;;- Absolute value instructions.
3435 ; abssi2 instruction pattern(s).
3438 (define_insn "abssi2"
3439 [(set (match_operand:SI 0 "general_operand" "=d")
3440 (abs:SI (match_operand:SI 1 "general_operand" "d")))]
3444 check_label_emit ();
3445 mvs_check_page (0, 2, 0);
3446 return \"LPR %0,%1\";
3448 [(set_attr "length" "2")]
3452 ; abshi2 instruction pattern(s).
3455 (define_insn "abshi2"
3456 [(set (match_operand:HI 0 "general_operand" "=d")
3457 (abs:HI (match_operand:HI 1 "general_operand" "d")))]
3461 check_label_emit ();
3462 mvs_check_page (0, 10, 0);
3463 return \"SLL %1,16\;SRA %1,16\;LPR %0,%1\";
3465 [(set_attr "length" "10")]
3469 ; absdf2 instruction pattern(s).
3472 (define_insn "absdf2"
3473 [(set (match_operand:DF 0 "general_operand" "=f")
3474 (abs:DF (match_operand:DF 1 "general_operand" "f")))]
3478 check_label_emit ();
3479 mvs_check_page (0, 2, 0);
3480 return \"LPDR %0,%1\";
3482 [(set_attr "length" "2")]
3486 ; abssf2 instruction pattern(s).
3489 (define_insn "abssf2"
3490 [(set (match_operand:SF 0 "general_operand" "=f")
3491 (abs:SF (match_operand:SF 1 "general_operand" "f")))]
3495 check_label_emit ();
3496 mvs_check_page (0, 2, 0);
3497 return \"LPER %0,%1\";
3499 [(set_attr "length" "2")]
3503 ;;- One complement instructions.
3507 ; one_cmpldi2 instruction pattern(s).
3510 ;(define_expand "one_cmpldi2"
3511 ; [(set (match_operand:DI 0 "general_operand" "")
3512 ; (not:DI (match_operand:DI 1 "general_operand" "")))]
3516 ; rtx gen_one_cmplsi2();
3518 ; emit_insn (gen_one_cmplsi2 (operand_subword (operands[0], 0, 1, DImode),
3519 ; operand_subword (operands[1], 0, 1, DImode)));
3520 ; emit_insn (gen_one_cmplsi2 (gen_lowpart (SImode, operands[0]),
3521 ; gen_lowpart (SImode, operands[1])));
3526 ; one_cmplsi2 instruction pattern(s).
3530 [(set (match_operand:SI 0 "r_or_s_operand" "=dm")
3531 (not:SI (match_operand:SI 1 "r_or_s_operand" "0")))]
3532 "TARGET_CHAR_INSTRUCTIONS"
3535 check_label_emit ();
3536 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3537 if (REG_P (operands[0]))
3539 mvs_check_page (0, 4, 4);
3540 return \"X %0,=F'-1'\";
3543 mvs_check_page (0, 6, 4);
3544 return \"XC %O0(4,%R0),=F'-1'\";
3546 [(set_attr "length" "6")]
3549 (define_insn "one_cmplsi2"
3550 [(set (match_operand:SI 0 "general_operand" "=d")
3551 (not:SI (match_operand:SI 1 "general_operand" "0")))]
3555 check_label_emit ();
3556 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3557 mvs_check_page (0, 4, 4);
3558 return \"X %0,=F'-1'\";
3560 [(set_attr "length" "4")]
3564 ; one_cmplhi2 instruction pattern(s).
3568 [(set (match_operand:HI 0 "r_or_s_operand" "=dm")
3569 (not:HI (match_operand:HI 1 "r_or_s_operand" "0")))]
3570 "TARGET_CHAR_INSTRUCTIONS"
3573 check_label_emit ();
3574 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3575 if (REG_P (operands[0]))
3577 mvs_check_page (0, 4, 4);
3578 return \"X %0,=F'-1'\";
3580 mvs_check_page (0, 6, 4);
3581 return \"XC %O0(2,%R0),=X'FFFF'\";
3583 [(set_attr "length" "6")]
3586 (define_insn "one_cmplhi2"
3587 [(set (match_operand:HI 0 "general_operand" "=d")
3588 (not:HI (match_operand:HI 1 "general_operand" "0")))]
3592 check_label_emit ();
3593 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3594 mvs_check_page (0, 4, 4);
3595 return \"X %0,=F'-1'\";
3597 [(set_attr "length" "4")]
3601 ; one_cmplqi2 instruction pattern(s).
3605 [(set (match_operand:QI 0 "r_or_s_operand" "=dm")
3606 (not:QI (match_operand:QI 1 "r_or_s_operand" "0")))]
3607 "TARGET_CHAR_INSTRUCTIONS"
3610 check_label_emit ();
3611 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3612 if (REG_P (operands[0]))
3614 mvs_check_page (0, 4, 4);
3615 return \"X %0,=F'-1'\";
3617 mvs_check_page (0, 4, 0);
3618 return \"XI %0,255\";
3620 [(set_attr "length" "4")]
3623 (define_insn "one_cmplqi2"
3624 [(set (match_operand:QI 0 "general_operand" "=d")
3625 (not:QI (match_operand:QI 1 "general_operand" "0")))]
3629 check_label_emit ();
3630 CC_STATUS_INIT; /* XOR sets CC but not how we want it */
3631 mvs_check_page (0, 4, 4);
3632 return \"X %0,=F'-1'\";
3634 [(set_attr "length" "4")]
3638 ;;- Arithmetic shift instructions.
3642 ; ashldi3 instruction pattern(s).
3645 (define_insn "ashldi3"
3646 [(set (match_operand:DI 0 "general_operand" "=d")
3647 (ashift:DI (match_operand:DI 1 "general_operand" "0")
3648 (match_operand:SI 2 "general_operand" "Ja")))]
3652 check_label_emit ();
3653 /* this status set seems not have the desired effect,
3654 * proably because the 64-bit long-long test is emulated ?! */
3655 CC_STATUS_SET (operands[0], operands[1]);
3656 mvs_check_page (0, 4, 0);
3657 if (REG_P (operands[2]))
3658 return \"SLDA %0,0(%2)\";
3659 return \"SLDA %0,%c2\";
3661 [(set_attr "length" "4")]
3665 ; ashrdi3 instruction pattern(s).
3668 (define_insn "ashrdi3"
3669 [(set (match_operand:DI 0 "register_operand" "=d")
3670 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
3671 (match_operand:SI 2 "general_operand" "Ja")))]
3675 check_label_emit ();
3676 /* this status set seems not have the desired effect,
3677 * proably because the 64-bit long-long test is emulated ?! */
3678 CC_STATUS_SET (operands[0], operands[1]);
3679 mvs_check_page (0, 4, 0);
3680 if (REG_P (operands[2]))
3681 return \"SRDA %0,0(%2)\";
3682 return \"SRDA %0,%c2\";
3684 [(set_attr "length" "4")]
3688 ; ashlsi3 instruction pattern(s).
3691 (define_insn "ashlsi3"
3692 [(set (match_operand:SI 0 "general_operand" "=d")
3693 (ashift:SI (match_operand:SI 1 "general_operand" "0")
3694 (match_operand:SI 2 "general_operand" "Ja")))]
3698 check_label_emit ();
3699 mvs_check_page (0, 4, 0);
3700 if (REG_P (operands[2]))
3701 return \"SLL %0,0(%2)\";
3702 return \"SLL %0,%c2\";
3704 [(set_attr "length" "4")]
3708 ; ashrsi3 instruction pattern(s).
3711 (define_insn "ashrsi3"
3712 [(set (match_operand:SI 0 "general_operand" "=d")
3713 (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
3714 (match_operand:SI 2 "general_operand" "Ja")))]
3718 check_label_emit ();
3719 CC_STATUS_SET (operands[0], operands[1]);
3720 mvs_check_page (0, 4, 0);
3721 if (REG_P (operands[2]))
3722 return \"SRA %0,0(%2)\";
3723 return \"SRA %0,%c2\";
3725 [(set_attr "length" "4")]
3729 ; ashlhi3 instruction pattern(s).
3732 (define_insn "ashlhi3"
3733 [(set (match_operand:HI 0 "general_operand" "=d")
3734 (ashift:HI (match_operand:HI 1 "general_operand" "0")
3735 (match_operand:SI 2 "general_operand" "Ja")))]
3739 check_label_emit ();
3740 mvs_check_page (0, 8, 0);
3741 if (REG_P (operands[2]))
3742 return \"SLL %0,16(%2)\;SRA %0,16\";
3743 return \"SLL %0,16+%c2\;SRA %0,16\";
3745 [(set_attr "length" "8")]
3749 ; ashrhi3 instruction pattern(s).
3752 (define_insn "ashrhi3"
3753 [(set (match_operand:HI 0 "general_operand" "=d")
3754 (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
3755 (match_operand:SI 2 "general_operand" "Ja")))]
3759 check_label_emit ();
3760 mvs_check_page (0, 8, 0);
3761 if (REG_P (operands[2]))
3762 return \"SLL %0,16\;SRA %0,16(%2)\";
3763 return \"SLL %0,16\;SRA %0,16+%c2\";
3765 [(set_attr "length" "8")]
3769 ; ashlqi3 instruction pattern(s).
3772 (define_insn "ashlqi3"
3773 [(set (match_operand:QI 0 "general_operand" "=d")
3774 (ashift:QI (match_operand:QI 1 "general_operand" "0")
3775 (match_operand:SI 2 "general_operand" "Ja")))]
3779 check_label_emit ();
3780 mvs_check_page (0, 4, 0);
3781 if (REG_P (operands[2]))
3782 return \"SLL %0,0(%2)\";
3783 return \"SLL %0,%c2\";
3785 [(set_attr "length" "4")]
3789 ; ashrqi3 instruction pattern(s).
3792 (define_insn "ashrqi3"
3793 [(set (match_operand:QI 0 "general_operand" "=d")
3794 (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
3795 (match_operand:SI 2 "general_operand" "Ja")))]
3799 check_label_emit ();
3800 mvs_check_page (0, 8, 0);
3801 if (REG_P (operands[2]))
3802 return \"SLL %0,24\;SRA %0,24(%2)\";
3803 return \"SLL %0,24\;SRA %0,24+%c2\";
3805 [(set_attr "length" "8")]
3809 ;;- Logical shift instructions.
3813 ; lshrdi3 instruction pattern(s).
3816 (define_insn "lshrdi3"
3817 [(set (match_operand:DI 0 "general_operand" "=d")
3818 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
3819 (match_operand:SI 2 "general_operand" "Ja")))]
3823 check_label_emit ();
3824 mvs_check_page (0, 4, 0);
3825 if (REG_P (operands[2]))
3826 return \"SRDL %0,0(%2)\";
3827 return \"SRDL %0,%c2\";
3829 [(set_attr "length" "4")]
3834 ; lshrsi3 instruction pattern(s).
3837 (define_insn "lshrsi3"
3838 [(set (match_operand:SI 0 "general_operand" "=d")
3839 (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
3840 (match_operand:SI 2 "general_operand" "Ja")))]
3844 check_label_emit ();
3845 mvs_check_page (0, 4, 0);
3846 if (REG_P (operands[2]))
3847 return \"SRL %0,0(%2)\";
3848 return \"SRL %0,%c2\";
3850 [(set_attr "length" "4")]
3854 ; lshrhi3 instruction pattern(s).
3857 (define_insn "lshrhi3"
3858 [(set (match_operand:HI 0 "general_operand" "=d")
3859 (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
3860 (match_operand:SI 2 "general_operand" "Ja")))]
3864 check_label_emit ();
3865 CC_STATUS_INIT; /* AND sets the CC but not how we want it */
3866 if (REG_P (operands[2]))
3868 mvs_check_page (0, 8, 4);
3869 return \"N %0,=X'0000FFFF'\;SRL %0,0(%2)\";
3871 mvs_check_page (0, 8, 4);
3872 return \"N %0,=X'0000FFFF'\;SRL %0,%c2\";
3874 [(set_attr "length" "8")]
3878 ; lshrqi3 instruction pattern(s).
3881 (define_insn "lshrqi3"
3882 [(set (match_operand:QI 0 "general_operand" "=d")
3883 (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
3884 (match_operand:SI 2 "general_operand" "Ja")))]
3888 check_label_emit ();
3889 CC_STATUS_INIT; /* AND sets the CC but not how we want it */
3890 mvs_check_page (0, 8, 4);
3891 if (REG_P (operands[2]))
3892 return \"N %0,=X'000000FF'\;SRL %0,0(%2)\";
3893 return \"N %0,=X'000000FF'\;SRL %0,%c2\";
3895 [(set_attr "length" "8")]
3898 ;; =======================================================================
3899 ;;- Conditional jump instructions.
3900 ;; =======================================================================
3903 ; beq instruction pattern(s).
3908 (if_then_else (eq (cc0)
3910 (label_ref (match_operand 0 "" ""))
3912 ; (clobber (reg:SI 14))
3917 check_label_emit ();
3918 mvs_check_page (0, 4, 0);
3919 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3923 mvs_check_page (0, 2, 4);
3924 return \"L 14,=A(%l0)\;BER 14\";
3926 [(set_attr "length" "6")]
3930 ; bne instruction pattern(s).
3935 (if_then_else (ne (cc0)
3937 (label_ref (match_operand 0 "" ""))
3939 ; (clobber (reg:SI 14))
3944 check_label_emit ();
3945 mvs_check_page (0, 4, 0);
3946 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3950 mvs_check_page (0, 2, 4);
3951 return \"L 14,=A(%l0)\;BNER 14\";
3953 [(set_attr "length" "6")]
3957 ; bgt instruction pattern(s).
3962 (if_then_else (gt (cc0)
3964 (label_ref (match_operand 0 "" ""))
3966 ; (clobber (reg:SI 14))
3971 check_label_emit ();
3972 mvs_check_page (0, 4, 0);
3973 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3977 mvs_check_page (0, 2, 4);
3978 return \"L 14,=A(%l0)\;BHR 14\";
3980 [(set_attr "length" "6")]
3984 ; bgtu instruction pattern(s).
3989 (if_then_else (gtu (cc0)
3991 (label_ref (match_operand 0 "" ""))
3993 ; (clobber (reg:SI 14))
3998 check_label_emit ();
3999 mvs_check_page (0, 4, 0);
4000 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4004 mvs_check_page (0, 2, 4);
4005 return \"L 14,=A(%l0)\;BHR 14\";
4007 [(set_attr "length" "6")]
4011 ; blt instruction pattern(s).
4016 (if_then_else (lt (cc0)
4018 (label_ref (match_operand 0 "" ""))
4020 ; (clobber (reg:SI 14))
4025 check_label_emit ();
4026 mvs_check_page (0, 4, 0);
4027 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4031 mvs_check_page (0, 2, 4);
4032 return \"L 14,=A(%l0)\;BLR 14\";
4034 [(set_attr "length" "6")]
4038 ; bltu instruction pattern(s).
4043 (if_then_else (ltu (cc0)
4045 (label_ref (match_operand 0 "" ""))
4047 ; (clobber (reg:SI 14))
4052 check_label_emit ();
4053 mvs_check_page (0, 4, 0);
4054 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4058 mvs_check_page (0, 2, 4);
4059 return \"L 14,=A(%l0)\;BLR 14\";
4061 [(set_attr "length" "6")]
4065 ; bge instruction pattern(s).
4070 (if_then_else (ge (cc0)
4072 (label_ref (match_operand 0 "" ""))
4074 ; (clobber (reg:SI 14))
4079 check_label_emit ();
4080 mvs_check_page (0, 4, 0);
4081 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4085 mvs_check_page (0, 2, 4);
4086 return \"L 14,=A(%l0)\;BNLR 14\";
4088 [(set_attr "length" "6")]
4092 ; bgeu instruction pattern(s).
4097 (if_then_else (geu (cc0)
4099 (label_ref (match_operand 0 "" ""))
4101 ; (clobber (reg:SI 14))
4106 check_label_emit ();
4107 mvs_check_page (0, 4, 0);
4108 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4112 mvs_check_page (0, 2, 4);
4113 return \"L 14,=A(%l0)\;BNLR 14\";
4115 [(set_attr "length" "6")]
4119 ; ble instruction pattern(s).
4124 (if_then_else (le (cc0)
4126 (label_ref (match_operand 0 "" ""))
4128 ; (clobber (reg:SI 14))
4133 check_label_emit ();
4134 mvs_check_page (0, 4, 0);
4135 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4139 mvs_check_page (0, 2, 4);
4140 return \"L 14,=A(%l0)\;BNHR 14\";
4142 [(set_attr "length" "6")]
4146 ; bleu instruction pattern(s).
4151 (if_then_else (leu (cc0)
4153 (label_ref (match_operand 0 "" ""))
4155 ; (clobber (reg:SI 14))
4160 check_label_emit ();
4161 mvs_check_page (0, 4, 0);
4162 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4166 mvs_check_page (0, 2, 4);
4167 return \"L 14,=A(%l0)\;BNHR 14\";
4169 [(set_attr "length" "6")]
4173 ;;- Negated conditional jump instructions.
4178 (if_then_else (eq (cc0)
4181 (label_ref (match_operand 0 "" ""))))
4182 ; (clobber (reg:SI 14))
4187 check_label_emit ();
4188 mvs_check_page (0, 4, 0);
4189 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4193 mvs_check_page (0, 2, 4);
4194 return \"L 14,=A(%l0)\;BNER 14\";
4196 [(set_attr "length" "6")]
4201 (if_then_else (ne (cc0)
4204 (label_ref (match_operand 0 "" ""))))
4205 ; (clobber (reg:SI 14))
4210 check_label_emit ();
4211 mvs_check_page (0, 4, 0);
4212 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4216 mvs_check_page (0, 2, 4);
4217 return \"L 14,=A(%l0)\;BER 14\";
4219 [(set_attr "length" "6")]
4224 (if_then_else (gt (cc0)
4227 (label_ref (match_operand 0 "" ""))))
4228 ; (clobber (reg:SI 14))
4233 check_label_emit ();
4234 mvs_check_page (0, 4, 0);
4235 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4239 mvs_check_page (0, 2, 4);
4240 return \"L 14,=A(%l0)\;BNHR 14\";
4242 [(set_attr "length" "6")]
4247 (if_then_else (gtu (cc0)
4250 (label_ref (match_operand 0 "" ""))))
4251 ; (clobber (reg:SI 14))
4256 check_label_emit ();
4257 mvs_check_page (0, 4, 0);
4258 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4262 mvs_check_page (0, 2, 4);
4263 return \"L 14,=A(%l0)\;BNHR 14\";
4265 [(set_attr "length" "6")]
4270 (if_then_else (lt (cc0)
4273 (label_ref (match_operand 0 "" ""))))
4274 ; (clobber (reg:SI 14))
4279 check_label_emit ();
4280 mvs_check_page (0, 4, 0);
4281 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4285 mvs_check_page (0, 2, 4);
4286 return \"L 14,=A(%l0)\;BNLR 14\";
4288 [(set_attr "length" "6")]
4293 (if_then_else (ltu (cc0)
4296 (label_ref (match_operand 0 "" ""))))
4297 ; (clobber (reg:SI 14))
4302 check_label_emit ();
4303 mvs_check_page (0, 4, 0);
4304 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4308 mvs_check_page (0, 2, 4);
4309 return \"L 14,=A(%l0)\;BNLR 14\";
4311 [(set_attr "length" "6")]
4316 (if_then_else (ge (cc0)
4319 (label_ref (match_operand 0 "" ""))))
4320 ; (clobber (reg:SI 14))
4325 check_label_emit ();
4326 mvs_check_page (0, 4, 0);
4327 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4331 mvs_check_page (0, 2, 4);
4332 return \"L 14,=A(%l0)\;BLR 14\";
4334 [(set_attr "length" "6")]
4339 (if_then_else (geu (cc0)
4342 (label_ref (match_operand 0 "" ""))))
4343 ; (clobber (reg:SI 14))
4348 check_label_emit ();
4349 mvs_check_page (0, 4, 0);
4350 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4354 mvs_check_page (0, 2, 4);
4355 return \"L 14,=A(%l0)\;BLR 14\";
4357 [(set_attr "length" "6")]
4362 (if_then_else (le (cc0)
4365 (label_ref (match_operand 0 "" ""))))
4366 ; (clobber (reg:SI 14))
4371 check_label_emit ();
4372 mvs_check_page (0, 4, 0);
4373 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4377 mvs_check_page (0, 2, 4);
4378 return \"L 14,=A(%l0)\;BHR 14\";
4380 [(set_attr "length" "6")]
4385 (if_then_else (leu (cc0)
4388 (label_ref (match_operand 0 "" ""))))
4389 ; (clobber (reg:SI 14))
4394 check_label_emit ();
4395 mvs_check_page (0, 4, 0);
4396 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4400 mvs_check_page (0, 2, 4);
4401 return \"L 14,=A(%l0)\;BHR 14\";
4403 [(set_attr "length" "6")]
4406 ;; ==============================================================
4407 ;;- Subtract one and jump if not zero.
4408 ;; These insns seem to not be getting matched ...
4409 ;; XXX should fix this, as it would improve for loops
4414 (ne (plus:SI (match_operand:SI 0 "register_operand" "+d")
4417 (label_ref (match_operand 1 "" ""))
4420 (plus:SI (match_dup 0)
4422 ; (clobber (reg:SI 14))
4427 check_label_emit ();
4428 mvs_check_page (0, 4, 0);
4429 if (mvs_check_label (CODE_LABEL_NUMBER (operands[1])))
4431 return \"BCT %0,%l1\";
4433 mvs_check_page (0, 2, 4);
4434 return \"L 14,=A(%l1)\;BCTR %0,14\";
4436 [(set_attr "length" "6")]
4442 (eq (plus:SI (match_operand:SI 0 "register_operand" "+d")
4446 (label_ref (match_operand 1 "" ""))))
4448 (plus:SI (match_dup 0)
4450 ; (clobber (reg:SI 14))
4455 check_label_emit ();
4456 mvs_check_page (0, 4, 0);
4457 if (mvs_check_label (CODE_LABEL_NUMBER (operands[1])))
4459 return \"BCT %0,%l1\";
4461 mvs_check_page (0, 2, 4);
4462 return \"L 14,=A(%l1)\;BCTR %0,14\";
4464 [(set_attr "length" "6")]
4467 ;; =============================================================
4468 ;;- Unconditional jump instructions.
4472 ; jump instruction pattern(s).
4477 (label_ref (match_operand 0 "" "")))
4478 ; (clobber (reg:SI 14))
4483 check_label_emit ();
4484 mvs_check_page (0, 4, 0);
4485 if (i370_short_branch(insn) || mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4489 mvs_check_page (0, 2, 4);
4490 return \"L 14,=A(%l0)\;BR 14\";
4492 [(set_attr "length" "6")]
4496 ; indirect-jump instruction pattern(s).
4497 ; hack alert -- should check that displacement is < 4096
4499 (define_insn "indirect_jump"
4500 [(set (pc) (match_operand:SI 0 "general_operand" "rm"))]
4504 check_label_emit ();
4505 if (REG_P (operands[0]))
4507 mvs_check_page (0, 2, 0);
4510 mvs_check_page (0, 4, 0);
4513 [(set_attr "length" "4")]
4517 ; tablejump instruction pattern(s).
4520 (define_insn "tablejump"
4522 (match_operand:SI 0 "general_operand" "am"))
4523 (use (label_ref (match_operand 1 "" "")))
4524 ; (clobber (reg:SI 14))
4529 check_label_emit ();
4530 if (REG_P (operands[0]))
4532 mvs_check_page (0, 6, 0);
4533 return \"BR %0\;DS 0F\";
4535 mvs_check_page (0, 10, 0);
4536 return \"L 14,%0\;BR 14\;DS 0F\";
4538 [(set_attr "length" "10")]
4542 ;;- Jump to subroutine.
4544 ;; For the C/370 environment the internal functions, ie. sqrt, are called with
4545 ;; a non-standard form. So, we must fix it here. There's no BM like IBM.
4547 ;; The ELF ABI is different from the C/370 ABI because we have a simpler,
4548 ;; more powerful way of dealing with structure-value returns. Basically,
4549 ;; we use R1 to point at structure returns (64-bit and larger returns)
4550 ;; and R11 to point at the args. Note that this handles double-precision
4551 ;; (64-bit) values just fine, in a less-kludged manner than the C/370 ABI.
4552 ;; Since R1 is used, we use R2 to pass the argument pointer to the routine.
4555 ; call instruction pattern(s).
4557 ; We define four call instruction patterns below. The first two patterns,
4558 ; although general, end up matching (only?) calls through function pointers.
4559 ; The last two, which require a symbol-ref to match, get used for all
4560 ; ordinary subroutine calls.
4563 [(call (match_operand:QI 0 "memory_operand" "m")
4564 (match_operand:SI 1 "immediate_operand" "i"))
4565 (clobber (reg:SI 2))
4570 static char temp[128];
4571 int i = STACK_POINTER_OFFSET;
4574 check_label_emit ();
4575 #ifdef TARGET_ELF_ABI
4576 mvs_check_page (0, 10, 4);
4577 sprintf ( temp, \"LA r2,%d(,sp)\;LA 15,%%0\;BASR 14,15\", i );
4580 if (mvs_function_check (XSTR (operands[0], 0)))
4582 mvs_check_page (0, 22, 4);
4583 sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;LA 15,%%0\;BALR 14,15\;LD 0,136(,13)\",
4588 mvs_check_page (0, 10, 4);
4589 sprintf ( temp, \"LA 1,%d(,13)\;LA 15,%%0\;BALR 14,15\", i );
4594 [(set_attr "length" "22")]
4598 ; call_value instruction pattern(s).
4601 (define_insn "call_value"
4602 [(set (match_operand 0 "" "=rf")
4603 (call (match_operand:QI 1 "memory_operand" "m")
4604 (match_operand:SI 2 "general_operand" "i")))
4605 (clobber (reg:SI 2))
4610 static char temp[128];
4611 int i = STACK_POINTER_OFFSET;
4614 check_label_emit ();
4615 #ifdef TARGET_ELF_ABI
4616 mvs_check_page (0, 10, 4);
4617 sprintf ( temp, \"LA r2,%d(,sp)\;LA 15,%%1\;BASR 14,15\", i );
4620 if (mvs_function_check (XSTR (operands[1], 0)))
4622 mvs_check_page (0, 22, 4);
4623 sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;LA 15,%%1\;BALR 14,15\;LD 0,136(,13)\",
4628 mvs_check_page (0, 10, 4);
4629 sprintf ( temp, \"LA 1,%d(,13)\;LA 15,%%1\;BALR 14,15\", i );
4634 [(set_attr "length" "22")]
4638 [(call (mem:QI (match_operand:SI 0 "" "i"))
4639 (match_operand:SI 1 "general_operand" "g"))
4640 (clobber (reg:SI 2))
4642 "GET_CODE (operands[0]) == SYMBOL_REF"
4645 static char temp[128];
4646 int i = STACK_POINTER_OFFSET;
4649 check_label_emit ();
4650 #ifdef TARGET_ELF_ABI
4651 mvs_check_page (0, 10, 4);
4652 sprintf ( temp, \"LA r2,%d(,sp)\;L 15,%%0\;BASR 14,15\", i );
4655 if (mvs_function_check (XSTR (operands[0], 0)))
4657 mvs_check_page (0, 22, 4);
4658 sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;L 15,%%0\;BALR 14,15\;LD 0,136(,13)\",
4663 mvs_check_page (0, 10, 4);
4664 sprintf ( temp, \"LA 1,%d(,13)\;L 15,%%0\;BALR 14,15\", i );
4669 [(set_attr "length" "22")]
4673 [(set (match_operand 0 "" "=rf")
4674 (call (mem:QI (match_operand:SI 1 "" "i"))
4675 (match_operand:SI 2 "general_operand" "g")))
4676 (clobber (reg:SI 2))
4678 "GET_CODE (operands[1]) == SYMBOL_REF"
4681 static char temp[128];
4682 int i = STACK_POINTER_OFFSET;
4685 check_label_emit ();
4686 #ifdef TARGET_ELF_ABI
4687 mvs_check_page (0, 10, 4);
4688 sprintf ( temp, \"LA r2,%d(,sp)\;L 15,%%1\;BASR 14,15\", i );
4691 if (mvs_function_check (XSTR (operands[1], 0)))
4693 mvs_check_page (0, 22, 4);
4694 sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;L 15,%%1\;BALR 14,15\;LD 0,136(,13)\",
4699 mvs_check_page (0, 10, 4);
4700 sprintf ( temp, \"LA 1,%d(,13)\;L 15,%%1\;BALR 14,15\", i );
4705 [(set_attr "length" "22")]
4709 ;; Call subroutine returning any type.
4710 ;; This instruction pattern appears to be used only by the
4711 ;; expand_builtin_apply definition for __builtin_apply. It is needed
4712 ;; since call_value might return an in in r15 or a float in fpr0 (r16)
4713 ;; and the builtin code calla abort since the reg is ambiguous. Well,
4714 ;; the below is probably broken anyway, we just want to go for now.
4716 (define_expand "untyped_call"
4717 [(parallel [(call (match_operand 0 "" "")
4719 (match_operand 1 "" "")
4720 (match_operand 2 "" "")])]
4726 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx, const0_rtx));
4728 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4730 rtx set = XVECEXP (operands[2], 0, i);
4731 emit_move_insn (SET_DEST (set), SET_SRC (set));
4734 /* The optimizer does not know that the call sets the function value
4735 registers we stored in the result block. We avoid problems by
4736 claiming that all hard registers are used and clobbered at this
4738 /* emit_insn (gen_blockage ()); */
4745 ;;- Miscellaneous instructions.
4749 ; nop instruction pattern(s).
4757 check_label_emit ();
4758 mvs_check_page (0, 2, 0);
4761 [(set_attr "length" "2")]