gcc/config/i386/constraints.md

   1 ;; Constraint definitions for IA-32 and x86-64.
   2 ;; Copyright (C) 2006, 2007 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 ;;; Unused letters:
  21 ;;;     B     H           T  W
  22 ;;;           h jk          vw
  23
  24 ;; Integer register constraints.
  25 ;; It is not necessary to define 'r' here.
  26 (define_register_constraint "R" "LEGACY_REGS"
  27  "Legacy register---the eight integer registers available on all
  28   i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
  29   @code{si}, @code{di}, @code{bp}, @code{sp}).")
  30
  31 (define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS"
  32  "Any register accessible as @code{@var{r}l}.  In 32-bit mode, @code{a},
  33   @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.")
  34
  35 (define_register_constraint "Q" "Q_REGS"
  36  "Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
  37   @code{c}, and @code{d}.")
  38
  39 (define_register_constraint "l" "INDEX_REGS"
  40  "@internal Any register that can be used as the index in a base+index
  41   memory access: that is, any general register except the stack pointer.")
  42
  43 (define_register_constraint "a" "AREG"
  44  "The @code{a} register.")
  45
  46 (define_register_constraint "b" "BREG"
  47  "The @code{b} register.")
  48
  49 (define_register_constraint "c" "CREG"
  50  "The @code{c} register.")
  51
  52 (define_register_constraint "d" "DREG"
  53  "The @code{d} register.")
  54
  55 (define_register_constraint "S" "SIREG"
  56  "The @code{si} register.")
  57
  58 (define_register_constraint "D" "DIREG"
  59  "The @code{di} register.")
  60
  61 (define_register_constraint "A" "AD_REGS"
  62  "The @code{a} and @code{d} registers, as a pair (for instructions
  63   that return half the result in one and half in the other).")
  64
  65 (define_register_constraint "U" "CLOBBERED_REGS"
  66  "The call-clobbered integer registers.")
  67
  68 ;; Floating-point register constraints.
  69 (define_register_constraint "f"
  70  "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FLOAT_REGS : NO_REGS"
  71  "Any 80387 floating-point (stack) register.")
  72
  73 (define_register_constraint "t"
  74  "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_TOP_REG : NO_REGS"
  75  "Top of 80387 floating-point stack (@code{%st(0)}).")
  76
  77 (define_register_constraint "u"
  78  "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS"
  79  "Second from top of 80387 floating-point stack (@code{%st(1)}).")
  80
  81 ;; Vector registers (also used for plain floating point nowadays).
  82 (define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS"
  83  "Any MMX register.")
  84
  85 (define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS"
  86  "Any SSE register.")
  87
  88 ;; We use the Y prefix to denote any number of conditional register sets:
  89 ;;  z   First SSE register.
  90 ;;  2   SSE2 enabled
  91 ;;  i   SSE2 inter-unit moves enabled
  92 ;;  m   MMX inter-unit moves enabled
  93 ;;  d   Integer register when integer DFmode moves are enabled
  94 ;;  x   Integer register when integer XFmode moves are enabled
  95
  96 (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
  97  "First SSE register (@code{%xmm0}).")
  98
  99 (define_register_constraint "Y2" "TARGET_SSE2 ? SSE_REGS : NO_REGS"
 100  "@internal Any SSE register, when SSE2 is enabled.")
 101
 102 (define_register_constraint "Yi"
 103  "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES ? SSE_REGS : NO_REGS"
 104  "@internal Any SSE register, when SSE2 and inter-unit moves are enabled.")
 105
 106 (define_register_constraint "Ym"
 107  "TARGET_MMX && TARGET_INTER_UNIT_MOVES ? MMX_REGS : NO_REGS"
 108  "@internal Any MMX register, when inter-unit moves are enabled.")
 109
 110 (define_register_constraint "Yd"
 111  "TARGET_INTEGER_DFMODE_MOVES ? GENERAL_REGS : NO_REGS"
 112  "@internal Any integer register when integer DFmode moves are enabled.")
 113
 114 (define_register_constraint "Yx"
 115  "optimize_function_for_speed_p (cfun) ? GENERAL_REGS : NO_REGS"
 116  "@internal Any integer register when integer XFmode moves are enabled.")
 117
 118 (define_constraint "z"
 119   "@internal Constant call address operand."
 120   (match_operand 0 "constant_call_address_operand"))
 121
 122 ;; Integer constant constraints.
 123 (define_constraint "I"
 124   "Integer constant in the range 0 @dots{} 31, for 32-bit shifts."
 125   (and (match_code "const_int")
 126        (match_test "IN_RANGE (ival, 0, 31)")))
 127
 128 (define_constraint "J"
 129   "Integer constant in the range 0 @dots{} 63, for 64-bit shifts."
 130   (and (match_code "const_int")
 131        (match_test "IN_RANGE (ival, 0, 63)")))
 132
 133 (define_constraint "K"
 134   "Signed 8-bit integer constant."
 135   (and (match_code "const_int")
 136        (match_test "IN_RANGE (ival, -128, 127)")))
 137
 138 (define_constraint "L"
 139   "@code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move."
 140   (and (match_code "const_int")
 141        (match_test "ival == 0xFF || ival == 0xFFFF")))
 142
 143 (define_constraint "M"
 144   "0, 1, 2, or 3 (shifts for the @code{lea} instruction)."
 145   (and (match_code "const_int")
 146        (match_test "IN_RANGE (ival, 0, 3)")))
 147
 148 (define_constraint "N"
 149   "Unsigned 8-bit integer constant (for @code{in} and @code{out}
 150    instructions)."
 151   (and (match_code "const_int")
 152        (match_test "IN_RANGE (ival, 0, 255)")))
 153
 154 (define_constraint "O"
 155   "@internal Integer constant in the range 0 @dots{} 127, for 128-bit shifts."
 156   (and (match_code "const_int")
 157        (match_test "IN_RANGE (ival, 0, 127)")))
 158
 159 ;; Floating-point constant constraints.
 160 ;; We allow constants even if TARGET_80387 isn't set, because the
 161 ;; stack register converter may need to load 0.0 into the function
 162 ;; value register (top of stack).
 163 (define_constraint "G"
 164   "Standard 80387 floating point constant."
 165   (and (match_code "const_double")
 166        (match_test "standard_80387_constant_p (op) > 0")))
 167
 168 ;; This can theoretically be any mode's CONST0_RTX.
 169 (define_constraint "C"
 170   "Standard SSE floating point constant."
 171   (match_test "standard_sse_constant_p (op)"))
 172
 173 ;; Constant-or-symbol-reference constraints.
 174
 175 (define_constraint "e"
 176   "32-bit signed integer constant, or a symbolic reference known
 177    to fit that range (for immediate operands in sign-extending x86-64
 178    instructions)."
 179   (match_operand 0 "x86_64_immediate_operand"))
 180
 181 (define_constraint "Z"
 182   "32-bit unsigned integer constant, or a symbolic reference known
 183    to fit that range (for immediate operands in zero-extending x86-64
 184    instructions)."
 185   (match_operand 0 "x86_64_zext_immediate_operand"))