gcc/config/i386/constraints.md

   1 ;; Constraint definitions for IA-32 and x86-64.
   2 ;; Copyright (C) 2006-2016 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 ;;; Unused letters:
  21 ;;;           H
  22 ;;;           h j               z
  23
  24 ;; Integer register constraints.
  25 ;; It is not necessary to define 'r' here.
  26 (define_register_constraint "R" "LEGACY_REGS"
  27  "Legacy register---the eight integer registers available on all
  28   i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
  29   @code{si}, @code{di}, @code{bp}, @code{sp}).")
  30
  31 (define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS"
  32  "Any register accessible as @code{@var{r}l}.  In 32-bit mode, @code{a},
  33   @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.")
  34
  35 (define_register_constraint "Q" "Q_REGS"
  36  "Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
  37   @code{c}, and @code{d}.")
  38
  39 (define_register_constraint "l" "INDEX_REGS"
  40  "@internal Any register that can be used as the index in a base+index
  41   memory access: that is, any general register except the stack pointer.")
  42
  43 (define_register_constraint "a" "AREG"
  44  "The @code{a} register.")
  45
  46 (define_register_constraint "b" "BREG"
  47  "The @code{b} register.")
  48
  49 (define_register_constraint "c" "CREG"
  50  "The @code{c} register.")
  51
  52 (define_register_constraint "d" "DREG"
  53  "The @code{d} register.")
  54
  55 (define_register_constraint "S" "SIREG"
  56  "The @code{si} register.")
  57
  58 (define_register_constraint "D" "DIREG"
  59  "The @code{di} register.")
  60
  61 (define_register_constraint "A" "AD_REGS"
  62  "The @code{a} and @code{d} registers, as a pair (for instructions
  63   that return half the result in one and half in the other).")
  64
  65 (define_register_constraint "U" "CLOBBERED_REGS"
  66  "The call-clobbered integer registers.")
  67
  68 ;; Floating-point register constraints.
  69 (define_register_constraint "f"
  70  "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FLOAT_REGS : NO_REGS"
  71  "Any 80387 floating-point (stack) register.")
  72
  73 (define_register_constraint "t"
  74  "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_TOP_REG : NO_REGS"
  75  "Top of 80387 floating-point stack (@code{%st(0)}).")
  76
  77 (define_register_constraint "u"
  78  "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS"
  79  "Second from top of 80387 floating-point stack (@code{%st(1)}).")
  80
  81 (define_register_constraint "Yk" "TARGET_AVX512F ? MASK_EVEX_REGS : NO_REGS"
  82 "@internal Any mask register that can be used as predicate, i.e. k1-k7.")
  83
  84 (define_register_constraint "k" "TARGET_AVX512F ? MASK_REGS : NO_REGS"
  85 "@internal Any mask register.")
  86
  87 ;; Vector registers (also used for plain floating point nowadays).
  88 (define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS"
  89  "Any MMX register.")
  90
  91 (define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS"
  92  "Any SSE register.")
  93
  94 (define_register_constraint "v" "TARGET_SSE ? ALL_SSE_REGS : NO_REGS"
  95  "Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).")
  96
  97 (define_register_constraint "w" "TARGET_MPX ? BND_REGS : NO_REGS"
  98  "@internal Any bound register.")
  99
 100 ;; We use the Y prefix to denote any number of conditional register sets:
 101 ;;  z   First SSE register.
 102 ;;  i   SSE2 inter-unit moves to SSE register enabled
 103 ;;  j   SSE2 inter-unit moves from SSE register enabled
 104 ;;  m   MMX inter-unit moves to MMX register enabled
 105 ;;  n   MMX inter-unit moves from MMX register enabled
 106 ;;  a   Integer register when zero extensions with AND are disabled
 107 ;;  b   Any register that can be used as the GOT base when calling
 108 ;;      ___tls_get_addr: that is, any general register except EAX
 109 ;;      and ESP, for -fno-plt if linker supports it.  Otherwise,
 110 ;;      EBX.
 111 ;;  p   Integer register when TARGET_PARTIAL_REG_STALL is disabled
 112 ;;  f   x87 register when 80387 floating point arithmetic is enabled
 113 ;;  r   SSE regs not requiring REX prefix when prefixes avoidance is enabled
 114 ;;      and all SSE regs otherwise
 115
 116 (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
 117  "First SSE register (@code{%xmm0}).")
 118
 119 (define_register_constraint "Yi"
 120  "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC ? ALL_SSE_REGS : NO_REGS"
 121  "@internal Any SSE register, when SSE2 and inter-unit moves to vector registers are enabled.")
 122
 123 (define_register_constraint "Yj"
 124  "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_FROM_VEC ? ALL_SSE_REGS : NO_REGS"
 125  "@internal Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled.")
 126
 127 (define_register_constraint "Ym"
 128  "TARGET_MMX && TARGET_INTER_UNIT_MOVES_TO_VEC ? MMX_REGS : NO_REGS"
 129  "@internal Any MMX register, when inter-unit moves to vector registers are enabled.")
 130
 131 (define_register_constraint "Yn"
 132  "TARGET_MMX && TARGET_INTER_UNIT_MOVES_FROM_VEC ? MMX_REGS : NO_REGS"
 133  "@internal Any MMX register, when inter-unit moves from vector registers are enabled.")
 134
 135 (define_register_constraint "Yp"
 136  "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS"
 137  "@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.")
 138
 139 (define_register_constraint "Ya"
 140  "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)
 141   ? NO_REGS : GENERAL_REGS"
 142  "@internal Any integer register when zero extensions with AND are disabled.")
 143
 144 (define_register_constraint "Yb"
 145  "(!flag_plt && HAVE_AS_IX86_TLS_GET_ADDR_GOT) ? TLS_GOTBASE_REGS : BREG"
 146  "@internal Any register that can be used as the GOT base when calling
 147   ___tls_get_addr: that is, any general register except @code{a} and
 148   @code{sp} registers, for -fno-plt if linker supports it.  Otherwise,
 149   @code{b} register.")
 150
 151 (define_register_constraint "Yf"
 152  "(ix86_fpmath & FPMATH_387) ? FLOAT_REGS : NO_REGS"
 153  "@internal Any x87 register when 80387 FP arithmetic is enabled.")
 154
 155 (define_register_constraint "Yr"
 156  "TARGET_SSE ? (TARGET_AVOID_4BYTE_PREFIXES ? NO_REX_SSE_REGS : ALL_SSE_REGS) : NO_REGS"
 157  "@internal Lower SSE register when avoiding REX prefix and all SSE registers otherwise.")
 158
 159 (define_register_constraint "Yv"
 160  "TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS"
 161  "@internal For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), otherwise any SSE register.")
 162
 163 ;; We use the B prefix to denote any number of internal operands:
 164 ;;  f  FLAGS_REG
 165 ;;  g  GOT memory operand.
 166 ;;  m  Vector memory operand
 167 ;;  s  Sibcall memory operand, not valid for TARGET_X32
 168 ;;  w  Call memory operand, not valid for TARGET_X32
 169 ;;  z  Constant call address operand.
 170 ;;  C  SSE constant operand.
 171
 172 (define_constraint "Bf"
 173   "@internal Flags register operand."
 174   (match_operand 0 "flags_reg_operand"))
 175
 176 (define_constraint "Bg"
 177   "@internal GOT memory operand."
 178   (match_operand 0 "GOT_memory_operand"))
 179
 180 (define_special_memory_constraint "Bm"
 181   "@internal Vector memory operand."
 182   (match_operand 0 "vector_memory_operand"))
 183
 184 (define_constraint "Bs"
 185   "@internal Sibcall memory operand."
 186   (ior (and (not (match_test "TARGET_X32"))
 187             (match_operand 0 "sibcall_memory_operand"))
 188        (and (match_test "TARGET_X32 && Pmode == DImode")
 189             (match_operand 0 "GOT_memory_operand"))))
 190
 191 (define_constraint "Bw"
 192   "@internal Call memory operand."
 193   (ior (and (not (match_test "TARGET_X32"))
 194             (match_operand 0 "memory_operand"))
 195        (and (match_test "TARGET_X32 && Pmode == DImode")
 196             (match_operand 0 "GOT_memory_operand"))))
 197
 198 (define_constraint "Bz"
 199   "@internal Constant call address operand."
 200   (match_operand 0 "constant_call_address_operand"))
 201
 202 (define_constraint "BC"
 203   "@internal SSE constant -1 operand."
 204   (and (match_test "TARGET_SSE")
 205        (ior (match_test "op == constm1_rtx")
 206             (match_operand 0 "vector_all_ones_operand"))))
 207
 208 ;; Integer constant constraints.
 209 (define_constraint "I"
 210   "Integer constant in the range 0 @dots{} 31, for 32-bit shifts."
 211   (and (match_code "const_int")
 212        (match_test "IN_RANGE (ival, 0, 31)")))
 213
 214 (define_constraint "J"
 215   "Integer constant in the range 0 @dots{} 63, for 64-bit shifts."
 216   (and (match_code "const_int")
 217        (match_test "IN_RANGE (ival, 0, 63)")))
 218
 219 (define_constraint "K"
 220   "Signed 8-bit integer constant."
 221   (and (match_code "const_int")
 222        (match_test "IN_RANGE (ival, -128, 127)")))
 223
 224 (define_constraint "L"
 225   "@code{0xFF}, @code{0xFFFF} or @code{0xFFFFFFFF}
 226    for AND as a zero-extending move."
 227   (and (match_code "const_int")
 228        (match_test "ival == 0xff || ival == 0xffff
 229                     || ival == (HOST_WIDE_INT) 0xffffffff")))
 230
 231 (define_constraint "M"
 232   "0, 1, 2, or 3 (shifts for the @code{lea} instruction)."
 233   (and (match_code "const_int")
 234        (match_test "IN_RANGE (ival, 0, 3)")))
 235
 236 (define_constraint "N"
 237   "Unsigned 8-bit integer constant (for @code{in} and @code{out}
 238    instructions)."
 239   (and (match_code "const_int")
 240        (match_test "IN_RANGE (ival, 0, 255)")))
 241
 242 (define_constraint "O"
 243   "@internal Integer constant in the range 0 @dots{} 127, for 128-bit shifts."
 244   (and (match_code "const_int")
 245        (match_test "IN_RANGE (ival, 0, 127)")))
 246
 247 ;; Floating-point constant constraints.
 248 ;; We allow constants even if TARGET_80387 isn't set, because the
 249 ;; stack register converter may need to load 0.0 into the function
 250 ;; value register (top of stack).
 251 (define_constraint "G"
 252   "Standard 80387 floating point constant."
 253   (and (match_code "const_double")
 254        (match_test "standard_80387_constant_p (op) > 0")))
 255
 256 ;; This can theoretically be any mode's CONST0_RTX.
 257 (define_constraint "C"
 258   "SSE constant zero operand."
 259   (and (match_test "TARGET_SSE")
 260        (ior (match_test "op == const0_rtx")
 261             (match_operand 0 "const0_operand"))))
 262
 263 ;; Constant-or-symbol-reference constraints.
 264
 265 (define_constraint "e"
 266   "32-bit signed integer constant, or a symbolic reference known
 267    to fit that range (for immediate operands in sign-extending x86-64
 268    instructions)."
 269   (match_operand 0 "x86_64_immediate_operand"))
 270
 271 ;; We use W prefix to denote any number of
 272 ;; constant-or-symbol-reference constraints
 273
 274 (define_constraint "We"
 275   "32-bit signed integer constant, or a symbolic reference known
 276    to fit that range (for sign-extending conversion operations that
 277    require non-VOIDmode immediate operands)."
 278   (and (match_operand 0 "x86_64_immediate_operand")
 279        (match_test "GET_MODE (op) != VOIDmode")))
 280
 281 (define_constraint "Wz"
 282   "32-bit unsigned integer constant, or a symbolic reference known
 283    to fit that range (for zero-extending conversion operations that
 284    require non-VOIDmode immediate operands)."
 285   (and (match_operand 0 "x86_64_zext_immediate_operand")
 286        (match_test "GET_MODE (op) != VOIDmode")))
 287
 288 (define_constraint "Wd"
 289   "128-bit integer constant where both the high and low 64-bit word
 290    of it satisfies the e constraint."
 291   (match_operand 0 "x86_64_hilo_int_operand"))
 292
 293 (define_constraint "Z"
 294   "32-bit unsigned integer constant, or a symbolic reference known
 295    to fit that range (for immediate operands in zero-extending x86-64
 296    instructions)."
 297   (match_operand 0 "x86_64_zext_immediate_operand"))
 298
 299 ;; T prefix is used for different address constraints
 300 ;;   v - VSIB address
 301 ;;   s - address with no segment register
 302 ;;   i - address with no index and no rip
 303 ;;   b - address with no base and no rip
 304
 305 (define_address_constraint "Tv"
 306   "VSIB address operand"
 307   (match_operand 0 "vsib_address_operand"))
 308
 309 (define_address_constraint "Ts"
 310   "Address operand without segment register"
 311   (match_operand 0 "address_no_seg_operand"))
 312
 313 (define_address_constraint "Ti"
 314   "MPX address operand without index"
 315   (match_operand 0 "address_mpx_no_index_operand"))
 316
 317 (define_address_constraint "Tb"
 318   "MPX address operand without base"
 319   (match_operand 0 "address_mpx_no_base_operand"))