gcc/config/i386/driver-i386.c

   1 /* Subroutines for the gcc driver.
   2    Copyright (C) 2006, 2007, 2008, 2010 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3, or (at your option)
   9 any later version.
  10
  11 GCC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 #include "config.h"
  21 #include "system.h"
  22 #include "coretypes.h"
  23 #include "tm.h"
  24
  25 const char *host_detect_local_cpu (int argc, const char **argv);
  26
  27 #ifdef __GNUC__
  28 #include "cpuid.h"
  29
  30 struct cache_desc
  31 {
  32   unsigned sizekb;
  33   unsigned assoc;
  34   unsigned line;
  35 };
  36
  37 /* Returns command line parameters that describe size and
  38    cache line size of the processor caches.  */
  39
  40 static char *
  41 describe_cache (struct cache_desc level1, struct cache_desc level2)
  42 {
  43   char size[100], line[100], size2[100];
  44
  45   /* At the moment, gcc does not use the information
  46      about the associativity of the cache.  */
  47
  48   snprintf (size, sizeof (size),
  49             "--param l1-cache-size=%u ", level1.sizekb);
  50   snprintf (line, sizeof (line),
  51             "--param l1-cache-line-size=%u ", level1.line);
  52
  53   snprintf (size2, sizeof (size2),
  54             "--param l2-cache-size=%u ", level2.sizekb);
  55
  56   return concat (size, line, size2, NULL);
  57 }
  58
  59 /* Detect L2 cache parameters using CPUID extended function 0x80000006.  */
  60
  61 static void
  62 detect_l2_cache (struct cache_desc *level2)
  63 {
  64   unsigned eax, ebx, ecx, edx;
  65   unsigned assoc;
  66
  67   __cpuid (0x80000006, eax, ebx, ecx, edx);
  68
  69   level2->sizekb = (ecx >> 16) & 0xffff;
  70   level2->line = ecx & 0xff;
  71
  72   assoc = (ecx >> 12) & 0xf;
  73   if (assoc == 6)
  74     assoc = 8;
  75   else if (assoc == 8)
  76     assoc = 16;
  77   else if (assoc >= 0xa && assoc <= 0xc)
  78     assoc = 32 + (assoc - 0xa) * 16;
  79   else if (assoc >= 0xd && assoc <= 0xe)
  80     assoc = 96 + (assoc - 0xd) * 32;
  81
  82   level2->assoc = assoc;
  83 }
  84
  85 /* Returns the description of caches for an AMD processor.  */
  86
  87 static const char *
  88 detect_caches_amd (unsigned max_ext_level)
  89 {
  90   unsigned eax, ebx, ecx, edx;
  91
  92   struct cache_desc level1, level2 = {0, 0, 0};
  93
  94   if (max_ext_level < 0x80000005)
  95     return "";
  96
  97   __cpuid (0x80000005, eax, ebx, ecx, edx);
  98
  99   level1.sizekb = (ecx >> 24) & 0xff;
 100   level1.assoc = (ecx >> 16) & 0xff;
 101   level1.line = ecx & 0xff;
 102
 103   if (max_ext_level >= 0x80000006)
 104     detect_l2_cache (&level2);
 105
 106   return describe_cache (level1, level2);
 107 }
 108
 109 /* Decodes the size, the associativity and the cache line size of
 110    L1/L2 caches of an Intel processor.  Values are based on
 111    "Intel Processor Identification and the CPUID Instruction"
 112    [Application Note 485], revision -032, December 2007.  */
 113
 114 static void
 115 decode_caches_intel (unsigned reg, bool xeon_mp,
 116                      struct cache_desc *level1, struct cache_desc *level2)
 117 {
 118   int i;
 119
 120   for (i = 24; i >= 0; i -= 8)
 121     switch ((reg >> i) & 0xff)
 122       {
 123       case 0x0a:
 124         level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
 125         break;
 126       case 0x0c:
 127         level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
 128         break;
 129       case 0x2c:
 130         level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
 131         break;
 132       case 0x39:
 133         level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
 134         break;
 135       case 0x3a:
 136         level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
 137         break;
 138       case 0x3b:
 139         level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
 140         break;
 141       case 0x3c:
 142         level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
 143         break;
 144       case 0x3d:
 145         level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
 146         break;
 147       case 0x3e:
 148         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 149         break;
 150       case 0x41:
 151         level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
 152         break;
 153       case 0x42:
 154         level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
 155         break;
 156       case 0x43:
 157         level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
 158         break;
 159       case 0x44:
 160         level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
 161         break;
 162       case 0x45:
 163         level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
 164         break;
 165       case 0x49:
 166         if (xeon_mp)
 167           break;
 168         level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
 169         break;
 170       case 0x4e:
 171         level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
 172         break;
 173       case 0x60:
 174         level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
 175         break;
 176       case 0x66:
 177         level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
 178         break;
 179       case 0x67:
 180         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 181         break;
 182       case 0x68:
 183         level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
 184         break;
 185       case 0x78:
 186         level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
 187         break;
 188       case 0x79:
 189         level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
 190         break;
 191       case 0x7a:
 192         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 193         break;
 194       case 0x7b:
 195         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 196         break;
 197       case 0x7c:
 198         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 199         break;
 200       case 0x7d:
 201         level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
 202         break;
 203       case 0x7f:
 204         level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
 205         break;
 206       case 0x82:
 207         level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
 208         break;
 209       case 0x83:
 210         level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
 211         break;
 212       case 0x84:
 213         level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
 214         break;
 215       case 0x85:
 216         level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
 217         break;
 218       case 0x86:
 219         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 220         break;
 221       case 0x87:
 222         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 223
 224       default:
 225         break;
 226       }
 227 }
 228
 229 /* Detect cache parameters using CPUID function 2.  */
 230
 231 static void
 232 detect_caches_cpuid2 (bool xeon_mp,
 233                       struct cache_desc *level1, struct cache_desc *level2)
 234 {
 235   unsigned regs[4];
 236   int nreps, i;
 237
 238   __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 239
 240   nreps = regs[0] & 0x0f;
 241   regs[0] &= ~0x0f;
 242
 243   while (--nreps >= 0)
 244     {
 245       for (i = 0; i < 4; i++)
 246         if (regs[i] && !((regs[i] >> 31) & 1))
 247           decode_caches_intel (regs[i], xeon_mp, level1, level2);
 248
 249       if (nreps)
 250         __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 251     }
 252 }
 253
 254 /* Detect cache parameters using CPUID function 4. This
 255    method doesn't require hardcoded tables.  */
 256
 257 enum cache_type
 258 {
 259   CACHE_END = 0,
 260   CACHE_DATA = 1,
 261   CACHE_INST = 2,
 262   CACHE_UNIFIED = 3
 263 };
 264
 265 static void
 266 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
 267                       struct cache_desc *level3)
 268 {
 269   struct cache_desc *cache;
 270
 271   unsigned eax, ebx, ecx, edx;
 272   int count;
 273
 274   for (count = 0;; count++)
 275     {
 276       __cpuid_count(4, count, eax, ebx, ecx, edx);
 277       switch (eax & 0x1f)
 278         {
 279         case CACHE_END:
 280           return;
 281         case CACHE_DATA:
 282         case CACHE_UNIFIED:
 283           {
 284             switch ((eax >> 5) & 0x07)
 285               {
 286               case 1:
 287                 cache = level1;
 288                 break;
 289               case 2:
 290                 cache = level2;
 291                 break;
 292               case 3:
 293                 cache = level3;
 294                 break;
 295               default:
 296                 cache = NULL;
 297               }
 298
 299             if (cache)
 300               {
 301                 unsigned sets = ecx + 1;
 302                 unsigned part = ((ebx >> 12) & 0x03ff) + 1;
 303
 304                 cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
 305                 cache->line = (ebx & 0x0fff) + 1;
 306
 307                 cache->sizekb = (cache->assoc * part
 308                                  * cache->line * sets) / 1024;
 309               }
 310           }
 311         default:
 312           break;
 313         }
 314     }
 315 }
 316
 317 /* Returns the description of caches for an Intel processor.  */
 318
 319 static const char *
 320 detect_caches_intel (bool xeon_mp, unsigned max_level,
 321                      unsigned max_ext_level, unsigned *l2sizekb)
 322 {
 323   struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
 324
 325   if (max_level >= 4)
 326     detect_caches_cpuid4 (&level1, &level2, &level3);
 327   else if (max_level >= 2)
 328     detect_caches_cpuid2 (xeon_mp, &level1, &level2);
 329   else
 330     return "";
 331
 332   if (level1.sizekb == 0)
 333     return "";
 334
 335   /* Let the L3 replace the L2. This assumes inclusive caches
 336      and single threaded program for now. */
 337   if (level3.sizekb)
 338     level2 = level3;
 339
 340   /* Intel CPUs are equipped with AMD style L2 cache info.  Try this
 341      method if other methods fail to provide L2 cache parameters.  */
 342   if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
 343     detect_l2_cache (&level2);
 344
 345   *l2sizekb = level2.sizekb;
 346
 347   return describe_cache (level1, level2);
 348 }
 349
 350 enum vendor_signatures
 351 {
 352   SIG_INTEL =   0x756e6547 /* Genu */,
 353   SIG_AMD =     0x68747541 /* Auth */
 354 };
 355
 356 enum processor_signatures
 357 {
 358   SIG_GEODE =   0x646f6547 /* Geod */
 359 };
 360
 361 /* This will be called by the spec parser in gcc.c when it sees
 362    a %:local_cpu_detect(args) construct.  Currently it will be called
 363    with either "arch" or "tune" as argument depending on if -march=native
 364    or -mtune=native is to be substituted.
 365
 366    It returns a string containing new command line parameters to be
 367    put at the place of the above two options, depending on what CPU
 368    this is executed.  E.g. "-march=k8" on an AMD64 machine
 369    for -march=native.
 370
 371    ARGC and ARGV are set depending on the actual arguments given
 372    in the spec.  */
 373
 374 const char *host_detect_local_cpu (int argc, const char **argv)
 375 {
 376   enum processor_type processor = PROCESSOR_I386;
 377   const char *cpu = "i386";
 378
 379   const char *cache = "";
 380   const char *options = "";
 381
 382   unsigned int eax, ebx, ecx, edx;
 383
 384   unsigned int max_level, ext_level;
 385
 386   unsigned int vendor;
 387   unsigned int model, family;
 388
 389   unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
 390   unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
 391
 392   /* Extended features */
 393   unsigned int has_lahf_lm = 0, has_sse4a = 0;
 394   unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
 395   unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
 396   unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0;
 397   unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
 398   unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
 399   unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
 400   unsigned int has_hle = 0;
 401
 402   bool arch;
 403
 404   unsigned int l2sizekb = 0;
 405
 406   if (argc < 1)
 407     return NULL;
 408
 409   arch = !strcmp (argv[0], "arch");
 410
 411   if (!arch && strcmp (argv[0], "tune"))
 412     return NULL;
 413
 414   max_level = __get_cpuid_max (0, &vendor);
 415   if (max_level < 1)
 416     goto done;
 417
 418   __cpuid (1, eax, ebx, ecx, edx);
 419
 420   model = (eax >> 4) & 0x0f;
 421   family = (eax >> 8) & 0x0f;
 422   if (vendor == SIG_INTEL)
 423     {
 424       unsigned int extended_model, extended_family;
 425
 426       extended_model = (eax >> 12) & 0xf0;
 427       extended_family = (eax >> 20) & 0xff;
 428       if (family == 0x0f)
 429         {
 430           family += extended_family;
 431           model += extended_model;
 432         }
 433       else if (family == 0x06)
 434         model += extended_model;
 435     }
 436
 437   has_sse3 = ecx & bit_SSE3;
 438   has_ssse3 = ecx & bit_SSSE3;
 439   has_sse4_1 = ecx & bit_SSE4_1;
 440   has_sse4_2 = ecx & bit_SSE4_2;
 441   has_avx = ecx & bit_AVX;
 442   has_cmpxchg16b = ecx & bit_CMPXCHG16B;
 443   has_movbe = ecx & bit_MOVBE;
 444   has_popcnt = ecx & bit_POPCNT;
 445   has_aes = ecx & bit_AES;
 446   has_pclmul = ecx & bit_PCLMUL;
 447   has_fma = ecx & bit_FMA;
 448
 449   has_cmpxchg8b = edx & bit_CMPXCHG8B;
 450   has_cmov = edx & bit_CMOV;
 451   has_mmx = edx & bit_MMX;
 452   has_sse = edx & bit_SSE;
 453   has_sse2 = edx & bit_SSE2;
 454
 455   if (max_level >= 7)
 456     {
 457       __cpuid_count (7, 0, eax, ebx, ecx, edx);
 458
 459       has_bmi = ebx & bit_BMI;
 460       has_hle = ebx & bit_HLE;
 461       has_avx2 = ebx & bit_AVX2;
 462       has_bmi2 = ebx & bit_BMI2;
 463     }
 464
 465   /* Check cpuid level of extended features.  */
 466   __cpuid (0x80000000, ext_level, ebx, ecx, edx);
 467
 468   if (ext_level > 0x80000000)
 469     {
 470       __cpuid (0x80000001, eax, ebx, ecx, edx);
 471
 472       has_lahf_lm = ecx & bit_LAHF_LM;
 473       has_sse4a = ecx & bit_SSE4a;
 474       has_abm = ecx & bit_ABM;
 475       has_lwp = ecx & bit_LWP;
 476       has_fma4 = ecx & bit_FMA4;
 477       if (vendor == SIG_AMD && has_fma4 && has_fma)
 478         has_fma4 = 0;
 479       has_xop = ecx & bit_XOP;
 480       has_tbm = ecx & bit_TBM;
 481       has_lzcnt = ecx & bit_LZCNT;
 482
 483       has_longmode = edx & bit_LM;
 484       has_3dnowp = edx & bit_3DNOWP;
 485       has_3dnow = edx & bit_3DNOW;
 486     }
 487
 488   if (!arch)
 489     {
 490       if (vendor == SIG_AMD)
 491         cache = detect_caches_amd (ext_level);
 492       else if (vendor == SIG_INTEL)
 493         {
 494           bool xeon_mp = (family == 15 && model == 6);
 495           cache = detect_caches_intel (xeon_mp, max_level,
 496                                        ext_level, &l2sizekb);
 497         }
 498     }
 499
 500   if (vendor == SIG_AMD)
 501     {
 502       unsigned int name;
 503
 504       /* Detect geode processor by its processor signature.  */
 505       if (ext_level > 0x80000001)
 506         __cpuid (0x80000002, name, ebx, ecx, edx);
 507       else
 508         name = 0;
 509
 510       if (name == SIG_GEODE)
 511         processor = PROCESSOR_GEODE;
 512       else if (has_bmi)
 513         processor = PROCESSOR_BDVER2;
 514       else if (has_xop)
 515         processor = PROCESSOR_BDVER1;
 516       else if (has_sse4a && has_ssse3)
 517         processor = PROCESSOR_BTVER1;
 518       else if (has_sse4a)
 519         processor = PROCESSOR_AMDFAM10;
 520       else if (has_sse2 || has_longmode)
 521         processor = PROCESSOR_K8;
 522       else if (has_3dnowp && family == 6)
 523         processor = PROCESSOR_ATHLON;
 524       else if (has_mmx)
 525         processor = PROCESSOR_K6;
 526       else
 527         processor = PROCESSOR_PENTIUM;
 528     }
 529   else
 530     {
 531       switch (family)
 532         {
 533         case 4:
 534           processor = PROCESSOR_I486;
 535           break;
 536         case 5:
 537           processor = PROCESSOR_PENTIUM;
 538           break;
 539         case 6:
 540           processor = PROCESSOR_PENTIUMPRO;
 541           break;
 542         case 15:
 543           processor = PROCESSOR_PENTIUM4;
 544           break;
 545         default:
 546           /* We have no idea.  */
 547           processor = PROCESSOR_GENERIC32;
 548         }
 549     }
 550
 551   switch (processor)
 552     {
 553     case PROCESSOR_I386:
 554       /* Default.  */
 555       break;
 556     case PROCESSOR_I486:
 557       cpu = "i486";
 558       break;
 559     case PROCESSOR_PENTIUM:
 560       if (arch && has_mmx)
 561         cpu = "pentium-mmx";
 562       else
 563         cpu = "pentium";
 564       break;
 565     case PROCESSOR_PENTIUMPRO:
 566       switch (model)
 567         {
 568         case 0x1c:
 569         case 0x26:
 570           /* Atom.  */
 571           cpu = "atom";
 572           break;
 573         case 0x1a:
 574         case 0x1e:
 575         case 0x1f:
 576         case 0x2e:
 577           /* Nehalem.  */
 578           cpu = "corei7";
 579           break;
 580         case 0x25:
 581         case 0x2c:
 582         case 0x2f:
 583           /* Westmere.  */
 584           cpu = "corei7";
 585           break;
 586         case 0x2a:
 587         case 0x2d:
 588           /* Sandy Bridge.  */
 589           cpu = "corei7-avx";
 590           break;
 591         case 0x17:
 592         case 0x1d:
 593           /* Penryn.  */
 594           cpu = "core2";
 595           break;
 596         case 0x0f:
 597           /* Merom.  */
 598           cpu = "core2";
 599           break;
 600         default:
 601           if (arch)
 602             {
 603               /* This is unknown family 0x6 CPU.  */
 604               if (has_avx)
 605                 /* Assume Sandy Bridge.  */
 606                 cpu = "corei7-avx";
 607               else if (has_sse4_2)
 608                 /* Assume Core i7.  */
 609                 cpu = "corei7";
 610               else if (has_ssse3)
 611                 {
 612                   if (has_movbe)
 613                     /* Assume Atom.  */
 614                     cpu = "atom";
 615                   else
 616                     /* Assume Core 2.  */
 617                     cpu = "core2";
 618                 }
 619               else if (has_sse3)
 620                 /* It is Core Duo.  */
 621                 cpu = "pentium-m";
 622               else if (has_sse2)
 623                 /* It is Pentium M.  */
 624                 cpu = "pentium-m";
 625               else if (has_sse)
 626                 /* It is Pentium III.  */
 627                 cpu = "pentium3";
 628               else if (has_mmx)
 629                 /* It is Pentium II.  */
 630                 cpu = "pentium2";
 631               else
 632                 /* Default to Pentium Pro.  */
 633                 cpu = "pentiumpro";
 634             }
 635           else
 636             /* For -mtune, we default to -mtune=generic.  */
 637             cpu = "generic";
 638           break;
 639         }
 640       break;
 641     case PROCESSOR_PENTIUM4:
 642       if (has_sse3)
 643         {
 644           if (has_longmode)
 645             cpu = "nocona";
 646           else
 647             cpu = "prescott";
 648         }
 649       else
 650         cpu = "pentium4";
 651       break;
 652     case PROCESSOR_GEODE:
 653       cpu = "geode";
 654       break;
 655     case PROCESSOR_K6:
 656       if (arch && has_3dnow)
 657         cpu = "k6-3";
 658       else
 659         cpu = "k6";
 660       break;
 661     case PROCESSOR_ATHLON:
 662       if (arch && has_sse)
 663         cpu = "athlon-4";
 664       else
 665         cpu = "athlon";
 666       break;
 667     case PROCESSOR_K8:
 668       if (arch && has_sse3)
 669         cpu = "k8-sse3";
 670       else
 671         cpu = "k8";
 672       break;
 673     case PROCESSOR_AMDFAM10:
 674       cpu = "amdfam10";
 675       break;
 676     case PROCESSOR_BDVER1:
 677       cpu = "bdver1";
 678       break;
 679     case PROCESSOR_BDVER2:
 680       cpu = "bdver2";
 681       break;
 682     case PROCESSOR_BTVER1:
 683       cpu = "btver1";
 684       break;
 685
 686     default:
 687       /* Use something reasonable.  */
 688       if (arch)
 689         {
 690           if (has_ssse3)
 691             cpu = "core2";
 692           else if (has_sse3)
 693             {
 694               if (has_longmode)
 695                 cpu = "nocona";
 696               else
 697                 cpu = "prescott";
 698             }
 699           else if (has_sse2)
 700             cpu = "pentium4";
 701           else if (has_cmov)
 702             cpu = "pentiumpro";
 703           else if (has_mmx)
 704             cpu = "pentium-mmx";
 705           else if (has_cmpxchg8b)
 706             cpu = "pentium";
 707         }
 708       else
 709         cpu = "generic";
 710     }
 711
 712   if (arch)
 713     {
 714       const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16";
 715       const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf";
 716       const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe";
 717       const char *ase = has_aes ? " -maes" : " -mno-aes";
 718       const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul";
 719       const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt";
 720       const char *abm = has_abm ? " -mabm" : " -mno-abm";
 721       const char *lwp = has_lwp ? " -mlwp" : " -mno-lwp";
 722       const char *fma = has_fma ? " -mfma" : " -mno-fma";
 723       const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4";
 724       const char *xop = has_xop ? " -mxop" : " -mno-xop";
 725       const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi";
 726       const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2";
 727       const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm";
 728       const char *avx = has_avx ? " -mavx" : " -mno-avx";
 729       const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2";
 730       const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
 731       const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
 732       const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt";
 733       const char *hle = has_hle ? " -mhle" : " -mno-hle";
 734
 735       options = concat (options, cx16, sahf, movbe, ase, pclmul,
 736                         popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
 737                         tbm, avx, avx2, sse4_2, sse4_1, lzcnt,
 738                         hle, NULL);
 739     }
 740
 741 done:
 742   return concat (cache, "-m", argv[0], "=", cpu, options, NULL);
 743 }
 744 #else
 745
 746 /* If we aren't compiling with GCC then the driver will just ignore
 747    -march and -mtune "native" target and will leave to the newly
 748    built compiler to generate code for its default target.  */
 749
 750 const char *host_detect_local_cpu (int argc ATTRIBUTE_UNUSED,
 751                                    const char **argv ATTRIBUTE_UNUSED)
 752 {
 753   return NULL;
 754 }
 755 #endif /* __GNUC__ */