1 /* Subroutines for the gcc driver.
2 Copyright (C) 2006, 2007, 2008, 2010 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
25 const char *host_detect_local_cpu (int argc
, const char **argv
);
37 /* Returns command line parameters that describe size and
38 cache line size of the processor caches. */
41 describe_cache (struct cache_desc level1
, struct cache_desc level2
)
43 char size
[100], line
[100], size2
[100];
45 /* At the moment, gcc does not use the information
46 about the associativity of the cache. */
48 snprintf (size
, sizeof (size
),
49 "--param l1-cache-size=%u ", level1
.sizekb
);
50 snprintf (line
, sizeof (line
),
51 "--param l1-cache-line-size=%u ", level1
.line
);
53 snprintf (size2
, sizeof (size2
),
54 "--param l2-cache-size=%u ", level2
.sizekb
);
56 return concat (size
, line
, size2
, NULL
);
59 /* Detect L2 cache parameters using CPUID extended function 0x80000006. */
62 detect_l2_cache (struct cache_desc
*level2
)
64 unsigned eax
, ebx
, ecx
, edx
;
67 __cpuid (0x80000006, eax
, ebx
, ecx
, edx
);
69 level2
->sizekb
= (ecx
>> 16) & 0xffff;
70 level2
->line
= ecx
& 0xff;
72 assoc
= (ecx
>> 12) & 0xf;
77 else if (assoc
>= 0xa && assoc
<= 0xc)
78 assoc
= 32 + (assoc
- 0xa) * 16;
79 else if (assoc
>= 0xd && assoc
<= 0xe)
80 assoc
= 96 + (assoc
- 0xd) * 32;
82 level2
->assoc
= assoc
;
85 /* Returns the description of caches for an AMD processor. */
88 detect_caches_amd (unsigned max_ext_level
)
90 unsigned eax
, ebx
, ecx
, edx
;
92 struct cache_desc level1
, level2
= {0, 0, 0};
94 if (max_ext_level
< 0x80000005)
97 __cpuid (0x80000005, eax
, ebx
, ecx
, edx
);
99 level1
.sizekb
= (ecx
>> 24) & 0xff;
100 level1
.assoc
= (ecx
>> 16) & 0xff;
101 level1
.line
= ecx
& 0xff;
103 if (max_ext_level
>= 0x80000006)
104 detect_l2_cache (&level2
);
106 return describe_cache (level1
, level2
);
109 /* Decodes the size, the associativity and the cache line size of
110 L1/L2 caches of an Intel processor. Values are based on
111 "Intel Processor Identification and the CPUID Instruction"
112 [Application Note 485], revision -032, December 2007. */
115 decode_caches_intel (unsigned reg
, bool xeon_mp
,
116 struct cache_desc
*level1
, struct cache_desc
*level2
)
120 for (i
= 24; i
>= 0; i
-= 8)
121 switch ((reg
>> i
) & 0xff)
124 level1
->sizekb
= 8; level1
->assoc
= 2; level1
->line
= 32;
127 level1
->sizekb
= 16; level1
->assoc
= 4; level1
->line
= 32;
130 level1
->sizekb
= 32; level1
->assoc
= 8; level1
->line
= 64;
133 level2
->sizekb
= 128; level2
->assoc
= 4; level2
->line
= 64;
136 level2
->sizekb
= 192; level2
->assoc
= 6; level2
->line
= 64;
139 level2
->sizekb
= 128; level2
->assoc
= 2; level2
->line
= 64;
142 level2
->sizekb
= 256; level2
->assoc
= 4; level2
->line
= 64;
145 level2
->sizekb
= 384; level2
->assoc
= 6; level2
->line
= 64;
148 level2
->sizekb
= 512; level2
->assoc
= 4; level2
->line
= 64;
151 level2
->sizekb
= 128; level2
->assoc
= 4; level2
->line
= 32;
154 level2
->sizekb
= 256; level2
->assoc
= 4; level2
->line
= 32;
157 level2
->sizekb
= 512; level2
->assoc
= 4; level2
->line
= 32;
160 level2
->sizekb
= 1024; level2
->assoc
= 4; level2
->line
= 32;
163 level2
->sizekb
= 2048; level2
->assoc
= 4; level2
->line
= 32;
168 level2
->sizekb
= 4096; level2
->assoc
= 16; level2
->line
= 64;
171 level2
->sizekb
= 6144; level2
->assoc
= 24; level2
->line
= 64;
174 level1
->sizekb
= 16; level1
->assoc
= 8; level1
->line
= 64;
177 level1
->sizekb
= 8; level1
->assoc
= 4; level1
->line
= 64;
180 level1
->sizekb
= 16; level1
->assoc
= 4; level1
->line
= 64;
183 level1
->sizekb
= 32; level1
->assoc
= 4; level1
->line
= 64;
186 level2
->sizekb
= 1024; level2
->assoc
= 4; level2
->line
= 64;
189 level2
->sizekb
= 128; level2
->assoc
= 8; level2
->line
= 64;
192 level2
->sizekb
= 256; level2
->assoc
= 8; level2
->line
= 64;
195 level2
->sizekb
= 512; level2
->assoc
= 8; level2
->line
= 64;
198 level2
->sizekb
= 1024; level2
->assoc
= 8; level2
->line
= 64;
201 level2
->sizekb
= 2048; level2
->assoc
= 8; level2
->line
= 64;
204 level2
->sizekb
= 512; level2
->assoc
= 2; level2
->line
= 64;
207 level2
->sizekb
= 256; level2
->assoc
= 8; level2
->line
= 32;
210 level2
->sizekb
= 512; level2
->assoc
= 8; level2
->line
= 32;
213 level2
->sizekb
= 1024; level2
->assoc
= 8; level2
->line
= 32;
216 level2
->sizekb
= 2048; level2
->assoc
= 8; level2
->line
= 32;
219 level2
->sizekb
= 512; level2
->assoc
= 4; level2
->line
= 64;
222 level2
->sizekb
= 1024; level2
->assoc
= 8; level2
->line
= 64;
229 /* Detect cache parameters using CPUID function 2. */
232 detect_caches_cpuid2 (bool xeon_mp
,
233 struct cache_desc
*level1
, struct cache_desc
*level2
)
238 __cpuid (2, regs
[0], regs
[1], regs
[2], regs
[3]);
240 nreps
= regs
[0] & 0x0f;
245 for (i
= 0; i
< 4; i
++)
246 if (regs
[i
] && !((regs
[i
] >> 31) & 1))
247 decode_caches_intel (regs
[i
], xeon_mp
, level1
, level2
);
250 __cpuid (2, regs
[0], regs
[1], regs
[2], regs
[3]);
254 /* Detect cache parameters using CPUID function 4. This
255 method doesn't require hardcoded tables. */
266 detect_caches_cpuid4 (struct cache_desc
*level1
, struct cache_desc
*level2
,
267 struct cache_desc
*level3
)
269 struct cache_desc
*cache
;
271 unsigned eax
, ebx
, ecx
, edx
;
274 for (count
= 0;; count
++)
276 __cpuid_count(4, count
, eax
, ebx
, ecx
, edx
);
284 switch ((eax
>> 5) & 0x07)
301 unsigned sets
= ecx
+ 1;
302 unsigned part
= ((ebx
>> 12) & 0x03ff) + 1;
304 cache
->assoc
= ((ebx
>> 22) & 0x03ff) + 1;
305 cache
->line
= (ebx
& 0x0fff) + 1;
307 cache
->sizekb
= (cache
->assoc
* part
308 * cache
->line
* sets
) / 1024;
317 /* Returns the description of caches for an Intel processor. */
320 detect_caches_intel (bool xeon_mp
, unsigned max_level
,
321 unsigned max_ext_level
, unsigned *l2sizekb
)
323 struct cache_desc level1
= {0, 0, 0}, level2
= {0, 0, 0}, level3
= {0, 0, 0};
326 detect_caches_cpuid4 (&level1
, &level2
, &level3
);
327 else if (max_level
>= 2)
328 detect_caches_cpuid2 (xeon_mp
, &level1
, &level2
);
332 if (level1
.sizekb
== 0)
335 /* Let the L3 replace the L2. This assumes inclusive caches
336 and single threaded program for now. */
340 /* Intel CPUs are equipped with AMD style L2 cache info. Try this
341 method if other methods fail to provide L2 cache parameters. */
342 if (level2
.sizekb
== 0 && max_ext_level
>= 0x80000006)
343 detect_l2_cache (&level2
);
345 *l2sizekb
= level2
.sizekb
;
347 return describe_cache (level1
, level2
);
350 enum vendor_signatures
352 SIG_INTEL
= 0x756e6547 /* Genu */,
353 SIG_AMD
= 0x68747541 /* Auth */
356 enum processor_signatures
358 SIG_GEODE
= 0x646f6547 /* Geod */
361 /* This will be called by the spec parser in gcc.c when it sees
362 a %:local_cpu_detect(args) construct. Currently it will be called
363 with either "arch" or "tune" as argument depending on if -march=native
364 or -mtune=native is to be substituted.
366 It returns a string containing new command line parameters to be
367 put at the place of the above two options, depending on what CPU
368 this is executed. E.g. "-march=k8" on an AMD64 machine
371 ARGC and ARGV are set depending on the actual arguments given
374 const char *host_detect_local_cpu (int argc
, const char **argv
)
376 enum processor_type processor
= PROCESSOR_I386
;
377 const char *cpu
= "i386";
379 const char *cache
= "";
380 const char *options
= "";
382 unsigned int eax
, ebx
, ecx
, edx
;
384 unsigned int max_level
, ext_level
;
387 unsigned int model
, family
;
389 unsigned int has_sse3
, has_ssse3
, has_cmpxchg16b
;
390 unsigned int has_cmpxchg8b
, has_cmov
, has_mmx
, has_sse
, has_sse2
;
392 /* Extended features */
393 unsigned int has_lahf_lm
= 0, has_sse4a
= 0;
394 unsigned int has_longmode
= 0, has_3dnowp
= 0, has_3dnow
= 0;
395 unsigned int has_movbe
= 0, has_sse4_1
= 0, has_sse4_2
= 0;
396 unsigned int has_popcnt
= 0, has_aes
= 0, has_avx
= 0, has_avx2
= 0;
397 unsigned int has_pclmul
= 0, has_abm
= 0, has_lwp
= 0;
398 unsigned int has_fma
= 0, has_fma4
= 0, has_xop
= 0;
399 unsigned int has_bmi
= 0, has_bmi2
= 0, has_tbm
= 0, has_lzcnt
= 0;
400 unsigned int has_hle
= 0, has_rtm
= 0;
404 unsigned int l2sizekb
= 0;
409 arch
= !strcmp (argv
[0], "arch");
411 if (!arch
&& strcmp (argv
[0], "tune"))
414 max_level
= __get_cpuid_max (0, &vendor
);
418 __cpuid (1, eax
, ebx
, ecx
, edx
);
420 model
= (eax
>> 4) & 0x0f;
421 family
= (eax
>> 8) & 0x0f;
422 if (vendor
== SIG_INTEL
)
424 unsigned int extended_model
, extended_family
;
426 extended_model
= (eax
>> 12) & 0xf0;
427 extended_family
= (eax
>> 20) & 0xff;
430 family
+= extended_family
;
431 model
+= extended_model
;
433 else if (family
== 0x06)
434 model
+= extended_model
;
437 has_sse3
= ecx
& bit_SSE3
;
438 has_ssse3
= ecx
& bit_SSSE3
;
439 has_sse4_1
= ecx
& bit_SSE4_1
;
440 has_sse4_2
= ecx
& bit_SSE4_2
;
441 has_avx
= ecx
& bit_AVX
;
442 has_cmpxchg16b
= ecx
& bit_CMPXCHG16B
;
443 has_movbe
= ecx
& bit_MOVBE
;
444 has_popcnt
= ecx
& bit_POPCNT
;
445 has_aes
= ecx
& bit_AES
;
446 has_pclmul
= ecx
& bit_PCLMUL
;
447 has_fma
= ecx
& bit_FMA
;
449 has_cmpxchg8b
= edx
& bit_CMPXCHG8B
;
450 has_cmov
= edx
& bit_CMOV
;
451 has_mmx
= edx
& bit_MMX
;
452 has_sse
= edx
& bit_SSE
;
453 has_sse2
= edx
& bit_SSE2
;
457 __cpuid_count (7, 0, eax
, ebx
, ecx
, edx
);
459 has_bmi
= ebx
& bit_BMI
;
460 has_hle
= ebx
& bit_HLE
;
461 has_rtm
= ebx
& bit_RTM
;
462 has_avx2
= ebx
& bit_AVX2
;
463 has_bmi2
= ebx
& bit_BMI2
;
466 /* Check cpuid level of extended features. */
467 __cpuid (0x80000000, ext_level
, ebx
, ecx
, edx
);
469 if (ext_level
> 0x80000000)
471 __cpuid (0x80000001, eax
, ebx
, ecx
, edx
);
473 has_lahf_lm
= ecx
& bit_LAHF_LM
;
474 has_sse4a
= ecx
& bit_SSE4a
;
475 has_abm
= ecx
& bit_ABM
;
476 has_lwp
= ecx
& bit_LWP
;
477 has_fma4
= ecx
& bit_FMA4
;
478 if (vendor
== SIG_AMD
&& has_fma4
&& has_fma
)
480 has_xop
= ecx
& bit_XOP
;
481 has_tbm
= ecx
& bit_TBM
;
482 has_lzcnt
= ecx
& bit_LZCNT
;
484 has_longmode
= edx
& bit_LM
;
485 has_3dnowp
= edx
& bit_3DNOWP
;
486 has_3dnow
= edx
& bit_3DNOW
;
491 if (vendor
== SIG_AMD
)
492 cache
= detect_caches_amd (ext_level
);
493 else if (vendor
== SIG_INTEL
)
495 bool xeon_mp
= (family
== 15 && model
== 6);
496 cache
= detect_caches_intel (xeon_mp
, max_level
,
497 ext_level
, &l2sizekb
);
501 if (vendor
== SIG_AMD
)
505 /* Detect geode processor by its processor signature. */
506 if (ext_level
> 0x80000001)
507 __cpuid (0x80000002, name
, ebx
, ecx
, edx
);
511 if (name
== SIG_GEODE
)
512 processor
= PROCESSOR_GEODE
;
514 processor
= PROCESSOR_BDVER2
;
516 processor
= PROCESSOR_BDVER1
;
517 else if (has_sse4a
&& has_ssse3
)
518 processor
= PROCESSOR_BTVER1
;
520 processor
= PROCESSOR_AMDFAM10
;
521 else if (has_sse2
|| has_longmode
)
522 processor
= PROCESSOR_K8
;
523 else if (has_3dnowp
&& family
== 6)
524 processor
= PROCESSOR_ATHLON
;
526 processor
= PROCESSOR_K6
;
528 processor
= PROCESSOR_PENTIUM
;
535 processor
= PROCESSOR_I486
;
538 processor
= PROCESSOR_PENTIUM
;
541 processor
= PROCESSOR_PENTIUMPRO
;
544 processor
= PROCESSOR_PENTIUM4
;
547 /* We have no idea. */
548 processor
= PROCESSOR_GENERIC32
;
560 case PROCESSOR_PENTIUM
:
566 case PROCESSOR_PENTIUMPRO
:
604 /* This is unknown family 0x6 CPU. */
606 /* Assume Sandy Bridge. */
609 /* Assume Core i7. */
621 /* It is Core Duo. */
624 /* It is Pentium M. */
627 /* It is Pentium III. */
630 /* It is Pentium II. */
633 /* Default to Pentium Pro. */
637 /* For -mtune, we default to -mtune=generic. */
642 case PROCESSOR_PENTIUM4
:
653 case PROCESSOR_GEODE
:
657 if (arch
&& has_3dnow
)
662 case PROCESSOR_ATHLON
:
669 if (arch
&& has_sse3
)
674 case PROCESSOR_AMDFAM10
:
677 case PROCESSOR_BDVER1
:
680 case PROCESSOR_BDVER2
:
683 case PROCESSOR_BTVER1
:
688 /* Use something reasonable. */
706 else if (has_cmpxchg8b
)
715 const char *cx16
= has_cmpxchg16b
? " -mcx16" : " -mno-cx16";
716 const char *sahf
= has_lahf_lm
? " -msahf" : " -mno-sahf";
717 const char *movbe
= has_movbe
? " -mmovbe" : " -mno-movbe";
718 const char *ase
= has_aes
? " -maes" : " -mno-aes";
719 const char *pclmul
= has_pclmul
? " -mpclmul" : " -mno-pclmul";
720 const char *popcnt
= has_popcnt
? " -mpopcnt" : " -mno-popcnt";
721 const char *abm
= has_abm
? " -mabm" : " -mno-abm";
722 const char *lwp
= has_lwp
? " -mlwp" : " -mno-lwp";
723 const char *fma
= has_fma
? " -mfma" : " -mno-fma";
724 const char *fma4
= has_fma4
? " -mfma4" : " -mno-fma4";
725 const char *xop
= has_xop
? " -mxop" : " -mno-xop";
726 const char *bmi
= has_bmi
? " -mbmi" : " -mno-bmi";
727 const char *bmi2
= has_bmi2
? " -mbmi2" : " -mno-bmi2";
728 const char *tbm
= has_tbm
? " -mtbm" : " -mno-tbm";
729 const char *avx
= has_avx
? " -mavx" : " -mno-avx";
730 const char *avx2
= has_avx2
? " -mavx2" : " -mno-avx2";
731 const char *sse4_2
= has_sse4_2
? " -msse4.2" : " -mno-sse4.2";
732 const char *sse4_1
= has_sse4_1
? " -msse4.1" : " -mno-sse4.1";
733 const char *lzcnt
= has_lzcnt
? " -mlzcnt" : " -mno-lzcnt";
734 const char *hle
= has_hle
? " -mhle" : " -mno-hle";
735 const char *rtm
= has_rtm
? " -mrtm" : " -mno-rtm";
737 options
= concat (options
, cx16
, sahf
, movbe
, ase
, pclmul
,
738 popcnt
, abm
, lwp
, fma
, fma4
, xop
, bmi
, bmi2
,
739 tbm
, avx
, avx2
, sse4_2
, sse4_1
, lzcnt
, rtm
,
744 return concat (cache
, "-m", argv
[0], "=", cpu
, options
, NULL
);
748 /* If we aren't compiling with GCC then the driver will just ignore
749 -march and -mtune "native" target and will leave to the newly
750 built compiler to generate code for its default target. */
752 const char *host_detect_local_cpu (int argc ATTRIBUTE_UNUSED
,
753 const char **argv ATTRIBUTE_UNUSED
)
757 #endif /* __GNUC__ */